Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.53 99.36 98.73 100.00 100.00 100.00 99.09


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T513 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2347054150 Mar 24 12:21:13 PM PDT 24 Mar 24 12:21:14 PM PDT 24 15818609 ps
T514 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1002198215 Mar 24 12:22:22 PM PDT 24 Mar 24 12:22:23 PM PDT 24 54606323 ps
T515 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3267458259 Mar 24 12:21:02 PM PDT 24 Mar 24 12:21:04 PM PDT 24 194155405 ps
T516 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2223238447 Mar 24 12:22:29 PM PDT 24 Mar 24 12:22:31 PM PDT 24 1088208692 ps
T70 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1454047089 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:13 PM PDT 24 90080513 ps
T517 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1516977489 Mar 24 12:20:58 PM PDT 24 Mar 24 12:20:59 PM PDT 24 16063548 ps
T518 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.975722627 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:07 PM PDT 24 35338225 ps
T519 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.94868549 Mar 24 12:20:58 PM PDT 24 Mar 24 12:21:00 PM PDT 24 56626618 ps
T520 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.834937595 Mar 24 12:21:26 PM PDT 24 Mar 24 12:21:30 PM PDT 24 332627937 ps
T521 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1925634382 Mar 24 12:20:59 PM PDT 24 Mar 24 12:21:00 PM PDT 24 60232930 ps
T71 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2984441891 Mar 24 12:20:50 PM PDT 24 Mar 24 12:20:51 PM PDT 24 17382565 ps
T522 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1686053619 Mar 24 12:21:30 PM PDT 24 Mar 24 12:21:31 PM PDT 24 181921613 ps
T523 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2058259974 Mar 24 12:20:46 PM PDT 24 Mar 24 12:20:47 PM PDT 24 67816628 ps
T72 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3721669090 Mar 24 12:20:30 PM PDT 24 Mar 24 12:20:31 PM PDT 24 44803806 ps
T524 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3813633919 Mar 24 12:21:41 PM PDT 24 Mar 24 12:21:42 PM PDT 24 246876590 ps
T525 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1242562657 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:09 PM PDT 24 64169822 ps
T73 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1946356791 Mar 24 12:21:02 PM PDT 24 Mar 24 12:21:02 PM PDT 24 33359615 ps
T526 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2370088336 Mar 24 12:21:10 PM PDT 24 Mar 24 12:21:12 PM PDT 24 29794244 ps
T527 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2878775393 Mar 24 12:20:50 PM PDT 24 Mar 24 12:20:51 PM PDT 24 12215219 ps
T528 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1057165774 Mar 24 12:20:37 PM PDT 24 Mar 24 12:20:38 PM PDT 24 56218608 ps
T529 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4261319264 Mar 24 12:22:50 PM PDT 24 Mar 24 12:22:52 PM PDT 24 202850293 ps
T74 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.297024110 Mar 24 12:22:11 PM PDT 24 Mar 24 12:22:12 PM PDT 24 142404477 ps
T530 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.744890913 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:06 PM PDT 24 14591054 ps
T531 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3603006925 Mar 24 12:21:23 PM PDT 24 Mar 24 12:21:24 PM PDT 24 28298216 ps
T532 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2422036417 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:07 PM PDT 24 66029962 ps
T533 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2179640440 Mar 24 12:22:11 PM PDT 24 Mar 24 12:22:12 PM PDT 24 235400044 ps
T534 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.714040198 Mar 24 12:21:36 PM PDT 24 Mar 24 12:21:38 PM PDT 24 15686739 ps
T535 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2512276 Mar 24 12:20:56 PM PDT 24 Mar 24 12:20:58 PM PDT 24 16716642 ps
T536 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2077789249 Mar 24 12:21:15 PM PDT 24 Mar 24 12:21:16 PM PDT 24 19210573 ps
T537 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3352166994 Mar 24 12:22:09 PM PDT 24 Mar 24 12:22:10 PM PDT 24 12684483 ps
T75 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2237287028 Mar 24 12:21:41 PM PDT 24 Mar 24 12:21:42 PM PDT 24 15153640 ps
T538 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1808729319 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:10 PM PDT 24 163322077 ps
T539 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3256197523 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:06 PM PDT 24 38854049 ps
T540 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3336981374 Mar 24 12:22:37 PM PDT 24 Mar 24 12:22:38 PM PDT 24 48651333 ps
T541 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2744823265 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:10 PM PDT 24 14081944 ps
T542 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3224649239 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:06 PM PDT 24 105072479 ps
T543 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3390843045 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:05 PM PDT 24 18405270 ps
T76 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3654481952 Mar 24 12:22:22 PM PDT 24 Mar 24 12:22:23 PM PDT 24 12474180 ps
T544 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2224903063 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:09 PM PDT 24 29953910 ps
T545 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2921683203 Mar 24 12:21:16 PM PDT 24 Mar 24 12:21:17 PM PDT 24 41197740 ps
T546 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4034540141 Mar 24 12:20:54 PM PDT 24 Mar 24 12:20:57 PM PDT 24 397749330 ps
T547 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.857737214 Mar 24 12:20:54 PM PDT 24 Mar 24 12:20:56 PM PDT 24 36579290 ps
T548 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.25730708 Mar 24 12:21:36 PM PDT 24 Mar 24 12:21:38 PM PDT 24 25465104 ps
T549 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2961329354 Mar 24 12:20:54 PM PDT 24 Mar 24 12:20:55 PM PDT 24 15506697 ps
T550 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3602748818 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:05 PM PDT 24 16828533 ps
T551 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3274978948 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:06 PM PDT 24 15740557 ps
T552 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.60547938 Mar 24 12:20:38 PM PDT 24 Mar 24 12:20:38 PM PDT 24 32460538 ps
T553 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2710856983 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:09 PM PDT 24 71027353 ps
T554 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3883045621 Mar 24 12:21:17 PM PDT 24 Mar 24 12:21:18 PM PDT 24 562433470 ps
T555 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2476891392 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:07 PM PDT 24 1442214871 ps
T77 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2840732900 Mar 24 12:20:52 PM PDT 24 Mar 24 12:20:52 PM PDT 24 53163406 ps
T556 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.486890987 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:05 PM PDT 24 29974972 ps
T557 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1026361809 Mar 24 12:21:20 PM PDT 24 Mar 24 12:21:22 PM PDT 24 33150622 ps
T558 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2269822757 Mar 24 12:21:26 PM PDT 24 Mar 24 12:21:28 PM PDT 24 162647625 ps
T559 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3178402377 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:09 PM PDT 24 19404694 ps
T560 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4264286069 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:06 PM PDT 24 105144731 ps
T78 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1094556766 Mar 24 12:21:26 PM PDT 24 Mar 24 12:21:27 PM PDT 24 20390138 ps
T561 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1615265666 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:09 PM PDT 24 57599060 ps
T562 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1212765363 Mar 24 12:20:50 PM PDT 24 Mar 24 12:20:51 PM PDT 24 30461287 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1307048119 Mar 24 12:20:59 PM PDT 24 Mar 24 12:21:01 PM PDT 24 140054600 ps
T564 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.433074049 Mar 24 12:21:02 PM PDT 24 Mar 24 12:21:03 PM PDT 24 89735550 ps
T565 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2140232140 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:06 PM PDT 24 26778677 ps
T79 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1074274390 Mar 24 12:20:50 PM PDT 24 Mar 24 12:20:51 PM PDT 24 164051993 ps
T566 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2457932456 Mar 24 12:20:52 PM PDT 24 Mar 24 12:20:53 PM PDT 24 392383790 ps
T567 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1339952224 Mar 24 12:21:10 PM PDT 24 Mar 24 12:21:11 PM PDT 24 34061983 ps
T568 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3174765892 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:06 PM PDT 24 25525285 ps
T569 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2571911412 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:05 PM PDT 24 28674246 ps
T80 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.816293163 Mar 24 12:21:23 PM PDT 24 Mar 24 12:21:24 PM PDT 24 12466481 ps
T570 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3922449737 Mar 24 12:20:54 PM PDT 24 Mar 24 12:20:56 PM PDT 24 87062302 ps
T571 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1178000206 Mar 24 12:21:10 PM PDT 24 Mar 24 12:21:11 PM PDT 24 38465119 ps
T572 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.388087031 Mar 24 12:20:49 PM PDT 24 Mar 24 12:20:51 PM PDT 24 34496721 ps
T98 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3334116248 Mar 24 12:21:05 PM PDT 24 Mar 24 12:21:06 PM PDT 24 942988870 ps
T573 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1149347455 Mar 24 12:21:26 PM PDT 24 Mar 24 12:21:27 PM PDT 24 15912460 ps
T574 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1680977643 Mar 24 12:21:11 PM PDT 24 Mar 24 12:21:12 PM PDT 24 31342290 ps
T575 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2606927153 Mar 24 12:22:37 PM PDT 24 Mar 24 12:22:38 PM PDT 24 14838632 ps
T576 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2599645472 Mar 24 12:22:01 PM PDT 24 Mar 24 12:22:07 PM PDT 24 33897416 ps
T577 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1643866303 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:10 PM PDT 24 45813033 ps
T578 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4010094305 Mar 24 12:20:54 PM PDT 24 Mar 24 12:20:55 PM PDT 24 12766000 ps
T579 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.539178189 Mar 24 12:21:30 PM PDT 24 Mar 24 12:21:31 PM PDT 24 27768089 ps
T580 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1511688610 Mar 24 12:20:49 PM PDT 24 Mar 24 12:20:50 PM PDT 24 16264258 ps
T581 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3703908909 Mar 24 12:20:59 PM PDT 24 Mar 24 12:21:00 PM PDT 24 90525338 ps
T582 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3498327204 Mar 24 12:22:11 PM PDT 24 Mar 24 12:22:15 PM PDT 24 4624975575 ps

Test location /workspace/coverage/default/66.rv_timer_random.2597518739
Short name T3
Test name
Test status
Simulation time 117178473961 ps
CPU time 2438.92 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 01:25:40 PM PDT 24
Peak memory 190912 kb
Host smart-3e040cac-be12-44cf-9145-3cbf02808545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597518739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2597518739
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2785599799
Short name T13
Test name
Test status
Simulation time 175166772078 ps
CPU time 580.43 seconds
Started Mar 24 12:44:45 PM PDT 24
Finished Mar 24 12:54:27 PM PDT 24
Peak memory 205640 kb
Host smart-2dda21a7-8bc1-4a7b-96a7-666c15dab58d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785599799 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2785599799
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2118702939
Short name T104
Test name
Test status
Simulation time 3793035042348 ps
CPU time 2869.12 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 01:32:18 PM PDT 24
Peak memory 190868 kb
Host smart-f1c6a741-4019-40e6-a971-aba1fef6bb65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118702939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2118702939
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1203417111
Short name T29
Test name
Test status
Simulation time 469330144 ps
CPU time 1.35 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:01 PM PDT 24
Peak memory 195272 kb
Host smart-fb023085-21f0-47b3-b199-b2082b3403b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203417111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1203417111
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2467179796
Short name T166
Test name
Test status
Simulation time 3052244958371 ps
CPU time 7100.41 seconds
Started Mar 24 12:44:49 PM PDT 24
Finished Mar 24 02:43:11 PM PDT 24
Peak memory 190884 kb
Host smart-3ea287f9-932c-4b97-b97b-b226af391e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467179796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2467179796
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2142966267
Short name T149
Test name
Test status
Simulation time 376414438826 ps
CPU time 1758.89 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 01:13:48 PM PDT 24
Peak memory 195512 kb
Host smart-04e0d557-7cb0-49d1-a959-ac9f09042f79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142966267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2142966267
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4089663849
Short name T129
Test name
Test status
Simulation time 294743557490 ps
CPU time 902.09 seconds
Started Mar 24 12:44:43 PM PDT 24
Finished Mar 24 12:59:45 PM PDT 24
Peak memory 190860 kb
Host smart-085c0d36-dc2a-45b2-8c9b-1dac6cfd1cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089663849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4089663849
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.225357811
Short name T189
Test name
Test status
Simulation time 1886061377082 ps
CPU time 1663.75 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 01:12:51 PM PDT 24
Peak memory 190888 kb
Host smart-fa84abeb-9a32-4216-9777-3218386c8787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225357811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
225357811
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.499396423
Short name T295
Test name
Test status
Simulation time 1090767219015 ps
CPU time 3241.18 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 01:38:24 PM PDT 24
Peak memory 190860 kb
Host smart-c1279f26-53a5-4105-8062-5f0e9db1e8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499396423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.499396423
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1746134588
Short name T28
Test name
Test status
Simulation time 2986332195788 ps
CPU time 1709.18 seconds
Started Mar 24 12:44:56 PM PDT 24
Finished Mar 24 01:13:26 PM PDT 24
Peak memory 190824 kb
Host smart-4240f600-acbd-4dfb-b2ba-9f8108c1e200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746134588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1746134588
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3731479574
Short name T143
Test name
Test status
Simulation time 2584947603944 ps
CPU time 1471.07 seconds
Started Mar 24 12:44:59 PM PDT 24
Finished Mar 24 01:09:30 PM PDT 24
Peak memory 190904 kb
Host smart-5952c12f-1a11-4c6c-9329-dcd658d768ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731479574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3731479574
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1946356791
Short name T73
Test name
Test status
Simulation time 33359615 ps
CPU time 0.61 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:02 PM PDT 24
Peak memory 182684 kb
Host smart-4e2f9966-9576-454b-aa32-011330a57cf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946356791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1946356791
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3133594268
Short name T221
Test name
Test status
Simulation time 2930443657066 ps
CPU time 1753.34 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 01:14:22 PM PDT 24
Peak memory 190716 kb
Host smart-6da8ead9-83da-42fa-9a22-615e96bb4b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133594268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3133594268
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3737577403
Short name T245
Test name
Test status
Simulation time 2580869015753 ps
CPU time 2498.08 seconds
Started Mar 24 12:44:56 PM PDT 24
Finished Mar 24 01:26:35 PM PDT 24
Peak memory 190892 kb
Host smart-5780f0e9-c83b-4444-b421-d68b232d62a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737577403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3737577403
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2495535383
Short name T18
Test name
Test status
Simulation time 252357547 ps
CPU time 0.85 seconds
Started Mar 24 12:44:26 PM PDT 24
Finished Mar 24 12:44:27 PM PDT 24
Peak memory 213300 kb
Host smart-14d90dd9-b785-494e-a150-196c90108dd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495535383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2495535383
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2593184662
Short name T167
Test name
Test status
Simulation time 1161049739385 ps
CPU time 1596.07 seconds
Started Mar 24 12:44:46 PM PDT 24
Finished Mar 24 01:11:24 PM PDT 24
Peak memory 190888 kb
Host smart-42f37845-5613-4c0c-94a6-b99a8ea29be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593184662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2593184662
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random.56141304
Short name T4
Test name
Test status
Simulation time 203590500175 ps
CPU time 1813.91 seconds
Started Mar 24 12:44:32 PM PDT 24
Finished Mar 24 01:14:46 PM PDT 24
Peak memory 190892 kb
Host smart-e0681510-15eb-4bc0-a1db-ec950c04f79c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56141304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.56141304
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3739461020
Short name T210
Test name
Test status
Simulation time 3224756971979 ps
CPU time 2285.47 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 01:22:18 PM PDT 24
Peak memory 191108 kb
Host smart-6be5eea9-97a3-4fc2-b130-35791af4b73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739461020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3739461020
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1126691520
Short name T206
Test name
Test status
Simulation time 541331191633 ps
CPU time 321.26 seconds
Started Mar 24 12:44:39 PM PDT 24
Finished Mar 24 12:50:06 PM PDT 24
Peak memory 190896 kb
Host smart-6bac0e75-424f-4efd-8534-04b3e5d18e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126691520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1126691520
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.482177946
Short name T144
Test name
Test status
Simulation time 2850265455216 ps
CPU time 1258.65 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 01:05:27 PM PDT 24
Peak memory 190860 kb
Host smart-fb57ee3d-31d7-4943-b73b-1fecf20fc6b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482177946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.482177946
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4235126253
Short name T268
Test name
Test status
Simulation time 1713631761625 ps
CPU time 2095.96 seconds
Started Mar 24 12:44:27 PM PDT 24
Finished Mar 24 01:19:23 PM PDT 24
Peak memory 190912 kb
Host smart-2354361c-25d9-4bdd-9bc3-211540d8da0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235126253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4235126253
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_random.978970014
Short name T67
Test name
Test status
Simulation time 144764234820 ps
CPU time 236.42 seconds
Started Mar 24 12:44:56 PM PDT 24
Finished Mar 24 12:48:53 PM PDT 24
Peak memory 190896 kb
Host smart-a0bc3a98-e09f-433c-855e-46ae0265eb3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978970014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.978970014
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3927858218
Short name T156
Test name
Test status
Simulation time 1399107858449 ps
CPU time 2163.29 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 01:20:28 PM PDT 24
Peak memory 191124 kb
Host smart-0cf0f3ef-302c-4e39-b70d-c9b2ca62094c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927858218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3927858218
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1764140687
Short name T94
Test name
Test status
Simulation time 600245970226 ps
CPU time 1370.13 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 01:07:14 PM PDT 24
Peak memory 190892 kb
Host smart-21f95334-b33e-4c1c-9579-ac5e370ddcd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764140687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1764140687
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.3841314120
Short name T254
Test name
Test status
Simulation time 141950330381 ps
CPU time 411.21 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 12:51:57 PM PDT 24
Peak memory 190836 kb
Host smart-c3ae32d1-9fd8-4a12-b0ed-cfc64bc61ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841314120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3841314120
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1175926081
Short name T325
Test name
Test status
Simulation time 625474531628 ps
CPU time 904.56 seconds
Started Mar 24 12:44:46 PM PDT 24
Finished Mar 24 12:59:52 PM PDT 24
Peak memory 190920 kb
Host smart-a2f80e74-53d3-44de-b395-a6aa86406164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175926081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1175926081
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4269240623
Short name T217
Test name
Test status
Simulation time 279665126421 ps
CPU time 728.29 seconds
Started Mar 24 12:44:41 PM PDT 24
Finished Mar 24 12:56:50 PM PDT 24
Peak memory 190868 kb
Host smart-556df6ec-e637-453a-80b4-e457c3fd1b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269240623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4269240623
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.3585533071
Short name T131
Test name
Test status
Simulation time 139719045198 ps
CPU time 253.59 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:49:31 PM PDT 24
Peak memory 190872 kb
Host smart-8c118d1c-a3e0-442e-bc13-842d8f9ab7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585533071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3585533071
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1918588457
Short name T327
Test name
Test status
Simulation time 154830522856 ps
CPU time 540.47 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:54:12 PM PDT 24
Peak memory 190808 kb
Host smart-98c853c7-6f12-4e17-8e8e-a72166cd75da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918588457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1918588457
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2653878640
Short name T53
Test name
Test status
Simulation time 126089889463 ps
CPU time 256.69 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:49:18 PM PDT 24
Peak memory 190912 kb
Host smart-dffd7c04-cf08-4330-971d-2d4b6629d6cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653878640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2653878640
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/99.rv_timer_random.101743668
Short name T108
Test name
Test status
Simulation time 125234844208 ps
CPU time 487.83 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 12:53:24 PM PDT 24
Peak memory 190904 kb
Host smart-dc69de0b-07b6-4e4b-8e9d-5d060953d276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101743668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.101743668
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1938045785
Short name T133
Test name
Test status
Simulation time 3670775614326 ps
CPU time 1028.19 seconds
Started Mar 24 12:44:50 PM PDT 24
Finished Mar 24 01:01:59 PM PDT 24
Peak memory 182664 kb
Host smart-bdddb16d-449e-4771-bd6f-2e1ffcace702
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938045785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1938045785
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.2878518729
Short name T125
Test name
Test status
Simulation time 233616311397 ps
CPU time 816.36 seconds
Started Mar 24 12:44:48 PM PDT 24
Finished Mar 24 12:58:25 PM PDT 24
Peak memory 190856 kb
Host smart-60e77907-118c-40d2-bd46-f247eb93e7fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878518729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2878518729
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.85459068
Short name T81
Test name
Test status
Simulation time 346421632 ps
CPU time 0.83 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 193096 kb
Host smart-56d42aa1-c54a-44d3-b1a3-ec84d90f9d3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85459068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_tim
er_same_csr_outstanding.85459068
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/145.rv_timer_random.3915386689
Short name T328
Test name
Test status
Simulation time 406283028215 ps
CPU time 1359.49 seconds
Started Mar 24 12:45:00 PM PDT 24
Finished Mar 24 01:07:40 PM PDT 24
Peak memory 190816 kb
Host smart-b23e19c2-7d75-4dea-8e4d-d11e6ea726d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915386689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3915386689
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2413709362
Short name T220
Test name
Test status
Simulation time 212085600647 ps
CPU time 194.12 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 190816 kb
Host smart-abca55c0-eabb-4ac6-ac78-75342b43aa4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413709362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2413709362
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.686858398
Short name T287
Test name
Test status
Simulation time 4003438787874 ps
CPU time 3031.1 seconds
Started Mar 24 12:44:39 PM PDT 24
Finished Mar 24 01:35:10 PM PDT 24
Peak memory 190864 kb
Host smart-3d043f23-c4b2-4746-af68-e8da44a4cb7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686858398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
686858398
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/83.rv_timer_random.1020772081
Short name T148
Test name
Test status
Simulation time 388431001617 ps
CPU time 338.8 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:50:46 PM PDT 24
Peak memory 190848 kb
Host smart-7ffd7d77-cca1-459c-8563-77e72a8bb978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020772081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1020772081
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.497266895
Short name T226
Test name
Test status
Simulation time 104513212607 ps
CPU time 912.66 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 01:00:23 PM PDT 24
Peak memory 190892 kb
Host smart-b147e481-6d92-4413-b381-d1dffa3cd4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497266895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.497266895
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.3595730738
Short name T333
Test name
Test status
Simulation time 120891400325 ps
CPU time 204.09 seconds
Started Mar 24 12:45:21 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 190900 kb
Host smart-52ff23fd-aac4-41d0-9ea0-c21c819120fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595730738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3595730738
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1480469713
Short name T264
Test name
Test status
Simulation time 316253452252 ps
CPU time 465.91 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 12:53:02 PM PDT 24
Peak memory 190872 kb
Host smart-77b54b57-8e80-4b72-9eae-e5ebbac89c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480469713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1480469713
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.649411805
Short name T311
Test name
Test status
Simulation time 204827679223 ps
CPU time 495.07 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:53:19 PM PDT 24
Peak memory 190864 kb
Host smart-6e226653-1dda-4c5d-a6cd-a30bc3ba9e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649411805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.649411805
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3493060912
Short name T184
Test name
Test status
Simulation time 218250690194 ps
CPU time 518.96 seconds
Started Mar 24 12:44:34 PM PDT 24
Finished Mar 24 12:53:18 PM PDT 24
Peak memory 182668 kb
Host smart-53510dd6-562f-4e29-b079-5753663a9e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493060912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3493060912
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/103.rv_timer_random.3437239682
Short name T288
Test name
Test status
Simulation time 164320053872 ps
CPU time 755.64 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:57:46 PM PDT 24
Peak memory 190860 kb
Host smart-12432d2f-61a5-4a1f-ad87-6cb986c40a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437239682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3437239682
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.630979542
Short name T197
Test name
Test status
Simulation time 290858693640 ps
CPU time 165.09 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:47:55 PM PDT 24
Peak memory 190820 kb
Host smart-00aa0f7e-b892-4786-9dd5-734a461c53c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630979542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.630979542
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.247198345
Short name T201
Test name
Test status
Simulation time 415536736446 ps
CPU time 2117.15 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 01:20:38 PM PDT 24
Peak memory 190876 kb
Host smart-7dae3bce-2756-4360-8a37-657d565c03c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247198345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.247198345
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2612899824
Short name T430
Test name
Test status
Simulation time 1295583697320 ps
CPU time 892.32 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 12:59:37 PM PDT 24
Peak memory 190876 kb
Host smart-415bdf9e-244a-448f-b033-59d103050889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612899824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2612899824
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/164.rv_timer_random.2825465756
Short name T243
Test name
Test status
Simulation time 1020141037353 ps
CPU time 900.33 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 01:00:15 PM PDT 24
Peak memory 190868 kb
Host smart-89df7a53-d3ef-415d-b520-d1b78525dcb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825465756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2825465756
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2780158845
Short name T278
Test name
Test status
Simulation time 343576827918 ps
CPU time 300.28 seconds
Started Mar 24 12:45:19 PM PDT 24
Finished Mar 24 12:50:20 PM PDT 24
Peak memory 194320 kb
Host smart-16b2c570-cdef-41e2-9948-f294ba51f4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780158845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2780158845
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.840463459
Short name T181
Test name
Test status
Simulation time 380940694585 ps
CPU time 291.61 seconds
Started Mar 24 12:44:40 PM PDT 24
Finished Mar 24 12:49:32 PM PDT 24
Peak memory 191084 kb
Host smart-b484256b-c84c-491a-80a3-81619f8c97d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840463459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.840463459
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3121374375
Short name T429
Test name
Test status
Simulation time 192813467491 ps
CPU time 301 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 182724 kb
Host smart-2ad48bb0-7945-4d2b-b658-ba66be2c9c51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121374375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3121374375
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3599418946
Short name T48
Test name
Test status
Simulation time 2100221610632 ps
CPU time 691.15 seconds
Started Mar 24 12:44:58 PM PDT 24
Finished Mar 24 12:56:29 PM PDT 24
Peak memory 190852 kb
Host smart-1b5fcfda-faf6-4518-95c6-9555f07fe323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599418946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3599418946
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/84.rv_timer_random.1933242036
Short name T183
Test name
Test status
Simulation time 228267048606 ps
CPU time 1588.88 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 01:11:42 PM PDT 24
Peak memory 190828 kb
Host smart-bd0245df-5ae0-4f47-ad5e-4db6452e98d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933242036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1933242036
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2481615861
Short name T31
Test name
Test status
Simulation time 87136154 ps
CPU time 1.06 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 183080 kb
Host smart-c3faa256-c73f-47f4-862d-e2d1c6abf851
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481615861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2481615861
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2138178580
Short name T291
Test name
Test status
Simulation time 1199120446648 ps
CPU time 617.23 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:54:33 PM PDT 24
Peak memory 182720 kb
Host smart-2e3a5bbd-e537-474c-bd07-3332ea4f0019
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138178580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2138178580
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/105.rv_timer_random.1299745917
Short name T223
Test name
Test status
Simulation time 422160833048 ps
CPU time 144.33 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 190884 kb
Host smart-581bbf28-3821-4dd3-8875-8e67ed79148a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299745917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1299745917
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.4123456720
Short name T145
Test name
Test status
Simulation time 370832028688 ps
CPU time 322.94 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 12:50:08 PM PDT 24
Peak memory 182648 kb
Host smart-67b6cfea-3ae3-4b44-9ece-cfe059f39bca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123456720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.4123456720
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2187907932
Short name T141
Test name
Test status
Simulation time 968930975935 ps
CPU time 593.28 seconds
Started Mar 24 12:44:49 PM PDT 24
Finished Mar 24 12:54:44 PM PDT 24
Peak memory 182704 kb
Host smart-83ace490-de1f-4825-8142-e0e09b74f3cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187907932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2187907932
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/156.rv_timer_random.583337228
Short name T250
Test name
Test status
Simulation time 83210534093 ps
CPU time 124.94 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:47:06 PM PDT 24
Peak memory 190912 kb
Host smart-7a70b4f7-c923-4d56-a2b6-ab7243845477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583337228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.583337228
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.1415123555
Short name T190
Test name
Test status
Simulation time 100823404700 ps
CPU time 200.86 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:48:29 PM PDT 24
Peak memory 190880 kb
Host smart-a0bf142b-c27a-4a60-88ae-4cd9ef0ca52f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415123555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1415123555
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2664861474
Short name T339
Test name
Test status
Simulation time 78764028510 ps
CPU time 238.36 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:49:11 PM PDT 24
Peak memory 182712 kb
Host smart-ae1a557c-aa8a-452c-9a93-61e1961e2e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664861474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2664861474
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.615086523
Short name T168
Test name
Test status
Simulation time 152600349391 ps
CPU time 284.56 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:49:54 PM PDT 24
Peak memory 190864 kb
Host smart-274fabae-7c54-4920-bb11-546e8294f14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615086523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.615086523
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2005592152
Short name T119
Test name
Test status
Simulation time 162926928987 ps
CPU time 1118.84 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 01:03:55 PM PDT 24
Peak memory 182928 kb
Host smart-d8aa1906-c860-426a-a9f5-be1b93ea514b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005592152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2005592152
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.4119581410
Short name T214
Test name
Test status
Simulation time 6500588086107 ps
CPU time 1598.37 seconds
Started Mar 24 12:44:43 PM PDT 24
Finished Mar 24 01:11:22 PM PDT 24
Peak memory 182652 kb
Host smart-50aba892-fab0-4651-8e69-538f335053ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119581410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.4119581410
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3284867724
Short name T25
Test name
Test status
Simulation time 624163669067 ps
CPU time 776.54 seconds
Started Mar 24 12:45:00 PM PDT 24
Finished Mar 24 12:57:57 PM PDT 24
Peak memory 194820 kb
Host smart-7047c220-c62a-420e-9636-06ceec3824cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284867724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3284867724
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.979757869
Short name T112
Test name
Test status
Simulation time 658552868604 ps
CPU time 362.1 seconds
Started Mar 24 12:44:50 PM PDT 24
Finished Mar 24 12:50:53 PM PDT 24
Peak memory 182692 kb
Host smart-2009900f-5d2f-4b6c-ba1f-a22cc38b5576
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979757869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.979757869
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3631849172
Short name T323
Test name
Test status
Simulation time 265790603883 ps
CPU time 137.84 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 12:47:02 PM PDT 24
Peak memory 182736 kb
Host smart-968efae2-7c78-497e-a006-b26e9c8b2314
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631849172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3631849172
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/53.rv_timer_random.1787249342
Short name T5
Test name
Test status
Simulation time 111423674297 ps
CPU time 40.78 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:45:53 PM PDT 24
Peak memory 190872 kb
Host smart-6d4d6dbf-d615-46f2-b5c4-1780bf2b017f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787249342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1787249342
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2208118077
Short name T318
Test name
Test status
Simulation time 1105787686990 ps
CPU time 165.02 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:47:49 PM PDT 24
Peak memory 190892 kb
Host smart-4c3e4ce6-a8be-4ddb-b2c9-eaa104fcbb02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208118077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2208118077
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2082502176
Short name T316
Test name
Test status
Simulation time 2124524542 ps
CPU time 8.46 seconds
Started Mar 24 12:44:19 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 190688 kb
Host smart-f603dc12-15c1-4a15-9f7e-c07c63c90bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082502176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2082502176
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1131720527
Short name T344
Test name
Test status
Simulation time 1488028862635 ps
CPU time 850.62 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 12:58:39 PM PDT 24
Peak memory 182696 kb
Host smart-eeb7eb6f-f70a-4d25-a27b-760ceedd9378
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131720527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1131720527
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/106.rv_timer_random.1068619285
Short name T321
Test name
Test status
Simulation time 755063206884 ps
CPU time 2354.14 seconds
Started Mar 24 12:45:32 PM PDT 24
Finished Mar 24 01:24:46 PM PDT 24
Peak memory 190908 kb
Host smart-91aa3fa4-c301-4d34-a8f6-c66a8ba82523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068619285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1068619285
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.3656995325
Short name T41
Test name
Test status
Simulation time 149963738917 ps
CPU time 837.9 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 12:58:27 PM PDT 24
Peak memory 193892 kb
Host smart-990f2f54-bbc3-4bb6-9909-96c493c97daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656995325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3656995325
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2769288112
Short name T213
Test name
Test status
Simulation time 919453314576 ps
CPU time 1113.06 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 01:03:45 PM PDT 24
Peak memory 190824 kb
Host smart-e9adf329-ba5d-490a-acf4-c1dc3d2eb1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769288112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2769288112
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1163295130
Short name T340
Test name
Test status
Simulation time 82328957952 ps
CPU time 1702.03 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 01:13:30 PM PDT 24
Peak memory 190900 kb
Host smart-49ecad84-2c88-426d-a76d-b2d446ce5646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163295130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1163295130
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1073522501
Short name T446
Test name
Test status
Simulation time 10194513900 ps
CPU time 9.27 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 12:44:32 PM PDT 24
Peak memory 182668 kb
Host smart-a22f59b0-706d-49f5-a208-9fb106ddcad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073522501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1073522501
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/126.rv_timer_random.3218383474
Short name T139
Test name
Test status
Simulation time 138716264707 ps
CPU time 224.43 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:48:56 PM PDT 24
Peak memory 191140 kb
Host smart-2cde9848-3932-48dc-8f81-ff591eddef17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218383474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3218383474
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2394348030
Short name T107
Test name
Test status
Simulation time 2784203616884 ps
CPU time 2045.01 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 01:19:14 PM PDT 24
Peak memory 191228 kb
Host smart-e940bdd8-9539-4def-9f0a-e26943179f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394348030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2394348030
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3887123442
Short name T237
Test name
Test status
Simulation time 178952840234 ps
CPU time 329.67 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:50:40 PM PDT 24
Peak memory 190912 kb
Host smart-7b00fc66-78f5-42a8-8da5-9d580ff3a318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887123442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3887123442
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3959381814
Short name T271
Test name
Test status
Simulation time 567583839266 ps
CPU time 526.62 seconds
Started Mar 24 12:44:31 PM PDT 24
Finished Mar 24 12:53:18 PM PDT 24
Peak memory 190864 kb
Host smart-91e6a9b6-76d5-44b1-a67a-365ae3b44243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959381814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3959381814
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2888676014
Short name T297
Test name
Test status
Simulation time 127939979227 ps
CPU time 120.1 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:47:18 PM PDT 24
Peak memory 190908 kb
Host smart-f8362bef-fc46-4529-b11d-4a2a6cdc4b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888676014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2888676014
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2114109425
Short name T160
Test name
Test status
Simulation time 496980556999 ps
CPU time 235.23 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:49:07 PM PDT 24
Peak memory 190832 kb
Host smart-46659594-f489-42e7-af01-536b4a8ea330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114109425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2114109425
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3881262484
Short name T179
Test name
Test status
Simulation time 311164764969 ps
CPU time 218.49 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:48:52 PM PDT 24
Peak memory 190916 kb
Host smart-152ebb1d-a370-42c1-a9db-e655df7b8e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881262484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3881262484
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1075439702
Short name T212
Test name
Test status
Simulation time 74896672843 ps
CPU time 129.82 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:47:17 PM PDT 24
Peak memory 194144 kb
Host smart-74ed608e-85e6-4535-bdf5-62a9e7ee08a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075439702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1075439702
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1274175394
Short name T300
Test name
Test status
Simulation time 291826081591 ps
CPU time 258.77 seconds
Started Mar 24 12:44:42 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 182692 kb
Host smart-f93e930d-1a35-4569-8c58-6f1a53587d52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274175394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1274175394
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.693036596
Short name T204
Test name
Test status
Simulation time 662514023351 ps
CPU time 1135.45 seconds
Started Mar 24 12:44:46 PM PDT 24
Finished Mar 24 01:03:43 PM PDT 24
Peak memory 190884 kb
Host smart-d27c3783-bdf5-4e7b-8714-ebcbb20542d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693036596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
693036596
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1610604073
Short name T207
Test name
Test status
Simulation time 3936168060 ps
CPU time 7.74 seconds
Started Mar 24 12:44:46 PM PDT 24
Finished Mar 24 12:44:56 PM PDT 24
Peak memory 182672 kb
Host smart-24b4cdab-1a00-4add-8771-f45ca7a98879
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610604073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1610604073
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.460688867
Short name T147
Test name
Test status
Simulation time 10683087605 ps
CPU time 17.54 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 12:45:24 PM PDT 24
Peak memory 182632 kb
Host smart-76f95f6e-8709-4d28-91bb-4024ec983d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460688867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.460688867
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2654127433
Short name T27
Test name
Test status
Simulation time 1194681296224 ps
CPU time 550.57 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:54:09 PM PDT 24
Peak memory 194508 kb
Host smart-793b7390-4eb7-47b5-8767-c6f61b17dc84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654127433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2654127433
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4255479771
Short name T240
Test name
Test status
Simulation time 86794685961 ps
CPU time 37.05 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 12:45:00 PM PDT 24
Peak memory 182708 kb
Host smart-0543ae31-fdb1-4303-8eba-8b3b64d5621a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255479771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.4255479771
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.15353693
Short name T52
Test name
Test status
Simulation time 733147622472 ps
CPU time 1219.73 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 01:05:28 PM PDT 24
Peak memory 194112 kb
Host smart-c90b5851-b140-4d5a-85f0-cdc88fffeeb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15353693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.15353693
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1769919795
Short name T192
Test name
Test status
Simulation time 213534685056 ps
CPU time 279.74 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 182636 kb
Host smart-b7a8cf89-b713-411b-b1ea-7d7a5f846c05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769919795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1769919795
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2103434260
Short name T150
Test name
Test status
Simulation time 2016017235626 ps
CPU time 1810.97 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 01:14:27 PM PDT 24
Peak memory 195088 kb
Host smart-127c354f-8a14-4e06-b447-2fec96a8e23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103434260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2103434260
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2606927153
Short name T575
Test name
Test status
Simulation time 14838632 ps
CPU time 0.59 seconds
Started Mar 24 12:22:37 PM PDT 24
Finished Mar 24 12:22:38 PM PDT 24
Peak memory 182548 kb
Host smart-600c2661-6858-4169-9bea-806f4a8769cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606927153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2606927153
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4261319264
Short name T529
Test name
Test status
Simulation time 202850293 ps
CPU time 1.42 seconds
Started Mar 24 12:22:50 PM PDT 24
Finished Mar 24 12:22:52 PM PDT 24
Peak memory 182700 kb
Host smart-06b9cb1b-fe10-486e-84e5-bef3c30ea752
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261319264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.4261319264
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1270502581
Short name T506
Test name
Test status
Simulation time 12795767 ps
CPU time 0.53 seconds
Started Mar 24 12:22:40 PM PDT 24
Finished Mar 24 12:22:41 PM PDT 24
Peak memory 182544 kb
Host smart-648baeb4-0ada-491c-9bb4-85e912cb0376
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270502581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1270502581
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2179640440
Short name T533
Test name
Test status
Simulation time 235400044 ps
CPU time 0.84 seconds
Started Mar 24 12:22:11 PM PDT 24
Finished Mar 24 12:22:12 PM PDT 24
Peak memory 196112 kb
Host smart-7eeb9822-aa28-4e3b-ac6f-b649c7e1c660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179640440 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2179640440
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3721669090
Short name T72
Test name
Test status
Simulation time 44803806 ps
CPU time 0.54 seconds
Started Mar 24 12:20:30 PM PDT 24
Finished Mar 24 12:20:31 PM PDT 24
Peak memory 182980 kb
Host smart-78f35c93-6038-4594-8595-1fb099e4d039
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721669090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3721669090
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.60547938
Short name T552
Test name
Test status
Simulation time 32460538 ps
CPU time 0.55 seconds
Started Mar 24 12:20:38 PM PDT 24
Finished Mar 24 12:20:38 PM PDT 24
Peak memory 181884 kb
Host smart-7da77168-8a35-4f06-aefb-cbe02b012320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60547938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.60547938
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3322775047
Short name T87
Test name
Test status
Simulation time 135959038 ps
CPU time 0.83 seconds
Started Mar 24 12:20:37 PM PDT 24
Finished Mar 24 12:20:38 PM PDT 24
Peak memory 193152 kb
Host smart-afc19f68-e1ae-4fa9-9cb7-d62b0ba854e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322775047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3322775047
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2880868158
Short name T493
Test name
Test status
Simulation time 57526059 ps
CPU time 1.17 seconds
Started Mar 24 12:20:24 PM PDT 24
Finished Mar 24 12:20:25 PM PDT 24
Peak memory 197976 kb
Host smart-5787e7fa-b893-4c4e-88b6-b8d122e92ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880868158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2880868158
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1222896971
Short name T500
Test name
Test status
Simulation time 594085792 ps
CPU time 1.11 seconds
Started Mar 24 12:20:38 PM PDT 24
Finished Mar 24 12:20:39 PM PDT 24
Peak memory 183240 kb
Host smart-868360b1-94a3-435c-a7ee-6f3a9710fabe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222896971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1222896971
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.297024110
Short name T74
Test name
Test status
Simulation time 142404477 ps
CPU time 0.64 seconds
Started Mar 24 12:22:11 PM PDT 24
Finished Mar 24 12:22:12 PM PDT 24
Peak memory 181200 kb
Host smart-89e0e4a1-4ae2-45b0-886a-3eed17363768
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297024110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.297024110
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3498327204
Short name T582
Test name
Test status
Simulation time 4624975575 ps
CPU time 3.51 seconds
Started Mar 24 12:22:11 PM PDT 24
Finished Mar 24 12:22:15 PM PDT 24
Peak memory 181488 kb
Host smart-1cc52a93-dfed-46e0-a092-5398b5315d0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498327204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3498327204
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.395312139
Short name T491
Test name
Test status
Simulation time 49692414 ps
CPU time 0.56 seconds
Started Mar 24 12:23:06 PM PDT 24
Finished Mar 24 12:23:07 PM PDT 24
Peak memory 182520 kb
Host smart-7b50fa03-966b-48fe-9acf-78477ee844da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395312139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.395312139
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1057165774
Short name T528
Test name
Test status
Simulation time 56218608 ps
CPU time 0.85 seconds
Started Mar 24 12:20:37 PM PDT 24
Finished Mar 24 12:20:38 PM PDT 24
Peak memory 194824 kb
Host smart-49422b71-df8c-49bf-a333-7f9d842fb6f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057165774 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1057165774
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2983865
Short name T42
Test name
Test status
Simulation time 15255620 ps
CPU time 0.55 seconds
Started Mar 24 12:20:35 PM PDT 24
Finished Mar 24 12:20:36 PM PDT 24
Peak memory 182452 kb
Host smart-3ff4cbd7-ae2f-44ff-a1ea-9fb5372241e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2983865
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3213998003
Short name T473
Test name
Test status
Simulation time 209555639 ps
CPU time 0.53 seconds
Started Mar 24 12:22:47 PM PDT 24
Finished Mar 24 12:22:48 PM PDT 24
Peak memory 182424 kb
Host smart-f6032e76-dac8-46d1-b46b-df0b97d10633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213998003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3213998003
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2609828232
Short name T86
Test name
Test status
Simulation time 25138292 ps
CPU time 0.65 seconds
Started Mar 24 12:20:37 PM PDT 24
Finished Mar 24 12:20:38 PM PDT 24
Peak memory 191912 kb
Host smart-1be0d9da-d45d-4c4e-9930-2cf856c6515f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609828232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2609828232
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2056930585
Short name T509
Test name
Test status
Simulation time 521571365 ps
CPU time 2.29 seconds
Started Mar 24 12:20:38 PM PDT 24
Finished Mar 24 12:20:40 PM PDT 24
Peak memory 197404 kb
Host smart-2ff999e9-f75f-4074-b672-c04a0105ede7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056930585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2056930585
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1316491726
Short name T30
Test name
Test status
Simulation time 170009096 ps
CPU time 0.85 seconds
Started Mar 24 12:20:36 PM PDT 24
Finished Mar 24 12:20:37 PM PDT 24
Peak memory 193840 kb
Host smart-fa3dc936-9ff4-446e-80d6-f519e637036a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316491726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1316491726
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.94868549
Short name T519
Test name
Test status
Simulation time 56626618 ps
CPU time 1.43 seconds
Started Mar 24 12:20:58 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 197364 kb
Host smart-de67bb68-4e64-4b4c-a0a3-67d7197dc2b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94868549 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.94868549
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3102692758
Short name T58
Test name
Test status
Simulation time 79734457 ps
CPU time 0.57 seconds
Started Mar 24 12:21:28 PM PDT 24
Finished Mar 24 12:21:29 PM PDT 24
Peak memory 182500 kb
Host smart-1c42f0ef-d37b-4ba4-833b-dcf159b68b4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102692758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3102692758
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1643866303
Short name T577
Test name
Test status
Simulation time 45813033 ps
CPU time 0.58 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 182428 kb
Host smart-25508e71-27bf-49ce-8fcc-dd13ca2b5f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643866303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1643866303
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3883045621
Short name T554
Test name
Test status
Simulation time 562433470 ps
CPU time 0.87 seconds
Started Mar 24 12:21:17 PM PDT 24
Finished Mar 24 12:21:18 PM PDT 24
Peak memory 191772 kb
Host smart-1e16c802-16f4-4d2b-a20d-0374051a21b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883045621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3883045621
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.975722627
Short name T518
Test name
Test status
Simulation time 35338225 ps
CPU time 1.62 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:07 PM PDT 24
Peak memory 197492 kb
Host smart-d8703211-8330-4ace-88af-e088753fb118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975722627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.975722627
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4264286069
Short name T560
Test name
Test status
Simulation time 105144731 ps
CPU time 1.2 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 183356 kb
Host smart-e08e9454-1883-42b9-8cff-cafe1897f0f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264286069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4264286069
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3603006925
Short name T531
Test name
Test status
Simulation time 28298216 ps
CPU time 1.25 seconds
Started Mar 24 12:21:23 PM PDT 24
Finished Mar 24 12:21:24 PM PDT 24
Peak memory 197512 kb
Host smart-34713e72-4ea4-4c8a-82be-94f7d095f164
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603006925 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3603006925
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.486890987
Short name T556
Test name
Test status
Simulation time 29974972 ps
CPU time 0.55 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:05 PM PDT 24
Peak memory 182584 kb
Host smart-6e04336d-8251-426a-b73e-b7309c0e75bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486890987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.486890987
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1615265666
Short name T561
Test name
Test status
Simulation time 57599060 ps
CPU time 0.55 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 181896 kb
Host smart-93f0d4de-09d4-4232-bd9a-0817825a104c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615265666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1615265666
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1321672189
Short name T84
Test name
Test status
Simulation time 31400523 ps
CPU time 0.73 seconds
Started Mar 24 12:21:27 PM PDT 24
Finished Mar 24 12:21:28 PM PDT 24
Peak memory 192912 kb
Host smart-d8b9a71b-81d7-4e73-b8df-c64677784d43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321672189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1321672189
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2863608079
Short name T494
Test name
Test status
Simulation time 190999761 ps
CPU time 1.2 seconds
Started Mar 24 12:21:23 PM PDT 24
Finished Mar 24 12:21:25 PM PDT 24
Peak memory 197304 kb
Host smart-c0e8197b-9c41-466c-9896-5d366b74b492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863608079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2863608079
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3315885917
Short name T100
Test name
Test status
Simulation time 187821131 ps
CPU time 1.12 seconds
Started Mar 24 12:21:36 PM PDT 24
Finished Mar 24 12:21:38 PM PDT 24
Peak memory 181348 kb
Host smart-dcc197a0-b9e7-43d8-836d-15096510d43c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315885917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3315885917
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4159968867
Short name T499
Test name
Test status
Simulation time 40393935 ps
CPU time 1.1 seconds
Started Mar 24 12:21:23 PM PDT 24
Finished Mar 24 12:21:25 PM PDT 24
Peak memory 196756 kb
Host smart-d79ab2d6-666b-4352-994e-d65907314f9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159968867 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.4159968867
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4205175111
Short name T33
Test name
Test status
Simulation time 14421343 ps
CPU time 0.54 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 182396 kb
Host smart-0013fd5d-1125-427b-8a24-191f448f6a31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205175111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4205175111
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2140232140
Short name T565
Test name
Test status
Simulation time 26778677 ps
CPU time 0.63 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 182564 kb
Host smart-221ff37d-b761-407a-b927-35ea29d806fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140232140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2140232140
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.91572138
Short name T59
Test name
Test status
Simulation time 16169642 ps
CPU time 0.61 seconds
Started Mar 24 12:21:28 PM PDT 24
Finished Mar 24 12:21:30 PM PDT 24
Peak memory 191836 kb
Host smart-121009a1-5e6e-4a42-9bf6-844c8acd440a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91572138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_tim
er_same_csr_outstanding.91572138
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3267458259
Short name T515
Test name
Test status
Simulation time 194155405 ps
CPU time 2.39 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:04 PM PDT 24
Peak memory 197652 kb
Host smart-59067a44-8cdb-4ce0-8d52-c1c6fd91969d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267458259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3267458259
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.433074049
Short name T564
Test name
Test status
Simulation time 89735550 ps
CPU time 1.12 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:03 PM PDT 24
Peak memory 195148 kb
Host smart-8323d169-6a11-454a-808a-6a9837d1cc82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433074049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.433074049
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1871849319
Short name T461
Test name
Test status
Simulation time 38385958 ps
CPU time 1.11 seconds
Started Mar 24 12:21:10 PM PDT 24
Finished Mar 24 12:21:11 PM PDT 24
Peak memory 197696 kb
Host smart-82a5b974-e491-4366-970b-57a5467b0c54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871849319 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1871849319
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2921683203
Short name T545
Test name
Test status
Simulation time 41197740 ps
CPU time 0.68 seconds
Started Mar 24 12:21:16 PM PDT 24
Finished Mar 24 12:21:17 PM PDT 24
Peak memory 181716 kb
Host smart-8ad1472c-8a60-4b86-af13-1d8a5b1ccf08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921683203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2921683203
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1739527925
Short name T480
Test name
Test status
Simulation time 51435586 ps
CPU time 0.59 seconds
Started Mar 24 12:21:10 PM PDT 24
Finished Mar 24 12:21:11 PM PDT 24
Peak memory 182036 kb
Host smart-15a63ea8-650a-451c-bb5e-3a0abfac2107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739527925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1739527925
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3168909338
Short name T512
Test name
Test status
Simulation time 15893714 ps
CPU time 0.63 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:53 PM PDT 24
Peak memory 192420 kb
Host smart-bd4e8296-0c0c-4315-9b63-e25470ff3a2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168909338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3168909338
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3847766267
Short name T462
Test name
Test status
Simulation time 51489660 ps
CPU time 1.36 seconds
Started Mar 24 12:21:06 PM PDT 24
Finished Mar 24 12:21:08 PM PDT 24
Peak memory 197380 kb
Host smart-16f6f7e6-4db1-40bd-9a08-a28df26b6df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847766267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3847766267
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1307048119
Short name T563
Test name
Test status
Simulation time 140054600 ps
CPU time 1.36 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:01 PM PDT 24
Peak memory 183228 kb
Host smart-0d7e835d-02b6-4909-a943-5d1b37c4e719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307048119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1307048119
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3703908909
Short name T581
Test name
Test status
Simulation time 90525338 ps
CPU time 1 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 197204 kb
Host smart-e37523cb-b7a0-4d7a-82e6-7f531193fc93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703908909 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3703908909
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4015820744
Short name T97
Test name
Test status
Simulation time 17659991 ps
CPU time 0.54 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 182608 kb
Host smart-b06608f2-f776-4566-8030-569e731da961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015820744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4015820744
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1257204853
Short name T485
Test name
Test status
Simulation time 38838811 ps
CPU time 0.55 seconds
Started Mar 24 12:21:32 PM PDT 24
Finished Mar 24 12:21:33 PM PDT 24
Peak memory 182396 kb
Host smart-3b9f5c0c-59c5-4c5d-a5b5-f55d0ab16157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257204853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1257204853
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2269822757
Short name T558
Test name
Test status
Simulation time 162647625 ps
CPU time 1.24 seconds
Started Mar 24 12:21:26 PM PDT 24
Finished Mar 24 12:21:28 PM PDT 24
Peak memory 197192 kb
Host smart-cd8fa38e-4ac4-44fc-b144-9d04882a68cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269822757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2269822757
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2443272030
Short name T495
Test name
Test status
Simulation time 40413664 ps
CPU time 0.81 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:53 PM PDT 24
Peak memory 183544 kb
Host smart-073f7948-cbc1-4af8-b313-10f21244b4d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443272030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2443272030
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.784102996
Short name T503
Test name
Test status
Simulation time 140254096 ps
CPU time 1 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 197308 kb
Host smart-043fd1c8-2844-4c30-b230-2fb2845a44ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784102996 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.784102996
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1094556766
Short name T78
Test name
Test status
Simulation time 20390138 ps
CPU time 0.54 seconds
Started Mar 24 12:21:26 PM PDT 24
Finished Mar 24 12:21:27 PM PDT 24
Peak memory 181932 kb
Host smart-5dbf2af5-b66d-4c76-a810-192aa5710f07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094556766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1094556766
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.562888669
Short name T467
Test name
Test status
Simulation time 13670405 ps
CPU time 0.56 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:55 PM PDT 24
Peak memory 182016 kb
Host smart-dc8100fd-419f-49a9-89eb-1da29bd0ab79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562888669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.562888669
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2710856983
Short name T553
Test name
Test status
Simulation time 71027353 ps
CPU time 0.76 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 191572 kb
Host smart-f5900bb0-6d2e-47de-903f-7478cb8bcf0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710856983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2710856983
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.863553752
Short name T488
Test name
Test status
Simulation time 61230292 ps
CPU time 2.7 seconds
Started Mar 24 12:21:26 PM PDT 24
Finished Mar 24 12:21:29 PM PDT 24
Peak memory 197108 kb
Host smart-81618d49-8f5e-41ec-a91e-272037073ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863553752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.863553752
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2033542085
Short name T496
Test name
Test status
Simulation time 97441226 ps
CPU time 1.34 seconds
Started Mar 24 12:20:55 PM PDT 24
Finished Mar 24 12:20:58 PM PDT 24
Peak memory 183296 kb
Host smart-75d9b4f1-5b24-4e2a-9796-a855cf2695c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033542085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2033542085
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2517118833
Short name T457
Test name
Test status
Simulation time 29543453 ps
CPU time 0.75 seconds
Started Mar 24 12:20:58 PM PDT 24
Finished Mar 24 12:20:59 PM PDT 24
Peak memory 195052 kb
Host smart-288eac21-4ce7-4727-9e84-774b5f0610d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517118833 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2517118833
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2237287028
Short name T75
Test name
Test status
Simulation time 15153640 ps
CPU time 0.58 seconds
Started Mar 24 12:21:41 PM PDT 24
Finished Mar 24 12:21:42 PM PDT 24
Peak memory 182536 kb
Host smart-71241ea1-0ca9-436c-a8f2-c760eabff457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237287028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2237287028
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3624320911
Short name T484
Test name
Test status
Simulation time 56601982 ps
CPU time 0.59 seconds
Started Mar 24 12:21:28 PM PDT 24
Finished Mar 24 12:21:29 PM PDT 24
Peak memory 182436 kb
Host smart-0fe56d47-66c5-4fa3-8324-6b4940eb08af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624320911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3624320911
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1925634382
Short name T521
Test name
Test status
Simulation time 60232930 ps
CPU time 0.62 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 191892 kb
Host smart-9ea9f44d-a73c-4b9f-bffb-d076fd3b6b0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925634382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1925634382
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1919250499
Short name T479
Test name
Test status
Simulation time 146964487 ps
CPU time 1.79 seconds
Started Mar 24 12:21:38 PM PDT 24
Finished Mar 24 12:21:40 PM PDT 24
Peak memory 197412 kb
Host smart-31efb539-ee12-4c16-afa3-2bd7069b5eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919250499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1919250499
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1005627495
Short name T508
Test name
Test status
Simulation time 354693527 ps
CPU time 1.37 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 183784 kb
Host smart-bb554780-98fa-4b1a-85a1-5d9fc7121311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005627495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1005627495
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3174765892
Short name T568
Test name
Test status
Simulation time 25525285 ps
CPU time 0.71 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 195108 kb
Host smart-b1be2608-c7ef-4b6e-8348-d9b1175568e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174765892 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3174765892
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2512276
Short name T535
Test name
Test status
Simulation time 16716642 ps
CPU time 0.64 seconds
Started Mar 24 12:20:56 PM PDT 24
Finished Mar 24 12:20:58 PM PDT 24
Peak memory 182656 kb
Host smart-6838c15b-cc40-46c5-93a6-e61e20cf4bc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2512276
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3178402377
Short name T559
Test name
Test status
Simulation time 19404694 ps
CPU time 0.57 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 182408 kb
Host smart-4e2a5eae-6605-4406-b823-6bea2e719da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178402377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3178402377
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3813633919
Short name T524
Test name
Test status
Simulation time 246876590 ps
CPU time 0.81 seconds
Started Mar 24 12:21:41 PM PDT 24
Finished Mar 24 12:21:42 PM PDT 24
Peak memory 193272 kb
Host smart-e8bafcaa-5bd7-4eff-99e6-03cd1e5ea7ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813633919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3813633919
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2154437655
Short name T477
Test name
Test status
Simulation time 460733470 ps
CPU time 2.41 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:08 PM PDT 24
Peak memory 197516 kb
Host smart-f9901ad4-5ae5-40c4-adf5-5486af322a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154437655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2154437655
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3334116248
Short name T98
Test name
Test status
Simulation time 942988870 ps
CPU time 1.33 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 195244 kb
Host smart-89e52845-635a-4af7-bc11-448a1543c8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334116248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3334116248
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2512515104
Short name T472
Test name
Test status
Simulation time 82993357 ps
CPU time 1.09 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 197364 kb
Host smart-3a0c982b-3304-43ba-947e-db09c716d954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512515104 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2512515104
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.816293163
Short name T80
Test name
Test status
Simulation time 12466481 ps
CPU time 0.58 seconds
Started Mar 24 12:21:23 PM PDT 24
Finished Mar 24 12:21:24 PM PDT 24
Peak memory 191764 kb
Host smart-c40d18bc-9cdd-4ac1-b5ab-f41d40dad46a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816293163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.816293163
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3256197523
Short name T539
Test name
Test status
Simulation time 38854049 ps
CPU time 0.54 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 182496 kb
Host smart-a4e5adb8-195f-4d56-9734-e7ce9acbf186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256197523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3256197523
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1686053619
Short name T522
Test name
Test status
Simulation time 181921613 ps
CPU time 0.8 seconds
Started Mar 24 12:21:30 PM PDT 24
Finished Mar 24 12:21:31 PM PDT 24
Peak memory 193152 kb
Host smart-5fe926d0-91b8-4afe-830c-c15773db1c96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686053619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1686053619
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2370088336
Short name T526
Test name
Test status
Simulation time 29794244 ps
CPU time 1.66 seconds
Started Mar 24 12:21:10 PM PDT 24
Finished Mar 24 12:21:12 PM PDT 24
Peak memory 197388 kb
Host smart-4eafcfb1-e94b-424e-9e39-12fa81bc456d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370088336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2370088336
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.388087031
Short name T572
Test name
Test status
Simulation time 34496721 ps
CPU time 1.02 seconds
Started Mar 24 12:20:49 PM PDT 24
Finished Mar 24 12:20:51 PM PDT 24
Peak memory 196420 kb
Host smart-4866852e-645b-4fc8-b611-c20553c0455d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388087031 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.388087031
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2987536483
Short name T56
Test name
Test status
Simulation time 35388731 ps
CPU time 0.57 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 182544 kb
Host smart-ec4edc94-7136-451f-b22c-ac04ec5098ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987536483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2987536483
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1149347455
Short name T573
Test name
Test status
Simulation time 15912460 ps
CPU time 0.55 seconds
Started Mar 24 12:21:26 PM PDT 24
Finished Mar 24 12:21:27 PM PDT 24
Peak memory 182200 kb
Host smart-82fba7ea-05a9-43c6-9ea8-84364771c999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149347455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1149347455
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.25730708
Short name T548
Test name
Test status
Simulation time 25465104 ps
CPU time 0.77 seconds
Started Mar 24 12:21:36 PM PDT 24
Finished Mar 24 12:21:38 PM PDT 24
Peak memory 189836 kb
Host smart-f0a1939c-4fbe-439e-8c5b-84891e9f2615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25730708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_tim
er_same_csr_outstanding.25730708
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.834937595
Short name T520
Test name
Test status
Simulation time 332627937 ps
CPU time 2.99 seconds
Started Mar 24 12:21:26 PM PDT 24
Finished Mar 24 12:21:30 PM PDT 24
Peak memory 197232 kb
Host smart-8404217c-5d65-4a55-a315-9b2abba78511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834937595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.834937595
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3138283974
Short name T60
Test name
Test status
Simulation time 115644335 ps
CPU time 0.82 seconds
Started Mar 24 12:22:30 PM PDT 24
Finished Mar 24 12:22:31 PM PDT 24
Peak memory 192412 kb
Host smart-93707cb1-73a4-4878-a6a3-8ea2390cbd1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138283974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3138283974
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3921707909
Short name T468
Test name
Test status
Simulation time 196902720 ps
CPU time 2.44 seconds
Started Mar 24 12:22:12 PM PDT 24
Finished Mar 24 12:22:14 PM PDT 24
Peak memory 182740 kb
Host smart-8abf27ec-e22c-4e65-89aa-f9b67b949c44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921707909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3921707909
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2599645472
Short name T576
Test name
Test status
Simulation time 33897416 ps
CPU time 0.57 seconds
Started Mar 24 12:22:01 PM PDT 24
Finished Mar 24 12:22:07 PM PDT 24
Peak memory 181184 kb
Host smart-b9a8e2b1-4b1d-4b00-b81b-4eedd62ae8e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599645472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2599645472
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3939708144
Short name T492
Test name
Test status
Simulation time 28605747 ps
CPU time 0.64 seconds
Started Mar 24 12:22:27 PM PDT 24
Finished Mar 24 12:22:28 PM PDT 24
Peak memory 192400 kb
Host smart-d956157f-487d-4bd5-a884-808b673469d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939708144 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3939708144
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3370622154
Short name T505
Test name
Test status
Simulation time 16635904 ps
CPU time 0.52 seconds
Started Mar 24 12:22:46 PM PDT 24
Finished Mar 24 12:22:47 PM PDT 24
Peak memory 182212 kb
Host smart-41c28dd4-2871-49b6-96c8-5ae6831095e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370622154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3370622154
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3352166994
Short name T537
Test name
Test status
Simulation time 12684483 ps
CPU time 0.52 seconds
Started Mar 24 12:22:09 PM PDT 24
Finished Mar 24 12:22:10 PM PDT 24
Peak memory 181900 kb
Host smart-bf10f524-5342-409e-95c4-259f5e678aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352166994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3352166994
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4127185159
Short name T83
Test name
Test status
Simulation time 116444991 ps
CPU time 0.76 seconds
Started Mar 24 12:20:42 PM PDT 24
Finished Mar 24 12:20:42 PM PDT 24
Peak memory 190996 kb
Host smart-dbb1d25d-b43a-44b1-a22e-a9d3787695b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127185159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4127185159
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1736638057
Short name T498
Test name
Test status
Simulation time 50656227 ps
CPU time 2.34 seconds
Started Mar 24 12:20:42 PM PDT 24
Finished Mar 24 12:20:45 PM PDT 24
Peak memory 197524 kb
Host smart-43237094-ea30-4c8e-a409-bf557e984a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736638057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1736638057
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3200885480
Short name T99
Test name
Test status
Simulation time 96515078 ps
CPU time 1.29 seconds
Started Mar 24 12:20:40 PM PDT 24
Finished Mar 24 12:20:41 PM PDT 24
Peak memory 194944 kb
Host smart-8997c07e-7c8e-485c-8ead-c4f410fd0fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200885480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3200885480
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1152535513
Short name T511
Test name
Test status
Simulation time 30465494 ps
CPU time 0.56 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 182372 kb
Host smart-d28658c3-9489-43d9-ae5c-672b3a73d347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152535513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1152535513
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.539178189
Short name T579
Test name
Test status
Simulation time 27768089 ps
CPU time 0.59 seconds
Started Mar 24 12:21:30 PM PDT 24
Finished Mar 24 12:21:31 PM PDT 24
Peak memory 182904 kb
Host smart-1d7829a0-3aff-45d6-8b89-e3df4cff5e6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539178189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.539178189
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.141883044
Short name T475
Test name
Test status
Simulation time 144046240 ps
CPU time 0.6 seconds
Started Mar 24 12:21:36 PM PDT 24
Finished Mar 24 12:21:38 PM PDT 24
Peak memory 182476 kb
Host smart-751ce04b-47ef-48d1-8990-e6fe6f435789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141883044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.141883044
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2942477086
Short name T459
Test name
Test status
Simulation time 26964070 ps
CPU time 0.55 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:04 PM PDT 24
Peak memory 182424 kb
Host smart-4946807b-5e9e-41e5-a23e-65832aee56ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942477086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2942477086
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3003769239
Short name T464
Test name
Test status
Simulation time 74672444 ps
CPU time 0.55 seconds
Started Mar 24 12:21:16 PM PDT 24
Finished Mar 24 12:21:17 PM PDT 24
Peak memory 182132 kb
Host smart-71782e3a-bcbd-4257-a4a4-932414e447bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003769239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3003769239
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.529259209
Short name T465
Test name
Test status
Simulation time 84572702 ps
CPU time 0.55 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:05 PM PDT 24
Peak memory 181900 kb
Host smart-6cb48094-cdc5-41ee-8f65-d20dcb97ab40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529259209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.529259209
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1339952224
Short name T567
Test name
Test status
Simulation time 34061983 ps
CPU time 0.55 seconds
Started Mar 24 12:21:10 PM PDT 24
Finished Mar 24 12:21:11 PM PDT 24
Peak memory 181904 kb
Host smart-2eba6b57-da91-448f-a4fa-367f9645375a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339952224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1339952224
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2744823265
Short name T541
Test name
Test status
Simulation time 14081944 ps
CPU time 0.57 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 182492 kb
Host smart-96ed35f9-c8ef-45a2-9c5b-c17455c8e72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744823265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2744823265
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2521977903
Short name T490
Test name
Test status
Simulation time 17244914 ps
CPU time 0.55 seconds
Started Mar 24 12:21:06 PM PDT 24
Finished Mar 24 12:21:07 PM PDT 24
Peak memory 182480 kb
Host smart-8737bbeb-1512-4bbb-a9f0-bf16b0baf656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521977903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2521977903
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.744890913
Short name T530
Test name
Test status
Simulation time 14591054 ps
CPU time 0.55 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 182228 kb
Host smart-733e3025-1eca-48c0-8762-2ccd259e9670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744890913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.744890913
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1074274390
Short name T79
Test name
Test status
Simulation time 164051993 ps
CPU time 0.79 seconds
Started Mar 24 12:20:50 PM PDT 24
Finished Mar 24 12:20:51 PM PDT 24
Peak memory 192324 kb
Host smart-59c999dc-2677-4bf0-80f3-cedafe50e858
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074274390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1074274390
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4034540141
Short name T546
Test name
Test status
Simulation time 397749330 ps
CPU time 3.35 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:57 PM PDT 24
Peak memory 190968 kb
Host smart-1089b531-6f9a-417b-a064-ddff2c0fbbb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034540141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.4034540141
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1212765363
Short name T562
Test name
Test status
Simulation time 30461287 ps
CPU time 0.61 seconds
Started Mar 24 12:20:50 PM PDT 24
Finished Mar 24 12:20:51 PM PDT 24
Peak memory 182572 kb
Host smart-6bea9b77-ca94-4c05-bfac-7b4dc860eebe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212765363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1212765363
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2506315585
Short name T510
Test name
Test status
Simulation time 30007943 ps
CPU time 0.62 seconds
Started Mar 24 12:20:45 PM PDT 24
Finished Mar 24 12:20:46 PM PDT 24
Peak memory 193676 kb
Host smart-c9586ad9-dc70-47d9-8fea-15718f22a119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506315585 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2506315585
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2840732900
Short name T77
Test name
Test status
Simulation time 53163406 ps
CPU time 0.57 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:52 PM PDT 24
Peak memory 182552 kb
Host smart-85b58ddf-c95d-40d5-827b-6e2d0cbc7735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840732900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2840732900
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.460180595
Short name T474
Test name
Test status
Simulation time 18226686 ps
CPU time 0.58 seconds
Started Mar 24 12:21:10 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 182468 kb
Host smart-5a617455-2095-4a25-b841-015b2953b5f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460180595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.460180595
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1680977643
Short name T574
Test name
Test status
Simulation time 31342290 ps
CPU time 0.75 seconds
Started Mar 24 12:21:11 PM PDT 24
Finished Mar 24 12:21:12 PM PDT 24
Peak memory 193252 kb
Host smart-a0c47076-0abe-4181-b045-345f50570194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680977643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1680977643
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2679985497
Short name T504
Test name
Test status
Simulation time 45239390 ps
CPU time 2.06 seconds
Started Mar 24 12:20:50 PM PDT 24
Finished Mar 24 12:20:53 PM PDT 24
Peak memory 197464 kb
Host smart-9d152160-8b56-4e36-8b13-d6ad737111bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679985497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2679985497
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2457932456
Short name T566
Test name
Test status
Simulation time 392383790 ps
CPU time 1.37 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:53 PM PDT 24
Peak memory 195444 kb
Host smart-030c4e78-694f-4b7d-904e-ffb03cdebb98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457932456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2457932456
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.619462215
Short name T460
Test name
Test status
Simulation time 16949713 ps
CPU time 0.55 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 182516 kb
Host smart-58417946-d4da-453d-80f1-866186021fe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619462215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.619462215
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.852804175
Short name T458
Test name
Test status
Simulation time 31473775 ps
CPU time 0.56 seconds
Started Mar 24 12:21:07 PM PDT 24
Finished Mar 24 12:21:08 PM PDT 24
Peak memory 182480 kb
Host smart-841f2638-fb1c-4bd1-a51e-2fb0ba8e97b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852804175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.852804175
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2077789249
Short name T536
Test name
Test status
Simulation time 19210573 ps
CPU time 0.56 seconds
Started Mar 24 12:21:15 PM PDT 24
Finished Mar 24 12:21:16 PM PDT 24
Peak memory 181268 kb
Host smart-5fe71993-8e45-4549-bb42-e6e7de974e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077789249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2077789249
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1178000206
Short name T571
Test name
Test status
Simulation time 38465119 ps
CPU time 0.59 seconds
Started Mar 24 12:21:10 PM PDT 24
Finished Mar 24 12:21:11 PM PDT 24
Peak memory 181904 kb
Host smart-7f64dc37-7b59-45c3-afc3-1fd6c7ca1ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178000206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1178000206
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3274978948
Short name T551
Test name
Test status
Simulation time 15740557 ps
CPU time 0.59 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 182016 kb
Host smart-fcbef17a-5ae0-4a78-b114-ba0f46a35577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274978948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3274978948
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1043147081
Short name T456
Test name
Test status
Simulation time 92613124 ps
CPU time 0.54 seconds
Started Mar 24 12:21:07 PM PDT 24
Finished Mar 24 12:21:08 PM PDT 24
Peak memory 182452 kb
Host smart-dde346e3-2743-4d0a-9e6f-7cc51b3aef01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043147081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1043147081
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2224903063
Short name T544
Test name
Test status
Simulation time 29953910 ps
CPU time 0.54 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 182356 kb
Host smart-3d81caad-5202-4fa9-bb88-5a79c22d7df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224903063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2224903063
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2851117490
Short name T483
Test name
Test status
Simulation time 37550837 ps
CPU time 0.53 seconds
Started Mar 24 12:21:07 PM PDT 24
Finished Mar 24 12:21:08 PM PDT 24
Peak memory 181868 kb
Host smart-f37e758f-1a87-4775-9ec2-1ac331b43815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851117490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2851117490
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.723100933
Short name T489
Test name
Test status
Simulation time 12113148 ps
CPU time 0.54 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:05 PM PDT 24
Peak memory 181944 kb
Host smart-a79702f6-5ffb-4d65-833b-64b9ff1d8eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723100933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.723100933
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1242562657
Short name T525
Test name
Test status
Simulation time 64169822 ps
CPU time 0.55 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 182460 kb
Host smart-c6096a26-58fe-4014-92f8-069577abf5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242562657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1242562657
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4012299172
Short name T57
Test name
Test status
Simulation time 140031022 ps
CPU time 0.75 seconds
Started Mar 24 12:22:23 PM PDT 24
Finished Mar 24 12:22:24 PM PDT 24
Peak memory 182524 kb
Host smart-fde68734-ec2b-4837-b108-0f890f50bf66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012299172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.4012299172
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1454047089
Short name T70
Test name
Test status
Simulation time 90080513 ps
CPU time 3.15 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:13 PM PDT 24
Peak memory 190972 kb
Host smart-50c403e2-4712-495e-bab4-789adf89d2fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454047089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1454047089
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3336981374
Short name T540
Test name
Test status
Simulation time 48651333 ps
CPU time 0.54 seconds
Started Mar 24 12:22:37 PM PDT 24
Finished Mar 24 12:22:38 PM PDT 24
Peak memory 182524 kb
Host smart-4ffce904-69f4-46c2-96d5-37595c4ea317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336981374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3336981374
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3174368484
Short name T497
Test name
Test status
Simulation time 24772177 ps
CPU time 0.79 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 195160 kb
Host smart-0d203663-368e-4a91-af27-11f7e5bc9711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174368484 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3174368484
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2984441891
Short name T71
Test name
Test status
Simulation time 17382565 ps
CPU time 0.65 seconds
Started Mar 24 12:20:50 PM PDT 24
Finished Mar 24 12:20:51 PM PDT 24
Peak memory 192212 kb
Host smart-804afb92-41e4-49a9-a326-842505750e92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984441891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2984441891
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2961329354
Short name T549
Test name
Test status
Simulation time 15506697 ps
CPU time 0.56 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:55 PM PDT 24
Peak memory 181924 kb
Host smart-9914df35-b9bd-40ab-ab74-77d1fc21228d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961329354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2961329354
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2596140590
Short name T82
Test name
Test status
Simulation time 114541308 ps
CPU time 0.78 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:52 PM PDT 24
Peak memory 191580 kb
Host smart-1b7f5e6f-3cd0-489d-b147-80a9e2db42b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596140590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2596140590
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.115801195
Short name T45
Test name
Test status
Simulation time 488620935 ps
CPU time 2.01 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:56 PM PDT 24
Peak memory 197392 kb
Host smart-d8261723-cd0f-4d82-8216-9f5106bbadd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115801195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.115801195
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2223238447
Short name T516
Test name
Test status
Simulation time 1088208692 ps
CPU time 1.36 seconds
Started Mar 24 12:22:29 PM PDT 24
Finished Mar 24 12:22:31 PM PDT 24
Peak memory 195140 kb
Host smart-d357edcf-ac8d-4ace-b81e-3c976fed365a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223238447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2223238447
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3602748818
Short name T550
Test name
Test status
Simulation time 16828533 ps
CPU time 0.56 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:05 PM PDT 24
Peak memory 182532 kb
Host smart-a2521597-9f6d-4e05-9a99-7164724c28b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602748818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3602748818
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3390843045
Short name T543
Test name
Test status
Simulation time 18405270 ps
CPU time 0.56 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:05 PM PDT 24
Peak memory 182428 kb
Host smart-bd065d38-fce1-4f8e-99b1-226bea7e857e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390843045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3390843045
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2571911412
Short name T569
Test name
Test status
Simulation time 28674246 ps
CPU time 0.54 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:05 PM PDT 24
Peak memory 182484 kb
Host smart-8d595ea7-3721-41db-ad8a-5b980ea2abbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571911412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2571911412
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1343147468
Short name T481
Test name
Test status
Simulation time 26948728 ps
CPU time 0.5 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 181800 kb
Host smart-3c9efc8b-b1bb-42fa-9b3b-89895657be7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343147468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1343147468
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2669162689
Short name T478
Test name
Test status
Simulation time 14899778 ps
CPU time 0.59 seconds
Started Mar 24 12:21:12 PM PDT 24
Finished Mar 24 12:21:14 PM PDT 24
Peak memory 182460 kb
Host smart-3377868e-93b7-4b8f-8469-b6906ae13dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669162689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2669162689
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2546962029
Short name T486
Test name
Test status
Simulation time 25890964 ps
CPU time 0.5 seconds
Started Mar 24 12:21:10 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 181924 kb
Host smart-57fb4170-e3f9-4355-a675-a111227ff643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546962029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2546962029
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3871906440
Short name T470
Test name
Test status
Simulation time 17114849 ps
CPU time 0.54 seconds
Started Mar 24 12:21:24 PM PDT 24
Finished Mar 24 12:21:25 PM PDT 24
Peak memory 182388 kb
Host smart-e4542659-1092-487d-96b8-63b3a2595654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871906440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3871906440
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2347054150
Short name T513
Test name
Test status
Simulation time 15818609 ps
CPU time 0.52 seconds
Started Mar 24 12:21:13 PM PDT 24
Finished Mar 24 12:21:14 PM PDT 24
Peak memory 182088 kb
Host smart-2b08d0fa-3394-4fed-a548-7c4daf30bc97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347054150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2347054150
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1026361809
Short name T557
Test name
Test status
Simulation time 33150622 ps
CPU time 0.59 seconds
Started Mar 24 12:21:20 PM PDT 24
Finished Mar 24 12:21:22 PM PDT 24
Peak memory 181080 kb
Host smart-5ef68f5e-2be8-48f3-bd62-b5a316349768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026361809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1026361809
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4181780720
Short name T476
Test name
Test status
Simulation time 11678058 ps
CPU time 0.52 seconds
Started Mar 24 12:21:24 PM PDT 24
Finished Mar 24 12:21:25 PM PDT 24
Peak memory 182420 kb
Host smart-8a238e4d-20e1-4421-8b55-eb868e44d2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181780720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4181780720
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2058259974
Short name T523
Test name
Test status
Simulation time 67816628 ps
CPU time 0.7 seconds
Started Mar 24 12:20:46 PM PDT 24
Finished Mar 24 12:20:47 PM PDT 24
Peak memory 194560 kb
Host smart-f6a35deb-2061-432f-a462-1d89f051fe7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058259974 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2058259974
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.329256198
Short name T96
Test name
Test status
Simulation time 55213630 ps
CPU time 0.59 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 181724 kb
Host smart-30cd1630-3b5f-4e4f-9be5-7559bb89082d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329256198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.329256198
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2878775393
Short name T527
Test name
Test status
Simulation time 12215219 ps
CPU time 0.55 seconds
Started Mar 24 12:20:50 PM PDT 24
Finished Mar 24 12:20:51 PM PDT 24
Peak memory 181888 kb
Host smart-dbe7709c-3923-4f4c-af85-7d3861fd33c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878775393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2878775393
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3718707999
Short name T43
Test name
Test status
Simulation time 296518538 ps
CPU time 0.83 seconds
Started Mar 24 12:20:50 PM PDT 24
Finished Mar 24 12:20:51 PM PDT 24
Peak memory 193096 kb
Host smart-7d5d1027-2311-4d95-8c13-b07ec49655aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718707999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3718707999
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2422036417
Short name T532
Test name
Test status
Simulation time 66029962 ps
CPU time 1.54 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:07 PM PDT 24
Peak memory 197604 kb
Host smart-f6aef87b-c27c-405d-8cfc-d8a0147e7938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422036417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2422036417
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.229399484
Short name T482
Test name
Test status
Simulation time 147795195 ps
CPU time 1.53 seconds
Started Mar 24 12:20:50 PM PDT 24
Finished Mar 24 12:20:52 PM PDT 24
Peak memory 195236 kb
Host smart-44a4e445-26b0-4c70-a311-2581d74db9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229399484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.229399484
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2328151674
Short name T501
Test name
Test status
Simulation time 187284807 ps
CPU time 0.86 seconds
Started Mar 24 12:20:44 PM PDT 24
Finished Mar 24 12:20:45 PM PDT 24
Peak memory 197016 kb
Host smart-e7885e00-066a-4fe8-8770-b60a67794a3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328151674 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2328151674
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4010094305
Short name T578
Test name
Test status
Simulation time 12766000 ps
CPU time 0.55 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:55 PM PDT 24
Peak memory 181924 kb
Host smart-cf2734a5-cffe-4124-94ce-d3f8ceeeda1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010094305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4010094305
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3224649239
Short name T542
Test name
Test status
Simulation time 105072479 ps
CPU time 0.71 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 193020 kb
Host smart-5ca417f7-1e21-4b24-aa0c-f555980f24c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224649239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3224649239
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1002198215
Short name T514
Test name
Test status
Simulation time 54606323 ps
CPU time 0.8 seconds
Started Mar 24 12:22:22 PM PDT 24
Finished Mar 24 12:22:23 PM PDT 24
Peak memory 195196 kb
Host smart-8596340d-9774-47a7-9016-2be9f678e326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002198215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1002198215
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3922449737
Short name T570
Test name
Test status
Simulation time 87062302 ps
CPU time 1.12 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:56 PM PDT 24
Peak memory 194944 kb
Host smart-e74c3b03-ee37-449a-a607-fa257ff0833e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922449737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3922449737
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3727737605
Short name T507
Test name
Test status
Simulation time 48260982 ps
CPU time 1.19 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:53 PM PDT 24
Peak memory 197480 kb
Host smart-fc833821-4910-460f-833a-1745e7a70c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727737605 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3727737605
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3654481952
Short name T76
Test name
Test status
Simulation time 12474180 ps
CPU time 0.58 seconds
Started Mar 24 12:22:22 PM PDT 24
Finished Mar 24 12:22:23 PM PDT 24
Peak memory 182496 kb
Host smart-068d68ca-3f31-4f3a-bb73-44ff7cda1fa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654481952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3654481952
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1389000536
Short name T487
Test name
Test status
Simulation time 24868634 ps
CPU time 0.57 seconds
Started Mar 24 12:20:50 PM PDT 24
Finished Mar 24 12:20:51 PM PDT 24
Peak memory 182400 kb
Host smart-1c240c37-58f4-4ab0-84a3-bb32b9fb94f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389000536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1389000536
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.99217267
Short name T85
Test name
Test status
Simulation time 34839657 ps
CPU time 0.79 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:52 PM PDT 24
Peak memory 193404 kb
Host smart-fce42709-0285-453d-afe5-52c415f1cde8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99217267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_time
r_same_csr_outstanding.99217267
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.857737214
Short name T547
Test name
Test status
Simulation time 36579290 ps
CPU time 1.74 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:56 PM PDT 24
Peak memory 197252 kb
Host smart-604216f8-ee91-456c-8d68-e7c342aaed5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857737214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.857737214
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4031753144
Short name T44
Test name
Test status
Simulation time 182115181 ps
CPU time 0.79 seconds
Started Mar 24 12:20:44 PM PDT 24
Finished Mar 24 12:20:45 PM PDT 24
Peak memory 193344 kb
Host smart-0e1af221-ed90-4328-a355-42111f7230df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031753144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.4031753144
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1607817127
Short name T32
Test name
Test status
Simulation time 53274421 ps
CPU time 0.81 seconds
Started Mar 24 12:20:48 PM PDT 24
Finished Mar 24 12:20:49 PM PDT 24
Peak memory 197068 kb
Host smart-f0043731-0056-41ec-9412-a16575bd19a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607817127 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1607817127
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1516977489
Short name T517
Test name
Test status
Simulation time 16063548 ps
CPU time 0.55 seconds
Started Mar 24 12:20:58 PM PDT 24
Finished Mar 24 12:20:59 PM PDT 24
Peak memory 182452 kb
Host smart-ebe14c74-1ffb-426d-a631-abd78bb97f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516977489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1516977489
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1244134233
Short name T471
Test name
Test status
Simulation time 33898402 ps
CPU time 0.61 seconds
Started Mar 24 12:21:01 PM PDT 24
Finished Mar 24 12:21:01 PM PDT 24
Peak memory 181920 kb
Host smart-2290530b-044e-4804-9604-abf5ad6c22a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244134233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1244134233
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1808729319
Short name T538
Test name
Test status
Simulation time 163322077 ps
CPU time 0.84 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 191576 kb
Host smart-558ad6b7-5189-4329-b160-d8ff38e065a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808729319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1808729319
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2039873941
Short name T502
Test name
Test status
Simulation time 122023166 ps
CPU time 2.05 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:57 PM PDT 24
Peak memory 197452 kb
Host smart-2ba09a9c-6841-4673-a41e-e1e1ff5f82d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039873941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2039873941
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4200970331
Short name T46
Test name
Test status
Simulation time 368724184 ps
CPU time 1.09 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 194676 kb
Host smart-5e161e42-db22-4524-99c1-e8780f84903e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200970331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4200970331
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2050079763
Short name T469
Test name
Test status
Simulation time 45600753 ps
CPU time 0.77 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 195208 kb
Host smart-82ea71bd-f590-4718-af46-95e6916ef4b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050079763 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2050079763
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.714040198
Short name T534
Test name
Test status
Simulation time 15686739 ps
CPU time 0.61 seconds
Started Mar 24 12:21:36 PM PDT 24
Finished Mar 24 12:21:38 PM PDT 24
Peak memory 180760 kb
Host smart-d2a9b976-c1e3-45e1-bb53-d691263c2571
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714040198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.714040198
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1161959113
Short name T463
Test name
Test status
Simulation time 21062094 ps
CPU time 0.56 seconds
Started Mar 24 12:21:22 PM PDT 24
Finished Mar 24 12:21:22 PM PDT 24
Peak memory 182524 kb
Host smart-749fb85d-985f-4bdf-8169-2a75e70b1b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161959113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1161959113
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1511688610
Short name T580
Test name
Test status
Simulation time 16264258 ps
CPU time 0.67 seconds
Started Mar 24 12:20:49 PM PDT 24
Finished Mar 24 12:20:50 PM PDT 24
Peak memory 191928 kb
Host smart-cab24866-6591-44aa-8a51-8ccdaf5e26d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511688610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1511688610
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1434374431
Short name T466
Test name
Test status
Simulation time 308018980 ps
CPU time 2.6 seconds
Started Mar 24 12:21:22 PM PDT 24
Finished Mar 24 12:21:25 PM PDT 24
Peak memory 197492 kb
Host smart-086632b3-c501-457d-8230-862a5c6b6434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434374431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1434374431
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2476891392
Short name T555
Test name
Test status
Simulation time 1442214871 ps
CPU time 1.44 seconds
Started Mar 24 12:21:05 PM PDT 24
Finished Mar 24 12:21:07 PM PDT 24
Peak memory 194528 kb
Host smart-a4981914-706c-4952-94e1-b881e8377067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476891392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2476891392
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.775637580
Short name T142
Test name
Test status
Simulation time 202761732512 ps
CPU time 317.95 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 182720 kb
Host smart-ee876e9f-4c4f-48e8-bf9f-74bfef196dea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775637580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.775637580
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3047624908
Short name T377
Test name
Test status
Simulation time 194570789637 ps
CPU time 86.6 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:45:42 PM PDT 24
Peak memory 182648 kb
Host smart-98cfcd48-57fa-4157-bbe8-007a49702fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047624908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3047624908
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1130162890
Short name T409
Test name
Test status
Simulation time 37803255691 ps
CPU time 40.98 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:53 PM PDT 24
Peak memory 182692 kb
Host smart-543a0cba-6e10-4a14-94e6-dbaeadf092bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130162890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1130162890
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2928378232
Short name T359
Test name
Test status
Simulation time 321936895976 ps
CPU time 284.96 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 12:49:14 PM PDT 24
Peak memory 182708 kb
Host smart-fd161240-a701-4663-903d-e22dc120198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928378232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2928378232
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2881576171
Short name T20
Test name
Test status
Simulation time 1124249054 ps
CPU time 0.9 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:16 PM PDT 24
Peak memory 214272 kb
Host smart-f81eff02-ccfa-41c9-a730-35819508c433
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881576171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2881576171
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.68351662
Short name T365
Test name
Test status
Simulation time 180482527 ps
CPU time 0.56 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 182620 kb
Host smart-10929a6f-312e-4812-a65b-ba8879ee32a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68351662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.68351662
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2146651362
Short name T418
Test name
Test status
Simulation time 303182981306 ps
CPU time 191.16 seconds
Started Mar 24 12:44:18 PM PDT 24
Finished Mar 24 12:47:29 PM PDT 24
Peak memory 182708 kb
Host smart-ffa69316-4c78-4a1a-93d8-2b7fd417a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146651362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2146651362
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.362065356
Short name T164
Test name
Test status
Simulation time 214778615991 ps
CPU time 515.06 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 12:53:04 PM PDT 24
Peak memory 193268 kb
Host smart-2ae733b2-41f2-4e55-ae4e-e8812aef7f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362065356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.362065356
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.348206001
Short name T384
Test name
Test status
Simulation time 3546732887 ps
CPU time 9.12 seconds
Started Mar 24 12:44:37 PM PDT 24
Finished Mar 24 12:44:46 PM PDT 24
Peak memory 182600 kb
Host smart-5cbd7e53-3325-43d0-8996-b60920294d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348206001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.348206001
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2945268905
Short name T228
Test name
Test status
Simulation time 506459666593 ps
CPU time 597.3 seconds
Started Mar 24 12:45:05 PM PDT 24
Finished Mar 24 12:55:02 PM PDT 24
Peak memory 190796 kb
Host smart-7d99ce89-06e2-48dd-a8de-a1ce06735103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945268905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2945268905
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2358955018
Short name T299
Test name
Test status
Simulation time 93022420940 ps
CPU time 118.61 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:47:08 PM PDT 24
Peak memory 190796 kb
Host smart-d9ec8e76-05fe-444f-82eb-c3cc4e793a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358955018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2358955018
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1648117190
Short name T69
Test name
Test status
Simulation time 1484360222120 ps
CPU time 485.78 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:53:13 PM PDT 24
Peak memory 190868 kb
Host smart-9650311e-6053-401e-bd80-1cbacbab2a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648117190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1648117190
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3026379165
Short name T302
Test name
Test status
Simulation time 381360664472 ps
CPU time 216.13 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 190804 kb
Host smart-01408c59-fafa-4d94-92ca-f6fd632b98d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026379165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3026379165
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3870070564
Short name T442
Test name
Test status
Simulation time 142746187280 ps
CPU time 742.33 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 190840 kb
Host smart-9e587a6e-0139-4b66-ab7a-ec83ac1f2743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870070564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3870070564
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2094061970
Short name T290
Test name
Test status
Simulation time 141320602324 ps
CPU time 132.38 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 12:47:29 PM PDT 24
Peak memory 190904 kb
Host smart-1eb27191-bdd2-45a8-9656-2d0bfb5ec159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094061970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2094061970
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3360250458
Short name T188
Test name
Test status
Simulation time 2850953820513 ps
CPU time 618.1 seconds
Started Mar 24 12:44:47 PM PDT 24
Finished Mar 24 12:55:06 PM PDT 24
Peak memory 182656 kb
Host smart-592c0422-c7e6-4a7a-89f7-bf2108d860ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360250458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3360250458
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1156105106
Short name T356
Test name
Test status
Simulation time 722976100546 ps
CPU time 262.13 seconds
Started Mar 24 12:44:34 PM PDT 24
Finished Mar 24 12:48:56 PM PDT 24
Peak memory 182652 kb
Host smart-cef52407-e9a8-45f2-8e5a-52d5b38acf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156105106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1156105106
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2517005383
Short name T92
Test name
Test status
Simulation time 471875402486 ps
CPU time 175.54 seconds
Started Mar 24 12:44:25 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 194292 kb
Host smart-068a9b4b-fe5b-44ca-beac-cf7d9f0cb506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517005383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2517005383
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2490292937
Short name T263
Test name
Test status
Simulation time 21510663106 ps
CPU time 34.04 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:45:47 PM PDT 24
Peak memory 190908 kb
Host smart-2e3bf9b6-7d55-4e6c-8ed9-07d378354c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490292937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2490292937
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3336243054
Short name T281
Test name
Test status
Simulation time 510147466932 ps
CPU time 1730.14 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 190904 kb
Host smart-fc308834-c4e5-4147-a04c-8fa0406eacc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336243054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3336243054
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3685657436
Short name T2
Test name
Test status
Simulation time 52021058900 ps
CPU time 56.86 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 12:46:03 PM PDT 24
Peak memory 182712 kb
Host smart-4c8045bc-7fa6-4d5a-bdc4-5dcac8fc1dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685657436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3685657436
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2936593370
Short name T332
Test name
Test status
Simulation time 60517573275 ps
CPU time 48.55 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 12:45:55 PM PDT 24
Peak memory 182752 kb
Host smart-83153231-1039-430a-81dc-78d9e088890f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936593370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2936593370
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.367309209
Short name T200
Test name
Test status
Simulation time 359201079287 ps
CPU time 467.94 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 12:53:04 PM PDT 24
Peak memory 190816 kb
Host smart-946e05da-2cde-4f6e-a777-e227e5235f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367309209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.367309209
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1353868405
Short name T324
Test name
Test status
Simulation time 56346679035 ps
CPU time 65.58 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:46:15 PM PDT 24
Peak memory 190908 kb
Host smart-50503800-89b3-4db4-a3cf-caae73dd3caf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353868405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1353868405
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3312049533
Short name T209
Test name
Test status
Simulation time 260354848463 ps
CPU time 555.22 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:54:20 PM PDT 24
Peak memory 190912 kb
Host smart-18f3f332-7795-4792-b668-754aaf862c61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312049533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3312049533
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1832191537
Short name T363
Test name
Test status
Simulation time 330423129821 ps
CPU time 141.83 seconds
Started Mar 24 12:44:30 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 182652 kb
Host smart-11d2a52a-1f44-41a2-8d79-1508c6420cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832191537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1832191537
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3998291445
Short name T273
Test name
Test status
Simulation time 62549817808 ps
CPU time 105.67 seconds
Started Mar 24 12:44:27 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 190888 kb
Host smart-a526fa81-7339-454b-a422-722a643a2b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998291445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3998291445
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.24348041
Short name T171
Test name
Test status
Simulation time 1168378629705 ps
CPU time 840.11 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 12:58:24 PM PDT 24
Peak memory 194624 kb
Host smart-b2d95e64-ee76-4179-99ca-a7b3773eeb0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24348041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.24348041
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.3379147307
Short name T230
Test name
Test status
Simulation time 396450301316 ps
CPU time 1762.17 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 01:14:33 PM PDT 24
Peak memory 191228 kb
Host smart-359c1930-a723-46a9-bdb7-413fade69b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379147307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3379147307
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2711664507
Short name T198
Test name
Test status
Simulation time 167407662576 ps
CPU time 151.4 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:47:47 PM PDT 24
Peak memory 190912 kb
Host smart-ff5db2ca-21ca-48e8-a5e6-6a168fae1b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711664507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2711664507
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1417127011
Short name T177
Test name
Test status
Simulation time 810456416319 ps
CPU time 1092.16 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 01:03:23 PM PDT 24
Peak memory 190896 kb
Host smart-6b69235c-4fb5-429d-b001-39e778541b28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417127011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1417127011
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2014926072
Short name T282
Test name
Test status
Simulation time 13498326982 ps
CPU time 20.79 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:45:35 PM PDT 24
Peak memory 182656 kb
Host smart-99e23a5e-956c-48a3-9b5c-ec05d75bfd0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014926072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2014926072
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3976414979
Short name T203
Test name
Test status
Simulation time 1140090747870 ps
CPU time 658.64 seconds
Started Mar 24 12:45:21 PM PDT 24
Finished Mar 24 12:56:20 PM PDT 24
Peak memory 190824 kb
Host smart-e446a4fb-d968-4e9c-8e03-f552d8b034d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976414979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3976414979
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3719457875
Short name T450
Test name
Test status
Simulation time 114406485578 ps
CPU time 1710.27 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 182708 kb
Host smart-88257c46-94a7-4096-a6b7-497776d8ee2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719457875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3719457875
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3279528647
Short name T253
Test name
Test status
Simulation time 189910371755 ps
CPU time 774.58 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:58:15 PM PDT 24
Peak memory 190868 kb
Host smart-be03abbd-4ecc-4bad-9442-92b61488884c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279528647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3279528647
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1216299115
Short name T154
Test name
Test status
Simulation time 530368256461 ps
CPU time 276.6 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:49:45 PM PDT 24
Peak memory 190844 kb
Host smart-c96f796a-f070-45f9-8a0e-1e905a4c763d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216299115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1216299115
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.712103811
Short name T115
Test name
Test status
Simulation time 195564794679 ps
CPU time 254.18 seconds
Started Mar 24 12:44:27 PM PDT 24
Finished Mar 24 12:48:41 PM PDT 24
Peak memory 190900 kb
Host smart-92b0b313-4030-42a4-9908-72802d715b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712103811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.712103811
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.897876783
Short name T392
Test name
Test status
Simulation time 22842488 ps
CPU time 0.6 seconds
Started Mar 24 12:44:51 PM PDT 24
Finished Mar 24 12:44:52 PM PDT 24
Peak memory 182376 kb
Host smart-245f198d-7ce6-405b-94c2-45e512ab1b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897876783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.897876783
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.2639910052
Short name T152
Test name
Test status
Simulation time 585672276961 ps
CPU time 318.74 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 190892 kb
Host smart-6450b98a-aeba-4e5b-a8bc-910c799fbdfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639910052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2639910052
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1839390092
Short name T247
Test name
Test status
Simulation time 223899820604 ps
CPU time 439.46 seconds
Started Mar 24 12:45:19 PM PDT 24
Finished Mar 24 12:52:39 PM PDT 24
Peak memory 190904 kb
Host smart-013474cc-d316-4909-b4af-82a7ee43ea25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839390092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1839390092
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2756405654
Short name T260
Test name
Test status
Simulation time 47550170239 ps
CPU time 73.68 seconds
Started Mar 24 12:45:21 PM PDT 24
Finished Mar 24 12:46:35 PM PDT 24
Peak memory 193132 kb
Host smart-dbb3e0fc-e8a3-4693-909c-5dcb3c16fcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756405654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2756405654
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3255313484
Short name T6
Test name
Test status
Simulation time 287510756002 ps
CPU time 323.65 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:50:33 PM PDT 24
Peak memory 190904 kb
Host smart-7c2a7acf-b93c-4b6e-9480-57fcafaf37cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255313484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3255313484
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.767057332
Short name T437
Test name
Test status
Simulation time 93346804059 ps
CPU time 208.95 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:48:36 PM PDT 24
Peak memory 190840 kb
Host smart-7abc98a7-e430-4854-aab5-4cba14a02685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767057332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.767057332
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1679308547
Short name T319
Test name
Test status
Simulation time 94814326618 ps
CPU time 80.75 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:46:33 PM PDT 24
Peak memory 190756 kb
Host smart-31589e79-7348-4b11-8184-a0f6ef29e5e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679308547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1679308547
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3162202486
Short name T26
Test name
Test status
Simulation time 206030088745 ps
CPU time 101 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:47:01 PM PDT 24
Peak memory 190892 kb
Host smart-19d0f6f0-c166-4c86-a9cb-a38b1b79c78a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162202486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3162202486
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1383777317
Short name T194
Test name
Test status
Simulation time 291146512950 ps
CPU time 278.24 seconds
Started Mar 24 12:44:55 PM PDT 24
Finished Mar 24 12:49:34 PM PDT 24
Peak memory 182724 kb
Host smart-ac1692a4-22ea-412a-a1ea-538d8b1c65b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383777317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1383777317
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2669594538
Short name T372
Test name
Test status
Simulation time 164280016286 ps
CPU time 126.68 seconds
Started Mar 24 12:44:22 PM PDT 24
Finished Mar 24 12:46:29 PM PDT 24
Peak memory 182716 kb
Host smart-951f6508-9665-4473-acf7-849f1f88ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669594538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2669594538
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.85890871
Short name T114
Test name
Test status
Simulation time 164685362994 ps
CPU time 454.12 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 12:51:58 PM PDT 24
Peak memory 190912 kb
Host smart-2c03be45-603d-4845-8453-c1227161f186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85890871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.85890871
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4285260472
Short name T364
Test name
Test status
Simulation time 71257223 ps
CPU time 0.64 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:44:29 PM PDT 24
Peak memory 182448 kb
Host smart-cba07aeb-4ec8-41f3-b6f5-2929673ee920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285260472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4285260472
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1568151281
Short name T39
Test name
Test status
Simulation time 21757991053 ps
CPU time 155.94 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 12:47:00 PM PDT 24
Peak memory 197332 kb
Host smart-e4eec9ab-c1c4-4b34-8143-3ff0e0ba4d90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568151281 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.1568151281
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.2552704982
Short name T132
Test name
Test status
Simulation time 156401533098 ps
CPU time 577.35 seconds
Started Mar 24 12:45:22 PM PDT 24
Finished Mar 24 12:54:59 PM PDT 24
Peak memory 190872 kb
Host smart-a815ee51-cdf4-4f4e-9351-231f3d6c32a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552704982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2552704982
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1004808723
Short name T285
Test name
Test status
Simulation time 198116316196 ps
CPU time 662.66 seconds
Started Mar 24 12:45:00 PM PDT 24
Finished Mar 24 12:56:03 PM PDT 24
Peak memory 190904 kb
Host smart-3e65476c-1129-42c7-8396-cf805f56a8c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004808723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1004808723
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.28365720
Short name T229
Test name
Test status
Simulation time 56557045261 ps
CPU time 98.39 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 190900 kb
Host smart-1079f53e-6cf0-4231-9a10-76d1f4f518d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28365720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.28365720
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.193608553
Short name T336
Test name
Test status
Simulation time 227368269762 ps
CPU time 132.65 seconds
Started Mar 24 12:45:21 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 190924 kb
Host smart-929b2406-9b80-4ecc-b298-caf0daa785a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193608553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.193608553
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.4285759676
Short name T242
Test name
Test status
Simulation time 220596024799 ps
CPU time 82.2 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:46:31 PM PDT 24
Peak memory 182716 kb
Host smart-dfde0907-12be-4b45-94ce-4d2b92b03f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285759676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4285759676
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3941983545
Short name T121
Test name
Test status
Simulation time 308365591129 ps
CPU time 200.68 seconds
Started Mar 24 12:45:24 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 190872 kb
Host smart-9ae74f09-cc39-4cf1-8d40-3a79851225ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941983545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3941983545
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4227945443
Short name T202
Test name
Test status
Simulation time 605768960348 ps
CPU time 1279.31 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 190816 kb
Host smart-9cefaaef-e1de-423e-add6-6155bc47b7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227945443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4227945443
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3802990233
Short name T296
Test name
Test status
Simulation time 1974821633045 ps
CPU time 579.86 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:54:48 PM PDT 24
Peak memory 190904 kb
Host smart-bf1bc0b3-9a7b-4150-b082-8c5687fc6b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802990233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3802990233
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.114281330
Short name T68
Test name
Test status
Simulation time 285788602302 ps
CPU time 479.7 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 12:52:43 PM PDT 24
Peak memory 182744 kb
Host smart-042776e3-8756-42f1-8774-df3382b2f21c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114281330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.114281330
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3066056654
Short name T423
Test name
Test status
Simulation time 122541929603 ps
CPU time 193.69 seconds
Started Mar 24 12:44:35 PM PDT 24
Finished Mar 24 12:47:49 PM PDT 24
Peak memory 182704 kb
Host smart-8b7a806b-2c7a-4ff4-aba7-c62e14e6074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066056654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3066056654
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1096271783
Short name T174
Test name
Test status
Simulation time 111360188665 ps
CPU time 18.8 seconds
Started Mar 24 12:44:42 PM PDT 24
Finished Mar 24 12:45:07 PM PDT 24
Peak memory 190900 kb
Host smart-090c642f-539b-457a-9ec5-ea8c0686e88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096271783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1096271783
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.781169842
Short name T162
Test name
Test status
Simulation time 67941723150 ps
CPU time 115.1 seconds
Started Mar 24 12:44:37 PM PDT 24
Finished Mar 24 12:46:32 PM PDT 24
Peak memory 190912 kb
Host smart-6c008f15-ee0a-48be-b98c-9736b671d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781169842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.781169842
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.862339364
Short name T55
Test name
Test status
Simulation time 62819308383 ps
CPU time 281 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:49:54 PM PDT 24
Peak memory 205520 kb
Host smart-f31405a3-eb86-489d-9a5f-feaac4ddbbd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862339364 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.862339364
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.784116747
Short name T218
Test name
Test status
Simulation time 123136576711 ps
CPU time 81.35 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:46:32 PM PDT 24
Peak memory 190912 kb
Host smart-40f4cd77-4e38-4ed3-a1ef-8256b0ea1090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784116747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.784116747
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2530134858
Short name T258
Test name
Test status
Simulation time 115726575400 ps
CPU time 337 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:50:40 PM PDT 24
Peak memory 190836 kb
Host smart-ae35b820-2ce1-4948-889d-4ee6ae081677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530134858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2530134858
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.693792935
Short name T424
Test name
Test status
Simulation time 64218996035 ps
CPU time 50.71 seconds
Started Mar 24 12:45:18 PM PDT 24
Finished Mar 24 12:46:09 PM PDT 24
Peak memory 190844 kb
Host smart-63f5c76d-686c-4229-a9de-4f9f62ee4586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693792935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.693792935
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3255223134
Short name T157
Test name
Test status
Simulation time 89728037747 ps
CPU time 250.09 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 12:49:27 PM PDT 24
Peak memory 190876 kb
Host smart-a2736cd0-c591-4b8a-bf8f-9b2317d712ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255223134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3255223134
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3316555892
Short name T272
Test name
Test status
Simulation time 29343486221 ps
CPU time 48.73 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:45:52 PM PDT 24
Peak memory 182620 kb
Host smart-87fa34e2-c133-4712-92be-b7c63669010d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316555892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3316555892
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2933433706
Short name T248
Test name
Test status
Simulation time 81524341042 ps
CPU time 128.32 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:47:23 PM PDT 24
Peak memory 193184 kb
Host smart-5b309447-991c-40d6-afca-4b8b4e319304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933433706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2933433706
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1181184362
Short name T185
Test name
Test status
Simulation time 1673844690030 ps
CPU time 431.67 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:52:27 PM PDT 24
Peak memory 190900 kb
Host smart-57956ea6-7e6d-4bd4-a2f3-7076ebbebb0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181184362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1181184362
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1529851693
Short name T283
Test name
Test status
Simulation time 381381152017 ps
CPU time 186.89 seconds
Started Mar 24 12:44:38 PM PDT 24
Finished Mar 24 12:47:45 PM PDT 24
Peak memory 182664 kb
Host smart-dade5107-b07c-4118-ba96-0f6a2f4ae9f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529851693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1529851693
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2589029082
Short name T380
Test name
Test status
Simulation time 147910764918 ps
CPU time 210.76 seconds
Started Mar 24 12:44:56 PM PDT 24
Finished Mar 24 12:48:28 PM PDT 24
Peak memory 182716 kb
Host smart-e1bbebdb-2062-4811-8ebc-e633ef112d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589029082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2589029082
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.4005138565
Short name T397
Test name
Test status
Simulation time 613611598 ps
CPU time 1.32 seconds
Started Mar 24 12:44:42 PM PDT 24
Finished Mar 24 12:44:43 PM PDT 24
Peak memory 190820 kb
Host smart-b38492ac-9a08-4817-9330-63b798230e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005138565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.4005138565
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/162.rv_timer_random.2854350209
Short name T428
Test name
Test status
Simulation time 89791358841 ps
CPU time 535.33 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:54:02 PM PDT 24
Peak memory 190816 kb
Host smart-edb527b1-421d-4b2b-8bf8-0b1f7861b541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854350209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2854350209
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1624921471
Short name T315
Test name
Test status
Simulation time 244836939934 ps
CPU time 299.8 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:50:07 PM PDT 24
Peak memory 190864 kb
Host smart-fa2874e1-dc38-4085-a8bc-85a46d8694c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624921471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1624921471
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3339652179
Short name T234
Test name
Test status
Simulation time 38254254460 ps
CPU time 79.99 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:46:34 PM PDT 24
Peak memory 190860 kb
Host smart-d28d34ff-8fbc-4fd3-bf7c-2acfa1dc7c8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339652179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3339652179
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1408204971
Short name T225
Test name
Test status
Simulation time 161924609803 ps
CPU time 116.77 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:47:10 PM PDT 24
Peak memory 190804 kb
Host smart-9d850913-e2ef-4fe5-a007-56677df4fafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408204971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1408204971
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3018696165
Short name T191
Test name
Test status
Simulation time 90714472424 ps
CPU time 232.76 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 190808 kb
Host smart-a1a3edfd-b424-49ce-9275-c41764861787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018696165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3018696165
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1160328785
Short name T261
Test name
Test status
Simulation time 78579152717 ps
CPU time 581.35 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:54:48 PM PDT 24
Peak memory 190812 kb
Host smart-09ad7722-2a98-439a-b491-25991bb5042a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160328785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1160328785
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1768865243
Short name T267
Test name
Test status
Simulation time 235976388884 ps
CPU time 227.37 seconds
Started Mar 24 12:44:38 PM PDT 24
Finished Mar 24 12:48:31 PM PDT 24
Peak memory 182668 kb
Host smart-803ef60b-4962-47d9-ac7d-aac2b0a1c0bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768865243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1768865243
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2621986507
Short name T90
Test name
Test status
Simulation time 392115550129 ps
CPU time 177.19 seconds
Started Mar 24 12:44:34 PM PDT 24
Finished Mar 24 12:47:31 PM PDT 24
Peak memory 182604 kb
Host smart-f0745071-b8f5-4fac-b136-1cafba89dacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621986507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2621986507
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.4172024786
Short name T113
Test name
Test status
Simulation time 289996587382 ps
CPU time 165.18 seconds
Started Mar 24 12:44:19 PM PDT 24
Finished Mar 24 12:47:04 PM PDT 24
Peak memory 190900 kb
Host smart-87ac83fe-dfdd-480c-b263-9c3cb692d67a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172024786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4172024786
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2102120498
Short name T345
Test name
Test status
Simulation time 280851961 ps
CPU time 2.5 seconds
Started Mar 24 12:44:25 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 190800 kb
Host smart-01cfd957-7944-4232-80bf-59d4e6f6effd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102120498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2102120498
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.497745224
Short name T238
Test name
Test status
Simulation time 547514828718 ps
CPU time 831.24 seconds
Started Mar 24 12:44:37 PM PDT 24
Finished Mar 24 12:58:29 PM PDT 24
Peak memory 190920 kb
Host smart-81f5f30b-641a-4a3f-a085-4aca26dde9bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497745224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
497745224
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.235086291
Short name T176
Test name
Test status
Simulation time 438223155066 ps
CPU time 561.24 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:54:28 PM PDT 24
Peak memory 190816 kb
Host smart-8f62adaf-0cca-4157-817d-7e85c6093192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235086291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.235086291
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3487868023
Short name T140
Test name
Test status
Simulation time 185868014469 ps
CPU time 337.5 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:50:48 PM PDT 24
Peak memory 190888 kb
Host smart-8ccf6340-5799-4dd2-a7ed-38d60fe7831a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487868023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3487868023
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2210908529
Short name T187
Test name
Test status
Simulation time 211681189751 ps
CPU time 1716.65 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 190864 kb
Host smart-d8b7a6d8-187c-46c7-916c-eb09b651265d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210908529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2210908529
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.161747780
Short name T305
Test name
Test status
Simulation time 124844567015 ps
CPU time 480.02 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:53:03 PM PDT 24
Peak memory 194152 kb
Host smart-02d533ca-4cff-4016-a4da-5c69464dda16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161747780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.161747780
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1708771807
Short name T222
Test name
Test status
Simulation time 596892078845 ps
CPU time 434.4 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:52:24 PM PDT 24
Peak memory 193508 kb
Host smart-38760b4a-cea7-46a9-a84d-2314e24a5140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708771807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1708771807
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2376655396
Short name T255
Test name
Test status
Simulation time 6698144431 ps
CPU time 39.74 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:45:44 PM PDT 24
Peak memory 182892 kb
Host smart-cf8ff3e3-6699-4001-8074-294117f52a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376655396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2376655396
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2294038307
Short name T135
Test name
Test status
Simulation time 37381916362 ps
CPU time 137.04 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 190892 kb
Host smart-fe8fb6e3-b3e8-49b9-86ae-bd0e2531f640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294038307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2294038307
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2215612156
Short name T313
Test name
Test status
Simulation time 24128041769 ps
CPU time 21.48 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:45:42 PM PDT 24
Peak memory 182636 kb
Host smart-5482bf04-9bb4-485f-b772-fd619211324f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215612156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2215612156
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3696744900
Short name T178
Test name
Test status
Simulation time 2290570638138 ps
CPU time 1122.98 seconds
Started Mar 24 12:44:32 PM PDT 24
Finished Mar 24 01:03:15 PM PDT 24
Peak memory 182692 kb
Host smart-08263a3f-168d-48b0-81f5-910d53a878d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696744900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3696744900
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2502983459
Short name T371
Test name
Test status
Simulation time 261316506842 ps
CPU time 97.82 seconds
Started Mar 24 12:44:43 PM PDT 24
Finished Mar 24 12:46:21 PM PDT 24
Peak memory 182680 kb
Host smart-201dfed7-b4cf-4f0a-8bba-5724e53cdf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502983459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2502983459
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.194360456
Short name T379
Test name
Test status
Simulation time 93545056229 ps
CPU time 52.76 seconds
Started Mar 24 12:44:46 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 182704 kb
Host smart-27eb1c11-e05d-41ab-bc5e-dfc0f9f21e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194360456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.194360456
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2322817260
Short name T366
Test name
Test status
Simulation time 21644319131 ps
CPU time 36.31 seconds
Started Mar 24 12:44:54 PM PDT 24
Finished Mar 24 12:45:30 PM PDT 24
Peak memory 190768 kb
Host smart-3e2a8fd0-2b73-40f0-b87e-9ce7211720ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322817260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2322817260
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1174136725
Short name T199
Test name
Test status
Simulation time 180044154700 ps
CPU time 1142.3 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 01:04:08 PM PDT 24
Peak memory 190896 kb
Host smart-6a14495b-5dca-4df1-8e44-e7feb9cd4e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174136725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1174136725
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1476716848
Short name T448
Test name
Test status
Simulation time 191995583446 ps
CPU time 1695.21 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 01:13:28 PM PDT 24
Peak memory 182672 kb
Host smart-723370f2-45c9-4d2c-ae1b-5c972450114f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476716848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1476716848
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3217364917
Short name T105
Test name
Test status
Simulation time 184063410088 ps
CPU time 90.43 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:46:42 PM PDT 24
Peak memory 190928 kb
Host smart-ddcd1e50-3b58-449a-be16-3a9479a46206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217364917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3217364917
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1228619419
Short name T182
Test name
Test status
Simulation time 94410511077 ps
CPU time 177.81 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:48:09 PM PDT 24
Peak memory 190904 kb
Host smart-7cf75d1c-b954-4b68-81c4-366f033a4d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228619419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1228619419
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1003482536
Short name T7
Test name
Test status
Simulation time 122651963818 ps
CPU time 829.29 seconds
Started Mar 24 12:45:26 PM PDT 24
Finished Mar 24 12:59:16 PM PDT 24
Peak memory 190912 kb
Host smart-333c1fca-f69b-4dca-8cfd-42c41cf8ea6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003482536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1003482536
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.587187908
Short name T252
Test name
Test status
Simulation time 270225328727 ps
CPU time 73.15 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:46:31 PM PDT 24
Peak memory 182704 kb
Host smart-612ca61f-b600-470c-9308-830b937517ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587187908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.587187908
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.990892837
Short name T235
Test name
Test status
Simulation time 78295555161 ps
CPU time 21.97 seconds
Started Mar 24 12:44:38 PM PDT 24
Finished Mar 24 12:45:00 PM PDT 24
Peak memory 182696 kb
Host smart-cad9a523-57ec-4e21-b5f6-a93368381ea0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990892837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.990892837
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1437811827
Short name T391
Test name
Test status
Simulation time 125285946323 ps
CPU time 100.3 seconds
Started Mar 24 12:44:39 PM PDT 24
Finished Mar 24 12:46:19 PM PDT 24
Peak memory 182560 kb
Host smart-aac49c9f-1382-4a4f-81c1-8e9a11afc75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437811827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1437811827
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2406167258
Short name T65
Test name
Test status
Simulation time 199888647186 ps
CPU time 424.08 seconds
Started Mar 24 12:44:48 PM PDT 24
Finished Mar 24 12:51:53 PM PDT 24
Peak memory 190924 kb
Host smart-2b551ce3-ee62-442e-a668-0e683c1e6809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406167258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2406167258
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3141414056
Short name T376
Test name
Test status
Simulation time 467945131 ps
CPU time 0.86 seconds
Started Mar 24 12:44:42 PM PDT 24
Finished Mar 24 12:44:44 PM PDT 24
Peak memory 192120 kb
Host smart-057b7876-bf90-4408-ac0c-66acbb1dd04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141414056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3141414056
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.489899614
Short name T257
Test name
Test status
Simulation time 370970039327 ps
CPU time 312.03 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:50:17 PM PDT 24
Peak memory 190908 kb
Host smart-1dae7419-76d9-4be3-a548-40c7e4ad1a2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489899614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.489899614
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.943483616
Short name T249
Test name
Test status
Simulation time 191294687043 ps
CPU time 121.64 seconds
Started Mar 24 12:45:25 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 190900 kb
Host smart-e6a43b4e-95d6-40d8-870f-0df6629077f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943483616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.943483616
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.886910015
Short name T289
Test name
Test status
Simulation time 269590931518 ps
CPU time 134.87 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 190880 kb
Host smart-0c1f4fad-f7cb-4ade-817d-1e439254ea14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886910015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.886910015
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3446681566
Short name T110
Test name
Test status
Simulation time 181840424702 ps
CPU time 371.86 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:51:29 PM PDT 24
Peak memory 190824 kb
Host smart-d154ff93-e45e-4040-8787-de6e9a7eebee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446681566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3446681566
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1580995214
Short name T155
Test name
Test status
Simulation time 643329757902 ps
CPU time 2363.72 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 01:24:38 PM PDT 24
Peak memory 190836 kb
Host smart-93718018-9cc3-4a1c-932c-dd6ce9a4ee2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580995214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1580995214
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3152995974
Short name T335
Test name
Test status
Simulation time 145439156619 ps
CPU time 176.74 seconds
Started Mar 24 12:45:26 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 190868 kb
Host smart-ad1a0e10-f68e-4b6d-ae19-35ec839d76e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152995974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3152995974
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3783685689
Short name T127
Test name
Test status
Simulation time 69214843705 ps
CPU time 28.06 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:45:42 PM PDT 24
Peak memory 182508 kb
Host smart-d14cae23-d250-4f09-a3c6-ffc9fb63cf86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783685689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3783685689
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1443339799
Short name T388
Test name
Test status
Simulation time 160229945334 ps
CPU time 72.16 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:46:32 PM PDT 24
Peak memory 182712 kb
Host smart-f649032f-3cf9-4a8c-a812-82db6b88c637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443339799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1443339799
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.594977394
Short name T169
Test name
Test status
Simulation time 2464508261778 ps
CPU time 1301.96 seconds
Started Mar 24 12:44:33 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 182664 kb
Host smart-c33f0e5a-e38f-4c6d-8790-3cdbd1f90a93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594977394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.594977394
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3695632668
Short name T352
Test name
Test status
Simulation time 552873438918 ps
CPU time 229.59 seconds
Started Mar 24 12:44:33 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 182588 kb
Host smart-6533672b-36d4-403d-8a75-649d3f636098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695632668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3695632668
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.4174137020
Short name T304
Test name
Test status
Simulation time 86970540520 ps
CPU time 66.98 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:45:23 PM PDT 24
Peak memory 182708 kb
Host smart-40311232-e0cf-42e7-9ebc-8e62f65a17c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174137020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4174137020
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.4147504798
Short name T322
Test name
Test status
Simulation time 17613950811 ps
CPU time 10.05 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 12:44:33 PM PDT 24
Peak memory 190836 kb
Host smart-fedd8c78-38a9-4b0c-b73b-4796378861dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147504798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.4147504798
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2015130340
Short name T19
Test name
Test status
Simulation time 513162348 ps
CPU time 0.88 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 12:44:25 PM PDT 24
Peak memory 214280 kb
Host smart-9023ab2b-f57d-427a-a81f-904407952fe9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015130340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2015130340
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3799160554
Short name T47
Test name
Test status
Simulation time 102132175685 ps
CPU time 144.75 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 12:46:48 PM PDT 24
Peak memory 195320 kb
Host smart-e74fc812-fc1f-4960-a3fe-2fa42da879aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799160554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3799160554
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1935114710
Short name T120
Test name
Test status
Simulation time 51521625604 ps
CPU time 97 seconds
Started Mar 24 12:44:46 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 182632 kb
Host smart-6a207d6d-4b4d-4401-8730-ea0555f2968e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935114710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1935114710
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3119937674
Short name T383
Test name
Test status
Simulation time 34208711358 ps
CPU time 43.93 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 12:45:13 PM PDT 24
Peak memory 182604 kb
Host smart-629ff0d7-0c3a-401f-86d0-6540f64fb012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119937674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3119937674
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3725986332
Short name T123
Test name
Test status
Simulation time 145126362373 ps
CPU time 69.49 seconds
Started Mar 24 12:44:36 PM PDT 24
Finished Mar 24 12:45:46 PM PDT 24
Peak memory 190888 kb
Host smart-a1f7b2cd-9c45-4e42-988f-a45f5f77ab89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725986332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3725986332
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2186832673
Short name T455
Test name
Test status
Simulation time 14118922231 ps
CPU time 21.03 seconds
Started Mar 24 12:44:42 PM PDT 24
Finished Mar 24 12:45:03 PM PDT 24
Peak memory 190824 kb
Host smart-dd9c6a6b-3634-40c5-82f6-6880e7e9456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186832673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2186832673
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.1514138080
Short name T15
Test name
Test status
Simulation time 23621037756 ps
CPU time 177.48 seconds
Started Mar 24 12:44:45 PM PDT 24
Finished Mar 24 12:47:43 PM PDT 24
Peak memory 197308 kb
Host smart-9205ac3d-379a-418a-a75b-2ce5a939f047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514138080 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.1514138080
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_random.2716606584
Short name T292
Test name
Test status
Simulation time 475091818886 ps
CPU time 269.2 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:49:30 PM PDT 24
Peak memory 190912 kb
Host smart-bc5c1e14-79ff-41ba-b39b-50da59b7ed41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716606584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2716606584
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3048283250
Short name T310
Test name
Test status
Simulation time 189918654403 ps
CPU time 304.82 seconds
Started Mar 24 12:44:31 PM PDT 24
Finished Mar 24 12:49:36 PM PDT 24
Peak memory 190876 kb
Host smart-6d5fe666-bb8a-4b7a-83b0-0701dd0d4da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048283250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3048283250
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2021707243
Short name T419
Test name
Test status
Simulation time 66979943485 ps
CPU time 53.48 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 12:45:22 PM PDT 24
Peak memory 182668 kb
Host smart-ee1ec0e4-f606-48ff-a4f5-2775df94fced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021707243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2021707243
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4135892992
Short name T227
Test name
Test status
Simulation time 773164970794 ps
CPU time 427.24 seconds
Started Mar 24 12:44:35 PM PDT 24
Finished Mar 24 12:51:43 PM PDT 24
Peak memory 182900 kb
Host smart-a59452d6-df93-4c0e-b9c6-e080d5a53a95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135892992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4135892992
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.117780315
Short name T355
Test name
Test status
Simulation time 66943374756 ps
CPU time 93.99 seconds
Started Mar 24 12:44:38 PM PDT 24
Finished Mar 24 12:46:12 PM PDT 24
Peak memory 182720 kb
Host smart-c6c8531d-6216-448f-a7c9-ac5e0578d5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117780315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.117780315
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2427638531
Short name T63
Test name
Test status
Simulation time 214140315883 ps
CPU time 395.56 seconds
Started Mar 24 12:44:38 PM PDT 24
Finished Mar 24 12:51:14 PM PDT 24
Peak memory 191140 kb
Host smart-e7c2919f-1209-4dec-a826-70feac803217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427638531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2427638531
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3515531152
Short name T382
Test name
Test status
Simulation time 161754855 ps
CPU time 1.56 seconds
Started Mar 24 12:44:39 PM PDT 24
Finished Mar 24 12:44:40 PM PDT 24
Peak memory 182560 kb
Host smart-fff1c79e-98e6-4c2b-9bb5-d50465ed6ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515531152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3515531152
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.1523474921
Short name T440
Test name
Test status
Simulation time 43364357399 ps
CPU time 352.22 seconds
Started Mar 24 12:44:41 PM PDT 24
Finished Mar 24 12:50:33 PM PDT 24
Peak memory 205524 kb
Host smart-2a830353-a64d-4432-92c7-4244b1ce365b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523474921 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.1523474921
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.892554947
Short name T66
Test name
Test status
Simulation time 19704079124 ps
CPU time 9.23 seconds
Started Mar 24 12:44:47 PM PDT 24
Finished Mar 24 12:44:57 PM PDT 24
Peak memory 182724 kb
Host smart-832e2945-4c2f-4e2b-b500-55afc85fc0a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892554947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.892554947
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.454561245
Short name T374
Test name
Test status
Simulation time 77393689536 ps
CPU time 61.07 seconds
Started Mar 24 12:44:38 PM PDT 24
Finished Mar 24 12:45:39 PM PDT 24
Peak memory 182584 kb
Host smart-fa66ae8c-e26e-4de3-83f7-46514a527b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454561245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.454561245
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2049275137
Short name T134
Test name
Test status
Simulation time 33102701328 ps
CPU time 1150.46 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 01:03:54 PM PDT 24
Peak memory 190860 kb
Host smart-a40f30c9-a5c9-4cea-848f-ca9a718fb698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049275137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2049275137
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1451429455
Short name T346
Test name
Test status
Simulation time 55692007580 ps
CPU time 378.97 seconds
Started Mar 24 12:44:43 PM PDT 24
Finished Mar 24 12:51:02 PM PDT 24
Peak memory 182616 kb
Host smart-b0d9dc42-2beb-4df5-96f0-4366c264d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451429455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1451429455
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1475514934
Short name T342
Test name
Test status
Simulation time 590807503573 ps
CPU time 2800.98 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 01:31:47 PM PDT 24
Peak memory 191128 kb
Host smart-75c86241-e384-4960-b5ec-f6989e38bd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475514934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1475514934
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2848490833
Short name T40
Test name
Test status
Simulation time 63643870537 ps
CPU time 708.43 seconds
Started Mar 24 12:44:51 PM PDT 24
Finished Mar 24 12:56:39 PM PDT 24
Peak memory 207380 kb
Host smart-1c4297da-17b9-4c47-80c5-17ec72c55d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848490833 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2848490833
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.661294842
Short name T375
Test name
Test status
Simulation time 57504402594 ps
CPU time 82.98 seconds
Started Mar 24 12:44:48 PM PDT 24
Finished Mar 24 12:46:12 PM PDT 24
Peak memory 182572 kb
Host smart-c330dcc8-1af5-4b83-a05e-a6ccb3debfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661294842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.661294842
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3938380117
Short name T274
Test name
Test status
Simulation time 1152303743 ps
CPU time 2.62 seconds
Started Mar 24 12:44:48 PM PDT 24
Finished Mar 24 12:44:52 PM PDT 24
Peak memory 182504 kb
Host smart-d59c5e90-8887-4302-a981-b44f7433d5ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938380117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3938380117
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.4117407327
Short name T117
Test name
Test status
Simulation time 33933839996 ps
CPU time 68.68 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 190832 kb
Host smart-52c07a08-7a09-4280-80e4-f93fa46eb341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117407327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4117407327
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.418818005
Short name T172
Test name
Test status
Simulation time 521365214634 ps
CPU time 310.08 seconds
Started Mar 24 12:44:45 PM PDT 24
Finished Mar 24 12:49:57 PM PDT 24
Peak memory 182728 kb
Host smart-7945a100-a55b-4d93-805d-81158549e586
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418818005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.418818005
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.557089890
Short name T416
Test name
Test status
Simulation time 33721336911 ps
CPU time 27.04 seconds
Started Mar 24 12:44:41 PM PDT 24
Finished Mar 24 12:45:08 PM PDT 24
Peak memory 182680 kb
Host smart-acb3eddc-cf6d-4dbd-a436-ffd8cecbbbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557089890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.557089890
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.430705326
Short name T453
Test name
Test status
Simulation time 119693720048 ps
CPU time 69.53 seconds
Started Mar 24 12:44:59 PM PDT 24
Finished Mar 24 12:46:09 PM PDT 24
Peak memory 190888 kb
Host smart-39fbf32c-f66a-455d-91d2-1dfe3d05aa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430705326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.430705326
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3088217199
Short name T370
Test name
Test status
Simulation time 1261063773953 ps
CPU time 298.68 seconds
Started Mar 24 12:44:47 PM PDT 24
Finished Mar 24 12:49:47 PM PDT 24
Peak memory 182708 kb
Host smart-2c679318-abfa-473a-98fc-fda0cf8dc099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088217199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3088217199
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4216007300
Short name T279
Test name
Test status
Simulation time 5646854916 ps
CPU time 10.06 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 12:44:54 PM PDT 24
Peak memory 182688 kb
Host smart-23e4bc53-cb21-4d62-be96-3cc039838a09
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216007300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4216007300
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1071595010
Short name T454
Test name
Test status
Simulation time 331548026127 ps
CPU time 149.23 seconds
Started Mar 24 12:44:30 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 182740 kb
Host smart-42dc4464-5931-4dfc-9038-b85382cb7584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071595010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1071595010
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2298803040
Short name T8
Test name
Test status
Simulation time 143070286900 ps
CPU time 202.67 seconds
Started Mar 24 12:44:46 PM PDT 24
Finished Mar 24 12:48:10 PM PDT 24
Peak memory 190856 kb
Host smart-f59641e5-f86e-45e1-a1ba-1f2412b4630b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298803040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2298803040
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.207193141
Short name T402
Test name
Test status
Simulation time 187924895125 ps
CPU time 84.8 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:46:29 PM PDT 24
Peak memory 191112 kb
Host smart-2238684d-8fa3-4f81-8ab3-7698a27a5fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207193141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.207193141
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3013481981
Short name T36
Test name
Test status
Simulation time 43352984724 ps
CPU time 320.91 seconds
Started Mar 24 12:44:39 PM PDT 24
Finished Mar 24 12:50:01 PM PDT 24
Peak memory 197304 kb
Host smart-c3491e1a-fb89-43ca-9bde-567a6ac8fc3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013481981 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3013481981
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1417014523
Short name T196
Test name
Test status
Simulation time 1627408246462 ps
CPU time 743.13 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 12:56:53 PM PDT 24
Peak memory 182732 kb
Host smart-319d7bf9-a1de-4036-8f63-cf92a8290aff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417014523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1417014523
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1466133945
Short name T433
Test name
Test status
Simulation time 740463289964 ps
CPU time 288.68 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 12:49:32 PM PDT 24
Peak memory 182676 kb
Host smart-a3128991-663e-40ec-8f9a-1fc3e20436b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466133945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1466133945
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.750683792
Short name T1
Test name
Test status
Simulation time 112135013810 ps
CPU time 190.88 seconds
Started Mar 24 12:44:48 PM PDT 24
Finished Mar 24 12:48:00 PM PDT 24
Peak memory 190832 kb
Host smart-93e4029c-9287-4ed3-8834-172721c80354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750683792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.750683792
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1215137357
Short name T88
Test name
Test status
Simulation time 125745354659 ps
CPU time 115 seconds
Started Mar 24 12:44:26 PM PDT 24
Finished Mar 24 12:46:22 PM PDT 24
Peak memory 190880 kb
Host smart-3f166bc3-92f5-4e71-9ecb-d8f4c39ce63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215137357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1215137357
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3023730381
Short name T165
Test name
Test status
Simulation time 54549435039 ps
CPU time 24.16 seconds
Started Mar 24 12:44:58 PM PDT 24
Finished Mar 24 12:45:23 PM PDT 24
Peak memory 182668 kb
Host smart-29fce1d8-a3b0-45df-a594-bd98ad986746
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023730381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3023730381
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2548399322
Short name T349
Test name
Test status
Simulation time 58751232966 ps
CPU time 78.79 seconds
Started Mar 24 12:44:31 PM PDT 24
Finished Mar 24 12:45:50 PM PDT 24
Peak memory 182712 kb
Host smart-497fe57d-a482-4477-8a35-c400bd814d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548399322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2548399322
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.4079761080
Short name T401
Test name
Test status
Simulation time 132835697556 ps
CPU time 83.05 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:46:24 PM PDT 24
Peak memory 194504 kb
Host smart-69ef0c5f-d0af-4302-8a1c-8cb01474cccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079761080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4079761080
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3652800152
Short name T368
Test name
Test status
Simulation time 8946355121 ps
CPU time 5.51 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 12:44:49 PM PDT 24
Peak memory 182716 kb
Host smart-13c19563-fc71-4b87-a0b3-a7b1f8a9f2e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652800152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3652800152
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.365179083
Short name T412
Test name
Test status
Simulation time 272346582022 ps
CPU time 68.76 seconds
Started Mar 24 12:44:37 PM PDT 24
Finished Mar 24 12:45:46 PM PDT 24
Peak memory 182728 kb
Host smart-69073d34-5824-4f60-b746-bb80f51ef716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365179083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.365179083
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2770615303
Short name T163
Test name
Test status
Simulation time 233801897244 ps
CPU time 990.69 seconds
Started Mar 24 12:44:38 PM PDT 24
Finished Mar 24 01:01:09 PM PDT 24
Peak memory 190824 kb
Host smart-cde191ef-886a-4888-a79c-e505be6c79d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770615303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2770615303
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1991022890
Short name T12
Test name
Test status
Simulation time 199740104529 ps
CPU time 106.2 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 12:46:38 PM PDT 24
Peak memory 194392 kb
Host smart-3e029f5e-2475-4a3e-b388-c9eedeeef71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991022890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1991022890
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2004197285
Short name T451
Test name
Test status
Simulation time 178578138894 ps
CPU time 296.45 seconds
Started Mar 24 12:44:45 PM PDT 24
Finished Mar 24 12:49:44 PM PDT 24
Peak memory 182684 kb
Host smart-e3371e45-bb8e-4f8b-84c9-7a3dc0df9e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004197285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2004197285
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.171492743
Short name T434
Test name
Test status
Simulation time 234974888525 ps
CPU time 104 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 12:46:08 PM PDT 24
Peak memory 182728 kb
Host smart-57222d9e-3986-4cb5-bd84-5930e0d18159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171492743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.171492743
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1657345395
Short name T215
Test name
Test status
Simulation time 165789920112 ps
CPU time 175.48 seconds
Started Mar 24 12:44:22 PM PDT 24
Finished Mar 24 12:47:17 PM PDT 24
Peak memory 190860 kb
Host smart-d5e6016b-22ad-444d-9cbc-899636784a39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657345395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1657345395
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3458937541
Short name T173
Test name
Test status
Simulation time 46325454889 ps
CPU time 75.39 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:45:29 PM PDT 24
Peak memory 194052 kb
Host smart-fbc2dfdb-0bc0-4c26-92b6-d50c148f7b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458937541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3458937541
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2436287587
Short name T16
Test name
Test status
Simulation time 62288009 ps
CPU time 0.85 seconds
Started Mar 24 12:44:26 PM PDT 24
Finished Mar 24 12:44:27 PM PDT 24
Peak memory 213104 kb
Host smart-6b5d44b5-7761-4f4f-9f41-ddeac614289d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436287587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2436287587
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.482065483
Short name T387
Test name
Test status
Simulation time 495888257484 ps
CPU time 728.74 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:56:21 PM PDT 24
Peak memory 190756 kb
Host smart-a7d2c5b8-f7fb-4904-ae10-82b0a3a54d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482065483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.482065483
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2550496732
Short name T38
Test name
Test status
Simulation time 132027730490 ps
CPU time 284.58 seconds
Started Mar 24 12:44:17 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 205448 kb
Host smart-b6307e33-973f-444d-9a94-ea120dd9e2a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550496732 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2550496732
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3797154598
Short name T224
Test name
Test status
Simulation time 1137325648132 ps
CPU time 585.12 seconds
Started Mar 24 12:44:43 PM PDT 24
Finished Mar 24 12:54:29 PM PDT 24
Peak memory 182932 kb
Host smart-2cecaef4-29e5-4812-810d-e89e5126b2f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797154598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3797154598
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.435618333
Short name T414
Test name
Test status
Simulation time 549564786144 ps
CPU time 206.35 seconds
Started Mar 24 12:44:45 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 182572 kb
Host smart-aceeea1c-7264-4df9-a14a-e6433003b920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435618333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.435618333
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2677577661
Short name T102
Test name
Test status
Simulation time 252900554352 ps
CPU time 178.23 seconds
Started Mar 24 12:44:38 PM PDT 24
Finished Mar 24 12:47:36 PM PDT 24
Peak memory 190908 kb
Host smart-d0c6f1f7-3ecb-4c69-8924-897f7a7b8b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677577661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2677577661
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1718456221
Short name T413
Test name
Test status
Simulation time 77291999488 ps
CPU time 75.15 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 12:46:00 PM PDT 24
Peak memory 194076 kb
Host smart-2c1ecf4e-d900-439a-a526-840926b41631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718456221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1718456221
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2500465019
Short name T61
Test name
Test status
Simulation time 91860739342 ps
CPU time 68.17 seconds
Started Mar 24 12:44:51 PM PDT 24
Finished Mar 24 12:45:59 PM PDT 24
Peak memory 182696 kb
Host smart-c34596a1-dd4a-4c6e-950d-3afc01eb5ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500465019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2500465019
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2137483361
Short name T136
Test name
Test status
Simulation time 127429015487 ps
CPU time 459.95 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 12:52:32 PM PDT 24
Peak memory 194164 kb
Host smart-2e70678b-c5e4-4c64-b4cf-a40c11e2500d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137483361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2137483361
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3811386379
Short name T330
Test name
Test status
Simulation time 282061914751 ps
CPU time 589.14 seconds
Started Mar 24 12:44:49 PM PDT 24
Finished Mar 24 12:54:40 PM PDT 24
Peak memory 182696 kb
Host smart-d0b981fe-c2c6-4d5b-b27d-071ecb86e79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811386379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3811386379
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.226778069
Short name T50
Test name
Test status
Simulation time 45080380 ps
CPU time 0.53 seconds
Started Mar 24 12:44:55 PM PDT 24
Finished Mar 24 12:44:56 PM PDT 24
Peak memory 182384 kb
Host smart-fc9e516b-cc6b-4bd0-92b3-b44303c44847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226778069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
226778069
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3877763917
Short name T256
Test name
Test status
Simulation time 1307865851803 ps
CPU time 676.51 seconds
Started Mar 24 12:44:36 PM PDT 24
Finished Mar 24 12:55:53 PM PDT 24
Peak memory 182688 kb
Host smart-132e3845-d16e-446b-9e23-6d9127f71395
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877763917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3877763917
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.997445685
Short name T360
Test name
Test status
Simulation time 134322321976 ps
CPU time 55.81 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 12:45:48 PM PDT 24
Peak memory 182704 kb
Host smart-fd3d8c95-81a8-4cdb-aad4-ebe1a80bd9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997445685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.997445685
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.820269245
Short name T275
Test name
Test status
Simulation time 80611420740 ps
CPU time 98.96 seconds
Started Mar 24 12:44:48 PM PDT 24
Finished Mar 24 12:46:28 PM PDT 24
Peak memory 190776 kb
Host smart-b773c047-8dec-4e7a-9819-ba2bb71edbe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820269245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.820269245
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3118233792
Short name T303
Test name
Test status
Simulation time 69093096958 ps
CPU time 80.27 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:46:22 PM PDT 24
Peak memory 190872 kb
Host smart-58a3fb2d-da82-4768-9073-ee362ceb76ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118233792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3118233792
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2565569032
Short name T244
Test name
Test status
Simulation time 509008720016 ps
CPU time 789.95 seconds
Started Mar 24 12:44:53 PM PDT 24
Finished Mar 24 12:58:04 PM PDT 24
Peak memory 182528 kb
Host smart-78ec298b-f86a-416e-aad6-9f8bf2524eb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565569032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2565569032
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3244571959
Short name T443
Test name
Test status
Simulation time 3149301653 ps
CPU time 5.08 seconds
Started Mar 24 12:44:42 PM PDT 24
Finished Mar 24 12:44:47 PM PDT 24
Peak memory 182556 kb
Host smart-5ab26285-0140-4579-b655-7d8af1890e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244571959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3244571959
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2337621813
Short name T153
Test name
Test status
Simulation time 232545661040 ps
CPU time 523.28 seconds
Started Mar 24 12:44:50 PM PDT 24
Finished Mar 24 12:53:34 PM PDT 24
Peak memory 190904 kb
Host smart-a65d9ff8-bc89-4ac7-81f3-a798dae2adec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337621813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2337621813
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3979875065
Short name T126
Test name
Test status
Simulation time 308215398827 ps
CPU time 329.76 seconds
Started Mar 24 12:44:47 PM PDT 24
Finished Mar 24 12:50:18 PM PDT 24
Peak memory 190912 kb
Host smart-ba9f3612-092b-4b31-8aff-b96449fa8b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979875065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3979875065
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.778439880
Short name T49
Test name
Test status
Simulation time 69156092 ps
CPU time 0.53 seconds
Started Mar 24 12:44:42 PM PDT 24
Finished Mar 24 12:44:43 PM PDT 24
Peak memory 181952 kb
Host smart-5d6058c3-4414-45d7-a8eb-410a291a776b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778439880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
778439880
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3240063312
Short name T438
Test name
Test status
Simulation time 235062574225 ps
CPU time 370.49 seconds
Started Mar 24 12:44:56 PM PDT 24
Finished Mar 24 12:51:07 PM PDT 24
Peak memory 182656 kb
Host smart-b9b6ebc9-9072-495d-a204-536a96187561
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240063312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3240063312
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.526436028
Short name T357
Test name
Test status
Simulation time 63170588685 ps
CPU time 53.72 seconds
Started Mar 24 12:44:58 PM PDT 24
Finished Mar 24 12:45:57 PM PDT 24
Peak memory 182696 kb
Host smart-5c4b781c-eda6-42b7-ba8a-b004abaa8574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526436028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.526436028
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3861127175
Short name T317
Test name
Test status
Simulation time 54920080223 ps
CPU time 407.99 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:51:49 PM PDT 24
Peak memory 182508 kb
Host smart-16f55fba-7f20-45c8-b7fb-8679b5ae2dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861127175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3861127175
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2730836533
Short name T420
Test name
Test status
Simulation time 349241540534 ps
CPU time 192.77 seconds
Started Mar 24 12:45:00 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 194660 kb
Host smart-930c4628-cc65-41b8-afcf-57382fcf33d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730836533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2730836533
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.4266085289
Short name T34
Test name
Test status
Simulation time 65598199558 ps
CPU time 348.93 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:50:57 PM PDT 24
Peak memory 205504 kb
Host smart-f75971a8-d6e0-40b3-b74b-fec6154cc6ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266085289 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.4266085289
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1564822867
Short name T21
Test name
Test status
Simulation time 165052762761 ps
CPU time 275.93 seconds
Started Mar 24 12:44:49 PM PDT 24
Finished Mar 24 12:49:25 PM PDT 24
Peak memory 182692 kb
Host smart-43001544-d78c-4bc1-8042-83bbef8ed794
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564822867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1564822867
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.4233434774
Short name T449
Test name
Test status
Simulation time 153662562914 ps
CPU time 135.25 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 182504 kb
Host smart-73f94c14-4806-4267-a346-5ea304d6985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233434774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4233434774
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1641322518
Short name T124
Test name
Test status
Simulation time 21777187798 ps
CPU time 11.04 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:45:15 PM PDT 24
Peak memory 182504 kb
Host smart-98d51723-9362-4ea9-bce2-05c50eedfde1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641322518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1641322518
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1313072313
Short name T343
Test name
Test status
Simulation time 24931709801 ps
CPU time 23.18 seconds
Started Mar 24 12:44:43 PM PDT 24
Finished Mar 24 12:45:06 PM PDT 24
Peak memory 182640 kb
Host smart-0f62abfa-f13c-4d20-ba23-7162896a6479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313072313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1313072313
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2410479790
Short name T426
Test name
Test status
Simulation time 569176562017 ps
CPU time 427.79 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:52:12 PM PDT 24
Peak memory 190884 kb
Host smart-827a3b01-3047-4439-be1c-49a0457e7aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410479790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2410479790
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.665109918
Short name T35
Test name
Test status
Simulation time 122389223489 ps
CPU time 818.45 seconds
Started Mar 24 12:44:54 PM PDT 24
Finished Mar 24 12:58:32 PM PDT 24
Peak memory 205532 kb
Host smart-8935c39b-f255-49eb-9a0f-2c01f6728b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665109918 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.665109918
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2532582998
Short name T276
Test name
Test status
Simulation time 277005637052 ps
CPU time 480.12 seconds
Started Mar 24 12:44:42 PM PDT 24
Finished Mar 24 12:52:42 PM PDT 24
Peak memory 182692 kb
Host smart-6d592b62-7521-4a66-bc34-62f6aa5548ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532582998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2532582998
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2428676178
Short name T62
Test name
Test status
Simulation time 258628320108 ps
CPU time 110.64 seconds
Started Mar 24 12:44:54 PM PDT 24
Finished Mar 24 12:46:45 PM PDT 24
Peak memory 182640 kb
Host smart-b75c494e-c2ff-4deb-bba7-0824c281c5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428676178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2428676178
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2561758623
Short name T24
Test name
Test status
Simulation time 273033467398 ps
CPU time 349.42 seconds
Started Mar 24 12:44:49 PM PDT 24
Finished Mar 24 12:50:39 PM PDT 24
Peak memory 190916 kb
Host smart-c007f1fa-f9dc-48f3-9dda-3a6837d5df03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561758623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2561758623
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2667389947
Short name T298
Test name
Test status
Simulation time 151953525803 ps
CPU time 226.98 seconds
Started Mar 24 12:44:54 PM PDT 24
Finished Mar 24 12:48:42 PM PDT 24
Peak memory 182496 kb
Host smart-76afed81-5b50-447f-a228-292b4e9c94d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667389947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2667389947
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.468178670
Short name T452
Test name
Test status
Simulation time 523831567780 ps
CPU time 1494.84 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 01:09:47 PM PDT 24
Peak memory 190864 kb
Host smart-d51d4ab9-0149-4522-9ac2-832212bd501d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468178670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
468178670
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.679268490
Short name T422
Test name
Test status
Simulation time 369371143863 ps
CPU time 148.36 seconds
Started Mar 24 12:44:55 PM PDT 24
Finished Mar 24 12:47:24 PM PDT 24
Peak memory 182704 kb
Host smart-bebfd29d-903e-4247-a321-5bf59aaba14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679268490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.679268490
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3884695797
Short name T270
Test name
Test status
Simulation time 230379834222 ps
CPU time 1263.76 seconds
Started Mar 24 12:44:49 PM PDT 24
Finished Mar 24 01:05:53 PM PDT 24
Peak memory 190892 kb
Host smart-929d262c-664a-4dfe-9d3b-dba8c21d1cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884695797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3884695797
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.184826283
Short name T51
Test name
Test status
Simulation time 586747387984 ps
CPU time 954.84 seconds
Started Mar 24 12:44:44 PM PDT 24
Finished Mar 24 01:00:40 PM PDT 24
Peak memory 190880 kb
Host smart-84509ca4-8aef-4851-a837-2dc32e3d180b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184826283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
184826283
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1007532826
Short name T111
Test name
Test status
Simulation time 6511674398 ps
CPU time 12.78 seconds
Started Mar 24 12:44:53 PM PDT 24
Finished Mar 24 12:45:06 PM PDT 24
Peak memory 182728 kb
Host smart-6b284fa1-6ddb-4aa5-b532-b60080627a22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007532826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1007532826
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.311939590
Short name T348
Test name
Test status
Simulation time 639282875393 ps
CPU time 247.49 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 182680 kb
Host smart-27c8bf75-56a7-4701-9ecb-f488cf84ab4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311939590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.311939590
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3062848474
Short name T101
Test name
Test status
Simulation time 577669406840 ps
CPU time 234.88 seconds
Started Mar 24 12:44:50 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 190892 kb
Host smart-355cea12-bc76-408b-ba62-295b243dddef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062848474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3062848474
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2098836391
Short name T9
Test name
Test status
Simulation time 21597139302 ps
CPU time 26.59 seconds
Started Mar 24 12:44:59 PM PDT 24
Finished Mar 24 12:45:26 PM PDT 24
Peak memory 190912 kb
Host smart-f44819e3-cf1a-4bc7-a497-d7d783b42549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098836391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2098836391
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3526499333
Short name T37
Test name
Test status
Simulation time 23444956258 ps
CPU time 178.73 seconds
Started Mar 24 12:45:02 PM PDT 24
Finished Mar 24 12:48:01 PM PDT 24
Peak memory 197284 kb
Host smart-9f5a12df-b97d-4c30-b9d6-23febec5dcc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526499333 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3526499333
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3483135362
Short name T361
Test name
Test status
Simulation time 198655882914 ps
CPU time 140.29 seconds
Started Mar 24 12:44:45 PM PDT 24
Finished Mar 24 12:47:08 PM PDT 24
Peak memory 182500 kb
Host smart-5231a29e-3377-4bdd-bea9-f46286d1f279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483135362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3483135362
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1991515056
Short name T410
Test name
Test status
Simulation time 26832343772 ps
CPU time 34.77 seconds
Started Mar 24 12:44:55 PM PDT 24
Finished Mar 24 12:45:30 PM PDT 24
Peak memory 182688 kb
Host smart-e3f16278-f501-4a4b-bdb1-e0297926401c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991515056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1991515056
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3856400458
Short name T219
Test name
Test status
Simulation time 87486211367 ps
CPU time 182.75 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:48:06 PM PDT 24
Peak memory 190852 kb
Host smart-6e60e392-dc5e-4709-8c09-dae0d286ba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856400458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3856400458
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.911754657
Short name T421
Test name
Test status
Simulation time 93847776255 ps
CPU time 392.43 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 12:51:24 PM PDT 24
Peak memory 205584 kb
Host smart-fa724703-4147-42b1-94ea-8bdff9c337e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911754657 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.911754657
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1366850341
Short name T22
Test name
Test status
Simulation time 106289033535 ps
CPU time 160.87 seconds
Started Mar 24 12:44:20 PM PDT 24
Finished Mar 24 12:47:01 PM PDT 24
Peak memory 182628 kb
Host smart-23245c37-ed84-4ef3-9c96-6129437d1435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366850341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1366850341
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2526747018
Short name T262
Test name
Test status
Simulation time 207015495759 ps
CPU time 575.89 seconds
Started Mar 24 12:44:20 PM PDT 24
Finished Mar 24 12:53:56 PM PDT 24
Peak memory 190852 kb
Host smart-60d5bbe0-e22f-4cb6-a81e-3a585c1a8f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526747018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2526747018
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1705019461
Short name T89
Test name
Test status
Simulation time 50592932478 ps
CPU time 83.55 seconds
Started Mar 24 12:44:25 PM PDT 24
Finished Mar 24 12:45:49 PM PDT 24
Peak memory 193384 kb
Host smart-bf1b636f-2896-4c30-a580-b868bde6ce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705019461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1705019461
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.285025764
Short name T17
Test name
Test status
Simulation time 118715644 ps
CPU time 0.75 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:16 PM PDT 24
Peak memory 213172 kb
Host smart-f2facc3f-335a-41c7-8a90-70844f90627e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285025764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.285025764
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1936368659
Short name T425
Test name
Test status
Simulation time 23530352300 ps
CPU time 9.13 seconds
Started Mar 24 12:44:33 PM PDT 24
Finished Mar 24 12:44:42 PM PDT 24
Peak memory 193216 kb
Host smart-ab03383e-8d49-4d92-86bc-7249d2fb9be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936368659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1936368659
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1026382644
Short name T246
Test name
Test status
Simulation time 543856256911 ps
CPU time 293.4 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:49:55 PM PDT 24
Peak memory 182600 kb
Host smart-e351770d-c5fe-4954-b06b-b19135ce6221
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026382644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1026382644
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2132534813
Short name T358
Test name
Test status
Simulation time 123377137340 ps
CPU time 181.77 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:48:09 PM PDT 24
Peak memory 182688 kb
Host smart-373a9459-76d2-4bc4-9be8-ffbb4015d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132534813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2132534813
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2471364402
Short name T231
Test name
Test status
Simulation time 182834663891 ps
CPU time 318.5 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:50:20 PM PDT 24
Peak memory 191104 kb
Host smart-d9e62d1a-ffe3-462d-9df5-8a49e63cd383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471364402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2471364402
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.108608388
Short name T266
Test name
Test status
Simulation time 60098288208 ps
CPU time 27.14 seconds
Started Mar 24 12:44:53 PM PDT 24
Finished Mar 24 12:45:20 PM PDT 24
Peak memory 194076 kb
Host smart-22672356-bb46-47c3-9d11-4b8ca794d7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108608388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.108608388
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3240070605
Short name T353
Test name
Test status
Simulation time 87800457639 ps
CPU time 39.68 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:45:47 PM PDT 24
Peak memory 182672 kb
Host smart-e62dfd6c-d4bf-45eb-a310-75a4d59544ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240070605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3240070605
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1552342043
Short name T405
Test name
Test status
Simulation time 12022273598 ps
CPU time 19.6 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:45:17 PM PDT 24
Peak memory 182720 kb
Host smart-4fde8f52-4d4d-48e3-8c3d-5803eafccc1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552342043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1552342043
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.694721100
Short name T407
Test name
Test status
Simulation time 178623294246 ps
CPU time 272.41 seconds
Started Mar 24 12:44:54 PM PDT 24
Finished Mar 24 12:49:27 PM PDT 24
Peak memory 182512 kb
Host smart-de364d47-c0d0-412d-bee2-0d57e0417a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694721100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.694721100
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3109895254
Short name T411
Test name
Test status
Simulation time 118578904843 ps
CPU time 55.71 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:46:10 PM PDT 24
Peak memory 193840 kb
Host smart-9ff699ba-4049-470a-8604-c75d0af593bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109895254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3109895254
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1861526713
Short name T381
Test name
Test status
Simulation time 611909339509 ps
CPU time 332.61 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:50:31 PM PDT 24
Peak memory 190896 kb
Host smart-028577d7-9bac-449b-bff1-7e12c8136385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861526713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1861526713
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2746272174
Short name T138
Test name
Test status
Simulation time 442246183608 ps
CPU time 222.85 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 12:48:35 PM PDT 24
Peak memory 182640 kb
Host smart-e2371963-8c1d-4aee-8569-eeb8bb118d48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746272174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2746272174
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1454113290
Short name T351
Test name
Test status
Simulation time 121981895743 ps
CPU time 180.69 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 12:47:52 PM PDT 24
Peak memory 182732 kb
Host smart-b680df2c-9626-4a2c-a435-81af0c3f6bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454113290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1454113290
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3750701984
Short name T54
Test name
Test status
Simulation time 115677170165 ps
CPU time 117.77 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:47:00 PM PDT 24
Peak memory 190780 kb
Host smart-94c09aaa-90b5-4f37-a954-92f1bd5f1905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750701984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3750701984
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2485371171
Short name T396
Test name
Test status
Simulation time 16521872 ps
CPU time 0.61 seconds
Started Mar 24 12:45:02 PM PDT 24
Finished Mar 24 12:45:03 PM PDT 24
Peak memory 182500 kb
Host smart-a1b5b1d8-22c3-44d4-ace0-9a9429531ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485371171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2485371171
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1539974033
Short name T436
Test name
Test status
Simulation time 71917777879 ps
CPU time 293.68 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:50:07 PM PDT 24
Peak memory 205532 kb
Host smart-778ee3f8-7250-453b-8cfc-fe68bb822c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539974033 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1539974033
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.703515588
Short name T23
Test name
Test status
Simulation time 146203304579 ps
CPU time 265.37 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:49:22 PM PDT 24
Peak memory 182680 kb
Host smart-0907f8f7-f4cd-419c-b441-59a68ef56d4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703515588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.703515588
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.4005887186
Short name T435
Test name
Test status
Simulation time 63086689003 ps
CPU time 97.31 seconds
Started Mar 24 12:44:54 PM PDT 24
Finished Mar 24 12:46:31 PM PDT 24
Peak memory 182620 kb
Host smart-ebb8ca87-504e-4d2e-a80e-32d900902e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005887186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4005887186
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.166304462
Short name T137
Test name
Test status
Simulation time 233959308852 ps
CPU time 249.12 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:49:07 PM PDT 24
Peak memory 190888 kb
Host smart-4e55b9f8-cf48-41da-a304-e0ea30faa9db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166304462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.166304462
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.4135869404
Short name T284
Test name
Test status
Simulation time 166300420956 ps
CPU time 349.43 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:50:59 PM PDT 24
Peak memory 190888 kb
Host smart-a2539aea-bf9d-4b32-bcaf-db3dbef70fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135869404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4135869404
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.885343397
Short name T159
Test name
Test status
Simulation time 919582520547 ps
CPU time 690.25 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:56:33 PM PDT 24
Peak memory 190844 kb
Host smart-9fc30366-874b-4d16-9be8-23f4246bfab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885343397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
885343397
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1165073994
Short name T301
Test name
Test status
Simulation time 179613962875 ps
CPU time 316.19 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:50:19 PM PDT 24
Peak memory 182628 kb
Host smart-89dbe496-c42a-401d-ac62-b7bb48a35c01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165073994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1165073994
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.164522393
Short name T389
Test name
Test status
Simulation time 240969443278 ps
CPU time 101.41 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:46:45 PM PDT 24
Peak memory 182640 kb
Host smart-676997ef-5d2b-4e89-9484-516c5e8dd4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164522393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.164522393
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2462301698
Short name T216
Test name
Test status
Simulation time 826437688049 ps
CPU time 706.73 seconds
Started Mar 24 12:44:52 PM PDT 24
Finished Mar 24 12:56:39 PM PDT 24
Peak memory 190912 kb
Host smart-6f1df6e9-bad9-45a4-805a-5d19e7366c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462301698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2462301698
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1643510041
Short name T373
Test name
Test status
Simulation time 581797844 ps
CPU time 0.7 seconds
Started Mar 24 12:44:45 PM PDT 24
Finished Mar 24 12:44:48 PM PDT 24
Peak memory 182468 kb
Host smart-ea06b468-004f-4373-9313-d940106686a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643510041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1643510041
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1186771727
Short name T415
Test name
Test status
Simulation time 3650331660410 ps
CPU time 574.53 seconds
Started Mar 24 12:45:05 PM PDT 24
Finished Mar 24 12:54:40 PM PDT 24
Peak memory 190932 kb
Host smart-63d726bd-5689-428d-8e67-f66c225b66e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186771727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1186771727
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random.1369740511
Short name T116
Test name
Test status
Simulation time 455878004503 ps
CPU time 232.07 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:48:53 PM PDT 24
Peak memory 190916 kb
Host smart-1ba0ca92-b559-4bf8-b15e-97a38c932b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369740511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1369740511
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1923174131
Short name T378
Test name
Test status
Simulation time 93169088 ps
CPU time 0.56 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:45:09 PM PDT 24
Peak memory 182452 kb
Host smart-f6ad5baf-da55-4663-a1c2-6232fdac4f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923174131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1923174131
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2988403227
Short name T354
Test name
Test status
Simulation time 1302112170339 ps
CPU time 211.03 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:48:28 PM PDT 24
Peak memory 182632 kb
Host smart-b94a726f-efd3-4632-9da3-c7b55d904056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988403227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2988403227
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1139083993
Short name T95
Test name
Test status
Simulation time 454992741689 ps
CPU time 1180.84 seconds
Started Mar 24 12:44:49 PM PDT 24
Finished Mar 24 01:04:31 PM PDT 24
Peak memory 221948 kb
Host smart-7cdcdcbc-2d4c-40e2-8dba-1d3f6ccb7de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139083993 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1139083993
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2218778214
Short name T241
Test name
Test status
Simulation time 1627079874984 ps
CPU time 888.3 seconds
Started Mar 24 12:45:00 PM PDT 24
Finished Mar 24 12:59:49 PM PDT 24
Peak memory 182712 kb
Host smart-7ecefc0d-7222-4300-80dc-0af4cd988ca2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218778214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2218778214
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1473296219
Short name T399
Test name
Test status
Simulation time 815087076704 ps
CPU time 246.25 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:49:09 PM PDT 24
Peak memory 182676 kb
Host smart-a54fbec9-9d61-47ff-91ec-a326c516715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473296219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1473296219
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1944173436
Short name T439
Test name
Test status
Simulation time 122507985642 ps
CPU time 115.09 seconds
Started Mar 24 12:44:50 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 190920 kb
Host smart-fabc599a-d018-4a53-80e0-c2146016db52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944173436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1944173436
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.601929487
Short name T367
Test name
Test status
Simulation time 56960534 ps
CPU time 0.61 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:45:15 PM PDT 24
Peak memory 182492 kb
Host smart-0f7a5be4-15f8-40c7-8722-8c7c75621cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601929487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.601929487
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.3229513049
Short name T14
Test name
Test status
Simulation time 107962421922 ps
CPU time 603.57 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:55:11 PM PDT 24
Peak memory 205540 kb
Host smart-bc99c199-9a23-4200-8675-21d98a4d5769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229513049 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.3229513049
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4019746033
Short name T312
Test name
Test status
Simulation time 907785526973 ps
CPU time 1043.38 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 01:02:25 PM PDT 24
Peak memory 182716 kb
Host smart-e2e4f1b0-ec7c-440b-baa7-b966c0d14330
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019746033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4019746033
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2823553882
Short name T394
Test name
Test status
Simulation time 476287773310 ps
CPU time 118.09 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:47:18 PM PDT 24
Peak memory 182684 kb
Host smart-1bf77bb4-289c-4c7c-b792-98bcce0320ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823553882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2823553882
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.715968315
Short name T93
Test name
Test status
Simulation time 400137982981 ps
CPU time 477.92 seconds
Started Mar 24 12:44:54 PM PDT 24
Finished Mar 24 12:52:52 PM PDT 24
Peak memory 190868 kb
Host smart-be5dcdba-5954-4959-98a8-a7b122b1f8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715968315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.715968315
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3809584725
Short name T385
Test name
Test status
Simulation time 122532958 ps
CPU time 1.25 seconds
Started Mar 24 12:45:00 PM PDT 24
Finished Mar 24 12:45:01 PM PDT 24
Peak memory 191824 kb
Host smart-4cdf0f4b-1756-417d-b9e3-d0dc9f440a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809584725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3809584725
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.14286058
Short name T91
Test name
Test status
Simulation time 81316639204 ps
CPU time 105.03 seconds
Started Mar 24 12:44:54 PM PDT 24
Finished Mar 24 12:46:39 PM PDT 24
Peak memory 182660 kb
Host smart-cc5fe008-757b-4d20-8e74-4372a310382b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14286058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.14286058
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2574185633
Short name T293
Test name
Test status
Simulation time 44910249227 ps
CPU time 34.64 seconds
Started Mar 24 12:44:56 PM PDT 24
Finished Mar 24 12:45:30 PM PDT 24
Peak memory 182692 kb
Host smart-b084bdf9-7bcd-4a44-9e84-4f2150ea6ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574185633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2574185633
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1697734777
Short name T427
Test name
Test status
Simulation time 17099339737 ps
CPU time 13.78 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:45:15 PM PDT 24
Peak memory 182708 kb
Host smart-92cf50bd-4182-479d-9586-d79a8d409cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697734777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1697734777
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2212350534
Short name T205
Test name
Test status
Simulation time 162931935558 ps
CPU time 265.9 seconds
Started Mar 24 12:45:02 PM PDT 24
Finished Mar 24 12:49:28 PM PDT 24
Peak memory 182720 kb
Host smart-a5c64d58-0458-495e-8b10-9a69a2e8b536
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212350534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2212350534
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2318571724
Short name T417
Test name
Test status
Simulation time 58593222771 ps
CPU time 51.91 seconds
Started Mar 24 12:44:59 PM PDT 24
Finished Mar 24 12:45:52 PM PDT 24
Peak memory 182692 kb
Host smart-e4642bf7-ad4b-432a-9797-d1b96a3d1b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318571724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2318571724
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4086371490
Short name T314
Test name
Test status
Simulation time 44621021469 ps
CPU time 70.28 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:46:22 PM PDT 24
Peak memory 182680 kb
Host smart-4a1016e8-df1f-409c-8161-60758ccc643c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086371490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4086371490
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2421238236
Short name T386
Test name
Test status
Simulation time 3753873733 ps
CPU time 10.76 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:45:19 PM PDT 24
Peak memory 182684 kb
Host smart-e1bc04a9-0e98-4090-b4f8-fab264c24661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421238236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2421238236
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3506294121
Short name T398
Test name
Test status
Simulation time 130806046 ps
CPU time 0.6 seconds
Started Mar 24 12:45:05 PM PDT 24
Finished Mar 24 12:45:06 PM PDT 24
Peak memory 182392 kb
Host smart-c26b8e25-82e2-4415-8e6a-cd7c24ccadea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506294121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3506294121
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1526235581
Short name T64
Test name
Test status
Simulation time 50573168465 ps
CPU time 18.95 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:44:47 PM PDT 24
Peak memory 182728 kb
Host smart-1017ea74-42b2-4268-bb3e-51fb5fba8d8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526235581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1526235581
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3261821958
Short name T400
Test name
Test status
Simulation time 198917218697 ps
CPU time 253.53 seconds
Started Mar 24 12:44:41 PM PDT 24
Finished Mar 24 12:48:55 PM PDT 24
Peak memory 182700 kb
Host smart-dd56f502-afee-413e-b1c8-491d162669b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261821958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3261821958
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3105700823
Short name T306
Test name
Test status
Simulation time 441220532464 ps
CPU time 221.89 seconds
Started Mar 24 12:44:20 PM PDT 24
Finished Mar 24 12:48:02 PM PDT 24
Peak memory 190896 kb
Host smart-ef009956-6d48-49e4-9092-b1b0f4682a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105700823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3105700823
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1851729854
Short name T341
Test name
Test status
Simulation time 68053255176 ps
CPU time 22.73 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:36 PM PDT 24
Peak memory 182548 kb
Host smart-61520806-6a7b-4da6-a645-98b2eabeb921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851729854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1851729854
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.4139014361
Short name T338
Test name
Test status
Simulation time 56061873810 ps
CPU time 99.98 seconds
Started Mar 24 12:45:00 PM PDT 24
Finished Mar 24 12:46:41 PM PDT 24
Peak memory 190864 kb
Host smart-3d88e10f-a073-4cf6-ad40-20d3f055f13c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139014361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.4139014361
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.4281735696
Short name T329
Test name
Test status
Simulation time 10866139779 ps
CPU time 37.53 seconds
Started Mar 24 12:45:02 PM PDT 24
Finished Mar 24 12:45:40 PM PDT 24
Peak memory 182712 kb
Host smart-4ca54937-abdf-4d69-9a32-897280da505a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281735696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4281735696
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2883198741
Short name T232
Test name
Test status
Simulation time 266275110207 ps
CPU time 169.45 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:47:54 PM PDT 24
Peak memory 190872 kb
Host smart-0c6188b6-da85-477b-9765-2f47db934263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883198741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2883198741
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2174067075
Short name T109
Test name
Test status
Simulation time 50486462502 ps
CPU time 79.74 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:46:24 PM PDT 24
Peak memory 190812 kb
Host smart-f4fdd818-3578-448a-b909-a9484b31d8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174067075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2174067075
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.4068302862
Short name T146
Test name
Test status
Simulation time 31457232128 ps
CPU time 54.59 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 182692 kb
Host smart-47d4a536-3465-4075-a8b5-f7ecbdaa9e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068302862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4068302862
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.567964155
Short name T128
Test name
Test status
Simulation time 494978131341 ps
CPU time 1454.46 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 01:09:21 PM PDT 24
Peak memory 190888 kb
Host smart-e1f31208-052d-40b7-be0c-8082a4e147f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567964155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.567964155
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.265978691
Short name T286
Test name
Test status
Simulation time 96210863028 ps
CPU time 407.25 seconds
Started Mar 24 12:44:59 PM PDT 24
Finished Mar 24 12:51:46 PM PDT 24
Peak memory 190880 kb
Host smart-969c54fa-fd8c-4323-a7fc-f7bf8be5b445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265978691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.265978691
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.90216744
Short name T118
Test name
Test status
Simulation time 696071774828 ps
CPU time 310.3 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:50:20 PM PDT 24
Peak memory 190904 kb
Host smart-40d1456f-8e55-47d6-8f67-8eaf82463e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90216744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.90216744
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3171120938
Short name T445
Test name
Test status
Simulation time 30757436986 ps
CPU time 49.21 seconds
Started Mar 24 12:44:20 PM PDT 24
Finished Mar 24 12:45:10 PM PDT 24
Peak memory 182724 kb
Host smart-43dba011-7ad9-4728-aa4b-5c4de9923bea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171120938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3171120938
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3242725727
Short name T350
Test name
Test status
Simulation time 225503714755 ps
CPU time 152.3 seconds
Started Mar 24 12:44:26 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 182700 kb
Host smart-0c527458-857a-4aec-8a27-7826610b82c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242725727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3242725727
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3833149876
Short name T103
Test name
Test status
Simulation time 136053506041 ps
CPU time 497.41 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:52:45 PM PDT 24
Peak memory 190808 kb
Host smart-88c857f1-ac89-4d00-bd28-f8e8e2405282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833149876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3833149876
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1970480382
Short name T393
Test name
Test status
Simulation time 315065665 ps
CPU time 0.64 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:45:16 PM PDT 24
Peak memory 182436 kb
Host smart-e9ab9e7a-09b6-463c-beb6-34fb935765d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970480382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1970480382
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3144402364
Short name T170
Test name
Test status
Simulation time 412544822997 ps
CPU time 828.55 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:58:59 PM PDT 24
Peak memory 190888 kb
Host smart-e3c2a253-1849-4b58-a224-6eaeffe26bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144402364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3144402364
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2315391728
Short name T326
Test name
Test status
Simulation time 95721048994 ps
CPU time 509.29 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:53:40 PM PDT 24
Peak memory 190880 kb
Host smart-b9627abf-a5e4-47cf-8e49-06f6438d03f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315391728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2315391728
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1965854235
Short name T408
Test name
Test status
Simulation time 43918957128 ps
CPU time 69.22 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 182624 kb
Host smart-760bf2d4-c0a2-4aa9-9db8-dec2b2b64fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965854235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1965854235
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3878311515
Short name T309
Test name
Test status
Simulation time 40166056503 ps
CPU time 1474.51 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 01:09:36 PM PDT 24
Peak memory 182724 kb
Host smart-9081d520-7a90-4558-937a-b218f03ac127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878311515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3878311515
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1848339884
Short name T265
Test name
Test status
Simulation time 349145794186 ps
CPU time 1352.03 seconds
Started Mar 24 12:45:02 PM PDT 24
Finished Mar 24 01:07:34 PM PDT 24
Peak memory 190844 kb
Host smart-ff5aa201-b20b-40d6-8ffc-120f81f863fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848339884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1848339884
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.55869242
Short name T233
Test name
Test status
Simulation time 273373961393 ps
CPU time 223.82 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 190848 kb
Host smart-4c545a1b-ded8-4ebe-9ddb-a7506b5bf675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55869242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.55869242
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2005457807
Short name T447
Test name
Test status
Simulation time 694056011049 ps
CPU time 362.74 seconds
Started Mar 24 12:45:02 PM PDT 24
Finished Mar 24 12:51:05 PM PDT 24
Peak memory 190916 kb
Host smart-a7c7b85f-2c6d-4f2d-afc7-ab2a1a96eead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005457807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2005457807
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2424871392
Short name T130
Test name
Test status
Simulation time 35507634636 ps
CPU time 62.6 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 182688 kb
Host smart-9f0c0ed0-cea3-4364-a3c7-7f8905e57728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424871392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2424871392
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.823320741
Short name T208
Test name
Test status
Simulation time 850077266400 ps
CPU time 382.18 seconds
Started Mar 24 12:44:50 PM PDT 24
Finished Mar 24 12:51:13 PM PDT 24
Peak memory 190864 kb
Host smart-3d8bbd5f-72b5-423d-b946-5bf84e42cf13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823320741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.823320741
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.4124739216
Short name T307
Test name
Test status
Simulation time 770364450379 ps
CPU time 592.78 seconds
Started Mar 24 12:44:48 PM PDT 24
Finished Mar 24 12:54:42 PM PDT 24
Peak memory 182716 kb
Host smart-a1b462d1-daa4-470a-afce-56829174fcaf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124739216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.4124739216
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4288205221
Short name T390
Test name
Test status
Simulation time 164223456506 ps
CPU time 117.19 seconds
Started Mar 24 12:44:46 PM PDT 24
Finished Mar 24 12:46:45 PM PDT 24
Peak memory 182704 kb
Host smart-cfbe21ce-f1b0-477a-9de2-52231ae94775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288205221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4288205221
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3240420013
Short name T308
Test name
Test status
Simulation time 127514617441 ps
CPU time 308.44 seconds
Started Mar 24 12:44:47 PM PDT 24
Finished Mar 24 12:50:01 PM PDT 24
Peak memory 192940 kb
Host smart-72231cd9-a8b4-418d-96af-2e4a890dc42c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240420013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3240420013
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2726833490
Short name T441
Test name
Test status
Simulation time 340416565 ps
CPU time 0.95 seconds
Started Mar 24 12:44:36 PM PDT 24
Finished Mar 24 12:44:37 PM PDT 24
Peak memory 182492 kb
Host smart-d78d153b-a225-4688-93d1-74c8238249c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726833490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2726833490
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2939346719
Short name T193
Test name
Test status
Simulation time 44987535309 ps
CPU time 87.86 seconds
Started Mar 24 12:45:02 PM PDT 24
Finished Mar 24 12:46:30 PM PDT 24
Peak memory 182604 kb
Host smart-7befcf6f-2228-4719-9cb6-e6e99d01d038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939346719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2939346719
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2726264934
Short name T334
Test name
Test status
Simulation time 29474520802 ps
CPU time 27.11 seconds
Started Mar 24 12:45:05 PM PDT 24
Finished Mar 24 12:45:32 PM PDT 24
Peak memory 182704 kb
Host smart-71debbfe-26ac-47fe-9764-5ca0e4090177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726264934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2726264934
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1777975517
Short name T10
Test name
Test status
Simulation time 137808930889 ps
CPU time 452.39 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:52:30 PM PDT 24
Peak memory 190908 kb
Host smart-4cfe4b5d-1779-4603-848a-1d2171f54b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777975517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1777975517
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3841343029
Short name T431
Test name
Test status
Simulation time 40130914909 ps
CPU time 84.69 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:46:38 PM PDT 24
Peak memory 190888 kb
Host smart-1050a0f8-d672-49d4-a9a9-3adb3b1f2ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841343029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3841343029
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2380481853
Short name T369
Test name
Test status
Simulation time 549703475 ps
CPU time 2.02 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:45:06 PM PDT 24
Peak memory 182540 kb
Host smart-009d62ab-e61d-4b31-834d-79e02ceed2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380481853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2380481853
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.679876777
Short name T122
Test name
Test status
Simulation time 167925707877 ps
CPU time 307.29 seconds
Started Mar 24 12:44:56 PM PDT 24
Finished Mar 24 12:50:04 PM PDT 24
Peak memory 190892 kb
Host smart-12a8015d-5bf6-49a7-816d-108a9688ca76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679876777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.679876777
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.199178134
Short name T331
Test name
Test status
Simulation time 241011528367 ps
CPU time 389.18 seconds
Started Mar 24 12:45:00 PM PDT 24
Finished Mar 24 12:51:30 PM PDT 24
Peak memory 190900 kb
Host smart-adb7bf9b-f671-4f90-9150-b2ec501c04f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199178134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.199178134
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1606784453
Short name T280
Test name
Test status
Simulation time 139710300123 ps
CPU time 1276.96 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 01:06:30 PM PDT 24
Peak memory 190848 kb
Host smart-b85305d7-79f3-4adf-9d35-ba956f29e35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606784453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1606784453
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2307907390
Short name T236
Test name
Test status
Simulation time 2265156388496 ps
CPU time 789.48 seconds
Started Mar 24 12:45:02 PM PDT 24
Finished Mar 24 12:58:11 PM PDT 24
Peak memory 193340 kb
Host smart-46faa5d9-8934-4c1f-ba03-5d465cfca919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307907390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2307907390
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1357243065
Short name T320
Test name
Test status
Simulation time 1432963585910 ps
CPU time 784.41 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:57:33 PM PDT 24
Peak memory 182620 kb
Host smart-1af90bee-cf26-4791-b4e0-10109a676671
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357243065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1357243065
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.4063025898
Short name T395
Test name
Test status
Simulation time 169213867125 ps
CPU time 214.15 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 12:47:58 PM PDT 24
Peak memory 182708 kb
Host smart-da12b2a6-01c2-4ee7-aa58-2cf69ec8f59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063025898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.4063025898
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1751924274
Short name T404
Test name
Test status
Simulation time 71247488395 ps
CPU time 722.97 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:56:32 PM PDT 24
Peak memory 190852 kb
Host smart-9784503b-5a0d-4450-8ccd-80f2325881d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751924274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1751924274
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.9837885
Short name T347
Test name
Test status
Simulation time 818363349 ps
CPU time 1.01 seconds
Started Mar 24 12:44:34 PM PDT 24
Finished Mar 24 12:44:35 PM PDT 24
Peak memory 182436 kb
Host smart-f0459990-ac79-4100-8993-95e3d1bf3516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9837885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.9837885
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3186162854
Short name T362
Test name
Test status
Simulation time 66632248608 ps
CPU time 98.46 seconds
Started Mar 24 12:44:23 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 182700 kb
Host smart-75a669df-6559-4f85-bb72-9beef3d6a408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186162854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3186162854
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3088626171
Short name T180
Test name
Test status
Simulation time 612650792902 ps
CPU time 527.1 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:53:57 PM PDT 24
Peak memory 190836 kb
Host smart-83824d11-48fe-4fac-a0be-4aaf409311e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088626171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3088626171
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.512405654
Short name T269
Test name
Test status
Simulation time 46404809064 ps
CPU time 284.03 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:49:57 PM PDT 24
Peak memory 190828 kb
Host smart-7642a75b-6d5f-48e3-911e-6a46db61b4a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512405654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.512405654
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.4172377678
Short name T195
Test name
Test status
Simulation time 100762996961 ps
CPU time 410.22 seconds
Started Mar 24 12:44:55 PM PDT 24
Finished Mar 24 12:51:45 PM PDT 24
Peak memory 190840 kb
Host smart-bec8be71-7023-4a8f-80f8-440ad0bc1045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172377678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.4172377678
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.763359640
Short name T403
Test name
Test status
Simulation time 159191136034 ps
CPU time 1108.39 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 01:03:26 PM PDT 24
Peak memory 190884 kb
Host smart-fa01a7b6-2a50-4d7d-b4c3-953c667ed08c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763359640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.763359640
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.778031776
Short name T259
Test name
Test status
Simulation time 425768491916 ps
CPU time 183.97 seconds
Started Mar 24 12:44:57 PM PDT 24
Finished Mar 24 12:48:02 PM PDT 24
Peak memory 190888 kb
Host smart-bb5e9552-36b0-44d0-8cc4-e3caee833c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778031776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.778031776
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.620454733
Short name T106
Test name
Test status
Simulation time 525062134128 ps
CPU time 259.37 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:49:28 PM PDT 24
Peak memory 190940 kb
Host smart-e76a4710-d110-4f61-9ab8-e1e0b80f548a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620454733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.620454733
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2815612185
Short name T211
Test name
Test status
Simulation time 271724218889 ps
CPU time 243.45 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:49:15 PM PDT 24
Peak memory 190864 kb
Host smart-1c612402-3335-444e-b08f-f7b13a2ad89e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815612185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2815612185
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.747622357
Short name T239
Test name
Test status
Simulation time 117076820131 ps
CPU time 312.36 seconds
Started Mar 24 12:45:24 PM PDT 24
Finished Mar 24 12:50:36 PM PDT 24
Peak memory 190864 kb
Host smart-9dd113df-08f9-445b-8424-73583889b1d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747622357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.747622357
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.494360694
Short name T277
Test name
Test status
Simulation time 63451222100 ps
CPU time 103.5 seconds
Started Mar 24 12:44:39 PM PDT 24
Finished Mar 24 12:46:22 PM PDT 24
Peak memory 182724 kb
Host smart-5cb0fbf8-1698-4855-93ce-73a976a04a60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494360694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.494360694
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1622577174
Short name T432
Test name
Test status
Simulation time 516043598779 ps
CPU time 217.4 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:47:53 PM PDT 24
Peak memory 182700 kb
Host smart-e770a380-0c9b-42fb-8216-108c76168ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622577174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1622577174
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.976142509
Short name T337
Test name
Test status
Simulation time 249874147258 ps
CPU time 141.91 seconds
Started Mar 24 12:44:48 PM PDT 24
Finished Mar 24 12:47:10 PM PDT 24
Peak memory 182704 kb
Host smart-0e5c0d23-907f-48c6-bb34-5ab36fc2b0fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976142509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.976142509
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2489954531
Short name T11
Test name
Test status
Simulation time 143050415 ps
CPU time 0.67 seconds
Started Mar 24 12:44:37 PM PDT 24
Finished Mar 24 12:44:38 PM PDT 24
Peak memory 182484 kb
Host smart-9785b5e3-174a-477b-bd2b-47eaf5b71a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489954531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2489954531
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.160207690
Short name T444
Test name
Test status
Simulation time 376009394361 ps
CPU time 246.27 seconds
Started Mar 24 12:44:56 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 190848 kb
Host smart-ad27b020-b5fa-4d5e-9022-4dfbff1395fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160207690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.160207690
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2243550455
Short name T158
Test name
Test status
Simulation time 110946397212 ps
CPU time 94.3 seconds
Started Mar 24 12:45:01 PM PDT 24
Finished Mar 24 12:46:35 PM PDT 24
Peak memory 190852 kb
Host smart-eb93165d-c178-4c4d-add0-f9dcc70e19f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243550455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2243550455
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1975700190
Short name T175
Test name
Test status
Simulation time 564784081674 ps
CPU time 815.07 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:58:45 PM PDT 24
Peak memory 182740 kb
Host smart-add440b7-ecc3-4fc1-b715-46d6af12f258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975700190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1975700190
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2458693600
Short name T161
Test name
Test status
Simulation time 185051271906 ps
CPU time 329.58 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:50:42 PM PDT 24
Peak memory 190844 kb
Host smart-44d45c1f-e244-4284-ac64-667df40554d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458693600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2458693600
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1102981956
Short name T186
Test name
Test status
Simulation time 89991426705 ps
CPU time 155.9 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:47:51 PM PDT 24
Peak memory 190816 kb
Host smart-a74981b8-2aec-4d8f-b18c-d82c465669fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102981956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1102981956
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.404024028
Short name T294
Test name
Test status
Simulation time 49816480295 ps
CPU time 53.72 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 192660 kb
Host smart-b67f826f-8662-47cb-9b96-a1363330e532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404024028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.404024028
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1184119066
Short name T251
Test name
Test status
Simulation time 24673139652 ps
CPU time 21.92 seconds
Started Mar 24 12:45:18 PM PDT 24
Finished Mar 24 12:45:40 PM PDT 24
Peak memory 182692 kb
Host smart-7f8886bc-113e-4e6b-bccf-68b7b45fd0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184119066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1184119066
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.663187070
Short name T406
Test name
Test status
Simulation time 11046625930 ps
CPU time 16.45 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:45:28 PM PDT 24
Peak memory 182520 kb
Host smart-d9646bcf-ddb1-484f-825e-138d1b179b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663187070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.663187070
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2436651190
Short name T151
Test name
Test status
Simulation time 1038626999831 ps
CPU time 389.91 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:51:42 PM PDT 24
Peak memory 193480 kb
Host smart-bbc7198d-68cc-46d1-84a0-48056930f5e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436651190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2436651190
Directory /workspace/98.rv_timer_random/latest
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