Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 583
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2407913777 Mar 26 02:32:04 PM PDT 24 Mar 26 02:32:05 PM PDT 24 24996667 ps
T510 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3127151931 Mar 26 02:32:05 PM PDT 24 Mar 26 02:32:06 PM PDT 24 55729236 ps
T511 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4007580321 Mar 26 02:31:53 PM PDT 24 Mar 26 02:31:54 PM PDT 24 332025869 ps
T512 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2691780438 Mar 26 02:31:53 PM PDT 24 Mar 26 02:31:54 PM PDT 24 19335568 ps
T513 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3451758510 Mar 26 02:31:52 PM PDT 24 Mar 26 02:31:53 PM PDT 24 32934135 ps
T514 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.491852072 Mar 26 02:31:53 PM PDT 24 Mar 26 02:31:54 PM PDT 24 241678605 ps
T515 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2173931254 Mar 26 02:31:39 PM PDT 24 Mar 26 02:31:40 PM PDT 24 74209257 ps
T516 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3005383035 Mar 26 02:31:55 PM PDT 24 Mar 26 02:31:56 PM PDT 24 430658667 ps
T85 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1891875063 Mar 26 02:31:52 PM PDT 24 Mar 26 02:31:53 PM PDT 24 12090576 ps
T517 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3181277916 Mar 26 02:31:25 PM PDT 24 Mar 26 02:31:26 PM PDT 24 15362301 ps
T518 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3431121575 Mar 26 02:31:26 PM PDT 24 Mar 26 02:31:27 PM PDT 24 17804844 ps
T519 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3566415429 Mar 26 02:31:23 PM PDT 24 Mar 26 02:31:26 PM PDT 24 238579242 ps
T520 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4044722180 Mar 26 02:31:39 PM PDT 24 Mar 26 02:31:40 PM PDT 24 30140968 ps
T521 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1297854099 Mar 26 02:32:07 PM PDT 24 Mar 26 02:32:07 PM PDT 24 57522578 ps
T522 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.301036251 Mar 26 02:31:23 PM PDT 24 Mar 26 02:31:26 PM PDT 24 289640821 ps
T523 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2567530879 Mar 26 02:32:13 PM PDT 24 Mar 26 02:32:14 PM PDT 24 36853670 ps
T524 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2219285708 Mar 26 02:32:04 PM PDT 24 Mar 26 02:32:05 PM PDT 24 105718809 ps
T525 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.744168534 Mar 26 02:31:52 PM PDT 24 Mar 26 02:31:54 PM PDT 24 261592800 ps
T526 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2773616021 Mar 26 02:30:57 PM PDT 24 Mar 26 02:30:58 PM PDT 24 103447279 ps
T527 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1297778582 Mar 26 02:31:38 PM PDT 24 Mar 26 02:31:39 PM PDT 24 33885155 ps
T86 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3521411903 Mar 26 02:31:13 PM PDT 24 Mar 26 02:31:14 PM PDT 24 55358085 ps
T528 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.205285308 Mar 26 02:30:45 PM PDT 24 Mar 26 02:30:47 PM PDT 24 1639065467 ps
T529 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1805120359 Mar 26 02:31:52 PM PDT 24 Mar 26 02:31:53 PM PDT 24 73138834 ps
T530 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.877085687 Mar 26 02:32:06 PM PDT 24 Mar 26 02:32:07 PM PDT 24 27593502 ps
T531 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.647181862 Mar 26 02:30:56 PM PDT 24 Mar 26 02:30:57 PM PDT 24 12521000 ps
T532 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.673109889 Mar 26 02:30:56 PM PDT 24 Mar 26 02:30:57 PM PDT 24 121123704 ps
T533 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2354171224 Mar 26 02:31:24 PM PDT 24 Mar 26 02:31:25 PM PDT 24 38616826 ps
T534 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1355004321 Mar 26 02:31:39 PM PDT 24 Mar 26 02:31:40 PM PDT 24 81580837 ps
T535 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3010018585 Mar 26 02:32:06 PM PDT 24 Mar 26 02:32:07 PM PDT 24 14186413 ps
T536 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.551424103 Mar 26 02:32:15 PM PDT 24 Mar 26 02:32:15 PM PDT 24 54262169 ps
T537 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.319692009 Mar 26 02:32:06 PM PDT 24 Mar 26 02:32:06 PM PDT 24 19050614 ps
T538 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1927398695 Mar 26 02:32:05 PM PDT 24 Mar 26 02:32:06 PM PDT 24 114560235 ps
T539 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4271644084 Mar 26 02:32:10 PM PDT 24 Mar 26 02:32:11 PM PDT 24 139990485 ps
T540 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.259986690 Mar 26 02:31:14 PM PDT 24 Mar 26 02:31:17 PM PDT 24 192757332 ps
T541 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4218020713 Mar 26 02:30:56 PM PDT 24 Mar 26 02:30:57 PM PDT 24 16309774 ps
T542 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3007524798 Mar 26 02:31:12 PM PDT 24 Mar 26 02:31:13 PM PDT 24 59576597 ps
T543 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3790413639 Mar 26 02:31:25 PM PDT 24 Mar 26 02:31:26 PM PDT 24 325024049 ps
T544 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3881542713 Mar 26 02:32:05 PM PDT 24 Mar 26 02:32:06 PM PDT 24 34862836 ps
T545 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3182786179 Mar 26 02:32:05 PM PDT 24 Mar 26 02:32:06 PM PDT 24 13309807 ps
T546 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1355139704 Mar 26 02:31:51 PM PDT 24 Mar 26 02:31:53 PM PDT 24 45869477 ps
T547 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.495279593 Mar 26 02:32:04 PM PDT 24 Mar 26 02:32:05 PM PDT 24 17309069 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3874373529 Mar 26 02:31:13 PM PDT 24 Mar 26 02:31:14 PM PDT 24 133021941 ps
T549 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4203133713 Mar 26 02:30:56 PM PDT 24 Mar 26 02:30:57 PM PDT 24 44664474 ps
T550 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.675536194 Mar 26 02:32:07 PM PDT 24 Mar 26 02:32:08 PM PDT 24 50577630 ps
T551 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.84271455 Mar 26 02:31:13 PM PDT 24 Mar 26 02:31:14 PM PDT 24 67638264 ps
T552 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.972570866 Mar 26 02:31:54 PM PDT 24 Mar 26 02:31:55 PM PDT 24 43386417 ps
T553 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3456140856 Mar 26 02:32:18 PM PDT 24 Mar 26 02:32:18 PM PDT 24 14289393 ps
T554 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.640002506 Mar 26 02:32:03 PM PDT 24 Mar 26 02:32:04 PM PDT 24 47847559 ps
T87 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2558193771 Mar 26 02:31:53 PM PDT 24 Mar 26 02:31:54 PM PDT 24 41573699 ps
T555 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4061886574 Mar 26 02:31:23 PM PDT 24 Mar 26 02:31:24 PM PDT 24 84543574 ps
T556 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.165783656 Mar 26 02:31:54 PM PDT 24 Mar 26 02:31:55 PM PDT 24 37295460 ps
T92 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2184929131 Mar 26 02:30:56 PM PDT 24 Mar 26 02:30:57 PM PDT 24 17778547 ps
T557 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1144777514 Mar 26 02:32:06 PM PDT 24 Mar 26 02:32:06 PM PDT 24 56832713 ps
T88 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.306924117 Mar 26 02:31:54 PM PDT 24 Mar 26 02:31:54 PM PDT 24 11449420 ps
T558 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1992122589 Mar 26 02:30:57 PM PDT 24 Mar 26 02:30:58 PM PDT 24 80037316 ps
T559 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.772184574 Mar 26 02:32:02 PM PDT 24 Mar 26 02:32:03 PM PDT 24 14754669 ps
T560 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2637656241 Mar 26 02:31:51 PM PDT 24 Mar 26 02:31:53 PM PDT 24 17035709 ps
T561 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3315237474 Mar 26 02:31:25 PM PDT 24 Mar 26 02:31:26 PM PDT 24 99280557 ps
T562 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3933189355 Mar 26 02:31:12 PM PDT 24 Mar 26 02:31:14 PM PDT 24 101994032 ps
T563 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2225842613 Mar 26 02:32:06 PM PDT 24 Mar 26 02:32:07 PM PDT 24 106893786 ps
T564 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2738405120 Mar 26 02:32:03 PM PDT 24 Mar 26 02:32:04 PM PDT 24 14738588 ps
T565 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1569321501 Mar 26 02:31:11 PM PDT 24 Mar 26 02:31:12 PM PDT 24 293131308 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4016982468 Mar 26 02:31:51 PM PDT 24 Mar 26 02:31:54 PM PDT 24 46543028 ps
T567 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2121216699 Mar 26 02:31:54 PM PDT 24 Mar 26 02:31:55 PM PDT 24 53881907 ps
T568 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1856429968 Mar 26 02:31:24 PM PDT 24 Mar 26 02:31:26 PM PDT 24 133640792 ps
T569 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2346793396 Mar 26 02:30:44 PM PDT 24 Mar 26 02:30:46 PM PDT 24 156270689 ps
T570 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3648747267 Mar 26 02:31:51 PM PDT 24 Mar 26 02:31:55 PM PDT 24 44103074 ps
T571 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3216688679 Mar 26 02:32:03 PM PDT 24 Mar 26 02:32:04 PM PDT 24 13355634 ps
T90 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3047075722 Mar 26 02:30:55 PM PDT 24 Mar 26 02:30:58 PM PDT 24 1101187918 ps
T91 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1371907269 Mar 26 02:31:23 PM PDT 24 Mar 26 02:31:24 PM PDT 24 63741269 ps
T572 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3864424858 Mar 26 02:32:04 PM PDT 24 Mar 26 02:32:04 PM PDT 24 62646519 ps
T573 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1953018610 Mar 26 02:31:53 PM PDT 24 Mar 26 02:31:55 PM PDT 24 367834669 ps
T574 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2043913637 Mar 26 02:31:13 PM PDT 24 Mar 26 02:31:14 PM PDT 24 20998289 ps
T575 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3551575804 Mar 26 02:31:52 PM PDT 24 Mar 26 02:31:53 PM PDT 24 17949448 ps
T576 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2868312510 Mar 26 02:32:10 PM PDT 24 Mar 26 02:32:11 PM PDT 24 16069106 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3211127848 Mar 26 02:31:13 PM PDT 24 Mar 26 02:31:14 PM PDT 24 39518197 ps
T577 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.338457679 Mar 26 02:32:04 PM PDT 24 Mar 26 02:32:04 PM PDT 24 16210217 ps
T578 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3293525673 Mar 26 02:31:24 PM PDT 24 Mar 26 02:31:26 PM PDT 24 65587204 ps
T579 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1205433427 Mar 26 02:32:07 PM PDT 24 Mar 26 02:32:07 PM PDT 24 21372960 ps
T580 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.823047303 Mar 26 02:31:51 PM PDT 24 Mar 26 02:31:54 PM PDT 24 215312052 ps
T581 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1718552869 Mar 26 02:30:56 PM PDT 24 Mar 26 02:30:57 PM PDT 24 18390720 ps
T582 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1401187010 Mar 26 02:31:13 PM PDT 24 Mar 26 02:31:14 PM PDT 24 43009152 ps
T583 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2020018398 Mar 26 02:32:05 PM PDT 24 Mar 26 02:32:05 PM PDT 24 24741800 ps

Test location /workspace/coverage/default/51.rv_timer_random.3501664622
Short name T7
Test name
Test status
Simulation time 492158241176 ps
CPU time 354.57 seconds
Started Mar 26 02:34:52 PM PDT 24
Finished Mar 26 02:40:47 PM PDT 24
Peak memory 190832 kb
Host smart-12f02cb2-30cd-4b30-9905-c643f21e6566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501664622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3501664622
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.1713379304
Short name T11
Test name
Test status
Simulation time 54869147416 ps
CPU time 615.49 seconds
Started Mar 26 02:33:04 PM PDT 24
Finished Mar 26 02:43:20 PM PDT 24
Peak memory 205528 kb
Host smart-618cd354-4a9f-4c62-9de0-891fb87e70cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713379304 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.1713379304
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2607193813
Short name T6
Test name
Test status
Simulation time 1794513873114 ps
CPU time 1458.91 seconds
Started Mar 26 02:33:55 PM PDT 24
Finished Mar 26 02:58:14 PM PDT 24
Peak memory 190788 kb
Host smart-2d50a6ff-2c18-45f0-af8b-37d5fd4a6a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607193813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2607193813
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.326411717
Short name T27
Test name
Test status
Simulation time 109120329 ps
CPU time 1.37 seconds
Started Mar 26 02:30:57 PM PDT 24
Finished Mar 26 02:30:58 PM PDT 24
Peak memory 183556 kb
Host smart-f64ce7a8-6e04-4039-9083-002646ebaa61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326411717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.326411717
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1421328431
Short name T66
Test name
Test status
Simulation time 307760093497 ps
CPU time 1327.73 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:54:54 PM PDT 24
Peak memory 190856 kb
Host smart-9e7e5e6e-933a-4eee-9b8e-2a867fbc97f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421328431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1421328431
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1756778635
Short name T151
Test name
Test status
Simulation time 1081186094666 ps
CPU time 3064.99 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 03:23:23 PM PDT 24
Peak memory 190828 kb
Host smart-92df435a-36c8-43c9-93ae-3dbd8daf0cf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756778635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1756778635
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1845406300
Short name T206
Test name
Test status
Simulation time 804938147811 ps
CPU time 829.56 seconds
Started Mar 26 02:32:55 PM PDT 24
Finished Mar 26 02:46:46 PM PDT 24
Peak memory 190912 kb
Host smart-7d23c314-411b-49e0-9091-d7a3c670ac47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845406300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1845406300
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.547993911
Short name T46
Test name
Test status
Simulation time 17624553 ps
CPU time 0.59 seconds
Started Mar 26 02:31:39 PM PDT 24
Finished Mar 26 02:31:39 PM PDT 24
Peak memory 182780 kb
Host smart-70999ac5-3bea-471a-aa87-9221c1e65447
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547993911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.547993911
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3821522870
Short name T141
Test name
Test status
Simulation time 1859462845844 ps
CPU time 2525.4 seconds
Started Mar 26 02:32:46 PM PDT 24
Finished Mar 26 03:14:53 PM PDT 24
Peak memory 195584 kb
Host smart-ba1337be-bbc4-41bc-bd9e-e3b95bad2eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821522870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3821522870
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4266895556
Short name T297
Test name
Test status
Simulation time 3799279194467 ps
CPU time 2594.16 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 03:16:02 PM PDT 24
Peak memory 190792 kb
Host smart-301e57b0-4624-46e4-9880-ab61df10c70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266895556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4266895556
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1144479340
Short name T248
Test name
Test status
Simulation time 2802702268174 ps
CPU time 1433.41 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:56:28 PM PDT 24
Peak memory 190888 kb
Host smart-6013267e-1cd9-4201-97ad-0eea14b64fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144479340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1144479340
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1573906091
Short name T224
Test name
Test status
Simulation time 1206427958597 ps
CPU time 1388.64 seconds
Started Mar 26 02:32:29 PM PDT 24
Finished Mar 26 02:55:38 PM PDT 24
Peak memory 190896 kb
Host smart-b4250a03-3103-4dd1-b534-924091d08604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573906091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1573906091
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2157584257
Short name T172
Test name
Test status
Simulation time 628537993929 ps
CPU time 2078.25 seconds
Started Mar 26 02:34:06 PM PDT 24
Finished Mar 26 03:08:45 PM PDT 24
Peak memory 195752 kb
Host smart-2642db64-3413-4d78-913f-ed152ed91b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157584257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2157584257
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1545285192
Short name T18
Test name
Test status
Simulation time 35630477 ps
CPU time 0.73 seconds
Started Mar 26 02:32:18 PM PDT 24
Finished Mar 26 02:32:19 PM PDT 24
Peak memory 213120 kb
Host smart-7636e876-ea95-4776-98c3-4d2c20b3912d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545285192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1545285192
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1831003097
Short name T168
Test name
Test status
Simulation time 391854889446 ps
CPU time 764.58 seconds
Started Mar 26 02:32:14 PM PDT 24
Finished Mar 26 02:44:59 PM PDT 24
Peak memory 190860 kb
Host smart-1e504b80-593d-4e47-b1d1-6b68a5f41dac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831003097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1831003097
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.586738436
Short name T185
Test name
Test status
Simulation time 1486976450541 ps
CPU time 833.58 seconds
Started Mar 26 02:33:55 PM PDT 24
Finished Mar 26 02:47:49 PM PDT 24
Peak memory 195656 kb
Host smart-3691fa3f-3258-41f9-8288-20174786027d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586738436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
586738436
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.481966423
Short name T136
Test name
Test status
Simulation time 1249062462868 ps
CPU time 2317.43 seconds
Started Mar 26 02:34:07 PM PDT 24
Finished Mar 26 03:12:44 PM PDT 24
Peak memory 190844 kb
Host smart-40b29c39-6731-4e7b-8ee8-4fb6382dfcfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481966423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
481966423
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/63.rv_timer_random.3238888853
Short name T19
Test name
Test status
Simulation time 527995841230 ps
CPU time 324.77 seconds
Started Mar 26 02:34:59 PM PDT 24
Finished Mar 26 02:40:25 PM PDT 24
Peak memory 190852 kb
Host smart-3b985074-0d7f-4e0c-b396-09e7a82ccd0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238888853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3238888853
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3511199505
Short name T62
Test name
Test status
Simulation time 2613210327378 ps
CPU time 956.61 seconds
Started Mar 26 02:34:49 PM PDT 24
Finished Mar 26 02:50:47 PM PDT 24
Peak memory 190884 kb
Host smart-fa05a40e-e7b7-46b5-aa13-8fa4c45ab042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511199505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3511199505
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1817839712
Short name T234
Test name
Test status
Simulation time 1714631719710 ps
CPU time 1353.8 seconds
Started Mar 26 02:33:05 PM PDT 24
Finished Mar 26 02:55:39 PM PDT 24
Peak memory 190872 kb
Host smart-f29c7ef9-0cb3-4bd3-a6e8-12f16211a651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817839712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1817839712
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.847763685
Short name T113
Test name
Test status
Simulation time 1229828867963 ps
CPU time 1491.58 seconds
Started Mar 26 02:32:56 PM PDT 24
Finished Mar 26 02:57:48 PM PDT 24
Peak memory 195600 kb
Host smart-f4656a65-84f4-4afc-95f4-182c30ea1e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847763685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
847763685
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.325015171
Short name T114
Test name
Test status
Simulation time 627105043537 ps
CPU time 616.71 seconds
Started Mar 26 02:33:33 PM PDT 24
Finished Mar 26 02:43:52 PM PDT 24
Peak memory 190912 kb
Host smart-9afba509-9580-4666-acbc-cdfb2878f655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325015171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
325015171
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.784810071
Short name T332
Test name
Test status
Simulation time 1486939317177 ps
CPU time 764.32 seconds
Started Mar 26 02:33:44 PM PDT 24
Finished Mar 26 02:46:28 PM PDT 24
Peak memory 195340 kb
Host smart-740357df-4049-41ca-b721-d457c2eed2a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784810071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
784810071
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/107.rv_timer_random.2892623071
Short name T203
Test name
Test status
Simulation time 635944274768 ps
CPU time 848.74 seconds
Started Mar 26 02:35:33 PM PDT 24
Finished Mar 26 02:49:42 PM PDT 24
Peak memory 190820 kb
Host smart-f6fe72c6-45b4-4fa6-918a-40df97ae9320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892623071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2892623071
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2602611601
Short name T53
Test name
Test status
Simulation time 4693675477043 ps
CPU time 912.92 seconds
Started Mar 26 02:32:57 PM PDT 24
Finished Mar 26 02:48:12 PM PDT 24
Peak memory 190892 kb
Host smart-4ec75177-2775-4e1a-a11d-0fd837d16305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602611601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2602611601
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2996504684
Short name T190
Test name
Test status
Simulation time 4772888461005 ps
CPU time 3668.02 seconds
Started Mar 26 02:33:33 PM PDT 24
Finished Mar 26 03:34:44 PM PDT 24
Peak memory 190868 kb
Host smart-d04f5f02-6f13-4bd3-9970-1399c9b9fd22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996504684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2996504684
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.3896228791
Short name T170
Test name
Test status
Simulation time 921264295570 ps
CPU time 612.55 seconds
Started Mar 26 02:32:20 PM PDT 24
Finished Mar 26 02:42:33 PM PDT 24
Peak memory 190048 kb
Host smart-4acde9bf-2739-4293-b97c-20084e15e625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896228791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3896228791
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3887397983
Short name T147
Test name
Test status
Simulation time 661060892069 ps
CPU time 328.43 seconds
Started Mar 26 02:34:19 PM PDT 24
Finished Mar 26 02:39:47 PM PDT 24
Peak memory 182692 kb
Host smart-ab68f70f-b7cf-43ab-abdf-9a0517abbc2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887397983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3887397983
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.170246619
Short name T83
Test name
Test status
Simulation time 63671038 ps
CPU time 0.58 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:13 PM PDT 24
Peak memory 182848 kb
Host smart-a81065e6-aceb-41aa-bfaf-dedca5258d03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170246619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.170246619
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.326655548
Short name T216
Test name
Test status
Simulation time 823632104300 ps
CPU time 3097.81 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 03:24:13 PM PDT 24
Peak memory 194980 kb
Host smart-6df7758a-f4c6-48a6-bba5-cef6707fb315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326655548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
326655548
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/126.rv_timer_random.328555900
Short name T122
Test name
Test status
Simulation time 737029966176 ps
CPU time 445.09 seconds
Started Mar 26 02:35:53 PM PDT 24
Finished Mar 26 02:43:19 PM PDT 24
Peak memory 190816 kb
Host smart-c7c91a12-6206-4d93-83d1-7eaa5a78915d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328555900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.328555900
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2982170407
Short name T201
Test name
Test status
Simulation time 347038310997 ps
CPU time 355.08 seconds
Started Mar 26 02:36:13 PM PDT 24
Finished Mar 26 02:42:08 PM PDT 24
Peak memory 190880 kb
Host smart-cdec8239-0b74-44eb-baaa-a651409cdb36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982170407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2982170407
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2997900620
Short name T10
Test name
Test status
Simulation time 3892798749543 ps
CPU time 2470.6 seconds
Started Mar 26 02:32:46 PM PDT 24
Finished Mar 26 03:13:59 PM PDT 24
Peak memory 196504 kb
Host smart-a77fd02d-039d-4543-bff1-8591013a6be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997900620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2997900620
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_random.1927453613
Short name T187
Test name
Test status
Simulation time 455464861714 ps
CPU time 824.8 seconds
Started Mar 26 02:32:46 PM PDT 24
Finished Mar 26 02:46:32 PM PDT 24
Peak memory 190852 kb
Host smart-d7740f9a-38a8-4785-bc8d-dd03ab96c510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927453613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1927453613
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3759506777
Short name T214
Test name
Test status
Simulation time 665365394574 ps
CPU time 1418.36 seconds
Started Mar 26 02:34:43 PM PDT 24
Finished Mar 26 02:58:22 PM PDT 24
Peak memory 190880 kb
Host smart-9a4e9a9c-0d9f-4e27-a7ae-50cec2dc58f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759506777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3759506777
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/87.rv_timer_random.3182207263
Short name T289
Test name
Test status
Simulation time 133374652355 ps
CPU time 1166.6 seconds
Started Mar 26 02:35:24 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 190872 kb
Host smart-91db650c-8724-4e5b-bdc1-35c2450595f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182207263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3182207263
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2161825771
Short name T162
Test name
Test status
Simulation time 386894501746 ps
CPU time 1923.63 seconds
Started Mar 26 02:35:36 PM PDT 24
Finished Mar 26 03:07:40 PM PDT 24
Peak memory 190876 kb
Host smart-dfeba768-b773-4c6d-be2b-a49534326a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161825771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2161825771
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3260012494
Short name T251
Test name
Test status
Simulation time 498336056563 ps
CPU time 308.19 seconds
Started Mar 26 02:35:53 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 190908 kb
Host smart-544e2c67-cc9d-4756-a1ed-0d45dce06e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260012494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3260012494
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1281638852
Short name T293
Test name
Test status
Simulation time 2651088096750 ps
CPU time 1288.78 seconds
Started Mar 26 02:36:03 PM PDT 24
Finished Mar 26 02:57:32 PM PDT 24
Peak memory 190796 kb
Host smart-d366595e-9604-4a74-b1eb-96b4616cfbdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281638852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1281638852
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.2664474552
Short name T338
Test name
Test status
Simulation time 212981393719 ps
CPU time 595.64 seconds
Started Mar 26 02:32:36 PM PDT 24
Finished Mar 26 02:42:31 PM PDT 24
Peak memory 194200 kb
Host smart-f7c4492d-de9e-400a-92a4-6fd262e54fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664474552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2664474552
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3404221655
Short name T116
Test name
Test status
Simulation time 284924126085 ps
CPU time 1540.35 seconds
Started Mar 26 02:36:35 PM PDT 24
Finished Mar 26 03:02:16 PM PDT 24
Peak memory 190852 kb
Host smart-c2e5eb99-dd44-4829-bbbd-f177fd727ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404221655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3404221655
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3637394016
Short name T61
Test name
Test status
Simulation time 532885975664 ps
CPU time 344.63 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 02:38:02 PM PDT 24
Peak memory 194632 kb
Host smart-cc3a85b3-071b-4bda-bda4-04fd58d1886b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637394016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3637394016
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.567671795
Short name T182
Test name
Test status
Simulation time 480205320959 ps
CPU time 259.86 seconds
Started Mar 26 02:32:57 PM PDT 24
Finished Mar 26 02:37:18 PM PDT 24
Peak memory 182700 kb
Host smart-c3e21836-7e87-47c2-bdaa-d10c51b26637
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567671795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.567671795
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/73.rv_timer_random.1368050772
Short name T273
Test name
Test status
Simulation time 752307144086 ps
CPU time 535.32 seconds
Started Mar 26 02:35:10 PM PDT 24
Finished Mar 26 02:44:05 PM PDT 24
Peak memory 190852 kb
Host smart-6ad30f49-fd24-4fe0-bac9-af6a8123ea5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368050772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1368050772
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.4100915490
Short name T215
Test name
Test status
Simulation time 138454987379 ps
CPU time 2234.18 seconds
Started Mar 26 02:35:10 PM PDT 24
Finished Mar 26 03:12:24 PM PDT 24
Peak memory 190868 kb
Host smart-7f6afbba-884d-48a0-a6dc-80b0a48f7e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100915490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4100915490
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3763759113
Short name T432
Test name
Test status
Simulation time 148752513403 ps
CPU time 775.87 seconds
Started Mar 26 02:35:12 PM PDT 24
Finished Mar 26 02:48:08 PM PDT 24
Peak memory 190872 kb
Host smart-e981d533-a022-4c32-a6de-eebe9755c8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763759113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3763759113
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.4239984793
Short name T264
Test name
Test status
Simulation time 499160340674 ps
CPU time 742.99 seconds
Started Mar 26 02:35:34 PM PDT 24
Finished Mar 26 02:47:57 PM PDT 24
Peak memory 190828 kb
Host smart-d64b3c71-c7e7-49e8-85b9-4b6e5ba4d92d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239984793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.4239984793
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.335266447
Short name T191
Test name
Test status
Simulation time 384470834295 ps
CPU time 728.31 seconds
Started Mar 26 02:35:53 PM PDT 24
Finished Mar 26 02:48:02 PM PDT 24
Peak memory 190840 kb
Host smart-4c479e8d-6930-4c36-9ffd-57b011bfea6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335266447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.335266447
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1845446780
Short name T219
Test name
Test status
Simulation time 741792955278 ps
CPU time 389.25 seconds
Started Mar 26 02:36:03 PM PDT 24
Finished Mar 26 02:42:33 PM PDT 24
Peak memory 190840 kb
Host smart-996660b8-0155-4e02-8dcd-66d9f46e17b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845446780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1845446780
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2979240366
Short name T146
Test name
Test status
Simulation time 193794476457 ps
CPU time 593.26 seconds
Started Mar 26 02:36:34 PM PDT 24
Finished Mar 26 02:46:28 PM PDT 24
Peak memory 193588 kb
Host smart-f4ea1647-a8b3-4557-ba8d-7426ebdcba86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979240366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2979240366
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1451523746
Short name T186
Test name
Test status
Simulation time 379765481725 ps
CPU time 792.71 seconds
Started Mar 26 02:34:17 PM PDT 24
Finished Mar 26 02:47:30 PM PDT 24
Peak memory 190880 kb
Host smart-c8c3339d-601e-4422-a38c-aa06856820a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451523746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1451523746
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.834808530
Short name T225
Test name
Test status
Simulation time 108538122438 ps
CPU time 175.72 seconds
Started Mar 26 02:34:39 PM PDT 24
Finished Mar 26 02:37:35 PM PDT 24
Peak memory 194048 kb
Host smart-98cbbd9e-dafd-475e-933c-a9638210458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834808530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.834808530
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/83.rv_timer_random.3655413630
Short name T55
Test name
Test status
Simulation time 111049230775 ps
CPU time 229.69 seconds
Started Mar 26 02:35:23 PM PDT 24
Finished Mar 26 02:39:13 PM PDT 24
Peak memory 190836 kb
Host smart-84dfd337-94b2-46ed-a2d4-890ff519a646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655413630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3655413630
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2102757723
Short name T217
Test name
Test status
Simulation time 891488744427 ps
CPU time 894.59 seconds
Started Mar 26 02:35:24 PM PDT 24
Finished Mar 26 02:50:19 PM PDT 24
Peak memory 190820 kb
Host smart-6d4ce22f-f8d2-4520-8da8-d5dde56f1f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102757723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2102757723
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1554905393
Short name T204
Test name
Test status
Simulation time 122304767232 ps
CPU time 311.18 seconds
Started Mar 26 02:35:23 PM PDT 24
Finished Mar 26 02:40:35 PM PDT 24
Peak memory 190892 kb
Host smart-f199dff9-299b-4d65-a3a6-cf998be8d853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554905393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1554905393
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.369793240
Short name T93
Test name
Test status
Simulation time 15015279 ps
CPU time 0.6 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 192056 kb
Host smart-4b61304b-62ec-4380-b722-b73719838914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369793240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.369793240
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/102.rv_timer_random.2885363738
Short name T209
Test name
Test status
Simulation time 414494336806 ps
CPU time 301.54 seconds
Started Mar 26 02:35:34 PM PDT 24
Finished Mar 26 02:40:36 PM PDT 24
Peak memory 193408 kb
Host smart-289d92e1-d07b-4399-b4b5-6319d50debce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885363738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2885363738
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1983603210
Short name T255
Test name
Test status
Simulation time 349022497901 ps
CPU time 397.75 seconds
Started Mar 26 02:35:35 PM PDT 24
Finished Mar 26 02:42:13 PM PDT 24
Peak memory 190876 kb
Host smart-9d474daa-32f2-4300-87d3-6fe75ea4ea91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983603210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1983603210
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.414246702
Short name T279
Test name
Test status
Simulation time 67919450234 ps
CPU time 166.88 seconds
Started Mar 26 02:35:44 PM PDT 24
Finished Mar 26 02:38:31 PM PDT 24
Peak memory 190896 kb
Host smart-14fe7c1d-5528-427b-96c0-2d355c39639e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414246702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.414246702
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3415963535
Short name T9
Test name
Test status
Simulation time 396406683070 ps
CPU time 542.44 seconds
Started Mar 26 02:35:53 PM PDT 24
Finished Mar 26 02:44:56 PM PDT 24
Peak memory 190856 kb
Host smart-175b4fa2-a8ad-4340-9fdd-713bc7b2ded1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415963535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3415963535
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1622131673
Short name T300
Test name
Test status
Simulation time 214251816943 ps
CPU time 1098.39 seconds
Started Mar 26 02:36:03 PM PDT 24
Finished Mar 26 02:54:22 PM PDT 24
Peak memory 190852 kb
Host smart-7deb3351-3ebf-46d9-b141-fe02819c3c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622131673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1622131673
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3829964645
Short name T126
Test name
Test status
Simulation time 62858617090 ps
CPU time 252.68 seconds
Started Mar 26 02:36:12 PM PDT 24
Finished Mar 26 02:40:25 PM PDT 24
Peak memory 190856 kb
Host smart-79286f46-e07e-4264-9bab-32c6e11c4db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829964645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3829964645
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1132305077
Short name T324
Test name
Test status
Simulation time 299424152482 ps
CPU time 278.51 seconds
Started Mar 26 02:36:33 PM PDT 24
Finished Mar 26 02:41:12 PM PDT 24
Peak memory 190884 kb
Host smart-eb75b2bb-ecb6-400c-a453-f85136657ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132305077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1132305077
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1965855399
Short name T220
Test name
Test status
Simulation time 3939542624442 ps
CPU time 1584.47 seconds
Started Mar 26 02:33:44 PM PDT 24
Finished Mar 26 03:00:08 PM PDT 24
Peak memory 190884 kb
Host smart-a388ac84-8577-4f8f-981d-68b638d7dffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965855399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1965855399
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.3634065013
Short name T269
Test name
Test status
Simulation time 402206240125 ps
CPU time 206.84 seconds
Started Mar 26 02:33:53 PM PDT 24
Finished Mar 26 02:37:20 PM PDT 24
Peak memory 190828 kb
Host smart-67961a3d-ccef-4126-8b50-1e70416a8ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634065013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3634065013
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.4158762219
Short name T271
Test name
Test status
Simulation time 1924149149629 ps
CPU time 5062.09 seconds
Started Mar 26 02:34:17 PM PDT 24
Finished Mar 26 03:58:40 PM PDT 24
Peak memory 190868 kb
Host smart-c5912482-7b9d-44e2-b2f0-3766193cd916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158762219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.4158762219
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random.4162413234
Short name T266
Test name
Test status
Simulation time 322835808629 ps
CPU time 331.43 seconds
Started Mar 26 02:34:29 PM PDT 24
Finished Mar 26 02:40:02 PM PDT 24
Peak memory 190828 kb
Host smart-7630a592-6c98-46eb-99f0-e9239528f687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162413234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4162413234
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2545752211
Short name T137
Test name
Test status
Simulation time 1240846955427 ps
CPU time 563.05 seconds
Started Mar 26 02:35:05 PM PDT 24
Finished Mar 26 02:44:28 PM PDT 24
Peak memory 190852 kb
Host smart-d45a1296-f29b-4baf-bb47-1b5c107ad64b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545752211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2545752211
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.418005662
Short name T143
Test name
Test status
Simulation time 378112073331 ps
CPU time 290.53 seconds
Started Mar 26 02:35:05 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 194384 kb
Host smart-41a532ea-91a1-4317-83e0-4615e1507546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418005662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.418005662
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.465927640
Short name T159
Test name
Test status
Simulation time 193214433605 ps
CPU time 637.63 seconds
Started Mar 26 02:35:23 PM PDT 24
Finished Mar 26 02:46:01 PM PDT 24
Peak memory 190892 kb
Host smart-ff2b0c01-4f1d-4302-98bf-f32d3648fc95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465927640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.465927640
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.205285308
Short name T528
Test name
Test status
Simulation time 1639065467 ps
CPU time 1.38 seconds
Started Mar 26 02:30:45 PM PDT 24
Finished Mar 26 02:30:47 PM PDT 24
Peak memory 195864 kb
Host smart-ea7edab2-ec32-47b5-b592-6759eb929edf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205285308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.205285308
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4148607375
Short name T171
Test name
Test status
Simulation time 222779670225 ps
CPU time 416.66 seconds
Started Mar 26 02:32:18 PM PDT 24
Finished Mar 26 02:39:15 PM PDT 24
Peak memory 190864 kb
Host smart-cdc1ac02-c09b-4f64-856a-b2cfbabe3a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148607375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4148607375
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1347270487
Short name T131
Test name
Test status
Simulation time 871458640844 ps
CPU time 506.03 seconds
Started Mar 26 02:32:33 PM PDT 24
Finished Mar 26 02:40:59 PM PDT 24
Peak memory 182608 kb
Host smart-f4fdaa96-a82e-44cd-9a08-a6301d9e07f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347270487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1347270487
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/105.rv_timer_random.2756600604
Short name T106
Test name
Test status
Simulation time 717544828259 ps
CPU time 378.83 seconds
Started Mar 26 02:35:35 PM PDT 24
Finished Mar 26 02:41:54 PM PDT 24
Peak memory 190892 kb
Host smart-6454daa4-b1ef-40ca-b286-6557e1733137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756600604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2756600604
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3497886356
Short name T110
Test name
Test status
Simulation time 16251903996 ps
CPU time 32.29 seconds
Started Mar 26 02:35:35 PM PDT 24
Finished Mar 26 02:36:07 PM PDT 24
Peak memory 182700 kb
Host smart-009363b2-2df5-4e11-8fa6-aac1c383fff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497886356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3497886356
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.3972151075
Short name T153
Test name
Test status
Simulation time 708340111484 ps
CPU time 1145.53 seconds
Started Mar 26 02:32:36 PM PDT 24
Finished Mar 26 02:51:42 PM PDT 24
Peak memory 190828 kb
Host smart-ae462568-d2f2-4ecf-9f48-32d826484a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972151075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3972151075
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4225627990
Short name T276
Test name
Test status
Simulation time 73125436044 ps
CPU time 199.03 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:35:55 PM PDT 24
Peak memory 182624 kb
Host smart-16507d7e-3275-4369-aec5-1f7a0da88d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225627990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4225627990
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.585458844
Short name T241
Test name
Test status
Simulation time 47102210088 ps
CPU time 140.59 seconds
Started Mar 26 02:35:44 PM PDT 24
Finished Mar 26 02:38:04 PM PDT 24
Peak memory 190896 kb
Host smart-4e26b8fd-ba0a-4346-a4c3-4c8a382066ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585458844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.585458844
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3915561143
Short name T451
Test name
Test status
Simulation time 127763234676 ps
CPU time 606.33 seconds
Started Mar 26 02:35:43 PM PDT 24
Finished Mar 26 02:45:49 PM PDT 24
Peak memory 190852 kb
Host smart-5f2a1991-92a8-4e88-9a5a-c1c3a69e5449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915561143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3915561143
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1156283163
Short name T336
Test name
Test status
Simulation time 131792817850 ps
CPU time 506.45 seconds
Started Mar 26 02:35:44 PM PDT 24
Finished Mar 26 02:44:11 PM PDT 24
Peak memory 190820 kb
Host smart-e257d69e-9e0e-49fd-a117-37c55d847e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156283163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1156283163
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3282424774
Short name T183
Test name
Test status
Simulation time 44780446628 ps
CPU time 298.71 seconds
Started Mar 26 02:35:54 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 190888 kb
Host smart-ebf1c84b-7765-4821-966f-a7917d943cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282424774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3282424774
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1687636907
Short name T316
Test name
Test status
Simulation time 59166109715 ps
CPU time 71.48 seconds
Started Mar 26 02:35:53 PM PDT 24
Finished Mar 26 02:37:04 PM PDT 24
Peak memory 190872 kb
Host smart-712827f7-c789-48c4-9ef5-634981f8e1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687636907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1687636907
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1283363581
Short name T202
Test name
Test status
Simulation time 209328067016 ps
CPU time 350.61 seconds
Started Mar 26 02:36:00 PM PDT 24
Finished Mar 26 02:41:51 PM PDT 24
Peak memory 190812 kb
Host smart-44ed2c6d-046b-4a88-9b42-f384cb5fe08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283363581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1283363581
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3810872062
Short name T329
Test name
Test status
Simulation time 263647287357 ps
CPU time 256.7 seconds
Started Mar 26 02:32:38 PM PDT 24
Finished Mar 26 02:36:56 PM PDT 24
Peak memory 182712 kb
Host smart-9d1c16ad-ac2e-4673-95d5-d1de60d3f8a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810872062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3810872062
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3086034024
Short name T119
Test name
Test status
Simulation time 1679947547411 ps
CPU time 502.4 seconds
Started Mar 26 02:32:32 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 195244 kb
Host smart-a3593d68-fead-4c8b-bcce-b6515c51f305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086034024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3086034024
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1522731367
Short name T60
Test name
Test status
Simulation time 853668927934 ps
CPU time 541.48 seconds
Started Mar 26 02:32:36 PM PDT 24
Finished Mar 26 02:41:37 PM PDT 24
Peak memory 194960 kb
Host smart-b0fb762a-1423-4192-b79a-9594db5e5463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522731367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1522731367
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/164.rv_timer_random.3127214375
Short name T194
Test name
Test status
Simulation time 129954260879 ps
CPU time 854.07 seconds
Started Mar 26 02:36:23 PM PDT 24
Finished Mar 26 02:50:37 PM PDT 24
Peak memory 190888 kb
Host smart-7c17d027-a164-43ed-99a9-afda703443d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127214375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3127214375
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.816106521
Short name T105
Test name
Test status
Simulation time 532704280814 ps
CPU time 589.84 seconds
Started Mar 26 02:36:23 PM PDT 24
Finished Mar 26 02:46:14 PM PDT 24
Peak memory 190848 kb
Host smart-05e0fa20-6309-4162-a675-b2e86bd54051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816106521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.816106521
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2400938932
Short name T313
Test name
Test status
Simulation time 54412729538 ps
CPU time 219.04 seconds
Started Mar 26 02:36:23 PM PDT 24
Finished Mar 26 02:40:02 PM PDT 24
Peak memory 182616 kb
Host smart-8abe84a2-87a1-4178-a061-829174d770a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400938932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2400938932
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3171114382
Short name T132
Test name
Test status
Simulation time 214406911913 ps
CPU time 1966.11 seconds
Started Mar 26 02:36:34 PM PDT 24
Finished Mar 26 03:09:21 PM PDT 24
Peak memory 190872 kb
Host smart-f34b648d-8825-4ab8-bae0-284795dbbf2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171114382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3171114382
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1902944752
Short name T261
Test name
Test status
Simulation time 170846799256 ps
CPU time 106.82 seconds
Started Mar 26 02:36:46 PM PDT 24
Finished Mar 26 02:38:34 PM PDT 24
Peak memory 190852 kb
Host smart-301290a0-1683-4319-b4ca-1ca46ea10d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902944752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1902944752
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1731655668
Short name T196
Test name
Test status
Simulation time 171574335075 ps
CPU time 293.54 seconds
Started Mar 26 02:33:37 PM PDT 24
Finished Mar 26 02:38:31 PM PDT 24
Peak memory 182704 kb
Host smart-cc758cc2-2d2f-4025-b1a3-cd10b6f72250
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731655668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1731655668
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/64.rv_timer_random.3370574905
Short name T218
Test name
Test status
Simulation time 165409930617 ps
CPU time 1908.72 seconds
Started Mar 26 02:34:58 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 190868 kb
Host smart-b7ea6eeb-fcbe-4768-b894-dc1aba8c4f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370574905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3370574905
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.673109889
Short name T532
Test name
Test status
Simulation time 121123704 ps
CPU time 0.83 seconds
Started Mar 26 02:30:56 PM PDT 24
Finished Mar 26 02:30:57 PM PDT 24
Peak memory 192544 kb
Host smart-beccec2b-8e60-47b8-8649-e89addd42a6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673109889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.673109889
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3047075722
Short name T90
Test name
Test status
Simulation time 1101187918 ps
CPU time 2.74 seconds
Started Mar 26 02:30:55 PM PDT 24
Finished Mar 26 02:30:58 PM PDT 24
Peak memory 183200 kb
Host smart-8cf82a1d-8d10-4535-a2e5-b3c717544579
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047075722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3047075722
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1992122589
Short name T558
Test name
Test status
Simulation time 80037316 ps
CPU time 0.64 seconds
Started Mar 26 02:30:57 PM PDT 24
Finished Mar 26 02:30:58 PM PDT 24
Peak memory 182780 kb
Host smart-ab1bdcf2-a22b-40ae-9ca8-f1959df2d30e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992122589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1992122589
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2688552374
Short name T469
Test name
Test status
Simulation time 35126926 ps
CPU time 0.85 seconds
Started Mar 26 02:30:56 PM PDT 24
Finished Mar 26 02:30:57 PM PDT 24
Peak memory 196624 kb
Host smart-f588d69f-e3dd-41d9-99b9-84fe7cd008f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688552374 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2688552374
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.429559627
Short name T82
Test name
Test status
Simulation time 42455743 ps
CPU time 0.57 seconds
Started Mar 26 02:30:56 PM PDT 24
Finished Mar 26 02:30:57 PM PDT 24
Peak memory 182720 kb
Host smart-6fd8c36d-697d-4d6b-b9a5-040d0d783155
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429559627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.429559627
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4218020713
Short name T541
Test name
Test status
Simulation time 16309774 ps
CPU time 0.59 seconds
Started Mar 26 02:30:56 PM PDT 24
Finished Mar 26 02:30:57 PM PDT 24
Peak memory 182748 kb
Host smart-9e01f6f2-c087-4e34-98be-e212ec85b682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218020713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.4218020713
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.647181862
Short name T531
Test name
Test status
Simulation time 12521000 ps
CPU time 0.56 seconds
Started Mar 26 02:30:56 PM PDT 24
Finished Mar 26 02:30:57 PM PDT 24
Peak memory 191248 kb
Host smart-550a227a-b245-446d-8a2e-de71ef0481c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647181862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.647181862
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2346793396
Short name T569
Test name
Test status
Simulation time 156270689 ps
CPU time 1.65 seconds
Started Mar 26 02:30:44 PM PDT 24
Finished Mar 26 02:30:46 PM PDT 24
Peak memory 197760 kb
Host smart-ef490624-4f22-4806-ba6e-06ca6cb59aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346793396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2346793396
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3521411903
Short name T86
Test name
Test status
Simulation time 55358085 ps
CPU time 0.78 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 192564 kb
Host smart-70b85b60-f65c-4d7a-91ad-1022b8abf85e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521411903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3521411903
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2773616021
Short name T526
Test name
Test status
Simulation time 103447279 ps
CPU time 1.53 seconds
Started Mar 26 02:30:57 PM PDT 24
Finished Mar 26 02:30:58 PM PDT 24
Peak memory 192292 kb
Host smart-b8c22203-9e0e-40d1-8a48-5d7cfa73e9b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773616021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2773616021
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1718552869
Short name T581
Test name
Test status
Simulation time 18390720 ps
CPU time 0.53 seconds
Started Mar 26 02:30:56 PM PDT 24
Finished Mar 26 02:30:57 PM PDT 24
Peak memory 182272 kb
Host smart-75ad7b80-98d1-406e-843f-71389f3c6c2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718552869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1718552869
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4017850665
Short name T468
Test name
Test status
Simulation time 20577263 ps
CPU time 0.7 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 194480 kb
Host smart-f0246145-be7b-4e3c-bc3d-37b309dbe3e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017850665 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4017850665
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2184929131
Short name T92
Test name
Test status
Simulation time 17778547 ps
CPU time 0.6 seconds
Started Mar 26 02:30:56 PM PDT 24
Finished Mar 26 02:30:57 PM PDT 24
Peak memory 182836 kb
Host smart-6d966988-076f-46c1-9ac7-0090f29fa876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184929131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2184929131
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4203133713
Short name T549
Test name
Test status
Simulation time 44664474 ps
CPU time 0.59 seconds
Started Mar 26 02:30:56 PM PDT 24
Finished Mar 26 02:30:57 PM PDT 24
Peak memory 182636 kb
Host smart-87fbe4e7-edb8-499f-9100-67be42619c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203133713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4203133713
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2300657691
Short name T506
Test name
Test status
Simulation time 18750900 ps
CPU time 0.61 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:13 PM PDT 24
Peak memory 191840 kb
Host smart-c63cb70a-9dbc-454b-95fd-0298596defb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300657691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2300657691
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2190895942
Short name T487
Test name
Test status
Simulation time 228042982 ps
CPU time 2.72 seconds
Started Mar 26 02:30:55 PM PDT 24
Finished Mar 26 02:30:58 PM PDT 24
Peak memory 197692 kb
Host smart-eb0d8ba7-fd3c-4bb6-97fe-01886e70c958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190895942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2190895942
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.473477773
Short name T461
Test name
Test status
Simulation time 48074011 ps
CPU time 1.12 seconds
Started Mar 26 02:31:54 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 197676 kb
Host smart-521f056a-510b-45c9-9373-99d3f4676079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473477773 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.473477773
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1891875063
Short name T85
Test name
Test status
Simulation time 12090576 ps
CPU time 0.55 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 182532 kb
Host smart-e9a4b584-da86-40ed-8e56-c337ae3e8b24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891875063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1891875063
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1297778582
Short name T527
Test name
Test status
Simulation time 33885155 ps
CPU time 0.52 seconds
Started Mar 26 02:31:38 PM PDT 24
Finished Mar 26 02:31:39 PM PDT 24
Peak memory 182628 kb
Host smart-702b3ac0-f328-4c6b-a921-5de2670b77ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297778582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1297778582
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3351659133
Short name T479
Test name
Test status
Simulation time 90406662 ps
CPU time 1.78 seconds
Started Mar 26 02:31:38 PM PDT 24
Finished Mar 26 02:31:40 PM PDT 24
Peak memory 197700 kb
Host smart-e779c0d1-8da8-4c78-8018-ab1c3aae4892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351659133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3351659133
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2368600620
Short name T103
Test name
Test status
Simulation time 95317609 ps
CPU time 1.13 seconds
Started Mar 26 02:31:40 PM PDT 24
Finished Mar 26 02:31:41 PM PDT 24
Peak memory 183364 kb
Host smart-06c6b08c-effd-47ef-ae60-d1f041f6268f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368600620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2368600620
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.913113794
Short name T44
Test name
Test status
Simulation time 144699433 ps
CPU time 0.79 seconds
Started Mar 26 02:31:54 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 195116 kb
Host smart-f2daebeb-d960-4c96-9ba4-14e69b76c08d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913113794 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.913113794
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2558193771
Short name T87
Test name
Test status
Simulation time 41573699 ps
CPU time 0.56 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 182756 kb
Host smart-a73b0200-38d3-4405-bfbb-5a0d70a41866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558193771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2558193771
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2991161348
Short name T482
Test name
Test status
Simulation time 15969533 ps
CPU time 0.57 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 182724 kb
Host smart-7b539b65-eff2-45d3-ac39-1c4632ed94c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991161348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2991161348
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3551575804
Short name T575
Test name
Test status
Simulation time 17949448 ps
CPU time 0.75 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 193428 kb
Host smart-151ae0a3-4eba-466b-bc20-59de88e335f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551575804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3551575804
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1182034905
Short name T475
Test name
Test status
Simulation time 90150828 ps
CPU time 1.2 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 197640 kb
Host smart-ed9842a9-fc29-4b3e-99eb-9ac862908e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182034905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1182034905
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1953018610
Short name T573
Test name
Test status
Simulation time 367834669 ps
CPU time 1.42 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 195652 kb
Host smart-cbc90663-a2f5-4bd3-8570-e75925c9d682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953018610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1953018610
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1657237581
Short name T505
Test name
Test status
Simulation time 49563554 ps
CPU time 0.91 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 196508 kb
Host smart-46766b4e-1e1f-41d6-81d8-77f5bde7026f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657237581 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1657237581
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.306924117
Short name T88
Test name
Test status
Simulation time 11449420 ps
CPU time 0.58 seconds
Started Mar 26 02:31:54 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 182712 kb
Host smart-4577ed52-79ae-4967-8385-2b6e13a9987b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306924117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.306924117
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.423505835
Short name T477
Test name
Test status
Simulation time 61196921 ps
CPU time 0.53 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 182152 kb
Host smart-f2ac7311-fef8-4704-9100-529512911c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423505835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.423505835
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1355139704
Short name T546
Test name
Test status
Simulation time 45869477 ps
CPU time 0.62 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 192144 kb
Host smart-59b6611a-1ea4-42e8-8160-e3a7389e35b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355139704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1355139704
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3537846893
Short name T492
Test name
Test status
Simulation time 196884985 ps
CPU time 1.14 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 195652 kb
Host smart-df962a87-5234-4f5f-86cf-c9622730de72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537846893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3537846893
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.491852072
Short name T514
Test name
Test status
Simulation time 241678605 ps
CPU time 0.86 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 192800 kb
Host smart-204e87c6-5eb9-4cc9-87dd-2431bc904be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491852072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.491852072
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4016982468
Short name T566
Test name
Test status
Simulation time 46543028 ps
CPU time 1.05 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 197372 kb
Host smart-37bf5e5d-bb28-488b-9c5f-47953147f39c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016982468 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4016982468
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1805120359
Short name T529
Test name
Test status
Simulation time 73138834 ps
CPU time 0.62 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 182764 kb
Host smart-33680171-92f7-42cf-89ce-604be4902181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805120359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1805120359
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.628825246
Short name T502
Test name
Test status
Simulation time 20519649 ps
CPU time 0.55 seconds
Started Mar 26 02:31:54 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 182076 kb
Host smart-dfcca2c0-2017-4f3c-853e-4aec15c96698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628825246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.628825246
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2691780438
Short name T512
Test name
Test status
Simulation time 19335568 ps
CPU time 0.65 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 192020 kb
Host smart-a6e5fb82-6633-49ed-832f-51a937cc2664
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691780438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2691780438
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2092391690
Short name T484
Test name
Test status
Simulation time 108695586 ps
CPU time 2.71 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 197896 kb
Host smart-4f066f0a-575f-451b-9eea-34f34dcd5ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092391690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2092391690
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4007580321
Short name T511
Test name
Test status
Simulation time 332025869 ps
CPU time 1.1 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 194784 kb
Host smart-4b862e90-9d42-4949-8ae3-5e4a05cd77f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007580321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.4007580321
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4127283194
Short name T476
Test name
Test status
Simulation time 29120209 ps
CPU time 1.33 seconds
Started Mar 26 02:31:54 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 197720 kb
Host smart-66317c5b-7cdd-49fd-bbef-28cf0a118efc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127283194 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4127283194
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2968590249
Short name T481
Test name
Test status
Simulation time 15986448 ps
CPU time 0.59 seconds
Started Mar 26 02:31:55 PM PDT 24
Finished Mar 26 02:31:56 PM PDT 24
Peak memory 182852 kb
Host smart-4aa1cca5-01e1-4bb0-adee-dee61bc40740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968590249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2968590249
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2505956506
Short name T460
Test name
Test status
Simulation time 13421824 ps
CPU time 0.59 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 182308 kb
Host smart-c4929e8d-eab2-4811-896d-0cd293d2d3b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505956506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2505956506
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.165783656
Short name T556
Test name
Test status
Simulation time 37295460 ps
CPU time 0.79 seconds
Started Mar 26 02:31:54 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 193324 kb
Host smart-ea2645ba-c9ac-4ca5-a421-9e65b03d711c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165783656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.165783656
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.744168534
Short name T525
Test name
Test status
Simulation time 261592800 ps
CPU time 1.38 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 197508 kb
Host smart-0fca793e-2946-468a-a780-d7023043fe02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744168534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.744168534
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.823047303
Short name T580
Test name
Test status
Simulation time 215312052 ps
CPU time 1.32 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 195600 kb
Host smart-ba4eb1de-f765-472f-9510-b5c64e8d4d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823047303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.823047303
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3707991944
Short name T31
Test name
Test status
Simulation time 367112699 ps
CPU time 0.88 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 196496 kb
Host smart-a338b55b-d133-4e35-a614-e998516b0c68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707991944 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3707991944
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.593468102
Short name T99
Test name
Test status
Simulation time 28416357 ps
CPU time 0.56 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 182732 kb
Host smart-0d89183e-12f4-4c3f-a086-02298ce07af6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593468102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.593468102
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2527748337
Short name T497
Test name
Test status
Simulation time 26128973 ps
CPU time 0.56 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 182612 kb
Host smart-1ae7b51e-1fd0-4822-b11d-960b03184623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527748337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2527748337
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3569611121
Short name T32
Test name
Test status
Simulation time 33613653 ps
CPU time 0.77 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:54 PM PDT 24
Peak memory 191784 kb
Host smart-2828dc8b-9f57-4a66-9676-b9f7e1867c6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569611121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3569611121
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3451758510
Short name T513
Test name
Test status
Simulation time 32934135 ps
CPU time 1.2 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 197580 kb
Host smart-c1d428ea-6175-45f6-a0de-069157fbdd99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451758510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3451758510
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3005383035
Short name T516
Test name
Test status
Simulation time 430658667 ps
CPU time 0.88 seconds
Started Mar 26 02:31:55 PM PDT 24
Finished Mar 26 02:31:56 PM PDT 24
Peak memory 193652 kb
Host smart-f81da444-bac3-4de3-b43f-ae51445b34cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005383035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3005383035
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.972570866
Short name T552
Test name
Test status
Simulation time 43386417 ps
CPU time 0.95 seconds
Started Mar 26 02:31:54 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 196608 kb
Host smart-b8a97965-970a-403f-a8c8-938cb61d1501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972570866 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.972570866
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3953208479
Short name T473
Test name
Test status
Simulation time 15477148 ps
CPU time 0.56 seconds
Started Mar 26 02:31:52 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 182700 kb
Host smart-d30ae7e4-4012-47f6-bea1-6ab3646b8dc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953208479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3953208479
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2637656241
Short name T560
Test name
Test status
Simulation time 17035709 ps
CPU time 0.59 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:53 PM PDT 24
Peak memory 182792 kb
Host smart-baf24393-7752-4b62-863b-5f68e2e9cd52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637656241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2637656241
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2121216699
Short name T567
Test name
Test status
Simulation time 53881907 ps
CPU time 0.75 seconds
Started Mar 26 02:31:54 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 193120 kb
Host smart-33d7ddc7-d930-47eb-958a-0c1d05d3090a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121216699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2121216699
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3648747267
Short name T570
Test name
Test status
Simulation time 44103074 ps
CPU time 2.13 seconds
Started Mar 26 02:31:51 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 197704 kb
Host smart-cc4fbc55-be6b-40d2-9981-f6ac6b2ea747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648747267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3648747267
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1720789537
Short name T507
Test name
Test status
Simulation time 235600338 ps
CPU time 1.29 seconds
Started Mar 26 02:31:53 PM PDT 24
Finished Mar 26 02:31:55 PM PDT 24
Peak memory 195292 kb
Host smart-5dafb338-83e6-4a67-8696-cbbfb162c197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720789537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1720789537
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3633100971
Short name T485
Test name
Test status
Simulation time 140354225 ps
CPU time 0.94 seconds
Started Mar 26 02:32:06 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 197444 kb
Host smart-64dfe0e2-d14b-4f39-9a3d-1661d6e9b33e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633100971 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3633100971
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2738405120
Short name T564
Test name
Test status
Simulation time 14738588 ps
CPU time 0.57 seconds
Started Mar 26 02:32:03 PM PDT 24
Finished Mar 26 02:32:04 PM PDT 24
Peak memory 182808 kb
Host smart-75172118-ce4d-44cd-97ca-c317cd95e51b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738405120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2738405120
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2407913777
Short name T509
Test name
Test status
Simulation time 24996667 ps
CPU time 0.55 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 182636 kb
Host smart-cb19819c-372f-49bb-ba51-75f1a975036b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407913777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2407913777
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.324077673
Short name T79
Test name
Test status
Simulation time 28492646 ps
CPU time 0.66 seconds
Started Mar 26 02:32:13 PM PDT 24
Finished Mar 26 02:32:14 PM PDT 24
Peak memory 192072 kb
Host smart-5b6d3b60-d58f-498d-945e-b59d6f738008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324077673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.324077673
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1785649873
Short name T459
Test name
Test status
Simulation time 122408433 ps
CPU time 2.3 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 197692 kb
Host smart-6e12a288-939c-4b06-a210-ed91edb7a3e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785649873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1785649873
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2089620012
Short name T500
Test name
Test status
Simulation time 155020446 ps
CPU time 1.19 seconds
Started Mar 26 02:32:03 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 183548 kb
Host smart-7fdc4edd-c3b0-40c6-9540-8e326f068fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089620012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2089620012
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3881542713
Short name T544
Test name
Test status
Simulation time 34862836 ps
CPU time 0.88 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 196660 kb
Host smart-d5fcb8d7-fa18-401e-8f7e-b592e2bf7026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881542713 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3881542713
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4134880962
Short name T80
Test name
Test status
Simulation time 14445319 ps
CPU time 0.6 seconds
Started Mar 26 02:32:06 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 182420 kb
Host smart-cdb97293-33e1-4bca-b55c-e6b9a45ea1c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134880962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.4134880962
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1144777514
Short name T557
Test name
Test status
Simulation time 56832713 ps
CPU time 0.59 seconds
Started Mar 26 02:32:06 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 182656 kb
Host smart-b2646bc7-10f3-4135-aa43-efd2021b187d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144777514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1144777514
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2219285708
Short name T524
Test name
Test status
Simulation time 105718809 ps
CPU time 0.72 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 192140 kb
Host smart-c80d292b-8a7f-41b2-8019-ed7256fa4ed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219285708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2219285708
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3895693307
Short name T463
Test name
Test status
Simulation time 50962870 ps
CPU time 1.23 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 197548 kb
Host smart-787efaee-f50f-4486-9378-e2482639f8cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895693307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3895693307
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.543179064
Short name T102
Test name
Test status
Simulation time 238519542 ps
CPU time 1.4 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 183236 kb
Host smart-db4b8c02-6080-43af-8341-abaa89aa4e90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543179064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.543179064
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.877085687
Short name T530
Test name
Test status
Simulation time 27593502 ps
CPU time 1.03 seconds
Started Mar 26 02:32:06 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 197620 kb
Host smart-83bdb9eb-92ea-49c2-a436-5704fbc26862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877085687 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.877085687
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.578174452
Short name T77
Test name
Test status
Simulation time 18854294 ps
CPU time 0.6 seconds
Started Mar 26 02:32:07 PM PDT 24
Finished Mar 26 02:32:08 PM PDT 24
Peak memory 182716 kb
Host smart-ec1b2433-cc42-4d30-9fb0-396abfa89f44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578174452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.578174452
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3127151931
Short name T510
Test name
Test status
Simulation time 55729236 ps
CPU time 0.55 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 182712 kb
Host smart-7d5be483-0b46-4852-acbc-e5e9c455c0ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127151931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3127151931
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.640002506
Short name T554
Test name
Test status
Simulation time 47847559 ps
CPU time 0.76 seconds
Started Mar 26 02:32:03 PM PDT 24
Finished Mar 26 02:32:04 PM PDT 24
Peak memory 193332 kb
Host smart-d32c7e66-9a4e-41f6-aff1-991e854615a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640002506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.640002506
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1858422247
Short name T490
Test name
Test status
Simulation time 296433091 ps
CPU time 1.6 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 197740 kb
Host smart-fdf3eb77-e98d-4ad4-befd-7a90f226f8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858422247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1858422247
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2478488523
Short name T29
Test name
Test status
Simulation time 393806482 ps
CPU time 1.5 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 195644 kb
Host smart-a6385a0c-a35e-42be-a8e7-c19ac8f2b7ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478488523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2478488523
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1401187010
Short name T582
Test name
Test status
Simulation time 43009152 ps
CPU time 0.83 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 182756 kb
Host smart-aded1343-c4d7-4e52-b19f-3b24a24b02d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401187010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1401187010
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3933189355
Short name T562
Test name
Test status
Simulation time 101994032 ps
CPU time 1.53 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 191176 kb
Host smart-d9851671-592d-4325-a130-360ba9842759
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933189355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3933189355
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2015547600
Short name T491
Test name
Test status
Simulation time 48048760 ps
CPU time 0.54 seconds
Started Mar 26 02:31:14 PM PDT 24
Finished Mar 26 02:31:15 PM PDT 24
Peak memory 182828 kb
Host smart-782834fb-0bd4-42f1-ab56-639ef254fcae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015547600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2015547600
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.84271455
Short name T551
Test name
Test status
Simulation time 67638264 ps
CPU time 0.84 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 196556 kb
Host smart-b1b71df9-f101-4b50-b2ad-0674d5e10fea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84271455 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.84271455
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3211127848
Short name T89
Test name
Test status
Simulation time 39518197 ps
CPU time 0.52 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 182432 kb
Host smart-7497109f-fc20-4998-a6f4-1b3f41ac2d2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211127848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3211127848
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.647171216
Short name T472
Test name
Test status
Simulation time 17682916 ps
CPU time 0.55 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:12 PM PDT 24
Peak memory 182624 kb
Host smart-87f846ac-c4c1-403e-b606-f3c6dd0f6b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647171216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.647171216
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2043913637
Short name T574
Test name
Test status
Simulation time 20998289 ps
CPU time 0.62 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 192028 kb
Host smart-79f6c4e6-ea2a-47af-8b02-5fb530bb6f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043913637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2043913637
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3944798935
Short name T466
Test name
Test status
Simulation time 28904675 ps
CPU time 1.49 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:15 PM PDT 24
Peak memory 197732 kb
Host smart-42a7f3d9-3746-4fdd-b953-627dc88f54bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944798935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3944798935
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3874373529
Short name T548
Test name
Test status
Simulation time 133021941 ps
CPU time 0.85 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 193940 kb
Host smart-02dd652a-4862-47a4-b0c1-445d35586527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874373529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3874373529
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1350110752
Short name T478
Test name
Test status
Simulation time 19023146 ps
CPU time 0.51 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 182212 kb
Host smart-08f1da94-d221-46a2-8391-88a5d634ba52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350110752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1350110752
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1297854099
Short name T521
Test name
Test status
Simulation time 57522578 ps
CPU time 0.53 seconds
Started Mar 26 02:32:07 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 182108 kb
Host smart-39d1bb6f-0e25-4a51-a047-545ee3850eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297854099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1297854099
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1195429111
Short name T471
Test name
Test status
Simulation time 57314291 ps
CPU time 0.56 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 182716 kb
Host smart-a3dab5ea-c963-43f7-a0fb-5b635b262347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195429111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1195429111
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2105096000
Short name T462
Test name
Test status
Simulation time 18295662 ps
CPU time 0.54 seconds
Started Mar 26 02:32:10 PM PDT 24
Finished Mar 26 02:32:11 PM PDT 24
Peak memory 182188 kb
Host smart-a68ad7f8-c665-49f6-92a7-0d1f6d5bbc71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105096000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2105096000
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2440456991
Short name T498
Test name
Test status
Simulation time 47205831 ps
CPU time 0.53 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 182720 kb
Host smart-cc372ed9-cf33-44fb-8c41-eaefcde34f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440456991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2440456991
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.30346736
Short name T488
Test name
Test status
Simulation time 24460340 ps
CPU time 0.54 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 02:32:18 PM PDT 24
Peak memory 182556 kb
Host smart-f1d76f37-d0ac-4497-b149-530c6e515f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30346736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.30346736
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1205433427
Short name T579
Test name
Test status
Simulation time 21372960 ps
CPU time 0.57 seconds
Started Mar 26 02:32:07 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 182644 kb
Host smart-b36f688c-9350-48c1-b96a-54ea65a94f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205433427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1205433427
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2279820548
Short name T489
Test name
Test status
Simulation time 17074830 ps
CPU time 0.57 seconds
Started Mar 26 02:32:21 PM PDT 24
Finished Mar 26 02:32:22 PM PDT 24
Peak memory 182668 kb
Host smart-cff09776-4316-4420-b113-deaf4b567a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279820548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2279820548
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.675536194
Short name T550
Test name
Test status
Simulation time 50577630 ps
CPU time 0.57 seconds
Started Mar 26 02:32:07 PM PDT 24
Finished Mar 26 02:32:08 PM PDT 24
Peak memory 182632 kb
Host smart-ab2751d9-9160-42ad-bc31-a47c2f66b7f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675536194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.675536194
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3216688679
Short name T571
Test name
Test status
Simulation time 13355634 ps
CPU time 0.57 seconds
Started Mar 26 02:32:03 PM PDT 24
Finished Mar 26 02:32:04 PM PDT 24
Peak memory 182752 kb
Host smart-01e4d8ae-d959-40e8-822e-3b0712550687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216688679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3216688679
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4075553365
Short name T43
Test name
Test status
Simulation time 21545378 ps
CPU time 0.64 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:13 PM PDT 24
Peak memory 192040 kb
Host smart-70229592-3676-455a-929f-3d99e681232e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075553365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.4075553365
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.259986690
Short name T540
Test name
Test status
Simulation time 192757332 ps
CPU time 2.42 seconds
Started Mar 26 02:31:14 PM PDT 24
Finished Mar 26 02:31:17 PM PDT 24
Peak memory 191176 kb
Host smart-17fc379b-3dde-4d6a-bad9-8c947257f72d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259986690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.259986690
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3007524798
Short name T542
Test name
Test status
Simulation time 59576597 ps
CPU time 0.54 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:13 PM PDT 24
Peak memory 182172 kb
Host smart-442d33a1-570e-44e7-b904-bd8859929a1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007524798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3007524798
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1199885559
Short name T508
Test name
Test status
Simulation time 117386552 ps
CPU time 0.91 seconds
Started Mar 26 02:31:14 PM PDT 24
Finished Mar 26 02:31:16 PM PDT 24
Peak memory 197048 kb
Host smart-dd7ad254-b266-4088-adb9-1a1b38affaa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199885559 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1199885559
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3463157166
Short name T486
Test name
Test status
Simulation time 27106335 ps
CPU time 0.56 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:13 PM PDT 24
Peak memory 182580 kb
Host smart-9add3860-a39f-4607-ba49-d7606005bb83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463157166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3463157166
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.476207379
Short name T95
Test name
Test status
Simulation time 46117676 ps
CPU time 0.65 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 192000 kb
Host smart-2725830a-763d-443d-9cf9-f62afa860d6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476207379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.476207379
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3346731506
Short name T470
Test name
Test status
Simulation time 141082355 ps
CPU time 1.81 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 197692 kb
Host smart-43a01e8f-bd76-4c68-b84d-90edea21150b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346731506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3346731506
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2117352011
Short name T101
Test name
Test status
Simulation time 49622125 ps
CPU time 0.85 seconds
Started Mar 26 02:31:13 PM PDT 24
Finished Mar 26 02:31:14 PM PDT 24
Peak memory 193432 kb
Host smart-18ccb3be-ce7a-44c5-8f43-76374be4d2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117352011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2117352011
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.495279593
Short name T547
Test name
Test status
Simulation time 17309069 ps
CPU time 0.57 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 182680 kb
Host smart-ee32c519-98da-4d1e-967e-16812afde9d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495279593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.495279593
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3182786179
Short name T545
Test name
Test status
Simulation time 13309807 ps
CPU time 0.55 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 182688 kb
Host smart-24716375-778c-492a-bb6e-1bb125b59d87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182786179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3182786179
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4271644084
Short name T539
Test name
Test status
Simulation time 139990485 ps
CPU time 0.57 seconds
Started Mar 26 02:32:10 PM PDT 24
Finished Mar 26 02:32:11 PM PDT 24
Peak memory 182684 kb
Host smart-e4efe4a8-e743-4b08-96fa-32c6dcc993db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271644084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4271644084
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1927398695
Short name T538
Test name
Test status
Simulation time 114560235 ps
CPU time 0.55 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 182664 kb
Host smart-d926627c-40f8-4a62-b631-5423b2f79faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927398695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1927398695
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.338457679
Short name T577
Test name
Test status
Simulation time 16210217 ps
CPU time 0.58 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:04 PM PDT 24
Peak memory 182596 kb
Host smart-1a816c87-89ef-497b-a41a-32dbf2757447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338457679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.338457679
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.840897377
Short name T483
Test name
Test status
Simulation time 52970017 ps
CPU time 0.55 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 182672 kb
Host smart-0d04326f-d22a-4e67-b60a-6833cd2fbc38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840897377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.840897377
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2225842613
Short name T563
Test name
Test status
Simulation time 106893786 ps
CPU time 0.58 seconds
Started Mar 26 02:32:06 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 182632 kb
Host smart-c7ddb536-e5e9-44eb-9ebb-a83160a3c191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225842613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2225842613
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.319692009
Short name T537
Test name
Test status
Simulation time 19050614 ps
CPU time 0.53 seconds
Started Mar 26 02:32:06 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 182188 kb
Host smart-23380a69-3a4c-446f-b0c4-3c6a83e54cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319692009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.319692009
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.772184574
Short name T559
Test name
Test status
Simulation time 14754669 ps
CPU time 0.62 seconds
Started Mar 26 02:32:02 PM PDT 24
Finished Mar 26 02:32:03 PM PDT 24
Peak memory 182620 kb
Host smart-f8007968-d9ed-4b3c-80d9-408b514260b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772184574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.772184574
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2020018398
Short name T583
Test name
Test status
Simulation time 24741800 ps
CPU time 0.54 seconds
Started Mar 26 02:32:05 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 182724 kb
Host smart-cdd6eaca-9eb3-46a2-b2cd-070a7a9a4857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020018398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2020018398
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3487730658
Short name T78
Test name
Test status
Simulation time 127113140 ps
CPU time 0.81 seconds
Started Mar 26 02:31:24 PM PDT 24
Finished Mar 26 02:31:25 PM PDT 24
Peak memory 182680 kb
Host smart-9f6d042f-52a2-4564-9427-2f415cadade6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487730658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3487730658
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.301036251
Short name T522
Test name
Test status
Simulation time 289640821 ps
CPU time 2.64 seconds
Started Mar 26 02:31:23 PM PDT 24
Finished Mar 26 02:31:26 PM PDT 24
Peak memory 191256 kb
Host smart-188770e3-e90a-4f61-99f0-5ce47cb0d0cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301036251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.301036251
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3072475953
Short name T45
Test name
Test status
Simulation time 87451210 ps
CPU time 0.59 seconds
Started Mar 26 02:31:25 PM PDT 24
Finished Mar 26 02:31:27 PM PDT 24
Peak memory 182772 kb
Host smart-79753c85-ca5c-4523-b788-f9b45b7ff2e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072475953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3072475953
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1856429968
Short name T568
Test name
Test status
Simulation time 133640792 ps
CPU time 1.77 seconds
Started Mar 26 02:31:24 PM PDT 24
Finished Mar 26 02:31:26 PM PDT 24
Peak memory 197660 kb
Host smart-fb0244cd-b6ff-4d9b-a77b-a7ccdea02570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856429968 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1856429968
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1371907269
Short name T91
Test name
Test status
Simulation time 63741269 ps
CPU time 0.61 seconds
Started Mar 26 02:31:23 PM PDT 24
Finished Mar 26 02:31:24 PM PDT 24
Peak memory 191936 kb
Host smart-5822b2b0-71f4-4cb9-ae13-c73b7f13a382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371907269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1371907269
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3315237474
Short name T561
Test name
Test status
Simulation time 99280557 ps
CPU time 0.59 seconds
Started Mar 26 02:31:25 PM PDT 24
Finished Mar 26 02:31:26 PM PDT 24
Peak memory 182684 kb
Host smart-1450803b-cfd4-48cd-a654-7339c440517b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315237474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3315237474
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1599477409
Short name T48
Test name
Test status
Simulation time 128419684 ps
CPU time 0.82 seconds
Started Mar 26 02:31:24 PM PDT 24
Finished Mar 26 02:31:25 PM PDT 24
Peak memory 193520 kb
Host smart-eaba4a45-a1f4-49fc-93ca-f4de8dbb86eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599477409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1599477409
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3556219920
Short name T503
Test name
Test status
Simulation time 150109230 ps
CPU time 2.4 seconds
Started Mar 26 02:31:12 PM PDT 24
Finished Mar 26 02:31:15 PM PDT 24
Peak memory 197660 kb
Host smart-bf405fc3-d838-4eb4-812b-3ebdf9232778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556219920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3556219920
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1569321501
Short name T565
Test name
Test status
Simulation time 293131308 ps
CPU time 1.11 seconds
Started Mar 26 02:31:11 PM PDT 24
Finished Mar 26 02:31:12 PM PDT 24
Peak memory 195264 kb
Host smart-0e0866f9-8439-4442-ae2a-0f71b94d88bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569321501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1569321501
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3864424858
Short name T572
Test name
Test status
Simulation time 62646519 ps
CPU time 0.61 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:04 PM PDT 24
Peak memory 182684 kb
Host smart-314ac82a-b378-453a-abad-b8c9f5a86023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864424858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3864424858
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.171664726
Short name T496
Test name
Test status
Simulation time 27818142 ps
CPU time 0.56 seconds
Started Mar 26 02:32:04 PM PDT 24
Finished Mar 26 02:32:05 PM PDT 24
Peak memory 182176 kb
Host smart-2c67be45-7947-4aed-af7b-8178d4106344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171664726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.171664726
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2272217365
Short name T464
Test name
Test status
Simulation time 17915900 ps
CPU time 0.58 seconds
Started Mar 26 02:32:03 PM PDT 24
Finished Mar 26 02:32:04 PM PDT 24
Peak memory 182368 kb
Host smart-f668338b-fd19-474c-8431-ec98108305b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272217365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2272217365
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2868312510
Short name T576
Test name
Test status
Simulation time 16069106 ps
CPU time 0.58 seconds
Started Mar 26 02:32:10 PM PDT 24
Finished Mar 26 02:32:11 PM PDT 24
Peak memory 182676 kb
Host smart-d050771f-60e7-4ac8-992a-34421af944ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868312510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2868312510
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3010018585
Short name T535
Test name
Test status
Simulation time 14186413 ps
CPU time 0.57 seconds
Started Mar 26 02:32:06 PM PDT 24
Finished Mar 26 02:32:07 PM PDT 24
Peak memory 182616 kb
Host smart-c3bf1ec4-829b-4efe-8763-3c8ef6559f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010018585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3010018585
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.154477939
Short name T465
Test name
Test status
Simulation time 40683520 ps
CPU time 0.57 seconds
Started Mar 26 02:32:06 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 182616 kb
Host smart-2d56954c-6627-4c2f-9e5a-f328efa28316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154477939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.154477939
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.634845805
Short name T494
Test name
Test status
Simulation time 46682272 ps
CPU time 0.57 seconds
Started Mar 26 02:32:13 PM PDT 24
Finished Mar 26 02:32:13 PM PDT 24
Peak memory 182776 kb
Host smart-95b7d1c4-234c-48ea-809a-6fa8ab1e6771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634845805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.634845805
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3456140856
Short name T553
Test name
Test status
Simulation time 14289393 ps
CPU time 0.59 seconds
Started Mar 26 02:32:18 PM PDT 24
Finished Mar 26 02:32:18 PM PDT 24
Peak memory 182724 kb
Host smart-21245c5b-7176-4140-b832-ce549f9baf11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456140856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3456140856
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2567530879
Short name T523
Test name
Test status
Simulation time 36853670 ps
CPU time 0.52 seconds
Started Mar 26 02:32:13 PM PDT 24
Finished Mar 26 02:32:14 PM PDT 24
Peak memory 182180 kb
Host smart-2265903c-f2c6-4c6d-8024-667561da4679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567530879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2567530879
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.551424103
Short name T536
Test name
Test status
Simulation time 54262169 ps
CPU time 0.57 seconds
Started Mar 26 02:32:15 PM PDT 24
Finished Mar 26 02:32:15 PM PDT 24
Peak memory 182568 kb
Host smart-bb78d2a7-2022-417a-9221-4836422769bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551424103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.551424103
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.175404396
Short name T467
Test name
Test status
Simulation time 25994998 ps
CPU time 1.12 seconds
Started Mar 26 02:31:26 PM PDT 24
Finished Mar 26 02:31:28 PM PDT 24
Peak memory 197616 kb
Host smart-1a664cc6-7ff9-43db-a72e-757c6fbced60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175404396 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.175404396
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3190093498
Short name T501
Test name
Test status
Simulation time 14262109 ps
CPU time 0.58 seconds
Started Mar 26 02:31:26 PM PDT 24
Finished Mar 26 02:31:27 PM PDT 24
Peak memory 182780 kb
Host smart-34e76dc1-3523-48fc-8482-aaf03b1d1b47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190093498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3190093498
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2354171224
Short name T533
Test name
Test status
Simulation time 38616826 ps
CPU time 0.54 seconds
Started Mar 26 02:31:24 PM PDT 24
Finished Mar 26 02:31:25 PM PDT 24
Peak memory 182736 kb
Host smart-ecdc5248-90df-42ef-8c16-cd5c93bd8a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354171224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2354171224
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2569744027
Short name T96
Test name
Test status
Simulation time 43518844 ps
CPU time 0.69 seconds
Started Mar 26 02:31:23 PM PDT 24
Finished Mar 26 02:31:23 PM PDT 24
Peak memory 191904 kb
Host smart-fe40bbf0-f74e-4929-a15c-ec6754b6512d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569744027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2569744027
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3566415429
Short name T519
Test name
Test status
Simulation time 238579242 ps
CPU time 2.9 seconds
Started Mar 26 02:31:23 PM PDT 24
Finished Mar 26 02:31:26 PM PDT 24
Peak memory 197688 kb
Host smart-0acb3e8f-00b2-4c56-8ce5-d275711ccfe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566415429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3566415429
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3506052455
Short name T100
Test name
Test status
Simulation time 47209486 ps
CPU time 0.86 seconds
Started Mar 26 02:31:25 PM PDT 24
Finished Mar 26 02:31:26 PM PDT 24
Peak memory 194052 kb
Host smart-094bf50d-53e1-4f60-aba5-7bfcb8c25ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506052455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3506052455
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4050271559
Short name T30
Test name
Test status
Simulation time 34036790 ps
CPU time 0.89 seconds
Started Mar 26 02:31:24 PM PDT 24
Finished Mar 26 02:31:25 PM PDT 24
Peak memory 196880 kb
Host smart-bd966d8c-660a-4b56-8fc3-0e0ab2c30de0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050271559 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.4050271559
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.721895010
Short name T495
Test name
Test status
Simulation time 16759593 ps
CPU time 0.59 seconds
Started Mar 26 02:31:24 PM PDT 24
Finished Mar 26 02:31:25 PM PDT 24
Peak memory 182776 kb
Host smart-0c51cf17-3471-4676-afc0-f35ea7e8d7c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721895010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.721895010
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4111323824
Short name T493
Test name
Test status
Simulation time 50205188 ps
CPU time 0.57 seconds
Started Mar 26 02:31:25 PM PDT 24
Finished Mar 26 02:31:27 PM PDT 24
Peak memory 182800 kb
Host smart-3e69c485-51bf-41a2-90e2-6fc0e3c5c45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111323824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4111323824
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.231985887
Short name T81
Test name
Test status
Simulation time 70986367 ps
CPU time 0.85 seconds
Started Mar 26 02:31:23 PM PDT 24
Finished Mar 26 02:31:24 PM PDT 24
Peak memory 193612 kb
Host smart-b1209565-f5c3-416f-a3c6-aeb8ee5b9b34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231985887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.231985887
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3293525673
Short name T578
Test name
Test status
Simulation time 65587204 ps
CPU time 1.33 seconds
Started Mar 26 02:31:24 PM PDT 24
Finished Mar 26 02:31:26 PM PDT 24
Peak memory 197668 kb
Host smart-63afaf9c-db17-4b85-aad3-ff811e6bb537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293525673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3293525673
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3790413639
Short name T543
Test name
Test status
Simulation time 325024049 ps
CPU time 0.87 seconds
Started Mar 26 02:31:25 PM PDT 24
Finished Mar 26 02:31:26 PM PDT 24
Peak memory 193452 kb
Host smart-8903d697-7bb4-43fb-9d43-1438e180867c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790413639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3790413639
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1836152919
Short name T480
Test name
Test status
Simulation time 117355719 ps
CPU time 0.92 seconds
Started Mar 26 02:31:23 PM PDT 24
Finished Mar 26 02:31:24 PM PDT 24
Peak memory 197428 kb
Host smart-471174f7-dea7-4428-97ad-10ca2f8a5099
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836152919 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1836152919
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3181277916
Short name T517
Test name
Test status
Simulation time 15362301 ps
CPU time 0.6 seconds
Started Mar 26 02:31:25 PM PDT 24
Finished Mar 26 02:31:26 PM PDT 24
Peak memory 182796 kb
Host smart-7dccf86e-efbc-4d61-b32b-cfa8fa8ad9f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181277916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3181277916
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3431121575
Short name T518
Test name
Test status
Simulation time 17804844 ps
CPU time 0.55 seconds
Started Mar 26 02:31:26 PM PDT 24
Finished Mar 26 02:31:27 PM PDT 24
Peak memory 182696 kb
Host smart-ffdad475-926c-42f3-926e-53a943bb1a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431121575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3431121575
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2150680129
Short name T94
Test name
Test status
Simulation time 36454597 ps
CPU time 0.62 seconds
Started Mar 26 02:31:27 PM PDT 24
Finished Mar 26 02:31:28 PM PDT 24
Peak memory 192192 kb
Host smart-41aa550c-1e59-4d2c-9c4f-7f4e2d784b0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150680129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2150680129
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2205158921
Short name T58
Test name
Test status
Simulation time 396476554 ps
CPU time 1.92 seconds
Started Mar 26 02:31:26 PM PDT 24
Finished Mar 26 02:31:29 PM PDT 24
Peak memory 197728 kb
Host smart-b3b10afb-99f9-4dfd-912e-3f3ac72c2880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205158921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2205158921
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2610747416
Short name T28
Test name
Test status
Simulation time 71532014 ps
CPU time 0.85 seconds
Started Mar 26 02:31:24 PM PDT 24
Finished Mar 26 02:31:25 PM PDT 24
Peak memory 193672 kb
Host smart-5dbf257d-5a29-40b6-8a09-ccf44bce62b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610747416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2610747416
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2976042612
Short name T47
Test name
Test status
Simulation time 36593770 ps
CPU time 0.91 seconds
Started Mar 26 02:31:39 PM PDT 24
Finished Mar 26 02:31:40 PM PDT 24
Peak memory 197472 kb
Host smart-06938dca-f370-47f9-a268-e3403cc8e0c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976042612 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2976042612
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1233793001
Short name T84
Test name
Test status
Simulation time 62863428 ps
CPU time 0.6 seconds
Started Mar 26 02:31:38 PM PDT 24
Finished Mar 26 02:31:39 PM PDT 24
Peak memory 182816 kb
Host smart-c7b76d67-352e-4778-bc71-dc436c525475
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233793001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1233793001
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2378186282
Short name T504
Test name
Test status
Simulation time 50559232 ps
CPU time 0.58 seconds
Started Mar 26 02:31:39 PM PDT 24
Finished Mar 26 02:31:40 PM PDT 24
Peak memory 182692 kb
Host smart-5c5ea591-c786-4fb6-a001-1d9acaccfc6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378186282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2378186282
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.140486099
Short name T98
Test name
Test status
Simulation time 18462255 ps
CPU time 0.78 seconds
Started Mar 26 02:31:39 PM PDT 24
Finished Mar 26 02:31:40 PM PDT 24
Peak memory 193476 kb
Host smart-3485df7c-3d46-4b81-8c6f-3d5d447d740f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140486099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.140486099
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2638509750
Short name T474
Test name
Test status
Simulation time 49318761 ps
CPU time 2.32 seconds
Started Mar 26 02:31:26 PM PDT 24
Finished Mar 26 02:31:29 PM PDT 24
Peak memory 197668 kb
Host smart-733213a7-66f1-4456-8692-f0bba497a29e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638509750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2638509750
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4061886574
Short name T555
Test name
Test status
Simulation time 84543574 ps
CPU time 1.06 seconds
Started Mar 26 02:31:23 PM PDT 24
Finished Mar 26 02:31:24 PM PDT 24
Peak memory 183484 kb
Host smart-b0807554-ca6f-4473-bde3-dd39e5298ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061886574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4061886574
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2173931254
Short name T515
Test name
Test status
Simulation time 74209257 ps
CPU time 0.72 seconds
Started Mar 26 02:31:39 PM PDT 24
Finished Mar 26 02:31:40 PM PDT 24
Peak memory 195032 kb
Host smart-4b77d03c-e267-4113-8d77-bbdccb7961d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173931254 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2173931254
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4044722180
Short name T520
Test name
Test status
Simulation time 30140968 ps
CPU time 0.52 seconds
Started Mar 26 02:31:39 PM PDT 24
Finished Mar 26 02:31:40 PM PDT 24
Peak memory 182184 kb
Host smart-a6d25003-113c-4511-b40b-32b47f4f3346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044722180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4044722180
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.577621937
Short name T97
Test name
Test status
Simulation time 37250896 ps
CPU time 0.6 seconds
Started Mar 26 02:31:38 PM PDT 24
Finished Mar 26 02:31:38 PM PDT 24
Peak memory 192116 kb
Host smart-e9dd40ab-c465-4f81-aebb-06f84808227a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577621937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.577621937
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4140188371
Short name T499
Test name
Test status
Simulation time 95261815 ps
CPU time 1.71 seconds
Started Mar 26 02:31:38 PM PDT 24
Finished Mar 26 02:31:39 PM PDT 24
Peak memory 197660 kb
Host smart-e09c9685-53c7-4de1-a90b-c1e631b8b6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140188371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4140188371
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1355004321
Short name T534
Test name
Test status
Simulation time 81580837 ps
CPU time 1.15 seconds
Started Mar 26 02:31:39 PM PDT 24
Finished Mar 26 02:31:40 PM PDT 24
Peak memory 183524 kb
Host smart-a7532dea-edc3-454a-bc36-2da878c0f416
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355004321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1355004321
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2391235902
Short name T446
Test name
Test status
Simulation time 527581424016 ps
CPU time 523 seconds
Started Mar 26 02:32:15 PM PDT 24
Finished Mar 26 02:40:58 PM PDT 24
Peak memory 182580 kb
Host smart-984864f7-18d8-4fed-9197-076faa57cdbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391235902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2391235902
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.863866384
Short name T417
Test name
Test status
Simulation time 448489673865 ps
CPU time 156 seconds
Started Mar 26 02:32:15 PM PDT 24
Finished Mar 26 02:34:51 PM PDT 24
Peak memory 182628 kb
Host smart-7e7e0b97-b5af-453e-a75f-41936c92aa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863866384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.863866384
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3558040883
Short name T285
Test name
Test status
Simulation time 287672554863 ps
CPU time 1112.35 seconds
Started Mar 26 02:32:14 PM PDT 24
Finished Mar 26 02:50:47 PM PDT 24
Peak memory 190812 kb
Host smart-f7d4aaee-7401-4260-bbed-7a0c2725f9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558040883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3558040883
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3929309011
Short name T22
Test name
Test status
Simulation time 104251418796 ps
CPU time 933.06 seconds
Started Mar 26 02:32:15 PM PDT 24
Finished Mar 26 02:47:48 PM PDT 24
Peak memory 190796 kb
Host smart-cbc1bb55-5026-4841-85a7-2e4c2b6e63c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929309011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3929309011
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1053316375
Short name T308
Test name
Test status
Simulation time 365255537141 ps
CPU time 581.17 seconds
Started Mar 26 02:32:18 PM PDT 24
Finished Mar 26 02:41:59 PM PDT 24
Peak memory 182632 kb
Host smart-7ff29377-dd01-4e23-b3b7-4655907a319c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053316375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1053316375
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2733940424
Short name T391
Test name
Test status
Simulation time 169800726073 ps
CPU time 232.2 seconds
Started Mar 26 02:32:13 PM PDT 24
Finished Mar 26 02:36:05 PM PDT 24
Peak memory 182884 kb
Host smart-45e7ba21-8709-4459-bccd-8c31229feb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733940424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2733940424
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.557108563
Short name T104
Test name
Test status
Simulation time 248129116798 ps
CPU time 153.37 seconds
Started Mar 26 02:32:13 PM PDT 24
Finished Mar 26 02:34:47 PM PDT 24
Peak memory 190876 kb
Host smart-fd612577-7a31-4688-8a92-a12f27a80234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557108563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.557108563
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.93778270
Short name T277
Test name
Test status
Simulation time 52613624101 ps
CPU time 73.82 seconds
Started Mar 26 02:32:20 PM PDT 24
Finished Mar 26 02:33:34 PM PDT 24
Peak memory 190868 kb
Host smart-ba84eb88-eb35-430d-a60b-9141d2ce605d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93778270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.93778270
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.104272089
Short name T14
Test name
Test status
Simulation time 313744336 ps
CPU time 0.94 seconds
Started Mar 26 02:32:15 PM PDT 24
Finished Mar 26 02:32:16 PM PDT 24
Peak memory 215712 kb
Host smart-a734f14c-fda6-453c-b21e-83e641cbb751
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104272089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.104272089
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1999257700
Short name T439
Test name
Test status
Simulation time 88162505341 ps
CPU time 72.78 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:33:47 PM PDT 24
Peak memory 182576 kb
Host smart-9b73768d-273f-4276-ac5f-393b18beb29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999257700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1999257700
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2911766518
Short name T311
Test name
Test status
Simulation time 72136293287 ps
CPU time 144.53 seconds
Started Mar 26 02:32:37 PM PDT 24
Finished Mar 26 02:35:03 PM PDT 24
Peak memory 190844 kb
Host smart-9908e773-e44c-49d7-afc0-a4801300f25a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911766518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2911766518
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4006704193
Short name T422
Test name
Test status
Simulation time 433466698 ps
CPU time 0.77 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:32:35 PM PDT 24
Peak memory 182508 kb
Host smart-db6af2e6-7f3e-4350-86f5-28425c54938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006704193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4006704193
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3719048528
Short name T230
Test name
Test status
Simulation time 570624724646 ps
CPU time 338.45 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:38:14 PM PDT 24
Peak memory 195116 kb
Host smart-9bf9bec8-0278-4daf-85e1-5d96aa34708b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719048528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3719048528
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.4220972879
Short name T174
Test name
Test status
Simulation time 99563247847 ps
CPU time 47.34 seconds
Started Mar 26 02:35:36 PM PDT 24
Finished Mar 26 02:36:23 PM PDT 24
Peak memory 190860 kb
Host smart-009586cc-ab18-43b3-8a89-dff5e8bec768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220972879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4220972879
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2649993701
Short name T177
Test name
Test status
Simulation time 41477709474 ps
CPU time 710.52 seconds
Started Mar 26 02:35:33 PM PDT 24
Finished Mar 26 02:47:24 PM PDT 24
Peak memory 190860 kb
Host smart-0767f5a2-be89-4b8c-ae04-364e6946f827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649993701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2649993701
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.664147762
Short name T5
Test name
Test status
Simulation time 689770882071 ps
CPU time 184.63 seconds
Started Mar 26 02:35:36 PM PDT 24
Finished Mar 26 02:38:41 PM PDT 24
Peak memory 190844 kb
Host smart-c541f4e7-0fdb-4e58-a99a-682b65451450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664147762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.664147762
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.884505165
Short name T315
Test name
Test status
Simulation time 295617932358 ps
CPU time 166.73 seconds
Started Mar 26 02:35:34 PM PDT 24
Finished Mar 26 02:38:21 PM PDT 24
Peak memory 190900 kb
Host smart-926e8252-533f-4686-99ae-c78a91768468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884505165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.884505165
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3218213321
Short name T111
Test name
Test status
Simulation time 187500738197 ps
CPU time 1324.35 seconds
Started Mar 26 02:35:33 PM PDT 24
Finished Mar 26 02:57:38 PM PDT 24
Peak memory 190816 kb
Host smart-7645795a-2fe8-4aa5-8556-574185530bf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218213321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3218213321
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.266019770
Short name T433
Test name
Test status
Simulation time 137277961067 ps
CPU time 65.74 seconds
Started Mar 26 02:35:33 PM PDT 24
Finished Mar 26 02:36:39 PM PDT 24
Peak memory 190872 kb
Host smart-54ebf8a0-dd43-417a-b8fa-8b4f2e213c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266019770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.266019770
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1301832585
Short name T25
Test name
Test status
Simulation time 18618325488 ps
CPU time 17.98 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:32:53 PM PDT 24
Peak memory 182708 kb
Host smart-a99f21d9-8a3c-4b22-ba5a-1d20c2544423
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301832585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1301832585
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1751733984
Short name T379
Test name
Test status
Simulation time 518095720254 ps
CPU time 210.69 seconds
Started Mar 26 02:32:36 PM PDT 24
Finished Mar 26 02:36:06 PM PDT 24
Peak memory 182604 kb
Host smart-0d44cfb5-5f98-4c3c-95d4-2586eebfce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751733984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1751733984
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.994195747
Short name T359
Test name
Test status
Simulation time 272641714119 ps
CPU time 111.09 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:34:26 PM PDT 24
Peak memory 190896 kb
Host smart-6aa583dc-8cf9-44b1-8d26-c101f3fc1e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994195747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.994195747
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4002694320
Short name T342
Test name
Test status
Simulation time 40943069896 ps
CPU time 68.4 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:33:43 PM PDT 24
Peak memory 182648 kb
Host smart-68e6ed5b-7721-4555-8bdd-39e016cf3739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002694320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4002694320
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3134458368
Short name T232
Test name
Test status
Simulation time 1081394877303 ps
CPU time 238.65 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:36:33 PM PDT 24
Peak memory 190876 kb
Host smart-b1d9faf3-43fb-49f0-9a3c-f0c2849a1b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134458368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3134458368
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.1005084978
Short name T448
Test name
Test status
Simulation time 290434273807 ps
CPU time 148.01 seconds
Started Mar 26 02:35:36 PM PDT 24
Finished Mar 26 02:38:04 PM PDT 24
Peak memory 190828 kb
Host smart-117aacdc-8270-4303-a592-ee6e14a30b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005084978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1005084978
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3117776194
Short name T23
Test name
Test status
Simulation time 50903551155 ps
CPU time 129.65 seconds
Started Mar 26 02:35:34 PM PDT 24
Finished Mar 26 02:37:44 PM PDT 24
Peak memory 182668 kb
Host smart-62171ce4-b545-4711-8d0d-56b6ab706fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117776194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3117776194
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.357710962
Short name T263
Test name
Test status
Simulation time 55822073689 ps
CPU time 80.48 seconds
Started Mar 26 02:35:34 PM PDT 24
Finished Mar 26 02:36:54 PM PDT 24
Peak memory 190892 kb
Host smart-a18d45ab-864a-4ee5-b8b6-68e17af3594f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357710962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.357710962
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3865889830
Short name T142
Test name
Test status
Simulation time 237735891747 ps
CPU time 956.09 seconds
Started Mar 26 02:35:33 PM PDT 24
Finished Mar 26 02:51:29 PM PDT 24
Peak memory 190844 kb
Host smart-972b1dba-89e0-44fd-b2a1-726c04d61fb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865889830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3865889830
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.402344442
Short name T354
Test name
Test status
Simulation time 56872864257 ps
CPU time 96.67 seconds
Started Mar 26 02:35:42 PM PDT 24
Finished Mar 26 02:37:19 PM PDT 24
Peak memory 193740 kb
Host smart-54c74175-0698-4471-a079-f61a3659f9fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402344442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.402344442
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3095357190
Short name T205
Test name
Test status
Simulation time 153567764841 ps
CPU time 222.26 seconds
Started Mar 26 02:35:43 PM PDT 24
Finished Mar 26 02:39:25 PM PDT 24
Peak memory 190880 kb
Host smart-0fed16b5-4ab6-440b-ac62-d2068d6b0b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095357190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3095357190
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3662288313
Short name T256
Test name
Test status
Simulation time 193090916345 ps
CPU time 1193.44 seconds
Started Mar 26 02:35:45 PM PDT 24
Finished Mar 26 02:55:38 PM PDT 24
Peak memory 190820 kb
Host smart-0adbeb7c-3b77-4c8f-b392-fd09c0a07e06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662288313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3662288313
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3143577430
Short name T134
Test name
Test status
Simulation time 98245582398 ps
CPU time 87.94 seconds
Started Mar 26 02:35:43 PM PDT 24
Finished Mar 26 02:37:11 PM PDT 24
Peak memory 190808 kb
Host smart-94c8b7ef-ab2b-4a10-84d4-5182849fdec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143577430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3143577430
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1174412452
Short name T21
Test name
Test status
Simulation time 68197086318 ps
CPU time 109.73 seconds
Started Mar 26 02:32:32 PM PDT 24
Finished Mar 26 02:34:22 PM PDT 24
Peak memory 182868 kb
Host smart-131fcd71-6db4-4790-80d6-2995811d65a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174412452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1174412452
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3007250243
Short name T438
Test name
Test status
Simulation time 127591172085 ps
CPU time 172.1 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:35:26 PM PDT 24
Peak memory 182672 kb
Host smart-6b3065b6-14d3-433a-bbfb-6d7e02cb1de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007250243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3007250243
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/121.rv_timer_random.1527770132
Short name T67
Test name
Test status
Simulation time 190230269769 ps
CPU time 489.88 seconds
Started Mar 26 02:35:42 PM PDT 24
Finished Mar 26 02:43:52 PM PDT 24
Peak memory 190840 kb
Host smart-dcac31b5-c192-411f-8f06-caba4726fae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527770132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1527770132
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.938899603
Short name T286
Test name
Test status
Simulation time 330024058016 ps
CPU time 412.85 seconds
Started Mar 26 02:35:44 PM PDT 24
Finished Mar 26 02:42:37 PM PDT 24
Peak memory 190888 kb
Host smart-3809179c-ab04-46ff-9c30-25fe39941b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938899603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.938899603
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4198249018
Short name T406
Test name
Test status
Simulation time 44164727021 ps
CPU time 71.26 seconds
Started Mar 26 02:35:52 PM PDT 24
Finished Mar 26 02:37:04 PM PDT 24
Peak memory 182464 kb
Host smart-4b75d3e4-01c1-480f-9104-4b451810df0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198249018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4198249018
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4140036595
Short name T282
Test name
Test status
Simulation time 248709293851 ps
CPU time 405.21 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:39:20 PM PDT 24
Peak memory 182688 kb
Host smart-cc7b3fb8-a737-43ad-9869-e1a70b8f1b6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140036595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4140036595
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.4283892240
Short name T57
Test name
Test status
Simulation time 35252923168 ps
CPU time 60.23 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:33:36 PM PDT 24
Peak memory 182636 kb
Host smart-4cd2c07f-0c43-4154-97ff-7c275ee1e395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283892240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.4283892240
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.159858353
Short name T242
Test name
Test status
Simulation time 84284127491 ps
CPU time 1309.17 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:54:23 PM PDT 24
Peak memory 190836 kb
Host smart-4166c5d0-7646-4ddf-957c-76884de0a893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159858353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.159858353
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3661135670
Short name T365
Test name
Test status
Simulation time 25808288757 ps
CPU time 39.13 seconds
Started Mar 26 02:32:36 PM PDT 24
Finished Mar 26 02:33:15 PM PDT 24
Peak memory 190892 kb
Host smart-c93ee115-69a4-418b-9ee1-744c2d6a290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661135670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3661135670
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2892720554
Short name T429
Test name
Test status
Simulation time 689936168869 ps
CPU time 234.88 seconds
Started Mar 26 02:32:33 PM PDT 24
Finished Mar 26 02:36:28 PM PDT 24
Peak memory 182700 kb
Host smart-bb7feef9-c064-4ef6-9204-65cf122b2c1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892720554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2892720554
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.1435705439
Short name T356
Test name
Test status
Simulation time 57624939182 ps
CPU time 102.05 seconds
Started Mar 26 02:35:54 PM PDT 24
Finished Mar 26 02:37:36 PM PDT 24
Peak memory 190852 kb
Host smart-9e24a3f7-e37e-4d0b-bb97-851abd08f559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435705439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1435705439
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2815209914
Short name T250
Test name
Test status
Simulation time 95721465996 ps
CPU time 162.24 seconds
Started Mar 26 02:35:53 PM PDT 24
Finished Mar 26 02:38:35 PM PDT 24
Peak memory 190880 kb
Host smart-9edfa31e-4240-4f63-a52e-3c45f93a3c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815209914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2815209914
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3175272617
Short name T331
Test name
Test status
Simulation time 512906978756 ps
CPU time 1140.85 seconds
Started Mar 26 02:35:55 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 190776 kb
Host smart-70773cfa-8818-48e0-bb9e-f049655721e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175272617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3175272617
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2847826564
Short name T278
Test name
Test status
Simulation time 595449933242 ps
CPU time 240.65 seconds
Started Mar 26 02:36:00 PM PDT 24
Finished Mar 26 02:40:01 PM PDT 24
Peak memory 190820 kb
Host smart-3dbb9e9d-faef-492d-94ea-9326c58cab46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847826564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2847826564
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2765318666
Short name T330
Test name
Test status
Simulation time 84664671426 ps
CPU time 128.49 seconds
Started Mar 26 02:35:55 PM PDT 24
Finished Mar 26 02:38:03 PM PDT 24
Peak memory 190804 kb
Host smart-43aea0bd-7d89-4770-9920-2a0943d971f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765318666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2765318666
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1383606773
Short name T138
Test name
Test status
Simulation time 75170599627 ps
CPU time 116.49 seconds
Started Mar 26 02:35:53 PM PDT 24
Finished Mar 26 02:37:49 PM PDT 24
Peak memory 190880 kb
Host smart-6973563c-eb12-4f7c-8ffa-ea1d7cf41944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383606773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1383606773
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.4280446385
Short name T357
Test name
Test status
Simulation time 136278341119 ps
CPU time 245.96 seconds
Started Mar 26 02:35:57 PM PDT 24
Finished Mar 26 02:40:03 PM PDT 24
Peak memory 190872 kb
Host smart-81ee1777-bd05-48bc-adcf-e8fe92243d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280446385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4280446385
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3440613582
Short name T437
Test name
Test status
Simulation time 191812042406 ps
CPU time 268.4 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:37:03 PM PDT 24
Peak memory 182668 kb
Host smart-bcb093e1-087a-4c27-b35b-36916e3ce952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440613582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3440613582
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1530218311
Short name T413
Test name
Test status
Simulation time 34219577996 ps
CPU time 17.25 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:32:52 PM PDT 24
Peak memory 182676 kb
Host smart-131c0b51-66da-4685-830b-65a59b650072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530218311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1530218311
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.136902086
Short name T350
Test name
Test status
Simulation time 139459565632 ps
CPU time 60.77 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:33:35 PM PDT 24
Peak memory 182652 kb
Host smart-4451d803-218a-4d7f-8472-9e95960073ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136902086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.136902086
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.622852235
Short name T197
Test name
Test status
Simulation time 471309259655 ps
CPU time 212 seconds
Started Mar 26 02:35:52 PM PDT 24
Finished Mar 26 02:39:25 PM PDT 24
Peak memory 190904 kb
Host smart-3679c273-a010-4013-ab85-154a1ffe8347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622852235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.622852235
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2465035117
Short name T358
Test name
Test status
Simulation time 663002225809 ps
CPU time 111.4 seconds
Started Mar 26 02:36:04 PM PDT 24
Finished Mar 26 02:37:55 PM PDT 24
Peak memory 182656 kb
Host smart-d9f60f91-7fdb-4618-ab58-93ec96f7f86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465035117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2465035117
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1510716741
Short name T270
Test name
Test status
Simulation time 268595515080 ps
CPU time 84.45 seconds
Started Mar 26 02:36:02 PM PDT 24
Finished Mar 26 02:37:27 PM PDT 24
Peak memory 190828 kb
Host smart-4ab72275-3ddc-4cbb-a2bf-9ca10d8ec821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510716741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1510716741
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1756020348
Short name T374
Test name
Test status
Simulation time 214735976527 ps
CPU time 61.55 seconds
Started Mar 26 02:36:03 PM PDT 24
Finished Mar 26 02:37:05 PM PDT 24
Peak memory 182656 kb
Host smart-89a6bad1-d8fb-4963-9d9c-e7c6d43bf68b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756020348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1756020348
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3751869376
Short name T325
Test name
Test status
Simulation time 180563834889 ps
CPU time 431 seconds
Started Mar 26 02:36:02 PM PDT 24
Finished Mar 26 02:43:14 PM PDT 24
Peak memory 190776 kb
Host smart-85bada89-567b-4bc9-8099-316ab5ab53d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751869376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3751869376
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1503217710
Short name T243
Test name
Test status
Simulation time 275624039267 ps
CPU time 251.3 seconds
Started Mar 26 02:36:03 PM PDT 24
Finished Mar 26 02:40:15 PM PDT 24
Peak memory 190816 kb
Host smart-12079988-382d-44f7-867c-379f1d1eea2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503217710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1503217710
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.546008166
Short name T442
Test name
Test status
Simulation time 455118993951 ps
CPU time 268.53 seconds
Started Mar 26 02:32:36 PM PDT 24
Finished Mar 26 02:37:04 PM PDT 24
Peak memory 182640 kb
Host smart-ff84b7f4-3839-4a0e-a537-886fd56fa254
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546008166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.546008166
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1499216888
Short name T394
Test name
Test status
Simulation time 53967583700 ps
CPU time 81.62 seconds
Started Mar 26 02:32:36 PM PDT 24
Finished Mar 26 02:33:57 PM PDT 24
Peak memory 182628 kb
Host smart-1ae10322-9c18-4382-90c4-46b0ea136e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499216888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1499216888
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.4161515581
Short name T260
Test name
Test status
Simulation time 861882828096 ps
CPU time 816.18 seconds
Started Mar 26 02:32:36 PM PDT 24
Finished Mar 26 02:46:13 PM PDT 24
Peak memory 190912 kb
Host smart-024e055a-c34b-4c68-b851-1d95432fe6ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161515581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4161515581
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3295488517
Short name T411
Test name
Test status
Simulation time 283043223 ps
CPU time 0.73 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:32:35 PM PDT 24
Peak memory 191180 kb
Host smart-96943850-b83c-42b1-b0f3-108753edfce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295488517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3295488517
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3714359460
Short name T328
Test name
Test status
Simulation time 230764727009 ps
CPU time 932.28 seconds
Started Mar 26 02:36:02 PM PDT 24
Finished Mar 26 02:51:35 PM PDT 24
Peak memory 190868 kb
Host smart-f5675f11-f8ef-4c8d-9782-dcb7251962aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714359460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3714359460
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1926630963
Short name T120
Test name
Test status
Simulation time 93852810127 ps
CPU time 1139.86 seconds
Started Mar 26 02:36:13 PM PDT 24
Finished Mar 26 02:55:13 PM PDT 24
Peak memory 190852 kb
Host smart-49f5a2ba-d0a0-4237-baa2-2b09c02b1168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926630963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1926630963
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1254881016
Short name T361
Test name
Test status
Simulation time 72246071364 ps
CPU time 321.22 seconds
Started Mar 26 02:36:13 PM PDT 24
Finished Mar 26 02:41:34 PM PDT 24
Peak memory 190812 kb
Host smart-99505617-5d53-455e-a2a5-9965fd701abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254881016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1254881016
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.572782700
Short name T222
Test name
Test status
Simulation time 227202282259 ps
CPU time 544.71 seconds
Started Mar 26 02:36:11 PM PDT 24
Finished Mar 26 02:45:16 PM PDT 24
Peak memory 190812 kb
Host smart-028c4300-53bb-4bf9-8471-ab0302d4f9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572782700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.572782700
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1575625762
Short name T290
Test name
Test status
Simulation time 272037807482 ps
CPU time 95.89 seconds
Started Mar 26 02:36:12 PM PDT 24
Finished Mar 26 02:37:48 PM PDT 24
Peak memory 190780 kb
Host smart-313be16e-4103-4160-a935-11cda1b469be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575625762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1575625762
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2264871916
Short name T50
Test name
Test status
Simulation time 68478313053 ps
CPU time 40.52 seconds
Started Mar 26 02:36:11 PM PDT 24
Finished Mar 26 02:36:53 PM PDT 24
Peak memory 182664 kb
Host smart-e6c1f481-27fb-4b1b-858b-b69d0f08d78a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264871916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2264871916
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.218350550
Short name T149
Test name
Test status
Simulation time 56977491072 ps
CPU time 55.63 seconds
Started Mar 26 02:36:12 PM PDT 24
Finished Mar 26 02:37:07 PM PDT 24
Peak memory 190856 kb
Host smart-c9575636-04f6-4b99-9ec7-e29eca4f0760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218350550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.218350550
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2088232903
Short name T351
Test name
Test status
Simulation time 70147882497 ps
CPU time 313.9 seconds
Started Mar 26 02:36:12 PM PDT 24
Finished Mar 26 02:41:26 PM PDT 24
Peak memory 192936 kb
Host smart-114b3813-5efd-4b15-872e-2d3bf53596f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088232903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2088232903
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3242880845
Short name T247
Test name
Test status
Simulation time 311642505829 ps
CPU time 301.48 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:37:37 PM PDT 24
Peak memory 182720 kb
Host smart-cb09d2af-c449-4666-9ea6-3cb676d5ee19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242880845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3242880845
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1165619445
Short name T382
Test name
Test status
Simulation time 636809339202 ps
CPU time 121.77 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:34:37 PM PDT 24
Peak memory 182608 kb
Host smart-40dd1bbe-6686-43de-92d1-99dc5e186185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165619445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1165619445
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1626740770
Short name T259
Test name
Test status
Simulation time 1410691319271 ps
CPU time 618.97 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:42:54 PM PDT 24
Peak memory 190844 kb
Host smart-9e4c0725-46d4-43bb-970d-f5cae4ea69dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626740770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1626740770
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1469745157
Short name T258
Test name
Test status
Simulation time 16463003009 ps
CPU time 26.68 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:33:02 PM PDT 24
Peak memory 182620 kb
Host smart-0c200ccb-33d4-4d2b-8044-07136d7f930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469745157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1469745157
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2451075868
Short name T344
Test name
Test status
Simulation time 468796116644 ps
CPU time 391.03 seconds
Started Mar 26 02:32:34 PM PDT 24
Finished Mar 26 02:39:05 PM PDT 24
Peak memory 194788 kb
Host smart-56ddf8d4-4ae6-494d-b724-17a8df4bd527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451075868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2451075868
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1430942319
Short name T69
Test name
Test status
Simulation time 52052543316 ps
CPU time 87.98 seconds
Started Mar 26 02:36:23 PM PDT 24
Finished Mar 26 02:37:51 PM PDT 24
Peak memory 182692 kb
Host smart-1330b24b-4d34-42a3-b92a-c294cf79a98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430942319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1430942319
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1526871426
Short name T229
Test name
Test status
Simulation time 306372926908 ps
CPU time 206.93 seconds
Started Mar 26 02:36:23 PM PDT 24
Finished Mar 26 02:39:50 PM PDT 24
Peak memory 193864 kb
Host smart-baadb0a8-2c26-440e-ab5b-7cdb70072afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526871426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1526871426
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1815544319
Short name T436
Test name
Test status
Simulation time 64955475553 ps
CPU time 77.21 seconds
Started Mar 26 02:36:24 PM PDT 24
Finished Mar 26 02:37:42 PM PDT 24
Peak memory 182672 kb
Host smart-821e6f94-164b-4e20-8df3-6ef4e8d7872d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815544319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1815544319
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3581319579
Short name T144
Test name
Test status
Simulation time 467785467811 ps
CPU time 384.31 seconds
Started Mar 26 02:36:24 PM PDT 24
Finished Mar 26 02:42:49 PM PDT 24
Peak memory 190876 kb
Host smart-26cb9880-b3d7-4e79-b1b0-f503e768fc18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581319579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3581319579
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3502715797
Short name T112
Test name
Test status
Simulation time 150560624689 ps
CPU time 298.42 seconds
Started Mar 26 02:36:23 PM PDT 24
Finished Mar 26 02:41:22 PM PDT 24
Peak memory 190888 kb
Host smart-b0472733-d049-4a80-9752-3b8e57e35974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502715797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3502715797
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2986430893
Short name T127
Test name
Test status
Simulation time 59092895003 ps
CPU time 176.88 seconds
Started Mar 26 02:36:24 PM PDT 24
Finished Mar 26 02:39:21 PM PDT 24
Peak memory 190816 kb
Host smart-ec41c2c8-ae10-4444-ab76-c80a5fb3c5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986430893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2986430893
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1498765581
Short name T139
Test name
Test status
Simulation time 79010902211 ps
CPU time 134.3 seconds
Started Mar 26 02:36:21 PM PDT 24
Finished Mar 26 02:38:35 PM PDT 24
Peak memory 194388 kb
Host smart-8d0501c3-9052-454d-bf7a-9b26816f8892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498765581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1498765581
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.690706140
Short name T319
Test name
Test status
Simulation time 29426103432 ps
CPU time 29.7 seconds
Started Mar 26 02:32:38 PM PDT 24
Finished Mar 26 02:33:09 PM PDT 24
Peak memory 182688 kb
Host smart-8b66f203-6a20-447e-ba7b-71903ffaa5ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690706140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.690706140
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3727260048
Short name T426
Test name
Test status
Simulation time 128171833605 ps
CPU time 57.21 seconds
Started Mar 26 02:32:35 PM PDT 24
Finished Mar 26 02:33:32 PM PDT 24
Peak memory 182608 kb
Host smart-ce34d34c-4c60-45ec-951d-cd9213aae157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727260048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3727260048
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1152415922
Short name T227
Test name
Test status
Simulation time 101613041060 ps
CPU time 451.07 seconds
Started Mar 26 02:32:38 PM PDT 24
Finished Mar 26 02:40:09 PM PDT 24
Peak memory 190844 kb
Host smart-86bb9400-c411-4bf7-ab84-4804342b5ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152415922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1152415922
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3808251485
Short name T195
Test name
Test status
Simulation time 562662005777 ps
CPU time 1157.52 seconds
Started Mar 26 02:36:23 PM PDT 24
Finished Mar 26 02:55:40 PM PDT 24
Peak memory 190848 kb
Host smart-fc411036-9307-47c9-b702-da1045b83d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808251485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3808251485
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3959491088
Short name T307
Test name
Test status
Simulation time 201831375955 ps
CPU time 100.68 seconds
Started Mar 26 02:36:23 PM PDT 24
Finished Mar 26 02:38:04 PM PDT 24
Peak memory 190908 kb
Host smart-8d617a13-a252-4a79-b54d-9d8d9ea77822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959491088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3959491088
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3067224960
Short name T26
Test name
Test status
Simulation time 103415269451 ps
CPU time 298.95 seconds
Started Mar 26 02:36:24 PM PDT 24
Finished Mar 26 02:41:23 PM PDT 24
Peak memory 192952 kb
Host smart-6004eca8-5d12-4c99-ab54-f4a119a81846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067224960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3067224960
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2443629142
Short name T155
Test name
Test status
Simulation time 383713085352 ps
CPU time 252.96 seconds
Started Mar 26 02:36:36 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 193396 kb
Host smart-c98057ab-2285-40fc-91ef-f08c006e29f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443629142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2443629142
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1397344383
Short name T178
Test name
Test status
Simulation time 105978766465 ps
CPU time 164.68 seconds
Started Mar 26 02:36:35 PM PDT 24
Finished Mar 26 02:39:20 PM PDT 24
Peak memory 190888 kb
Host smart-7cefb144-4281-4c0e-88e4-6c1e8cb8a52e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397344383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1397344383
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2112331513
Short name T109
Test name
Test status
Simulation time 1717003948723 ps
CPU time 1482.81 seconds
Started Mar 26 02:36:35 PM PDT 24
Finished Mar 26 03:01:18 PM PDT 24
Peak memory 191056 kb
Host smart-911d6102-bacd-4e7d-8395-d695314062cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112331513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2112331513
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.892697476
Short name T337
Test name
Test status
Simulation time 8342601590 ps
CPU time 12.57 seconds
Started Mar 26 02:36:34 PM PDT 24
Finished Mar 26 02:36:46 PM PDT 24
Peak memory 182636 kb
Host smart-40dabd83-be91-4466-8035-d469dd12d4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892697476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.892697476
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.612292113
Short name T128
Test name
Test status
Simulation time 257183775137 ps
CPU time 424.77 seconds
Started Mar 26 02:32:46 PM PDT 24
Finished Mar 26 02:39:53 PM PDT 24
Peak memory 182728 kb
Host smart-648091c1-72cf-41e6-99c6-20d883ac4ad8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612292113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.612292113
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.603031701
Short name T414
Test name
Test status
Simulation time 60355747959 ps
CPU time 78.3 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:34:05 PM PDT 24
Peak memory 182692 kb
Host smart-df26bc01-4937-4be4-936b-f8f11a5d1a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603031701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.603031701
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.936419016
Short name T333
Test name
Test status
Simulation time 124398003160 ps
CPU time 351.38 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:38:37 PM PDT 24
Peak memory 190864 kb
Host smart-16ebaf13-b803-4c6b-8e14-fd184a4c2e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936419016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.936419016
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3754349443
Short name T150
Test name
Test status
Simulation time 25997900345 ps
CPU time 15.68 seconds
Started Mar 26 02:32:48 PM PDT 24
Finished Mar 26 02:33:04 PM PDT 24
Peak memory 190804 kb
Host smart-39cdf9b4-c997-4891-a5c9-ca8d6d0989e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754349443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3754349443
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3737583392
Short name T298
Test name
Test status
Simulation time 111558738168 ps
CPU time 183.58 seconds
Started Mar 26 02:36:33 PM PDT 24
Finished Mar 26 02:39:37 PM PDT 24
Peak memory 190864 kb
Host smart-29659705-5d5d-48f6-a938-04e29003bdb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737583392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3737583392
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1123812739
Short name T252
Test name
Test status
Simulation time 92166732511 ps
CPU time 584.8 seconds
Started Mar 26 02:36:35 PM PDT 24
Finished Mar 26 02:46:20 PM PDT 24
Peak memory 190844 kb
Host smart-ec6a46e1-ff65-4d62-b5f9-8d2e9f0c39f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123812739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1123812739
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2859831117
Short name T188
Test name
Test status
Simulation time 362155985237 ps
CPU time 197.09 seconds
Started Mar 26 02:36:33 PM PDT 24
Finished Mar 26 02:39:51 PM PDT 24
Peak memory 190828 kb
Host smart-c5e3e394-bbbb-4373-aa1a-4109cfe70ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859831117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2859831117
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1780323320
Short name T284
Test name
Test status
Simulation time 278630116374 ps
CPU time 116.52 seconds
Started Mar 26 02:36:46 PM PDT 24
Finished Mar 26 02:38:44 PM PDT 24
Peak memory 191056 kb
Host smart-48dfd6e0-02b3-4fad-bce3-6ea0ecb8b5e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780323320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1780323320
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2770921266
Short name T54
Test name
Test status
Simulation time 20593159114 ps
CPU time 19.28 seconds
Started Mar 26 02:36:45 PM PDT 24
Finished Mar 26 02:37:04 PM PDT 24
Peak memory 182616 kb
Host smart-709a2a0a-a514-4375-bded-49a55f3c8fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770921266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2770921266
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1839165412
Short name T238
Test name
Test status
Simulation time 167874036203 ps
CPU time 298.44 seconds
Started Mar 26 02:36:46 PM PDT 24
Finished Mar 26 02:41:46 PM PDT 24
Peak memory 190852 kb
Host smart-87217880-add3-4c4d-8686-0bbdb6de48c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839165412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1839165412
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.991735070
Short name T320
Test name
Test status
Simulation time 181088720143 ps
CPU time 158.48 seconds
Started Mar 26 02:36:46 PM PDT 24
Finished Mar 26 02:39:25 PM PDT 24
Peak memory 182704 kb
Host smart-d849fd13-ce1e-439f-bbd4-49b0e0bf44a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991735070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.991735070
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2928470420
Short name T179
Test name
Test status
Simulation time 227668286166 ps
CPU time 112.95 seconds
Started Mar 26 02:36:46 PM PDT 24
Finished Mar 26 02:38:39 PM PDT 24
Peak memory 190808 kb
Host smart-c0a7635a-c607-4e51-a6e7-f4ecb009b96c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928470420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2928470420
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1958691883
Short name T347
Test name
Test status
Simulation time 239585029727 ps
CPU time 139.22 seconds
Started Mar 26 02:36:46 PM PDT 24
Finished Mar 26 02:39:05 PM PDT 24
Peak memory 190828 kb
Host smart-a0821d65-4d8f-46a0-9240-fc7d04dd44db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958691883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1958691883
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3444654949
Short name T236
Test name
Test status
Simulation time 154889776100 ps
CPU time 217.41 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:36:24 PM PDT 24
Peak memory 182684 kb
Host smart-a95ee478-0afa-4806-828c-30f9ee31ce5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444654949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3444654949
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2322186205
Short name T421
Test name
Test status
Simulation time 114701543509 ps
CPU time 155.68 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:35:22 PM PDT 24
Peak memory 182664 kb
Host smart-1083b65d-58fe-4ae8-9cd6-8e82a1a487a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322186205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2322186205
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3334168699
Short name T453
Test name
Test status
Simulation time 123782928216 ps
CPU time 282.55 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:37:30 PM PDT 24
Peak memory 190844 kb
Host smart-b205dfd3-a493-41c5-8e24-9acf14c65906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334168699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3334168699
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2740904307
Short name T449
Test name
Test status
Simulation time 90173297471 ps
CPU time 179.65 seconds
Started Mar 26 02:32:48 PM PDT 24
Finished Mar 26 02:35:49 PM PDT 24
Peak memory 194396 kb
Host smart-1a9fbea8-050f-485d-b08e-db4bd9cdf016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740904307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2740904307
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1825160812
Short name T249
Test name
Test status
Simulation time 1730286718201 ps
CPU time 1155.52 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:52:02 PM PDT 24
Peak memory 190856 kb
Host smart-c13af895-9ff1-46b2-b0c9-91ac6aeadf94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825160812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1825160812
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.2725425024
Short name T125
Test name
Test status
Simulation time 524273072648 ps
CPU time 1485.46 seconds
Started Mar 26 02:36:47 PM PDT 24
Finished Mar 26 03:01:33 PM PDT 24
Peak memory 190872 kb
Host smart-0924c8f6-c857-40b5-a341-f7db66c930bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725425024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2725425024
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.4172189624
Short name T154
Test name
Test status
Simulation time 205692339670 ps
CPU time 136.71 seconds
Started Mar 26 02:36:45 PM PDT 24
Finished Mar 26 02:39:02 PM PDT 24
Peak memory 190868 kb
Host smart-ec38d910-cde1-475a-88f0-df4fe8b70399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172189624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.4172189624
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3322651761
Short name T366
Test name
Test status
Simulation time 293558737353 ps
CPU time 192.94 seconds
Started Mar 26 02:36:47 PM PDT 24
Finished Mar 26 02:40:01 PM PDT 24
Peak memory 190828 kb
Host smart-5db12eb3-b01f-4a1f-88c3-85e15a7ea6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322651761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3322651761
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1056632413
Short name T294
Test name
Test status
Simulation time 1799878515565 ps
CPU time 943.34 seconds
Started Mar 26 02:36:46 PM PDT 24
Finished Mar 26 02:52:29 PM PDT 24
Peak memory 190800 kb
Host smart-fc7cf028-be25-4da6-9c8c-46327544940b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056632413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1056632413
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1006980940
Short name T24
Test name
Test status
Simulation time 168677906168 ps
CPU time 96.31 seconds
Started Mar 26 02:36:44 PM PDT 24
Finished Mar 26 02:38:20 PM PDT 24
Peak memory 182668 kb
Host smart-c0833080-6d30-4181-af5a-909b5c28e5dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006980940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1006980940
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.408681894
Short name T326
Test name
Test status
Simulation time 107098280401 ps
CPU time 41.53 seconds
Started Mar 26 02:36:47 PM PDT 24
Finished Mar 26 02:37:29 PM PDT 24
Peak memory 182668 kb
Host smart-cde22510-4e2e-46f2-86e5-837d4ed50e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408681894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.408681894
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.394110150
Short name T445
Test name
Test status
Simulation time 497925710849 ps
CPU time 157.52 seconds
Started Mar 26 02:36:45 PM PDT 24
Finished Mar 26 02:39:23 PM PDT 24
Peak memory 192116 kb
Host smart-1bc8d671-ae51-4415-8031-2b39d6626f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394110150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.394110150
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1875545969
Short name T164
Test name
Test status
Simulation time 11864380965 ps
CPU time 20.3 seconds
Started Mar 26 02:36:46 PM PDT 24
Finished Mar 26 02:37:06 PM PDT 24
Peak memory 190892 kb
Host smart-cea21347-f505-49ab-bf30-2d97f5b3676e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875545969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1875545969
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3959838525
Short name T231
Test name
Test status
Simulation time 309225925765 ps
CPU time 140.53 seconds
Started Mar 26 02:36:45 PM PDT 24
Finished Mar 26 02:39:06 PM PDT 24
Peak memory 182644 kb
Host smart-a6d2df1e-37e4-49f6-8833-a45fc4eb7b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959838525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3959838525
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3261760329
Short name T133
Test name
Test status
Simulation time 1368123962861 ps
CPU time 832.56 seconds
Started Mar 26 02:32:20 PM PDT 24
Finished Mar 26 02:46:13 PM PDT 24
Peak memory 182704 kb
Host smart-b40caaff-bc8f-4957-8a88-c11ba4e1723c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261760329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3261760329
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.382684263
Short name T405
Test name
Test status
Simulation time 236234888637 ps
CPU time 104.03 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 02:34:01 PM PDT 24
Peak memory 182676 kb
Host smart-057d3857-f58d-4216-89bb-917922ad6d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382684263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.382684263
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3395822672
Short name T306
Test name
Test status
Simulation time 64529758468 ps
CPU time 114.67 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 02:34:12 PM PDT 24
Peak memory 190828 kb
Host smart-9aba6f8c-f608-4d47-a63a-c009552138a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395822672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3395822672
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3479828560
Short name T397
Test name
Test status
Simulation time 34729918776 ps
CPU time 31.26 seconds
Started Mar 26 02:32:13 PM PDT 24
Finished Mar 26 02:32:45 PM PDT 24
Peak memory 194336 kb
Host smart-e2f25180-9f73-468c-ab56-8096b71e9583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479828560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3479828560
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.88472080
Short name T15
Test name
Test status
Simulation time 85834961 ps
CPU time 0.89 seconds
Started Mar 26 02:32:14 PM PDT 24
Finished Mar 26 02:32:15 PM PDT 24
Peak memory 214296 kb
Host smart-aa7461bf-5cff-4563-91bf-99f84fc42e8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88472080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.88472080
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.125546151
Short name T39
Test name
Test status
Simulation time 151884096651 ps
CPU time 787.83 seconds
Started Mar 26 02:32:20 PM PDT 24
Finished Mar 26 02:45:28 PM PDT 24
Peak memory 212124 kb
Host smart-a5a62d4c-2d82-4384-af0f-08db380b7fa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125546151 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.125546151
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2310662320
Short name T107
Test name
Test status
Simulation time 241348911655 ps
CPU time 328.07 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:38:15 PM PDT 24
Peak memory 182732 kb
Host smart-652ccec3-ed43-4b50-b4e2-7c5323ff4684
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310662320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2310662320
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1079904517
Short name T409
Test name
Test status
Simulation time 29297652250 ps
CPU time 20.65 seconds
Started Mar 26 02:32:46 PM PDT 24
Finished Mar 26 02:33:08 PM PDT 24
Peak memory 182584 kb
Host smart-e728f66a-fa3c-46ff-87cb-bf9d5a66b127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079904517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1079904517
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3699381462
Short name T184
Test name
Test status
Simulation time 199977768164 ps
CPU time 1574.39 seconds
Started Mar 26 02:32:46 PM PDT 24
Finished Mar 26 02:59:02 PM PDT 24
Peak memory 190908 kb
Host smart-f21f61a8-d1bd-49b1-94bb-53e1f8b87586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699381462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3699381462
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3657293973
Short name T362
Test name
Test status
Simulation time 98535781748 ps
CPU time 157.06 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:35:24 PM PDT 24
Peak memory 182592 kb
Host smart-a4090f7c-9559-4c2d-a925-e80eb195ec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657293973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3657293973
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2248916339
Short name T165
Test name
Test status
Simulation time 748731668865 ps
CPU time 419.87 seconds
Started Mar 26 02:32:44 PM PDT 24
Finished Mar 26 02:39:45 PM PDT 24
Peak memory 182712 kb
Host smart-1787462d-ab00-4b3e-b19c-3d05e3bfae68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248916339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2248916339
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2857432775
Short name T435
Test name
Test status
Simulation time 497532788833 ps
CPU time 204.63 seconds
Started Mar 26 02:32:46 PM PDT 24
Finished Mar 26 02:36:12 PM PDT 24
Peak memory 182676 kb
Host smart-525c2d0f-d138-4cf1-b7a6-004b7ff58bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857432775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2857432775
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.852060778
Short name T376
Test name
Test status
Simulation time 92505614578 ps
CPU time 105.08 seconds
Started Mar 26 02:32:44 PM PDT 24
Finished Mar 26 02:34:31 PM PDT 24
Peak memory 182680 kb
Host smart-f565176c-5943-49a0-b7a3-0b22828b2c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852060778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.852060778
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1202119777
Short name T440
Test name
Test status
Simulation time 344762673 ps
CPU time 1.1 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:32:48 PM PDT 24
Peak memory 182484 kb
Host smart-edc3f97d-1315-4b44-8e19-2b83dfa0f6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202119777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1202119777
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2831010157
Short name T63
Test name
Test status
Simulation time 869493334814 ps
CPU time 493.45 seconds
Started Mar 26 02:32:48 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 190844 kb
Host smart-3abb1a03-2448-4cf5-be08-9c6948d4e1e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831010157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2831010157
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.21160434
Short name T38
Test name
Test status
Simulation time 90178328370 ps
CPU time 485.67 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 205564 kb
Host smart-52f4b5d8-612f-4397-9ba2-10cbebd2b15d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160434 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.21160434
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4016826697
Short name T341
Test name
Test status
Simulation time 148778237018 ps
CPU time 144.77 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:35:11 PM PDT 24
Peak memory 182720 kb
Host smart-e64d9c2d-20fa-406d-98a4-a4f5b0b8d911
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016826697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4016826697
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.986609711
Short name T423
Test name
Test status
Simulation time 334322078365 ps
CPU time 56.31 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:33:43 PM PDT 24
Peak memory 182680 kb
Host smart-730748ab-7b88-4353-a2e9-4fc0c60a1189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986609711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.986609711
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1331256447
Short name T305
Test name
Test status
Simulation time 167088722559 ps
CPU time 1455.65 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:57:02 PM PDT 24
Peak memory 190836 kb
Host smart-d1d5f09c-90ad-48b0-8882-90e4b931a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331256447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1331256447
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.482345751
Short name T272
Test name
Test status
Simulation time 270916965571 ps
CPU time 246.5 seconds
Started Mar 26 02:32:45 PM PDT 24
Finished Mar 26 02:36:54 PM PDT 24
Peak memory 182632 kb
Host smart-cadd4538-5e9d-4180-b531-9778ffe025cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482345751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.482345751
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3481048154
Short name T399
Test name
Test status
Simulation time 351746666048 ps
CPU time 157.45 seconds
Started Mar 26 02:32:46 PM PDT 24
Finished Mar 26 02:35:25 PM PDT 24
Peak memory 182636 kb
Host smart-b6f2a70e-0e49-4100-87dd-f8bdcc5bb46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481048154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3481048154
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.176999174
Short name T346
Test name
Test status
Simulation time 77453298054 ps
CPU time 129.38 seconds
Started Mar 26 02:32:44 PM PDT 24
Finished Mar 26 02:34:55 PM PDT 24
Peak memory 190896 kb
Host smart-998b0089-4d0c-42c2-9141-1431a3187bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176999174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.176999174
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3223448956
Short name T403
Test name
Test status
Simulation time 178993844 ps
CPU time 1.31 seconds
Started Mar 26 02:32:57 PM PDT 24
Finished Mar 26 02:33:00 PM PDT 24
Peak memory 182620 kb
Host smart-68ad1b8c-f6a2-4568-88d9-692eee9a75bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223448956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3223448956
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2211764478
Short name T118
Test name
Test status
Simulation time 238872185427 ps
CPU time 230.5 seconds
Started Mar 26 02:32:59 PM PDT 24
Finished Mar 26 02:36:50 PM PDT 24
Peak memory 182724 kb
Host smart-8befba5f-b779-40c0-a2a5-4634e21ee896
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211764478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2211764478
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1533147375
Short name T452
Test name
Test status
Simulation time 173721958806 ps
CPU time 63.98 seconds
Started Mar 26 02:32:54 PM PDT 24
Finished Mar 26 02:34:00 PM PDT 24
Peak memory 182688 kb
Host smart-47c05028-de8b-4250-bc92-9c3d050bbc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533147375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1533147375
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.417410422
Short name T68
Test name
Test status
Simulation time 321074279000 ps
CPU time 215.44 seconds
Started Mar 26 02:32:55 PM PDT 24
Finished Mar 26 02:36:31 PM PDT 24
Peak memory 190876 kb
Host smart-80b41a1e-a575-4402-942f-6488dc345820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417410422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.417410422
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1049901824
Short name T334
Test name
Test status
Simulation time 127701372561 ps
CPU time 119.19 seconds
Started Mar 26 02:32:57 PM PDT 24
Finished Mar 26 02:34:58 PM PDT 24
Peak memory 190620 kb
Host smart-4ceade10-abba-4606-9217-dda4344bacb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049901824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1049901824
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3340568311
Short name T343
Test name
Test status
Simulation time 195129472500 ps
CPU time 351.51 seconds
Started Mar 26 02:32:59 PM PDT 24
Finished Mar 26 02:38:50 PM PDT 24
Peak memory 182728 kb
Host smart-6353cf32-413a-4e88-916f-5f8941cc5231
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340568311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3340568311
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2388088329
Short name T447
Test name
Test status
Simulation time 300051970006 ps
CPU time 178.02 seconds
Started Mar 26 02:32:55 PM PDT 24
Finished Mar 26 02:35:54 PM PDT 24
Peak memory 182664 kb
Host smart-4069293e-132a-4aa7-9217-42fa4248b609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388088329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2388088329
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.156129286
Short name T121
Test name
Test status
Simulation time 207351021304 ps
CPU time 266.69 seconds
Started Mar 26 02:32:58 PM PDT 24
Finished Mar 26 02:37:25 PM PDT 24
Peak memory 190784 kb
Host smart-87c2fa9c-7c71-4d97-a99f-02a752b9731d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156129286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.156129286
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.338672666
Short name T207
Test name
Test status
Simulation time 53411873331 ps
CPU time 406.74 seconds
Started Mar 26 02:32:55 PM PDT 24
Finished Mar 26 02:39:43 PM PDT 24
Peak memory 194476 kb
Host smart-d97ed043-1c01-46c4-99c1-908f99c368bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338672666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.338672666
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.4210077859
Short name T34
Test name
Test status
Simulation time 125197173695 ps
CPU time 265.88 seconds
Started Mar 26 02:32:57 PM PDT 24
Finished Mar 26 02:37:24 PM PDT 24
Peak memory 205496 kb
Host smart-d1434ff8-a09b-412b-96cb-a76ba9d050d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210077859 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.4210077859
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2102106456
Short name T443
Test name
Test status
Simulation time 158440420097 ps
CPU time 70.43 seconds
Started Mar 26 02:32:57 PM PDT 24
Finished Mar 26 02:34:09 PM PDT 24
Peak memory 182644 kb
Host smart-3de92a3c-1996-4d11-b6ed-41bc4f234753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102106456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2102106456
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.740386527
Short name T166
Test name
Test status
Simulation time 159304915785 ps
CPU time 85.74 seconds
Started Mar 26 02:32:56 PM PDT 24
Finished Mar 26 02:34:24 PM PDT 24
Peak memory 190880 kb
Host smart-c5744c67-a8eb-40a8-a664-c0eb950c3a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740386527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.740386527
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.466379780
Short name T175
Test name
Test status
Simulation time 117563677042 ps
CPU time 111.06 seconds
Started Mar 26 02:32:59 PM PDT 24
Finished Mar 26 02:34:51 PM PDT 24
Peak memory 182672 kb
Host smart-3f9899de-910e-4410-bd23-a5276f7e5a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466379780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.466379780
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.4047803628
Short name T257
Test name
Test status
Simulation time 558340611106 ps
CPU time 616.39 seconds
Started Mar 26 02:32:58 PM PDT 24
Finished Mar 26 02:43:15 PM PDT 24
Peak memory 190820 kb
Host smart-a95d0f75-3e9d-458c-9214-74554021e99d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047803628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.4047803628
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.423449898
Short name T240
Test name
Test status
Simulation time 323228724611 ps
CPU time 184.26 seconds
Started Mar 26 02:32:58 PM PDT 24
Finished Mar 26 02:36:03 PM PDT 24
Peak memory 182612 kb
Host smart-44ce6ce0-9251-4d64-92c2-021d0ae99346
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423449898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.423449898
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1211083974
Short name T424
Test name
Test status
Simulation time 62494250950 ps
CPU time 94.65 seconds
Started Mar 26 02:32:59 PM PDT 24
Finished Mar 26 02:34:35 PM PDT 24
Peak memory 182668 kb
Host smart-526a2afd-56bd-4531-9ce4-be6849efbafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211083974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1211083974
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3311107985
Short name T295
Test name
Test status
Simulation time 206269797082 ps
CPU time 120.01 seconds
Started Mar 26 02:32:55 PM PDT 24
Finished Mar 26 02:34:56 PM PDT 24
Peak memory 190900 kb
Host smart-d3d92c71-713f-48ba-a99a-7b993e207dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311107985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3311107985
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2948313770
Short name T352
Test name
Test status
Simulation time 216174292773 ps
CPU time 134.79 seconds
Started Mar 26 02:32:58 PM PDT 24
Finished Mar 26 02:35:13 PM PDT 24
Peak memory 182588 kb
Host smart-677df387-0288-40b4-a5ea-62fc8d37a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948313770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2948313770
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.702833535
Short name T386
Test name
Test status
Simulation time 314827378112 ps
CPU time 134.95 seconds
Started Mar 26 02:32:56 PM PDT 24
Finished Mar 26 02:35:12 PM PDT 24
Peak memory 182696 kb
Host smart-c97f750a-1ce8-486e-afa0-df50071dca60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702833535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
702833535
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2612287485
Short name T360
Test name
Test status
Simulation time 8052009869 ps
CPU time 14.22 seconds
Started Mar 26 02:33:06 PM PDT 24
Finished Mar 26 02:33:22 PM PDT 24
Peak memory 182684 kb
Host smart-d13e5336-525a-4de6-a89c-865134b79501
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612287485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2612287485
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2872374010
Short name T392
Test name
Test status
Simulation time 441407931911 ps
CPU time 170.56 seconds
Started Mar 26 02:33:04 PM PDT 24
Finished Mar 26 02:35:55 PM PDT 24
Peak memory 182640 kb
Host smart-68c27f5a-0cb4-4e7a-9fc0-11b4dd5fb1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872374010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2872374010
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2429613741
Short name T296
Test name
Test status
Simulation time 44276255919 ps
CPU time 64.8 seconds
Started Mar 26 02:32:55 PM PDT 24
Finished Mar 26 02:34:01 PM PDT 24
Peak memory 182612 kb
Host smart-82caeb26-e385-47b5-8ba4-839d406d4488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429613741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2429613741
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2354028394
Short name T412
Test name
Test status
Simulation time 126333906 ps
CPU time 1.17 seconds
Started Mar 26 02:33:06 PM PDT 24
Finished Mar 26 02:33:09 PM PDT 24
Peak memory 182540 kb
Host smart-1ff9524a-1d6b-4a18-a5bc-acab71b84e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354028394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2354028394
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1347061573
Short name T314
Test name
Test status
Simulation time 320601426258 ps
CPU time 332.68 seconds
Started Mar 26 02:33:04 PM PDT 24
Finished Mar 26 02:38:37 PM PDT 24
Peak memory 182644 kb
Host smart-20b106ef-f840-4fc0-9e0d-96e6b743591a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347061573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1347061573
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.869031163
Short name T416
Test name
Test status
Simulation time 255345066207 ps
CPU time 166.6 seconds
Started Mar 26 02:33:04 PM PDT 24
Finished Mar 26 02:35:51 PM PDT 24
Peak memory 182696 kb
Host smart-f7785951-ba69-4493-b2c5-15da8d813ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869031163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.869031163
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1730468586
Short name T212
Test name
Test status
Simulation time 693903427450 ps
CPU time 466.15 seconds
Started Mar 26 02:33:09 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 190872 kb
Host smart-792b8b02-2419-4ed5-892b-fb344f87f6a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730468586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1730468586
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2329736223
Short name T378
Test name
Test status
Simulation time 116274953 ps
CPU time 0.61 seconds
Started Mar 26 02:33:09 PM PDT 24
Finished Mar 26 02:33:10 PM PDT 24
Peak memory 182332 kb
Host smart-7c1c573a-3376-43ed-bc7a-d48b58c5a53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329736223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2329736223
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1138905597
Short name T1
Test name
Test status
Simulation time 249067446990 ps
CPU time 189.33 seconds
Started Mar 26 02:33:05 PM PDT 24
Finished Mar 26 02:36:17 PM PDT 24
Peak memory 195228 kb
Host smart-bd101b5c-93ea-4edd-bb3b-5561fa32c785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138905597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1138905597
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4209115219
Short name T75
Test name
Test status
Simulation time 131258672690 ps
CPU time 173.28 seconds
Started Mar 26 02:32:16 PM PDT 24
Finished Mar 26 02:35:09 PM PDT 24
Peak memory 182640 kb
Host smart-525a3113-a98d-4a32-9089-3a4e64161bd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209115219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4209115219
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2801287302
Short name T377
Test name
Test status
Simulation time 114591800943 ps
CPU time 152.25 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 02:34:50 PM PDT 24
Peak memory 182676 kb
Host smart-bae38429-5932-4155-9553-f36604b6bdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801287302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2801287302
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1893229473
Short name T390
Test name
Test status
Simulation time 156643714974 ps
CPU time 69.43 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 02:33:26 PM PDT 24
Peak memory 182668 kb
Host smart-f58a9fbf-6f42-4615-8487-091d1c2e8940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893229473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1893229473
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2829691470
Short name T16
Test name
Test status
Simulation time 65421068 ps
CPU time 0.84 seconds
Started Mar 26 02:32:16 PM PDT 24
Finished Mar 26 02:32:17 PM PDT 24
Peak memory 213180 kb
Host smart-5b1f7f9e-eff6-4f46-a4a3-7fac4f6e90ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829691470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2829691470
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.599077192
Short name T35
Test name
Test status
Simulation time 102975959795 ps
CPU time 443.12 seconds
Started Mar 26 02:32:13 PM PDT 24
Finished Mar 26 02:39:36 PM PDT 24
Peak memory 205772 kb
Host smart-7419dff5-4548-4ea6-a7ca-c41508a314c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599077192 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.599077192
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.624385997
Short name T265
Test name
Test status
Simulation time 742088665388 ps
CPU time 1243.48 seconds
Started Mar 26 02:33:22 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 182720 kb
Host smart-1bb36913-6908-4dff-9e5f-a40af95e986f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624385997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.624385997
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1135054207
Short name T383
Test name
Test status
Simulation time 410268660559 ps
CPU time 196.09 seconds
Started Mar 26 02:33:21 PM PDT 24
Finished Mar 26 02:36:38 PM PDT 24
Peak memory 182644 kb
Host smart-d8d750e2-695d-4309-b576-8d5f508f8c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135054207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1135054207
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1869221344
Short name T199
Test name
Test status
Simulation time 669246288768 ps
CPU time 367.01 seconds
Started Mar 26 02:33:22 PM PDT 24
Finished Mar 26 02:39:30 PM PDT 24
Peak memory 190812 kb
Host smart-3f4923b8-bdd6-4618-a4d6-a857ec95ed2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869221344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1869221344
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3888780138
Short name T210
Test name
Test status
Simulation time 34438315591 ps
CPU time 68.26 seconds
Started Mar 26 02:33:22 PM PDT 24
Finished Mar 26 02:34:31 PM PDT 24
Peak memory 182672 kb
Host smart-ebee1c75-318a-4fdf-8445-c6c9006cc9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888780138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3888780138
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.400918816
Short name T221
Test name
Test status
Simulation time 247701965701 ps
CPU time 440.94 seconds
Started Mar 26 02:33:21 PM PDT 24
Finished Mar 26 02:40:44 PM PDT 24
Peak memory 190784 kb
Host smart-7f787eca-29e4-48d5-89bb-137ebbe00693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400918816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
400918816
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.649203446
Short name T410
Test name
Test status
Simulation time 429868605998 ps
CPU time 150.32 seconds
Started Mar 26 02:33:24 PM PDT 24
Finished Mar 26 02:35:55 PM PDT 24
Peak memory 182676 kb
Host smart-904028c1-7800-4da8-9643-2c3ce7b40db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649203446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.649203446
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.984813546
Short name T115
Test name
Test status
Simulation time 655852297767 ps
CPU time 1783.84 seconds
Started Mar 26 02:33:21 PM PDT 24
Finished Mar 26 03:03:07 PM PDT 24
Peak memory 194596 kb
Host smart-594963bd-6d64-4fcb-8bf2-f828981067a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984813546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.984813546
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.4107960586
Short name T20
Test name
Test status
Simulation time 925459470 ps
CPU time 1.3 seconds
Started Mar 26 02:33:33 PM PDT 24
Finished Mar 26 02:33:37 PM PDT 24
Peak memory 182480 kb
Host smart-711072c1-0b02-4d76-b614-005ea0514123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107960586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.4107960586
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3861935652
Short name T123
Test name
Test status
Simulation time 399943251398 ps
CPU time 219.68 seconds
Started Mar 26 02:33:33 PM PDT 24
Finished Mar 26 02:37:15 PM PDT 24
Peak memory 182660 kb
Host smart-a09801ad-8c10-4c23-bc4d-52b4712efa23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861935652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3861935652
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3733947497
Short name T387
Test name
Test status
Simulation time 180557886483 ps
CPU time 74.28 seconds
Started Mar 26 02:33:39 PM PDT 24
Finished Mar 26 02:34:53 PM PDT 24
Peak memory 182476 kb
Host smart-41dc3d89-f3a2-4d16-8567-036c6f5dd10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733947497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3733947497
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2482124625
Short name T304
Test name
Test status
Simulation time 9921952736 ps
CPU time 9.93 seconds
Started Mar 26 02:33:33 PM PDT 24
Finished Mar 26 02:33:45 PM PDT 24
Peak memory 182620 kb
Host smart-9afa7420-3f2a-4cff-a13c-657bdb502c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482124625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2482124625
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1923055862
Short name T458
Test name
Test status
Simulation time 331237417 ps
CPU time 0.98 seconds
Started Mar 26 02:33:32 PM PDT 24
Finished Mar 26 02:33:36 PM PDT 24
Peak memory 182404 kb
Host smart-0d12a466-ca5d-42d4-869f-e25253538da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923055862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1923055862
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2260842894
Short name T36
Test name
Test status
Simulation time 254211660550 ps
CPU time 821.64 seconds
Started Mar 26 02:33:32 PM PDT 24
Finished Mar 26 02:47:17 PM PDT 24
Peak memory 209844 kb
Host smart-5261c9bf-a7ea-4c4a-a4a2-4e89716f6534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260842894 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2260842894
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1972442550
Short name T169
Test name
Test status
Simulation time 12837420683 ps
CPU time 13.67 seconds
Started Mar 26 02:33:39 PM PDT 24
Finished Mar 26 02:33:53 PM PDT 24
Peak memory 182680 kb
Host smart-1ebcc87c-3263-4d76-a942-c925472c3b89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972442550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1972442550
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1974828221
Short name T368
Test name
Test status
Simulation time 345552598512 ps
CPU time 147.13 seconds
Started Mar 26 02:33:39 PM PDT 24
Finished Mar 26 02:36:06 PM PDT 24
Peak memory 182540 kb
Host smart-332f04c2-8540-41b6-a885-8fb5cd88ec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974828221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1974828221
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2444569839
Short name T309
Test name
Test status
Simulation time 39674002295 ps
CPU time 64.05 seconds
Started Mar 26 02:33:32 PM PDT 24
Finished Mar 26 02:34:39 PM PDT 24
Peak memory 190880 kb
Host smart-7386be38-dacc-4fc5-930b-5797d98d269a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444569839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2444569839
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2068150975
Short name T457
Test name
Test status
Simulation time 223778666 ps
CPU time 0.67 seconds
Started Mar 26 02:33:44 PM PDT 24
Finished Mar 26 02:33:45 PM PDT 24
Peak memory 182428 kb
Host smart-8c6b791b-4c6b-42da-8669-f2e8a59f6d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068150975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2068150975
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3524483348
Short name T244
Test name
Test status
Simulation time 508811331382 ps
CPU time 374.74 seconds
Started Mar 26 02:33:45 PM PDT 24
Finished Mar 26 02:40:00 PM PDT 24
Peak memory 182660 kb
Host smart-ed70f3f0-b9b7-4d19-abbe-a731089f583f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524483348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3524483348
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3952651272
Short name T4
Test name
Test status
Simulation time 528659386200 ps
CPU time 218.7 seconds
Started Mar 26 02:33:44 PM PDT 24
Finished Mar 26 02:37:23 PM PDT 24
Peak memory 182688 kb
Host smart-1c7e05f7-3ea0-4e92-8999-b84379e0cc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952651272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3952651272
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2942646501
Short name T363
Test name
Test status
Simulation time 74086331188 ps
CPU time 265.36 seconds
Started Mar 26 02:33:44 PM PDT 24
Finished Mar 26 02:38:09 PM PDT 24
Peak memory 190892 kb
Host smart-1213ec8f-12ce-4d3e-b5f5-371e90b59a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942646501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2942646501
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1807656259
Short name T318
Test name
Test status
Simulation time 28793779169 ps
CPU time 39.5 seconds
Started Mar 26 02:33:44 PM PDT 24
Finished Mar 26 02:34:23 PM PDT 24
Peak memory 182452 kb
Host smart-80855946-4ccc-4ab8-a650-489ea0ffcd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807656259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1807656259
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2627838790
Short name T340
Test name
Test status
Simulation time 602383866726 ps
CPU time 199.88 seconds
Started Mar 26 02:33:43 PM PDT 24
Finished Mar 26 02:37:03 PM PDT 24
Peak memory 182728 kb
Host smart-0ab73fff-ae29-4450-a16e-8f832cc4bb3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627838790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2627838790
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.4160235377
Short name T444
Test name
Test status
Simulation time 75719876174 ps
CPU time 113.44 seconds
Started Mar 26 02:33:45 PM PDT 24
Finished Mar 26 02:35:38 PM PDT 24
Peak memory 182684 kb
Host smart-a6b706b1-3baa-4340-b1c8-35c5d394bae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160235377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4160235377
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.4144072812
Short name T129
Test name
Test status
Simulation time 1669588214872 ps
CPU time 452.44 seconds
Started Mar 26 02:33:45 PM PDT 24
Finished Mar 26 02:41:17 PM PDT 24
Peak memory 190864 kb
Host smart-100dd554-3f19-4aab-8499-dc80fa08faac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144072812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4144072812
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3711002936
Short name T400
Test name
Test status
Simulation time 164099596580 ps
CPU time 65.92 seconds
Started Mar 26 02:33:55 PM PDT 24
Finished Mar 26 02:35:02 PM PDT 24
Peak memory 182680 kb
Host smart-7213c4ee-e5e9-4a7b-a611-33d72791283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711002936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3711002936
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.803552331
Short name T389
Test name
Test status
Simulation time 192847843041 ps
CPU time 307.52 seconds
Started Mar 26 02:33:56 PM PDT 24
Finished Mar 26 02:39:04 PM PDT 24
Peak memory 182708 kb
Host smart-0fc71b6e-4d54-40e0-8070-cff0f5ebba49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803552331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
803552331
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1938146417
Short name T303
Test name
Test status
Simulation time 103903086248 ps
CPU time 166.11 seconds
Started Mar 26 02:33:56 PM PDT 24
Finished Mar 26 02:36:42 PM PDT 24
Peak memory 182700 kb
Host smart-9e4504df-2ab5-42ae-ad00-ab1bbc44a4c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938146417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1938146417
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1230101759
Short name T41
Test name
Test status
Simulation time 261723137478 ps
CPU time 102.16 seconds
Started Mar 26 02:33:55 PM PDT 24
Finished Mar 26 02:35:37 PM PDT 24
Peak memory 182628 kb
Host smart-9c2eb4ca-3d8e-47ca-bf5c-ad658016b4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230101759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1230101759
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2297078341
Short name T140
Test name
Test status
Simulation time 93973802297 ps
CPU time 276.3 seconds
Started Mar 26 02:33:55 PM PDT 24
Finished Mar 26 02:38:31 PM PDT 24
Peak memory 190904 kb
Host smart-9aa8bf51-fb5c-4aad-8af2-92e9fee22221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297078341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2297078341
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.618303460
Short name T375
Test name
Test status
Simulation time 37768929 ps
CPU time 1.37 seconds
Started Mar 26 02:33:56 PM PDT 24
Finished Mar 26 02:33:58 PM PDT 24
Peak memory 182596 kb
Host smart-366751c5-5109-4a56-9e68-c4a89a00e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618303460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.618303460
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2177710288
Short name T33
Test name
Test status
Simulation time 86050971856 ps
CPU time 1069.01 seconds
Started Mar 26 02:33:57 PM PDT 24
Finished Mar 26 02:51:46 PM PDT 24
Peak memory 205564 kb
Host smart-7d207dfb-b248-4edf-a928-a2953f9cb2a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177710288 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2177710288
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.617169545
Short name T396
Test name
Test status
Simulation time 246433240079 ps
CPU time 456.08 seconds
Started Mar 26 02:33:59 PM PDT 24
Finished Mar 26 02:41:36 PM PDT 24
Peak memory 182688 kb
Host smart-65e57ec4-96ac-422a-86ba-6980407e3819
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617169545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.617169545
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3867580930
Short name T402
Test name
Test status
Simulation time 63213006783 ps
CPU time 80.96 seconds
Started Mar 26 02:33:54 PM PDT 24
Finished Mar 26 02:35:15 PM PDT 24
Peak memory 182688 kb
Host smart-c194ffbe-103a-43bb-95ed-70c8e19627a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867580930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3867580930
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2106422613
Short name T283
Test name
Test status
Simulation time 26011780107 ps
CPU time 217.49 seconds
Started Mar 26 02:33:55 PM PDT 24
Finished Mar 26 02:37:33 PM PDT 24
Peak memory 194980 kb
Host smart-f2234eea-3bf3-486a-a840-f7c814d83e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106422613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2106422613
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3525561006
Short name T73
Test name
Test status
Simulation time 70510102961 ps
CPU time 129.73 seconds
Started Mar 26 02:33:54 PM PDT 24
Finished Mar 26 02:36:04 PM PDT 24
Peak memory 182712 kb
Host smart-13cec65c-b8a3-470b-a83c-458ef5967cc9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525561006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3525561006
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1129218661
Short name T407
Test name
Test status
Simulation time 109626365563 ps
CPU time 163.18 seconds
Started Mar 26 02:33:55 PM PDT 24
Finished Mar 26 02:36:38 PM PDT 24
Peak memory 182584 kb
Host smart-bff45988-f50d-4420-9c2e-76918392699d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129218661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1129218661
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3908312189
Short name T211
Test name
Test status
Simulation time 137590470698 ps
CPU time 523.92 seconds
Started Mar 26 02:33:55 PM PDT 24
Finished Mar 26 02:42:39 PM PDT 24
Peak memory 192192 kb
Host smart-afc09097-db52-4d3d-8b77-331ca96fe6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908312189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3908312189
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3301916240
Short name T321
Test name
Test status
Simulation time 50107842819 ps
CPU time 88.15 seconds
Started Mar 26 02:34:06 PM PDT 24
Finished Mar 26 02:35:34 PM PDT 24
Peak memory 190848 kb
Host smart-dc1470ad-839d-45e4-add1-79279506edc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301916240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3301916240
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3808957324
Short name T189
Test name
Test status
Simulation time 1009804742986 ps
CPU time 559.03 seconds
Started Mar 26 02:34:08 PM PDT 24
Finished Mar 26 02:43:27 PM PDT 24
Peak memory 182632 kb
Host smart-2d403637-4de1-486b-bf5e-ad542350d981
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808957324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3808957324
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3333096906
Short name T74
Test name
Test status
Simulation time 211365923692 ps
CPU time 81.28 seconds
Started Mar 26 02:34:07 PM PDT 24
Finished Mar 26 02:35:29 PM PDT 24
Peak memory 182596 kb
Host smart-dfc22f3e-81a6-4cae-86a7-238a81af6856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333096906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3333096906
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2314744531
Short name T267
Test name
Test status
Simulation time 254634346393 ps
CPU time 144.71 seconds
Started Mar 26 02:34:07 PM PDT 24
Finished Mar 26 02:36:32 PM PDT 24
Peak memory 190864 kb
Host smart-73ef56dc-9952-4645-b1e2-50bbc3dd6986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314744531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2314744531
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2931666807
Short name T193
Test name
Test status
Simulation time 48600782356 ps
CPU time 87.54 seconds
Started Mar 26 02:34:06 PM PDT 24
Finished Mar 26 02:35:34 PM PDT 24
Peak memory 182684 kb
Host smart-5a6311cb-71b9-4ae7-b5e6-49a0b3d9b21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931666807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2931666807
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.802286658
Short name T13
Test name
Test status
Simulation time 50808672945 ps
CPU time 117.44 seconds
Started Mar 26 02:34:07 PM PDT 24
Finished Mar 26 02:36:04 PM PDT 24
Peak memory 197276 kb
Host smart-ec9b9023-1675-429a-b4cb-d68600cb73c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802286658 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.802286658
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2942262853
Short name T353
Test name
Test status
Simulation time 32893830847 ps
CPU time 7.76 seconds
Started Mar 26 02:32:14 PM PDT 24
Finished Mar 26 02:32:22 PM PDT 24
Peak memory 182688 kb
Host smart-5c6f81c4-d015-42e0-9e4d-df637caf22c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942262853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2942262853
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1781452905
Short name T455
Test name
Test status
Simulation time 80337185338 ps
CPU time 109.48 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 02:34:07 PM PDT 24
Peak memory 182676 kb
Host smart-dea20a8d-680d-4e60-b931-6d9aeb82be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781452905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1781452905
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.4241815492
Short name T246
Test name
Test status
Simulation time 117204510710 ps
CPU time 843.4 seconds
Started Mar 26 02:32:17 PM PDT 24
Finished Mar 26 02:46:21 PM PDT 24
Peak memory 190868 kb
Host smart-8c7c31d7-b4fc-462b-b1b1-2cb920e02ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241815492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.4241815492
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.909967951
Short name T385
Test name
Test status
Simulation time 635668711 ps
CPU time 0.77 seconds
Started Mar 26 02:32:29 PM PDT 24
Finished Mar 26 02:32:29 PM PDT 24
Peak memory 191040 kb
Host smart-1b752f62-427c-4982-a3ec-ae80a39b36e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909967951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.909967951
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2198452573
Short name T17
Test name
Test status
Simulation time 39484944 ps
CPU time 0.72 seconds
Started Mar 26 02:32:28 PM PDT 24
Finished Mar 26 02:32:29 PM PDT 24
Peak memory 213008 kb
Host smart-18db004e-e492-44bd-9e00-2fd40790046c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198452573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2198452573
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1030127220
Short name T370
Test name
Test status
Simulation time 1797569460460 ps
CPU time 281.46 seconds
Started Mar 26 02:32:15 PM PDT 24
Finished Mar 26 02:36:57 PM PDT 24
Peak memory 190772 kb
Host smart-06d4f24d-2aca-4022-8c62-80c73bb3c245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030127220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1030127220
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1085054140
Short name T262
Test name
Test status
Simulation time 33966632836 ps
CPU time 34.51 seconds
Started Mar 26 02:34:17 PM PDT 24
Finished Mar 26 02:34:51 PM PDT 24
Peak memory 182700 kb
Host smart-67fae0b2-edbc-429a-88e0-7688c32869f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085054140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1085054140
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3830901291
Short name T369
Test name
Test status
Simulation time 578545680567 ps
CPU time 197.42 seconds
Started Mar 26 02:34:07 PM PDT 24
Finished Mar 26 02:37:25 PM PDT 24
Peak memory 182628 kb
Host smart-c21881fc-5a5e-4c83-b634-546bd37d55da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830901291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3830901291
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2280605536
Short name T130
Test name
Test status
Simulation time 199168639924 ps
CPU time 331.24 seconds
Started Mar 26 02:34:08 PM PDT 24
Finished Mar 26 02:39:39 PM PDT 24
Peak memory 190808 kb
Host smart-e5c10dad-69da-4d04-9f94-b0d465df2d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280605536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2280605536
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3315144031
Short name T8
Test name
Test status
Simulation time 205382267907 ps
CPU time 116.77 seconds
Started Mar 26 02:34:20 PM PDT 24
Finished Mar 26 02:36:17 PM PDT 24
Peak memory 190816 kb
Host smart-5ef67d91-4d6e-45b7-9be9-4160b3c03fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315144031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3315144031
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2667537996
Short name T419
Test name
Test status
Simulation time 104549243 ps
CPU time 0.55 seconds
Started Mar 26 02:34:17 PM PDT 24
Finished Mar 26 02:34:17 PM PDT 24
Peak memory 182408 kb
Host smart-e6f6f671-20c7-4b59-bc02-cd6b6e73b6e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667537996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2667537996
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.410912494
Short name T37
Test name
Test status
Simulation time 117489405260 ps
CPU time 135.22 seconds
Started Mar 26 02:34:18 PM PDT 24
Finished Mar 26 02:36:33 PM PDT 24
Peak memory 197296 kb
Host smart-119e0e1c-2796-459a-830c-e50a345b61dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410912494 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.410912494
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1900088185
Short name T401
Test name
Test status
Simulation time 82011371122 ps
CPU time 126.1 seconds
Started Mar 26 02:34:18 PM PDT 24
Finished Mar 26 02:36:25 PM PDT 24
Peak memory 182684 kb
Host smart-75d2f499-b2dc-475e-a50c-1d192aadc7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900088185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1900088185
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.624933134
Short name T176
Test name
Test status
Simulation time 104912664611 ps
CPU time 432.68 seconds
Started Mar 26 02:34:17 PM PDT 24
Finished Mar 26 02:41:30 PM PDT 24
Peak memory 190888 kb
Host smart-fda37d2a-b4b6-4d82-9631-e2953850556f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624933134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.624933134
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1027025516
Short name T418
Test name
Test status
Simulation time 441807382 ps
CPU time 2.08 seconds
Started Mar 26 02:34:18 PM PDT 24
Finished Mar 26 02:34:20 PM PDT 24
Peak memory 190784 kb
Host smart-5ebbdd9f-bb9d-4a2a-894c-463d1d620572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027025516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1027025516
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.193424694
Short name T148
Test name
Test status
Simulation time 41579106472 ps
CPU time 82.05 seconds
Started Mar 26 02:34:17 PM PDT 24
Finished Mar 26 02:35:39 PM PDT 24
Peak memory 182708 kb
Host smart-cf093c44-60b1-48e2-adbf-9cd0041b8b53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193424694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.193424694
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3136877449
Short name T373
Test name
Test status
Simulation time 33709476060 ps
CPU time 51.77 seconds
Started Mar 26 02:34:19 PM PDT 24
Finished Mar 26 02:35:11 PM PDT 24
Peak memory 182656 kb
Host smart-3609a082-fb02-46e9-8c9b-ff7f3f27207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136877449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3136877449
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1701092704
Short name T302
Test name
Test status
Simulation time 152252743700 ps
CPU time 145.64 seconds
Started Mar 26 02:34:19 PM PDT 24
Finished Mar 26 02:36:45 PM PDT 24
Peak memory 190856 kb
Host smart-94ed13c3-90e9-4d36-9765-2ca7ada66973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701092704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1701092704
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.941881881
Short name T408
Test name
Test status
Simulation time 445335682 ps
CPU time 1.19 seconds
Started Mar 26 02:34:20 PM PDT 24
Finished Mar 26 02:34:21 PM PDT 24
Peak memory 182560 kb
Host smart-2bf6b4c3-07d7-412a-a0c3-baa0bbba1404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941881881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.941881881
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2927556057
Short name T237
Test name
Test status
Simulation time 18230495583 ps
CPU time 152.96 seconds
Started Mar 26 02:34:18 PM PDT 24
Finished Mar 26 02:36:51 PM PDT 24
Peak memory 197328 kb
Host smart-b277cf7b-1137-42a6-b390-886e70871282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927556057 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2927556057
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2627510289
Short name T425
Test name
Test status
Simulation time 1071309778 ps
CPU time 2.48 seconds
Started Mar 26 02:34:30 PM PDT 24
Finished Mar 26 02:34:34 PM PDT 24
Peak memory 182508 kb
Host smart-8288c8a3-8f3b-47b8-82d7-1a04e73c915d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627510289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2627510289
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.4145959648
Short name T287
Test name
Test status
Simulation time 204399024250 ps
CPU time 1772.94 seconds
Started Mar 26 02:34:17 PM PDT 24
Finished Mar 26 03:03:51 PM PDT 24
Peak memory 190832 kb
Host smart-c19cf151-7002-493b-81ad-85371b3d7bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145959648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4145959648
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3113896512
Short name T339
Test name
Test status
Simulation time 10667790407 ps
CPU time 20.8 seconds
Started Mar 26 02:34:28 PM PDT 24
Finished Mar 26 02:34:49 PM PDT 24
Peak memory 190860 kb
Host smart-c421ae75-da81-4cfc-a66d-7ffcb543ebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113896512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3113896512
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2213914315
Short name T2
Test name
Test status
Simulation time 1166457470784 ps
CPU time 1249.43 seconds
Started Mar 26 02:34:30 PM PDT 24
Finished Mar 26 02:55:21 PM PDT 24
Peak memory 190884 kb
Host smart-bd07b461-0e43-464c-9e98-42ea07445d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213914315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2213914315
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.508788324
Short name T135
Test name
Test status
Simulation time 1051986486890 ps
CPU time 265.93 seconds
Started Mar 26 02:34:29 PM PDT 24
Finished Mar 26 02:38:57 PM PDT 24
Peak memory 182584 kb
Host smart-826cc7f2-4f0d-448f-8134-a210b5269992
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508788324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.508788324
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1657318415
Short name T427
Test name
Test status
Simulation time 156031359995 ps
CPU time 237.4 seconds
Started Mar 26 02:34:29 PM PDT 24
Finished Mar 26 02:38:28 PM PDT 24
Peak memory 182632 kb
Host smart-faa741f9-2a8f-4801-ad1b-4358ae140ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657318415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1657318415
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1158928734
Short name T40
Test name
Test status
Simulation time 30820025313 ps
CPU time 16 seconds
Started Mar 26 02:34:30 PM PDT 24
Finished Mar 26 02:34:47 PM PDT 24
Peak memory 193344 kb
Host smart-7faa2ed7-ffe9-4e15-ae78-406bf9352e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158928734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1158928734
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1480901104
Short name T64
Test name
Test status
Simulation time 429931374598 ps
CPU time 814.32 seconds
Started Mar 26 02:34:39 PM PDT 24
Finished Mar 26 02:48:14 PM PDT 24
Peak memory 190872 kb
Host smart-e57e1bd0-4b4e-42f1-9cd1-65438b6846de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480901104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1480901104
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1201474327
Short name T349
Test name
Test status
Simulation time 142545524354 ps
CPU time 240.09 seconds
Started Mar 26 02:34:40 PM PDT 24
Finished Mar 26 02:38:42 PM PDT 24
Peak memory 182580 kb
Host smart-4dc080d2-805b-44f9-bc04-5f17b8f454a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201474327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1201474327
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2958485828
Short name T51
Test name
Test status
Simulation time 278582131619 ps
CPU time 122.23 seconds
Started Mar 26 02:34:41 PM PDT 24
Finished Mar 26 02:36:44 PM PDT 24
Peak memory 182664 kb
Host smart-90924306-8924-43fc-8b0c-775f5e550d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958485828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2958485828
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3100834741
Short name T52
Test name
Test status
Simulation time 189576289590 ps
CPU time 92.58 seconds
Started Mar 26 02:34:41 PM PDT 24
Finished Mar 26 02:36:14 PM PDT 24
Peak memory 190880 kb
Host smart-39a27918-b23e-4b36-a546-7f526d6c0e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100834741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3100834741
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2112913453
Short name T348
Test name
Test status
Simulation time 245923771616 ps
CPU time 411.57 seconds
Started Mar 26 02:34:41 PM PDT 24
Finished Mar 26 02:41:33 PM PDT 24
Peak memory 182640 kb
Host smart-17021adb-7233-4642-824a-590800223fd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112913453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2112913453
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3406571714
Short name T70
Test name
Test status
Simulation time 111793912484 ps
CPU time 163.36 seconds
Started Mar 26 02:34:41 PM PDT 24
Finished Mar 26 02:37:25 PM PDT 24
Peak memory 182676 kb
Host smart-cced6367-5306-4710-99e4-86d288c0c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406571714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3406571714
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3741127534
Short name T280
Test name
Test status
Simulation time 141763721388 ps
CPU time 1280.95 seconds
Started Mar 26 02:34:39 PM PDT 24
Finished Mar 26 02:56:01 PM PDT 24
Peak memory 182640 kb
Host smart-d9525290-ac7a-4a4f-b516-41c21b42e94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741127534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3741127534
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2025987442
Short name T345
Test name
Test status
Simulation time 143643636 ps
CPU time 0.82 seconds
Started Mar 26 02:34:39 PM PDT 24
Finished Mar 26 02:34:42 PM PDT 24
Peak memory 191096 kb
Host smart-dbc3c0c0-d73e-4199-89c4-03f4f339e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025987442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2025987442
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3886653769
Short name T200
Test name
Test status
Simulation time 2034607556099 ps
CPU time 2524.15 seconds
Started Mar 26 02:34:40 PM PDT 24
Finished Mar 26 03:16:46 PM PDT 24
Peak memory 195628 kb
Host smart-ba004dce-6c94-4d59-8853-a4e28005bcbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886653769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3886653769
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.169231191
Short name T299
Test name
Test status
Simulation time 633391474582 ps
CPU time 578.86 seconds
Started Mar 26 02:34:40 PM PDT 24
Finished Mar 26 02:44:21 PM PDT 24
Peak memory 182632 kb
Host smart-6bdb99a5-30a9-402d-b6c8-4768f26f9380
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169231191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.169231191
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3206119093
Short name T384
Test name
Test status
Simulation time 424856214242 ps
CPU time 99.25 seconds
Started Mar 26 02:34:41 PM PDT 24
Finished Mar 26 02:36:21 PM PDT 24
Peak memory 182684 kb
Host smart-c530a7cc-e06f-4495-80bb-12d07e2ea114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206119093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3206119093
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3896290169
Short name T161
Test name
Test status
Simulation time 378655264621 ps
CPU time 1325.21 seconds
Started Mar 26 02:34:41 PM PDT 24
Finished Mar 26 02:56:47 PM PDT 24
Peak memory 190812 kb
Host smart-4e8a15bb-2770-43ca-81a9-96a7ca6b5869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896290169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3896290169
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.4046086449
Short name T180
Test name
Test status
Simulation time 35625432505 ps
CPU time 653.88 seconds
Started Mar 26 02:34:40 PM PDT 24
Finished Mar 26 02:45:36 PM PDT 24
Peak memory 182624 kb
Host smart-b4c52f15-1f92-4b68-95d6-dfcbfaaf947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046086449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.4046086449
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1130046457
Short name T59
Test name
Test status
Simulation time 63116289327 ps
CPU time 29.61 seconds
Started Mar 26 02:34:52 PM PDT 24
Finished Mar 26 02:35:22 PM PDT 24
Peak memory 182660 kb
Host smart-da485d23-a017-4300-91ea-032eec03a490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130046457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1130046457
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3714974390
Short name T292
Test name
Test status
Simulation time 8929095547 ps
CPU time 15.25 seconds
Started Mar 26 02:34:50 PM PDT 24
Finished Mar 26 02:35:06 PM PDT 24
Peak memory 182660 kb
Host smart-9e3b2477-29a9-4ece-b43c-d721c9edf194
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714974390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3714974390
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4078346728
Short name T381
Test name
Test status
Simulation time 323162246027 ps
CPU time 140.1 seconds
Started Mar 26 02:34:52 PM PDT 24
Finished Mar 26 02:37:12 PM PDT 24
Peak memory 182640 kb
Host smart-3d60650a-29c7-464d-a47a-a7d541fec878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078346728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4078346728
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3016860446
Short name T310
Test name
Test status
Simulation time 78892365826 ps
CPU time 93.88 seconds
Started Mar 26 02:34:54 PM PDT 24
Finished Mar 26 02:36:28 PM PDT 24
Peak memory 190824 kb
Host smart-72f307e8-8197-478c-b132-d5b534ec23e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016860446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3016860446
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.79489909
Short name T367
Test name
Test status
Simulation time 31113755 ps
CPU time 0.58 seconds
Started Mar 26 02:34:51 PM PDT 24
Finished Mar 26 02:34:51 PM PDT 24
Peak memory 182436 kb
Host smart-450cf22f-e0e1-4410-9747-098cf4b1d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79489909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.79489909
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2901861546
Short name T288
Test name
Test status
Simulation time 854958652849 ps
CPU time 507.81 seconds
Started Mar 26 02:34:51 PM PDT 24
Finished Mar 26 02:43:19 PM PDT 24
Peak memory 182644 kb
Host smart-bab0ac8c-b699-47a8-bbc7-9a43b9374b57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901861546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2901861546
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.46689094
Short name T428
Test name
Test status
Simulation time 157541373165 ps
CPU time 224.79 seconds
Started Mar 26 02:34:52 PM PDT 24
Finished Mar 26 02:38:37 PM PDT 24
Peak memory 182648 kb
Host smart-829bf8bb-21b9-47fb-9557-b6addeb17d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46689094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.46689094
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3885256305
Short name T226
Test name
Test status
Simulation time 233701947844 ps
CPU time 449.11 seconds
Started Mar 26 02:34:53 PM PDT 24
Finished Mar 26 02:42:22 PM PDT 24
Peak memory 191064 kb
Host smart-2ad6b5f9-bdc4-4e0c-a536-fe2a48a7c3fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885256305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3885256305
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3890202891
Short name T388
Test name
Test status
Simulation time 140764447611 ps
CPU time 98.37 seconds
Started Mar 26 02:34:51 PM PDT 24
Finished Mar 26 02:36:30 PM PDT 24
Peak memory 194412 kb
Host smart-2efac7e1-ee14-4ff7-8af3-fe502e871ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890202891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3890202891
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3390503494
Short name T380
Test name
Test status
Simulation time 237691123307 ps
CPU time 197.32 seconds
Started Mar 26 02:34:50 PM PDT 24
Finished Mar 26 02:38:08 PM PDT 24
Peak memory 190824 kb
Host smart-6a619830-3e95-4740-ba47-c449acec51fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390503494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3390503494
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1450778925
Short name T12
Test name
Test status
Simulation time 20355118170 ps
CPU time 207.25 seconds
Started Mar 26 02:34:51 PM PDT 24
Finished Mar 26 02:38:19 PM PDT 24
Peak memory 197296 kb
Host smart-1a0d396a-f088-4519-871d-59ee2726664e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450778925 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1450778925
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3734093587
Short name T228
Test name
Test status
Simulation time 159478138252 ps
CPU time 282.09 seconds
Started Mar 26 02:32:28 PM PDT 24
Finished Mar 26 02:37:11 PM PDT 24
Peak memory 182580 kb
Host smart-fcf7092e-90a5-4b43-8269-57f619d97f38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734093587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3734093587
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.131908561
Short name T372
Test name
Test status
Simulation time 488870199720 ps
CPU time 187.16 seconds
Started Mar 26 02:32:27 PM PDT 24
Finished Mar 26 02:35:34 PM PDT 24
Peak memory 182604 kb
Host smart-a4afe17e-c4b0-4f25-964e-c04c4d9cec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131908561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.131908561
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.746442916
Short name T56
Test name
Test status
Simulation time 42920571800 ps
CPU time 82.29 seconds
Started Mar 26 02:32:27 PM PDT 24
Finished Mar 26 02:33:49 PM PDT 24
Peak memory 190876 kb
Host smart-d32d418a-3df8-40d3-9cdc-e0841f719330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746442916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.746442916
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.169854982
Short name T323
Test name
Test status
Simulation time 84179677125 ps
CPU time 170.43 seconds
Started Mar 26 02:32:24 PM PDT 24
Finished Mar 26 02:35:15 PM PDT 24
Peak memory 194092 kb
Host smart-e554eaab-ef09-48e0-9aa6-949a9826f0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169854982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.169854982
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1437682832
Short name T355
Test name
Test status
Simulation time 243194869921 ps
CPU time 649.93 seconds
Started Mar 26 02:32:25 PM PDT 24
Finished Mar 26 02:43:15 PM PDT 24
Peak memory 190856 kb
Host smart-f3d0841c-3dd0-4ba9-9019-beb5fc9d0933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437682832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1437682832
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1198343104
Short name T42
Test name
Test status
Simulation time 71646237381 ps
CPU time 283.81 seconds
Started Mar 26 02:32:24 PM PDT 24
Finished Mar 26 02:37:08 PM PDT 24
Peak memory 197284 kb
Host smart-62a43108-5d68-4ec5-92b0-8c1eec4cbd8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198343104 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1198343104
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3885707219
Short name T317
Test name
Test status
Simulation time 2946166502993 ps
CPU time 806.34 seconds
Started Mar 26 02:34:50 PM PDT 24
Finished Mar 26 02:48:17 PM PDT 24
Peak memory 190884 kb
Host smart-ebbba7fe-bf59-49ae-901a-7c292b8ed968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885707219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3885707219
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3451158815
Short name T281
Test name
Test status
Simulation time 558845851624 ps
CPU time 279.41 seconds
Started Mar 26 02:34:51 PM PDT 24
Finished Mar 26 02:39:31 PM PDT 24
Peak memory 190868 kb
Host smart-67b6b0b0-26b9-4bd4-8672-5a46594e578a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451158815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3451158815
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.985668549
Short name T395
Test name
Test status
Simulation time 13658260599 ps
CPU time 19.49 seconds
Started Mar 26 02:34:54 PM PDT 24
Finished Mar 26 02:35:13 PM PDT 24
Peak memory 182616 kb
Host smart-91a4eaf3-f0c8-484f-a1cc-fe04528a8b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985668549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.985668549
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3598338442
Short name T430
Test name
Test status
Simulation time 83860215744 ps
CPU time 45.6 seconds
Started Mar 26 02:34:53 PM PDT 24
Finished Mar 26 02:35:39 PM PDT 24
Peak memory 182624 kb
Host smart-2fc326e3-76ed-49f0-9b12-148d0c0e2ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598338442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3598338442
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2903066657
Short name T364
Test name
Test status
Simulation time 644150049231 ps
CPU time 410.33 seconds
Started Mar 26 02:34:52 PM PDT 24
Finished Mar 26 02:41:42 PM PDT 24
Peak memory 190816 kb
Host smart-86d0c467-6fa6-408f-bbbd-71990a6902b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903066657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2903066657
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.446211477
Short name T198
Test name
Test status
Simulation time 913418569229 ps
CPU time 258.38 seconds
Started Mar 26 02:34:50 PM PDT 24
Finished Mar 26 02:39:09 PM PDT 24
Peak memory 190880 kb
Host smart-30c17d36-a90d-4760-a9c9-a79129d60d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446211477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.446211477
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.658245536
Short name T275
Test name
Test status
Simulation time 319670224413 ps
CPU time 259.94 seconds
Started Mar 26 02:34:51 PM PDT 24
Finished Mar 26 02:39:11 PM PDT 24
Peak memory 190848 kb
Host smart-f4b13180-f79c-4e6e-961b-c747d66ab08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658245536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.658245536
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.507281413
Short name T208
Test name
Test status
Simulation time 219816179102 ps
CPU time 896.17 seconds
Started Mar 26 02:35:00 PM PDT 24
Finished Mar 26 02:49:56 PM PDT 24
Peak memory 190872 kb
Host smart-5aa2c504-871c-4b87-9b0e-7c89047553ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507281413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.507281413
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.259443890
Short name T245
Test name
Test status
Simulation time 114185681381 ps
CPU time 1937.3 seconds
Started Mar 26 02:35:04 PM PDT 24
Finished Mar 26 03:07:22 PM PDT 24
Peak memory 190888 kb
Host smart-a926d216-1c92-4f14-b9e7-4be526844fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259443890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.259443890
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2081821324
Short name T393
Test name
Test status
Simulation time 20526806569 ps
CPU time 20.8 seconds
Started Mar 26 02:32:25 PM PDT 24
Finished Mar 26 02:32:46 PM PDT 24
Peak memory 182644 kb
Host smart-10627def-725d-4962-a5f7-81a7c1dc45f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081821324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2081821324
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3214997529
Short name T431
Test name
Test status
Simulation time 171662794114 ps
CPU time 64.69 seconds
Started Mar 26 02:32:24 PM PDT 24
Finished Mar 26 02:33:28 PM PDT 24
Peak memory 182656 kb
Host smart-7103d78f-6e93-4e2f-9194-e61f9b9e8ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214997529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3214997529
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1072731346
Short name T454
Test name
Test status
Simulation time 37338300955 ps
CPU time 58.77 seconds
Started Mar 26 02:32:27 PM PDT 24
Finished Mar 26 02:33:26 PM PDT 24
Peak memory 190812 kb
Host smart-8ec81a4e-951f-4075-8c3a-92374038e0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072731346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1072731346
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.324101686
Short name T434
Test name
Test status
Simulation time 7841250066 ps
CPU time 62.86 seconds
Started Mar 26 02:32:28 PM PDT 24
Finished Mar 26 02:33:31 PM PDT 24
Peak memory 192836 kb
Host smart-410e3613-1e2e-4302-a7cd-e40bfa319943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324101686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.324101686
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.60913474
Short name T173
Test name
Test status
Simulation time 298078400595 ps
CPU time 205.63 seconds
Started Mar 26 02:34:59 PM PDT 24
Finished Mar 26 02:38:25 PM PDT 24
Peak memory 194364 kb
Host smart-4362eb2a-56ff-4534-85b2-a1631ff94d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60913474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.60913474
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1888462000
Short name T158
Test name
Test status
Simulation time 83767865890 ps
CPU time 60.1 seconds
Started Mar 26 02:34:59 PM PDT 24
Finished Mar 26 02:35:59 PM PDT 24
Peak memory 182660 kb
Host smart-07e2d3cd-caa6-4451-8161-4758080fe218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888462000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1888462000
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3581495246
Short name T163
Test name
Test status
Simulation time 622574156510 ps
CPU time 314.06 seconds
Started Mar 26 02:35:07 PM PDT 24
Finished Mar 26 02:40:22 PM PDT 24
Peak memory 190896 kb
Host smart-e04d6e7c-42cc-49b9-996a-73c23f0f82cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581495246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3581495246
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1832977856
Short name T254
Test name
Test status
Simulation time 111409654471 ps
CPU time 386.36 seconds
Started Mar 26 02:35:04 PM PDT 24
Finished Mar 26 02:41:31 PM PDT 24
Peak memory 190800 kb
Host smart-c7c8f7f4-8f89-453d-9573-a974fe6b7a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832977856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1832977856
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4083685020
Short name T108
Test name
Test status
Simulation time 227876757638 ps
CPU time 965.21 seconds
Started Mar 26 02:35:06 PM PDT 24
Finished Mar 26 02:51:12 PM PDT 24
Peak memory 190908 kb
Host smart-c5a9c1f3-a8ed-47aa-8efa-db94a8d66bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083685020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4083685020
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.980172323
Short name T117
Test name
Test status
Simulation time 87598359485 ps
CPU time 215.76 seconds
Started Mar 26 02:34:59 PM PDT 24
Finished Mar 26 02:38:35 PM PDT 24
Peak memory 192864 kb
Host smart-da480e5a-9611-4123-8e98-b3399acae7d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980172323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.980172323
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.24711060
Short name T420
Test name
Test status
Simulation time 247656626454 ps
CPU time 139.12 seconds
Started Mar 26 02:32:24 PM PDT 24
Finished Mar 26 02:34:43 PM PDT 24
Peak memory 182676 kb
Host smart-4012aef0-2c0a-4e10-a560-68129ef2146f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24711060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
rv_timer_cfg_update_on_fly.24711060
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1570579323
Short name T371
Test name
Test status
Simulation time 202564152830 ps
CPU time 174.61 seconds
Started Mar 26 02:32:28 PM PDT 24
Finished Mar 26 02:35:23 PM PDT 24
Peak memory 182668 kb
Host smart-d2c67efc-2aa8-41e4-8800-ee6a47e0cc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570579323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1570579323
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.4233708016
Short name T71
Test name
Test status
Simulation time 589592780152 ps
CPU time 590.63 seconds
Started Mar 26 02:32:24 PM PDT 24
Finished Mar 26 02:42:15 PM PDT 24
Peak memory 190892 kb
Host smart-5abe4fea-6a24-4982-b400-1de562e06cb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233708016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.4233708016
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1705205840
Short name T72
Test name
Test status
Simulation time 29410761772 ps
CPU time 49.85 seconds
Started Mar 26 02:32:29 PM PDT 24
Finished Mar 26 02:33:19 PM PDT 24
Peak memory 190864 kb
Host smart-11f438e4-5f6f-4dc4-8c2d-2a8c9008bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705205840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1705205840
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2542228152
Short name T456
Test name
Test status
Simulation time 27867943 ps
CPU time 0.57 seconds
Started Mar 26 02:32:26 PM PDT 24
Finished Mar 26 02:32:27 PM PDT 24
Peak memory 182404 kb
Host smart-151b206d-2bb4-41b3-8306-591b257c1b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542228152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2542228152
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3197864412
Short name T441
Test name
Test status
Simulation time 87418956358 ps
CPU time 669.55 seconds
Started Mar 26 02:32:28 PM PDT 24
Finished Mar 26 02:43:37 PM PDT 24
Peak memory 205512 kb
Host smart-adb9262a-8ded-443b-bd71-e0f696a391e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197864412 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3197864412
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1359239205
Short name T156
Test name
Test status
Simulation time 1958864421993 ps
CPU time 419.14 seconds
Started Mar 26 02:35:00 PM PDT 24
Finished Mar 26 02:41:59 PM PDT 24
Peak memory 190884 kb
Host smart-21fc15a4-0401-4c83-a73a-27e69af5e2fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359239205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1359239205
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2393626689
Short name T3
Test name
Test status
Simulation time 43780479441 ps
CPU time 40.34 seconds
Started Mar 26 02:35:07 PM PDT 24
Finished Mar 26 02:35:47 PM PDT 24
Peak memory 194344 kb
Host smart-5ad593fb-a07d-4e14-94ac-25f17d18d0cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393626689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2393626689
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2760493840
Short name T167
Test name
Test status
Simulation time 183050703482 ps
CPU time 128.48 seconds
Started Mar 26 02:35:06 PM PDT 24
Finished Mar 26 02:37:15 PM PDT 24
Peak memory 193080 kb
Host smart-acf004e5-7a16-4c87-a2f3-469b8347106f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760493840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2760493840
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.219238025
Short name T192
Test name
Test status
Simulation time 99932550620 ps
CPU time 488.26 seconds
Started Mar 26 02:35:13 PM PDT 24
Finished Mar 26 02:43:22 PM PDT 24
Peak memory 182684 kb
Host smart-2fc18b83-acb1-4b6b-b018-6a1e3513a3d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219238025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.219238025
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1875295006
Short name T312
Test name
Test status
Simulation time 284505273657 ps
CPU time 189.3 seconds
Started Mar 26 02:35:09 PM PDT 24
Finished Mar 26 02:38:18 PM PDT 24
Peak memory 190776 kb
Host smart-3485ddde-561a-402e-b165-8dd1a7383e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875295006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1875295006
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3011505697
Short name T233
Test name
Test status
Simulation time 130901215196 ps
CPU time 66.53 seconds
Started Mar 26 02:35:10 PM PDT 24
Finished Mar 26 02:36:16 PM PDT 24
Peak memory 182672 kb
Host smart-3126c2c1-efc5-47d9-9749-f7807a03ff0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011505697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3011505697
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.4020127821
Short name T398
Test name
Test status
Simulation time 43169702961 ps
CPU time 40.88 seconds
Started Mar 26 02:35:12 PM PDT 24
Finished Mar 26 02:35:53 PM PDT 24
Peak memory 182864 kb
Host smart-7c0fef12-9a61-4f82-b5e8-72c2d32bb4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020127821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4020127821
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1006474596
Short name T152
Test name
Test status
Simulation time 201556130986 ps
CPU time 385.61 seconds
Started Mar 26 02:35:13 PM PDT 24
Finished Mar 26 02:41:39 PM PDT 24
Peak memory 182704 kb
Host smart-1ce5b555-67c9-4501-a035-f3e63565e506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006474596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1006474596
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.557985104
Short name T450
Test name
Test status
Simulation time 29927126063 ps
CPU time 23.84 seconds
Started Mar 26 02:35:13 PM PDT 24
Finished Mar 26 02:35:38 PM PDT 24
Peak memory 182696 kb
Host smart-65756e79-bad6-4f86-9ee5-086c1b5e8dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557985104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.557985104
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.75109749
Short name T253
Test name
Test status
Simulation time 161182090434 ps
CPU time 165.38 seconds
Started Mar 26 02:32:25 PM PDT 24
Finished Mar 26 02:35:11 PM PDT 24
Peak memory 182676 kb
Host smart-2af2c723-c412-4b52-a476-1e303c151854
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75109749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
rv_timer_cfg_update_on_fly.75109749
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3965227781
Short name T404
Test name
Test status
Simulation time 259898085819 ps
CPU time 196 seconds
Started Mar 26 02:32:26 PM PDT 24
Finished Mar 26 02:35:42 PM PDT 24
Peak memory 182612 kb
Host smart-9715e50b-2217-4fdd-804e-fcb6ca6f200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965227781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3965227781
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3016960332
Short name T235
Test name
Test status
Simulation time 58105540955 ps
CPU time 70.43 seconds
Started Mar 26 02:32:27 PM PDT 24
Finished Mar 26 02:33:38 PM PDT 24
Peak memory 193784 kb
Host smart-258eafd2-6046-4eeb-810a-706ea035eb71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016960332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3016960332
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3569042277
Short name T301
Test name
Test status
Simulation time 104190881594 ps
CPU time 81.77 seconds
Started Mar 26 02:32:29 PM PDT 24
Finished Mar 26 02:33:51 PM PDT 24
Peak memory 190884 kb
Host smart-2da93c1e-102d-431f-800b-cefc3c8eb680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569042277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3569042277
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.964170069
Short name T65
Test name
Test status
Simulation time 2598857840033 ps
CPU time 1398.69 seconds
Started Mar 26 02:32:26 PM PDT 24
Finished Mar 26 02:55:45 PM PDT 24
Peak memory 190884 kb
Host smart-dde09c3d-f14f-447b-bb53-a9bb622098ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964170069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.964170069
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.217967876
Short name T213
Test name
Test status
Simulation time 162188408103 ps
CPU time 307.39 seconds
Started Mar 26 02:35:10 PM PDT 24
Finished Mar 26 02:40:18 PM PDT 24
Peak memory 194588 kb
Host smart-61a48681-d928-4a42-8511-295c8b51d790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217967876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.217967876
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.237053561
Short name T145
Test name
Test status
Simulation time 236916337767 ps
CPU time 250.59 seconds
Started Mar 26 02:35:23 PM PDT 24
Finished Mar 26 02:39:34 PM PDT 24
Peak memory 190848 kb
Host smart-247c9525-3746-401f-8b6f-1a212e620300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237053561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.237053561
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.884110284
Short name T157
Test name
Test status
Simulation time 641254345594 ps
CPU time 741.26 seconds
Started Mar 26 02:35:24 PM PDT 24
Finished Mar 26 02:47:46 PM PDT 24
Peak memory 190848 kb
Host smart-d3757f4d-e045-47a4-b286-9a94bff31dac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884110284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.884110284
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3273519445
Short name T268
Test name
Test status
Simulation time 175389531814 ps
CPU time 258.76 seconds
Started Mar 26 02:35:24 PM PDT 24
Finished Mar 26 02:39:43 PM PDT 24
Peak memory 190848 kb
Host smart-ff8216bc-6c1b-4089-8f48-c8c6e13e30a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273519445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3273519445
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2263828790
Short name T327
Test name
Test status
Simulation time 58498117381 ps
CPU time 141.03 seconds
Started Mar 26 02:35:23 PM PDT 24
Finished Mar 26 02:37:44 PM PDT 24
Peak memory 190800 kb
Host smart-1d34b72a-d29a-4c5a-ba15-fe18c2bdcfec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263828790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2263828790
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2805247864
Short name T181
Test name
Test status
Simulation time 88611554657 ps
CPU time 91.66 seconds
Started Mar 26 02:32:24 PM PDT 24
Finished Mar 26 02:33:55 PM PDT 24
Peak memory 182588 kb
Host smart-d8eb06d4-f40c-4570-82be-8d9618192cf9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805247864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2805247864
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1305131056
Short name T415
Test name
Test status
Simulation time 95172950555 ps
CPU time 42.61 seconds
Started Mar 26 02:32:27 PM PDT 24
Finished Mar 26 02:33:10 PM PDT 24
Peak memory 182700 kb
Host smart-c6794838-b29a-4dae-849c-75dacf634718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305131056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1305131056
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1505088772
Short name T274
Test name
Test status
Simulation time 256131498791 ps
CPU time 111.82 seconds
Started Mar 26 02:32:28 PM PDT 24
Finished Mar 26 02:34:20 PM PDT 24
Peak memory 190848 kb
Host smart-97b7b8ed-c730-4d5a-9ef8-5bae67161eaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505088772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1505088772
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1303342186
Short name T223
Test name
Test status
Simulation time 57930523898 ps
CPU time 87.92 seconds
Started Mar 26 02:32:24 PM PDT 24
Finished Mar 26 02:33:52 PM PDT 24
Peak memory 194780 kb
Host smart-178c7dad-9737-4095-a707-d1e1a9fb3353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303342186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1303342186
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.4090004896
Short name T76
Test name
Test status
Simulation time 159029183397 ps
CPU time 859.86 seconds
Started Mar 26 02:32:29 PM PDT 24
Finished Mar 26 02:46:49 PM PDT 24
Peak memory 212808 kb
Host smart-8619fd5a-cf48-42f6-9721-d6b1d5746d5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090004896 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.4090004896
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1948679574
Short name T160
Test name
Test status
Simulation time 66613207495 ps
CPU time 120.97 seconds
Started Mar 26 02:35:23 PM PDT 24
Finished Mar 26 02:37:24 PM PDT 24
Peak memory 190908 kb
Host smart-ee2dd6ee-6511-4f8c-86d8-a2cd46212673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948679574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1948679574
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3294450085
Short name T322
Test name
Test status
Simulation time 48369915641 ps
CPU time 85.27 seconds
Started Mar 26 02:35:35 PM PDT 24
Finished Mar 26 02:37:00 PM PDT 24
Peak memory 190892 kb
Host smart-6fdc856c-28ab-4c85-8da3-5e5ff4b6bde8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294450085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3294450085
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.278904506
Short name T335
Test name
Test status
Simulation time 2481395507 ps
CPU time 5.23 seconds
Started Mar 26 02:35:34 PM PDT 24
Finished Mar 26 02:35:40 PM PDT 24
Peak memory 182640 kb
Host smart-5851d87e-bba6-48bb-93fb-2d6bd7a22869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278904506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.278904506
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3316846477
Short name T124
Test name
Test status
Simulation time 2384889928565 ps
CPU time 855.45 seconds
Started Mar 26 02:35:33 PM PDT 24
Finished Mar 26 02:49:49 PM PDT 24
Peak memory 190844 kb
Host smart-6b17cc22-efd5-4129-a1b0-cd530e990e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316846477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3316846477
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2148868583
Short name T49
Test name
Test status
Simulation time 216103487444 ps
CPU time 377.54 seconds
Started Mar 26 02:35:33 PM PDT 24
Finished Mar 26 02:41:51 PM PDT 24
Peak memory 190852 kb
Host smart-fc40d262-3920-4215-9ff5-33e66d9e5105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148868583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2148868583
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2013706687
Short name T239
Test name
Test status
Simulation time 76191800957 ps
CPU time 182.89 seconds
Started Mar 26 02:35:35 PM PDT 24
Finished Mar 26 02:38:38 PM PDT 24
Peak memory 190892 kb
Host smart-ca29ae13-03e7-4f62-90c2-39aa5535c2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013706687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2013706687
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1053475505
Short name T291
Test name
Test status
Simulation time 77191044862 ps
CPU time 268.38 seconds
Started Mar 26 02:35:34 PM PDT 24
Finished Mar 26 02:40:03 PM PDT 24
Peak memory 190896 kb
Host smart-f879e19c-682a-43d8-847c-a569ca319611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053475505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1053475505
Directory /workspace/99.rv_timer_random/latest
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