Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.36 98.73 100.00 100.00 100.00 99.89


Total test records in report: 583
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2109215006 Mar 28 12:31:15 PM PDT 24 Mar 28 12:31:15 PM PDT 24 19089431 ps
T113 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3375189047 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:43 PM PDT 24 94353904 ps
T512 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2479859861 Mar 28 12:31:08 PM PDT 24 Mar 28 12:31:09 PM PDT 24 24440729 ps
T513 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.133999701 Mar 28 12:31:03 PM PDT 24 Mar 28 12:31:04 PM PDT 24 90464592 ps
T514 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3810963986 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:44 PM PDT 24 452194265 ps
T515 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2370611517 Mar 28 12:31:03 PM PDT 24 Mar 28 12:31:04 PM PDT 24 65583170 ps
T516 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3125842643 Mar 28 12:31:03 PM PDT 24 Mar 28 12:31:04 PM PDT 24 24844619 ps
T139 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1821075582 Mar 28 12:30:36 PM PDT 24 Mar 28 12:30:37 PM PDT 24 89882724 ps
T517 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1265578046 Mar 28 12:31:14 PM PDT 24 Mar 28 12:31:15 PM PDT 24 48662847 ps
T518 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1237803895 Mar 28 12:30:56 PM PDT 24 Mar 28 12:30:57 PM PDT 24 35916942 ps
T114 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1910246417 Mar 28 12:30:50 PM PDT 24 Mar 28 12:30:51 PM PDT 24 27707433 ps
T519 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3603778824 Mar 28 12:30:57 PM PDT 24 Mar 28 12:30:58 PM PDT 24 12803831 ps
T140 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3458006357 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:44 PM PDT 24 99810104 ps
T520 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1262387935 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:43 PM PDT 24 39954016 ps
T521 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3516283215 Mar 28 12:30:43 PM PDT 24 Mar 28 12:30:44 PM PDT 24 70871307 ps
T522 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3976211404 Mar 28 12:30:52 PM PDT 24 Mar 28 12:30:53 PM PDT 24 128481803 ps
T523 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1795686682 Mar 28 12:30:48 PM PDT 24 Mar 28 12:30:48 PM PDT 24 408782400 ps
T115 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2605393859 Mar 28 12:30:45 PM PDT 24 Mar 28 12:30:46 PM PDT 24 38447110 ps
T524 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1860302643 Mar 28 12:31:00 PM PDT 24 Mar 28 12:31:01 PM PDT 24 37052992 ps
T525 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.79845856 Mar 28 12:30:59 PM PDT 24 Mar 28 12:30:59 PM PDT 24 53035208 ps
T526 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1413721880 Mar 28 12:30:52 PM PDT 24 Mar 28 12:30:55 PM PDT 24 153781714 ps
T527 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1372786634 Mar 28 12:31:04 PM PDT 24 Mar 28 12:31:05 PM PDT 24 292962190 ps
T528 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3590260517 Mar 28 12:31:00 PM PDT 24 Mar 28 12:31:02 PM PDT 24 196575434 ps
T529 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.480248268 Mar 28 12:30:43 PM PDT 24 Mar 28 12:30:45 PM PDT 24 243116615 ps
T118 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2860975199 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:44 PM PDT 24 11861596 ps
T530 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1569033093 Mar 28 12:31:02 PM PDT 24 Mar 28 12:31:02 PM PDT 24 39692659 ps
T531 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1097717040 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:44 PM PDT 24 18837856 ps
T532 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2817839200 Mar 28 12:30:52 PM PDT 24 Mar 28 12:30:52 PM PDT 24 54911408 ps
T533 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2456755534 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:42 PM PDT 24 32640056 ps
T534 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2448737537 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:44 PM PDT 24 168053932 ps
T535 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3207967589 Mar 28 12:31:18 PM PDT 24 Mar 28 12:31:18 PM PDT 24 80499885 ps
T536 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.406967038 Mar 28 12:30:45 PM PDT 24 Mar 28 12:30:48 PM PDT 24 582346483 ps
T537 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.444210868 Mar 28 12:30:47 PM PDT 24 Mar 28 12:30:47 PM PDT 24 42431081 ps
T538 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.239243482 Mar 28 12:31:05 PM PDT 24 Mar 28 12:31:06 PM PDT 24 13011183 ps
T539 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.967652065 Mar 28 12:30:53 PM PDT 24 Mar 28 12:30:54 PM PDT 24 60505105 ps
T540 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.359780384 Mar 28 12:30:51 PM PDT 24 Mar 28 12:30:52 PM PDT 24 33060647 ps
T541 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2059341512 Mar 28 12:30:50 PM PDT 24 Mar 28 12:30:54 PM PDT 24 553570650 ps
T141 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1563778303 Mar 28 12:30:52 PM PDT 24 Mar 28 12:30:53 PM PDT 24 49353533 ps
T542 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2431853237 Mar 28 12:31:02 PM PDT 24 Mar 28 12:31:03 PM PDT 24 73471725 ps
T543 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2523325813 Mar 28 12:31:03 PM PDT 24 Mar 28 12:31:04 PM PDT 24 25167029 ps
T544 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.200301888 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:44 PM PDT 24 65406618 ps
T545 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3396686244 Mar 28 12:30:43 PM PDT 24 Mar 28 12:30:46 PM PDT 24 1326381887 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.88270660 Mar 28 12:30:51 PM PDT 24 Mar 28 12:30:51 PM PDT 24 62700783 ps
T547 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3292709743 Mar 28 12:31:03 PM PDT 24 Mar 28 12:31:05 PM PDT 24 46343663 ps
T548 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1603091724 Mar 28 12:31:12 PM PDT 24 Mar 28 12:31:14 PM PDT 24 66046834 ps
T116 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1397123743 Mar 28 12:30:54 PM PDT 24 Mar 28 12:30:55 PM PDT 24 28640494 ps
T549 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3191862731 Mar 28 12:30:44 PM PDT 24 Mar 28 12:30:45 PM PDT 24 29824512 ps
T550 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.656586139 Mar 28 12:30:45 PM PDT 24 Mar 28 12:30:47 PM PDT 24 39929131 ps
T551 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2454648802 Mar 28 12:30:46 PM PDT 24 Mar 28 12:30:47 PM PDT 24 34990232 ps
T552 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1685823237 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:44 PM PDT 24 61119886 ps
T553 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1537850537 Mar 28 12:30:39 PM PDT 24 Mar 28 12:30:40 PM PDT 24 71765100 ps
T554 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1872305064 Mar 28 12:31:07 PM PDT 24 Mar 28 12:31:08 PM PDT 24 38915984 ps
T555 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.358449004 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:44 PM PDT 24 35491111 ps
T556 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2445037854 Mar 28 12:31:07 PM PDT 24 Mar 28 12:31:07 PM PDT 24 14694045 ps
T119 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.172266070 Mar 28 12:30:49 PM PDT 24 Mar 28 12:30:50 PM PDT 24 14313177 ps
T557 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1191529569 Mar 28 12:31:02 PM PDT 24 Mar 28 12:31:03 PM PDT 24 37294077 ps
T558 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3727483949 Mar 28 12:31:07 PM PDT 24 Mar 28 12:31:07 PM PDT 24 10562025 ps
T559 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4285330605 Mar 28 12:30:32 PM PDT 24 Mar 28 12:30:34 PM PDT 24 930565407 ps
T560 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2059163157 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:43 PM PDT 24 48935155 ps
T561 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1253720469 Mar 28 12:30:45 PM PDT 24 Mar 28 12:30:46 PM PDT 24 18508800 ps
T562 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.263965059 Mar 28 12:31:03 PM PDT 24 Mar 28 12:31:04 PM PDT 24 64806832 ps
T563 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.724016893 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:42 PM PDT 24 27113402 ps
T564 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.215001080 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:21 PM PDT 24 48956278 ps
T565 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3481781682 Mar 28 12:30:39 PM PDT 24 Mar 28 12:30:39 PM PDT 24 12506441 ps
T566 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3375607915 Mar 28 12:30:40 PM PDT 24 Mar 28 12:30:42 PM PDT 24 45452034 ps
T567 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2572635960 Mar 28 12:31:10 PM PDT 24 Mar 28 12:31:11 PM PDT 24 193559191 ps
T568 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3407808592 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:43 PM PDT 24 40819038 ps
T569 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.26789835 Mar 28 12:30:51 PM PDT 24 Mar 28 12:30:52 PM PDT 24 305776394 ps
T570 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.170537533 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:44 PM PDT 24 20032087 ps
T571 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4275617049 Mar 28 12:30:40 PM PDT 24 Mar 28 12:30:42 PM PDT 24 15189984 ps
T572 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1082890707 Mar 28 12:30:51 PM PDT 24 Mar 28 12:30:52 PM PDT 24 145162509 ps
T573 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1586738158 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:44 PM PDT 24 99476600 ps
T574 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3561972688 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:43 PM PDT 24 232617255 ps
T575 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1561269049 Mar 28 12:30:58 PM PDT 24 Mar 28 12:31:00 PM PDT 24 43740537 ps
T576 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2069626222 Mar 28 12:30:40 PM PDT 24 Mar 28 12:30:42 PM PDT 24 69657855 ps
T577 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1599976323 Mar 28 12:30:39 PM PDT 24 Mar 28 12:30:40 PM PDT 24 15397746 ps
T117 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1909732827 Mar 28 12:31:00 PM PDT 24 Mar 28 12:31:01 PM PDT 24 19119009 ps
T578 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1356631744 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:45 PM PDT 24 105714588 ps
T579 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.220992851 Mar 28 12:30:40 PM PDT 24 Mar 28 12:30:44 PM PDT 24 461059276 ps
T580 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2347444437 Mar 28 12:30:46 PM PDT 24 Mar 28 12:30:47 PM PDT 24 37922185 ps
T581 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4084409264 Mar 28 12:30:46 PM PDT 24 Mar 28 12:30:47 PM PDT 24 27860041 ps
T582 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3916222286 Mar 28 12:30:42 PM PDT 24 Mar 28 12:30:43 PM PDT 24 13491546 ps
T583 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1989636514 Mar 28 12:31:09 PM PDT 24 Mar 28 12:31:11 PM PDT 24 1877997027 ps

Test location /workspace/coverage/default/173.rv_timer_random.3089109283
Short name T8
Test name
Test status
Simulation time 20550842200 ps
CPU time 39.61 seconds
Started Mar 28 12:58:54 PM PDT 24
Finished Mar 28 12:59:34 PM PDT 24
Peak memory 182616 kb
Host smart-742b25d5-2eb7-464f-8823-4d6eed9e2eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089109283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3089109283
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1357853235
Short name T15
Test name
Test status
Simulation time 139875773036 ps
CPU time 1515.23 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 01:22:43 PM PDT 24
Peak memory 210828 kb
Host smart-648ac5aa-fc19-40ca-a020-83f2774c242b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357853235 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1357853235
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1640282992
Short name T11
Test name
Test status
Simulation time 511839034624 ps
CPU time 1852.44 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 190832 kb
Host smart-25bd0c8a-b372-4d0b-a83a-d0c6955a7285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640282992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1640282992
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1049549099
Short name T74
Test name
Test status
Simulation time 596761072124 ps
CPU time 2126.33 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 195376 kb
Host smart-4dab30dd-549c-496f-8e28-981126199cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049549099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1049549099
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.4257288519
Short name T6
Test name
Test status
Simulation time 182535775691 ps
CPU time 1020.18 seconds
Started Mar 28 12:58:26 PM PDT 24
Finished Mar 28 01:15:27 PM PDT 24
Peak memory 190916 kb
Host smart-990e37f3-cc2d-44df-abee-905c45d82a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257288519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4257288519
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1418970457
Short name T32
Test name
Test status
Simulation time 330208076 ps
CPU time 1.16 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 194120 kb
Host smart-ad75e201-a6ac-4f2a-9617-07644416e04b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418970457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1418970457
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1966580150
Short name T176
Test name
Test status
Simulation time 541296224066 ps
CPU time 1472.75 seconds
Started Mar 28 12:57:38 PM PDT 24
Finished Mar 28 01:22:11 PM PDT 24
Peak memory 195840 kb
Host smart-57183afd-53c1-4a1a-b3d4-70c90ce42c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966580150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1966580150
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1615394526
Short name T72
Test name
Test status
Simulation time 2461819335816 ps
CPU time 1696.39 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:26:33 PM PDT 24
Peak memory 190808 kb
Host smart-3ea0405a-ac05-487a-a630-251a730e0444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615394526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1615394526
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2422458003
Short name T68
Test name
Test status
Simulation time 52937502 ps
CPU time 0.59 seconds
Started Mar 28 12:31:04 PM PDT 24
Finished Mar 28 12:31:05 PM PDT 24
Peak memory 182608 kb
Host smart-c369e53d-1295-4951-9717-cc6aa7a38b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422458003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2422458003
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2365807268
Short name T189
Test name
Test status
Simulation time 844044747831 ps
CPU time 1800.3 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:28:02 PM PDT 24
Peak memory 190904 kb
Host smart-cebc0e4f-6ed2-4794-9e02-61d66fae2619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365807268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2365807268
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2611903209
Short name T241
Test name
Test status
Simulation time 868335526236 ps
CPU time 1821.84 seconds
Started Mar 28 12:58:13 PM PDT 24
Finished Mar 28 01:28:35 PM PDT 24
Peak memory 190768 kb
Host smart-c58d725d-e66c-4eb8-9412-42eb887a2a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611903209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2611903209
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2654014245
Short name T194
Test name
Test status
Simulation time 628359667339 ps
CPU time 917.5 seconds
Started Mar 28 12:57:48 PM PDT 24
Finished Mar 28 01:13:06 PM PDT 24
Peak memory 195552 kb
Host smart-33407643-1544-4529-b3d3-29e94624eeb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654014245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2654014245
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3030130151
Short name T76
Test name
Test status
Simulation time 1417420569785 ps
CPU time 1425.26 seconds
Started Mar 28 12:57:39 PM PDT 24
Finished Mar 28 01:21:25 PM PDT 24
Peak memory 189972 kb
Host smart-d2228e01-2663-4f8d-95e9-2bf65c5bef0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030130151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3030130151
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3918238723
Short name T19
Test name
Test status
Simulation time 233947580 ps
CPU time 0.85 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 213196 kb
Host smart-a3a48cd8-c24d-4cb4-aff7-0f3a40312355
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918238723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3918238723
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/177.rv_timer_random.2840229638
Short name T165
Test name
Test status
Simulation time 754250662667 ps
CPU time 699.5 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:10:32 PM PDT 24
Peak memory 194376 kb
Host smart-b3eb1638-fcc7-4734-aaad-bce1591aab86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840229638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2840229638
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3972140347
Short name T249
Test name
Test status
Simulation time 175235548091 ps
CPU time 758.64 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:10:40 PM PDT 24
Peak memory 196296 kb
Host smart-b15de394-b19b-4159-8291-ede22c393856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972140347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3972140347
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/117.rv_timer_random.1625657343
Short name T48
Test name
Test status
Simulation time 323021226020 ps
CPU time 218.66 seconds
Started Mar 28 12:58:27 PM PDT 24
Finished Mar 28 01:02:06 PM PDT 24
Peak memory 190900 kb
Host smart-14220ac3-bd17-4743-b08b-9c7788d0bc2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625657343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1625657343
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1442573048
Short name T228
Test name
Test status
Simulation time 2334722210597 ps
CPU time 2295.08 seconds
Started Mar 28 12:57:48 PM PDT 24
Finished Mar 28 01:36:03 PM PDT 24
Peak memory 190912 kb
Host smart-f009a318-7f97-42ad-a51d-4c9b1f0864d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442573048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1442573048
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2950009729
Short name T12
Test name
Test status
Simulation time 673108071963 ps
CPU time 2674.48 seconds
Started Mar 28 12:57:45 PM PDT 24
Finished Mar 28 01:42:20 PM PDT 24
Peak memory 196348 kb
Host smart-b14ac21c-6495-4a68-8957-a4de0c947c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950009729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2950009729
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3393275650
Short name T71
Test name
Test status
Simulation time 386855132143 ps
CPU time 645.79 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:08:43 PM PDT 24
Peak memory 190868 kb
Host smart-f1353d0c-e301-40e6-9d13-ab885c5b94c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393275650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3393275650
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.2503596783
Short name T186
Test name
Test status
Simulation time 626748791979 ps
CPU time 1084.89 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 01:15:33 PM PDT 24
Peak memory 190948 kb
Host smart-323bc6d1-88b8-4a1f-be9e-b582e9e01021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503596783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2503596783
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1736104083
Short name T240
Test name
Test status
Simulation time 985032647398 ps
CPU time 682.63 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:09:07 PM PDT 24
Peak memory 190552 kb
Host smart-bea1930b-0db7-4d70-bb39-9fd340c1013a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736104083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1736104083
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_random.1512738014
Short name T182
Test name
Test status
Simulation time 169592029381 ps
CPU time 1834.49 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:28:36 PM PDT 24
Peak memory 190888 kb
Host smart-c4f2c169-8163-4399-99dd-2557b8046f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512738014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1512738014
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3854875189
Short name T330
Test name
Test status
Simulation time 333292250755 ps
CPU time 1349.32 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:20:46 PM PDT 24
Peak memory 190912 kb
Host smart-a87e17d8-07c0-40e8-a813-804168058be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854875189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3854875189
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1946325960
Short name T58
Test name
Test status
Simulation time 15119270 ps
CPU time 0.55 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 182608 kb
Host smart-1d699638-bf6f-4e3d-bfd5-6aa67264329d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946325960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1946325960
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/135.rv_timer_random.3833647143
Short name T259
Test name
Test status
Simulation time 161648867942 ps
CPU time 645.95 seconds
Started Mar 28 12:58:41 PM PDT 24
Finished Mar 28 01:09:28 PM PDT 24
Peak memory 190900 kb
Host smart-d0af3bcc-6366-42b1-bb84-28297f0d6135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833647143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3833647143
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2914159788
Short name T156
Test name
Test status
Simulation time 83155876992 ps
CPU time 133.01 seconds
Started Mar 28 12:58:40 PM PDT 24
Finished Mar 28 01:00:53 PM PDT 24
Peak memory 190824 kb
Host smart-59ff9589-fb29-4e0f-bb58-99cf9e8a500e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914159788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2914159788
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1476678188
Short name T52
Test name
Test status
Simulation time 829829584131 ps
CPU time 461.1 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:05:26 PM PDT 24
Peak memory 182724 kb
Host smart-497d0997-1aa3-4af7-a810-bfd9eab4b9b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476678188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1476678188
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_random.2534959898
Short name T104
Test name
Test status
Simulation time 149229015649 ps
CPU time 214.73 seconds
Started Mar 28 12:57:42 PM PDT 24
Finished Mar 28 01:01:17 PM PDT 24
Peak memory 194892 kb
Host smart-7437c71c-5a67-4f3c-8d41-e65f3db83013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534959898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2534959898
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.214458931
Short name T304
Test name
Test status
Simulation time 118454852533 ps
CPU time 191.61 seconds
Started Mar 28 12:58:24 PM PDT 24
Finished Mar 28 01:01:36 PM PDT 24
Peak memory 190548 kb
Host smart-abc463ce-3944-426d-9dca-4fb8dcf3aec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214458931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.214458931
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.241996818
Short name T206
Test name
Test status
Simulation time 117849068300 ps
CPU time 739.61 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 01:10:01 PM PDT 24
Peak memory 190908 kb
Host smart-827e7a9b-5e05-4614-9dd4-561a19f78589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241996818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.241996818
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_random.2768816150
Short name T211
Test name
Test status
Simulation time 151758217499 ps
CPU time 1698.84 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 01:25:46 PM PDT 24
Peak memory 190812 kb
Host smart-20c845ec-4883-4916-95eb-c344d469c4a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768816150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2768816150
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2434368850
Short name T272
Test name
Test status
Simulation time 767033971470 ps
CPU time 638.33 seconds
Started Mar 28 12:57:39 PM PDT 24
Finished Mar 28 01:08:18 PM PDT 24
Peak memory 194620 kb
Host smart-da160b69-9f05-444e-bac8-0585db8188f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434368850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2434368850
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.2024879223
Short name T280
Test name
Test status
Simulation time 699290485963 ps
CPU time 767.3 seconds
Started Mar 28 12:58:37 PM PDT 24
Finished Mar 28 01:11:26 PM PDT 24
Peak memory 190880 kb
Host smart-76c06865-35c9-48fa-8a5a-3b39300a18ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024879223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2024879223
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1038484005
Short name T67
Test name
Test status
Simulation time 138377535187 ps
CPU time 278.6 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:03:01 PM PDT 24
Peak memory 190208 kb
Host smart-597de274-9eaf-41fc-a0de-e2f4e0ad7a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038484005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1038484005
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3966344088
Short name T269
Test name
Test status
Simulation time 442857860321 ps
CPU time 1248.57 seconds
Started Mar 28 12:58:36 PM PDT 24
Finished Mar 28 01:19:25 PM PDT 24
Peak memory 190784 kb
Host smart-c66008d7-262f-4cf9-a30e-b9cebf11234d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966344088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3966344088
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3647979237
Short name T232
Test name
Test status
Simulation time 470730170659 ps
CPU time 303.43 seconds
Started Mar 28 12:59:09 PM PDT 24
Finished Mar 28 01:04:13 PM PDT 24
Peak memory 190860 kb
Host smart-4fced806-ab0a-4a41-84b0-72be12e07256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647979237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3647979237
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.1799773589
Short name T2
Test name
Test status
Simulation time 198124850863 ps
CPU time 308.52 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:03:10 PM PDT 24
Peak memory 190916 kb
Host smart-b6a13280-a41c-4f94-a3b2-1be43889c08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799773589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1799773589
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3076756962
Short name T66
Test name
Test status
Simulation time 556166221510 ps
CPU time 534.19 seconds
Started Mar 28 12:58:30 PM PDT 24
Finished Mar 28 01:07:25 PM PDT 24
Peak memory 190900 kb
Host smart-ac230f9f-8fd6-444d-b3d4-65b9697fc923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076756962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3076756962
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3609665431
Short name T208
Test name
Test status
Simulation time 171068599974 ps
CPU time 319.24 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:03:53 PM PDT 24
Peak memory 190764 kb
Host smart-1d98871f-2d8c-47e0-966f-b4fe03ba83ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609665431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3609665431
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.3150804177
Short name T274
Test name
Test status
Simulation time 744141387710 ps
CPU time 571.96 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:07:16 PM PDT 24
Peak memory 190888 kb
Host smart-860919de-f871-4a8b-8fcf-9d8710240dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150804177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3150804177
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1929170593
Short name T218
Test name
Test status
Simulation time 496027279503 ps
CPU time 1979.17 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 190880 kb
Host smart-f08c09cf-8ba6-4efb-93d0-467a580d6ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929170593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1929170593
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.542687362
Short name T160
Test name
Test status
Simulation time 219092099517 ps
CPU time 533.59 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 01:07:46 PM PDT 24
Peak memory 190852 kb
Host smart-193fd425-9030-435c-86a0-14967dff1a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542687362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.542687362
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.1346238408
Short name T163
Test name
Test status
Simulation time 458838655208 ps
CPU time 1008.9 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:14:47 PM PDT 24
Peak memory 190780 kb
Host smart-77989695-a2c0-4958-a854-ca3068059c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346238408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1346238408
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.1162153737
Short name T294
Test name
Test status
Simulation time 110364478994 ps
CPU time 295.37 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:02:53 PM PDT 24
Peak memory 190900 kb
Host smart-f8f3b9ab-148a-4e60-b1ac-a35903d577cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162153737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1162153737
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1554301789
Short name T209
Test name
Test status
Simulation time 388072636342 ps
CPU time 1220.98 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:18:44 PM PDT 24
Peak memory 191020 kb
Host smart-c0472830-d38b-4d1a-bed2-9799e0054102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554301789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1554301789
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2732619862
Short name T159
Test name
Test status
Simulation time 608448315563 ps
CPU time 2207.89 seconds
Started Mar 28 12:58:25 PM PDT 24
Finished Mar 28 01:35:14 PM PDT 24
Peak memory 190904 kb
Host smart-a661302b-93d0-4ba7-aa39-276051576b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732619862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2732619862
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3118039051
Short name T106
Test name
Test status
Simulation time 205396612501 ps
CPU time 670.72 seconds
Started Mar 28 12:58:27 PM PDT 24
Finished Mar 28 01:09:37 PM PDT 24
Peak memory 191020 kb
Host smart-9a9bc68e-b4b8-4fb2-9256-a0c50812d6f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118039051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3118039051
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3347099398
Short name T151
Test name
Test status
Simulation time 190324936058 ps
CPU time 658.21 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:09:31 PM PDT 24
Peak memory 190772 kb
Host smart-e9ea472a-699d-4654-bb5a-5b8b0a7df511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347099398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3347099398
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1566070607
Short name T91
Test name
Test status
Simulation time 366748805315 ps
CPU time 184.13 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 01:01:40 PM PDT 24
Peak memory 192968 kb
Host smart-4f0e050c-befe-45fc-abed-da0317f68fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566070607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1566070607
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1028691122
Short name T412
Test name
Test status
Simulation time 84037328331 ps
CPU time 168.89 seconds
Started Mar 28 12:58:31 PM PDT 24
Finished Mar 28 01:01:20 PM PDT 24
Peak memory 191908 kb
Host smart-08d5d17c-23c9-4dfe-ade9-eaa66da2679b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028691122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1028691122
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2536932432
Short name T129
Test name
Test status
Simulation time 315820205430 ps
CPU time 868.28 seconds
Started Mar 28 12:58:31 PM PDT 24
Finished Mar 28 01:13:00 PM PDT 24
Peak memory 190876 kb
Host smart-b3a0d7cd-7283-4ee9-ace2-295ab155b846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536932432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2536932432
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.399116309
Short name T158
Test name
Test status
Simulation time 255663138606 ps
CPU time 1608.85 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 190876 kb
Host smart-ff0839a9-8357-4626-acc0-e182a92b342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399116309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.399116309
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1180498616
Short name T303
Test name
Test status
Simulation time 105897454009 ps
CPU time 313.63 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:04:06 PM PDT 24
Peak memory 194476 kb
Host smart-bd3ad1d6-5fc0-453f-a43e-8f54c804b13a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180498616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1180498616
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.1227800495
Short name T334
Test name
Test status
Simulation time 103672591199 ps
CPU time 49.34 seconds
Started Mar 28 12:57:47 PM PDT 24
Finished Mar 28 12:58:36 PM PDT 24
Peak memory 190912 kb
Host smart-fa939fd2-fa12-4bb1-80a6-9541aa5acc25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227800495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1227800495
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1064096303
Short name T332
Test name
Test status
Simulation time 570745878372 ps
CPU time 1147.11 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 01:17:07 PM PDT 24
Peak memory 190772 kb
Host smart-b6d52995-0828-4f53-bdec-3ca9ce6a5d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064096303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1064096303
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random.1463578357
Short name T413
Test name
Test status
Simulation time 1037892653350 ps
CPU time 339.39 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 01:03:40 PM PDT 24
Peak memory 190796 kb
Host smart-73e39037-1e5f-431f-bd5a-d2c36f4e6a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463578357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1463578357
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3813558673
Short name T238
Test name
Test status
Simulation time 526531938142 ps
CPU time 736.03 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 01:10:30 PM PDT 24
Peak memory 194536 kb
Host smart-e2b20353-eb9a-41ad-8c91-9fc08983e3eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813558673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3813558673
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random.3396835760
Short name T243
Test name
Test status
Simulation time 485570620395 ps
CPU time 352.62 seconds
Started Mar 28 12:58:18 PM PDT 24
Finished Mar 28 01:04:10 PM PDT 24
Peak memory 190912 kb
Host smart-97c0a4ed-78d5-4244-ab6d-2152aff58a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396835760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3396835760
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.2652743381
Short name T316
Test name
Test status
Simulation time 742708039210 ps
CPU time 2563.87 seconds
Started Mar 28 12:57:30 PM PDT 24
Finished Mar 28 01:40:14 PM PDT 24
Peak memory 194804 kb
Host smart-ffe069f8-14b6-4d82-8659-5c4fcdc370fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652743381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2652743381
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2301051930
Short name T125
Test name
Test status
Simulation time 61208626 ps
CPU time 0.79 seconds
Started Mar 28 12:30:47 PM PDT 24
Finished Mar 28 12:30:48 PM PDT 24
Peak memory 193244 kb
Host smart-e05efad5-ba75-43d6-938c-342d53700b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301051930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2301051930
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/100.rv_timer_random.425909386
Short name T80
Test name
Test status
Simulation time 1775732003251 ps
CPU time 2027.02 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 190836 kb
Host smart-21b54b0c-2657-4b68-9bcd-7f114430852c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425909386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.425909386
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1215043311
Short name T147
Test name
Test status
Simulation time 102235499123 ps
CPU time 163.28 seconds
Started Mar 28 12:58:24 PM PDT 24
Finished Mar 28 01:01:07 PM PDT 24
Peak memory 190964 kb
Host smart-bf45c1f8-6470-4cca-b697-627601ffb7d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215043311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1215043311
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.962264324
Short name T172
Test name
Test status
Simulation time 208566850802 ps
CPU time 225.82 seconds
Started Mar 28 12:58:36 PM PDT 24
Finished Mar 28 01:02:22 PM PDT 24
Peak memory 190788 kb
Host smart-22629884-eebf-4c36-8641-441a83d25ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962264324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.962264324
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.691413357
Short name T49
Test name
Test status
Simulation time 305454789449 ps
CPU time 1736.64 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 190884 kb
Host smart-11d2d606-144f-4fac-9b96-64bd4ea138ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691413357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.691413357
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3048581707
Short name T196
Test name
Test status
Simulation time 78705666347 ps
CPU time 48.53 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 12:58:50 PM PDT 24
Peak memory 190912 kb
Host smart-4a991a2b-e7be-4c7f-9293-8ff48ffe595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048581707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3048581707
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3101212762
Short name T170
Test name
Test status
Simulation time 164725416877 ps
CPU time 263.2 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:02:21 PM PDT 24
Peak memory 182708 kb
Host smart-4217fc64-8058-4abc-bc1a-be20902a1232
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101212762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3101212762
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random.89963685
Short name T46
Test name
Test status
Simulation time 728123492999 ps
CPU time 1394.33 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:21:12 PM PDT 24
Peak memory 190904 kb
Host smart-1538241a-374a-454b-b66f-98240c6a2361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89963685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.89963685
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random.2877931907
Short name T50
Test name
Test status
Simulation time 83735163831 ps
CPU time 1639.68 seconds
Started Mar 28 12:58:12 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 190880 kb
Host smart-629ebb43-bb67-480b-8e67-239e0f119ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877931907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2877931907
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2569140139
Short name T148
Test name
Test status
Simulation time 512197138559 ps
CPU time 699.08 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 01:10:02 PM PDT 24
Peak memory 194488 kb
Host smart-eb2f1097-9a2b-4430-98ba-6c5cd4188951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569140139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2569140139
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3765127585
Short name T154
Test name
Test status
Simulation time 812151902290 ps
CPU time 476.8 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:06:30 PM PDT 24
Peak memory 190772 kb
Host smart-b3036bf8-37c6-4d4a-9dda-f836846e041e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765127585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3765127585
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3458006357
Short name T140
Test name
Test status
Simulation time 99810104 ps
CPU time 1.13 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 195096 kb
Host smart-8dcd2342-8812-483f-b207-20a60a44fd50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458006357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3458006357
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/106.rv_timer_random.3093232736
Short name T260
Test name
Test status
Simulation time 267877895270 ps
CPU time 461.16 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:06:14 PM PDT 24
Peak memory 190764 kb
Host smart-5ee38bca-9bf7-4c5b-b5ec-ffcd2e20db17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093232736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3093232736
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.2188450862
Short name T155
Test name
Test status
Simulation time 72185879441 ps
CPU time 60.96 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 12:59:24 PM PDT 24
Peak memory 190816 kb
Host smart-6aec8ddc-261d-4749-b69c-f91add2efcd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188450862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2188450862
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3145901763
Short name T227
Test name
Test status
Simulation time 123875129349 ps
CPU time 240.12 seconds
Started Mar 28 12:58:24 PM PDT 24
Finished Mar 28 01:02:25 PM PDT 24
Peak memory 190892 kb
Host smart-44057107-c145-49fd-ba04-fe9cd3fed70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145901763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3145901763
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2623069908
Short name T361
Test name
Test status
Simulation time 243304604670 ps
CPU time 223.19 seconds
Started Mar 28 12:58:34 PM PDT 24
Finished Mar 28 01:02:17 PM PDT 24
Peak memory 190752 kb
Host smart-86911b37-3222-470a-b28d-f2c1e05f5981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623069908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2623069908
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.7708704
Short name T279
Test name
Test status
Simulation time 517622873733 ps
CPU time 346.95 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 01:03:27 PM PDT 24
Peak memory 190872 kb
Host smart-b2ed59a7-b386-42fc-a99c-68083b1680dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7708704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.7708704
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.219746243
Short name T174
Test name
Test status
Simulation time 77308560356 ps
CPU time 1558.41 seconds
Started Mar 28 12:58:30 PM PDT 24
Finished Mar 28 01:24:29 PM PDT 24
Peak memory 194472 kb
Host smart-825c94c5-1a77-4d8c-99b1-88eb4aa342b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219746243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.219746243
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1397748288
Short name T354
Test name
Test status
Simulation time 225503916668 ps
CPU time 204.94 seconds
Started Mar 28 12:58:34 PM PDT 24
Finished Mar 28 01:01:59 PM PDT 24
Peak memory 190768 kb
Host smart-2b399a8e-d295-4e36-948f-47fc9f6151d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397748288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1397748288
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1133567993
Short name T251
Test name
Test status
Simulation time 304508165865 ps
CPU time 150.22 seconds
Started Mar 28 12:58:34 PM PDT 24
Finished Mar 28 01:01:04 PM PDT 24
Peak memory 190912 kb
Host smart-a11e3741-98c4-4676-851d-4df8a13f7727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133567993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1133567993
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4259704906
Short name T350
Test name
Test status
Simulation time 90577130824 ps
CPU time 216.03 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:02:28 PM PDT 24
Peak memory 190672 kb
Host smart-32c4abee-9a83-45cf-82dd-3ceb60191ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259704906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4259704906
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.846604609
Short name T247
Test name
Test status
Simulation time 4397139906 ps
CPU time 46.75 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 12:59:40 PM PDT 24
Peak memory 182708 kb
Host smart-a6a24800-fd81-41fc-8633-74604b8342ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846604609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.846604609
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1717835176
Short name T164
Test name
Test status
Simulation time 73122334981 ps
CPU time 107.95 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:00:40 PM PDT 24
Peak memory 190892 kb
Host smart-e4921a85-bf57-4ebf-ab1b-74a142203b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717835176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1717835176
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4117919861
Short name T289
Test name
Test status
Simulation time 181608771131 ps
CPU time 268.03 seconds
Started Mar 28 12:58:54 PM PDT 24
Finished Mar 28 01:03:22 PM PDT 24
Peak memory 190892 kb
Host smart-90c550cc-51ee-49a7-a7b7-cf3bb22d686e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117919861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4117919861
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3407101132
Short name T149
Test name
Test status
Simulation time 458308632103 ps
CPU time 260.97 seconds
Started Mar 28 12:58:51 PM PDT 24
Finished Mar 28 01:03:12 PM PDT 24
Peak memory 194392 kb
Host smart-3164a224-1e73-4a7f-9bfd-8d69729e387e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407101132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3407101132
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.3324910055
Short name T133
Test name
Test status
Simulation time 212414883944 ps
CPU time 55.78 seconds
Started Mar 28 12:58:51 PM PDT 24
Finished Mar 28 12:59:47 PM PDT 24
Peak memory 194476 kb
Host smart-c12be8ba-23b8-4f34-8c67-36040f54acc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324910055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3324910055
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3416037192
Short name T302
Test name
Test status
Simulation time 120103356394 ps
CPU time 68.23 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 01:00:21 PM PDT 24
Peak memory 190852 kb
Host smart-527abc9a-a6ec-435d-aeca-85c3b8a1e579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416037192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3416037192
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2153407964
Short name T253
Test name
Test status
Simulation time 90562547486 ps
CPU time 138.97 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 01:01:32 PM PDT 24
Peak memory 194404 kb
Host smart-1831c7ed-935d-43c5-934b-3d330abd0ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153407964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2153407964
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.4062319980
Short name T135
Test name
Test status
Simulation time 65124957631 ps
CPU time 762.36 seconds
Started Mar 28 12:59:11 PM PDT 24
Finished Mar 28 01:11:53 PM PDT 24
Peak memory 190856 kb
Host smart-1fe0dc5d-7a43-4f04-bad2-6d41931e11b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062319980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.4062319980
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1480489936
Short name T327
Test name
Test status
Simulation time 407287296295 ps
CPU time 613.39 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:08:11 PM PDT 24
Peak memory 182684 kb
Host smart-e19c120b-7351-48ea-92e8-f4c27a94e8f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480489936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1480489936
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1204462903
Short name T306
Test name
Test status
Simulation time 394286548203 ps
CPU time 377.52 seconds
Started Mar 28 12:57:59 PM PDT 24
Finished Mar 28 01:04:17 PM PDT 24
Peak memory 182648 kb
Host smart-295e136d-1e51-4b68-8cc9-c47986b33075
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204462903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1204462903
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.1383039497
Short name T198
Test name
Test status
Simulation time 174643460763 ps
CPU time 155.94 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 01:00:36 PM PDT 24
Peak memory 182716 kb
Host smart-b378fa7b-9cff-4a99-a2b8-c83c474d5e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383039497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1383039497
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3232955636
Short name T236
Test name
Test status
Simulation time 384795162222 ps
CPU time 671.15 seconds
Started Mar 28 12:57:56 PM PDT 24
Finished Mar 28 01:09:08 PM PDT 24
Peak memory 182716 kb
Host smart-95499014-4dd8-4e86-a6f0-d624c50ddab5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232955636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3232955636
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.449971122
Short name T192
Test name
Test status
Simulation time 165001327274 ps
CPU time 346.78 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:03:48 PM PDT 24
Peak memory 190892 kb
Host smart-ac6e4b85-5658-4655-9941-724b0c27735b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449971122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
449971122
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1694335498
Short name T338
Test name
Test status
Simulation time 1410120004729 ps
CPU time 688.56 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 01:09:42 PM PDT 24
Peak memory 182732 kb
Host smart-22253052-55c8-4d71-8cd4-c138058bc75f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694335498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1694335498
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3334086355
Short name T54
Test name
Test status
Simulation time 57778204337 ps
CPU time 452.94 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:05:49 PM PDT 24
Peak memory 205556 kb
Host smart-be4c10d8-7e60-47d5-920c-1d011fdfb853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334086355 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3334086355
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1905349360
Short name T229
Test name
Test status
Simulation time 676628821471 ps
CPU time 2269.13 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:36:04 PM PDT 24
Peak memory 194488 kb
Host smart-6a664893-0fac-4145-9efe-bf6e2f55744e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905349360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1905349360
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/62.rv_timer_random.1731289591
Short name T146
Test name
Test status
Simulation time 730599352928 ps
CPU time 624.96 seconds
Started Mar 28 12:58:24 PM PDT 24
Finished Mar 28 01:08:49 PM PDT 24
Peak memory 190880 kb
Host smart-6a4f5e9f-45b8-412f-b783-383a67665f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731289591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1731289591
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2192021133
Short name T226
Test name
Test status
Simulation time 41397239497 ps
CPU time 69.42 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:59:32 PM PDT 24
Peak memory 190680 kb
Host smart-17cf8875-a1b8-4c4d-b9b2-3bf8e9a72f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192021133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2192021133
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3598065834
Short name T278
Test name
Test status
Simulation time 104782540524 ps
CPU time 711.91 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:10:25 PM PDT 24
Peak memory 190764 kb
Host smart-3067497f-5304-495a-ab7a-ac3aa1dc9e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598065834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3598065834
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2456755534
Short name T533
Test name
Test status
Simulation time 32640056 ps
CPU time 0.82 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 182612 kb
Host smart-54a7e7d1-7fde-4868-b966-5df884c5a884
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456755534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2456755534
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3665586131
Short name T35
Test name
Test status
Simulation time 35836638 ps
CPU time 1.44 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 192756 kb
Host smart-3dda2c5d-d327-4f63-a9a3-d3caab709dbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665586131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3665586131
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2059163157
Short name T560
Test name
Test status
Simulation time 48935155 ps
CPU time 0.58 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 182244 kb
Host smart-a2474cf9-c5c8-4ec1-b7c1-0d172e035e7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059163157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2059163157
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.26789835
Short name T569
Test name
Test status
Simulation time 305776394 ps
CPU time 0.92 seconds
Started Mar 28 12:30:51 PM PDT 24
Finished Mar 28 12:30:52 PM PDT 24
Peak memory 197304 kb
Host smart-8b032d85-a60c-4994-b036-e78af1331129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26789835 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.26789835
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3759625672
Short name T101
Test name
Test status
Simulation time 36408722 ps
CPU time 0.56 seconds
Started Mar 28 12:30:57 PM PDT 24
Finished Mar 28 12:30:58 PM PDT 24
Peak memory 182668 kb
Host smart-beeb262e-dbfa-426d-82c0-da3f7a9c8199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759625672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3759625672
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3407808592
Short name T568
Test name
Test status
Simulation time 40819038 ps
CPU time 0.57 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 181548 kb
Host smart-dbe4c4cf-5aa5-4464-b806-e4f8f2d70a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407808592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3407808592
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1237803895
Short name T518
Test name
Test status
Simulation time 35916942 ps
CPU time 0.62 seconds
Started Mar 28 12:30:56 PM PDT 24
Finished Mar 28 12:30:57 PM PDT 24
Peak memory 191832 kb
Host smart-aa58f0cd-2ff4-4189-b4de-1278d69aef99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237803895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1237803895
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1930592914
Short name T485
Test name
Test status
Simulation time 551846430 ps
CPU time 2.74 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 197512 kb
Host smart-b5e99082-b0cc-466d-8959-437982d7f7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930592914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1930592914
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.762036370
Short name T142
Test name
Test status
Simulation time 232452099 ps
CPU time 0.85 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 193244 kb
Host smart-19e67ab1-911a-4c83-9a11-c53378d902c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762036370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.762036370
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3375189047
Short name T113
Test name
Test status
Simulation time 94353904 ps
CPU time 0.73 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 191884 kb
Host smart-2b677fe4-362a-471f-8f35-6fd16cc147d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375189047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3375189047
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2059341512
Short name T541
Test name
Test status
Simulation time 553570650 ps
CPU time 3.66 seconds
Started Mar 28 12:30:50 PM PDT 24
Finished Mar 28 12:30:54 PM PDT 24
Peak memory 191052 kb
Host smart-c8b5e59a-d09e-46fb-8601-9c32f6254b62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059341512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2059341512
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3262588585
Short name T111
Test name
Test status
Simulation time 55825659 ps
CPU time 0.57 seconds
Started Mar 28 12:30:53 PM PDT 24
Finished Mar 28 12:30:54 PM PDT 24
Peak memory 182608 kb
Host smart-dcc467e5-85d9-4020-b512-f4d7c0781083
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262588585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3262588585
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.836430087
Short name T461
Test name
Test status
Simulation time 22913663 ps
CPU time 0.71 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 194856 kb
Host smart-7cc75856-de36-49f1-9127-e0b1ca195a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836430087 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.836430087
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3446017373
Short name T484
Test name
Test status
Simulation time 11839213 ps
CPU time 0.54 seconds
Started Mar 28 12:30:46 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 182428 kb
Host smart-13d365fe-7730-4698-be6f-0f7aeb164c48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446017373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3446017373
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4275617049
Short name T571
Test name
Test status
Simulation time 15189984 ps
CPU time 0.58 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 182564 kb
Host smart-2f09feb7-caa6-4bdb-bf72-62cb2f84201b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275617049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4275617049
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.170537533
Short name T570
Test name
Test status
Simulation time 20032087 ps
CPU time 0.64 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 191864 kb
Host smart-a1a982cb-56f3-4e7e-81db-f217b27afbce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170537533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.170537533
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.220992851
Short name T579
Test name
Test status
Simulation time 461059276 ps
CPU time 2.58 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 197480 kb
Host smart-e8994c0e-e80a-4613-9ade-de5c6aafe2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220992851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.220992851
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.656586139
Short name T550
Test name
Test status
Simulation time 39929131 ps
CPU time 1.68 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 197588 kb
Host smart-ac549b04-4e8f-40b9-8bb7-1dafd2170ad5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656586139 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.656586139
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1599976323
Short name T577
Test name
Test status
Simulation time 15397746 ps
CPU time 0.58 seconds
Started Mar 28 12:30:39 PM PDT 24
Finished Mar 28 12:30:40 PM PDT 24
Peak memory 182612 kb
Host smart-1955ddab-b57c-46cf-b196-32fd8f05155f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599976323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1599976323
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1189370676
Short name T459
Test name
Test status
Simulation time 15378273 ps
CPU time 0.6 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 182536 kb
Host smart-c052d299-5663-4c8d-994f-71ee5151b20f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189370676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1189370676
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1500132445
Short name T506
Test name
Test status
Simulation time 144704774 ps
CPU time 2.59 seconds
Started Mar 28 12:31:02 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 197532 kb
Host smart-483f5991-a288-4de8-a62f-97a91534fcce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500132445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1500132445
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1409717769
Short name T33
Test name
Test status
Simulation time 253528076 ps
CPU time 1.1 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:52 PM PDT 24
Peak memory 195224 kb
Host smart-99ccc459-574f-4cb2-91dc-58887c6c0595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409717769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1409717769
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.512263351
Short name T480
Test name
Test status
Simulation time 30458716 ps
CPU time 0.87 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 197264 kb
Host smart-709d4ffd-244a-46d7-b36d-f78c3978defe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512263351 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.512263351
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3995225642
Short name T56
Test name
Test status
Simulation time 32702409 ps
CPU time 0.59 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 182592 kb
Host smart-2a5d39ff-38d9-410c-943d-c466c380065f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995225642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3995225642
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2969223643
Short name T458
Test name
Test status
Simulation time 57116964 ps
CPU time 0.54 seconds
Started Mar 28 12:30:48 PM PDT 24
Finished Mar 28 12:30:48 PM PDT 24
Peak memory 182560 kb
Host smart-eab548db-9a97-40b6-bf57-8353772fc613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969223643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2969223643
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.385927547
Short name T122
Test name
Test status
Simulation time 30621010 ps
CPU time 0.68 seconds
Started Mar 28 12:30:58 PM PDT 24
Finished Mar 28 12:30:58 PM PDT 24
Peak memory 191664 kb
Host smart-1bdc7e9c-9eaf-4768-b9cd-2427df99905d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385927547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.385927547
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3396686244
Short name T545
Test name
Test status
Simulation time 1326381887 ps
CPU time 2.34 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:46 PM PDT 24
Peak memory 197492 kb
Host smart-7a098e24-6745-4b35-8f8a-ee35374688dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396686244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3396686244
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2572635960
Short name T567
Test name
Test status
Simulation time 193559191 ps
CPU time 0.85 seconds
Started Mar 28 12:31:10 PM PDT 24
Finished Mar 28 12:31:11 PM PDT 24
Peak memory 193200 kb
Host smart-a9d841e9-2375-4a42-801d-e6ceb39c6bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572635960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2572635960
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2523325813
Short name T543
Test name
Test status
Simulation time 25167029 ps
CPU time 0.73 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 195596 kb
Host smart-58603156-0649-4e95-aa0f-73b20dcfb276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523325813 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2523325813
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1569033093
Short name T530
Test name
Test status
Simulation time 39692659 ps
CPU time 0.53 seconds
Started Mar 28 12:31:02 PM PDT 24
Finished Mar 28 12:31:02 PM PDT 24
Peak memory 182288 kb
Host smart-515763a8-169b-4437-ad3f-6127bb86c9d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569033093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1569033093
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3807111154
Short name T469
Test name
Test status
Simulation time 23647608 ps
CPU time 0.53 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:01 PM PDT 24
Peak memory 182464 kb
Host smart-b9c20985-5e65-491f-b1c2-3f309e965e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807111154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3807111154
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.133999701
Short name T513
Test name
Test status
Simulation time 90464592 ps
CPU time 0.71 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 192336 kb
Host smart-08b10dd9-c426-4697-9dd2-4c2445611290
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133999701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.133999701
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1561269049
Short name T575
Test name
Test status
Simulation time 43740537 ps
CPU time 1.97 seconds
Started Mar 28 12:30:58 PM PDT 24
Finished Mar 28 12:31:00 PM PDT 24
Peak memory 191056 kb
Host smart-8b0e9c64-9d9f-4aa7-8866-3455dd9ce83a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561269049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1561269049
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3590260517
Short name T528
Test name
Test status
Simulation time 196575434 ps
CPU time 1.12 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:02 PM PDT 24
Peak memory 195156 kb
Host smart-174d8466-b3e0-4ccc-b610-2158bd2261d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590260517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3590260517
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3818224696
Short name T55
Test name
Test status
Simulation time 157421238 ps
CPU time 0.69 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 194528 kb
Host smart-e5dcff48-b623-4af6-9956-3905e8a74084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818224696 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3818224696
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1397123743
Short name T116
Test name
Test status
Simulation time 28640494 ps
CPU time 0.55 seconds
Started Mar 28 12:30:54 PM PDT 24
Finished Mar 28 12:30:55 PM PDT 24
Peak memory 182664 kb
Host smart-da3ef1ec-7d8f-4aed-bba3-1f7be630e72f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397123743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1397123743
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1636026654
Short name T481
Test name
Test status
Simulation time 14109838 ps
CPU time 0.55 seconds
Started Mar 28 12:31:11 PM PDT 24
Finished Mar 28 12:31:12 PM PDT 24
Peak memory 182508 kb
Host smart-3612a13d-8f0e-44f5-865f-27395de89467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636026654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1636026654
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1253720469
Short name T561
Test name
Test status
Simulation time 18508800 ps
CPU time 0.69 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:46 PM PDT 24
Peak memory 192220 kb
Host smart-cc961cc5-999f-4752-9993-5b430705cffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253720469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1253720469
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3308307810
Short name T70
Test name
Test status
Simulation time 313762590 ps
CPU time 1.18 seconds
Started Mar 28 12:30:56 PM PDT 24
Finished Mar 28 12:30:58 PM PDT 24
Peak memory 195792 kb
Host smart-2b0bd20e-abe0-4f40-bf29-0df2001ceee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308307810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3308307810
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1795686682
Short name T523
Test name
Test status
Simulation time 408782400 ps
CPU time 0.84 seconds
Started Mar 28 12:30:48 PM PDT 24
Finished Mar 28 12:30:48 PM PDT 24
Peak memory 193196 kb
Host smart-4949ae34-51a2-47e2-b7aa-5d5ff5e3a6fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795686682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1795686682
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2454648802
Short name T551
Test name
Test status
Simulation time 34990232 ps
CPU time 0.89 seconds
Started Mar 28 12:30:46 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 197360 kb
Host smart-09bc8a4c-da74-4526-ab7d-880cca723a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454648802 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2454648802
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.444210868
Short name T537
Test name
Test status
Simulation time 42431081 ps
CPU time 0.53 seconds
Started Mar 28 12:30:47 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 181952 kb
Host smart-d8529a3d-65d6-4773-a985-84044f0ec448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444210868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.444210868
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1254915230
Short name T100
Test name
Test status
Simulation time 282492478 ps
CPU time 0.76 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 191668 kb
Host smart-edb83eb9-7663-4a9f-b691-70d07b54c31b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254915230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1254915230
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2980374437
Short name T510
Test name
Test status
Simulation time 199968412 ps
CPU time 1.73 seconds
Started Mar 28 12:30:47 PM PDT 24
Finished Mar 28 12:30:54 PM PDT 24
Peak memory 197676 kb
Host smart-7c8d7c2c-d049-4005-ba3a-e0b1bca65c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980374437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2980374437
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.967652065
Short name T539
Test name
Test status
Simulation time 60505105 ps
CPU time 0.8 seconds
Started Mar 28 12:30:53 PM PDT 24
Finished Mar 28 12:30:54 PM PDT 24
Peak memory 193596 kb
Host smart-e3c736c4-770e-4110-8265-87e9ba0ed63f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967652065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.967652065
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2347444437
Short name T580
Test name
Test status
Simulation time 37922185 ps
CPU time 0.99 seconds
Started Mar 28 12:30:46 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 196780 kb
Host smart-7c823ff4-ddf9-48aa-b687-9ae6eb24faf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347444437 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2347444437
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1739332207
Short name T493
Test name
Test status
Simulation time 82630320 ps
CPU time 0.56 seconds
Started Mar 28 12:30:44 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 182604 kb
Host smart-53360d80-d23b-4ae5-a039-40b2cc512129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739332207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1739332207
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.239243482
Short name T538
Test name
Test status
Simulation time 13011183 ps
CPU time 0.54 seconds
Started Mar 28 12:31:05 PM PDT 24
Finished Mar 28 12:31:06 PM PDT 24
Peak memory 182484 kb
Host smart-7e79981f-fab3-4062-8dcb-7be1cec3bd3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239243482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.239243482
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2479585967
Short name T126
Test name
Test status
Simulation time 79808081 ps
CPU time 0.65 seconds
Started Mar 28 12:31:12 PM PDT 24
Finished Mar 28 12:31:13 PM PDT 24
Peak memory 191896 kb
Host smart-ba46394c-92f3-4494-827e-33658e5529b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479585967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2479585967
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.480248268
Short name T529
Test name
Test status
Simulation time 243116615 ps
CPU time 1.35 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 197432 kb
Host smart-1a1ac10e-bdbc-44b0-9fb2-0bca879e4e00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480248268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.480248268
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1563778303
Short name T141
Test name
Test status
Simulation time 49353533 ps
CPU time 0.81 seconds
Started Mar 28 12:30:52 PM PDT 24
Finished Mar 28 12:30:53 PM PDT 24
Peak memory 193860 kb
Host smart-8447f33d-3f1d-4dac-84e6-ed7fc9ae2c44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563778303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1563778303
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.562741440
Short name T479
Test name
Test status
Simulation time 37108129 ps
CPU time 0.65 seconds
Started Mar 28 12:31:06 PM PDT 24
Finished Mar 28 12:31:07 PM PDT 24
Peak memory 193888 kb
Host smart-9db62e5d-671d-494e-9fe5-d2e697eb8d33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562741440 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.562741440
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.469093003
Short name T500
Test name
Test status
Simulation time 17598575 ps
CPU time 0.57 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:41 PM PDT 24
Peak memory 182600 kb
Host smart-041073e0-35a9-4649-b966-812c5fc25716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469093003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.469093003
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2777933981
Short name T489
Test name
Test status
Simulation time 21557673 ps
CPU time 0.58 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:03 PM PDT 24
Peak memory 182516 kb
Host smart-7e1a3286-a9fc-40ab-81a3-c731744f0a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777933981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2777933981
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2817839200
Short name T532
Test name
Test status
Simulation time 54911408 ps
CPU time 0.73 seconds
Started Mar 28 12:30:52 PM PDT 24
Finished Mar 28 12:30:52 PM PDT 24
Peak memory 193220 kb
Host smart-a60cdaf3-0ec9-47d7-9415-4017345dca8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817839200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2817839200
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.406967038
Short name T536
Test name
Test status
Simulation time 582346483 ps
CPU time 2.72 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:48 PM PDT 24
Peak memory 197500 kb
Host smart-d7a580e5-d782-4ce8-9734-47015bc4aff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406967038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.406967038
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1372786634
Short name T527
Test name
Test status
Simulation time 292962190 ps
CPU time 1.13 seconds
Started Mar 28 12:31:04 PM PDT 24
Finished Mar 28 12:31:05 PM PDT 24
Peak memory 195248 kb
Host smart-5562d146-8acb-4ea4-85cc-85df990bf538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372786634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1372786634
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1603091724
Short name T548
Test name
Test status
Simulation time 66046834 ps
CPU time 1.53 seconds
Started Mar 28 12:31:12 PM PDT 24
Finished Mar 28 12:31:14 PM PDT 24
Peak memory 197288 kb
Host smart-fa958aed-993b-40a7-89c8-acf371f77c2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603091724 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1603091724
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1909732827
Short name T117
Test name
Test status
Simulation time 19119009 ps
CPU time 0.55 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:01 PM PDT 24
Peak memory 182324 kb
Host smart-51030294-1714-482d-bbfb-edd6cc17d566
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909732827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1909732827
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3214280871
Short name T497
Test name
Test status
Simulation time 13198073 ps
CPU time 0.57 seconds
Started Mar 28 12:31:09 PM PDT 24
Finished Mar 28 12:31:10 PM PDT 24
Peak memory 182408 kb
Host smart-029d99e2-ea08-49f1-bfb7-7719f07a9055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214280871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3214280871
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3191862731
Short name T549
Test name
Test status
Simulation time 29824512 ps
CPU time 0.76 seconds
Started Mar 28 12:30:44 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 193296 kb
Host smart-ab823b2c-77a1-43b7-8702-3d5c5ca2d305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191862731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3191862731
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3292709743
Short name T547
Test name
Test status
Simulation time 46343663 ps
CPU time 2.31 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:05 PM PDT 24
Peak memory 197520 kb
Host smart-4e6edfc0-9d4e-49b7-b2d3-57b820e8d7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292709743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3292709743
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3561972688
Short name T574
Test name
Test status
Simulation time 232617255 ps
CPU time 1.35 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 182080 kb
Host smart-69c4bf23-62dc-4a72-9c1b-c8995cc43bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561972688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3561972688
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4178795020
Short name T464
Test name
Test status
Simulation time 40925557 ps
CPU time 1.01 seconds
Started Mar 28 12:31:07 PM PDT 24
Finished Mar 28 12:31:08 PM PDT 24
Peak memory 196548 kb
Host smart-59ad59cf-8dc4-422b-8c78-84eeea5fb23f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178795020 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4178795020
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2860975199
Short name T118
Test name
Test status
Simulation time 11861596 ps
CPU time 0.6 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 182628 kb
Host smart-7fe2e7ab-d86d-48f7-baa6-453f6629e015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860975199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2860975199
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1097717040
Short name T531
Test name
Test status
Simulation time 18837856 ps
CPU time 0.58 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 182376 kb
Host smart-395b1722-38bf-4580-99f1-265b8f092622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097717040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1097717040
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.716880776
Short name T124
Test name
Test status
Simulation time 56819592 ps
CPU time 0.59 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:41 PM PDT 24
Peak memory 191444 kb
Host smart-03d42d00-5192-4bf7-9356-3842252f1daa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716880776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.716880776
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1989636514
Short name T583
Test name
Test status
Simulation time 1877997027 ps
CPU time 1.8 seconds
Started Mar 28 12:31:09 PM PDT 24
Finished Mar 28 12:31:11 PM PDT 24
Peak memory 197440 kb
Host smart-0dcd435c-595a-414d-9d84-9d02b8069fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989636514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1989636514
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1082890707
Short name T572
Test name
Test status
Simulation time 145162509 ps
CPU time 1.36 seconds
Started Mar 28 12:30:51 PM PDT 24
Finished Mar 28 12:30:52 PM PDT 24
Peak memory 195472 kb
Host smart-03f5da4a-44c9-44ca-9e9e-f297ac5455a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082890707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1082890707
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3822702661
Short name T477
Test name
Test status
Simulation time 60891470 ps
CPU time 0.7 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 194340 kb
Host smart-46b770b0-b2c2-4954-a3e4-70ce52547c2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822702661 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3822702661
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.215001080
Short name T564
Test name
Test status
Simulation time 48956278 ps
CPU time 0.51 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 182624 kb
Host smart-f5b820fb-0101-4aec-adae-e71ef039d6ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215001080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.215001080
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1259670352
Short name T471
Test name
Test status
Simulation time 48374111 ps
CPU time 0.59 seconds
Started Mar 28 12:31:12 PM PDT 24
Finished Mar 28 12:31:13 PM PDT 24
Peak memory 182452 kb
Host smart-428b227b-746a-4b74-bea7-9eca24cf8992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259670352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1259670352
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4183992255
Short name T120
Test name
Test status
Simulation time 26687203 ps
CPU time 0.61 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 191948 kb
Host smart-1b351d5d-56b7-459f-80f3-4faaca49c842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183992255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4183992255
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1184489055
Short name T472
Test name
Test status
Simulation time 618757081 ps
CPU time 1.33 seconds
Started Mar 28 12:31:06 PM PDT 24
Finished Mar 28 12:31:08 PM PDT 24
Peak memory 197332 kb
Host smart-f0958c00-95a2-4d8a-82be-d0f35d2a6460
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184489055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1184489055
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2433482468
Short name T34
Test name
Test status
Simulation time 160560064 ps
CPU time 1.07 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 183320 kb
Host smart-1bc9342c-6407-4f3e-ab39-c67ddf7424a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433482468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2433482468
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.359780384
Short name T540
Test name
Test status
Simulation time 33060647 ps
CPU time 0.79 seconds
Started Mar 28 12:30:51 PM PDT 24
Finished Mar 28 12:30:52 PM PDT 24
Peak memory 192388 kb
Host smart-a340b53d-764e-45f9-b6c8-17c75848b08f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359780384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.359780384
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.702832519
Short name T99
Test name
Test status
Simulation time 566315029 ps
CPU time 2.53 seconds
Started Mar 28 12:30:44 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 190984 kb
Host smart-fe08212e-5e7d-4879-8c79-4b79453f7c2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702832519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.702832519
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1377239821
Short name T462
Test name
Test status
Simulation time 37513976 ps
CPU time 0.54 seconds
Started Mar 28 12:30:44 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 182608 kb
Host smart-88ca6fe9-f659-41a9-84bf-c431fa3e05c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377239821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1377239821
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3590964070
Short name T468
Test name
Test status
Simulation time 94372147 ps
CPU time 0.7 seconds
Started Mar 28 12:30:47 PM PDT 24
Finished Mar 28 12:30:52 PM PDT 24
Peak memory 194292 kb
Host smart-e0e6e276-526f-4d7b-93cc-065a5444794d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590964070 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3590964070
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3916222286
Short name T582
Test name
Test status
Simulation time 13491546 ps
CPU time 0.55 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 182612 kb
Host smart-9640bc73-e02b-48fd-b45d-a75eb9dc5f2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916222286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3916222286
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3298376088
Short name T507
Test name
Test status
Simulation time 40210868 ps
CPU time 0.53 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 181996 kb
Host smart-c589c8ef-b603-49ab-80ab-d15a56b83c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298376088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3298376088
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3375607915
Short name T566
Test name
Test status
Simulation time 45452034 ps
CPU time 0.71 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 190932 kb
Host smart-4c5205d0-5cd1-44e8-81ae-f2517a2b2894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375607915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3375607915
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1685823237
Short name T552
Test name
Test status
Simulation time 61119886 ps
CPU time 1.85 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 197548 kb
Host smart-4f138946-b0c5-4481-a1e7-8fe1a6f457fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685823237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1685823237
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1821075582
Short name T139
Test name
Test status
Simulation time 89882724 ps
CPU time 1.06 seconds
Started Mar 28 12:30:36 PM PDT 24
Finished Mar 28 12:30:37 PM PDT 24
Peak memory 194744 kb
Host smart-4494672d-ef11-417e-a76a-75e4da242fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821075582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1821075582
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.212104309
Short name T473
Test name
Test status
Simulation time 19363470 ps
CPU time 0.57 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 182492 kb
Host smart-0c1b4703-d1f7-432c-b9d4-0cff9f915b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212104309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.212104309
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2139012946
Short name T503
Test name
Test status
Simulation time 23608951 ps
CPU time 0.55 seconds
Started Mar 28 12:31:13 PM PDT 24
Finished Mar 28 12:31:13 PM PDT 24
Peak memory 182496 kb
Host smart-6b24e4da-303a-4c7e-928b-9700214c8185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139012946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2139012946
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.280276235
Short name T508
Test name
Test status
Simulation time 42218743 ps
CPU time 0.54 seconds
Started Mar 28 12:31:05 PM PDT 24
Finished Mar 28 12:31:05 PM PDT 24
Peak memory 182516 kb
Host smart-50be6944-1c0d-493c-b537-d842a5addb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280276235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.280276235
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3125842643
Short name T516
Test name
Test status
Simulation time 24844619 ps
CPU time 0.6 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 182592 kb
Host smart-bc8eb502-f090-43fe-a05a-6ef4f4cb17d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125842643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3125842643
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2490682501
Short name T475
Test name
Test status
Simulation time 16237044 ps
CPU time 0.62 seconds
Started Mar 28 12:31:01 PM PDT 24
Finished Mar 28 12:31:02 PM PDT 24
Peak memory 182452 kb
Host smart-1bbfb476-405b-4ece-bdf3-7d3a709cc732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490682501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2490682501
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3237741233
Short name T486
Test name
Test status
Simulation time 109460733 ps
CPU time 0.52 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:01 PM PDT 24
Peak memory 182012 kb
Host smart-b54cbddf-9033-45ff-a2fa-e045540b24dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237741233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3237741233
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3314646021
Short name T487
Test name
Test status
Simulation time 20216617 ps
CPU time 0.54 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 182468 kb
Host smart-6eead6bd-8964-4b9c-a2a7-c668fe580aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314646021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3314646021
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2109215006
Short name T511
Test name
Test status
Simulation time 19089431 ps
CPU time 0.58 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:15 PM PDT 24
Peak memory 182564 kb
Host smart-b083b984-a2c4-4ab8-aa55-9c1a950e6025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109215006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2109215006
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3207967589
Short name T535
Test name
Test status
Simulation time 80499885 ps
CPU time 0.53 seconds
Started Mar 28 12:31:18 PM PDT 24
Finished Mar 28 12:31:18 PM PDT 24
Peak memory 182168 kb
Host smart-0ff58f40-d5d0-454d-a625-895ed1c2dae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207967589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3207967589
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3516283215
Short name T521
Test name
Test status
Simulation time 70871307 ps
CPU time 0.52 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 181968 kb
Host smart-b643d113-5a79-4b10-b068-c5559e894d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516283215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3516283215
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1800764078
Short name T112
Test name
Test status
Simulation time 117467759 ps
CPU time 0.7 seconds
Started Mar 28 12:30:53 PM PDT 24
Finished Mar 28 12:30:54 PM PDT 24
Peak memory 192428 kb
Host smart-84696524-3e9a-4d69-9715-8c80126f178e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800764078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1800764078
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.770010663
Short name T36
Test name
Test status
Simulation time 1135637758 ps
CPU time 3.72 seconds
Started Mar 28 12:30:55 PM PDT 24
Finished Mar 28 12:30:59 PM PDT 24
Peak memory 191012 kb
Host smart-aae49865-0207-4aa2-846b-bdd3b807dc21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770010663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.770010663
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2409422547
Short name T465
Test name
Test status
Simulation time 65889590 ps
CPU time 0.55 seconds
Started Mar 28 12:30:37 PM PDT 24
Finished Mar 28 12:30:38 PM PDT 24
Peak memory 182604 kb
Host smart-36194459-f790-4ae2-aa32-cd6848c04c9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409422547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2409422547
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3747283231
Short name T483
Test name
Test status
Simulation time 35013208 ps
CPU time 0.85 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 196012 kb
Host smart-5a7667e0-6440-4062-b446-3b9f13901f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747283231 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3747283231
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3481781682
Short name T565
Test name
Test status
Simulation time 12506441 ps
CPU time 0.57 seconds
Started Mar 28 12:30:39 PM PDT 24
Finished Mar 28 12:30:39 PM PDT 24
Peak memory 181968 kb
Host smart-4aef9a26-361c-4e82-af91-4eb364125f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481781682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3481781682
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3708826081
Short name T127
Test name
Test status
Simulation time 52547853 ps
CPU time 0.63 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 191860 kb
Host smart-e76a23b9-4c41-492d-98d9-090187ddc164
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708826081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3708826081
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1356631744
Short name T578
Test name
Test status
Simulation time 105714588 ps
CPU time 2.25 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 197568 kb
Host smart-60c446e6-337f-4d03-9084-bd522b58704d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356631744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1356631744
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2059944431
Short name T499
Test name
Test status
Simulation time 116578334 ps
CPU time 1.33 seconds
Started Mar 28 12:30:59 PM PDT 24
Finished Mar 28 12:31:02 PM PDT 24
Peak memory 195328 kb
Host smart-f4c05f90-1889-41c8-92c8-4e9162a68bed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059944431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2059944431
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1191529569
Short name T557
Test name
Test status
Simulation time 37294077 ps
CPU time 0.58 seconds
Started Mar 28 12:31:02 PM PDT 24
Finished Mar 28 12:31:03 PM PDT 24
Peak memory 182512 kb
Host smart-af2ab647-529b-4af9-ad19-dd4fab3a52bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191529569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1191529569
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1644550345
Short name T496
Test name
Test status
Simulation time 27663421 ps
CPU time 0.56 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 182572 kb
Host smart-b21b03cb-ac0e-422f-bf26-30f34cf649ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644550345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1644550345
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.263965059
Short name T562
Test name
Test status
Simulation time 64806832 ps
CPU time 0.55 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 182012 kb
Host smart-b847e6bb-fff4-439d-a69b-e84aa20e8e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263965059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.263965059
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.900849906
Short name T463
Test name
Test status
Simulation time 15143327 ps
CPU time 0.54 seconds
Started Mar 28 12:31:12 PM PDT 24
Finished Mar 28 12:31:13 PM PDT 24
Peak memory 181576 kb
Host smart-7ca1dba2-e5cf-4c59-a96a-a741a9d8cdd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900849906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.900849906
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2445037854
Short name T556
Test name
Test status
Simulation time 14694045 ps
CPU time 0.56 seconds
Started Mar 28 12:31:07 PM PDT 24
Finished Mar 28 12:31:07 PM PDT 24
Peak memory 182560 kb
Host smart-27d9d7a9-3e10-4d40-8d59-95683c7a62b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445037854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2445037854
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2479859861
Short name T512
Test name
Test status
Simulation time 24440729 ps
CPU time 0.56 seconds
Started Mar 28 12:31:08 PM PDT 24
Finished Mar 28 12:31:09 PM PDT 24
Peak memory 182528 kb
Host smart-5e7aa064-82cc-4184-b2ad-8ee388950b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479859861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2479859861
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.246913604
Short name T474
Test name
Test status
Simulation time 12876367 ps
CPU time 0.53 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 182296 kb
Host smart-e37028f5-12f1-49de-8c72-90c8b15d9140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246913604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.246913604
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1860302643
Short name T524
Test name
Test status
Simulation time 37052992 ps
CPU time 0.58 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:01 PM PDT 24
Peak memory 182232 kb
Host smart-fc585bdd-0a26-47db-8f06-ec579ad642e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860302643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1860302643
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3727483949
Short name T558
Test name
Test status
Simulation time 10562025 ps
CPU time 0.54 seconds
Started Mar 28 12:31:07 PM PDT 24
Finished Mar 28 12:31:07 PM PDT 24
Peak memory 182132 kb
Host smart-5576a788-2bfc-4618-a1d9-1ffc321365aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727483949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3727483949
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3347788720
Short name T504
Test name
Test status
Simulation time 45594034 ps
CPU time 0.55 seconds
Started Mar 28 12:30:46 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 182456 kb
Host smart-443bdadb-053c-4839-bb21-e3d3385f8db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347788720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3347788720
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2605393859
Short name T115
Test name
Test status
Simulation time 38447110 ps
CPU time 0.81 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:46 PM PDT 24
Peak memory 191836 kb
Host smart-538eaaa9-2a19-4574-824b-bb58e2718d13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605393859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2605393859
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4285330605
Short name T559
Test name
Test status
Simulation time 930565407 ps
CPU time 1.55 seconds
Started Mar 28 12:30:32 PM PDT 24
Finished Mar 28 12:30:34 PM PDT 24
Peak memory 191260 kb
Host smart-8cf8af19-aa93-45cb-a7d6-6367a2ba4ab1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285330605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.4285330605
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1190148692
Short name T98
Test name
Test status
Simulation time 31996175 ps
CPU time 0.56 seconds
Started Mar 28 12:30:49 PM PDT 24
Finished Mar 28 12:30:50 PM PDT 24
Peak memory 182600 kb
Host smart-292a8117-f2d0-4a54-ba00-8bbb014c93c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190148692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1190148692
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3884710926
Short name T509
Test name
Test status
Simulation time 77270992 ps
CPU time 0.67 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 193540 kb
Host smart-bb9090bd-98e5-4dbf-af55-009dec9d4adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884710926 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3884710926
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.200301888
Short name T544
Test name
Test status
Simulation time 65406618 ps
CPU time 0.58 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 181556 kb
Host smart-1242c66b-6b58-461f-a527-05c8cc80a2ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200301888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.200301888
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3603778824
Short name T519
Test name
Test status
Simulation time 12803831 ps
CPU time 0.54 seconds
Started Mar 28 12:30:57 PM PDT 24
Finished Mar 28 12:30:58 PM PDT 24
Peak memory 182496 kb
Host smart-e0cc48f3-0c86-4c2f-b5d1-0911b3215bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603778824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3603778824
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.358449004
Short name T555
Test name
Test status
Simulation time 35491111 ps
CPU time 0.84 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 190468 kb
Host smart-4b502225-4acb-439a-a694-770588e4d066
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358449004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.358449004
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3451078428
Short name T470
Test name
Test status
Simulation time 24665702 ps
CPU time 1.18 seconds
Started Mar 28 12:30:39 PM PDT 24
Finished Mar 28 12:30:41 PM PDT 24
Peak memory 197484 kb
Host smart-bb453468-933a-4def-b949-f01e2c5f5298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451078428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3451078428
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2568454833
Short name T488
Test name
Test status
Simulation time 31340155 ps
CPU time 0.55 seconds
Started Mar 28 12:31:04 PM PDT 24
Finished Mar 28 12:31:05 PM PDT 24
Peak memory 181972 kb
Host smart-f63540b3-6e64-4bee-bca3-8125d7c96559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568454833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2568454833
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1265578046
Short name T517
Test name
Test status
Simulation time 48662847 ps
CPU time 0.57 seconds
Started Mar 28 12:31:14 PM PDT 24
Finished Mar 28 12:31:15 PM PDT 24
Peak memory 182564 kb
Host smart-9805ce17-5151-4084-ac6e-a5fdf0ad9556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265578046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1265578046
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1951893052
Short name T494
Test name
Test status
Simulation time 68029039 ps
CPU time 0.54 seconds
Started Mar 28 12:30:56 PM PDT 24
Finished Mar 28 12:30:57 PM PDT 24
Peak memory 181972 kb
Host smart-5fc41e1a-1904-4a87-b705-66c3567dbff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951893052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1951893052
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2144744614
Short name T502
Test name
Test status
Simulation time 25272181 ps
CPU time 0.55 seconds
Started Mar 28 12:31:13 PM PDT 24
Finished Mar 28 12:31:13 PM PDT 24
Peak memory 182620 kb
Host smart-eca10944-b611-4aa4-bfe0-197f846fc05a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144744614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2144744614
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2370611517
Short name T515
Test name
Test status
Simulation time 65583170 ps
CPU time 0.55 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:04 PM PDT 24
Peak memory 182692 kb
Host smart-a9923ec0-5b0b-4572-b17f-e8511e656cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370611517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2370611517
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3290504806
Short name T466
Test name
Test status
Simulation time 34449076 ps
CPU time 0.54 seconds
Started Mar 28 12:30:44 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 182604 kb
Host smart-4bec78bf-ab9a-48cc-a525-42e99f080296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290504806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3290504806
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1891980175
Short name T495
Test name
Test status
Simulation time 51732330 ps
CPU time 0.54 seconds
Started Mar 28 12:30:58 PM PDT 24
Finished Mar 28 12:30:59 PM PDT 24
Peak memory 182500 kb
Host smart-e622f6ea-7ef5-49b6-bf90-1a14075ea48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891980175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1891980175
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.699093813
Short name T492
Test name
Test status
Simulation time 30091324 ps
CPU time 0.58 seconds
Started Mar 28 12:31:08 PM PDT 24
Finished Mar 28 12:31:08 PM PDT 24
Peak memory 181972 kb
Host smart-8976ddad-b291-4551-92cf-ffa71a878d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699093813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.699093813
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.295286532
Short name T498
Test name
Test status
Simulation time 18024421 ps
CPU time 0.57 seconds
Started Mar 28 12:31:05 PM PDT 24
Finished Mar 28 12:31:06 PM PDT 24
Peak memory 182592 kb
Host smart-dd8c2c39-b32b-4aa0-9f1e-e1b71654e75e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295286532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.295286532
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.79845856
Short name T525
Test name
Test status
Simulation time 53035208 ps
CPU time 0.52 seconds
Started Mar 28 12:30:59 PM PDT 24
Finished Mar 28 12:30:59 PM PDT 24
Peak memory 181936 kb
Host smart-034a36ff-547b-4cbf-9188-2cceac296e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79845856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.79845856
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2621728394
Short name T460
Test name
Test status
Simulation time 55020524 ps
CPU time 0.75 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 194696 kb
Host smart-ab549d21-e472-4bb6-b750-bc7ba094a06e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621728394 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2621728394
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1262387935
Short name T520
Test name
Test status
Simulation time 39954016 ps
CPU time 0.58 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 182216 kb
Host smart-14508a6e-c8d9-4ac1-bed5-f835c67f6f97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262387935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1262387935
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1159500705
Short name T491
Test name
Test status
Simulation time 15141707 ps
CPU time 0.55 seconds
Started Mar 28 12:30:51 PM PDT 24
Finished Mar 28 12:30:51 PM PDT 24
Peak memory 182788 kb
Host smart-ba4c8cf2-2c3e-48a9-8c21-08aeac9ca7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159500705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1159500705
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3600300636
Short name T121
Test name
Test status
Simulation time 18340919 ps
CPU time 0.64 seconds
Started Mar 28 12:30:37 PM PDT 24
Finished Mar 28 12:30:38 PM PDT 24
Peak memory 192012 kb
Host smart-8f5af244-d882-474c-928f-aa3d0760f8f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600300636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3600300636
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3810963986
Short name T514
Test name
Test status
Simulation time 452194265 ps
CPU time 2.5 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 196340 kb
Host smart-78e1fcd9-3046-46b5-ad04-db3db389e7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810963986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3810963986
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1586738158
Short name T573
Test name
Test status
Simulation time 99476600 ps
CPU time 1.36 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 195008 kb
Host smart-69b28561-bee8-4066-ba12-687a35506c29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586738158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1586738158
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3476824112
Short name T482
Test name
Test status
Simulation time 89370584 ps
CPU time 1.02 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 197164 kb
Host smart-3ceefea2-baaf-41b2-aabc-ef5ff9cceacd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476824112 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3476824112
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1413416800
Short name T97
Test name
Test status
Simulation time 12471399 ps
CPU time 0.55 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 181476 kb
Host smart-6864a691-2ecb-4fb7-a29c-52cd9112dfc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413416800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1413416800
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4084409264
Short name T581
Test name
Test status
Simulation time 27860041 ps
CPU time 0.54 seconds
Started Mar 28 12:30:46 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 182476 kb
Host smart-d8e1f472-bb59-45b4-956c-63e8b7de7a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084409264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4084409264
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1537850537
Short name T553
Test name
Test status
Simulation time 71765100 ps
CPU time 0.73 seconds
Started Mar 28 12:30:39 PM PDT 24
Finished Mar 28 12:30:40 PM PDT 24
Peak memory 193304 kb
Host smart-b3a9bb92-a863-48eb-b3c4-6d3fb654c68f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537850537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1537850537
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1116845406
Short name T467
Test name
Test status
Simulation time 115823293 ps
CPU time 1.48 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 196284 kb
Host smart-d3aabfdb-3c30-45d9-87c7-25a8becc7b35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116845406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1116845406
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2448737537
Short name T534
Test name
Test status
Simulation time 168053932 ps
CPU time 0.81 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 182908 kb
Host smart-3530ccec-9584-414b-b8b8-0683051d87a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448737537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2448737537
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1455980433
Short name T490
Test name
Test status
Simulation time 52268881 ps
CPU time 1.13 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 197484 kb
Host smart-2423b2d4-8e00-412b-9e21-6223e1812be5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455980433 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1455980433
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.172266070
Short name T119
Test name
Test status
Simulation time 14313177 ps
CPU time 0.57 seconds
Started Mar 28 12:30:49 PM PDT 24
Finished Mar 28 12:30:50 PM PDT 24
Peak memory 182616 kb
Host smart-564a3faf-1814-48f1-8863-f71cf6443df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172266070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.172266070
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1754165431
Short name T501
Test name
Test status
Simulation time 17467328 ps
CPU time 0.51 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:46 PM PDT 24
Peak memory 181968 kb
Host smart-0b6d3b47-2f47-4c1e-b3c6-b9bb59ad910b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754165431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1754165431
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.724016893
Short name T563
Test name
Test status
Simulation time 27113402 ps
CPU time 0.65 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 191272 kb
Host smart-62e8926b-c9a8-4b4a-b7bb-64dc2906ca5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724016893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.724016893
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1413721880
Short name T526
Test name
Test status
Simulation time 153781714 ps
CPU time 2.86 seconds
Started Mar 28 12:30:52 PM PDT 24
Finished Mar 28 12:30:55 PM PDT 24
Peak memory 197496 kb
Host smart-3a20a18b-9929-480f-bc16-161a6c11d07f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413721880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1413721880
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2069626222
Short name T576
Test name
Test status
Simulation time 69657855 ps
CPU time 1.06 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:42 PM PDT 24
Peak memory 194772 kb
Host smart-7d706201-aab5-45c4-9d0c-e8272d1c1f54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069626222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2069626222
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2431853237
Short name T542
Test name
Test status
Simulation time 73471725 ps
CPU time 0.78 seconds
Started Mar 28 12:31:02 PM PDT 24
Finished Mar 28 12:31:03 PM PDT 24
Peak memory 195564 kb
Host smart-0ef677c2-95fb-4716-891c-841951a582f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431853237 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2431853237
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3307721880
Short name T57
Test name
Test status
Simulation time 98234522 ps
CPU time 0.52 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 182320 kb
Host smart-467a1b79-8bce-4548-a242-154022e2689b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307721880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3307721880
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.88270660
Short name T546
Test name
Test status
Simulation time 62700783 ps
CPU time 0.52 seconds
Started Mar 28 12:30:51 PM PDT 24
Finished Mar 28 12:30:51 PM PDT 24
Peak memory 182216 kb
Host smart-4ec2d7e2-352e-4447-bc80-03873deff626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88270660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.88270660
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1510622126
Short name T128
Test name
Test status
Simulation time 156320770 ps
CPU time 0.6 seconds
Started Mar 28 12:30:42 PM PDT 24
Finished Mar 28 12:30:43 PM PDT 24
Peak memory 191952 kb
Host smart-96bb0336-2122-4036-8ee0-08830bbde692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510622126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1510622126
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3305846745
Short name T69
Test name
Test status
Simulation time 622188299 ps
CPU time 2.46 seconds
Started Mar 28 12:30:40 PM PDT 24
Finished Mar 28 12:30:44 PM PDT 24
Peak memory 196488 kb
Host smart-cae68318-25a8-41d0-8ad4-0065566322ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305846745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3305846745
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1835930419
Short name T505
Test name
Test status
Simulation time 307885043 ps
CPU time 1.09 seconds
Started Mar 28 12:31:11 PM PDT 24
Finished Mar 28 12:31:12 PM PDT 24
Peak memory 194964 kb
Host smart-cf53fd31-8f49-4b9f-bc45-e9d0113e8f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835930419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1835930419
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1321561798
Short name T478
Test name
Test status
Simulation time 25767004 ps
CPU time 0.7 seconds
Started Mar 28 12:31:17 PM PDT 24
Finished Mar 28 12:31:18 PM PDT 24
Peak memory 194960 kb
Host smart-f5f59865-7dd1-4d19-a4c0-d943b2c90acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321561798 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1321561798
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1910246417
Short name T114
Test name
Test status
Simulation time 27707433 ps
CPU time 0.57 seconds
Started Mar 28 12:30:50 PM PDT 24
Finished Mar 28 12:30:51 PM PDT 24
Peak memory 182616 kb
Host smart-cb9a51c0-0e74-4f4c-98e1-8e7b34f2b609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910246417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1910246417
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1872305064
Short name T554
Test name
Test status
Simulation time 38915984 ps
CPU time 0.57 seconds
Started Mar 28 12:31:07 PM PDT 24
Finished Mar 28 12:31:08 PM PDT 24
Peak memory 182508 kb
Host smart-2b5096e0-ee04-4770-a6ff-aca23901f0f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872305064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1872305064
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4283157845
Short name T123
Test name
Test status
Simulation time 136984787 ps
CPU time 0.6 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:46 PM PDT 24
Peak memory 191916 kb
Host smart-55169a7c-5238-4f96-bc63-10613cba615a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283157845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.4283157845
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2678035441
Short name T476
Test name
Test status
Simulation time 155238022 ps
CPU time 1.71 seconds
Started Mar 28 12:30:46 PM PDT 24
Finished Mar 28 12:30:53 PM PDT 24
Peak memory 197468 kb
Host smart-1568ba6b-b890-4e1d-a0b3-e4128e740b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678035441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2678035441
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3976211404
Short name T522
Test name
Test status
Simulation time 128481803 ps
CPU time 1.06 seconds
Started Mar 28 12:30:52 PM PDT 24
Finished Mar 28 12:30:53 PM PDT 24
Peak memory 194852 kb
Host smart-7927419e-6ce6-424a-90d0-80c108962294
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976211404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3976211404
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1476331728
Short name T173
Test name
Test status
Simulation time 179339629999 ps
CPU time 323.18 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 01:02:51 PM PDT 24
Peak memory 182636 kb
Host smart-c56e2014-7af3-4c42-a44d-b1e0cba0e3cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476331728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1476331728
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.189218251
Short name T376
Test name
Test status
Simulation time 110612970445 ps
CPU time 157.15 seconds
Started Mar 28 12:57:31 PM PDT 24
Finished Mar 28 01:00:08 PM PDT 24
Peak memory 182692 kb
Host smart-8febc8ab-843a-4e8b-91d4-99929bc82064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189218251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.189218251
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3799216145
Short name T439
Test name
Test status
Simulation time 20784477300 ps
CPU time 12.74 seconds
Started Mar 28 12:57:24 PM PDT 24
Finished Mar 28 12:57:37 PM PDT 24
Peak memory 182688 kb
Host smart-a724fd62-eb70-4e95-b5ab-797a5ef0d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799216145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3799216145
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1384758432
Short name T89
Test name
Test status
Simulation time 576253280727 ps
CPU time 253.85 seconds
Started Mar 28 12:57:29 PM PDT 24
Finished Mar 28 01:01:43 PM PDT 24
Peak memory 190836 kb
Host smart-e20f1d69-b057-4df3-80f2-20013279d60d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384758432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1384758432
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.994585094
Short name T107
Test name
Test status
Simulation time 368668947397 ps
CPU time 346.06 seconds
Started Mar 28 12:57:20 PM PDT 24
Finished Mar 28 01:03:06 PM PDT 24
Peak memory 182600 kb
Host smart-1807f935-991d-4963-828f-da7ab2028656
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994585094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.994585094
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2140417799
Short name T449
Test name
Test status
Simulation time 158900266523 ps
CPU time 103.09 seconds
Started Mar 28 12:57:25 PM PDT 24
Finished Mar 28 12:59:09 PM PDT 24
Peak memory 182680 kb
Host smart-546e40f0-2137-46d7-a158-64f6464a0225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140417799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2140417799
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.232400652
Short name T29
Test name
Test status
Simulation time 81654675917 ps
CPU time 830.51 seconds
Started Mar 28 12:57:21 PM PDT 24
Finished Mar 28 01:11:11 PM PDT 24
Peak memory 182572 kb
Host smart-330fc44a-c06c-4baa-8303-af9acf965701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232400652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.232400652
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1823794352
Short name T222
Test name
Test status
Simulation time 346702511838 ps
CPU time 889.81 seconds
Started Mar 28 12:57:20 PM PDT 24
Finished Mar 28 01:12:10 PM PDT 24
Peak memory 194124 kb
Host smart-f2aa55d3-eed9-470f-9b9e-9c1e9d564727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823794352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1823794352
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.214278943
Short name T21
Test name
Test status
Simulation time 151862665 ps
CPU time 0.74 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 213820 kb
Host smart-50e1f334-0818-496b-b6e9-cef242b577b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214278943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.214278943
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1906999378
Short name T394
Test name
Test status
Simulation time 2498509479551 ps
CPU time 555.87 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 01:06:35 PM PDT 24
Peak memory 191024 kb
Host smart-fc859b5b-c340-4dab-b020-dcd2e2451963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906999378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1906999378
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1335275378
Short name T87
Test name
Test status
Simulation time 32353257786 ps
CPU time 264.46 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 01:01:47 PM PDT 24
Peak memory 205564 kb
Host smart-c0447d69-0db1-48ef-9ab3-1578a9106a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335275378 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1335275378
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.626831096
Short name T235
Test name
Test status
Simulation time 142244882477 ps
CPU time 270.73 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 01:02:12 PM PDT 24
Peak memory 182736 kb
Host smart-ca7ffcaf-2a18-41de-9cf8-e9e7e569f1dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626831096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.626831096
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1262929559
Short name T374
Test name
Test status
Simulation time 353526922425 ps
CPU time 294.75 seconds
Started Mar 28 12:57:46 PM PDT 24
Finished Mar 28 01:02:41 PM PDT 24
Peak memory 182488 kb
Host smart-2fd12938-6be5-4dca-93a5-c890a6db2708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262929559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1262929559
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3682323102
Short name T366
Test name
Test status
Simulation time 35560364232 ps
CPU time 62.51 seconds
Started Mar 28 12:57:48 PM PDT 24
Finished Mar 28 12:58:51 PM PDT 24
Peak memory 182480 kb
Host smart-0d4d2fa7-3945-4186-a77f-2f842cd49290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682323102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3682323102
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2827128017
Short name T110
Test name
Test status
Simulation time 21745889120 ps
CPU time 37.92 seconds
Started Mar 28 12:57:43 PM PDT 24
Finished Mar 28 12:58:21 PM PDT 24
Peak memory 182688 kb
Host smart-643796e6-0618-46a5-9e9d-5318908d8b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827128017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2827128017
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.559052122
Short name T362
Test name
Test status
Simulation time 176439243774 ps
CPU time 183.37 seconds
Started Mar 28 12:58:26 PM PDT 24
Finished Mar 28 01:01:29 PM PDT 24
Peak memory 182708 kb
Host smart-573e1dc3-e14f-4c96-a320-9c5db1346833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559052122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.559052122
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2248836537
Short name T365
Test name
Test status
Simulation time 337157629654 ps
CPU time 284.67 seconds
Started Mar 28 12:58:26 PM PDT 24
Finished Mar 28 01:03:11 PM PDT 24
Peak memory 190892 kb
Host smart-7aa12dfd-6233-46a0-8fca-59e2463fd531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248836537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2248836537
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3571393398
Short name T348
Test name
Test status
Simulation time 260823282180 ps
CPU time 76.94 seconds
Started Mar 28 12:58:24 PM PDT 24
Finished Mar 28 12:59:41 PM PDT 24
Peak memory 190540 kb
Host smart-3f9ad55c-bc8e-4426-86ec-578218712a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571393398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3571393398
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2664211752
Short name T184
Test name
Test status
Simulation time 457530629559 ps
CPU time 2523.19 seconds
Started Mar 28 12:58:25 PM PDT 24
Finished Mar 28 01:40:29 PM PDT 24
Peak memory 190900 kb
Host smart-bec11b3d-8ee0-4149-b392-d0c30641f00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664211752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2664211752
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2202119241
Short name T233
Test name
Test status
Simulation time 470014019877 ps
CPU time 309.29 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 01:03:33 PM PDT 24
Peak memory 193452 kb
Host smart-df43124c-7179-4ca4-9c63-248075ce6989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202119241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2202119241
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1541662009
Short name T234
Test name
Test status
Simulation time 190336400799 ps
CPU time 174.02 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 01:00:35 PM PDT 24
Peak memory 182652 kb
Host smart-ef9d3006-ca32-4a4e-93ef-f58c36780934
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541662009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1541662009
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3289634785
Short name T385
Test name
Test status
Simulation time 258820715230 ps
CPU time 166.46 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 01:00:26 PM PDT 24
Peak memory 182496 kb
Host smart-36423c7d-863a-452d-97b9-afdb87fdc08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289634785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3289634785
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.723210837
Short name T313
Test name
Test status
Simulation time 506731156203 ps
CPU time 274.41 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 01:02:16 PM PDT 24
Peak memory 190916 kb
Host smart-ab9a2084-42ba-4827-a530-62d91d6a3ab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723210837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.723210837
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1237887586
Short name T364
Test name
Test status
Simulation time 2275203225 ps
CPU time 4.83 seconds
Started Mar 28 12:57:39 PM PDT 24
Finished Mar 28 12:57:44 PM PDT 24
Peak memory 181600 kb
Host smart-43bf39f3-b6a6-4422-9d8a-de38d9d86982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237887586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1237887586
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.567241222
Short name T312
Test name
Test status
Simulation time 679108136016 ps
CPU time 1366.73 seconds
Started Mar 28 12:57:38 PM PDT 24
Finished Mar 28 01:20:25 PM PDT 24
Peak memory 190800 kb
Host smart-75108974-4a02-4ab2-a61f-f864cf7a9cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567241222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
567241222
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3224916627
Short name T39
Test name
Test status
Simulation time 42313142730 ps
CPU time 364.15 seconds
Started Mar 28 12:57:35 PM PDT 24
Finished Mar 28 01:03:39 PM PDT 24
Peak memory 205592 kb
Host smart-59651628-35f8-4284-9b53-a086e31486e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224916627 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3224916627
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.2389938729
Short name T290
Test name
Test status
Simulation time 248862177473 ps
CPU time 369.25 seconds
Started Mar 28 12:58:28 PM PDT 24
Finished Mar 28 01:04:37 PM PDT 24
Peak memory 193848 kb
Host smart-f0bdce82-4771-48c2-a634-58a548b6221f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389938729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2389938729
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1812975909
Short name T51
Test name
Test status
Simulation time 13979774800 ps
CPU time 17.75 seconds
Started Mar 28 12:58:27 PM PDT 24
Finished Mar 28 12:58:45 PM PDT 24
Peak memory 182708 kb
Host smart-c70cf3fc-14fe-42b6-9669-1cdf845999cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812975909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1812975909
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2587292062
Short name T257
Test name
Test status
Simulation time 501647760096 ps
CPU time 446.89 seconds
Started Mar 28 12:58:34 PM PDT 24
Finished Mar 28 01:06:01 PM PDT 24
Peak memory 190764 kb
Host smart-5d4a3758-292b-4bd5-b3d4-99ce5a4839fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587292062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2587292062
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.199218886
Short name T13
Test name
Test status
Simulation time 144979342022 ps
CPU time 224.03 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:02:17 PM PDT 24
Peak memory 190772 kb
Host smart-f7abd216-00d0-4aee-b6cb-22f46fb6ce66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199218886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.199218886
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3740012242
Short name T248
Test name
Test status
Simulation time 1238156216174 ps
CPU time 536.33 seconds
Started Mar 28 12:58:30 PM PDT 24
Finished Mar 28 01:07:27 PM PDT 24
Peak memory 190900 kb
Host smart-0393a574-f515-478b-b8c4-655f1baf8440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740012242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3740012242
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.148325249
Short name T216
Test name
Test status
Simulation time 71772434360 ps
CPU time 118.75 seconds
Started Mar 28 12:58:28 PM PDT 24
Finished Mar 28 01:00:27 PM PDT 24
Peak memory 190912 kb
Host smart-82d73110-0dda-4734-8e21-3a733eddcf3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148325249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.148325249
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3266507020
Short name T30
Test name
Test status
Simulation time 386667300772 ps
CPU time 206.53 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:01:11 PM PDT 24
Peak memory 182484 kb
Host smart-b1d9a29c-7bea-468c-bc4d-2befe9d50938
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266507020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3266507020
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3651456095
Short name T379
Test name
Test status
Simulation time 372463203393 ps
CPU time 138.78 seconds
Started Mar 28 12:57:39 PM PDT 24
Finished Mar 28 12:59:58 PM PDT 24
Peak memory 182596 kb
Host smart-d75fa14b-cbb2-4c65-a370-af7ea405f439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651456095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3651456095
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.919856482
Short name T7
Test name
Test status
Simulation time 680926616948 ps
CPU time 404.29 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 01:04:25 PM PDT 24
Peak memory 193256 kb
Host smart-6dd97c9f-9a07-408a-b105-763bd3cb85b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919856482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.919856482
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1105585439
Short name T369
Test name
Test status
Simulation time 178990691 ps
CPU time 1.45 seconds
Started Mar 28 12:57:38 PM PDT 24
Finished Mar 28 12:57:39 PM PDT 24
Peak memory 190812 kb
Host smart-1de6f576-78d3-49c6-ad12-48752c76f479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105585439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1105585439
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1727651056
Short name T308
Test name
Test status
Simulation time 884825374428 ps
CPU time 319.63 seconds
Started Mar 28 12:57:30 PM PDT 24
Finished Mar 28 01:02:50 PM PDT 24
Peak memory 190904 kb
Host smart-cbdd2cd1-4302-4778-ad81-74a4108e1c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727651056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1727651056
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3788057832
Short name T138
Test name
Test status
Simulation time 83156795684 ps
CPU time 289.41 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 01:02:30 PM PDT 24
Peak memory 206540 kb
Host smart-aed8f3dc-8f71-427b-9323-3d5a16956dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788057832 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3788057832
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3984775622
Short name T24
Test name
Test status
Simulation time 82718455976 ps
CPU time 387.86 seconds
Started Mar 28 12:58:32 PM PDT 24
Finished Mar 28 01:05:00 PM PDT 24
Peak memory 190764 kb
Host smart-3b6f634f-c567-4470-9c66-4390bb12ccc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984775622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3984775622
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3475456801
Short name T152
Test name
Test status
Simulation time 119935622471 ps
CPU time 165.94 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:01:19 PM PDT 24
Peak memory 190772 kb
Host smart-e5a4d5b9-bf96-4208-9a11-f42f67fba674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475456801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3475456801
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3769502610
Short name T343
Test name
Test status
Simulation time 129715455083 ps
CPU time 213.18 seconds
Started Mar 28 12:58:34 PM PDT 24
Finished Mar 28 01:02:07 PM PDT 24
Peak memory 190764 kb
Host smart-670d1921-945e-4f58-8bf1-ddd0a2fffdea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769502610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3769502610
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1342621240
Short name T346
Test name
Test status
Simulation time 66146314664 ps
CPU time 212.38 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:02:05 PM PDT 24
Peak memory 190772 kb
Host smart-01992e72-9c28-4ab4-bcf4-8260ec5becba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342621240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1342621240
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1830241400
Short name T25
Test name
Test status
Simulation time 100782872133 ps
CPU time 52.16 seconds
Started Mar 28 12:58:28 PM PDT 24
Finished Mar 28 12:59:20 PM PDT 24
Peak memory 190920 kb
Host smart-05bc2193-aff6-41cb-b1b8-713e6625c48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830241400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1830241400
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2125877725
Short name T109
Test name
Test status
Simulation time 24304390788 ps
CPU time 37.87 seconds
Started Mar 28 12:58:25 PM PDT 24
Finished Mar 28 12:59:03 PM PDT 24
Peak memory 190892 kb
Host smart-588fc5fd-644f-4d9a-aeb0-35e6b3a8e122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125877725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2125877725
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.322168391
Short name T390
Test name
Test status
Simulation time 167219316667 ps
CPU time 92.16 seconds
Started Mar 28 12:58:26 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 182704 kb
Host smart-0545ff42-3d05-4050-99a8-de9b3a8fec34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322168391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.322168391
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1862232589
Short name T440
Test name
Test status
Simulation time 71665258180 ps
CPU time 130.9 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 12:59:51 PM PDT 24
Peak memory 182496 kb
Host smart-d75447c8-1252-425d-9bb4-2cf1b2b045a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862232589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1862232589
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3093380568
Short name T388
Test name
Test status
Simulation time 42459616184 ps
CPU time 69.11 seconds
Started Mar 28 12:57:29 PM PDT 24
Finished Mar 28 12:58:38 PM PDT 24
Peak memory 182712 kb
Host smart-a2d6079b-700e-4c93-9471-dc9167fa77ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093380568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3093380568
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.216081094
Short name T324
Test name
Test status
Simulation time 163423139481 ps
CPU time 535.35 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 01:06:36 PM PDT 24
Peak memory 190680 kb
Host smart-91ce9cfb-77db-4c33-84c9-75d5e6e05365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216081094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.216081094
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.582213720
Short name T301
Test name
Test status
Simulation time 23516028313 ps
CPU time 38.04 seconds
Started Mar 28 12:57:31 PM PDT 24
Finished Mar 28 12:58:09 PM PDT 24
Peak memory 190888 kb
Host smart-363dcc7f-a3ac-48ea-b405-074b376b3552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582213720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.582213720
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.2426044029
Short name T291
Test name
Test status
Simulation time 395810218448 ps
CPU time 561.65 seconds
Started Mar 28 12:58:34 PM PDT 24
Finished Mar 28 01:07:55 PM PDT 24
Peak memory 190756 kb
Host smart-5093af9a-4db6-4000-9e5e-6be1e31a8ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426044029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2426044029
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.669756851
Short name T344
Test name
Test status
Simulation time 49232918082 ps
CPU time 158.37 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:01:12 PM PDT 24
Peak memory 190960 kb
Host smart-3cc950ca-0922-4f32-9f35-9f2f9f581853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669756851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.669756851
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.679272102
Short name T256
Test name
Test status
Simulation time 62938627159 ps
CPU time 93.21 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:00:06 PM PDT 24
Peak memory 182700 kb
Host smart-a5df04c5-bc4d-4bfa-ae91-fa40434e0c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679272102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.679272102
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1641089089
Short name T210
Test name
Test status
Simulation time 78510844382 ps
CPU time 45.68 seconds
Started Mar 28 12:58:37 PM PDT 24
Finished Mar 28 12:59:22 PM PDT 24
Peak memory 190900 kb
Host smart-485d9bc9-ad2e-49d5-9f34-a1d53e2b33d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641089089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1641089089
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.373913470
Short name T197
Test name
Test status
Simulation time 406261865768 ps
CPU time 108.88 seconds
Started Mar 28 12:58:42 PM PDT 24
Finished Mar 28 01:00:31 PM PDT 24
Peak memory 193228 kb
Host smart-194f63b8-686a-4fa0-bab1-80e5570688d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373913470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.373913470
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3285855536
Short name T179
Test name
Test status
Simulation time 176031095521 ps
CPU time 807.53 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 01:12:03 PM PDT 24
Peak memory 190828 kb
Host smart-1dacd396-ab59-4fc2-997d-ef12ea5c400a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285855536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3285855536
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.355925454
Short name T273
Test name
Test status
Simulation time 377108443658 ps
CPU time 627.62 seconds
Started Mar 28 12:57:38 PM PDT 24
Finished Mar 28 01:08:06 PM PDT 24
Peak memory 182628 kb
Host smart-3f037e8c-0088-44e6-938a-2bd93d97a63a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355925454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.355925454
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3023929619
Short name T372
Test name
Test status
Simulation time 197210054869 ps
CPU time 231.09 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 01:01:32 PM PDT 24
Peak memory 182380 kb
Host smart-96e19441-3914-4d02-9fbe-b262cb25a1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023929619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3023929619
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.143439833
Short name T318
Test name
Test status
Simulation time 58673500575 ps
CPU time 1701.16 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 01:26:02 PM PDT 24
Peak memory 182476 kb
Host smart-6d056734-642d-4a56-ad5b-eb0b75a10c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143439833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.143439833
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.2031894020
Short name T84
Test name
Test status
Simulation time 150855070902 ps
CPU time 423.46 seconds
Started Mar 28 12:58:32 PM PDT 24
Finished Mar 28 01:05:36 PM PDT 24
Peak memory 194500 kb
Host smart-baee4f60-576a-4840-8151-5ac1ac637646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031894020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2031894020
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2360001788
Short name T180
Test name
Test status
Simulation time 647933498206 ps
CPU time 402.72 seconds
Started Mar 28 12:58:34 PM PDT 24
Finished Mar 28 01:05:17 PM PDT 24
Peak memory 190756 kb
Host smart-450b5b29-4e18-4872-ad8f-eced6a4f391a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360001788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2360001788
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.4264333127
Short name T168
Test name
Test status
Simulation time 176220918099 ps
CPU time 375.54 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 01:04:51 PM PDT 24
Peak memory 190908 kb
Host smart-53c65475-a152-457d-ab65-dcb8cb7cae4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264333127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.4264333127
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.579579380
Short name T23
Test name
Test status
Simulation time 343185953271 ps
CPU time 370.4 seconds
Started Mar 28 12:58:42 PM PDT 24
Finished Mar 28 01:04:52 PM PDT 24
Peak memory 192980 kb
Host smart-72072559-680e-432c-8780-d2ab36f99322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579579380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.579579380
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.954485944
Short name T329
Test name
Test status
Simulation time 122276956621 ps
CPU time 406.25 seconds
Started Mar 28 12:58:42 PM PDT 24
Finished Mar 28 01:05:28 PM PDT 24
Peak memory 190904 kb
Host smart-62edf9a1-bd03-414f-8ac3-9a12261ad3fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954485944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.954485944
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2705441658
Short name T347
Test name
Test status
Simulation time 36785478503 ps
CPU time 58.59 seconds
Started Mar 28 12:58:43 PM PDT 24
Finished Mar 28 12:59:42 PM PDT 24
Peak memory 190892 kb
Host smart-aaacfec3-d79b-4fde-99f8-cd6085f98e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705441658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2705441658
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1639242578
Short name T271
Test name
Test status
Simulation time 55097409350 ps
CPU time 445.31 seconds
Started Mar 28 12:58:43 PM PDT 24
Finished Mar 28 01:06:08 PM PDT 24
Peak memory 190904 kb
Host smart-5fbba960-100d-491a-ae50-d11e0e2dcdf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639242578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1639242578
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2475029510
Short name T367
Test name
Test status
Simulation time 17114769244 ps
CPU time 16.8 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 12:58:01 PM PDT 24
Peak memory 182400 kb
Host smart-7484a424-1d39-409c-92f6-69335b35e58c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475029510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2475029510
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1577738415
Short name T430
Test name
Test status
Simulation time 37728945743 ps
CPU time 55.07 seconds
Started Mar 28 12:57:42 PM PDT 24
Finished Mar 28 12:58:37 PM PDT 24
Peak memory 182708 kb
Host smart-88223c90-d7e3-4599-9890-fb60561d1fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577738415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1577738415
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3322136310
Short name T340
Test name
Test status
Simulation time 108112189343 ps
CPU time 168.28 seconds
Started Mar 28 12:57:39 PM PDT 24
Finished Mar 28 01:00:27 PM PDT 24
Peak memory 190476 kb
Host smart-8c9e4965-12e0-4184-bb58-40570c295a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322136310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3322136310
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3442798632
Short name T436
Test name
Test status
Simulation time 1078829814 ps
CPU time 0.95 seconds
Started Mar 28 12:57:47 PM PDT 24
Finished Mar 28 12:57:48 PM PDT 24
Peak memory 182480 kb
Host smart-dc2d2d5f-5078-4a6b-bf0b-978d00dbb4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442798632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3442798632
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.1665574232
Short name T224
Test name
Test status
Simulation time 171020470649 ps
CPU time 792.55 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 01:11:48 PM PDT 24
Peak memory 190700 kb
Host smart-9a2ccb98-d0e3-478a-aa0f-b26ee8cddc83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665574232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1665574232
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3166426773
Short name T191
Test name
Test status
Simulation time 441428678000 ps
CPU time 484.76 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 01:06:40 PM PDT 24
Peak memory 190904 kb
Host smart-4518d1d6-2af4-4ddf-86d8-fc4b286ff176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166426773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3166426773
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3645418788
Short name T339
Test name
Test status
Simulation time 90704583923 ps
CPU time 72.87 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 12:59:48 PM PDT 24
Peak memory 190848 kb
Host smart-3fe0f814-0ebe-43bd-a9f5-4653d5629c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645418788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3645418788
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3363031476
Short name T130
Test name
Test status
Simulation time 203742847248 ps
CPU time 91.18 seconds
Started Mar 28 12:58:34 PM PDT 24
Finished Mar 28 01:00:06 PM PDT 24
Peak memory 190768 kb
Host smart-55f03300-025f-4db6-874c-bfbadf426ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363031476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3363031476
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.388326122
Short name T265
Test name
Test status
Simulation time 238047719646 ps
CPU time 317.4 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 01:03:53 PM PDT 24
Peak memory 190480 kb
Host smart-b0b6c6b7-855c-4a68-bc55-d8dec8a21dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388326122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.388326122
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3007346840
Short name T205
Test name
Test status
Simulation time 126784498482 ps
CPU time 139.02 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 01:00:54 PM PDT 24
Peak memory 190556 kb
Host smart-c904e64a-bcc0-4b0b-8a33-b83234476dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007346840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3007346840
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2014328986
Short name T335
Test name
Test status
Simulation time 117060427751 ps
CPU time 48.79 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 12:58:30 PM PDT 24
Peak memory 182740 kb
Host smart-45fa1ab7-f81d-47cd-a6ef-269700619e33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014328986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2014328986
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2153386177
Short name T431
Test name
Test status
Simulation time 331116387853 ps
CPU time 119.69 seconds
Started Mar 28 12:57:39 PM PDT 24
Finished Mar 28 12:59:39 PM PDT 24
Peak memory 182632 kb
Host smart-8c8c6107-9158-4902-a2a2-ab88cb847525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153386177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2153386177
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.466318092
Short name T65
Test name
Test status
Simulation time 1742903900350 ps
CPU time 1792.48 seconds
Started Mar 28 12:57:42 PM PDT 24
Finished Mar 28 01:27:35 PM PDT 24
Peak memory 190896 kb
Host smart-0d013570-5250-4ebd-8c1a-cf8e704d2c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466318092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.466318092
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1090132985
Short name T444
Test name
Test status
Simulation time 181317661522 ps
CPU time 66.72 seconds
Started Mar 28 12:57:39 PM PDT 24
Finished Mar 28 12:58:45 PM PDT 24
Peak memory 193988 kb
Host smart-6e19e39d-19cf-4018-aef4-82aacc1ca23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090132985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1090132985
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3900079418
Short name T383
Test name
Test status
Simulation time 1101688752583 ps
CPU time 531.48 seconds
Started Mar 28 12:57:46 PM PDT 24
Finished Mar 28 01:06:37 PM PDT 24
Peak memory 190908 kb
Host smart-74ee4601-3da4-4d93-9bbe-cb304ff2e55a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900079418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3900079418
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.200324042
Short name T215
Test name
Test status
Simulation time 90919198664 ps
CPU time 148.34 seconds
Started Mar 28 12:58:31 PM PDT 24
Finished Mar 28 01:01:00 PM PDT 24
Peak memory 190912 kb
Host smart-1aa07279-5daa-448f-9008-fbbce8599024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200324042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.200324042
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1835972407
Short name T328
Test name
Test status
Simulation time 514905771091 ps
CPU time 292.06 seconds
Started Mar 28 12:58:32 PM PDT 24
Finished Mar 28 01:03:24 PM PDT 24
Peak memory 190904 kb
Host smart-731f989f-7908-498a-9ee6-3fc052c94bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835972407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1835972407
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3896327477
Short name T90
Test name
Test status
Simulation time 40933749344 ps
CPU time 59.8 seconds
Started Mar 28 12:58:35 PM PDT 24
Finished Mar 28 12:59:35 PM PDT 24
Peak memory 182552 kb
Host smart-66d224b2-d30d-457e-abc8-ac464e92e517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896327477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3896327477
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.819942030
Short name T225
Test name
Test status
Simulation time 71192290498 ps
CPU time 179.93 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:01:52 PM PDT 24
Peak memory 182632 kb
Host smart-02ca909c-d4cf-4fa0-bc21-91f55829d775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819942030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.819942030
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3066246295
Short name T10
Test name
Test status
Simulation time 40947727217 ps
CPU time 69.39 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:00:02 PM PDT 24
Peak memory 191304 kb
Host smart-15d97e5c-3054-4ae6-b08a-d4c5008cf9f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066246295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3066246295
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1990670681
Short name T214
Test name
Test status
Simulation time 46220556721 ps
CPU time 132.44 seconds
Started Mar 28 12:58:55 PM PDT 24
Finished Mar 28 01:01:07 PM PDT 24
Peak memory 190852 kb
Host smart-ad303354-fbc9-4ded-8250-07ede20b5d2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990670681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1990670681
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3206305056
Short name T450
Test name
Test status
Simulation time 65343483705 ps
CPU time 36.31 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 12:58:18 PM PDT 24
Peak memory 182760 kb
Host smart-a1bb2e8a-cce6-4aad-8e2c-e4218266375e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206305056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3206305056
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3487183038
Short name T408
Test name
Test status
Simulation time 442149085479 ps
CPU time 196.83 seconds
Started Mar 28 12:57:52 PM PDT 24
Finished Mar 28 01:01:09 PM PDT 24
Peak memory 182588 kb
Host smart-52565209-90fa-427c-8ec7-8ebd4d67d250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487183038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3487183038
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1819111731
Short name T202
Test name
Test status
Simulation time 549782837542 ps
CPU time 1294.18 seconds
Started Mar 28 12:57:54 PM PDT 24
Finished Mar 28 01:19:29 PM PDT 24
Peak memory 190916 kb
Host smart-f5233007-ad5a-4980-948b-42fcbbaaae56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819111731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1819111731
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1160977244
Short name T244
Test name
Test status
Simulation time 129301753569 ps
CPU time 364.2 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 01:04:57 PM PDT 24
Peak memory 190916 kb
Host smart-1c661c34-fcfb-4827-b064-bed4429154ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160977244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1160977244
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3113138637
Short name T352
Test name
Test status
Simulation time 191918560782 ps
CPU time 282.3 seconds
Started Mar 28 12:58:54 PM PDT 24
Finished Mar 28 01:03:36 PM PDT 24
Peak memory 190908 kb
Host smart-f17530e5-84ca-44d8-b333-d13dba2bfd82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113138637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3113138637
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2273134432
Short name T237
Test name
Test status
Simulation time 58549471172 ps
CPU time 82.95 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:00:15 PM PDT 24
Peak memory 194412 kb
Host smart-8f987689-9cb4-4cfa-b005-1d85fb98391d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273134432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2273134432
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3507822680
Short name T433
Test name
Test status
Simulation time 319445561989 ps
CPU time 127.32 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 01:01:01 PM PDT 24
Peak memory 190908 kb
Host smart-fb473f97-ad95-4546-8892-8137b3da23fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507822680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3507822680
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2795571539
Short name T281
Test name
Test status
Simulation time 871485464553 ps
CPU time 1031.94 seconds
Started Mar 28 12:58:54 PM PDT 24
Finished Mar 28 01:16:06 PM PDT 24
Peak memory 190904 kb
Host smart-a62dc0f0-d8c2-4a00-ac31-7a00718677be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795571539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2795571539
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2192831222
Short name T358
Test name
Test status
Simulation time 429510347820 ps
CPU time 228.15 seconds
Started Mar 28 12:58:54 PM PDT 24
Finished Mar 28 01:02:42 PM PDT 24
Peak memory 190956 kb
Host smart-2af5e4bf-066a-4c86-9fb8-74c1ed654627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192831222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2192831222
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3902817742
Short name T102
Test name
Test status
Simulation time 89124086603 ps
CPU time 17.95 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 12:58:02 PM PDT 24
Peak memory 182656 kb
Host smart-3d95f7ae-e5b5-44f4-9ca9-8598f6f4fc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902817742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3902817742
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2534036069
Short name T355
Test name
Test status
Simulation time 93960437646 ps
CPU time 109.32 seconds
Started Mar 28 12:57:50 PM PDT 24
Finished Mar 28 12:59:40 PM PDT 24
Peak memory 182700 kb
Host smart-15330434-6c69-407b-903d-729c97ce2398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534036069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2534036069
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2431289874
Short name T183
Test name
Test status
Simulation time 114031668632 ps
CPU time 74.35 seconds
Started Mar 28 12:57:45 PM PDT 24
Finished Mar 28 12:59:00 PM PDT 24
Peak memory 190800 kb
Host smart-e8ac5812-4511-4cc6-9921-68be654c2e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431289874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2431289874
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4118529483
Short name T181
Test name
Test status
Simulation time 653639145962 ps
CPU time 1316.1 seconds
Started Mar 28 12:57:43 PM PDT 24
Finished Mar 28 01:19:39 PM PDT 24
Peak memory 190768 kb
Host smart-d5e63402-a54d-4bac-85da-f31e51d907f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118529483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4118529483
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.2210322992
Short name T453
Test name
Test status
Simulation time 12645720752 ps
CPU time 29.79 seconds
Started Mar 28 12:58:54 PM PDT 24
Finished Mar 28 12:59:24 PM PDT 24
Peak memory 182696 kb
Host smart-818a3bb4-bc18-443b-b4cf-385359795366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210322992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2210322992
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1266768647
Short name T221
Test name
Test status
Simulation time 779724741503 ps
CPU time 1742.35 seconds
Started Mar 28 12:58:50 PM PDT 24
Finished Mar 28 01:27:53 PM PDT 24
Peak memory 190812 kb
Host smart-585891dc-18cd-4817-869a-88376b522775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266768647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1266768647
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1517859653
Short name T217
Test name
Test status
Simulation time 157417494420 ps
CPU time 319.92 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 01:04:13 PM PDT 24
Peak memory 190904 kb
Host smart-c921cb8e-62fd-4868-abb9-778ebf56cc1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517859653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1517859653
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.454763070
Short name T246
Test name
Test status
Simulation time 475103965136 ps
CPU time 259.55 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:03:11 PM PDT 24
Peak memory 190776 kb
Host smart-36b97775-541e-4df5-9f3d-47af15ab006a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454763070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.454763070
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2485313586
Short name T263
Test name
Test status
Simulation time 27328543567 ps
CPU time 279.12 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 01:03:32 PM PDT 24
Peak memory 193072 kb
Host smart-0ebdd5f9-2531-48ee-abe8-218a89ab864e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485313586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2485313586
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.4167278525
Short name T255
Test name
Test status
Simulation time 146259860330 ps
CPU time 298.63 seconds
Started Mar 28 12:58:53 PM PDT 24
Finished Mar 28 01:03:52 PM PDT 24
Peak memory 194492 kb
Host smart-ce75c2a8-d73e-4939-9680-bed3dc2c3d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167278525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4167278525
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.143221097
Short name T134
Test name
Test status
Simulation time 355999856738 ps
CPU time 134.47 seconds
Started Mar 28 12:58:51 PM PDT 24
Finished Mar 28 01:01:06 PM PDT 24
Peak memory 194240 kb
Host smart-dd101a17-60a2-4465-90be-227591148d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143221097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.143221097
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3069111482
Short name T295
Test name
Test status
Simulation time 172507497828 ps
CPU time 2103.17 seconds
Started Mar 28 12:58:52 PM PDT 24
Finished Mar 28 01:33:55 PM PDT 24
Peak memory 192940 kb
Host smart-06a0b769-c3bb-4f30-998c-99c513198a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069111482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3069111482
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3437150944
Short name T187
Test name
Test status
Simulation time 633137116208 ps
CPU time 408.13 seconds
Started Mar 28 12:57:48 PM PDT 24
Finished Mar 28 01:04:36 PM PDT 24
Peak memory 182720 kb
Host smart-36df7765-6548-4745-b2a9-ffd9021ef86b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437150944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3437150944
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3829232726
Short name T377
Test name
Test status
Simulation time 385962578657 ps
CPU time 65.19 seconds
Started Mar 28 12:57:48 PM PDT 24
Finished Mar 28 12:58:53 PM PDT 24
Peak memory 182632 kb
Host smart-c7dd3688-a453-41da-8b0b-de6f5cf44ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829232726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3829232726
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3604378121
Short name T285
Test name
Test status
Simulation time 610042092432 ps
CPU time 336.16 seconds
Started Mar 28 12:57:49 PM PDT 24
Finished Mar 28 01:03:26 PM PDT 24
Peak memory 190832 kb
Host smart-0ca32fd0-244f-42ab-80ba-5b6260a2b7e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604378121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3604378121
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2428452163
Short name T443
Test name
Test status
Simulation time 328175500607 ps
CPU time 275.85 seconds
Started Mar 28 12:57:43 PM PDT 24
Finished Mar 28 01:02:19 PM PDT 24
Peak memory 182572 kb
Host smart-77610d9e-3b7d-4359-a53e-22f503188655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428452163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2428452163
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3729743338
Short name T41
Test name
Test status
Simulation time 20494338145 ps
CPU time 80.67 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 12:59:02 PM PDT 24
Peak memory 197348 kb
Host smart-bfe19788-6904-437c-9851-24afbb5a92ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729743338 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3729743338
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.2614393753
Short name T190
Test name
Test status
Simulation time 392742234543 ps
CPU time 506.94 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 01:07:40 PM PDT 24
Peak memory 190884 kb
Host smart-84b17089-31b8-408b-a6eb-717e953fc7f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614393753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2614393753
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3441593731
Short name T231
Test name
Test status
Simulation time 995939842777 ps
CPU time 738.16 seconds
Started Mar 28 12:59:14 PM PDT 24
Finished Mar 28 01:11:32 PM PDT 24
Peak memory 190884 kb
Host smart-d57b282e-9a3a-4d4f-a0d8-cf2beb0b5a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441593731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3441593731
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.400025710
Short name T270
Test name
Test status
Simulation time 405446766524 ps
CPU time 1826.07 seconds
Started Mar 28 12:59:07 PM PDT 24
Finished Mar 28 01:29:34 PM PDT 24
Peak memory 190768 kb
Host smart-0fcdefcb-82b8-4895-9682-f77fd795dac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400025710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.400025710
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2846786222
Short name T245
Test name
Test status
Simulation time 107082776392 ps
CPU time 474 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 01:07:07 PM PDT 24
Peak memory 190880 kb
Host smart-861ab3d7-a7b4-4c94-9475-5bf802a60a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846786222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2846786222
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3420855323
Short name T435
Test name
Test status
Simulation time 499048276831 ps
CPU time 278.57 seconds
Started Mar 28 12:57:20 PM PDT 24
Finished Mar 28 01:01:59 PM PDT 24
Peak memory 182724 kb
Host smart-81a0531f-8b0e-454d-bf99-e77aa24bd8cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420855323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3420855323
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1931553008
Short name T371
Test name
Test status
Simulation time 357725893619 ps
CPU time 141.06 seconds
Started Mar 28 12:57:24 PM PDT 24
Finished Mar 28 12:59:46 PM PDT 24
Peak memory 182680 kb
Host smart-af5d5c60-14c5-461f-9c54-242e3a1ac377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931553008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1931553008
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.952385004
Short name T333
Test name
Test status
Simulation time 1501249823605 ps
CPU time 1642.04 seconds
Started Mar 28 12:57:21 PM PDT 24
Finished Mar 28 01:24:44 PM PDT 24
Peak memory 193456 kb
Host smart-e8670fab-0db2-4c7d-9e9d-a3c492177bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952385004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.952385004
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1344666698
Short name T363
Test name
Test status
Simulation time 33344889305 ps
CPU time 15.08 seconds
Started Mar 28 12:57:24 PM PDT 24
Finished Mar 28 12:57:39 PM PDT 24
Peak memory 194560 kb
Host smart-ad6b92c1-763b-471b-8b67-af86abed004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344666698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1344666698
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.822802085
Short name T18
Test name
Test status
Simulation time 253625172 ps
CPU time 0.82 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 213292 kb
Host smart-30967c38-4b2f-4fad-87ee-21b78f4b963f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822802085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.822802085
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1682357697
Short name T230
Test name
Test status
Simulation time 370865553928 ps
CPU time 906.86 seconds
Started Mar 28 12:57:24 PM PDT 24
Finished Mar 28 01:12:31 PM PDT 24
Peak memory 195244 kb
Host smart-1373f3b0-8ec8-441e-b93c-680afad3bcf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682357697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1682357697
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3145091281
Short name T157
Test name
Test status
Simulation time 374701403873 ps
CPU time 201.6 seconds
Started Mar 28 12:57:45 PM PDT 24
Finished Mar 28 01:01:06 PM PDT 24
Peak memory 182696 kb
Host smart-a6875077-232f-4df6-a2d6-5078a9979fdf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145091281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3145091281
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2042556333
Short name T403
Test name
Test status
Simulation time 71560973536 ps
CPU time 118.89 seconds
Started Mar 28 12:57:47 PM PDT 24
Finished Mar 28 12:59:46 PM PDT 24
Peak memory 182676 kb
Host smart-b9345d37-78af-49e4-876e-7f84cb54dd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042556333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2042556333
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.401965234
Short name T143
Test name
Test status
Simulation time 123391228900 ps
CPU time 205.95 seconds
Started Mar 28 12:57:42 PM PDT 24
Finished Mar 28 01:01:08 PM PDT 24
Peak memory 190848 kb
Host smart-35c9ecd9-87eb-48b8-b677-87d96401a9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401965234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.401965234
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2421455827
Short name T93
Test name
Test status
Simulation time 215433574557 ps
CPU time 390.17 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:04:14 PM PDT 24
Peak memory 182624 kb
Host smart-5e2765b1-b536-45b0-98d0-8e35d0173692
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421455827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2421455827
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.359457660
Short name T407
Test name
Test status
Simulation time 70334688190 ps
CPU time 56.34 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 12:58:41 PM PDT 24
Peak memory 182560 kb
Host smart-32529c7c-0dd6-42d6-bd07-0e8b00a7fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359457660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.359457660
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1790706253
Short name T150
Test name
Test status
Simulation time 49905610845 ps
CPU time 77.56 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 12:59:02 PM PDT 24
Peak memory 182568 kb
Host smart-a1dc5bb8-dfb3-4855-a7b6-65772a1e94b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790706253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1790706253
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3727188862
Short name T250
Test name
Test status
Simulation time 92134574809 ps
CPU time 39.75 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 12:58:41 PM PDT 24
Peak memory 182688 kb
Host smart-c7378be4-4ace-4d24-afe0-29c1a186378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727188862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3727188862
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.986935250
Short name T105
Test name
Test status
Simulation time 192350672874 ps
CPU time 151.49 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:00:33 PM PDT 24
Peak memory 182708 kb
Host smart-55be986c-a7f7-4026-a829-bb63ea139cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986935250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.986935250
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.958241447
Short name T392
Test name
Test status
Simulation time 32733171688 ps
CPU time 29.1 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 12:58:30 PM PDT 24
Peak memory 190860 kb
Host smart-b34ce585-5016-47a4-9e35-a8a2e7e3af65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958241447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.958241447
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.799905166
Short name T401
Test name
Test status
Simulation time 31967958127 ps
CPU time 60.07 seconds
Started Mar 28 12:58:04 PM PDT 24
Finished Mar 28 12:59:04 PM PDT 24
Peak memory 190780 kb
Host smart-d3ca0b61-482d-46c2-a0c9-8b681590dd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799905166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.799905166
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3684636287
Short name T166
Test name
Test status
Simulation time 177754899003 ps
CPU time 285.76 seconds
Started Mar 28 12:57:58 PM PDT 24
Finished Mar 28 01:02:44 PM PDT 24
Peak memory 182736 kb
Host smart-2dc32ba5-4018-48b7-bb22-1d3d7fa8d436
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684636287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3684636287
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.685694535
Short name T131
Test name
Test status
Simulation time 78830473083 ps
CPU time 125.26 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:00:03 PM PDT 24
Peak memory 182680 kb
Host smart-aee9996a-0548-44b6-8e42-4e844f2f9940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685694535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.685694535
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2060118371
Short name T26
Test name
Test status
Simulation time 1449911961924 ps
CPU time 599.8 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:07:57 PM PDT 24
Peak memory 190836 kb
Host smart-86eba4dd-b85d-4b75-8249-a37c6c35642a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060118371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2060118371
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1325800092
Short name T264
Test name
Test status
Simulation time 188412384892 ps
CPU time 448.64 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 01:05:30 PM PDT 24
Peak memory 190756 kb
Host smart-84e3390d-201e-4d80-b364-e5c08df4284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325800092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1325800092
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.546119154
Short name T83
Test name
Test status
Simulation time 242941061003 ps
CPU time 204.64 seconds
Started Mar 28 12:57:58 PM PDT 24
Finished Mar 28 01:01:23 PM PDT 24
Peak memory 194516 kb
Host smart-c1498d9c-4263-4554-9fb3-a38da628101c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546119154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
546119154
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_random.1317286386
Short name T315
Test name
Test status
Simulation time 266728443799 ps
CPU time 591.95 seconds
Started Mar 28 12:57:57 PM PDT 24
Finished Mar 28 01:07:50 PM PDT 24
Peak memory 190788 kb
Host smart-1907c580-5c64-4f20-a069-c5cbd9803174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317286386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1317286386
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1304700901
Short name T417
Test name
Test status
Simulation time 41542545916 ps
CPU time 63.67 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 12:59:04 PM PDT 24
Peak memory 190840 kb
Host smart-e7794973-2374-4899-b4bb-465267b37462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304700901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1304700901
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1031985206
Short name T356
Test name
Test status
Simulation time 1666716163171 ps
CPU time 943.77 seconds
Started Mar 28 12:57:56 PM PDT 24
Finished Mar 28 01:13:40 PM PDT 24
Peak memory 182736 kb
Host smart-0bfeb823-ea57-4e73-9b32-be9d2356ed5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031985206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1031985206
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.854540129
Short name T81
Test name
Test status
Simulation time 77163648815 ps
CPU time 113.48 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 12:59:53 PM PDT 24
Peak memory 182564 kb
Host smart-ced45715-3cb5-4037-9036-4827c7945ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854540129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.854540129
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.389603268
Short name T409
Test name
Test status
Simulation time 4427565427 ps
CPU time 8.61 seconds
Started Mar 28 12:58:03 PM PDT 24
Finished Mar 28 12:58:12 PM PDT 24
Peak memory 182656 kb
Host smart-c2270a3d-b0f7-47cb-9a0a-a48617b46891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389603268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.389603268
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3183620086
Short name T421
Test name
Test status
Simulation time 1759304492978 ps
CPU time 699.05 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:09:41 PM PDT 24
Peak memory 195396 kb
Host smart-f6aaff49-103e-4ec3-999a-a607f79775b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183620086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3183620086
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1682064608
Short name T321
Test name
Test status
Simulation time 219515318774 ps
CPU time 385.51 seconds
Started Mar 28 12:57:58 PM PDT 24
Finished Mar 28 01:04:24 PM PDT 24
Peak memory 182724 kb
Host smart-49e48bd3-76d7-403d-ba35-14a967d4b417
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682064608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1682064608
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.327434846
Short name T389
Test name
Test status
Simulation time 183212510437 ps
CPU time 157.29 seconds
Started Mar 28 12:58:02 PM PDT 24
Finished Mar 28 01:00:39 PM PDT 24
Peak memory 182684 kb
Host smart-51360b32-05d1-4313-96ed-6de20684256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327434846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.327434846
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2299470178
Short name T103
Test name
Test status
Simulation time 46507729 ps
CPU time 0.64 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 12:58:02 PM PDT 24
Peak memory 182448 kb
Host smart-a34a7ec6-9b09-456c-9de8-faadda8747ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299470178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2299470178
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3045839760
Short name T5
Test name
Test status
Simulation time 451052501373 ps
CPU time 223.45 seconds
Started Mar 28 12:58:03 PM PDT 24
Finished Mar 28 01:01:47 PM PDT 24
Peak memory 182680 kb
Host smart-1138ea18-047c-4339-bdd2-aababd3ea45e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045839760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3045839760
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1462280742
Short name T418
Test name
Test status
Simulation time 30954417224 ps
CPU time 26.16 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 12:58:27 PM PDT 24
Peak memory 182644 kb
Host smart-814fb7d6-0a8c-4210-8ac6-a42cfb7424ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462280742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1462280742
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1113181963
Short name T219
Test name
Test status
Simulation time 90664270312 ps
CPU time 286.05 seconds
Started Mar 28 12:57:56 PM PDT 24
Finished Mar 28 01:02:43 PM PDT 24
Peak memory 190916 kb
Host smart-73c38ff2-139d-4c40-9938-022e6ac4781d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113181963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1113181963
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2976762754
Short name T108
Test name
Test status
Simulation time 295104598042 ps
CPU time 247.82 seconds
Started Mar 28 12:58:02 PM PDT 24
Finished Mar 28 01:02:10 PM PDT 24
Peak memory 182692 kb
Host smart-6af37851-5d8f-48c7-8089-ed1264a6a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976762754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2976762754
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2714920248
Short name T223
Test name
Test status
Simulation time 424571015479 ps
CPU time 318.13 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:03:19 PM PDT 24
Peak memory 194448 kb
Host smart-3136b75d-9a17-4852-a3eb-e429517758b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714920248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2714920248
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1830823687
Short name T420
Test name
Test status
Simulation time 181988560 ps
CPU time 0.67 seconds
Started Mar 28 12:57:58 PM PDT 24
Finished Mar 28 12:57:59 PM PDT 24
Peak memory 182444 kb
Host smart-ba6d2201-8d7d-44cd-a4b4-873e9de04d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830823687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1830823687
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4248429493
Short name T370
Test name
Test status
Simulation time 446614606535 ps
CPU time 120.52 seconds
Started Mar 28 12:57:58 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 182724 kb
Host smart-7a4b2e1a-85e2-46c7-b6ba-a15b59fa1fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248429493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4248429493
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1838223196
Short name T153
Test name
Test status
Simulation time 2800471984307 ps
CPU time 2462.85 seconds
Started Mar 28 12:57:59 PM PDT 24
Finished Mar 28 01:39:02 PM PDT 24
Peak memory 190916 kb
Host smart-2199df24-04fc-44f5-9d7d-ddf10753e1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838223196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1838223196
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.538951263
Short name T375
Test name
Test status
Simulation time 71070186 ps
CPU time 0.65 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 12:58:02 PM PDT 24
Peak memory 182440 kb
Host smart-429bd354-545b-465b-8c07-efb163f21923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538951263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.538951263
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3465975675
Short name T423
Test name
Test status
Simulation time 82099918473 ps
CPU time 37.86 seconds
Started Mar 28 12:57:26 PM PDT 24
Finished Mar 28 12:58:04 PM PDT 24
Peak memory 182708 kb
Host smart-c7c158bd-8985-4e7f-8064-350737d549e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465975675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3465975675
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.4266295222
Short name T424
Test name
Test status
Simulation time 187830577494 ps
CPU time 98.44 seconds
Started Mar 28 12:57:29 PM PDT 24
Finished Mar 28 12:59:08 PM PDT 24
Peak memory 182644 kb
Host smart-80ac3da1-d8b4-4ac3-b448-98e747980017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266295222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4266295222
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2926669698
Short name T442
Test name
Test status
Simulation time 366568852076 ps
CPU time 266.58 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:02:11 PM PDT 24
Peak memory 190888 kb
Host smart-5340e7e5-0641-4956-99c5-17a91f6ad9eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926669698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2926669698
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3192337409
Short name T171
Test name
Test status
Simulation time 4013033746 ps
CPU time 13.19 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 182664 kb
Host smart-af87657a-c9e7-49e5-9073-aef705b66914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192337409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3192337409
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1554585456
Short name T20
Test name
Test status
Simulation time 279907575 ps
CPU time 0.8 seconds
Started Mar 28 12:57:30 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 213132 kb
Host smart-105ba1d1-d13a-492d-9d96-b4c925d39b1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554585456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1554585456
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2684007145
Short name T213
Test name
Test status
Simulation time 2698981122497 ps
CPU time 1544.85 seconds
Started Mar 28 12:57:21 PM PDT 24
Finished Mar 28 01:23:06 PM PDT 24
Peak memory 190840 kb
Host smart-ec087737-b202-472a-aa44-980316cc890d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684007145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2684007145
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1443539793
Short name T203
Test name
Test status
Simulation time 70987458767 ps
CPU time 122.82 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 01:00:03 PM PDT 24
Peak memory 182460 kb
Host smart-dc3b5981-d7f1-45eb-be7f-92f843d35688
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443539793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1443539793
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1891087600
Short name T398
Test name
Test status
Simulation time 36465713200 ps
CPU time 46.71 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 12:58:48 PM PDT 24
Peak memory 182568 kb
Host smart-0a17c06d-b5d4-41ae-ba6f-43bb477a0a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891087600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1891087600
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.307096539
Short name T92
Test name
Test status
Simulation time 219075991 ps
CPU time 0.78 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 12:58:02 PM PDT 24
Peak memory 192260 kb
Host smart-542841a2-84da-48b5-ab5c-2dce17e64b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307096539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.307096539
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2488793541
Short name T177
Test name
Test status
Simulation time 2679546101883 ps
CPU time 1044.58 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 01:15:24 PM PDT 24
Peak memory 190568 kb
Host smart-355bfc2c-c403-4582-bf5d-3f2caa9ad13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488793541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2488793541
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2082187518
Short name T337
Test name
Test status
Simulation time 241904905588 ps
CPU time 413.92 seconds
Started Mar 28 12:58:02 PM PDT 24
Finished Mar 28 01:04:56 PM PDT 24
Peak memory 182724 kb
Host smart-789f925b-8c10-4086-8449-aae713050ed1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082187518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2082187518
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1225635368
Short name T381
Test name
Test status
Simulation time 442593810000 ps
CPU time 176.57 seconds
Started Mar 28 12:57:58 PM PDT 24
Finished Mar 28 01:00:54 PM PDT 24
Peak memory 182708 kb
Host smart-a0352550-d236-47b8-a46d-a00568487962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225635368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1225635368
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1522946897
Short name T368
Test name
Test status
Simulation time 652684315 ps
CPU time 0.89 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 12:58:02 PM PDT 24
Peak memory 182456 kb
Host smart-2434dd1f-ab0b-4c5e-b141-9402a5f0f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522946897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1522946897
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.879613461
Short name T283
Test name
Test status
Simulation time 862833505903 ps
CPU time 613.25 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:08:15 PM PDT 24
Peak memory 190896 kb
Host smart-ca2423d4-63e7-48df-b4d4-4ca57a2da6ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879613461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
879613461
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.3507504207
Short name T96
Test name
Test status
Simulation time 95202049270 ps
CPU time 995.33 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:14:37 PM PDT 24
Peak memory 210972 kb
Host smart-c058f1be-8e10-491a-b6f0-9933e7b3598d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507504207 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.3507504207
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1450677994
Short name T292
Test name
Test status
Simulation time 459226745711 ps
CPU time 233.2 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 01:01:55 PM PDT 24
Peak memory 182700 kb
Host smart-b610af4a-aa3f-4565-b8e9-9456e5372eb2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450677994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1450677994
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.255306241
Short name T425
Test name
Test status
Simulation time 107156273259 ps
CPU time 150.5 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 01:00:31 PM PDT 24
Peak memory 182636 kb
Host smart-b77bd7c9-6eb6-4e22-94b1-73f0abc5b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255306241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.255306241
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1010076346
Short name T422
Test name
Test status
Simulation time 103117226 ps
CPU time 0.71 seconds
Started Mar 28 12:58:01 PM PDT 24
Finished Mar 28 12:58:02 PM PDT 24
Peak memory 182504 kb
Host smart-2b030e5d-122f-4095-8f2d-77cba8dbacd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010076346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1010076346
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.4158502930
Short name T414
Test name
Test status
Simulation time 111355498425 ps
CPU time 94.94 seconds
Started Mar 28 12:57:58 PM PDT 24
Finished Mar 28 12:59:33 PM PDT 24
Peak memory 194756 kb
Host smart-b37b1b1b-888f-4966-8349-b379b5ed2126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158502930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.4158502930
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2323909324
Short name T261
Test name
Test status
Simulation time 5193017825 ps
CPU time 9.22 seconds
Started Mar 28 12:57:59 PM PDT 24
Finished Mar 28 12:58:08 PM PDT 24
Peak memory 182672 kb
Host smart-f4b7b471-1c5e-4b95-9647-b4aa58ebc53b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323909324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2323909324
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3698768138
Short name T79
Test name
Test status
Simulation time 119618280235 ps
CPU time 177.18 seconds
Started Mar 28 12:58:02 PM PDT 24
Finished Mar 28 01:00:59 PM PDT 24
Peak memory 181996 kb
Host smart-5077f495-ee80-492d-aa4c-0d004d0868a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698768138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3698768138
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3543173499
Short name T185
Test name
Test status
Simulation time 44959058109 ps
CPU time 69.53 seconds
Started Mar 28 12:57:59 PM PDT 24
Finished Mar 28 12:59:09 PM PDT 24
Peak memory 193064 kb
Host smart-31cb9016-2047-4e14-b157-959feb382ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543173499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3543173499
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.73659737
Short name T266
Test name
Test status
Simulation time 233762685348 ps
CPU time 384.29 seconds
Started Mar 28 12:58:00 PM PDT 24
Finished Mar 28 01:04:25 PM PDT 24
Peak memory 190796 kb
Host smart-d9b006b7-9a62-402d-9387-ecaf8774e943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73659737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.73659737
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2358312686
Short name T397
Test name
Test status
Simulation time 114643606781 ps
CPU time 30.23 seconds
Started Mar 28 12:58:10 PM PDT 24
Finished Mar 28 12:58:41 PM PDT 24
Peak memory 182768 kb
Host smart-5cb268d8-96d8-4ae8-8679-a04e4ae5b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358312686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2358312686
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.76937458
Short name T293
Test name
Test status
Simulation time 420972277563 ps
CPU time 146.73 seconds
Started Mar 28 12:58:10 PM PDT 24
Finished Mar 28 01:00:37 PM PDT 24
Peak memory 190908 kb
Host smart-59f673db-f259-46c9-839d-e2b363fd5d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76937458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.76937458
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3165372421
Short name T298
Test name
Test status
Simulation time 526220988217 ps
CPU time 962.29 seconds
Started Mar 28 12:58:10 PM PDT 24
Finished Mar 28 01:14:13 PM PDT 24
Peak memory 182724 kb
Host smart-152a2612-8585-4884-8997-868b868d58d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165372421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3165372421
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1557385727
Short name T86
Test name
Test status
Simulation time 582885050201 ps
CPU time 251.39 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 01:02:26 PM PDT 24
Peak memory 182692 kb
Host smart-665ec702-7f0f-4640-bc96-18eba9977288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557385727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1557385727
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1292209133
Short name T384
Test name
Test status
Simulation time 488770887 ps
CPU time 0.68 seconds
Started Mar 28 12:58:20 PM PDT 24
Finished Mar 28 12:58:21 PM PDT 24
Peak memory 182468 kb
Host smart-564cf8bc-2f0e-46ea-a714-8697e6e798d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292209133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1292209133
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.4224273621
Short name T16
Test name
Test status
Simulation time 45512628612 ps
CPU time 42.28 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:58:56 PM PDT 24
Peak memory 197396 kb
Host smart-7b852b95-2642-409d-8325-98ad5b10df3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224273621 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.4224273621
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1437394782
Short name T63
Test name
Test status
Simulation time 479427209221 ps
CPU time 219.89 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:01:55 PM PDT 24
Peak memory 182624 kb
Host smart-30f6d48d-c135-4261-86f6-07d03ff9f529
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437394782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1437394782
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2763916090
Short name T406
Test name
Test status
Simulation time 21086642008 ps
CPU time 32.91 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 12:58:48 PM PDT 24
Peak memory 182656 kb
Host smart-d7027c7b-d3e1-4777-9415-d045f3a42ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763916090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2763916090
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.653491079
Short name T349
Test name
Test status
Simulation time 51367305473 ps
CPU time 82.79 seconds
Started Mar 28 12:58:10 PM PDT 24
Finished Mar 28 12:59:33 PM PDT 24
Peak memory 182688 kb
Host smart-6317d7ff-f8d6-45c7-9454-6d8f858ecc63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653491079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.653491079
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2147852785
Short name T448
Test name
Test status
Simulation time 469172973 ps
CPU time 1.01 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:58:16 PM PDT 24
Peak memory 193064 kb
Host smart-18a6d095-3fd0-44e2-a4f1-7a7461579a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147852785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2147852785
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.133423160
Short name T53
Test name
Test status
Simulation time 79911233235 ps
CPU time 615.2 seconds
Started Mar 28 12:58:13 PM PDT 24
Finished Mar 28 01:08:28 PM PDT 24
Peak memory 212976 kb
Host smart-de5082ad-fc8e-43df-8224-1f2797bcb0eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133423160 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.133423160
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2298254010
Short name T201
Test name
Test status
Simulation time 3728539073494 ps
CPU time 937.97 seconds
Started Mar 28 12:58:12 PM PDT 24
Finished Mar 28 01:13:51 PM PDT 24
Peak memory 182648 kb
Host smart-ed99d131-702c-4a0a-80d6-cd2ae952db72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298254010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2298254010
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2488401187
Short name T426
Test name
Test status
Simulation time 645334594570 ps
CPU time 263.65 seconds
Started Mar 28 12:58:10 PM PDT 24
Finished Mar 28 01:02:34 PM PDT 24
Peak memory 182704 kb
Host smart-37677590-66c3-42e9-bee1-15ea7c7af092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488401187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2488401187
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1120627284
Short name T405
Test name
Test status
Simulation time 25998415578 ps
CPU time 38.03 seconds
Started Mar 28 12:58:08 PM PDT 24
Finished Mar 28 12:58:47 PM PDT 24
Peak memory 193044 kb
Host smart-ce806839-8b80-458a-ad14-34fe6a320698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120627284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1120627284
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.4256827735
Short name T416
Test name
Test status
Simulation time 1092447112 ps
CPU time 0.96 seconds
Started Mar 28 12:58:07 PM PDT 24
Finished Mar 28 12:58:08 PM PDT 24
Peak memory 182552 kb
Host smart-f466b916-1ed0-474c-88ab-8e1538a4f772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256827735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.4256827735
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3800793147
Short name T400
Test name
Test status
Simulation time 16817455547 ps
CPU time 25.24 seconds
Started Mar 28 12:58:09 PM PDT 24
Finished Mar 28 12:58:36 PM PDT 24
Peak memory 182720 kb
Host smart-b753288a-ee94-4386-b0af-8c07579dc310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800793147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3800793147
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3295248418
Short name T288
Test name
Test status
Simulation time 20805188101 ps
CPU time 18.55 seconds
Started Mar 28 12:58:12 PM PDT 24
Finished Mar 28 12:58:30 PM PDT 24
Peak memory 182676 kb
Host smart-778d953d-4068-4451-8af7-6bd822d5fa2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295248418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3295248418
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.679477638
Short name T432
Test name
Test status
Simulation time 109859322920 ps
CPU time 134.06 seconds
Started Mar 28 12:58:11 PM PDT 24
Finished Mar 28 01:00:26 PM PDT 24
Peak memory 182676 kb
Host smart-58b4cbe5-4994-47c8-899f-d98ffb94302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679477638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.679477638
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2852468775
Short name T427
Test name
Test status
Simulation time 369029720726 ps
CPU time 1773.52 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 182576 kb
Host smart-b53f95d8-be56-45b4-95b5-8e6f2b09abdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852468775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2852468775
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4111713526
Short name T445
Test name
Test status
Simulation time 1795068073 ps
CPU time 4.19 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:58:18 PM PDT 24
Peak memory 190784 kb
Host smart-c7565545-84de-49b1-83fd-5c97d0f7d569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111713526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4111713526
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.570112156
Short name T411
Test name
Test status
Simulation time 1242897937732 ps
CPU time 574.8 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:07:50 PM PDT 24
Peak memory 190904 kb
Host smart-d8692912-ad05-42ac-a6df-73d00697ceb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570112156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
570112156
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.4290270092
Short name T360
Test name
Test status
Simulation time 94782277762 ps
CPU time 167.23 seconds
Started Mar 28 12:58:11 PM PDT 24
Finished Mar 28 01:00:59 PM PDT 24
Peak memory 182720 kb
Host smart-e389f098-17b7-4465-b560-39c35023fbcd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290270092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.4290270092
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1742725939
Short name T419
Test name
Test status
Simulation time 154739447057 ps
CPU time 69 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:59:23 PM PDT 24
Peak memory 182704 kb
Host smart-92b70551-96b2-465f-abe6-9ff2d3169ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742725939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1742725939
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3838081660
Short name T314
Test name
Test status
Simulation time 9919425214 ps
CPU time 83.22 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:59:37 PM PDT 24
Peak memory 182704 kb
Host smart-1dd5024a-aa7d-47b3-aef3-cadeb1e25c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838081660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3838081660
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.708980366
Short name T404
Test name
Test status
Simulation time 160279621 ps
CPU time 0.84 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:58:15 PM PDT 24
Peak memory 191192 kb
Host smart-7f1ad078-8abd-4b9f-b9f5-21a518cccb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708980366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.708980366
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1137937383
Short name T59
Test name
Test status
Simulation time 670292444036 ps
CPU time 984.45 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 01:13:52 PM PDT 24
Peak memory 182732 kb
Host smart-30946abf-1877-4277-8946-3db7cb39d119
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137937383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1137937383
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.580981694
Short name T387
Test name
Test status
Simulation time 271261605507 ps
CPU time 113.66 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:59:21 PM PDT 24
Peak memory 182748 kb
Host smart-ad8afc8a-96cd-445e-a159-6faa0548cd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580981694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.580981694
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1821179793
Short name T307
Test name
Test status
Simulation time 182799253334 ps
CPU time 95.47 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:59:03 PM PDT 24
Peak memory 190948 kb
Host smart-242262d1-ac39-4f12-8277-0725e5f5691c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821179793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1821179793
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2141401137
Short name T296
Test name
Test status
Simulation time 168631160596 ps
CPU time 126.57 seconds
Started Mar 28 12:57:26 PM PDT 24
Finished Mar 28 12:59:33 PM PDT 24
Peak memory 190952 kb
Host smart-e12f3ba3-3982-4524-8ad3-39cb3e32708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141401137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2141401137
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4292797646
Short name T22
Test name
Test status
Simulation time 59684383 ps
CPU time 0.73 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 12:57:29 PM PDT 24
Peak memory 213184 kb
Host smart-a8694721-384c-4db2-bb8e-730f9c57f57a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292797646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4292797646
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.789382090
Short name T178
Test name
Test status
Simulation time 1682366398835 ps
CPU time 897.19 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 01:12:25 PM PDT 24
Peak memory 190808 kb
Host smart-6e1d1147-b4f3-4f5b-9635-2d08b5dd6ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789382090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.789382090
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3768746071
Short name T162
Test name
Test status
Simulation time 538141849938 ps
CPU time 519.49 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:06:55 PM PDT 24
Peak memory 182708 kb
Host smart-b1cc1667-6cb6-4fdd-bc6b-504547a403ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768746071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3768746071
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2129197350
Short name T373
Test name
Test status
Simulation time 464322116175 ps
CPU time 144.45 seconds
Started Mar 28 12:58:10 PM PDT 24
Finished Mar 28 01:00:35 PM PDT 24
Peak memory 182768 kb
Host smart-a2af904a-37c5-46f5-bff5-adabfb8dbb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129197350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2129197350
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2306727665
Short name T60
Test name
Test status
Simulation time 176707124682 ps
CPU time 92.64 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 12:59:47 PM PDT 24
Peak memory 190840 kb
Host smart-d06ee3ce-76fa-4d56-9e52-574b9d17de0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306727665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2306727665
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1761424554
Short name T286
Test name
Test status
Simulation time 63054415456 ps
CPU time 139.2 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:00:35 PM PDT 24
Peak memory 182564 kb
Host smart-32ab175b-3365-4247-aaa3-d1fea80d64cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761424554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1761424554
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2605977453
Short name T78
Test name
Test status
Simulation time 311985428191 ps
CPU time 203.02 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 01:01:38 PM PDT 24
Peak memory 195184 kb
Host smart-4f302dfc-25cf-42a9-b9a7-647fafccab9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605977453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2605977453
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3045953486
Short name T284
Test name
Test status
Simulation time 25923155480 ps
CPU time 25.42 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:58:39 PM PDT 24
Peak memory 182648 kb
Host smart-ccac08c8-9047-43c3-8b97-9a470b667bd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045953486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3045953486
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2510784684
Short name T378
Test name
Test status
Simulation time 126825675467 ps
CPU time 183.35 seconds
Started Mar 28 12:58:10 PM PDT 24
Finished Mar 28 01:01:14 PM PDT 24
Peak memory 182672 kb
Host smart-e36f7cdc-563a-41b6-b276-704928ca1e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510784684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2510784684
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1808418404
Short name T359
Test name
Test status
Simulation time 21390560525 ps
CPU time 19.48 seconds
Started Mar 28 12:58:12 PM PDT 24
Finished Mar 28 12:58:31 PM PDT 24
Peak memory 182680 kb
Host smart-2180c8eb-9b63-41ac-b1a5-83f8b4b1787d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808418404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1808418404
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3583895545
Short name T331
Test name
Test status
Simulation time 255278711538 ps
CPU time 131.25 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:00:27 PM PDT 24
Peak memory 194440 kb
Host smart-7f4555f3-49a0-49b4-aeb6-84169cf9f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583895545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3583895545
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1453129288
Short name T75
Test name
Test status
Simulation time 137996228675 ps
CPU time 108.92 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:00:04 PM PDT 24
Peak memory 194456 kb
Host smart-11a33518-3dbc-4672-8953-f2f1aa3cd555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453129288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1453129288
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.325923401
Short name T43
Test name
Test status
Simulation time 67726539223 ps
CPU time 134.44 seconds
Started Mar 28 12:58:12 PM PDT 24
Finished Mar 28 01:00:26 PM PDT 24
Peak memory 197344 kb
Host smart-a6ccfb5f-0051-41d4-a42d-f85a57d73b98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325923401 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.325923401
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3548785483
Short name T300
Test name
Test status
Simulation time 174223162687 ps
CPU time 308.08 seconds
Started Mar 28 12:58:11 PM PDT 24
Finished Mar 28 01:03:20 PM PDT 24
Peak memory 182700 kb
Host smart-0134c493-deb9-48fd-b13e-21b4fc4c3d5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548785483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3548785483
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.70516773
Short name T447
Test name
Test status
Simulation time 791978934234 ps
CPU time 163.76 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:00:59 PM PDT 24
Peak memory 182584 kb
Host smart-418b0dae-644a-4dd6-98de-91dc306fbda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70516773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.70516773
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2195916083
Short name T175
Test name
Test status
Simulation time 763452846396 ps
CPU time 1029.33 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:15:25 PM PDT 24
Peak memory 190848 kb
Host smart-37e4eb68-b762-4ad9-b0c6-ec385f03b250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195916083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2195916083
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3579921910
Short name T212
Test name
Test status
Simulation time 1328031957 ps
CPU time 0.82 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 12:58:15 PM PDT 24
Peak memory 191484 kb
Host smart-e6cd1e61-69d2-4aeb-be75-48e98166e54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579921910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3579921910
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.954898686
Short name T220
Test name
Test status
Simulation time 462922679412 ps
CPU time 762.27 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:10:58 PM PDT 24
Peak memory 190900 kb
Host smart-022ca671-df64-49e7-a2f6-72e86b3d6dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954898686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
954898686
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1974213808
Short name T310
Test name
Test status
Simulation time 5145070753277 ps
CPU time 2719.58 seconds
Started Mar 28 12:58:18 PM PDT 24
Finished Mar 28 01:43:38 PM PDT 24
Peak memory 182684 kb
Host smart-4b9d1d5a-4dd1-447d-b3cc-e9979c8aa769
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974213808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1974213808
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1693236682
Short name T386
Test name
Test status
Simulation time 2503308929 ps
CPU time 1.8 seconds
Started Mar 28 12:58:18 PM PDT 24
Finished Mar 28 12:58:20 PM PDT 24
Peak memory 182552 kb
Host smart-b5f40ccd-c600-4199-a707-c93ec93c8a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693236682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1693236682
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3571349076
Short name T239
Test name
Test status
Simulation time 525831725203 ps
CPU time 671.4 seconds
Started Mar 28 12:58:20 PM PDT 24
Finished Mar 28 01:09:32 PM PDT 24
Peak memory 190880 kb
Host smart-55988e75-abf3-435d-b327-4e817e09e2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571349076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3571349076
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3641061498
Short name T446
Test name
Test status
Simulation time 77593891137 ps
CPU time 49.39 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:59:04 PM PDT 24
Peak memory 182716 kb
Host smart-5d88da35-a757-468d-9f5a-9af31c950109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641061498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3641061498
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.450722941
Short name T199
Test name
Test status
Simulation time 432114365159 ps
CPU time 1470.56 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 01:22:45 PM PDT 24
Peak memory 182568 kb
Host smart-89f06d23-e02a-40e2-b184-8ae8e26e6e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450722941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
450722941
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.4112785883
Short name T17
Test name
Test status
Simulation time 102790321804 ps
CPU time 879.53 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:12:55 PM PDT 24
Peak memory 208088 kb
Host smart-b5e2f84f-0e11-44d1-afa4-ff761c9f555f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112785883 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.4112785883
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1083340204
Short name T438
Test name
Test status
Simulation time 2389301131552 ps
CPU time 1059.61 seconds
Started Mar 28 12:58:20 PM PDT 24
Finished Mar 28 01:16:01 PM PDT 24
Peak memory 182492 kb
Host smart-6f159d5b-e6f9-4979-a4b0-1d389596ff0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083340204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1083340204
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4269772485
Short name T457
Test name
Test status
Simulation time 63710429608 ps
CPU time 95.17 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:59:58 PM PDT 24
Peak memory 182596 kb
Host smart-4e11db41-5d57-4d27-beb5-919fd4eb1d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269772485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4269772485
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1036467328
Short name T434
Test name
Test status
Simulation time 70323216028 ps
CPU time 27.95 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:58:51 PM PDT 24
Peak memory 181708 kb
Host smart-eb64a728-30a8-4eb8-8da3-bd61b4bab5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036467328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1036467328
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3466836339
Short name T382
Test name
Test status
Simulation time 72865079 ps
CPU time 0.53 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 12:58:16 PM PDT 24
Peak memory 182344 kb
Host smart-f6d6f024-7981-4735-9c04-3adda8aa615b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466836339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3466836339
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.939377181
Short name T136
Test name
Test status
Simulation time 455491270735 ps
CPU time 795.3 seconds
Started Mar 28 12:58:17 PM PDT 24
Finished Mar 28 01:11:32 PM PDT 24
Peak memory 182732 kb
Host smart-94b801b5-930e-4097-8fe4-be31b03b89e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939377181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.939377181
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.3976466914
Short name T28
Test name
Test status
Simulation time 137767963567 ps
CPU time 229.69 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 01:02:04 PM PDT 24
Peak memory 193104 kb
Host smart-61ff1b6f-f018-42e0-88ce-577709bea3e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976466914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3976466914
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3828433957
Short name T380
Test name
Test status
Simulation time 28941148135 ps
CPU time 13.67 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:58:36 PM PDT 24
Peak memory 194108 kb
Host smart-8f661d90-ff7a-48ea-a64c-8833137535e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828433957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3828433957
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.368637905
Short name T451
Test name
Test status
Simulation time 2303918824517 ps
CPU time 502.94 seconds
Started Mar 28 12:58:18 PM PDT 24
Finished Mar 28 01:06:41 PM PDT 24
Peak memory 194160 kb
Host smart-18dafce1-4a5b-4283-9e26-38ec8875feb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368637905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
368637905
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1662525646
Short name T345
Test name
Test status
Simulation time 25678248339 ps
CPU time 39.85 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 12:59:03 PM PDT 24
Peak memory 182656 kb
Host smart-fe82ffc3-51e4-465e-b3ad-aa309f44602c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662525646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1662525646
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2246991903
Short name T137
Test name
Test status
Simulation time 69093188271 ps
CPU time 32.21 seconds
Started Mar 28 12:58:17 PM PDT 24
Finished Mar 28 12:58:49 PM PDT 24
Peak memory 182704 kb
Host smart-adb58955-6f99-4d2a-9b15-c6959431f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246991903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2246991903
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1830659242
Short name T282
Test name
Test status
Simulation time 84848387363 ps
CPU time 375.1 seconds
Started Mar 28 12:58:17 PM PDT 24
Finished Mar 28 01:04:32 PM PDT 24
Peak memory 190904 kb
Host smart-679ee336-75ca-4a31-a1c8-df72e62c595c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830659242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1830659242
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2090166034
Short name T415
Test name
Test status
Simulation time 143315841515 ps
CPU time 79.86 seconds
Started Mar 28 12:58:18 PM PDT 24
Finished Mar 28 12:59:38 PM PDT 24
Peak memory 194264 kb
Host smart-6af5fa75-3dbb-4d24-ad33-7a2effd19bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090166034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2090166034
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.457394966
Short name T252
Test name
Test status
Simulation time 245740648052 ps
CPU time 614.85 seconds
Started Mar 28 12:58:17 PM PDT 24
Finished Mar 28 01:08:32 PM PDT 24
Peak memory 190888 kb
Host smart-133dbe72-a221-4e52-b914-3426c2c44214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457394966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
457394966
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2356249873
Short name T161
Test name
Test status
Simulation time 161484166382 ps
CPU time 289.18 seconds
Started Mar 28 12:58:25 PM PDT 24
Finished Mar 28 01:03:15 PM PDT 24
Peak memory 182656 kb
Host smart-1ca0cc88-fa06-417e-a8d1-fd060cd81690
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356249873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2356249873
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.208672666
Short name T3
Test name
Test status
Simulation time 733665262380 ps
CPU time 200.95 seconds
Started Mar 28 12:58:25 PM PDT 24
Finished Mar 28 01:01:46 PM PDT 24
Peak memory 182624 kb
Host smart-16554bca-0d49-4a7a-8263-c5b427ad2150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208672666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.208672666
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.27926545
Short name T207
Test name
Test status
Simulation time 452826584338 ps
CPU time 197.13 seconds
Started Mar 28 12:58:18 PM PDT 24
Finished Mar 28 01:01:35 PM PDT 24
Peak memory 190872 kb
Host smart-1201f662-2b5d-47c3-a494-2aab8d82dad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27926545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.27926545
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1335569538
Short name T429
Test name
Test status
Simulation time 16477121572 ps
CPU time 14.91 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 12:58:38 PM PDT 24
Peak memory 190820 kb
Host smart-2d93e847-876b-4314-b2dc-8ef7a7a0ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335569538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1335569538
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3378908014
Short name T44
Test name
Test status
Simulation time 431249370510 ps
CPU time 690.15 seconds
Started Mar 28 12:58:25 PM PDT 24
Finished Mar 28 01:09:56 PM PDT 24
Peak memory 190840 kb
Host smart-ae315cb7-14db-47a4-8e37-910c6a145f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378908014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3378908014
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.2590908204
Short name T40
Test name
Test status
Simulation time 84883389011 ps
CPU time 752.54 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:10:48 PM PDT 24
Peak memory 205580 kb
Host smart-099dd2fb-369b-42a2-9a0b-5623516b8b7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590908204 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.2590908204
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2158910060
Short name T317
Test name
Test status
Simulation time 381500778042 ps
CPU time 622.65 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 01:08:45 PM PDT 24
Peak memory 182736 kb
Host smart-5bddf8db-4df3-4a60-a30b-6541e3934534
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158910060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2158910060
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3983004343
Short name T456
Test name
Test status
Simulation time 18213297041 ps
CPU time 13.81 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:58:35 PM PDT 24
Peak memory 182704 kb
Host smart-5f263aab-0ede-4af2-b433-28f4e6ae6d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983004343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3983004343
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2460345560
Short name T31
Test name
Test status
Simulation time 222972118441 ps
CPU time 137.13 seconds
Started Mar 28 12:58:18 PM PDT 24
Finished Mar 28 01:00:35 PM PDT 24
Peak memory 190888 kb
Host smart-db57054d-c521-4a9d-9ead-10c3fbaeb200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460345560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2460345560
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2801775746
Short name T437
Test name
Test status
Simulation time 175875912541 ps
CPU time 541.64 seconds
Started Mar 28 12:58:20 PM PDT 24
Finished Mar 28 01:07:23 PM PDT 24
Peak memory 182704 kb
Host smart-21ce1fbe-c8d3-4a74-9582-ce4d6dce547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801775746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2801775746
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2715493557
Short name T336
Test name
Test status
Simulation time 464770834771 ps
CPU time 732.39 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:10:35 PM PDT 24
Peak memory 190908 kb
Host smart-2e6e41c9-7526-4ade-aafb-f2add23848fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715493557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2715493557
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.132541601
Short name T38
Test name
Test status
Simulation time 85588801087 ps
CPU time 327.83 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:03:51 PM PDT 24
Peak memory 205588 kb
Host smart-0b9fd34e-12de-4702-b4b8-4c23b192ca12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132541601 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.132541601
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4262964977
Short name T323
Test name
Test status
Simulation time 24249988148 ps
CPU time 27.1 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:58:50 PM PDT 24
Peak memory 182700 kb
Host smart-88238ccf-fa33-4f17-a296-c964fa3bfd55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262964977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4262964977
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.769671769
Short name T410
Test name
Test status
Simulation time 699869335671 ps
CPU time 303.82 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 01:03:27 PM PDT 24
Peak memory 182692 kb
Host smart-53b2222e-fe2f-40dd-9b40-d33b8bbde678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769671769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.769671769
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1677694964
Short name T64
Test name
Test status
Simulation time 102160434104 ps
CPU time 168.76 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:01:11 PM PDT 24
Peak memory 190868 kb
Host smart-6978b1c9-e76d-4d3e-a0a1-b800e39d457b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677694964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1677694964
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3647364816
Short name T94
Test name
Test status
Simulation time 1540015345 ps
CPU time 4.69 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 12:58:19 PM PDT 24
Peak memory 190712 kb
Host smart-161c1b95-b58a-4791-9e44-7a13516b6d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647364816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3647364816
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1402844580
Short name T1
Test name
Test status
Simulation time 161677531584 ps
CPU time 206.86 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 01:01:51 PM PDT 24
Peak memory 190908 kb
Host smart-bd6f529f-8161-4939-a64c-0f5edb13fd31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402844580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1402844580
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1725604330
Short name T342
Test name
Test status
Simulation time 132838492562 ps
CPU time 126.09 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:59:28 PM PDT 24
Peak memory 182724 kb
Host smart-ebb70f7d-ac2c-4183-a18d-69bc972025c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725604330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1725604330
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3422748343
Short name T399
Test name
Test status
Simulation time 392981358734 ps
CPU time 162.31 seconds
Started Mar 28 12:57:20 PM PDT 24
Finished Mar 28 01:00:03 PM PDT 24
Peak memory 182716 kb
Host smart-f4a65fee-4cff-4db9-b097-6ce791ab46be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422748343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3422748343
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1724665332
Short name T455
Test name
Test status
Simulation time 59884837926 ps
CPU time 136.49 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:00:01 PM PDT 24
Peak memory 190884 kb
Host smart-1a7820ea-74ce-4d83-b59c-e4152df0d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724665332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1724665332
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1490044045
Short name T73
Test name
Test status
Simulation time 1371657856782 ps
CPU time 719.05 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 01:09:22 PM PDT 24
Peak memory 190884 kb
Host smart-a62b08c1-2a3e-4b47-99bf-a1acd607b73f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490044045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1490044045
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1980607171
Short name T262
Test name
Test status
Simulation time 224629601151 ps
CPU time 1029.98 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:15:33 PM PDT 24
Peak memory 190168 kb
Host smart-6f4a34be-2aeb-4f10-b171-a1b7812ab2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980607171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1980607171
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2712329407
Short name T287
Test name
Test status
Simulation time 116411378381 ps
CPU time 643.24 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 01:09:06 PM PDT 24
Peak memory 194504 kb
Host smart-cc486160-7aa4-4632-9b0e-74ae82de2f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712329407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2712329407
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3248803642
Short name T258
Test name
Test status
Simulation time 157186483806 ps
CPU time 643.72 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:09:07 PM PDT 24
Peak memory 190900 kb
Host smart-e451d6de-d7e9-4a03-a7b7-0ab80e1f9589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248803642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3248803642
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3989365258
Short name T188
Test name
Test status
Simulation time 222692488448 ps
CPU time 2114.04 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 190896 kb
Host smart-39ea7552-e2e7-4ac2-87a5-c94c83405bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989365258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3989365258
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2412758077
Short name T204
Test name
Test status
Simulation time 245643735728 ps
CPU time 283.64 seconds
Started Mar 28 12:58:13 PM PDT 24
Finished Mar 28 01:02:57 PM PDT 24
Peak memory 190884 kb
Host smart-3f7c01b2-3b78-456f-b858-4e1526e0c047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412758077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2412758077
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3311019041
Short name T132
Test name
Test status
Simulation time 225116289238 ps
CPU time 374.53 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:04:38 PM PDT 24
Peak memory 190900 kb
Host smart-186be7aa-e63f-437c-9558-67dbd5656ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311019041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3311019041
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.926192216
Short name T61
Test name
Test status
Simulation time 1030676784768 ps
CPU time 553.96 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:07:30 PM PDT 24
Peak memory 190820 kb
Host smart-4f45aaae-ce98-440f-bdbc-9e83ebb6849f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926192216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.926192216
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2273161261
Short name T305
Test name
Test status
Simulation time 5388330204 ps
CPU time 44.61 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 12:59:08 PM PDT 24
Peak memory 182716 kb
Host smart-fac192bb-668d-49b7-a95b-464504817f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273161261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2273161261
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.792128817
Short name T357
Test name
Test status
Simulation time 426468400999 ps
CPU time 1426.16 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:22:02 PM PDT 24
Peak memory 190892 kb
Host smart-c603cb7d-068b-42cb-9f91-46bc7f73a345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792128817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.792128817
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3810278032
Short name T167
Test name
Test status
Simulation time 1596305284620 ps
CPU time 533.68 seconds
Started Mar 28 12:57:25 PM PDT 24
Finished Mar 28 01:06:19 PM PDT 24
Peak memory 182596 kb
Host smart-ef34c8d3-470c-456b-8761-dd702080b791
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810278032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3810278032
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1908381089
Short name T395
Test name
Test status
Simulation time 194037025259 ps
CPU time 203.2 seconds
Started Mar 28 12:57:29 PM PDT 24
Finished Mar 28 01:00:53 PM PDT 24
Peak memory 182644 kb
Host smart-91d6c117-357e-4d67-a0b6-c6711ee49ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908381089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1908381089
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3363295445
Short name T299
Test name
Test status
Simulation time 127291721393 ps
CPU time 454.87 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:05:19 PM PDT 24
Peak memory 190888 kb
Host smart-020aabd8-2c4d-4767-9136-e94347b2acd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363295445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3363295445
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2006181891
Short name T326
Test name
Test status
Simulation time 15764584781 ps
CPU time 27.09 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 12:58:11 PM PDT 24
Peak memory 190876 kb
Host smart-ebe4b5cb-b121-40f2-9a61-acb492319918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006181891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2006181891
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3571654034
Short name T396
Test name
Test status
Simulation time 30292710962 ps
CPU time 50.65 seconds
Started Mar 28 12:57:23 PM PDT 24
Finished Mar 28 12:58:14 PM PDT 24
Peak memory 194216 kb
Host smart-97ac9a39-f583-49a7-8a5f-708639333215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571654034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3571654034
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3960035906
Short name T297
Test name
Test status
Simulation time 5573688428 ps
CPU time 201.3 seconds
Started Mar 28 12:58:20 PM PDT 24
Finished Mar 28 01:01:42 PM PDT 24
Peak memory 182708 kb
Host smart-625aa74c-fc31-4c0b-a329-0199d62df731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960035906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3960035906
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3944555356
Short name T144
Test name
Test status
Simulation time 45942964975 ps
CPU time 73.76 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 12:59:38 PM PDT 24
Peak memory 190900 kb
Host smart-26b51793-a67b-4d1c-ad46-65bdf635e65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944555356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3944555356
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.188799218
Short name T27
Test name
Test status
Simulation time 109020028527 ps
CPU time 85.13 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:59:48 PM PDT 24
Peak memory 189920 kb
Host smart-0a32cded-adfc-4934-aceb-73b40dfc749e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188799218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.188799218
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2030109387
Short name T267
Test name
Test status
Simulation time 660209288183 ps
CPU time 488.29 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 01:06:31 PM PDT 24
Peak memory 190688 kb
Host smart-95223e18-a8df-4914-8c93-560b7e142453
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030109387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2030109387
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1503030664
Short name T275
Test name
Test status
Simulation time 132038643948 ps
CPU time 415.19 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:05:11 PM PDT 24
Peak memory 190872 kb
Host smart-647aaf37-8b57-4847-99f6-c3fd89c42a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503030664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1503030664
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.653336112
Short name T14
Test name
Test status
Simulation time 27453307816 ps
CPU time 232.6 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 01:02:15 PM PDT 24
Peak memory 190568 kb
Host smart-8db0a7cf-1e45-44eb-a025-e92f6d8a148a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653336112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.653336112
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2920405459
Short name T242
Test name
Test status
Simulation time 437565992621 ps
CPU time 254.94 seconds
Started Mar 28 12:58:14 PM PDT 24
Finished Mar 28 01:02:29 PM PDT 24
Peak memory 190820 kb
Host smart-8fa308fb-53b9-4209-b5ad-db38630f192b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920405459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2920405459
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.872798507
Short name T393
Test name
Test status
Simulation time 11020988656 ps
CPU time 19.34 seconds
Started Mar 28 12:57:35 PM PDT 24
Finished Mar 28 12:57:54 PM PDT 24
Peak memory 182652 kb
Host smart-3e51e98f-c09e-4963-97f3-c867ec438571
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872798507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.872798507
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.366703725
Short name T391
Test name
Test status
Simulation time 90467259141 ps
CPU time 120.44 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:59:28 PM PDT 24
Peak memory 182692 kb
Host smart-c430c8ec-53c3-4e67-bedc-4afe051e29fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366703725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.366703725
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/70.rv_timer_random.1983558888
Short name T62
Test name
Test status
Simulation time 568261549266 ps
CPU time 329.57 seconds
Started Mar 28 12:58:15 PM PDT 24
Finished Mar 28 01:03:45 PM PDT 24
Peak memory 190812 kb
Host smart-67785d8f-eb8b-497b-a159-f0cc0afb683d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983558888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1983558888
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3787357850
Short name T319
Test name
Test status
Simulation time 519777594852 ps
CPU time 369.9 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 01:04:32 PM PDT 24
Peak memory 190688 kb
Host smart-defbc966-5216-4d14-8fcc-4cf18d8a6bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787357850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3787357850
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.294133540
Short name T454
Test name
Test status
Simulation time 115189108194 ps
CPU time 32.62 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:58:54 PM PDT 24
Peak memory 182480 kb
Host smart-5b72b752-6c2d-4628-bf40-a0deceefdf0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294133540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.294133540
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3434080779
Short name T309
Test name
Test status
Simulation time 515320012946 ps
CPU time 114.92 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 01:00:16 PM PDT 24
Peak memory 190688 kb
Host smart-54487122-46c1-4c59-96ca-009f8059dd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434080779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3434080779
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1477723772
Short name T311
Test name
Test status
Simulation time 70419323062 ps
CPU time 106.4 seconds
Started Mar 28 12:58:17 PM PDT 24
Finished Mar 28 01:00:04 PM PDT 24
Peak memory 190880 kb
Host smart-21311bfe-5b12-41a0-8a37-37ef4e862ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477723772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1477723772
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2153635140
Short name T95
Test name
Test status
Simulation time 98571828684 ps
CPU time 529.62 seconds
Started Mar 28 12:58:17 PM PDT 24
Finished Mar 28 01:07:07 PM PDT 24
Peak memory 190880 kb
Host smart-d84e8bb3-9632-4831-a092-b377482bf9c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153635140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2153635140
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1124086301
Short name T441
Test name
Test status
Simulation time 87330747782 ps
CPU time 97.85 seconds
Started Mar 28 12:58:25 PM PDT 24
Finished Mar 28 01:00:04 PM PDT 24
Peak memory 190832 kb
Host smart-bc7c3a88-a040-4efe-9e6e-b34c76d17e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124086301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1124086301
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3507863168
Short name T200
Test name
Test status
Simulation time 1137891920165 ps
CPU time 373.68 seconds
Started Mar 28 12:58:23 PM PDT 24
Finished Mar 28 01:04:37 PM PDT 24
Peak memory 190832 kb
Host smart-a4514539-c4a2-4b11-9b19-6494127bc23f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507863168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3507863168
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2170799993
Short name T325
Test name
Test status
Simulation time 52602832844 ps
CPU time 121.97 seconds
Started Mar 28 12:58:16 PM PDT 24
Finished Mar 28 01:00:18 PM PDT 24
Peak memory 190880 kb
Host smart-acc481f9-adfb-464c-a35c-96c260d98211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170799993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2170799993
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3968701553
Short name T145
Test name
Test status
Simulation time 1357772601369 ps
CPU time 1229.76 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 01:18:11 PM PDT 24
Peak memory 182736 kb
Host smart-b33c6d6a-9e29-4ce8-bc6c-0ead5505a909
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968701553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3968701553
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3715133114
Short name T402
Test name
Test status
Simulation time 401981442523 ps
CPU time 275.39 seconds
Started Mar 28 12:57:30 PM PDT 24
Finished Mar 28 01:02:06 PM PDT 24
Peak memory 182628 kb
Host smart-8e1e5fbb-3292-4332-9330-564ea2c14f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715133114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3715133114
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3163801955
Short name T85
Test name
Test status
Simulation time 89165892102 ps
CPU time 223.31 seconds
Started Mar 28 12:57:48 PM PDT 24
Finished Mar 28 01:01:31 PM PDT 24
Peak memory 190648 kb
Host smart-c1888852-78e9-43d1-9e9e-8cc2335d361b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163801955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3163801955
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.606043259
Short name T341
Test name
Test status
Simulation time 56784909542 ps
CPU time 71.74 seconds
Started Mar 28 12:57:45 PM PDT 24
Finished Mar 28 12:58:57 PM PDT 24
Peak memory 190648 kb
Host smart-ecef6a9b-37f7-4beb-b1ff-80667ba37be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606043259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.606043259
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1680566255
Short name T47
Test name
Test status
Simulation time 606700065309 ps
CPU time 232.65 seconds
Started Mar 28 12:57:31 PM PDT 24
Finished Mar 28 01:01:23 PM PDT 24
Peak memory 182660 kb
Host smart-0f9160ad-e4e7-4c0a-87c4-a95295633bb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680566255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1680566255
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1831973631
Short name T37
Test name
Test status
Simulation time 50144361308 ps
CPU time 267.89 seconds
Started Mar 28 12:57:44 PM PDT 24
Finished Mar 28 01:02:12 PM PDT 24
Peak memory 205292 kb
Host smart-3ca8a771-9a33-475d-9fa7-2870222843e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831973631 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1831973631
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1160936759
Short name T169
Test name
Test status
Simulation time 163174180555 ps
CPU time 299.51 seconds
Started Mar 28 12:58:12 PM PDT 24
Finished Mar 28 01:03:12 PM PDT 24
Peak memory 190880 kb
Host smart-d744ffb0-cf96-4b62-b20d-ce4d1b804e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160936759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1160936759
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.4088750234
Short name T9
Test name
Test status
Simulation time 813481099264 ps
CPU time 399.49 seconds
Started Mar 28 12:58:19 PM PDT 24
Finished Mar 28 01:04:58 PM PDT 24
Peak memory 190888 kb
Host smart-6f43c2cd-f09d-4cda-9895-11e1dca796e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088750234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4088750234
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2436482022
Short name T276
Test name
Test status
Simulation time 445470276738 ps
CPU time 595.55 seconds
Started Mar 28 12:58:19 PM PDT 24
Finished Mar 28 01:08:15 PM PDT 24
Peak memory 190888 kb
Host smart-fafd91f2-dfc9-4ac8-986a-f15144cedd64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436482022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2436482022
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2063280493
Short name T4
Test name
Test status
Simulation time 98420840150 ps
CPU time 305.25 seconds
Started Mar 28 12:58:31 PM PDT 24
Finished Mar 28 01:03:37 PM PDT 24
Peak memory 182716 kb
Host smart-142aede6-2a6d-41ba-889c-205f8168495f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063280493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2063280493
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1134743923
Short name T277
Test name
Test status
Simulation time 50585502120 ps
CPU time 83.46 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 12:59:56 PM PDT 24
Peak memory 190772 kb
Host smart-0a306f89-b517-4018-8678-fcf5f9552d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134743923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1134743923
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4236530907
Short name T254
Test name
Test status
Simulation time 71111338325 ps
CPU time 79.85 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 12:59:43 PM PDT 24
Peak memory 182560 kb
Host smart-c99190f2-bca8-416b-b261-67624625235f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236530907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4236530907
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3521556099
Short name T193
Test name
Test status
Simulation time 500832210464 ps
CPU time 348.95 seconds
Started Mar 28 12:58:24 PM PDT 24
Finished Mar 28 01:04:13 PM PDT 24
Peak memory 190840 kb
Host smart-4cfc41a5-38dd-4ad3-81ce-32dacd10b244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521556099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3521556099
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3562329334
Short name T195
Test name
Test status
Simulation time 123235644757 ps
CPU time 680.56 seconds
Started Mar 28 12:58:20 PM PDT 24
Finished Mar 28 01:09:42 PM PDT 24
Peak memory 190840 kb
Host smart-c3946b78-e4fb-4c50-9be6-cb7638c58dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562329334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3562329334
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2057602925
Short name T351
Test name
Test status
Simulation time 98054778104 ps
CPU time 311.5 seconds
Started Mar 28 12:58:30 PM PDT 24
Finished Mar 28 01:03:42 PM PDT 24
Peak memory 190900 kb
Host smart-2e788e12-7379-44ea-b85a-67f6c49fa932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057602925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2057602925
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.681770275
Short name T320
Test name
Test status
Simulation time 1419151670278 ps
CPU time 1423.47 seconds
Started Mar 28 12:58:33 PM PDT 24
Finished Mar 28 01:22:17 PM PDT 24
Peak memory 190764 kb
Host smart-013d6dad-2141-4984-baec-3472cda6f3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681770275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.681770275
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2109450505
Short name T353
Test name
Test status
Simulation time 332159768151 ps
CPU time 597.35 seconds
Started Mar 28 12:57:39 PM PDT 24
Finished Mar 28 01:07:37 PM PDT 24
Peak memory 182656 kb
Host smart-5553a20c-50ad-418b-8898-95c4b828dc71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109450505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2109450505
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.727583618
Short name T428
Test name
Test status
Simulation time 593602969460 ps
CPU time 251.42 seconds
Started Mar 28 12:57:45 PM PDT 24
Finished Mar 28 01:01:57 PM PDT 24
Peak memory 182444 kb
Host smart-ed754815-b2d1-4b68-845f-00dac2bef45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727583618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.727583618
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1189051133
Short name T82
Test name
Test status
Simulation time 115177924192 ps
CPU time 133.44 seconds
Started Mar 28 12:57:41 PM PDT 24
Finished Mar 28 12:59:55 PM PDT 24
Peak memory 190684 kb
Host smart-61091fb8-2db8-4faa-bee3-f8f6515551ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189051133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1189051133
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.896726520
Short name T77
Test name
Test status
Simulation time 41405506868 ps
CPU time 65.84 seconds
Started Mar 28 12:57:42 PM PDT 24
Finished Mar 28 12:58:48 PM PDT 24
Peak memory 193036 kb
Host smart-29a5c3ce-e18a-49cc-bbf8-db1529596e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896726520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.896726520
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1260967401
Short name T42
Test name
Test status
Simulation time 30461789783 ps
CPU time 218.12 seconds
Started Mar 28 12:57:45 PM PDT 24
Finished Mar 28 01:01:23 PM PDT 24
Peak memory 205328 kb
Host smart-c88d1c31-f5b3-4ac3-8056-3e327d6f436f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260967401 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1260967401
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.rv_timer_random.1159416786
Short name T452
Test name
Test status
Simulation time 197972755976 ps
CPU time 96.65 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 190836 kb
Host smart-0d1ba50c-1206-4b86-ae2c-5e4b7c2e8a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159416786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1159416786
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.4086792531
Short name T322
Test name
Test status
Simulation time 44884476461 ps
CPU time 508.69 seconds
Started Mar 28 12:58:22 PM PDT 24
Finished Mar 28 01:06:52 PM PDT 24
Peak memory 182716 kb
Host smart-36605ac6-83e0-40b0-95b8-5e3271aebc4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086792531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4086792531
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2258641158
Short name T88
Test name
Test status
Simulation time 207518666294 ps
CPU time 414.46 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 01:05:17 PM PDT 24
Peak memory 190840 kb
Host smart-a59fe60e-08b0-4f11-b245-7183de48d0e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258641158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2258641158
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1704650271
Short name T268
Test name
Test status
Simulation time 618215462432 ps
CPU time 653.72 seconds
Started Mar 28 12:58:21 PM PDT 24
Finished Mar 28 01:09:15 PM PDT 24
Peak memory 190912 kb
Host smart-030aef85-80e5-400d-a97b-0e3d3cb79121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704650271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1704650271
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2526814919
Short name T45
Test name
Test status
Simulation time 291478867605 ps
CPU time 395.4 seconds
Started Mar 28 12:58:30 PM PDT 24
Finished Mar 28 01:05:06 PM PDT 24
Peak memory 190900 kb
Host smart-96e57693-f822-4bf4-a255-d59a8e7b61a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526814919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2526814919
Directory /workspace/99.rv_timer_random/latest
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