Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 576
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2481788989 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:27 PM PDT 24 584414368 ps
T509 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.528604234 Mar 31 12:22:20 PM PDT 24 Mar 31 12:22:23 PM PDT 24 395426350 ps
T510 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3747287422 Mar 31 12:23:26 PM PDT 24 Mar 31 12:23:28 PM PDT 24 81601610 ps
T511 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4258605811 Mar 31 12:23:28 PM PDT 24 Mar 31 12:23:29 PM PDT 24 46211661 ps
T512 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.525997864 Mar 31 12:23:30 PM PDT 24 Mar 31 12:23:31 PM PDT 24 21977309 ps
T513 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3521097445 Mar 31 12:23:41 PM PDT 24 Mar 31 12:23:47 PM PDT 24 36023670 ps
T514 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1089796664 Mar 31 12:23:31 PM PDT 24 Mar 31 12:23:32 PM PDT 24 34210356 ps
T515 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2481717642 Mar 31 12:23:42 PM PDT 24 Mar 31 12:23:43 PM PDT 24 27483650 ps
T516 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3526528986 Mar 31 12:23:12 PM PDT 24 Mar 31 12:23:15 PM PDT 24 189721990 ps
T517 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.524794639 Mar 31 12:23:23 PM PDT 24 Mar 31 12:23:25 PM PDT 24 93147205 ps
T518 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3436465077 Mar 31 12:23:23 PM PDT 24 Mar 31 12:23:29 PM PDT 24 91415428 ps
T519 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1147813772 Mar 31 12:23:30 PM PDT 24 Mar 31 12:23:32 PM PDT 24 2145132586 ps
T520 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3281100762 Mar 31 12:23:30 PM PDT 24 Mar 31 12:23:31 PM PDT 24 31075846 ps
T70 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3980691699 Mar 31 12:23:23 PM PDT 24 Mar 31 12:23:24 PM PDT 24 19105254 ps
T521 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.116263956 Mar 31 12:23:34 PM PDT 24 Mar 31 12:23:35 PM PDT 24 53127089 ps
T522 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3257779882 Mar 31 12:23:26 PM PDT 24 Mar 31 12:23:27 PM PDT 24 54253047 ps
T523 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3681892669 Mar 31 12:23:24 PM PDT 24 Mar 31 12:23:24 PM PDT 24 14824052 ps
T524 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2469364373 Mar 31 12:23:23 PM PDT 24 Mar 31 12:23:24 PM PDT 24 13798638 ps
T525 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.286165760 Mar 31 12:23:26 PM PDT 24 Mar 31 12:23:27 PM PDT 24 69297437 ps
T526 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3298891478 Mar 31 12:25:40 PM PDT 24 Mar 31 12:25:41 PM PDT 24 43733779 ps
T527 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1712298602 Mar 31 12:23:09 PM PDT 24 Mar 31 12:23:10 PM PDT 24 266208524 ps
T528 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2169089576 Mar 31 12:23:23 PM PDT 24 Mar 31 12:23:25 PM PDT 24 141199533 ps
T529 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4288148729 Mar 31 12:23:28 PM PDT 24 Mar 31 12:23:29 PM PDT 24 21754349 ps
T530 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2867313274 Mar 31 12:23:22 PM PDT 24 Mar 31 12:23:23 PM PDT 24 70670179 ps
T531 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2019520736 Mar 31 12:23:31 PM PDT 24 Mar 31 12:23:33 PM PDT 24 402855524 ps
T532 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.132016190 Mar 31 12:23:43 PM PDT 24 Mar 31 12:23:43 PM PDT 24 28905649 ps
T533 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1608653022 Mar 31 12:23:21 PM PDT 24 Mar 31 12:23:21 PM PDT 24 14469290 ps
T534 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3855516685 Mar 31 12:23:36 PM PDT 24 Mar 31 12:23:38 PM PDT 24 152296200 ps
T535 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3312270112 Mar 31 12:24:30 PM PDT 24 Mar 31 12:24:31 PM PDT 24 17951296 ps
T536 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4000918780 Mar 31 12:23:28 PM PDT 24 Mar 31 12:23:29 PM PDT 24 665654983 ps
T537 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.179170938 Mar 31 12:23:26 PM PDT 24 Mar 31 12:23:27 PM PDT 24 66177635 ps
T538 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1333651885 Mar 31 12:23:40 PM PDT 24 Mar 31 12:23:41 PM PDT 24 11398325 ps
T539 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3384259461 Mar 31 12:23:30 PM PDT 24 Mar 31 12:23:32 PM PDT 24 197126146 ps
T540 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3780922974 Mar 31 12:23:57 PM PDT 24 Mar 31 12:23:58 PM PDT 24 16515584 ps
T71 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1827506220 Mar 31 12:23:28 PM PDT 24 Mar 31 12:23:29 PM PDT 24 28561432 ps
T541 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2374344165 Mar 31 12:23:36 PM PDT 24 Mar 31 12:23:36 PM PDT 24 23458560 ps
T542 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2127847336 Mar 31 12:23:24 PM PDT 24 Mar 31 12:23:26 PM PDT 24 84378127 ps
T543 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.887077328 Mar 31 12:23:27 PM PDT 24 Mar 31 12:23:27 PM PDT 24 65542141 ps
T544 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1305066627 Mar 31 12:23:26 PM PDT 24 Mar 31 12:23:27 PM PDT 24 19603861 ps
T545 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3188118607 Mar 31 12:23:33 PM PDT 24 Mar 31 12:23:34 PM PDT 24 43543056 ps
T546 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4192745845 Mar 31 12:25:47 PM PDT 24 Mar 31 12:25:48 PM PDT 24 20966892 ps
T547 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2424350048 Mar 31 12:23:34 PM PDT 24 Mar 31 12:23:34 PM PDT 24 18603311 ps
T548 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.44441067 Mar 31 12:23:21 PM PDT 24 Mar 31 12:23:21 PM PDT 24 15116705 ps
T549 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2263587063 Mar 31 12:23:42 PM PDT 24 Mar 31 12:23:43 PM PDT 24 45741815 ps
T550 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3425637577 Mar 31 12:23:13 PM PDT 24 Mar 31 12:23:14 PM PDT 24 73908379 ps
T551 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3930286108 Mar 31 12:23:55 PM PDT 24 Mar 31 12:23:55 PM PDT 24 15540999 ps
T552 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2318529137 Mar 31 12:23:38 PM PDT 24 Mar 31 12:23:38 PM PDT 24 14322214 ps
T553 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1178010001 Mar 31 12:23:45 PM PDT 24 Mar 31 12:23:46 PM PDT 24 24735424 ps
T554 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3190434393 Mar 31 12:23:35 PM PDT 24 Mar 31 12:23:36 PM PDT 24 29465270 ps
T555 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2852628521 Mar 31 12:24:02 PM PDT 24 Mar 31 12:24:04 PM PDT 24 145555771 ps
T556 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1458899199 Mar 31 12:23:35 PM PDT 24 Mar 31 12:23:36 PM PDT 24 39423348 ps
T72 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3737548622 Mar 31 12:23:27 PM PDT 24 Mar 31 12:23:28 PM PDT 24 29622173 ps
T557 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.774732395 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:25 PM PDT 24 11999611 ps
T558 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1866426283 Mar 31 12:23:28 PM PDT 24 Mar 31 12:23:29 PM PDT 24 109026848 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3215535955 Mar 31 12:23:12 PM PDT 24 Mar 31 12:23:14 PM PDT 24 140744485 ps
T73 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1099749515 Mar 31 12:23:22 PM PDT 24 Mar 31 12:23:23 PM PDT 24 116376592 ps
T560 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3718650377 Mar 31 12:23:23 PM PDT 24 Mar 31 12:23:25 PM PDT 24 862290358 ps
T561 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.202574783 Mar 31 12:23:25 PM PDT 24 Mar 31 12:23:26 PM PDT 24 31341634 ps
T562 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.623441396 Mar 31 12:24:30 PM PDT 24 Mar 31 12:24:31 PM PDT 24 106622888 ps
T563 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1858829818 Mar 31 12:23:36 PM PDT 24 Mar 31 12:23:37 PM PDT 24 15661000 ps
T76 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2138543122 Mar 31 12:23:20 PM PDT 24 Mar 31 12:23:21 PM PDT 24 31177991 ps
T564 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2345126046 Mar 31 12:24:23 PM PDT 24 Mar 31 12:24:24 PM PDT 24 47960007 ps
T565 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3354776540 Mar 31 12:23:33 PM PDT 24 Mar 31 12:23:35 PM PDT 24 31861117 ps
T566 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2510636444 Mar 31 12:23:16 PM PDT 24 Mar 31 12:23:16 PM PDT 24 98808391 ps
T567 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.433284474 Mar 31 12:23:25 PM PDT 24 Mar 31 12:23:26 PM PDT 24 67178772 ps
T568 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.387164789 Mar 31 12:23:27 PM PDT 24 Mar 31 12:23:29 PM PDT 24 34921743 ps
T569 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.53740627 Mar 31 12:25:08 PM PDT 24 Mar 31 12:25:09 PM PDT 24 167493967 ps
T570 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1318869433 Mar 31 12:23:51 PM PDT 24 Mar 31 12:23:51 PM PDT 24 15879021 ps
T571 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3499429322 Mar 31 12:23:21 PM PDT 24 Mar 31 12:23:22 PM PDT 24 101374702 ps
T572 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2647499756 Mar 31 12:23:45 PM PDT 24 Mar 31 12:23:46 PM PDT 24 27621950 ps
T573 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.137029689 Mar 31 12:23:35 PM PDT 24 Mar 31 12:23:36 PM PDT 24 43930317 ps
T574 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3705825344 Mar 31 12:23:23 PM PDT 24 Mar 31 12:23:25 PM PDT 24 570894103 ps
T575 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1729807320 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:15 PM PDT 24 17966463 ps
T74 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.292901863 Mar 31 12:23:26 PM PDT 24 Mar 31 12:23:27 PM PDT 24 53204481 ps
T576 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1973186991 Mar 31 12:24:23 PM PDT 24 Mar 31 12:24:24 PM PDT 24 20550004 ps
T75 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4017498261 Mar 31 12:24:23 PM PDT 24 Mar 31 12:24:27 PM PDT 24 1473413494 ps

Test location /workspace/coverage/default/27.rv_timer_random.2655047966
Short name T2
Test name
Test status
Simulation time 441423060897 ps
CPU time 412.93 seconds
Started Mar 31 12:31:06 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 190860 kb
Host smart-482961c3-9e19-490d-83b1-76d44d13ad6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655047966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2655047966
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2465885420
Short name T12
Test name
Test status
Simulation time 17845498609 ps
CPU time 70.18 seconds
Started Mar 31 12:30:39 PM PDT 24
Finished Mar 31 12:31:49 PM PDT 24
Peak memory 197620 kb
Host smart-a06f2233-f5a1-40f1-bc07-3dd42809f4ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465885420 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.2465885420
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.916227871
Short name T185
Test name
Test status
Simulation time 1497594177114 ps
CPU time 3351.39 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 01:26:37 PM PDT 24
Peak memory 190900 kb
Host smart-9eb321c5-58f3-400f-8516-12a6c37f694f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916227871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
916227871
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3676844410
Short name T26
Test name
Test status
Simulation time 51779459 ps
CPU time 0.87 seconds
Started Mar 31 12:23:04 PM PDT 24
Finished Mar 31 12:23:05 PM PDT 24
Peak memory 182128 kb
Host smart-c994fe3e-743b-4b22-b742-344ff39d6937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676844410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3676844410
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4075751713
Short name T105
Test name
Test status
Simulation time 2959627424742 ps
CPU time 1814.79 seconds
Started Mar 31 12:30:53 PM PDT 24
Finished Mar 31 01:01:08 PM PDT 24
Peak memory 190788 kb
Host smart-a0e3b39b-038c-4cab-ad5f-b4e04dd367b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075751713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4075751713
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1048873571
Short name T54
Test name
Test status
Simulation time 1532999088198 ps
CPU time 1211.85 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:50:58 PM PDT 24
Peak memory 190896 kb
Host smart-62cddead-ee4b-49d6-b769-62ed32ae7cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048873571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1048873571
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1611918617
Short name T62
Test name
Test status
Simulation time 12091953 ps
CPU time 0.57 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 182584 kb
Host smart-61d94cd2-c863-4cfc-b3ec-05442d6d414d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611918617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1611918617
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2806506500
Short name T58
Test name
Test status
Simulation time 1667467653293 ps
CPU time 2749.68 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 01:17:01 PM PDT 24
Peak memory 190888 kb
Host smart-68ff8e31-4359-4429-8a34-635a4c582f77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806506500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2806506500
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1145511355
Short name T77
Test name
Test status
Simulation time 1954400368278 ps
CPU time 3167.52 seconds
Started Mar 31 12:31:00 PM PDT 24
Finished Mar 31 01:23:48 PM PDT 24
Peak memory 190884 kb
Host smart-969088a1-06fe-47f7-9c4c-c2fa847b7975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145511355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1145511355
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.3780122542
Short name T97
Test name
Test status
Simulation time 300461760805 ps
CPU time 590.22 seconds
Started Mar 31 12:31:13 PM PDT 24
Finished Mar 31 12:41:03 PM PDT 24
Peak memory 190840 kb
Host smart-5e1f5d8b-356f-46ee-893a-4543856168ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780122542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3780122542
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4032210076
Short name T56
Test name
Test status
Simulation time 752156739714 ps
CPU time 1408.28 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:54:14 PM PDT 24
Peak memory 190772 kb
Host smart-64377c3f-e8a6-488e-8734-25499aeedeb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032210076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4032210076
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2202664586
Short name T49
Test name
Test status
Simulation time 763537464931 ps
CPU time 1364.02 seconds
Started Mar 31 12:31:06 PM PDT 24
Finished Mar 31 12:53:50 PM PDT 24
Peak memory 190828 kb
Host smart-6c7f35c3-6f21-4afd-b774-5776aad3410a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202664586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2202664586
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1348685177
Short name T119
Test name
Test status
Simulation time 469263573867 ps
CPU time 765.25 seconds
Started Mar 31 12:30:41 PM PDT 24
Finished Mar 31 12:43:26 PM PDT 24
Peak memory 190748 kb
Host smart-be6b169c-4895-4455-94bd-66308465a28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348685177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1348685177
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.312539143
Short name T220
Test name
Test status
Simulation time 451717012585 ps
CPU time 1478.83 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 12:55:50 PM PDT 24
Peak memory 190780 kb
Host smart-62b0aa8c-ed4a-4407-a182-989ce59f08d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312539143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
312539143
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1712851870
Short name T17
Test name
Test status
Simulation time 39653471 ps
CPU time 0.75 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:30:38 PM PDT 24
Peak memory 213208 kb
Host smart-c4aa22ec-94dd-4799-9155-a81c6f3c6228
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712851870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1712851870
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3157926707
Short name T134
Test name
Test status
Simulation time 536736135921 ps
CPU time 472.84 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:38:37 PM PDT 24
Peak memory 190900 kb
Host smart-2874d6d5-cb11-4592-ba86-ac450309e7e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157926707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3157926707
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3729829319
Short name T175
Test name
Test status
Simulation time 2492192724876 ps
CPU time 1202.7 seconds
Started Mar 31 12:30:38 PM PDT 24
Finished Mar 31 12:50:41 PM PDT 24
Peak memory 194732 kb
Host smart-6bb5a8a1-97e3-412d-b02d-1fc8324e7a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729829319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3729829319
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/56.rv_timer_random.2606405762
Short name T100
Test name
Test status
Simulation time 1342602281092 ps
CPU time 1516.49 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:56:33 PM PDT 24
Peak memory 190892 kb
Host smart-7fe52377-790e-4485-81fb-c0b93d1924bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606405762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2606405762
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.1423202874
Short name T111
Test name
Test status
Simulation time 184098565565 ps
CPU time 745.25 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:43:02 PM PDT 24
Peak memory 190836 kb
Host smart-71b6f2b5-3928-4097-af68-ff9f11fb32f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423202874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1423202874
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3471037917
Short name T38
Test name
Test status
Simulation time 129548157978 ps
CPU time 247.67 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:35:27 PM PDT 24
Peak memory 194364 kb
Host smart-50438ce4-f8ba-4259-8139-bcfbdcc3f945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471037917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3471037917
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2143931546
Short name T141
Test name
Test status
Simulation time 197278660571 ps
CPU time 749.92 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:43:17 PM PDT 24
Peak memory 190852 kb
Host smart-395663c8-96d9-4491-97be-a2f725acc8eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143931546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2143931546
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1926547262
Short name T135
Test name
Test status
Simulation time 754526018416 ps
CPU time 1122.89 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:49:28 PM PDT 24
Peak memory 190904 kb
Host smart-aff96dc8-f64f-48e2-86a0-6d70bf857e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926547262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1926547262
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/87.rv_timer_random.1017761290
Short name T165
Test name
Test status
Simulation time 190452888926 ps
CPU time 327.36 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 190836 kb
Host smart-e57fdfd3-07aa-49c9-b84a-94bf0d488663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017761290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1017761290
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4132791632
Short name T129
Test name
Test status
Simulation time 284209824912 ps
CPU time 1040.61 seconds
Started Mar 31 12:31:24 PM PDT 24
Finished Mar 31 12:48:45 PM PDT 24
Peak memory 190900 kb
Host smart-753fee19-2501-4619-b818-7b1bb915c4de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132791632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4132791632
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1617705680
Short name T142
Test name
Test status
Simulation time 1619474299943 ps
CPU time 3320.24 seconds
Started Mar 31 12:30:51 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 190828 kb
Host smart-8c5feeba-8bab-4aa4-ac92-9b97d60aa47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617705680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1617705680
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/104.rv_timer_random.2828889495
Short name T145
Test name
Test status
Simulation time 197456898950 ps
CPU time 1873.82 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 01:02:43 PM PDT 24
Peak memory 190872 kb
Host smart-6034fdfb-e500-44de-a1f6-4f76b2463bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828889495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2828889495
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3899129418
Short name T80
Test name
Test status
Simulation time 1024803724381 ps
CPU time 1506.72 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:55:54 PM PDT 24
Peak memory 190708 kb
Host smart-46983369-09fb-41d9-8f59-6820dcc451e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899129418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3899129418
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3017391459
Short name T203
Test name
Test status
Simulation time 535433962819 ps
CPU time 1711.89 seconds
Started Mar 31 12:31:01 PM PDT 24
Finished Mar 31 12:59:34 PM PDT 24
Peak memory 190816 kb
Host smart-faebd73f-3c62-4557-8521-bad265962617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017391459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3017391459
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1965385748
Short name T4
Test name
Test status
Simulation time 121502826633 ps
CPU time 187.5 seconds
Started Mar 31 12:30:43 PM PDT 24
Finished Mar 31 12:33:50 PM PDT 24
Peak memory 190820 kb
Host smart-40017193-87b8-4d19-98d8-38185e447965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965385748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1965385748
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3003529934
Short name T107
Test name
Test status
Simulation time 1085054039078 ps
CPU time 843.32 seconds
Started Mar 31 12:30:35 PM PDT 24
Finished Mar 31 12:44:39 PM PDT 24
Peak memory 190828 kb
Host smart-c27d3a52-5089-4b61-9969-9bc0bb76f276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003529934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3003529934
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/186.rv_timer_random.4059157609
Short name T148
Test name
Test status
Simulation time 120055630352 ps
CPU time 344.39 seconds
Started Mar 31 12:31:28 PM PDT 24
Finished Mar 31 12:37:12 PM PDT 24
Peak memory 190856 kb
Host smart-4c00e52b-8a4c-4a85-8ed1-b4e96c413886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059157609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4059157609
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.943423673
Short name T205
Test name
Test status
Simulation time 655042531239 ps
CPU time 1602.23 seconds
Started Mar 31 12:31:07 PM PDT 24
Finished Mar 31 12:57:50 PM PDT 24
Peak memory 190888 kb
Host smart-a067bc89-a1af-4d46-a4cf-2ab29efe4282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943423673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
943423673
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1396457735
Short name T57
Test name
Test status
Simulation time 1204040078004 ps
CPU time 897.78 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:45:45 PM PDT 24
Peak memory 190792 kb
Host smart-d9153eba-b665-4b27-a920-e3ff33e4a053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396457735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1396457735
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/96.rv_timer_random.1679708998
Short name T144
Test name
Test status
Simulation time 486885785421 ps
CPU time 281.15 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:35:56 PM PDT 24
Peak memory 190892 kb
Host smart-bd54270f-c94a-4dbe-b386-42f2d59a4c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679708998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1679708998
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3627628424
Short name T63
Test name
Test status
Simulation time 21982824 ps
CPU time 0.79 seconds
Started Mar 31 12:25:27 PM PDT 24
Finished Mar 31 12:25:33 PM PDT 24
Peak memory 182944 kb
Host smart-b19a3a13-04a8-457a-a94d-56255dcb190c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627628424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3627628424
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/141.rv_timer_random.1055414805
Short name T99
Test name
Test status
Simulation time 151318780351 ps
CPU time 283.24 seconds
Started Mar 31 12:31:22 PM PDT 24
Finished Mar 31 12:36:05 PM PDT 24
Peak memory 190796 kb
Host smart-83fe688b-ebf7-4bb7-a354-7fa3e377fa51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055414805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1055414805
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3398233687
Short name T140
Test name
Test status
Simulation time 1031917004016 ps
CPU time 644.72 seconds
Started Mar 31 12:31:02 PM PDT 24
Finished Mar 31 12:41:47 PM PDT 24
Peak memory 190844 kb
Host smart-3ada9de7-b956-442f-a467-078b3eda709b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398233687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3398233687
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.2729667790
Short name T25
Test name
Test status
Simulation time 525342956680 ps
CPU time 835.49 seconds
Started Mar 31 12:31:30 PM PDT 24
Finished Mar 31 12:45:26 PM PDT 24
Peak memory 190860 kb
Host smart-fc9db8a2-18bb-4623-912d-8c6e1085f737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729667790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2729667790
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.4160955897
Short name T256
Test name
Test status
Simulation time 358796315196 ps
CPU time 327.52 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:36:57 PM PDT 24
Peak memory 190872 kb
Host smart-babda93c-eb6a-4066-9315-cce39d315ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160955897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4160955897
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3757118601
Short name T180
Test name
Test status
Simulation time 578693247302 ps
CPU time 976.01 seconds
Started Mar 31 12:30:43 PM PDT 24
Finished Mar 31 12:46:59 PM PDT 24
Peak memory 190784 kb
Host smart-12b0d058-fd2e-435f-8eb6-857fdb4887b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757118601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3757118601
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.4047223636
Short name T279
Test name
Test status
Simulation time 133224413738 ps
CPU time 74.34 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:32:33 PM PDT 24
Peak memory 190768 kb
Host smart-68272788-2d07-46b1-9b01-ffcbd0fa1b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047223636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.4047223636
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2832081005
Short name T101
Test name
Test status
Simulation time 778960330493 ps
CPU time 1161 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:49:57 PM PDT 24
Peak memory 190824 kb
Host smart-d502b00b-642c-4b9c-b27b-77e093c09ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832081005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2832081005
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_random.2748062873
Short name T222
Test name
Test status
Simulation time 579247188262 ps
CPU time 306.6 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 190836 kb
Host smart-5aa1928a-7d41-4f37-9a7b-afe7c6ce4677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748062873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2748062873
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3475442547
Short name T179
Test name
Test status
Simulation time 279316795413 ps
CPU time 490.78 seconds
Started Mar 31 12:30:50 PM PDT 24
Finished Mar 31 12:39:01 PM PDT 24
Peak memory 190760 kb
Host smart-f1890e3f-aed6-466c-8ad5-fd55349569c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475442547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3475442547
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2209014635
Short name T440
Test name
Test status
Simulation time 95863041254 ps
CPU time 233.89 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:34:34 PM PDT 24
Peak memory 190732 kb
Host smart-27c677f9-ad08-4201-be3a-c1331dd5e578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209014635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2209014635
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random.2760004575
Short name T52
Test name
Test status
Simulation time 719586894094 ps
CPU time 1317.36 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:52:34 PM PDT 24
Peak memory 190836 kb
Host smart-7ef5b197-9d18-4e8d-ae89-301cb112db94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760004575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2760004575
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3208821622
Short name T310
Test name
Test status
Simulation time 1045106559838 ps
CPU time 349.06 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:37:06 PM PDT 24
Peak memory 190828 kb
Host smart-f47c941c-f901-462f-9e18-a9d9af00e04d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208821622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3208821622
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3353664553
Short name T192
Test name
Test status
Simulation time 449174093574 ps
CPU time 384 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:36:56 PM PDT 24
Peak memory 190872 kb
Host smart-04a60fc3-dd93-49ac-9599-c58f5d671191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353664553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3353664553
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.1152384071
Short name T131
Test name
Test status
Simulation time 124499860215 ps
CPU time 279.53 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:36:03 PM PDT 24
Peak memory 190808 kb
Host smart-a67b8ecb-ef5b-45f5-9b24-6fd6c4283201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152384071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1152384071
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2423031214
Short name T212
Test name
Test status
Simulation time 456056981079 ps
CPU time 538.35 seconds
Started Mar 31 12:31:18 PM PDT 24
Finished Mar 31 12:40:16 PM PDT 24
Peak memory 190656 kb
Host smart-8aec7a42-2747-4e32-97bd-1f18c8a8a7c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423031214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2423031214
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.2301383557
Short name T184
Test name
Test status
Simulation time 125151084548 ps
CPU time 405.73 seconds
Started Mar 31 12:30:39 PM PDT 24
Finished Mar 31 12:37:25 PM PDT 24
Peak memory 190892 kb
Host smart-72e94880-b475-4aca-9f91-08563a103ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301383557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2301383557
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.4074163593
Short name T122
Test name
Test status
Simulation time 62928019775 ps
CPU time 104.18 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:32:32 PM PDT 24
Peak memory 190796 kb
Host smart-e505d3b0-b73d-40d7-bb63-accd32727a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074163593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4074163593
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.139574812
Short name T115
Test name
Test status
Simulation time 850920268317 ps
CPU time 270.71 seconds
Started Mar 31 12:31:10 PM PDT 24
Finished Mar 31 12:35:41 PM PDT 24
Peak memory 194040 kb
Host smart-deeef302-1b17-469e-a9d9-29f8827ca101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139574812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.139574812
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3406941225
Short name T167
Test name
Test status
Simulation time 167083004207 ps
CPU time 274.96 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:35:51 PM PDT 24
Peak memory 182700 kb
Host smart-40b77684-91fc-48c1-a78d-24c1a060e4e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406941225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3406941225
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/98.rv_timer_random.1899133546
Short name T254
Test name
Test status
Simulation time 349214528644 ps
CPU time 168.24 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:34:11 PM PDT 24
Peak memory 190896 kb
Host smart-ee8632bc-967e-4469-8d1b-7146fda9c459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899133546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1899133546
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3508892561
Short name T335
Test name
Test status
Simulation time 224217205481 ps
CPU time 195.93 seconds
Started Mar 31 12:30:35 PM PDT 24
Finished Mar 31 12:33:51 PM PDT 24
Peak memory 182644 kb
Host smart-ac6395b8-a57c-43b5-b187-f61a14730ac7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508892561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3508892561
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/131.rv_timer_random.2492006135
Short name T308
Test name
Test status
Simulation time 679339329594 ps
CPU time 439.98 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:38:45 PM PDT 24
Peak memory 190824 kb
Host smart-a810e8ef-b331-46db-8329-a5e6b9b0dfb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492006135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2492006135
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1453953294
Short name T197
Test name
Test status
Simulation time 388569660470 ps
CPU time 1066.39 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 12:49:07 PM PDT 24
Peak memory 190884 kb
Host smart-d57d338d-b59d-4250-8ed3-2b9e732b648e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453953294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1453953294
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1934770713
Short name T341
Test name
Test status
Simulation time 88476402154 ps
CPU time 160.69 seconds
Started Mar 31 12:31:22 PM PDT 24
Finished Mar 31 12:34:02 PM PDT 24
Peak memory 190832 kb
Host smart-ab612853-f944-43bf-947b-4fba10158039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934770713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1934770713
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2746022105
Short name T292
Test name
Test status
Simulation time 448284469835 ps
CPU time 443.02 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:38:46 PM PDT 24
Peak memory 190892 kb
Host smart-373a12aa-7170-46a3-8ab4-546ab42bdeec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746022105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2746022105
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.602641458
Short name T116
Test name
Test status
Simulation time 453791981622 ps
CPU time 261.27 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:35:48 PM PDT 24
Peak memory 190876 kb
Host smart-8f6aae76-6494-4786-b5e9-827854dc8e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602641458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.602641458
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2377974456
Short name T136
Test name
Test status
Simulation time 310296069186 ps
CPU time 187.23 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:34:34 PM PDT 24
Peak memory 193620 kb
Host smart-66eaa154-0ac6-4e0f-9ca9-473bb4f71952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377974456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2377974456
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2560586153
Short name T139
Test name
Test status
Simulation time 85995359778 ps
CPU time 101.21 seconds
Started Mar 31 12:31:31 PM PDT 24
Finished Mar 31 12:33:13 PM PDT 24
Peak memory 190828 kb
Host smart-d0d9e2fb-1294-4dbe-98d0-ef1bc4208721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560586153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2560586153
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3848621477
Short name T133
Test name
Test status
Simulation time 193927274301 ps
CPU time 566.72 seconds
Started Mar 31 12:31:27 PM PDT 24
Finished Mar 31 12:40:54 PM PDT 24
Peak memory 193596 kb
Host smart-9728f92f-19e5-479c-92b6-baceab81e545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848621477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3848621477
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3726479988
Short name T130
Test name
Test status
Simulation time 76716410682 ps
CPU time 116.97 seconds
Started Mar 31 12:31:32 PM PDT 24
Finished Mar 31 12:33:29 PM PDT 24
Peak memory 193764 kb
Host smart-39e7b96d-484a-42ed-b680-12fc8e755eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726479988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3726479988
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.643471695
Short name T53
Test name
Test status
Simulation time 300606989956 ps
CPU time 550.45 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:39:59 PM PDT 24
Peak memory 190884 kb
Host smart-c510c565-6990-44aa-975f-3b04cca1f85d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643471695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
643471695
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1964940770
Short name T176
Test name
Test status
Simulation time 1929700212497 ps
CPU time 1015.4 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:47:43 PM PDT 24
Peak memory 190816 kb
Host smart-2d7c2f95-e24b-4be3-856b-f98eff368b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964940770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1964940770
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2241768443
Short name T252
Test name
Test status
Simulation time 238448334979 ps
CPU time 365.05 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:36:51 PM PDT 24
Peak memory 182640 kb
Host smart-2b50cbbf-5b57-496a-bb91-2303a403626d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241768443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2241768443
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random.1803784743
Short name T157
Test name
Test status
Simulation time 79896443902 ps
CPU time 129.63 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:33:22 PM PDT 24
Peak memory 190824 kb
Host smart-721bcd02-1a69-4d29-aff2-9494154f1cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803784743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1803784743
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3169336705
Short name T9
Test name
Test status
Simulation time 462402141571 ps
CPU time 370.72 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:37:30 PM PDT 24
Peak memory 190804 kb
Host smart-bc41f277-a1f9-4a0b-91bb-a4aa1c2789ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169336705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3169336705
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1147813772
Short name T519
Test name
Test status
Simulation time 2145132586 ps
CPU time 1.67 seconds
Started Mar 31 12:23:30 PM PDT 24
Finished Mar 31 12:23:32 PM PDT 24
Peak memory 195172 kb
Host smart-c6e1b310-5317-4ba5-9ea7-42d091f2168c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147813772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1147813772
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3103703361
Short name T313
Test name
Test status
Simulation time 49861673362 ps
CPU time 44.72 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:31:21 PM PDT 24
Peak memory 182592 kb
Host smart-8635dba8-b19c-4892-8af0-03e3110b0963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103703361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3103703361
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.148382597
Short name T315
Test name
Test status
Simulation time 4853461761494 ps
CPU time 728.05 seconds
Started Mar 31 12:30:38 PM PDT 24
Finished Mar 31 12:42:46 PM PDT 24
Peak memory 195472 kb
Host smart-7f6c19a8-8141-4c0c-ae01-ced5089f7d76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148382597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.148382597
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.810067565
Short name T172
Test name
Test status
Simulation time 112124689292 ps
CPU time 65.58 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:31:43 PM PDT 24
Peak memory 182680 kb
Host smart-577154ba-b87b-4625-9c8a-adc140fd38f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810067565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.810067565
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/106.rv_timer_random.3883691277
Short name T274
Test name
Test status
Simulation time 80804240564 ps
CPU time 872.48 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:46:02 PM PDT 24
Peak memory 190860 kb
Host smart-aa7708b7-1ff9-475d-bee1-669ef2315f23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883691277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3883691277
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.997155758
Short name T233
Test name
Test status
Simulation time 52067620477 ps
CPU time 92.24 seconds
Started Mar 31 12:31:27 PM PDT 24
Finished Mar 31 12:33:00 PM PDT 24
Peak memory 193488 kb
Host smart-6cf289b0-6b12-428e-9016-6a26788c1750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997155758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.997155758
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.3616942856
Short name T44
Test name
Test status
Simulation time 85255429344 ps
CPU time 139.53 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:33:00 PM PDT 24
Peak memory 190828 kb
Host smart-88760fd1-af26-4b5f-bec6-49e287188cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616942856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3616942856
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.108269918
Short name T446
Test name
Test status
Simulation time 20319255931 ps
CPU time 32.23 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:31:53 PM PDT 24
Peak memory 182668 kb
Host smart-4351ad31-4e04-4244-b939-5a253ea061f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108269918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.108269918
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.395799428
Short name T1
Test name
Test status
Simulation time 57764921739 ps
CPU time 13.02 seconds
Started Mar 31 12:31:24 PM PDT 24
Finished Mar 31 12:31:38 PM PDT 24
Peak memory 182632 kb
Host smart-14e1541d-d3d3-4cd8-863e-553e1ac499f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395799428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.395799428
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1600332818
Short name T272
Test name
Test status
Simulation time 39624914547 ps
CPU time 126.02 seconds
Started Mar 31 12:31:28 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 182684 kb
Host smart-af774c87-b554-4e61-b152-d4648d08bec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600332818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1600332818
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.269062941
Short name T309
Test name
Test status
Simulation time 659314539708 ps
CPU time 325.64 seconds
Started Mar 31 12:31:22 PM PDT 24
Finished Mar 31 12:36:47 PM PDT 24
Peak memory 190904 kb
Host smart-f51d298d-860d-4ebb-b254-3036cf1b9d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269062941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.269062941
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2449375955
Short name T24
Test name
Test status
Simulation time 4541785621018 ps
CPU time 1033.52 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:47:47 PM PDT 24
Peak memory 190836 kb
Host smart-abb2eed1-5d11-405d-ae50-8c1a215d1b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449375955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2449375955
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/167.rv_timer_random.229328220
Short name T149
Test name
Test status
Simulation time 327560456271 ps
CPU time 684.26 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:42:51 PM PDT 24
Peak memory 190648 kb
Host smart-95f4e299-5eae-4d96-b503-a28f44a20230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229328220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.229328220
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2779698714
Short name T20
Test name
Test status
Simulation time 564418654265 ps
CPU time 528.53 seconds
Started Mar 31 12:30:55 PM PDT 24
Finished Mar 31 12:39:48 PM PDT 24
Peak memory 190892 kb
Host smart-b53b5168-d655-440b-ad02-3e40469fb2b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779698714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2779698714
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.735022514
Short name T314
Test name
Test status
Simulation time 459573767813 ps
CPU time 236.05 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:34:36 PM PDT 24
Peak memory 182704 kb
Host smart-154a6ae9-627f-4ef8-a13c-bb9c04ecd1b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735022514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.735022514
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.3731090212
Short name T257
Test name
Test status
Simulation time 176923981842 ps
CPU time 2312.27 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 01:09:18 PM PDT 24
Peak memory 190760 kb
Host smart-27eda096-229e-4d0e-84a3-081cf2343292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731090212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3731090212
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.3692939372
Short name T269
Test name
Test status
Simulation time 33258321890 ps
CPU time 313.21 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 12:36:25 PM PDT 24
Peak memory 182692 kb
Host smart-71addbcb-bfda-4ab9-a705-3358ad58d2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692939372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3692939372
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.4145352427
Short name T79
Test name
Test status
Simulation time 87347749252 ps
CPU time 974.17 seconds
Started Mar 31 12:30:55 PM PDT 24
Finished Mar 31 12:47:10 PM PDT 24
Peak memory 190796 kb
Host smart-ad68d030-0db2-465e-89b0-63d5312e9307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145352427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4145352427
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1735328022
Short name T146
Test name
Test status
Simulation time 342938116099 ps
CPU time 1222.59 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:51:11 PM PDT 24
Peak memory 190848 kb
Host smart-804df00e-21a0-46e0-b49a-7de4fdf64d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735328022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1735328022
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3150525079
Short name T177
Test name
Test status
Simulation time 72359759868 ps
CPU time 66.64 seconds
Started Mar 31 12:31:05 PM PDT 24
Finished Mar 31 12:32:12 PM PDT 24
Peak memory 182660 kb
Host smart-f0d89a16-2bc6-4a38-867b-889f408e0734
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150525079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3150525079
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random.3274846988
Short name T209
Test name
Test status
Simulation time 584720038497 ps
CPU time 685.33 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:42:39 PM PDT 24
Peak memory 190872 kb
Host smart-858d3255-955b-4393-93b0-74de079d7a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274846988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3274846988
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.140622113
Short name T201
Test name
Test status
Simulation time 189714020982 ps
CPU time 363.17 seconds
Started Mar 31 12:30:50 PM PDT 24
Finished Mar 31 12:36:53 PM PDT 24
Peak memory 190792 kb
Host smart-80cd995b-6cdf-4d46-a5d2-c8fe9e13e762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140622113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.140622113
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random.2806643884
Short name T297
Test name
Test status
Simulation time 324201441094 ps
CPU time 302.72 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:36:18 PM PDT 24
Peak memory 190880 kb
Host smart-c02e947f-a2aa-4da9-a5f0-e327d41ea8c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806643884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2806643884
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1668254170
Short name T278
Test name
Test status
Simulation time 1043430950383 ps
CPU time 970.21 seconds
Started Mar 31 12:31:09 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 182724 kb
Host smart-143d9210-57d1-4c0b-9710-56cd98d6d678
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668254170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1668254170
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4212636560
Short name T123
Test name
Test status
Simulation time 17184139701 ps
CPU time 9.78 seconds
Started Mar 31 12:31:18 PM PDT 24
Finished Mar 31 12:31:28 PM PDT 24
Peak memory 182656 kb
Host smart-958686fe-9d7e-4ae0-8427-3a942db467d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212636560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4212636560
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3564567070
Short name T320
Test name
Test status
Simulation time 6265431892 ps
CPU time 31.61 seconds
Started Mar 31 12:30:35 PM PDT 24
Finished Mar 31 12:31:07 PM PDT 24
Peak memory 182608 kb
Host smart-9a299b68-1c98-4cdb-826f-dd3a2211c8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564567070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3564567070
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.623441396
Short name T562
Test name
Test status
Simulation time 106622888 ps
CPU time 1.56 seconds
Started Mar 31 12:24:30 PM PDT 24
Finished Mar 31 12:24:31 PM PDT 24
Peak memory 190864 kb
Host smart-f74ddc67-a451-45c2-935c-449ee3788f87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623441396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.623441396
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3257779882
Short name T522
Test name
Test status
Simulation time 54253047 ps
CPU time 0.56 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 191796 kb
Host smart-4ce42bff-5602-4f12-9a18-61a6cabccb8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257779882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3257779882
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4192745845
Short name T546
Test name
Test status
Simulation time 20966892 ps
CPU time 1.04 seconds
Started Mar 31 12:25:47 PM PDT 24
Finished Mar 31 12:25:48 PM PDT 24
Peak memory 197592 kb
Host smart-f64aab40-4488-43b2-b3e9-e605298fde64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192745845 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.4192745845
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3737548622
Short name T72
Test name
Test status
Simulation time 29622173 ps
CPU time 0.56 seconds
Started Mar 31 12:23:27 PM PDT 24
Finished Mar 31 12:23:28 PM PDT 24
Peak memory 182612 kb
Host smart-eb5f797e-0859-4921-939b-b8d9cc02a09d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737548622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3737548622
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.967785205
Short name T460
Test name
Test status
Simulation time 149807532 ps
CPU time 0.52 seconds
Started Mar 31 12:23:03 PM PDT 24
Finished Mar 31 12:23:04 PM PDT 24
Peak memory 182132 kb
Host smart-4571501d-bb51-4853-a137-85af50542f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967785205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.967785205
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1305066627
Short name T544
Test name
Test status
Simulation time 19603861 ps
CPU time 0.59 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 191904 kb
Host smart-01af876e-9d54-4391-8ac0-a894d84dbf88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305066627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1305066627
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.528604234
Short name T509
Test name
Test status
Simulation time 395426350 ps
CPU time 2.33 seconds
Started Mar 31 12:22:20 PM PDT 24
Finished Mar 31 12:22:23 PM PDT 24
Peak memory 196476 kb
Host smart-0136ff0c-0574-4fad-b8d3-530f86e37477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528604234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.528604234
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1712298602
Short name T527
Test name
Test status
Simulation time 266208524 ps
CPU time 0.71 seconds
Started Mar 31 12:23:09 PM PDT 24
Finished Mar 31 12:23:10 PM PDT 24
Peak memory 192364 kb
Host smart-8165279d-002e-407e-b4db-61df9dcbe138
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712298602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1712298602
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1306936304
Short name T456
Test name
Test status
Simulation time 456737164 ps
CPU time 1.57 seconds
Started Mar 31 12:23:07 PM PDT 24
Finished Mar 31 12:23:09 PM PDT 24
Peak memory 193728 kb
Host smart-c0f194bc-e554-4694-b698-a54b9ab44c64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306936304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1306936304
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.887077328
Short name T543
Test name
Test status
Simulation time 65542141 ps
CPU time 0.56 seconds
Started Mar 31 12:23:27 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 182612 kb
Host smart-b2a2164b-82a2-4deb-891d-3b67349317de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887077328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.887077328
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3425637577
Short name T550
Test name
Test status
Simulation time 73908379 ps
CPU time 0.66 seconds
Started Mar 31 12:23:13 PM PDT 24
Finished Mar 31 12:23:14 PM PDT 24
Peak memory 194000 kb
Host smart-6e439255-17be-4cc4-bac0-9f677cee9e91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425637577 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3425637577
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3006926253
Short name T479
Test name
Test status
Simulation time 41812579 ps
CPU time 0.6 seconds
Started Mar 31 12:24:29 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 181796 kb
Host smart-426e74ba-546a-482f-81cb-2e03c6aa3e0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006926253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3006926253
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3338324558
Short name T475
Test name
Test status
Simulation time 12843130 ps
CPU time 0.54 seconds
Started Mar 31 12:24:30 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 182324 kb
Host smart-f0710480-325f-4d0f-be3d-6ad48b53d14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338324558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3338324558
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4288148729
Short name T529
Test name
Test status
Simulation time 21754349 ps
CPU time 0.6 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 191308 kb
Host smart-f578d630-d7a0-4955-8bf3-3979b224fa23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288148729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4288148729
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3737354249
Short name T506
Test name
Test status
Simulation time 85979585 ps
CPU time 2.21 seconds
Started Mar 31 12:23:06 PM PDT 24
Finished Mar 31 12:23:08 PM PDT 24
Peak memory 197448 kb
Host smart-aae58ab9-087f-4145-b3da-f392d46a0463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737354249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3737354249
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1506190287
Short name T94
Test name
Test status
Simulation time 124757564 ps
CPU time 1.35 seconds
Started Mar 31 12:23:06 PM PDT 24
Finished Mar 31 12:23:08 PM PDT 24
Peak memory 195288 kb
Host smart-b97d2a5e-6ebe-4da6-80cf-7b7fe5ba0d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506190287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1506190287
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.179170938
Short name T537
Test name
Test status
Simulation time 66177635 ps
CPU time 0.67 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 194172 kb
Host smart-5d851626-42b7-445e-a961-90e89d85b81a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179170938 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.179170938
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.202574783
Short name T561
Test name
Test status
Simulation time 31341634 ps
CPU time 0.59 seconds
Started Mar 31 12:23:25 PM PDT 24
Finished Mar 31 12:23:26 PM PDT 24
Peak memory 182548 kb
Host smart-04bba391-ad66-4735-9f9a-129ea0f4a56a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202574783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.202574783
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.774732395
Short name T557
Test name
Test status
Simulation time 11999611 ps
CPU time 0.61 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 182320 kb
Host smart-b24ed775-f8ee-4ba0-8eb3-cbe2a513f265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774732395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.774732395
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1685376146
Short name T87
Test name
Test status
Simulation time 40159418 ps
CPU time 0.79 seconds
Started Mar 31 12:23:08 PM PDT 24
Finished Mar 31 12:23:10 PM PDT 24
Peak memory 191588 kb
Host smart-ba5d0b5c-5724-494f-a0fe-c1a296bef5f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685376146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1685376146
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2127847336
Short name T542
Test name
Test status
Simulation time 84378127 ps
CPU time 1.84 seconds
Started Mar 31 12:23:24 PM PDT 24
Finished Mar 31 12:23:26 PM PDT 24
Peak memory 197440 kb
Host smart-a6c7f6f9-b313-4af4-9437-131702a9f8f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127847336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2127847336
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1802446453
Short name T454
Test name
Test status
Simulation time 46460044 ps
CPU time 0.75 seconds
Started Mar 31 12:23:30 PM PDT 24
Finished Mar 31 12:23:31 PM PDT 24
Peak memory 195516 kb
Host smart-0eeb9a1f-27e4-42cd-91a4-127d0a54f6a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802446453 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1802446453
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1089796664
Short name T514
Test name
Test status
Simulation time 34210356 ps
CPU time 0.55 seconds
Started Mar 31 12:23:31 PM PDT 24
Finished Mar 31 12:23:32 PM PDT 24
Peak memory 182560 kb
Host smart-e13202c6-f51f-4927-926b-571a0a26f21f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089796664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1089796664
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3521097445
Short name T513
Test name
Test status
Simulation time 36023670 ps
CPU time 0.53 seconds
Started Mar 31 12:23:41 PM PDT 24
Finished Mar 31 12:23:47 PM PDT 24
Peak memory 182160 kb
Host smart-0aabd49a-ac5b-46f2-b553-39fed0bcfaab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521097445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3521097445
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4000918780
Short name T536
Test name
Test status
Simulation time 665654983 ps
CPU time 0.81 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 193376 kb
Host smart-43b64b26-252f-469f-ab0c-847e44aae3ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000918780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.4000918780
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2244896129
Short name T463
Test name
Test status
Simulation time 89927039 ps
CPU time 1.13 seconds
Started Mar 31 12:23:31 PM PDT 24
Finished Mar 31 12:23:32 PM PDT 24
Peak memory 197568 kb
Host smart-adbe154f-3a11-49b8-b321-08bc9aa129bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244896129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2244896129
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3499429322
Short name T571
Test name
Test status
Simulation time 101374702 ps
CPU time 1.36 seconds
Started Mar 31 12:23:21 PM PDT 24
Finished Mar 31 12:23:22 PM PDT 24
Peak memory 183544 kb
Host smart-c82222bd-ebe7-4584-971a-00624fcfc5e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499429322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3499429322
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2890342814
Short name T469
Test name
Test status
Simulation time 102864716 ps
CPU time 0.88 seconds
Started Mar 31 12:23:21 PM PDT 24
Finished Mar 31 12:23:23 PM PDT 24
Peak memory 196704 kb
Host smart-a2a994a8-0276-4744-94c1-20418b160619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890342814 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2890342814
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1608653022
Short name T533
Test name
Test status
Simulation time 14469290 ps
CPU time 0.56 seconds
Started Mar 31 12:23:21 PM PDT 24
Finished Mar 31 12:23:21 PM PDT 24
Peak memory 182548 kb
Host smart-4d09ce8d-b0df-4a96-98d8-1402c32bbbb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608653022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1608653022
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.44441067
Short name T548
Test name
Test status
Simulation time 15116705 ps
CPU time 0.55 seconds
Started Mar 31 12:23:21 PM PDT 24
Finished Mar 31 12:23:21 PM PDT 24
Peak memory 182476 kb
Host smart-8edaaaa4-3372-432f-b1a1-569f34e86ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44441067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.44441067
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.525997864
Short name T512
Test name
Test status
Simulation time 21977309 ps
CPU time 0.66 seconds
Started Mar 31 12:23:30 PM PDT 24
Finished Mar 31 12:23:31 PM PDT 24
Peak memory 191936 kb
Host smart-6a4080f2-bf50-413a-8003-be1ed517ef8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525997864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.525997864
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3354776540
Short name T565
Test name
Test status
Simulation time 31861117 ps
CPU time 1.26 seconds
Started Mar 31 12:23:33 PM PDT 24
Finished Mar 31 12:23:35 PM PDT 24
Peak memory 191140 kb
Host smart-b3872178-762b-4bd4-b8ad-9931992fe906
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354776540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3354776540
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1081478881
Short name T474
Test name
Test status
Simulation time 368542319 ps
CPU time 1.04 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 194512 kb
Host smart-d1949214-f438-496f-a1c4-9491ec1a03a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081478881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1081478881
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3436465077
Short name T518
Test name
Test status
Simulation time 91415428 ps
CPU time 0.86 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 196116 kb
Host smart-97b8c994-7f58-4388-ae50-3c474ff13a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436465077 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3436465077
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.292901863
Short name T74
Test name
Test status
Simulation time 53204481 ps
CPU time 0.59 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 182580 kb
Host smart-06d50af0-52f4-4f1b-8ee3-459d0dc1675d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292901863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.292901863
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2016393816
Short name T471
Test name
Test status
Simulation time 36351945 ps
CPU time 0.51 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:41 PM PDT 24
Peak memory 182164 kb
Host smart-86537a37-b0b0-4179-85a6-914dee9624b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016393816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2016393816
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.116263956
Short name T521
Test name
Test status
Simulation time 53127089 ps
CPU time 0.61 seconds
Started Mar 31 12:23:34 PM PDT 24
Finished Mar 31 12:23:35 PM PDT 24
Peak memory 191376 kb
Host smart-0a568a33-ef6c-45b1-b4ce-e0728040f05e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116263956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.116263956
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2852628521
Short name T555
Test name
Test status
Simulation time 145555771 ps
CPU time 1.74 seconds
Started Mar 31 12:24:02 PM PDT 24
Finished Mar 31 12:24:04 PM PDT 24
Peak memory 197600 kb
Host smart-9980fe46-fcb1-4e61-8b98-0cd07eed46d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852628521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2852628521
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3188118607
Short name T545
Test name
Test status
Simulation time 43543056 ps
CPU time 0.8 seconds
Started Mar 31 12:23:33 PM PDT 24
Finished Mar 31 12:23:34 PM PDT 24
Peak memory 192984 kb
Host smart-20222439-7233-47b4-a8eb-d8119809886b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188118607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3188118607
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2183626936
Short name T468
Test name
Test status
Simulation time 23473958 ps
CPU time 0.93 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 197328 kb
Host smart-acc60ac4-0f73-44e5-8654-921ba5a2515e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183626936 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2183626936
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3347319521
Short name T498
Test name
Test status
Simulation time 25650110 ps
CPU time 0.57 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 180984 kb
Host smart-ae8e8980-8d21-4f3b-a907-216797ab8437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347319521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3347319521
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2469364373
Short name T524
Test name
Test status
Simulation time 13798638 ps
CPU time 0.55 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:24 PM PDT 24
Peak memory 182352 kb
Host smart-e44109a5-d337-4c85-acda-173439bf9152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469364373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2469364373
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.319496813
Short name T482
Test name
Test status
Simulation time 61936805 ps
CPU time 0.62 seconds
Started Mar 31 12:23:32 PM PDT 24
Finished Mar 31 12:23:33 PM PDT 24
Peak memory 191896 kb
Host smart-e14ebb94-22fc-480c-80c8-7b34f84fd64a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319496813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.319496813
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3855516685
Short name T534
Test name
Test status
Simulation time 152296200 ps
CPU time 1.97 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:38 PM PDT 24
Peak memory 197532 kb
Host smart-07318833-f758-43a1-9d53-86b74fe7a2e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855516685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3855516685
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.380431269
Short name T502
Test name
Test status
Simulation time 343828578 ps
CPU time 1.35 seconds
Started Mar 31 12:23:33 PM PDT 24
Finished Mar 31 12:23:35 PM PDT 24
Peak memory 183252 kb
Host smart-b5d62355-91e2-4688-9ada-bc772c1385f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380431269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.380431269
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3190434393
Short name T554
Test name
Test status
Simulation time 29465270 ps
CPU time 0.83 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 192896 kb
Host smart-69de1147-6f7e-43c5-ad34-f29b57e7f0c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190434393 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3190434393
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1866426283
Short name T558
Test name
Test status
Simulation time 109026848 ps
CPU time 0.56 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 181912 kb
Host smart-59e23791-8aeb-4b1d-a96a-5a32de6c46a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866426283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1866426283
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.387164789
Short name T568
Test name
Test status
Simulation time 34921743 ps
CPU time 0.57 seconds
Started Mar 31 12:23:27 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 182416 kb
Host smart-0e5a06d6-7df4-423b-8ba9-b87eecbe05c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387164789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.387164789
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1828399742
Short name T86
Test name
Test status
Simulation time 24508268 ps
CPU time 0.57 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:24 PM PDT 24
Peak memory 191068 kb
Host smart-f8c945fc-e282-42fa-927d-414a7cb1a3a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828399742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1828399742
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3384259461
Short name T539
Test name
Test status
Simulation time 197126146 ps
CPU time 1.95 seconds
Started Mar 31 12:23:30 PM PDT 24
Finished Mar 31 12:23:32 PM PDT 24
Peak memory 197456 kb
Host smart-cfbab353-12ac-43be-8477-16023be399b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384259461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3384259461
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3747287422
Short name T510
Test name
Test status
Simulation time 81601610 ps
CPU time 0.85 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:28 PM PDT 24
Peak memory 193460 kb
Host smart-1fadd8b9-20a7-4810-a95c-f3cb94bca47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747287422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3747287422
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.688565841
Short name T503
Test name
Test status
Simulation time 125001194 ps
CPU time 1.08 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:37 PM PDT 24
Peak memory 197560 kb
Host smart-4193623e-627f-4cf2-9f63-ae40c399c152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688565841 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.688565841
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2569145806
Short name T91
Test name
Test status
Simulation time 18073592 ps
CPU time 0.6 seconds
Started Mar 31 12:23:20 PM PDT 24
Finished Mar 31 12:23:21 PM PDT 24
Peak memory 182588 kb
Host smart-79f33537-a7ea-4602-be92-8da3edd3e5b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569145806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2569145806
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1622449941
Short name T476
Test name
Test status
Simulation time 28964531 ps
CPU time 0.54 seconds
Started Mar 31 12:23:24 PM PDT 24
Finished Mar 31 12:23:25 PM PDT 24
Peak memory 182472 kb
Host smart-62aa90de-fe48-430e-b0c7-75bd320adb8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622449941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1622449941
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1458899199
Short name T556
Test name
Test status
Simulation time 39423348 ps
CPU time 0.67 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 190312 kb
Host smart-ff852eb3-4a56-4f2a-941d-ee2401736990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458899199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1458899199
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2552838517
Short name T492
Test name
Test status
Simulation time 727233228 ps
CPU time 1.48 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:30 PM PDT 24
Peak memory 197440 kb
Host smart-a76bb5cb-ae10-48e3-be87-10b8d0db4153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552838517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2552838517
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4066945338
Short name T96
Test name
Test status
Simulation time 98576680 ps
CPU time 1.26 seconds
Started Mar 31 12:23:25 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 183368 kb
Host smart-330e24bf-4eb6-47a2-aec8-2830fe31be54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066945338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.4066945338
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3136890359
Short name T499
Test name
Test status
Simulation time 386924391 ps
CPU time 0.74 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:37 PM PDT 24
Peak memory 194308 kb
Host smart-0ad163d4-952b-4837-a4d2-17eed3a727b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136890359 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3136890359
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3917866884
Short name T43
Test name
Test status
Simulation time 27886537 ps
CPU time 0.55 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:37 PM PDT 24
Peak memory 182640 kb
Host smart-e80dc4fa-4b81-4cf7-a22e-e9f034175dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917866884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3917866884
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1858829818
Short name T563
Test name
Test status
Simulation time 15661000 ps
CPU time 0.55 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:37 PM PDT 24
Peak memory 182576 kb
Host smart-77608ee7-c623-4e83-ace2-b8c860b94f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858829818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1858829818
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2562686457
Short name T89
Test name
Test status
Simulation time 15312786 ps
CPU time 0.65 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 192280 kb
Host smart-ebfd2b6d-ff4c-4241-a6c0-67acc346836c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562686457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2562686457
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1265655145
Short name T462
Test name
Test status
Simulation time 43669574 ps
CPU time 2.08 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:38 PM PDT 24
Peak memory 195932 kb
Host smart-c7ee2115-5673-43cf-849e-abcecd938f04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265655145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1265655145
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2384353030
Short name T93
Test name
Test status
Simulation time 88589846 ps
CPU time 0.81 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 193680 kb
Host smart-bc031f38-5d78-4b31-a5bc-6b90053ef865
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384353030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2384353030
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3841001090
Short name T455
Test name
Test status
Simulation time 284271594 ps
CPU time 0.75 seconds
Started Mar 31 12:23:31 PM PDT 24
Finished Mar 31 12:23:32 PM PDT 24
Peak memory 195000 kb
Host smart-0066b863-1d98-43c0-b76d-042622e78a84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841001090 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3841001090
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2854935241
Short name T481
Test name
Test status
Simulation time 16281620 ps
CPU time 0.56 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 180972 kb
Host smart-ae5bde47-4368-4953-b2d7-2523292db28a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854935241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2854935241
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.305116911
Short name T448
Test name
Test status
Simulation time 35482603 ps
CPU time 0.53 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 180320 kb
Host smart-fcf07266-8518-4201-b289-e57560471721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305116911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.305116911
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.983212575
Short name T85
Test name
Test status
Simulation time 15478233 ps
CPU time 0.65 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 189944 kb
Host smart-bb4eb8d0-162d-4f3f-9b65-2b7f4ac4e93c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983212575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.983212575
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3863364845
Short name T450
Test name
Test status
Simulation time 119396521 ps
CPU time 1.19 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:37 PM PDT 24
Peak memory 196872 kb
Host smart-5c037171-46ff-41db-aabb-b6f0acc131b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863364845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3863364845
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2019520736
Short name T531
Test name
Test status
Simulation time 402855524 ps
CPU time 1.3 seconds
Started Mar 31 12:23:31 PM PDT 24
Finished Mar 31 12:23:33 PM PDT 24
Peak memory 195196 kb
Host smart-537614c2-5226-4d9f-a71b-4786551e28c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019520736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2019520736
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2318529137
Short name T552
Test name
Test status
Simulation time 14322214 ps
CPU time 0.65 seconds
Started Mar 31 12:23:38 PM PDT 24
Finished Mar 31 12:23:38 PM PDT 24
Peak memory 194136 kb
Host smart-b2d1ae02-e7d6-4189-9774-0e4b0b4b7076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318529137 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2318529137
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.304821428
Short name T69
Test name
Test status
Simulation time 26907143 ps
CPU time 0.56 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 182604 kb
Host smart-6faaf35e-8da6-4d72-a4cc-c26905073953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304821428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.304821428
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2902032778
Short name T473
Test name
Test status
Simulation time 17515163 ps
CPU time 0.55 seconds
Started Mar 31 12:23:46 PM PDT 24
Finished Mar 31 12:23:47 PM PDT 24
Peak memory 182520 kb
Host smart-5442127d-5d2c-4c65-8102-e0868b727f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902032778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2902032778
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.988278686
Short name T494
Test name
Test status
Simulation time 49511905 ps
CPU time 0.68 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 192548 kb
Host smart-d09b298b-12a2-492e-8303-4a802a9fe8e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988278686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.988278686
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3128574211
Short name T485
Test name
Test status
Simulation time 71457610 ps
CPU time 1.54 seconds
Started Mar 31 12:23:41 PM PDT 24
Finished Mar 31 12:23:43 PM PDT 24
Peak memory 197480 kb
Host smart-4468c36b-e8a2-4f72-8533-43b8ea7a7877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128574211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3128574211
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2958209661
Short name T487
Test name
Test status
Simulation time 51908842 ps
CPU time 0.87 seconds
Started Mar 31 12:23:31 PM PDT 24
Finished Mar 31 12:23:33 PM PDT 24
Peak memory 182152 kb
Host smart-77a76797-211c-4b19-8b55-145c06c52c73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958209661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2958209661
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.286165760
Short name T525
Test name
Test status
Simulation time 69297437 ps
CPU time 0.58 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 182468 kb
Host smart-a05d0ab9-9807-4d5e-b111-f8520bce7431
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286165760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.286165760
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1055641037
Short name T466
Test name
Test status
Simulation time 1620618862 ps
CPU time 3.59 seconds
Started Mar 31 12:23:09 PM PDT 24
Finished Mar 31 12:23:13 PM PDT 24
Peak memory 190972 kb
Host smart-ca0f1089-18b7-41bb-812e-ef22aa26e7a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055641037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1055641037
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3333484947
Short name T92
Test name
Test status
Simulation time 49832257 ps
CPU time 0.63 seconds
Started Mar 31 12:24:29 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 181560 kb
Host smart-a4200a79-9ff3-4a8e-9721-5f203bbafedd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333484947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3333484947
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3857094923
Short name T29
Test name
Test status
Simulation time 17560769 ps
CPU time 0.61 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 191924 kb
Host smart-c80eadf6-73bf-432d-8ea4-08add1ca1b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857094923 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3857094923
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.813578386
Short name T65
Test name
Test status
Simulation time 36914134 ps
CPU time 0.56 seconds
Started Mar 31 12:23:30 PM PDT 24
Finished Mar 31 12:23:30 PM PDT 24
Peak memory 182612 kb
Host smart-1810b66b-5f63-4c8b-9f0e-ccf04ea65261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813578386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.813578386
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.234529615
Short name T459
Test name
Test status
Simulation time 34343779 ps
CPU time 0.53 seconds
Started Mar 31 12:23:29 PM PDT 24
Finished Mar 31 12:23:31 PM PDT 24
Peak memory 181980 kb
Host smart-d636b416-1a68-45e1-a9d8-c689d0a7fee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234529615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.234529615
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3004142968
Short name T90
Test name
Test status
Simulation time 26530987 ps
CPU time 0.73 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 189984 kb
Host smart-1ac63089-bdc4-43e9-8894-4a12db6e46c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004142968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3004142968
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2481788989
Short name T508
Test name
Test status
Simulation time 584414368 ps
CPU time 3.23 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:27 PM PDT 24
Peak memory 197272 kb
Host smart-2cdfe060-4093-41da-9c30-ec70105cd9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481788989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2481788989
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2750337823
Short name T28
Test name
Test status
Simulation time 185288607 ps
CPU time 1.01 seconds
Started Mar 31 12:23:30 PM PDT 24
Finished Mar 31 12:23:31 PM PDT 24
Peak memory 183312 kb
Host smart-bb8b0325-295c-45ad-a85a-479c4b00e223
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750337823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2750337823
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2481717642
Short name T515
Test name
Test status
Simulation time 27483650 ps
CPU time 0.52 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:23:43 PM PDT 24
Peak memory 182416 kb
Host smart-2f0683e5-c8d6-4efe-a199-9ea0def2aeb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481717642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2481717642
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2647499756
Short name T572
Test name
Test status
Simulation time 27621950 ps
CPU time 0.61 seconds
Started Mar 31 12:23:45 PM PDT 24
Finished Mar 31 12:23:46 PM PDT 24
Peak memory 182540 kb
Host smart-dec47658-706a-4e1e-85f9-451a0aec6f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647499756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2647499756
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2589179468
Short name T505
Test name
Test status
Simulation time 14410074 ps
CPU time 0.56 seconds
Started Mar 31 12:23:52 PM PDT 24
Finished Mar 31 12:23:53 PM PDT 24
Peak memory 182424 kb
Host smart-e2558618-5e4e-4911-a23d-7b90bb48d206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589179468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2589179468
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.826352454
Short name T451
Test name
Test status
Simulation time 37892719 ps
CPU time 0.51 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:23:43 PM PDT 24
Peak memory 181964 kb
Host smart-a984a0ef-70ef-4322-884a-b4cd7b302b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826352454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.826352454
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2424350048
Short name T547
Test name
Test status
Simulation time 18603311 ps
CPU time 0.53 seconds
Started Mar 31 12:23:34 PM PDT 24
Finished Mar 31 12:23:34 PM PDT 24
Peak memory 182472 kb
Host smart-8b10e22b-b375-49bf-9f2d-fe5255d080ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424350048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2424350048
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.802338412
Short name T453
Test name
Test status
Simulation time 40341938 ps
CPU time 0.55 seconds
Started Mar 31 12:23:37 PM PDT 24
Finished Mar 31 12:23:37 PM PDT 24
Peak memory 182412 kb
Host smart-c02b120c-96f2-4d8b-933d-fae1112a040a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802338412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.802338412
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.132016190
Short name T532
Test name
Test status
Simulation time 28905649 ps
CPU time 0.53 seconds
Started Mar 31 12:23:43 PM PDT 24
Finished Mar 31 12:23:43 PM PDT 24
Peak memory 182488 kb
Host smart-ea0c582f-9411-44df-a5fe-58ec3e79420e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132016190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.132016190
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3825181236
Short name T486
Test name
Test status
Simulation time 21328149 ps
CPU time 0.53 seconds
Started Mar 31 12:23:41 PM PDT 24
Finished Mar 31 12:23:42 PM PDT 24
Peak memory 182508 kb
Host smart-6b0ba688-cbfa-43ef-b2a9-57a9f06a1b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825181236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3825181236
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1059248018
Short name T467
Test name
Test status
Simulation time 50587644 ps
CPU time 0.54 seconds
Started Mar 31 12:23:29 PM PDT 24
Finished Mar 31 12:23:30 PM PDT 24
Peak memory 182484 kb
Host smart-ecfbebc0-8699-4f2a-844a-bd7c21177cc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059248018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1059248018
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2374344165
Short name T541
Test name
Test status
Simulation time 23458560 ps
CPU time 0.57 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 182460 kb
Host smart-c0c56a88-788b-4fe9-ae73-ff14c29ec9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374344165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2374344165
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2138543122
Short name T76
Test name
Test status
Simulation time 31177991 ps
CPU time 0.81 seconds
Started Mar 31 12:23:20 PM PDT 24
Finished Mar 31 12:23:21 PM PDT 24
Peak memory 191816 kb
Host smart-949b0167-d412-485f-bb74-b2d0a306ea47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138543122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2138543122
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3526528986
Short name T516
Test name
Test status
Simulation time 189721990 ps
CPU time 2.5 seconds
Started Mar 31 12:23:12 PM PDT 24
Finished Mar 31 12:23:15 PM PDT 24
Peak memory 182764 kb
Host smart-b5def52b-ddaf-4f73-9368-0bc58ca20741
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526528986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3526528986
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1827506220
Short name T71
Test name
Test status
Simulation time 28561432 ps
CPU time 0.59 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 182488 kb
Host smart-916e6496-6d9c-4982-b5c3-58cdf2385b1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827506220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1827506220
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3281100762
Short name T520
Test name
Test status
Simulation time 31075846 ps
CPU time 0.62 seconds
Started Mar 31 12:23:30 PM PDT 24
Finished Mar 31 12:23:31 PM PDT 24
Peak memory 193596 kb
Host smart-ee4c2ba0-17b4-416c-9bcb-a61ddb10425c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281100762 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3281100762
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1099749515
Short name T73
Test name
Test status
Simulation time 116376592 ps
CPU time 0.63 seconds
Started Mar 31 12:23:22 PM PDT 24
Finished Mar 31 12:23:23 PM PDT 24
Peak memory 191800 kb
Host smart-7efbec71-b189-444c-88b9-6a39a518522a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099749515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1099749515
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3681892669
Short name T523
Test name
Test status
Simulation time 14824052 ps
CPU time 0.51 seconds
Started Mar 31 12:23:24 PM PDT 24
Finished Mar 31 12:23:24 PM PDT 24
Peak memory 182164 kb
Host smart-cfbc86da-2055-4f0c-8e1f-0e9b96befbfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681892669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3681892669
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3375326345
Short name T61
Test name
Test status
Simulation time 35691539 ps
CPU time 0.77 seconds
Started Mar 31 12:23:29 PM PDT 24
Finished Mar 31 12:23:30 PM PDT 24
Peak memory 191424 kb
Host smart-6fdd8704-e31c-44c9-acae-a4d849df3d56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375326345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3375326345
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3215535955
Short name T559
Test name
Test status
Simulation time 140744485 ps
CPU time 1.65 seconds
Started Mar 31 12:23:12 PM PDT 24
Finished Mar 31 12:23:14 PM PDT 24
Peak memory 197264 kb
Host smart-ba283938-9b8a-4007-a83d-8795e90d5e72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215535955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3215535955
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1302846094
Short name T490
Test name
Test status
Simulation time 276987462 ps
CPU time 1.12 seconds
Started Mar 31 12:23:21 PM PDT 24
Finished Mar 31 12:23:22 PM PDT 24
Peak memory 195004 kb
Host smart-f9eda7bf-a34c-4f90-a1fa-0cfc0c27f247
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302846094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1302846094
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1333651885
Short name T538
Test name
Test status
Simulation time 11398325 ps
CPU time 0.55 seconds
Started Mar 31 12:23:40 PM PDT 24
Finished Mar 31 12:23:41 PM PDT 24
Peak memory 182456 kb
Host smart-34f30be0-b050-4d93-9154-9f576ef6a503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333651885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1333651885
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.270299376
Short name T495
Test name
Test status
Simulation time 13742462 ps
CPU time 0.56 seconds
Started Mar 31 12:23:39 PM PDT 24
Finished Mar 31 12:23:44 PM PDT 24
Peak memory 182448 kb
Host smart-ca7a6091-bfbc-45c7-8744-b3b7d2b70481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270299376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.270299376
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2950088533
Short name T483
Test name
Test status
Simulation time 20774390 ps
CPU time 0.55 seconds
Started Mar 31 12:23:49 PM PDT 24
Finished Mar 31 12:23:49 PM PDT 24
Peak memory 182448 kb
Host smart-30c41a1d-5097-45f3-afb0-6a47edf704c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950088533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2950088533
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1642706846
Short name T489
Test name
Test status
Simulation time 41261497 ps
CPU time 0.54 seconds
Started Mar 31 12:23:34 PM PDT 24
Finished Mar 31 12:23:34 PM PDT 24
Peak memory 181936 kb
Host smart-0fbf46d4-5eb9-4bd7-9139-b09746043b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642706846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1642706846
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3780922974
Short name T540
Test name
Test status
Simulation time 16515584 ps
CPU time 0.56 seconds
Started Mar 31 12:23:57 PM PDT 24
Finished Mar 31 12:23:58 PM PDT 24
Peak memory 182540 kb
Host smart-9d998872-3a4c-446c-9097-b62b9fa97a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780922974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3780922974
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.97367824
Short name T507
Test name
Test status
Simulation time 80883328 ps
CPU time 0.54 seconds
Started Mar 31 12:23:46 PM PDT 24
Finished Mar 31 12:23:47 PM PDT 24
Peak memory 182464 kb
Host smart-25d52a4c-2102-409b-aad3-3e1740bf1c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97367824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.97367824
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3140158139
Short name T491
Test name
Test status
Simulation time 18411485 ps
CPU time 0.59 seconds
Started Mar 31 12:23:34 PM PDT 24
Finished Mar 31 12:23:34 PM PDT 24
Peak memory 182588 kb
Host smart-639a259b-fe54-4b28-b6ab-cc3c69d2f327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140158139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3140158139
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1041575833
Short name T447
Test name
Test status
Simulation time 15379293 ps
CPU time 0.53 seconds
Started Mar 31 12:23:51 PM PDT 24
Finished Mar 31 12:23:52 PM PDT 24
Peak memory 182536 kb
Host smart-b1a22800-8f7d-43fe-a274-7039958fe7cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041575833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1041575833
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3705290250
Short name T472
Test name
Test status
Simulation time 41845389 ps
CPU time 0.56 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 182520 kb
Host smart-e09a4138-899e-48cc-82f0-e84427d52200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705290250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3705290250
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.694361103
Short name T478
Test name
Test status
Simulation time 30426832 ps
CPU time 0.55 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:37 PM PDT 24
Peak memory 182076 kb
Host smart-d7239f0e-bfab-454a-bf16-277d26f678d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694361103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.694361103
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.628184652
Short name T66
Test name
Test status
Simulation time 125712507 ps
CPU time 0.75 seconds
Started Mar 31 12:24:30 PM PDT 24
Finished Mar 31 12:24:31 PM PDT 24
Peak memory 191640 kb
Host smart-bee35cd2-0ef6-4734-ae7d-70f4d011d03c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628184652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.628184652
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4017498261
Short name T75
Test name
Test status
Simulation time 1473413494 ps
CPU time 3.66 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:27 PM PDT 24
Peak memory 191708 kb
Host smart-db96ac28-539c-4c58-b4a1-2987c43d3113
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017498261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.4017498261
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1904067157
Short name T67
Test name
Test status
Simulation time 41633896 ps
CPU time 0.56 seconds
Started Mar 31 12:25:49 PM PDT 24
Finished Mar 31 12:25:50 PM PDT 24
Peak memory 182696 kb
Host smart-c8eeeae1-fb60-4e57-b6eb-566c743fc777
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904067157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1904067157
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.556164350
Short name T464
Test name
Test status
Simulation time 371948121 ps
CPU time 1.08 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 197304 kb
Host smart-0f29a7a2-7603-431c-87d1-e9c116d201dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556164350 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.556164350
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1764044709
Short name T68
Test name
Test status
Simulation time 43755790 ps
CPU time 0.56 seconds
Started Mar 31 12:23:22 PM PDT 24
Finished Mar 31 12:23:23 PM PDT 24
Peak memory 182556 kb
Host smart-760755d4-2dba-4f50-8243-8652928cb27f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764044709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1764044709
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1589062257
Short name T458
Test name
Test status
Simulation time 42703859 ps
CPU time 0.52 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:27 PM PDT 24
Peak memory 182268 kb
Host smart-37baa49d-b906-4e89-b4b5-32f1edb2589c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589062257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1589062257
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.433284474
Short name T567
Test name
Test status
Simulation time 67178772 ps
CPU time 0.77 seconds
Started Mar 31 12:23:25 PM PDT 24
Finished Mar 31 12:23:26 PM PDT 24
Peak memory 193420 kb
Host smart-c6544435-d429-45e2-9ce7-8be4a03008c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433284474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.433284474
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1772496982
Short name T465
Test name
Test status
Simulation time 161199296 ps
CPU time 2.61 seconds
Started Mar 31 12:23:27 PM PDT 24
Finished Mar 31 12:23:30 PM PDT 24
Peak memory 197468 kb
Host smart-ed4a6534-41dd-4ebe-884c-e27e1f0f9dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772496982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1772496982
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2169089576
Short name T528
Test name
Test status
Simulation time 141199533 ps
CPU time 1.34 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:25 PM PDT 24
Peak memory 183300 kb
Host smart-b482d84b-a998-4412-a1aa-0fa914f74cab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169089576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2169089576
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1729807320
Short name T575
Test name
Test status
Simulation time 17966463 ps
CPU time 0.64 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 182552 kb
Host smart-dde5cb21-bfc9-41c4-a78b-e3ed5a95e1d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729807320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1729807320
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.656792051
Short name T493
Test name
Test status
Simulation time 50602309 ps
CPU time 0.58 seconds
Started Mar 31 12:23:45 PM PDT 24
Finished Mar 31 12:23:46 PM PDT 24
Peak memory 182780 kb
Host smart-88527857-c665-440d-9245-76419b6628dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656792051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.656792051
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.137029689
Short name T573
Test name
Test status
Simulation time 43930317 ps
CPU time 0.52 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 180616 kb
Host smart-a8f9e007-6565-49d8-9dad-1aa03c4647eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137029689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.137029689
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1318869433
Short name T570
Test name
Test status
Simulation time 15879021 ps
CPU time 0.55 seconds
Started Mar 31 12:23:51 PM PDT 24
Finished Mar 31 12:23:51 PM PDT 24
Peak memory 181956 kb
Host smart-ba822e9a-b8e7-4142-a197-e8c1ac1f0054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318869433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1318869433
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1178010001
Short name T553
Test name
Test status
Simulation time 24735424 ps
CPU time 0.58 seconds
Started Mar 31 12:23:45 PM PDT 24
Finished Mar 31 12:23:46 PM PDT 24
Peak memory 182640 kb
Host smart-389d5526-a29f-4f8a-8fbc-84dd72e5bf5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178010001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1178010001
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.524150852
Short name T501
Test name
Test status
Simulation time 36216912 ps
CPU time 0.52 seconds
Started Mar 31 12:23:54 PM PDT 24
Finished Mar 31 12:23:55 PM PDT 24
Peak memory 182032 kb
Host smart-e97f252e-1c47-41df-86de-1f781bbe2c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524150852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.524150852
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3919390972
Short name T457
Test name
Test status
Simulation time 56789437 ps
CPU time 0.5 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 181940 kb
Host smart-eff2b9cc-0706-4aa4-92bd-b4bd3e524fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919390972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3919390972
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3930286108
Short name T551
Test name
Test status
Simulation time 15540999 ps
CPU time 0.58 seconds
Started Mar 31 12:23:55 PM PDT 24
Finished Mar 31 12:23:55 PM PDT 24
Peak memory 182428 kb
Host smart-52a42189-6fe0-4515-84bf-8e0b32dd204f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930286108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3930286108
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2263587063
Short name T549
Test name
Test status
Simulation time 45741815 ps
CPU time 0.51 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:23:43 PM PDT 24
Peak memory 181908 kb
Host smart-6848fcd0-1206-4391-af3f-cb17c30d86b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263587063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2263587063
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2329340428
Short name T452
Test name
Test status
Simulation time 39021435 ps
CPU time 0.52 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:37 PM PDT 24
Peak memory 182000 kb
Host smart-aaa704d5-78ff-4193-9f51-78406097fc3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329340428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2329340428
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3298891478
Short name T526
Test name
Test status
Simulation time 43733779 ps
CPU time 0.67 seconds
Started Mar 31 12:25:40 PM PDT 24
Finished Mar 31 12:25:41 PM PDT 24
Peak memory 193964 kb
Host smart-3cc138ee-1e92-444d-8850-c59db71dcb88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298891478 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3298891478
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3312270112
Short name T535
Test name
Test status
Simulation time 17951296 ps
CPU time 0.54 seconds
Started Mar 31 12:24:30 PM PDT 24
Finished Mar 31 12:24:31 PM PDT 24
Peak memory 182276 kb
Host smart-0d61cf06-6917-4e19-9e70-98fa3d276c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312270112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3312270112
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2988799004
Short name T461
Test name
Test status
Simulation time 12743487 ps
CPU time 0.53 seconds
Started Mar 31 12:24:45 PM PDT 24
Finished Mar 31 12:24:46 PM PDT 24
Peak memory 182484 kb
Host smart-0e9169c2-0dac-4371-83aa-a54f1c0af574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988799004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2988799004
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3020980289
Short name T484
Test name
Test status
Simulation time 221977712 ps
CPU time 0.77 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 193528 kb
Host smart-59f73376-bc55-42a0-8eb6-a9c3f2036b4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020980289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3020980289
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.524794639
Short name T517
Test name
Test status
Simulation time 93147205 ps
CPU time 1.16 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:25 PM PDT 24
Peak memory 197164 kb
Host smart-e87dc410-5da4-4656-955a-350616af56b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524794639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.524794639
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1076568281
Short name T95
Test name
Test status
Simulation time 644104131 ps
CPU time 1.37 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 193388 kb
Host smart-ac99bdc2-52e9-41ab-ad7e-e204727adb93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076568281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1076568281
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.867805593
Short name T31
Test name
Test status
Simulation time 78381011 ps
CPU time 0.66 seconds
Started Mar 31 12:23:25 PM PDT 24
Finished Mar 31 12:23:26 PM PDT 24
Peak memory 193744 kb
Host smart-dfef64f5-a92e-4ed4-830e-482e8492e727
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867805593 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.867805593
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2917030503
Short name T64
Test name
Test status
Simulation time 12503461 ps
CPU time 0.57 seconds
Started Mar 31 12:23:25 PM PDT 24
Finished Mar 31 12:23:25 PM PDT 24
Peak memory 182608 kb
Host smart-1223f89c-1641-435c-85e4-d6871b571c0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917030503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2917030503
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.263058370
Short name T477
Test name
Test status
Simulation time 53107653 ps
CPU time 0.58 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 179888 kb
Host smart-155b0bd7-3134-473b-867e-e797fe5c89b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263058370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.263058370
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2867313274
Short name T530
Test name
Test status
Simulation time 70670179 ps
CPU time 0.77 seconds
Started Mar 31 12:23:22 PM PDT 24
Finished Mar 31 12:23:23 PM PDT 24
Peak memory 191624 kb
Host smart-61244239-a1d6-4dad-8753-ab4bd79c59bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867313274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2867313274
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3705825344
Short name T574
Test name
Test status
Simulation time 570894103 ps
CPU time 2.39 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:25 PM PDT 24
Peak memory 197512 kb
Host smart-32e8ad64-e202-4412-b325-23545462a6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705825344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3705825344
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3274795041
Short name T27
Test name
Test status
Simulation time 49724527 ps
CPU time 0.83 seconds
Started Mar 31 12:23:24 PM PDT 24
Finished Mar 31 12:23:31 PM PDT 24
Peak memory 193840 kb
Host smart-1138a6a1-b71e-4d77-a40f-84915ce674b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274795041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3274795041
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1973186991
Short name T576
Test name
Test status
Simulation time 20550004 ps
CPU time 0.67 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 191256 kb
Host smart-90c59d5a-6219-40e0-8442-c277b27df360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973186991 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1973186991
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2345126046
Short name T564
Test name
Test status
Simulation time 47960007 ps
CPU time 0.59 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 179924 kb
Host smart-e995dacb-612a-4e45-97f6-440f83c3d6bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345126046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2345126046
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3657556767
Short name T88
Test name
Test status
Simulation time 35369255 ps
CPU time 0.85 seconds
Started Mar 31 12:23:24 PM PDT 24
Finished Mar 31 12:23:25 PM PDT 24
Peak memory 191608 kb
Host smart-540952cb-4dac-4d1e-9c44-663981a7bd55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657556767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3657556767
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1762149793
Short name T488
Test name
Test status
Simulation time 82867576 ps
CPU time 2.26 seconds
Started Mar 31 12:23:26 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 197480 kb
Host smart-edf452de-770a-499c-ab11-e1ef14cfc4d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762149793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1762149793
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.53740627
Short name T569
Test name
Test status
Simulation time 167493967 ps
CPU time 0.8 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:25:09 PM PDT 24
Peak memory 193364 kb
Host smart-39c5ce5b-6fde-4ee1-b95f-8328646324f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53740627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg
_err.53740627
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2510636444
Short name T566
Test name
Test status
Simulation time 98808391 ps
CPU time 0.75 seconds
Started Mar 31 12:23:16 PM PDT 24
Finished Mar 31 12:23:16 PM PDT 24
Peak memory 195520 kb
Host smart-a848ef5b-9044-4479-a39e-8eca9fbaf4ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510636444 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2510636444
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2683917831
Short name T480
Test name
Test status
Simulation time 44914557 ps
CPU time 0.53 seconds
Started Mar 31 12:23:29 PM PDT 24
Finished Mar 31 12:23:30 PM PDT 24
Peak memory 182240 kb
Host smart-cd684aa2-6993-4602-8544-b0402d4a4d65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683917831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2683917831
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2426378634
Short name T470
Test name
Test status
Simulation time 16048777 ps
CPU time 0.53 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:24 PM PDT 24
Peak memory 181952 kb
Host smart-4fe488b5-95eb-41f7-922d-44ed451e6f0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426378634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2426378634
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2382612915
Short name T504
Test name
Test status
Simulation time 18446667 ps
CPU time 0.68 seconds
Started Mar 31 12:23:27 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 193492 kb
Host smart-36a927c3-83da-4619-87ed-40ca94efef87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382612915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2382612915
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3718650377
Short name T560
Test name
Test status
Simulation time 862290358 ps
CPU time 1.83 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:25 PM PDT 24
Peak memory 197468 kb
Host smart-007aa8f9-83ea-4493-b281-3afb2be5f872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718650377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3718650377
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.931028618
Short name T500
Test name
Test status
Simulation time 428293469 ps
CPU time 1.34 seconds
Started Mar 31 12:23:30 PM PDT 24
Finished Mar 31 12:23:31 PM PDT 24
Peak memory 195424 kb
Host smart-02a40151-ec22-4282-81c7-3f3986b27491
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931028618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.931028618
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3008855239
Short name T497
Test name
Test status
Simulation time 41774011 ps
CPU time 0.87 seconds
Started Mar 31 12:23:31 PM PDT 24
Finished Mar 31 12:23:33 PM PDT 24
Peak memory 196364 kb
Host smart-9c8b6a53-0a45-4509-ab99-546d73e3a185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008855239 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3008855239
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3980691699
Short name T70
Test name
Test status
Simulation time 19105254 ps
CPU time 0.59 seconds
Started Mar 31 12:23:23 PM PDT 24
Finished Mar 31 12:23:24 PM PDT 24
Peak memory 182580 kb
Host smart-3d65a1c6-201a-4048-8dec-09e81e065e16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980691699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3980691699
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2314645202
Short name T449
Test name
Test status
Simulation time 96348141 ps
CPU time 0.54 seconds
Started Mar 31 12:23:29 PM PDT 24
Finished Mar 31 12:23:30 PM PDT 24
Peak memory 182380 kb
Host smart-1cd1cf18-32ae-40b2-b2d5-b8d19b9041c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314645202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2314645202
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2460761363
Short name T30
Test name
Test status
Simulation time 20575438 ps
CPU time 0.68 seconds
Started Mar 31 12:23:24 PM PDT 24
Finished Mar 31 12:23:25 PM PDT 24
Peak memory 191360 kb
Host smart-44353f6a-59a1-4148-9bb0-85842f793f93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460761363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2460761363
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4247409747
Short name T496
Test name
Test status
Simulation time 28473606 ps
CPU time 1.39 seconds
Started Mar 31 12:23:32 PM PDT 24
Finished Mar 31 12:23:34 PM PDT 24
Peak memory 197440 kb
Host smart-4ede1e21-6ee4-4af2-970e-4651790dfe02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247409747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4247409747
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4258605811
Short name T511
Test name
Test status
Simulation time 46211661 ps
CPU time 0.77 seconds
Started Mar 31 12:23:28 PM PDT 24
Finished Mar 31 12:23:29 PM PDT 24
Peak memory 193544 kb
Host smart-ee864be2-5ff7-417a-bbb7-6d37f3e85540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258605811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4258605811
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2288191702
Short name T328
Test name
Test status
Simulation time 42641396020 ps
CPU time 64.03 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:31:44 PM PDT 24
Peak memory 182732 kb
Host smart-44466390-2229-4951-8ddb-b1219fb271cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288191702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2288191702
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3841203217
Short name T365
Test name
Test status
Simulation time 84703324028 ps
CPU time 32.07 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:31:22 PM PDT 24
Peak memory 182656 kb
Host smart-27d2a41a-5e4b-48a5-aa57-3d53af0c21c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841203217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3841203217
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3997823028
Short name T127
Test name
Test status
Simulation time 157273054092 ps
CPU time 134.16 seconds
Started Mar 31 12:30:35 PM PDT 24
Finished Mar 31 12:32:49 PM PDT 24
Peak memory 190832 kb
Host smart-d505592e-cf30-44b1-89e7-90cd289d523e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997823028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3997823028
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3007251963
Short name T196
Test name
Test status
Simulation time 158233358333 ps
CPU time 238.41 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:34:35 PM PDT 24
Peak memory 182644 kb
Host smart-329133dd-1144-4d3c-8e0e-04953ac66c30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007251963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3007251963
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3199318628
Short name T406
Test name
Test status
Simulation time 234689273764 ps
CPU time 175.99 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:33:30 PM PDT 24
Peak memory 182592 kb
Host smart-ae48f30d-73e6-4818-8270-03357e50211c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199318628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3199318628
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1548439585
Short name T204
Test name
Test status
Simulation time 27445879474 ps
CPU time 44.14 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:31:18 PM PDT 24
Peak memory 182600 kb
Host smart-5b4c914b-1fe4-4d32-9fda-84d526760fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548439585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1548439585
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1186460387
Short name T18
Test name
Test status
Simulation time 62635965 ps
CPU time 0.84 seconds
Started Mar 31 12:30:42 PM PDT 24
Finished Mar 31 12:30:43 PM PDT 24
Peak memory 213104 kb
Host smart-fa3e6148-d526-462d-9a30-ce431be3b18d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186460387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1186460387
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3689301507
Short name T296
Test name
Test status
Simulation time 778274714146 ps
CPU time 2937.15 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 01:19:34 PM PDT 24
Peak memory 190884 kb
Host smart-577cdb24-ee93-4109-b7fc-2605c09180d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689301507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3689301507
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3302149556
Short name T427
Test name
Test status
Simulation time 59654618530 ps
CPU time 91.13 seconds
Started Mar 31 12:30:57 PM PDT 24
Finished Mar 31 12:32:28 PM PDT 24
Peak memory 182616 kb
Host smart-0feb0eff-34d4-4631-a2b7-54d429563139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302149556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3302149556
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1997375780
Short name T420
Test name
Test status
Simulation time 320757399 ps
CPU time 2.25 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:36 PM PDT 24
Peak memory 182544 kb
Host smart-4764e671-16e0-4db1-a923-d6b5f9a21a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997375780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1997375780
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.3635084381
Short name T240
Test name
Test status
Simulation time 1465016462 ps
CPU time 10.61 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:31:39 PM PDT 24
Peak memory 182620 kb
Host smart-d6d43ad8-9712-400c-98a8-ea0293c8b9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635084381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3635084381
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3480795815
Short name T174
Test name
Test status
Simulation time 420067476669 ps
CPU time 832.83 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:45:16 PM PDT 24
Peak memory 190644 kb
Host smart-9394e09e-71e5-4149-9fb4-5cd275b5a1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480795815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3480795815
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.548665714
Short name T162
Test name
Test status
Simulation time 14877247275 ps
CPU time 26.69 seconds
Started Mar 31 12:31:22 PM PDT 24
Finished Mar 31 12:31:49 PM PDT 24
Peak memory 182640 kb
Host smart-bbf5a981-e02a-4f54-8856-7a92714f76e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548665714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.548665714
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1897633057
Short name T169
Test name
Test status
Simulation time 177319967167 ps
CPU time 230.5 seconds
Started Mar 31 12:31:27 PM PDT 24
Finished Mar 31 12:35:17 PM PDT 24
Peak memory 190856 kb
Host smart-914d609e-aaa8-46bf-999f-11e3c4a900b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897633057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1897633057
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1387233332
Short name T332
Test name
Test status
Simulation time 211688601267 ps
CPU time 215.3 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:35:01 PM PDT 24
Peak memory 190892 kb
Host smart-d1e58383-a4c1-4cbd-8ee1-c01cb36fd65d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387233332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1387233332
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2077694279
Short name T188
Test name
Test status
Simulation time 138954806033 ps
CPU time 557.82 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:40:44 PM PDT 24
Peak memory 190856 kb
Host smart-939bd758-5631-4f0b-8236-c20740925168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077694279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2077694279
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1736859979
Short name T216
Test name
Test status
Simulation time 28212606668 ps
CPU time 49.44 seconds
Started Mar 31 12:30:41 PM PDT 24
Finished Mar 31 12:31:35 PM PDT 24
Peak memory 182632 kb
Host smart-b54cf5cf-6b7c-472a-883f-08bf35419591
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736859979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1736859979
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2354394892
Short name T400
Test name
Test status
Simulation time 357268052648 ps
CPU time 150.57 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:33:07 PM PDT 24
Peak memory 182688 kb
Host smart-1e99a503-0aa2-41ed-a5fd-4e09bc380208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354394892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2354394892
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2229108991
Short name T392
Test name
Test status
Simulation time 212866349 ps
CPU time 1.94 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:30:38 PM PDT 24
Peak memory 182536 kb
Host smart-b1a0cade-b5be-4b0e-9e32-9641fc56cd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229108991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2229108991
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1412184997
Short name T413
Test name
Test status
Simulation time 301395330160 ps
CPU time 48.13 seconds
Started Mar 31 12:31:34 PM PDT 24
Finished Mar 31 12:32:23 PM PDT 24
Peak memory 182548 kb
Host smart-00883715-e49e-4c41-b47b-d3451b7baa19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412184997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1412184997
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2604295000
Short name T178
Test name
Test status
Simulation time 505760976887 ps
CPU time 514.82 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:40:04 PM PDT 24
Peak memory 190860 kb
Host smart-4682f4c0-485c-4d72-a772-b1f978257345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604295000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2604295000
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.991691023
Short name T355
Test name
Test status
Simulation time 49128288595 ps
CPU time 22.86 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:31:52 PM PDT 24
Peak memory 182556 kb
Host smart-93eee549-498f-45e6-a63b-42b89a5feb3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991691023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.991691023
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3009437400
Short name T81
Test name
Test status
Simulation time 775768115191 ps
CPU time 66.57 seconds
Started Mar 31 12:31:24 PM PDT 24
Finished Mar 31 12:32:31 PM PDT 24
Peak memory 182692 kb
Host smart-ec897b44-c545-44be-96d1-2e8e7028221f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009437400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3009437400
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.544480703
Short name T412
Test name
Test status
Simulation time 30315744353 ps
CPU time 47.76 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:32:15 PM PDT 24
Peak memory 182668 kb
Host smart-127eecc8-7867-4839-8326-851e371e8fba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544480703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.544480703
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1361067788
Short name T241
Test name
Test status
Simulation time 62665189797 ps
CPU time 45.07 seconds
Started Mar 31 12:31:30 PM PDT 24
Finished Mar 31 12:32:15 PM PDT 24
Peak memory 182540 kb
Host smart-abf66e62-e997-4163-89d3-ec40ed2b2860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361067788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1361067788
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3307097394
Short name T59
Test name
Test status
Simulation time 341803242163 ps
CPU time 908.32 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:46:38 PM PDT 24
Peak memory 190796 kb
Host smart-b1716b30-8f1f-4e4b-be7c-35742ee76884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307097394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3307097394
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.379941345
Short name T191
Test name
Test status
Simulation time 2186685181896 ps
CPU time 458.78 seconds
Started Mar 31 12:31:22 PM PDT 24
Finished Mar 31 12:39:01 PM PDT 24
Peak memory 190900 kb
Host smart-764bd7eb-ee71-4a59-82b9-aef6df5ccf43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379941345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.379941345
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.4028735285
Short name T316
Test name
Test status
Simulation time 186355684238 ps
CPU time 310.45 seconds
Started Mar 31 12:30:41 PM PDT 24
Finished Mar 31 12:35:51 PM PDT 24
Peak memory 182588 kb
Host smart-32016bb2-1232-47df-8a6e-501a4cec495c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028735285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.4028735285
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.849557527
Short name T368
Test name
Test status
Simulation time 610749156223 ps
CPU time 302.05 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:36:14 PM PDT 24
Peak memory 182692 kb
Host smart-fa83dc23-7eb2-4ca0-b532-05113ea87768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849557527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.849557527
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1109968244
Short name T249
Test name
Test status
Simulation time 98914231188 ps
CPU time 45 seconds
Started Mar 31 12:30:41 PM PDT 24
Finished Mar 31 12:31:26 PM PDT 24
Peak memory 182616 kb
Host smart-75eadecc-836c-4fd4-b2db-afc00fbdf6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109968244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1109968244
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4078233584
Short name T353
Test name
Test status
Simulation time 122216393922 ps
CPU time 207.43 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:34:00 PM PDT 24
Peak memory 190844 kb
Host smart-77cfd915-6185-44e1-8288-6739c8b54a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078233584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4078233584
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3388008257
Short name T78
Test name
Test status
Simulation time 26265691815 ps
CPU time 65.9 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:32:23 PM PDT 24
Peak memory 182468 kb
Host smart-ad91a060-7653-405a-8c67-529d299eafff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388008257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3388008257
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1944153180
Short name T159
Test name
Test status
Simulation time 318401123784 ps
CPU time 369.86 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:37:36 PM PDT 24
Peak memory 190808 kb
Host smart-f8ebfe82-3221-4346-a60e-14597caa0300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944153180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1944153180
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1939639316
Short name T255
Test name
Test status
Simulation time 3962409842 ps
CPU time 41.57 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:32:05 PM PDT 24
Peak memory 182700 kb
Host smart-3323fe7d-fd16-44ba-8516-07a787f11a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939639316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1939639316
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3300649189
Short name T338
Test name
Test status
Simulation time 59247945411 ps
CPU time 33.36 seconds
Started Mar 31 12:31:31 PM PDT 24
Finished Mar 31 12:32:05 PM PDT 24
Peak memory 182672 kb
Host smart-46159534-713e-4a59-8668-add097fe9fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300649189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3300649189
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2684635736
Short name T164
Test name
Test status
Simulation time 280730375393 ps
CPU time 3158.91 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 01:24:01 PM PDT 24
Peak memory 190888 kb
Host smart-22fcf3b4-2a30-4aaf-a462-9c812334cf10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684635736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2684635736
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3706155363
Short name T219
Test name
Test status
Simulation time 85600287307 ps
CPU time 1025.45 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:48:31 PM PDT 24
Peak memory 190808 kb
Host smart-cd850a28-99d0-4819-b791-6f9d591976cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706155363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3706155363
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.924688851
Short name T108
Test name
Test status
Simulation time 42001787701 ps
CPU time 15.77 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 12:31:37 PM PDT 24
Peak memory 182544 kb
Host smart-92d63b86-f08a-4ebc-8f1d-400a2c76af39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924688851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.924688851
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3407354103
Short name T321
Test name
Test status
Simulation time 331464557397 ps
CPU time 152.35 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:33:59 PM PDT 24
Peak memory 190880 kb
Host smart-85ade4a8-a2b5-4132-a709-784976094b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407354103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3407354103
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1588666523
Short name T399
Test name
Test status
Simulation time 86103971558 ps
CPU time 72.81 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:32:38 PM PDT 24
Peak memory 182676 kb
Host smart-0870ef48-81a0-412d-a433-6a483def95d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588666523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1588666523
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.455212596
Short name T360
Test name
Test status
Simulation time 56152040268 ps
CPU time 87.58 seconds
Started Mar 31 12:30:52 PM PDT 24
Finished Mar 31 12:32:19 PM PDT 24
Peak memory 182628 kb
Host smart-1b346b78-fe5a-423e-8a23-46f6a2bd0a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455212596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.455212596
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1513079166
Short name T371
Test name
Test status
Simulation time 513513670 ps
CPU time 0.79 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:35 PM PDT 24
Peak memory 182408 kb
Host smart-e923c2e7-6914-4206-8f66-c10357ec6d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513079166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1513079166
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.410838707
Short name T154
Test name
Test status
Simulation time 147585571724 ps
CPU time 606.96 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:41:36 PM PDT 24
Peak memory 190880 kb
Host smart-acc8260f-ab6c-4c71-8ba8-1d7adcd81226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410838707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.410838707
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3027817483
Short name T19
Test name
Test status
Simulation time 82450317600 ps
CPU time 142.23 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 12:33:44 PM PDT 24
Peak memory 193296 kb
Host smart-1026d9c6-17b8-43d0-a84d-ceb8ed728244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027817483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3027817483
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.265364329
Short name T156
Test name
Test status
Simulation time 639926493309 ps
CPU time 168.87 seconds
Started Mar 31 12:31:22 PM PDT 24
Finished Mar 31 12:34:11 PM PDT 24
Peak memory 190872 kb
Host smart-b2a6728d-26bf-4245-8e81-96aa1bfb154e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265364329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.265364329
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2260247757
Short name T395
Test name
Test status
Simulation time 4554468279 ps
CPU time 2.59 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 12:31:24 PM PDT 24
Peak memory 182596 kb
Host smart-beeff4f7-5fc4-4048-abd5-bddb1fa45de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260247757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2260247757
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.796334324
Short name T228
Test name
Test status
Simulation time 139634309407 ps
CPU time 587.62 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:41:10 PM PDT 24
Peak memory 190904 kb
Host smart-21e4eee4-62dd-41bf-81f7-bea9329d1e06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796334324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.796334324
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.911712668
Short name T200
Test name
Test status
Simulation time 39241512264 ps
CPU time 64.99 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:32:34 PM PDT 24
Peak memory 194080 kb
Host smart-1825ff81-2134-458f-94b6-85d67b871347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911712668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.911712668
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3521355520
Short name T268
Test name
Test status
Simulation time 363240746159 ps
CPU time 573.31 seconds
Started Mar 31 12:30:35 PM PDT 24
Finished Mar 31 12:40:08 PM PDT 24
Peak memory 182724 kb
Host smart-5f885994-78e3-4871-a495-8a7450028c4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521355520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3521355520
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1034517258
Short name T407
Test name
Test status
Simulation time 133931572870 ps
CPU time 90.25 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:32:14 PM PDT 24
Peak memory 182628 kb
Host smart-af5c278e-51fe-49f3-a349-038e66f24d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034517258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1034517258
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.117555003
Short name T339
Test name
Test status
Simulation time 246845674009 ps
CPU time 240.12 seconds
Started Mar 31 12:30:41 PM PDT 24
Finished Mar 31 12:34:41 PM PDT 24
Peak memory 190824 kb
Host smart-4c25e194-a435-4130-b6b7-60e4a07108d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117555003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.117555003
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4001160350
Short name T327
Test name
Test status
Simulation time 31792681352 ps
CPU time 40.29 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:31:17 PM PDT 24
Peak memory 190880 kb
Host smart-0ac7ddac-3f2c-4ed6-8f92-106dc71fc9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001160350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4001160350
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.198030830
Short name T251
Test name
Test status
Simulation time 1023760802886 ps
CPU time 492.75 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:38:50 PM PDT 24
Peak memory 191168 kb
Host smart-0c7b4ac3-3f88-4d71-b7ac-4c561ee647a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198030830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
198030830
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.3896678153
Short name T290
Test name
Test status
Simulation time 19182542410 ps
CPU time 28.39 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:31:57 PM PDT 24
Peak memory 182536 kb
Host smart-4619f6a4-a9e1-4cc9-b29c-cbc0b19f2f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896678153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3896678153
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.4236780466
Short name T211
Test name
Test status
Simulation time 235059496644 ps
CPU time 486.88 seconds
Started Mar 31 12:31:27 PM PDT 24
Finished Mar 31 12:39:34 PM PDT 24
Peak memory 190892 kb
Host smart-584f89cc-04be-4c1c-ae11-ca31e5c888f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236780466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.4236780466
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2918182747
Short name T411
Test name
Test status
Simulation time 262303389278 ps
CPU time 203.32 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:34:43 PM PDT 24
Peak memory 190808 kb
Host smart-029034fe-8fd8-49fd-abde-ae7ff39ac7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918182747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2918182747
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3368468986
Short name T181
Test name
Test status
Simulation time 167856445216 ps
CPU time 1699.6 seconds
Started Mar 31 12:31:24 PM PDT 24
Finished Mar 31 12:59:45 PM PDT 24
Peak memory 190892 kb
Host smart-f159f8af-897a-4cbc-ae32-651d064d98ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368468986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3368468986
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3601393193
Short name T289
Test name
Test status
Simulation time 41436911720 ps
CPU time 47.42 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:32:08 PM PDT 24
Peak memory 182692 kb
Host smart-6cbccf78-cdf0-4128-9883-fd6a30116554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601393193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3601393193
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.4041408881
Short name T42
Test name
Test status
Simulation time 99897910524 ps
CPU time 53.51 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:32:13 PM PDT 24
Peak memory 182564 kb
Host smart-17d9838d-deb3-47f8-9082-0de07f749a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041408881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4041408881
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3638173974
Short name T6
Test name
Test status
Simulation time 121599119609 ps
CPU time 433.15 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:38:39 PM PDT 24
Peak memory 190892 kb
Host smart-1638a189-99d6-414b-a63f-742431818c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638173974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3638173974
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1925927566
Short name T409
Test name
Test status
Simulation time 111285618130 ps
CPU time 114.68 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:33:15 PM PDT 24
Peak memory 190788 kb
Host smart-ccaf696d-49f6-4918-851b-0a783dbacbf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925927566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1925927566
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1858695195
Short name T173
Test name
Test status
Simulation time 421314084910 ps
CPU time 384.76 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:37:10 PM PDT 24
Peak memory 182720 kb
Host smart-06c046b0-40af-44f9-b646-c9058d5ab3b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858695195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1858695195
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1865213972
Short name T433
Test name
Test status
Simulation time 605364623112 ps
CPU time 138.88 seconds
Started Mar 31 12:30:53 PM PDT 24
Finished Mar 31 12:33:12 PM PDT 24
Peak memory 182584 kb
Host smart-4387e3cc-491d-4ec9-92a8-c3c237930daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865213972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1865213972
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2197767093
Short name T126
Test name
Test status
Simulation time 462266773321 ps
CPU time 248.18 seconds
Started Mar 31 12:30:54 PM PDT 24
Finished Mar 31 12:35:02 PM PDT 24
Peak memory 190832 kb
Host smart-ab4c23f3-9e78-4c31-a96b-d5fad55221d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197767093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2197767093
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2406728878
Short name T275
Test name
Test status
Simulation time 272117390513 ps
CPU time 91.1 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:32:15 PM PDT 24
Peak memory 194728 kb
Host smart-023c11b4-b7b3-4980-8944-978cdb9a4a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406728878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2406728878
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.3616373523
Short name T307
Test name
Test status
Simulation time 25094863664 ps
CPU time 34.82 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:31:54 PM PDT 24
Peak memory 182556 kb
Host smart-4814c761-8d4d-43ed-b1ee-d1041398e387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616373523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3616373523
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.4186680853
Short name T445
Test name
Test status
Simulation time 553158426097 ps
CPU time 413.62 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 12:38:15 PM PDT 24
Peak memory 190892 kb
Host smart-40ff0a26-c55c-4fbe-8104-63542cba77c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186680853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4186680853
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.375608281
Short name T344
Test name
Test status
Simulation time 855317616498 ps
CPU time 427.99 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:38:34 PM PDT 24
Peak memory 190888 kb
Host smart-bf1b974d-6f55-4e6c-8d05-3fd3af47e001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375608281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.375608281
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.4060657694
Short name T428
Test name
Test status
Simulation time 45113123575 ps
CPU time 76.21 seconds
Started Mar 31 12:31:27 PM PDT 24
Finished Mar 31 12:32:44 PM PDT 24
Peak memory 182616 kb
Host smart-7adf090c-601c-4eb4-91b2-4f8863c6ec68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060657694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.4060657694
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.728265644
Short name T120
Test name
Test status
Simulation time 420053635596 ps
CPU time 343.32 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:37:04 PM PDT 24
Peak memory 190784 kb
Host smart-515e1977-2b2a-4593-b083-58619d13bbf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728265644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.728265644
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3472357891
Short name T171
Test name
Test status
Simulation time 206929588703 ps
CPU time 109.02 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:32:26 PM PDT 24
Peak memory 182948 kb
Host smart-962d9240-82f4-43e8-bd77-d7122bcf8e6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472357891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3472357891
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3560474869
Short name T21
Test name
Test status
Simulation time 17570471715 ps
CPU time 24.75 seconds
Started Mar 31 12:30:39 PM PDT 24
Finished Mar 31 12:31:04 PM PDT 24
Peak memory 182640 kb
Host smart-09f146ab-1248-43bc-95bd-cb20cba60d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560474869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3560474869
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2000547716
Short name T60
Test name
Test status
Simulation time 795163239 ps
CPU time 1.11 seconds
Started Mar 31 12:31:05 PM PDT 24
Finished Mar 31 12:31:06 PM PDT 24
Peak memory 182432 kb
Host smart-45c53170-c333-4663-9df8-7b13e7b197f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000547716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2000547716
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1583749601
Short name T40
Test name
Test status
Simulation time 47487941429 ps
CPU time 76.04 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:31:52 PM PDT 24
Peak memory 190792 kb
Host smart-cab12c03-9517-4979-ade3-a9815254bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583749601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1583749601
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1762476507
Short name T294
Test name
Test status
Simulation time 83419792384 ps
CPU time 74.84 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:32:35 PM PDT 24
Peak memory 182628 kb
Host smart-ad316e2e-c7fb-428f-9d58-c7bf9841641f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762476507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1762476507
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2207323734
Short name T349
Test name
Test status
Simulation time 5043093811 ps
CPU time 8.09 seconds
Started Mar 31 12:31:31 PM PDT 24
Finished Mar 31 12:31:40 PM PDT 24
Peak memory 182616 kb
Host smart-93fdd622-43cb-433e-916a-7798965d77f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207323734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2207323734
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2991400802
Short name T10
Test name
Test status
Simulation time 23756195545 ps
CPU time 21.96 seconds
Started Mar 31 12:31:32 PM PDT 24
Finished Mar 31 12:31:54 PM PDT 24
Peak memory 190824 kb
Host smart-9e5b0130-4635-4765-98e6-4341143d2e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991400802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2991400802
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.755814615
Short name T354
Test name
Test status
Simulation time 52283703488 ps
CPU time 80.37 seconds
Started Mar 31 12:31:28 PM PDT 24
Finished Mar 31 12:32:49 PM PDT 24
Peak memory 190892 kb
Host smart-7829e7e3-fc28-4b7e-a89a-f00fbea0fcb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755814615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.755814615
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3010500000
Short name T312
Test name
Test status
Simulation time 118352129619 ps
CPU time 488.41 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:39:37 PM PDT 24
Peak memory 182620 kb
Host smart-d5cd72a5-b4b1-4c4f-a88e-a4ef62a3df92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010500000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3010500000
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.49586809
Short name T337
Test name
Test status
Simulation time 157327915772 ps
CPU time 66.02 seconds
Started Mar 31 12:31:27 PM PDT 24
Finished Mar 31 12:32:33 PM PDT 24
Peak memory 182628 kb
Host smart-ca4f06f5-2389-4f28-b6ad-886ece117126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49586809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.49586809
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1402584080
Short name T298
Test name
Test status
Simulation time 35316380835 ps
CPU time 21.49 seconds
Started Mar 31 12:31:31 PM PDT 24
Finished Mar 31 12:31:52 PM PDT 24
Peak memory 182648 kb
Host smart-91547bad-d906-4fef-9469-5e5eaa66d989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402584080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1402584080
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2274678354
Short name T432
Test name
Test status
Simulation time 1335816991967 ps
CPU time 702.25 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:42:17 PM PDT 24
Peak memory 182700 kb
Host smart-61c29927-9368-419c-98d6-599f80d22998
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274678354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2274678354
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_random.1662297909
Short name T393
Test name
Test status
Simulation time 34327226763 ps
CPU time 184.47 seconds
Started Mar 31 12:30:51 PM PDT 24
Finished Mar 31 12:33:55 PM PDT 24
Peak memory 182692 kb
Host smart-b04a9f7a-9726-4a7d-885c-18a74823149a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662297909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1662297909
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1362975039
Short name T150
Test name
Test status
Simulation time 35814482324 ps
CPU time 60.24 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:31:46 PM PDT 24
Peak memory 182692 kb
Host smart-e884eb2c-e784-4731-b86a-43191fe0326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362975039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1362975039
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2207836021
Short name T117
Test name
Test status
Simulation time 200959734528 ps
CPU time 438.51 seconds
Started Mar 31 12:31:22 PM PDT 24
Finished Mar 31 12:38:41 PM PDT 24
Peak memory 182612 kb
Host smart-c58aa7a3-19e6-490a-8d4a-d12bc1b534bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207836021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2207836021
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2105686545
Short name T311
Test name
Test status
Simulation time 40539860927 ps
CPU time 37.84 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:32:05 PM PDT 24
Peak memory 182568 kb
Host smart-043fb67a-b96b-41f0-8a3a-06ed070dae3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105686545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2105686545
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2042035756
Short name T285
Test name
Test status
Simulation time 39468267678 ps
CPU time 106.63 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:33:13 PM PDT 24
Peak memory 182568 kb
Host smart-ff8e49ca-9c92-4b66-9b48-8f53d6278ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042035756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2042035756
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1476327709
Short name T45
Test name
Test status
Simulation time 175544897319 ps
CPU time 37.11 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:32:00 PM PDT 24
Peak memory 182600 kb
Host smart-57cb6237-44fc-49ae-a0b1-9df51577bc91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476327709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1476327709
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3388580812
Short name T318
Test name
Test status
Simulation time 150859372261 ps
CPU time 228.63 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:35:16 PM PDT 24
Peak memory 190836 kb
Host smart-3c477354-e8a8-4a98-bca2-9631efc701fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388580812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3388580812
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3253462541
Short name T271
Test name
Test status
Simulation time 214216423292 ps
CPU time 74.13 seconds
Started Mar 31 12:31:24 PM PDT 24
Finished Mar 31 12:32:39 PM PDT 24
Peak memory 182688 kb
Host smart-729ab30e-6bb7-42ec-8a63-5c1ca5204146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253462541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3253462541
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1482721651
Short name T50
Test name
Test status
Simulation time 268302810402 ps
CPU time 877.09 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:46:03 PM PDT 24
Peak memory 190828 kb
Host smart-2441bbb8-4c1d-4b06-a2b8-0b8fac6a3b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482721651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1482721651
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2055511086
Short name T303
Test name
Test status
Simulation time 68351874844 ps
CPU time 58.49 seconds
Started Mar 31 12:31:31 PM PDT 24
Finished Mar 31 12:32:30 PM PDT 24
Peak memory 194320 kb
Host smart-d9d2ecb6-0615-4d79-b9b0-56f26b6bc438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055511086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2055511086
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1787714887
Short name T345
Test name
Test status
Simulation time 189532965046 ps
CPU time 175.69 seconds
Started Mar 31 12:31:30 PM PDT 24
Finished Mar 31 12:34:26 PM PDT 24
Peak memory 190824 kb
Host smart-e5a6bf5b-33ec-4c8a-a3bb-4b6dcb77af51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787714887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1787714887
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4263314482
Short name T293
Test name
Test status
Simulation time 6768124199984 ps
CPU time 1991.7 seconds
Started Mar 31 12:30:49 PM PDT 24
Finished Mar 31 01:04:01 PM PDT 24
Peak memory 182552 kb
Host smart-7662aa1d-4ebb-4636-b485-a23cbda36b02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263314482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.4263314482
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.185618305
Short name T384
Test name
Test status
Simulation time 433089754765 ps
CPU time 185.17 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:33:51 PM PDT 24
Peak memory 182692 kb
Host smart-1182ae59-44bf-407d-881e-9b5111fb2381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185618305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.185618305
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3855075956
Short name T343
Test name
Test status
Simulation time 347541549235 ps
CPU time 400.35 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:37:20 PM PDT 24
Peak memory 190832 kb
Host smart-52292a0c-130b-4a0b-b257-2145ba66697f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855075956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3855075956
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.632151275
Short name T229
Test name
Test status
Simulation time 2503334476 ps
CPU time 4.6 seconds
Started Mar 31 12:31:09 PM PDT 24
Finished Mar 31 12:31:13 PM PDT 24
Peak memory 193596 kb
Host smart-4bf4db20-2ee4-4c09-b98f-b2c5b9b373df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632151275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.632151275
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2858404151
Short name T33
Test name
Test status
Simulation time 18042501367 ps
CPU time 97.88 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:32:30 PM PDT 24
Peak memory 197184 kb
Host smart-8cb3682e-3085-4c08-b63f-0818dd4bcfd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858404151 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2858404151
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1587117967
Short name T232
Test name
Test status
Simulation time 125924937391 ps
CPU time 1355.34 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:54:00 PM PDT 24
Peak memory 193044 kb
Host smart-5af54ac0-1f04-4a41-b000-2c468fdeb5c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587117967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1587117967
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.269887953
Short name T151
Test name
Test status
Simulation time 108349943440 ps
CPU time 2884.54 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 01:19:28 PM PDT 24
Peak memory 190760 kb
Host smart-3e0afae2-1536-49d9-8f08-ea1e63eacc84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269887953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.269887953
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2977488789
Short name T246
Test name
Test status
Simulation time 53290800087 ps
CPU time 99.76 seconds
Started Mar 31 12:31:28 PM PDT 24
Finished Mar 31 12:33:08 PM PDT 24
Peak memory 190784 kb
Host smart-5653adfb-6016-48aa-8b84-454081955835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977488789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2977488789
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.26404786
Short name T443
Test name
Test status
Simulation time 27287752157 ps
CPU time 47.21 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:32:14 PM PDT 24
Peak memory 182460 kb
Host smart-ae54d5e9-0aba-4b5b-83b4-442930216548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.26404786
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3304405441
Short name T189
Test name
Test status
Simulation time 258900753368 ps
CPU time 482.99 seconds
Started Mar 31 12:31:30 PM PDT 24
Finished Mar 31 12:39:33 PM PDT 24
Peak memory 190820 kb
Host smart-3eac9597-e79a-4859-aa08-8da254031c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304405441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3304405441
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.92404419
Short name T444
Test name
Test status
Simulation time 420437805035 ps
CPU time 679.08 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:41:59 PM PDT 24
Peak memory 182684 kb
Host smart-e9c26881-0bcd-4f70-a82c-864090b5d467
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92404419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.rv_timer_cfg_update_on_fly.92404419
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3371875775
Short name T408
Test name
Test status
Simulation time 22399414413 ps
CPU time 5.44 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:30:54 PM PDT 24
Peak memory 182680 kb
Host smart-7bc6e913-82d7-49c0-a595-57281a48f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371875775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3371875775
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.894623383
Short name T299
Test name
Test status
Simulation time 104023045780 ps
CPU time 72.59 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:31:50 PM PDT 24
Peak memory 182644 kb
Host smart-ce533adb-b764-49f0-8673-07d58cbcd94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894623383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.894623383
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1633495592
Short name T244
Test name
Test status
Simulation time 165488943127 ps
CPU time 209.36 seconds
Started Mar 31 12:31:28 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 190888 kb
Host smart-48a7f241-058a-42e8-ab35-e8ecf734e69d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633495592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1633495592
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2825147509
Short name T259
Test name
Test status
Simulation time 37338421520 ps
CPU time 19.57 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:31:45 PM PDT 24
Peak memory 182636 kb
Host smart-d620c2ae-8067-48e9-9803-ec0052757482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825147509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2825147509
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1973593744
Short name T48
Test name
Test status
Simulation time 104536024307 ps
CPU time 104.03 seconds
Started Mar 31 12:31:30 PM PDT 24
Finished Mar 31 12:33:14 PM PDT 24
Peak memory 190800 kb
Host smart-a58f42de-422b-47c6-b4c5-51b3a23b4776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973593744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1973593744
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.4217492187
Short name T398
Test name
Test status
Simulation time 144931792550 ps
CPU time 69.9 seconds
Started Mar 31 12:31:28 PM PDT 24
Finished Mar 31 12:32:38 PM PDT 24
Peak memory 182628 kb
Host smart-fa8a559f-afcc-43cf-abe3-0a6f52b931ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217492187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4217492187
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.924753080
Short name T224
Test name
Test status
Simulation time 93993530262 ps
CPU time 145.31 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:33:51 PM PDT 24
Peak memory 190768 kb
Host smart-f1b13cf4-9af6-4d72-acb5-8956ccecdc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924753080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.924753080
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3649288502
Short name T137
Test name
Test status
Simulation time 465214383913 ps
CPU time 273.16 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:36:00 PM PDT 24
Peak memory 193016 kb
Host smart-55aeb92e-08c0-4472-be32-8b7a74938c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649288502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3649288502
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1439793470
Short name T98
Test name
Test status
Simulation time 141002206771 ps
CPU time 70.73 seconds
Started Mar 31 12:31:32 PM PDT 24
Finished Mar 31 12:32:43 PM PDT 24
Peak memory 190828 kb
Host smart-e9a9ceb1-e66d-423f-b4f5-118d373d7ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439793470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1439793470
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1331715710
Short name T340
Test name
Test status
Simulation time 717199775939 ps
CPU time 272.11 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:36:01 PM PDT 24
Peak memory 190892 kb
Host smart-0e556387-bdfd-4f0d-9b00-931375e3ed7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331715710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1331715710
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2386892633
Short name T295
Test name
Test status
Simulation time 24745625861 ps
CPU time 20.83 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:31:48 PM PDT 24
Peak memory 182628 kb
Host smart-bbc2861b-4528-4c0e-a29a-c42b4b05115c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386892633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2386892633
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3459989936
Short name T202
Test name
Test status
Simulation time 174278452920 ps
CPU time 330.11 seconds
Started Mar 31 12:31:30 PM PDT 24
Finished Mar 31 12:37:00 PM PDT 24
Peak memory 190824 kb
Host smart-5a9d295b-a810-4ac0-9919-2ae124dd01a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459989936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3459989936
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2351402658
Short name T226
Test name
Test status
Simulation time 105865407213 ps
CPU time 180.15 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 182600 kb
Host smart-e7b7cc07-c1fd-486c-85ea-7b19ec7b8fe1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351402658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2351402658
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2384037042
Short name T389
Test name
Test status
Simulation time 29137496034 ps
CPU time 8.43 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:30:49 PM PDT 24
Peak memory 182596 kb
Host smart-a6f608ee-7902-4693-b59b-9fbdcdea0b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384037042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2384037042
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2044792065
Short name T143
Test name
Test status
Simulation time 93386339405 ps
CPU time 167.6 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:33:28 PM PDT 24
Peak memory 190792 kb
Host smart-06120a30-ce0e-4ab7-898c-6fbb35136fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044792065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2044792065
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1718215977
Short name T47
Test name
Test status
Simulation time 862698091 ps
CPU time 0.75 seconds
Started Mar 31 12:30:43 PM PDT 24
Finished Mar 31 12:30:44 PM PDT 24
Peak memory 182372 kb
Host smart-4210038a-ec9b-4c5a-9986-5681f9a057b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718215977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1718215977
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1443184640
Short name T11
Test name
Test status
Simulation time 125421294 ps
CPU time 0.7 seconds
Started Mar 31 12:30:41 PM PDT 24
Finished Mar 31 12:30:42 PM PDT 24
Peak memory 213120 kb
Host smart-26018057-2ee4-4bfc-b982-e8e150f44e14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443184640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1443184640
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1729705170
Short name T245
Test name
Test status
Simulation time 171876450652 ps
CPU time 318.51 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:36:07 PM PDT 24
Peak memory 182680 kb
Host smart-d14eb22a-503d-4ec1-9138-c858f509e947
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729705170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1729705170
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1600628177
Short name T394
Test name
Test status
Simulation time 115980622743 ps
CPU time 183.34 seconds
Started Mar 31 12:30:42 PM PDT 24
Finished Mar 31 12:33:46 PM PDT 24
Peak memory 182636 kb
Host smart-d35934ff-3ae8-49e5-b398-4aba7d7d9b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600628177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1600628177
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4288934129
Short name T396
Test name
Test status
Simulation time 18332789694 ps
CPU time 336.21 seconds
Started Mar 31 12:30:52 PM PDT 24
Finished Mar 31 12:36:28 PM PDT 24
Peak memory 182632 kb
Host smart-94c1a60c-f874-41ad-a4e6-c3d599356027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288934129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4288934129
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3520123892
Short name T442
Test name
Test status
Simulation time 1276699310291 ps
CPU time 664.74 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:41:49 PM PDT 24
Peak memory 190916 kb
Host smart-4e4ab7b2-fac2-4541-aa43-fceb9afe495d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520123892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3520123892
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3477923563
Short name T381
Test name
Test status
Simulation time 160853506543 ps
CPU time 222.15 seconds
Started Mar 31 12:30:50 PM PDT 24
Finished Mar 31 12:34:32 PM PDT 24
Peak memory 182680 kb
Host smart-bb603662-6ccf-48a8-b1fa-e84dc4c60e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477923563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3477923563
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1121465067
Short name T208
Test name
Test status
Simulation time 1461869288178 ps
CPU time 917.93 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:46:02 PM PDT 24
Peak memory 190772 kb
Host smart-8018682e-9d3b-406b-8a13-7c74aa16f21d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121465067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1121465067
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4258591823
Short name T388
Test name
Test status
Simulation time 40148503 ps
CPU time 0.57 seconds
Started Mar 31 12:31:00 PM PDT 24
Finished Mar 31 12:31:01 PM PDT 24
Peak memory 182280 kb
Host smart-1b0b2a79-c6d2-4159-8e68-ede55747274b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258591823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4258591823
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2024743735
Short name T3
Test name
Test status
Simulation time 415031915701 ps
CPU time 226.18 seconds
Started Mar 31 12:30:38 PM PDT 24
Finished Mar 31 12:34:24 PM PDT 24
Peak memory 182852 kb
Host smart-b854d576-c6e8-4830-b930-c46d112d93f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024743735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2024743735
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.2961621633
Short name T423
Test name
Test status
Simulation time 18739897434 ps
CPU time 174.12 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 182600 kb
Host smart-e10de787-0d05-4553-b434-b53469f2d8fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961621633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2961621633
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3330076595
Short name T281
Test name
Test status
Simulation time 18211610071 ps
CPU time 30.09 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:31:19 PM PDT 24
Peak memory 194288 kb
Host smart-31ca2ed6-fcbe-4a3c-8a57-fabe5090853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330076595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3330076595
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.4067497557
Short name T34
Test name
Test status
Simulation time 212267901837 ps
CPU time 299.58 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:35:45 PM PDT 24
Peak memory 205408 kb
Host smart-a5256950-ad08-4230-83dd-d2eb31b16bc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067497557 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.4067497557
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.87210730
Short name T346
Test name
Test status
Simulation time 67844229911 ps
CPU time 121.87 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:32:50 PM PDT 24
Peak memory 182552 kb
Host smart-b7da9974-f491-4df0-9352-cb55dd440df7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87210730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.rv_timer_cfg_update_on_fly.87210730
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2137925652
Short name T425
Test name
Test status
Simulation time 113202562495 ps
CPU time 49.32 seconds
Started Mar 31 12:30:49 PM PDT 24
Finished Mar 31 12:31:38 PM PDT 24
Peak memory 182552 kb
Host smart-58334196-5631-441a-b65c-9e00174a1a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137925652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2137925652
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3081898009
Short name T260
Test name
Test status
Simulation time 38920137905 ps
CPU time 234.65 seconds
Started Mar 31 12:31:07 PM PDT 24
Finished Mar 31 12:35:02 PM PDT 24
Peak memory 182556 kb
Host smart-e577a6bd-723a-4b63-a3f1-1a4fee41b27b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081898009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3081898009
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1221176606
Short name T231
Test name
Test status
Simulation time 101855601421 ps
CPU time 414.8 seconds
Started Mar 31 12:30:49 PM PDT 24
Finished Mar 31 12:37:44 PM PDT 24
Peak memory 182668 kb
Host smart-cc8cb66f-1943-4d02-b0f4-d3a4462f789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221176606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1221176606
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3687604242
Short name T267
Test name
Test status
Simulation time 135445459966 ps
CPU time 218.78 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:34:23 PM PDT 24
Peak memory 182716 kb
Host smart-a37fcd67-3722-47eb-88c5-c95a36d1d64a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687604242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3687604242
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3111330510
Short name T441
Test name
Test status
Simulation time 35992736800 ps
CPU time 56.36 seconds
Started Mar 31 12:31:04 PM PDT 24
Finished Mar 31 12:32:00 PM PDT 24
Peak memory 182592 kb
Host smart-3ca8e7ec-f22b-48d7-888a-32b04cb57727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111330510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3111330510
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.290555919
Short name T84
Test name
Test status
Simulation time 480026866 ps
CPU time 0.82 seconds
Started Mar 31 12:30:49 PM PDT 24
Finished Mar 31 12:30:50 PM PDT 24
Peak memory 182308 kb
Host smart-911f339d-eea3-445d-9e64-6405e5d15dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290555919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.290555919
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.564950231
Short name T270
Test name
Test status
Simulation time 340811372748 ps
CPU time 249.75 seconds
Started Mar 31 12:30:58 PM PDT 24
Finished Mar 31 12:35:08 PM PDT 24
Peak memory 182552 kb
Host smart-c55c9d49-3f71-4ae9-9a55-5378d5fb068b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564950231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.564950231
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1101842548
Short name T83
Test name
Test status
Simulation time 91980096931 ps
CPU time 128.07 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:32:54 PM PDT 24
Peak memory 182676 kb
Host smart-5b896db3-b84d-4696-a63a-decc20ca49d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101842548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1101842548
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3595886001
Short name T437
Test name
Test status
Simulation time 3688751753 ps
CPU time 1.03 seconds
Started Mar 31 12:31:09 PM PDT 24
Finished Mar 31 12:31:11 PM PDT 24
Peak memory 182452 kb
Host smart-87ef76ea-5a4d-432d-a17d-4e59e46317d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595886001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3595886001
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.4075310811
Short name T23
Test name
Test status
Simulation time 171794361506 ps
CPU time 62.47 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:31:50 PM PDT 24
Peak memory 194180 kb
Host smart-53cb7250-2925-47af-aaef-87f06639f4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075310811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.4075310811
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2476015839
Short name T352
Test name
Test status
Simulation time 378835573369 ps
CPU time 348.04 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:36:33 PM PDT 24
Peak memory 182568 kb
Host smart-712cbb1c-473d-4422-8401-f04d38100742
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476015839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2476015839
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.480041305
Short name T416
Test name
Test status
Simulation time 229188288262 ps
CPU time 197.33 seconds
Started Mar 31 12:30:50 PM PDT 24
Finished Mar 31 12:34:08 PM PDT 24
Peak memory 182680 kb
Host smart-8564b1ba-55a6-407a-bb60-9f42a21e4000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480041305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.480041305
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3946831864
Short name T325
Test name
Test status
Simulation time 40824364294 ps
CPU time 67.5 seconds
Started Mar 31 12:31:05 PM PDT 24
Finished Mar 31 12:32:13 PM PDT 24
Peak memory 190756 kb
Host smart-ca2d63d5-1740-4932-81a2-b52cb5429299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946831864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3946831864
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2203101621
Short name T147
Test name
Test status
Simulation time 67884545075 ps
CPU time 568.67 seconds
Started Mar 31 12:30:49 PM PDT 24
Finished Mar 31 12:40:18 PM PDT 24
Peak memory 193136 kb
Host smart-56a2d614-40c2-46a6-900b-5ba140dc8e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203101621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2203101621
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3169341637
Short name T288
Test name
Test status
Simulation time 51746429047 ps
CPU time 34.64 seconds
Started Mar 31 12:30:35 PM PDT 24
Finished Mar 31 12:31:10 PM PDT 24
Peak memory 182636 kb
Host smart-da2997cd-9f88-40e6-958d-acdcd5e5c1ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169341637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3169341637
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.4151203177
Short name T391
Test name
Test status
Simulation time 293761185363 ps
CPU time 240.15 seconds
Started Mar 31 12:31:06 PM PDT 24
Finished Mar 31 12:35:07 PM PDT 24
Peak memory 182616 kb
Host smart-255eaed9-2bc2-43df-9fbe-a290cd3dbfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151203177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.4151203177
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1670998829
Short name T283
Test name
Test status
Simulation time 31483686778 ps
CPU time 49.05 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:31:35 PM PDT 24
Peak memory 190752 kb
Host smart-f91c5007-ad37-4c09-82ec-34bda5c448f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670998829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1670998829
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2899208496
Short name T248
Test name
Test status
Simulation time 347228767300 ps
CPU time 1416.58 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:54:49 PM PDT 24
Peak memory 194976 kb
Host smart-55419b52-add8-4afd-9bc1-694ff0e48998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899208496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2899208496
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1354702659
Short name T436
Test name
Test status
Simulation time 338842061288 ps
CPU time 619.31 seconds
Started Mar 31 12:30:41 PM PDT 24
Finished Mar 31 12:41:00 PM PDT 24
Peak memory 182632 kb
Host smart-b427ab99-5bc1-43b9-9f3a-77be811cfa9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354702659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1354702659
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.211255993
Short name T362
Test name
Test status
Simulation time 44362107505 ps
CPU time 45.43 seconds
Started Mar 31 12:30:52 PM PDT 24
Finished Mar 31 12:31:38 PM PDT 24
Peak memory 182660 kb
Host smart-a4dc6281-f841-4d3c-9a2b-7e7caa8e7f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211255993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.211255993
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3241376237
Short name T125
Test name
Test status
Simulation time 173763838112 ps
CPU time 689.72 seconds
Started Mar 31 12:31:05 PM PDT 24
Finished Mar 31 12:42:35 PM PDT 24
Peak memory 190860 kb
Host smart-3ba3f0c7-2178-41c9-acdd-d88d6e5281c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241376237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3241376237
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3277861483
Short name T373
Test name
Test status
Simulation time 316191110 ps
CPU time 1.85 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:30:47 PM PDT 24
Peak memory 192848 kb
Host smart-7189eaca-41d3-4113-b8e3-dd7c42968b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277861483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3277861483
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.29765197
Short name T250
Test name
Test status
Simulation time 57019237622 ps
CPU time 82.09 seconds
Started Mar 31 12:31:07 PM PDT 24
Finished Mar 31 12:32:29 PM PDT 24
Peak memory 182652 kb
Host smart-bb2e52ea-896d-4cca-a78f-4d1b86d6178a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29765197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.rv_timer_cfg_update_on_fly.29765197
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1970357529
Short name T403
Test name
Test status
Simulation time 332704763513 ps
CPU time 276.79 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 12:35:48 PM PDT 24
Peak memory 182620 kb
Host smart-04298c1b-ab48-44ff-9db4-5fce8984c02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970357529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1970357529
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1531123776
Short name T109
Test name
Test status
Simulation time 102348933380 ps
CPU time 174.96 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:33:42 PM PDT 24
Peak memory 190872 kb
Host smart-8c8b27e6-6c8c-4cf8-9afb-7d2ad244c7e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531123776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1531123776
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3730344678
Short name T386
Test name
Test status
Simulation time 11592227161 ps
CPU time 8.9 seconds
Started Mar 31 12:31:09 PM PDT 24
Finished Mar 31 12:31:18 PM PDT 24
Peak memory 182444 kb
Host smart-3c721b54-cffb-4989-badd-5bc0fd99cd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730344678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3730344678
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3527636681
Short name T429
Test name
Test status
Simulation time 22695105537 ps
CPU time 21.87 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:30:58 PM PDT 24
Peak memory 182716 kb
Host smart-690da23d-7352-41cc-8fc4-cb91bb76bf83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527636681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3527636681
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2275997303
Short name T376
Test name
Test status
Simulation time 388134345524 ps
CPU time 159.76 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 182680 kb
Host smart-c2ef2762-1e3a-4500-9a6b-7323b72426ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275997303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2275997303
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1138474498
Short name T300
Test name
Test status
Simulation time 95192370082 ps
CPU time 317.81 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:36:10 PM PDT 24
Peak memory 190892 kb
Host smart-4c8730c2-5e1b-4333-a82b-a0c3e9eb8ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138474498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1138474498
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2719248282
Short name T347
Test name
Test status
Simulation time 45077999553 ps
CPU time 39.03 seconds
Started Mar 31 12:30:26 PM PDT 24
Finished Mar 31 12:31:05 PM PDT 24
Peak memory 190820 kb
Host smart-dcbcb65e-cad1-4ffd-95b9-85362dfa689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719248282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2719248282
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.490343716
Short name T15
Test name
Test status
Simulation time 137207177 ps
CPU time 0.72 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:35 PM PDT 24
Peak memory 213116 kb
Host smart-5a482595-b2cd-4619-ae3a-99243cb8c25e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490343716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.490343716
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2304538626
Short name T39
Test name
Test status
Simulation time 358097757349 ps
CPU time 388.77 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:37:14 PM PDT 24
Peak memory 182648 kb
Host smart-81253bf5-d0a0-429a-bddc-490fdd551f4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304538626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2304538626
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3419682947
Short name T378
Test name
Test status
Simulation time 76964950882 ps
CPU time 108.52 seconds
Started Mar 31 12:31:04 PM PDT 24
Finished Mar 31 12:32:52 PM PDT 24
Peak memory 182872 kb
Host smart-abc2da80-0e93-488f-8e6b-4beeace8530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419682947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3419682947
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3249278610
Short name T430
Test name
Test status
Simulation time 214463473407 ps
CPU time 203.14 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:34:42 PM PDT 24
Peak memory 191052 kb
Host smart-3a185484-43be-4b15-b70c-d1a7e9da7b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249278610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3249278610
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.616889787
Short name T282
Test name
Test status
Simulation time 34547584010 ps
CPU time 57.2 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:32:12 PM PDT 24
Peak memory 182624 kb
Host smart-faab42cd-39e3-46e2-ac68-4cc981263975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616889787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.616889787
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1194634196
Short name T334
Test name
Test status
Simulation time 1998749496215 ps
CPU time 450.9 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 182648 kb
Host smart-e6d2d10f-ec03-4692-afd7-3301d5c07289
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194634196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1194634196
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1468042182
Short name T366
Test name
Test status
Simulation time 108966737920 ps
CPU time 178.45 seconds
Started Mar 31 12:30:57 PM PDT 24
Finished Mar 31 12:33:56 PM PDT 24
Peak memory 182600 kb
Host smart-e3bd38d9-593b-4554-9f7f-b7927c48b539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468042182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1468042182
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3255192454
Short name T387
Test name
Test status
Simulation time 250578090 ps
CPU time 0.59 seconds
Started Mar 31 12:31:10 PM PDT 24
Finished Mar 31 12:31:11 PM PDT 24
Peak memory 182404 kb
Host smart-8f820976-912b-4039-b097-a56a5ca5bf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255192454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3255192454
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3089339902
Short name T160
Test name
Test status
Simulation time 1896816890654 ps
CPU time 559.05 seconds
Started Mar 31 12:31:08 PM PDT 24
Finished Mar 31 12:40:27 PM PDT 24
Peak memory 182852 kb
Host smart-f47e104f-1417-4d8e-ac88-d6c906310f0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089339902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3089339902
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1577396304
Short name T359
Test name
Test status
Simulation time 2105215068 ps
CPU time 3.7 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 181956 kb
Host smart-011c6939-b96f-480c-843a-00a005571782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577396304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1577396304
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3082947953
Short name T210
Test name
Test status
Simulation time 249681728856 ps
CPU time 755.91 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:43:23 PM PDT 24
Peak memory 190820 kb
Host smart-45acc1c7-d6c9-44a9-b592-cc6c3e8ea994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082947953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3082947953
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1457555472
Short name T261
Test name
Test status
Simulation time 859039466055 ps
CPU time 365.26 seconds
Started Mar 31 12:31:06 PM PDT 24
Finished Mar 31 12:37:11 PM PDT 24
Peak memory 182852 kb
Host smart-7fba0e60-2562-42a7-895d-07fa0e5427b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457555472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1457555472
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3960184763
Short name T363
Test name
Test status
Simulation time 130752509005 ps
CPU time 205.58 seconds
Started Mar 31 12:31:13 PM PDT 24
Finished Mar 31 12:34:39 PM PDT 24
Peak memory 182332 kb
Host smart-b92ea714-aaed-4d50-8423-a1c2d057eb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960184763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3960184763
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2164545374
Short name T291
Test name
Test status
Simulation time 153413013686 ps
CPU time 181.34 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:33:49 PM PDT 24
Peak memory 190840 kb
Host smart-fbf583de-6ee0-40c1-bcff-6647dae324b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164545374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2164545374
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1887400479
Short name T152
Test name
Test status
Simulation time 300462735953 ps
CPU time 180.1 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:33:46 PM PDT 24
Peak memory 190748 kb
Host smart-38c4fd0d-8622-4f58-b904-f211cba5dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887400479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1887400479
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1790985552
Short name T193
Test name
Test status
Simulation time 2212031075454 ps
CPU time 1002.84 seconds
Started Mar 31 12:30:50 PM PDT 24
Finished Mar 31 12:47:33 PM PDT 24
Peak memory 190724 kb
Host smart-2d2aa5b4-e9a7-4267-bb7e-a3e66b888e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790985552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1790985552
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.259150859
Short name T419
Test name
Test status
Simulation time 213690773326 ps
CPU time 337.87 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:36:31 PM PDT 24
Peak memory 182632 kb
Host smart-1232a1d8-0b64-4a98-958f-b442f17211a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259150859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.259150859
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.855381506
Short name T8
Test name
Test status
Simulation time 12213041955 ps
CPU time 5.42 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:30:50 PM PDT 24
Peak memory 182640 kb
Host smart-f173b544-8b5d-4187-a3b2-1b49f2e16c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855381506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.855381506
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2620354376
Short name T104
Test name
Test status
Simulation time 457772815030 ps
CPU time 254.01 seconds
Started Mar 31 12:31:10 PM PDT 24
Finished Mar 31 12:35:24 PM PDT 24
Peak memory 190844 kb
Host smart-5dba4d65-469e-4daf-b939-87a45e1dd23e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620354376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2620354376
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3219939663
Short name T418
Test name
Test status
Simulation time 82335723 ps
CPU time 0.64 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 182412 kb
Host smart-c55fcc1b-e794-4c3c-871b-ec78c5d78bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219939663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3219939663
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2291605027
Short name T426
Test name
Test status
Simulation time 219867969455 ps
CPU time 177.81 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:33:46 PM PDT 24
Peak memory 182628 kb
Host smart-afd86ed6-4cff-4919-8930-1ff5d1ddde2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291605027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2291605027
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2909015886
Short name T118
Test name
Test status
Simulation time 72112748013 ps
CPU time 296.29 seconds
Started Mar 31 12:31:04 PM PDT 24
Finished Mar 31 12:36:01 PM PDT 24
Peak memory 182640 kb
Host smart-8c15b506-fbca-4464-88bf-5799e636e088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909015886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2909015886
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.420845450
Short name T82
Test name
Test status
Simulation time 473170263 ps
CPU time 0.77 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:30:49 PM PDT 24
Peak memory 182420 kb
Host smart-e21968f8-0475-448e-9c68-0121a8821fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420845450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.420845450
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1002652168
Short name T121
Test name
Test status
Simulation time 337112715043 ps
CPU time 280.34 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:35:26 PM PDT 24
Peak memory 182576 kb
Host smart-76293e71-6907-4a9f-a7cf-b1de3230d030
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002652168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1002652168
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.496232332
Short name T374
Test name
Test status
Simulation time 492714613786 ps
CPU time 212.14 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:34:18 PM PDT 24
Peak memory 182576 kb
Host smart-67f0f492-7215-4c28-b0be-47d6e917f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496232332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.496232332
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.859855875
Short name T410
Test name
Test status
Simulation time 199198902 ps
CPU time 0.93 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:30:50 PM PDT 24
Peak memory 182232 kb
Host smart-c1e02c41-30bc-4bff-807f-323a560936d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859855875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.859855875
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.808968558
Short name T421
Test name
Test status
Simulation time 298295947889 ps
CPU time 239.43 seconds
Started Mar 31 12:31:03 PM PDT 24
Finished Mar 31 12:35:02 PM PDT 24
Peak memory 194204 kb
Host smart-2505226b-710e-4c24-9431-943fa514e03d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808968558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
808968558
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2022739468
Short name T14
Test name
Test status
Simulation time 55625247512 ps
CPU time 301.59 seconds
Started Mar 31 12:31:06 PM PDT 24
Finished Mar 31 12:36:08 PM PDT 24
Peak memory 207788 kb
Host smart-078d28c4-e5f9-4abc-a96d-4d65caede51b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022739468 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2022739468
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.890529549
Short name T417
Test name
Test status
Simulation time 125268398448 ps
CPU time 174.03 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:34:11 PM PDT 24
Peak memory 182872 kb
Host smart-efcaf218-9e1a-46d3-9b49-e1fcb7130310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890529549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.890529549
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2761462848
Short name T225
Test name
Test status
Simulation time 143419047858 ps
CPU time 241.83 seconds
Started Mar 31 12:30:45 PM PDT 24
Finished Mar 31 12:34:47 PM PDT 24
Peak memory 190876 kb
Host smart-bbfdf1d2-43fc-44eb-a5bd-0c138ee3dce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761462848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2761462848
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3473650585
Short name T51
Test name
Test status
Simulation time 83052363 ps
CPU time 0.66 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:30:48 PM PDT 24
Peak memory 181924 kb
Host smart-5d7c1ef5-b3f1-4377-aa5c-bb5470be30e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473650585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3473650585
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4204174236
Short name T217
Test name
Test status
Simulation time 697269766838 ps
CPU time 1284.06 seconds
Started Mar 31 12:30:53 PM PDT 24
Finished Mar 31 12:52:17 PM PDT 24
Peak memory 195292 kb
Host smart-c106312e-551e-4846-815b-c449c7418cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204174236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4204174236
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1092460824
Short name T138
Test name
Test status
Simulation time 6970586576 ps
CPU time 13.1 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:31:00 PM PDT 24
Peak memory 182700 kb
Host smart-ba11490d-41c9-4c2b-8509-193afcd79a8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092460824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1092460824
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2923149440
Short name T435
Test name
Test status
Simulation time 11712234565 ps
CPU time 18.1 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:31:07 PM PDT 24
Peak memory 182644 kb
Host smart-98213aac-bffb-46c5-9115-84386c963b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923149440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2923149440
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3109769051
Short name T415
Test name
Test status
Simulation time 11313269582 ps
CPU time 18.14 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:31:05 PM PDT 24
Peak memory 182492 kb
Host smart-04c48c55-a1c9-40de-b4e0-4a21403dc8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109769051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3109769051
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3404328074
Short name T106
Test name
Test status
Simulation time 1669776813834 ps
CPU time 1420.1 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:54:27 PM PDT 24
Peak memory 195784 kb
Host smart-ab7a6e6c-6ffc-4d57-ac50-13d481755180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404328074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3404328074
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3645229664
Short name T317
Test name
Test status
Simulation time 92150085782 ps
CPU time 169.66 seconds
Started Mar 31 12:30:50 PM PDT 24
Finished Mar 31 12:33:40 PM PDT 24
Peak memory 182648 kb
Host smart-94e6ba89-27b3-42ce-8b68-59b7283c7226
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645229664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3645229664
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1768359749
Short name T405
Test name
Test status
Simulation time 325070379725 ps
CPU time 52.23 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:31:40 PM PDT 24
Peak memory 182572 kb
Host smart-06434682-ce25-4006-994f-a1a407161e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768359749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1768359749
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2335049565
Short name T215
Test name
Test status
Simulation time 1039306785965 ps
CPU time 796.1 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:44:05 PM PDT 24
Peak memory 195308 kb
Host smart-eebe96f7-3b4f-42b7-a1ba-59387acb9c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335049565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2335049565
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.1697456502
Short name T35
Test name
Test status
Simulation time 55224175282 ps
CPU time 210.52 seconds
Started Mar 31 12:31:08 PM PDT 24
Finished Mar 31 12:34:39 PM PDT 24
Peak memory 197356 kb
Host smart-6d785e94-76f5-4abe-ab9c-158fc9d3d110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697456502 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.1697456502
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3094785383
Short name T253
Test name
Test status
Simulation time 202892357021 ps
CPU time 379.38 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:36:57 PM PDT 24
Peak memory 182592 kb
Host smart-27b0cb59-ea80-4c2e-9122-5e35f7d2e796
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094785383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3094785383
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.4268789357
Short name T390
Test name
Test status
Simulation time 139390330066 ps
CPU time 96.76 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:32:25 PM PDT 24
Peak memory 182632 kb
Host smart-dae96033-97f4-4f6b-8175-8304043b4607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268789357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.4268789357
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2255170648
Short name T153
Test name
Test status
Simulation time 20216673409 ps
CPU time 34.33 seconds
Started Mar 31 12:31:13 PM PDT 24
Finished Mar 31 12:31:47 PM PDT 24
Peak memory 182620 kb
Host smart-86418e31-6488-49b1-ba74-f24a1eebb18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255170648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2255170648
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.4124263457
Short name T385
Test name
Test status
Simulation time 45900334052 ps
CPU time 65.14 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:31:45 PM PDT 24
Peak memory 182620 kb
Host smart-0e40dd6c-fc16-4f08-b7bd-19846c45d252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124263457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4124263457
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.951088296
Short name T16
Test name
Test status
Simulation time 124569203 ps
CPU time 0.82 seconds
Started Mar 31 12:30:50 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 213180 kb
Host smart-54614105-16bb-4ecb-beb4-a7f62349b273
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951088296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.951088296
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1322962644
Short name T304
Test name
Test status
Simulation time 336276551768 ps
CPU time 624.85 seconds
Started Mar 31 12:31:06 PM PDT 24
Finished Mar 31 12:41:31 PM PDT 24
Peak memory 182668 kb
Host smart-434f3c59-c6bd-4e9f-9f96-785f3eff5294
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322962644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1322962644
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2685044958
Short name T414
Test name
Test status
Simulation time 110811066352 ps
CPU time 177.07 seconds
Started Mar 31 12:31:07 PM PDT 24
Finished Mar 31 12:34:05 PM PDT 24
Peak memory 182680 kb
Host smart-b623bba3-2c45-4ba0-8059-1e4b2b0de937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685044958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2685044958
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1368979005
Short name T190
Test name
Test status
Simulation time 172091664698 ps
CPU time 318.6 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:36:07 PM PDT 24
Peak memory 190816 kb
Host smart-5cb3f3e0-5403-4bf1-b124-5fba128d5b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368979005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1368979005
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.4061320942
Short name T357
Test name
Test status
Simulation time 14520019046 ps
CPU time 24.03 seconds
Started Mar 31 12:30:51 PM PDT 24
Finished Mar 31 12:31:15 PM PDT 24
Peak memory 182620 kb
Host smart-d680d5c0-57bb-4541-b403-a77ee79f3590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061320942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4061320942
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.4217808540
Short name T331
Test name
Test status
Simulation time 480914437399 ps
CPU time 430.98 seconds
Started Mar 31 12:31:00 PM PDT 24
Finished Mar 31 12:38:11 PM PDT 24
Peak memory 190760 kb
Host smart-94594ab6-a688-4e2f-9bbb-1832a4cbfefe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217808540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.4217808540
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1829681977
Short name T194
Test name
Test status
Simulation time 32067185104 ps
CPU time 27.68 seconds
Started Mar 31 12:31:01 PM PDT 24
Finished Mar 31 12:31:28 PM PDT 24
Peak memory 182664 kb
Host smart-d9704ab5-88ac-4696-8ba7-818ac0af8dd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829681977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1829681977
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.466730240
Short name T375
Test name
Test status
Simulation time 153041681794 ps
CPU time 65.13 seconds
Started Mar 31 12:30:51 PM PDT 24
Finished Mar 31 12:31:56 PM PDT 24
Peak memory 182648 kb
Host smart-fcb8178d-8ba6-49be-9b6b-e5f155bf4fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466730240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.466730240
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.609429392
Short name T206
Test name
Test status
Simulation time 737500632829 ps
CPU time 1562.39 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:56:51 PM PDT 24
Peak memory 193488 kb
Host smart-6148f0a3-f3ce-4c9d-9666-65aceb19cce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609429392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.609429392
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2441039661
Short name T424
Test name
Test status
Simulation time 287656005371 ps
CPU time 331.73 seconds
Started Mar 31 12:31:10 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 190784 kb
Host smart-eff868b7-aa9d-45e8-afb5-0fd008c7e5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441039661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2441039661
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3303378899
Short name T284
Test name
Test status
Simulation time 658277592357 ps
CPU time 418.66 seconds
Started Mar 31 12:31:06 PM PDT 24
Finished Mar 31 12:38:05 PM PDT 24
Peak memory 182676 kb
Host smart-1b25806b-beb1-4b20-99e5-4515fd6d31bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303378899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3303378899
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1648737952
Short name T361
Test name
Test status
Simulation time 214312106068 ps
CPU time 174.31 seconds
Started Mar 31 12:31:09 PM PDT 24
Finished Mar 31 12:34:04 PM PDT 24
Peak memory 182680 kb
Host smart-931ca3e3-e917-48fe-b218-37786a1a6883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648737952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1648737952
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.876129707
Short name T235
Test name
Test status
Simulation time 130812870170 ps
CPU time 360.96 seconds
Started Mar 31 12:30:49 PM PDT 24
Finished Mar 31 12:36:51 PM PDT 24
Peak memory 190804 kb
Host smart-88d00daf-32d7-4084-9eb3-0d1a4691deb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876129707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.876129707
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1327128645
Short name T265
Test name
Test status
Simulation time 442585323241 ps
CPU time 442.58 seconds
Started Mar 31 12:30:49 PM PDT 24
Finished Mar 31 12:38:12 PM PDT 24
Peak memory 190832 kb
Host smart-d71170ca-b422-469d-83ae-124fc17775c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327128645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1327128645
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3784120351
Short name T350
Test name
Test status
Simulation time 393466651196 ps
CPU time 709.49 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:43:04 PM PDT 24
Peak memory 182732 kb
Host smart-367e17bd-aaf3-422f-8c73-7ae22baf64ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784120351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3784120351
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3804302807
Short name T46
Test name
Test status
Simulation time 25171620129 ps
CPU time 36.65 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:31:25 PM PDT 24
Peak memory 182564 kb
Host smart-bd2d14bb-025b-4eb3-a9d9-abf96456fb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804302807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3804302807
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3491188116
Short name T199
Test name
Test status
Simulation time 32669406072 ps
CPU time 228.14 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:34:35 PM PDT 24
Peak memory 190760 kb
Host smart-0857aa10-2e27-4c71-875c-5a3dd46c9922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491188116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3491188116
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.208385827
Short name T401
Test name
Test status
Simulation time 59483492 ps
CPU time 0.57 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:31:16 PM PDT 24
Peak memory 182408 kb
Host smart-695de638-c394-4775-a392-02d7b3b68a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208385827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.208385827
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1058457447
Short name T55
Test name
Test status
Simulation time 1926652113 ps
CPU time 3.61 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:31:30 PM PDT 24
Peak memory 193300 kb
Host smart-b90120cc-df81-48b8-bd42-93ca34e574fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058457447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1058457447
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.401888179
Short name T397
Test name
Test status
Simulation time 92337051642 ps
CPU time 73.38 seconds
Started Mar 31 12:31:13 PM PDT 24
Finished Mar 31 12:32:26 PM PDT 24
Peak memory 182596 kb
Host smart-e8229282-9466-46b4-be7b-b6b541adec20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401888179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.401888179
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1811885070
Short name T5
Test name
Test status
Simulation time 14191960281 ps
CPU time 20.34 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:31:36 PM PDT 24
Peak memory 194748 kb
Host smart-8d16f1e9-e5ae-4594-8c8d-a614a6c0d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811885070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1811885070
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3195888974
Short name T37
Test name
Test status
Simulation time 88999726178 ps
CPU time 192.42 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:34:33 PM PDT 24
Peak memory 205556 kb
Host smart-23628cf9-1aeb-4d20-bdd3-647224781c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195888974 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3195888974
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2347470584
Short name T262
Test name
Test status
Simulation time 531345393698 ps
CPU time 381.39 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:37:37 PM PDT 24
Peak memory 182632 kb
Host smart-5b79a4dc-c15d-4b98-8910-7ea2e32a4b35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347470584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2347470584
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.2168702234
Short name T333
Test name
Test status
Simulation time 98984093340 ps
CPU time 47.02 seconds
Started Mar 31 12:31:08 PM PDT 24
Finished Mar 31 12:31:55 PM PDT 24
Peak memory 182556 kb
Host smart-3b89e186-aee7-4605-9245-2a3a9c53439a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168702234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2168702234
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3549388459
Short name T163
Test name
Test status
Simulation time 54268400962 ps
CPU time 95.82 seconds
Started Mar 31 12:31:18 PM PDT 24
Finished Mar 31 12:32:54 PM PDT 24
Peak memory 194408 kb
Host smart-b06f566d-cdab-4da1-badf-35be142b0522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549388459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3549388459
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.812759034
Short name T182
Test name
Test status
Simulation time 215348505343 ps
CPU time 1164.73 seconds
Started Mar 31 12:31:10 PM PDT 24
Finished Mar 31 12:50:35 PM PDT 24
Peak memory 190812 kb
Host smart-67c92c80-ad1e-4d74-8cf4-6b4f440d9b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812759034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
812759034
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.412132101
Short name T186
Test name
Test status
Simulation time 577731034886 ps
CPU time 382.09 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 182688 kb
Host smart-0a70fb4a-dd43-454e-9b6a-172b105138cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412132101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.412132101
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.174595544
Short name T380
Test name
Test status
Simulation time 153931332191 ps
CPU time 112.76 seconds
Started Mar 31 12:31:10 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 182612 kb
Host smart-6eca0ad3-fc0d-4a0c-ace5-fe19561208de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174595544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.174595544
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1024899519
Short name T183
Test name
Test status
Simulation time 458929629753 ps
CPU time 573.88 seconds
Started Mar 31 12:31:09 PM PDT 24
Finished Mar 31 12:40:43 PM PDT 24
Peak memory 193820 kb
Host smart-e59a6358-065f-4d57-9cc0-e9febb2c7d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024899519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1024899519
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2008880114
Short name T221
Test name
Test status
Simulation time 249071758127 ps
CPU time 129.49 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:33:24 PM PDT 24
Peak memory 194428 kb
Host smart-2bf1bb88-6330-4b20-b574-6a99026e92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008880114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2008880114
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2722976542
Short name T103
Test name
Test status
Simulation time 513017247782 ps
CPU time 710.71 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:43:11 PM PDT 24
Peak memory 195764 kb
Host smart-155a0178-0d49-4894-8f62-caa2172dc3f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722976542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2722976542
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1095786459
Short name T263
Test name
Test status
Simulation time 667203319131 ps
CPU time 370.56 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:37:22 PM PDT 24
Peak memory 182572 kb
Host smart-3938bb5a-e211-40d4-a1ab-4c0a3b95c5ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095786459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1095786459
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1751640692
Short name T382
Test name
Test status
Simulation time 980011734109 ps
CPU time 246.44 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:35:18 PM PDT 24
Peak memory 182688 kb
Host smart-d0fea9c7-796d-4620-90ed-b18d00eacac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751640692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1751640692
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3339478688
Short name T242
Test name
Test status
Simulation time 264246834680 ps
CPU time 132.79 seconds
Started Mar 31 12:31:06 PM PDT 24
Finished Mar 31 12:33:20 PM PDT 24
Peak memory 190828 kb
Host smart-6ed831fd-9a98-4f6d-b8d9-02c42d317e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339478688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3339478688
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3043346589
Short name T434
Test name
Test status
Simulation time 203521504737 ps
CPU time 219.46 seconds
Started Mar 31 12:31:27 PM PDT 24
Finished Mar 31 12:35:07 PM PDT 24
Peak memory 182684 kb
Host smart-d508ac88-0660-4126-ac0f-be21c4262ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043346589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3043346589
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1546431597
Short name T319
Test name
Test status
Simulation time 3296443224531 ps
CPU time 1057.07 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 12:48:58 PM PDT 24
Peak memory 194448 kb
Host smart-39cd4451-2461-4f2f-9c39-98df4909282d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546431597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1546431597
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3067286847
Short name T13
Test name
Test status
Simulation time 169505660533 ps
CPU time 327.36 seconds
Started Mar 31 12:31:08 PM PDT 24
Finished Mar 31 12:36:35 PM PDT 24
Peak memory 205524 kb
Host smart-70527ce4-f259-4bee-b5e5-477ab83a5ea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067286847 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3067286847
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1052185815
Short name T402
Test name
Test status
Simulation time 5613191701 ps
CPU time 9.48 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:31:32 PM PDT 24
Peak memory 182736 kb
Host smart-7d39f0ab-1726-41bb-b4f4-778857ebed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052185815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1052185815
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3862282722
Short name T170
Test name
Test status
Simulation time 127041225735 ps
CPU time 802.38 seconds
Started Mar 31 12:31:08 PM PDT 24
Finished Mar 31 12:44:31 PM PDT 24
Peak memory 190832 kb
Host smart-8cab0249-897b-4079-800c-f40416c83294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862282722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3862282722
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2572073760
Short name T439
Test name
Test status
Simulation time 92360537868 ps
CPU time 35.74 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 12:31:57 PM PDT 24
Peak memory 182480 kb
Host smart-5b1bc8c4-221c-4968-984f-de8ef3463bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572073760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2572073760
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1537198560
Short name T218
Test name
Test status
Simulation time 1324512386697 ps
CPU time 1055.02 seconds
Started Mar 31 12:31:13 PM PDT 24
Finished Mar 31 12:48:49 PM PDT 24
Peak memory 190804 kb
Host smart-e5e5c8c5-23a0-4fc2-a7a6-1d0c513709be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537198560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1537198560
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3479704756
Short name T367
Test name
Test status
Simulation time 148827832561 ps
CPU time 70.92 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:32:28 PM PDT 24
Peak memory 182628 kb
Host smart-8374518d-7b5e-4de2-903c-577fa4c08163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479704756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3479704756
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3537967160
Short name T195
Test name
Test status
Simulation time 264683706109 ps
CPU time 253.93 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:35:29 PM PDT 24
Peak memory 190836 kb
Host smart-078a1bf3-21b5-4265-90e8-916e11d713b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537967160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3537967160
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3923776791
Short name T383
Test name
Test status
Simulation time 438233347 ps
CPU time 1.15 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:31:17 PM PDT 24
Peak memory 182492 kb
Host smart-b31d244f-618d-4068-8df9-7401b4b8f76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923776791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3923776791
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.157875886
Short name T223
Test name
Test status
Simulation time 1053142513095 ps
CPU time 513.51 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:39:48 PM PDT 24
Peak memory 190816 kb
Host smart-c9628ac1-e249-4273-a5eb-30812532e44b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157875886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
157875886
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.3346975663
Short name T36
Test name
Test status
Simulation time 27071160615 ps
CPU time 232.96 seconds
Started Mar 31 12:31:18 PM PDT 24
Finished Mar 31 12:35:12 PM PDT 24
Peak memory 205500 kb
Host smart-1c8a9c0e-db07-406a-b85d-36396678638d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346975663 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.3346975663
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2966161370
Short name T239
Test name
Test status
Simulation time 228958329371 ps
CPU time 126.5 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:32:47 PM PDT 24
Peak memory 182620 kb
Host smart-2582da0d-6725-4abc-895c-15c90b957348
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966161370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2966161370
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1952421199
Short name T370
Test name
Test status
Simulation time 406280678393 ps
CPU time 165.01 seconds
Started Mar 31 12:30:54 PM PDT 24
Finished Mar 31 12:33:39 PM PDT 24
Peak memory 182688 kb
Host smart-3154c355-217f-49f7-a8d3-23701250b705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952421199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1952421199
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2539511799
Short name T258
Test name
Test status
Simulation time 2363084856 ps
CPU time 4.14 seconds
Started Mar 31 12:30:42 PM PDT 24
Finished Mar 31 12:30:47 PM PDT 24
Peak memory 182596 kb
Host smart-fdc4e6dc-134c-463b-a01d-67c4a77317b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539511799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2539511799
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1739080294
Short name T124
Test name
Test status
Simulation time 161014001427 ps
CPU time 79.53 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:31:57 PM PDT 24
Peak memory 190740 kb
Host smart-71a68f50-7445-4fee-b2d1-c4f1f7239e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739080294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1739080294
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.179618457
Short name T264
Test name
Test status
Simulation time 122382829388 ps
CPU time 440.58 seconds
Started Mar 31 12:31:10 PM PDT 24
Finished Mar 31 12:38:31 PM PDT 24
Peak memory 190828 kb
Host smart-5320a310-dbcc-471c-9052-aa7a8ddb737e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179618457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.179618457
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3464641396
Short name T324
Test name
Test status
Simulation time 258774148038 ps
CPU time 366.12 seconds
Started Mar 31 12:31:13 PM PDT 24
Finished Mar 31 12:37:19 PM PDT 24
Peak memory 190832 kb
Host smart-e097ecb2-ddd7-4175-82dc-597fcdb731eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464641396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3464641396
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1406326237
Short name T351
Test name
Test status
Simulation time 184536157281 ps
CPU time 761.5 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:44:08 PM PDT 24
Peak memory 194492 kb
Host smart-e1c33906-ff46-4c00-b9b7-8fc1b871b766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406326237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1406326237
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2633401073
Short name T247
Test name
Test status
Simulation time 420381617938 ps
CPU time 248.43 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:35:20 PM PDT 24
Peak memory 190764 kb
Host smart-a7387b9a-403b-4845-bc66-cabcaa65ea83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633401073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2633401073
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3252443482
Short name T214
Test name
Test status
Simulation time 267700854043 ps
CPU time 259.92 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:35:37 PM PDT 24
Peak memory 194172 kb
Host smart-933e6da6-c043-4ad1-9c17-10219833d56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252443482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3252443482
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3430831295
Short name T286
Test name
Test status
Simulation time 69326684547 ps
CPU time 1371.69 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:54:09 PM PDT 24
Peak memory 190848 kb
Host smart-dd17ec99-dfac-4005-ae2f-2040403c9510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430831295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3430831295
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.264648504
Short name T266
Test name
Test status
Simulation time 48902033111 ps
CPU time 113.92 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 190868 kb
Host smart-719e0888-7bde-42d2-abea-036419f28a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264648504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.264648504
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.867440437
Short name T161
Test name
Test status
Simulation time 58336558762 ps
CPU time 177.48 seconds
Started Mar 31 12:31:18 PM PDT 24
Finished Mar 31 12:34:15 PM PDT 24
Peak memory 190860 kb
Host smart-dba990f3-2624-4494-b942-b9ba67afd6a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867440437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.867440437
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4253548737
Short name T301
Test name
Test status
Simulation time 707832520129 ps
CPU time 418.24 seconds
Started Mar 31 12:30:43 PM PDT 24
Finished Mar 31 12:37:41 PM PDT 24
Peak memory 182640 kb
Host smart-db48624a-7907-4d7b-82a1-0423549026bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253548737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4253548737
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.734998317
Short name T377
Test name
Test status
Simulation time 239444995632 ps
CPU time 175.86 seconds
Started Mar 31 12:30:54 PM PDT 24
Finished Mar 31 12:33:50 PM PDT 24
Peak memory 182608 kb
Host smart-d4229339-19f1-4748-aed2-11c148f155cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734998317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.734998317
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1231564977
Short name T306
Test name
Test status
Simulation time 50611799989 ps
CPU time 963.23 seconds
Started Mar 31 12:30:38 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 190808 kb
Host smart-09bb8955-846a-4e95-9876-5e5a66bd3dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231564977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1231564977
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2297551126
Short name T323
Test name
Test status
Simulation time 126019952174 ps
CPU time 1048.04 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:48:40 PM PDT 24
Peak memory 190876 kb
Host smart-c734a395-73ee-4467-8633-5706a64c3538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297551126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2297551126
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2572055215
Short name T187
Test name
Test status
Simulation time 82937381975 ps
CPU time 131.23 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 12:33:23 PM PDT 24
Peak memory 190892 kb
Host smart-f573a5c4-6cfc-485f-b2b2-05c955ff8824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572055215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2572055215
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3854580705
Short name T302
Test name
Test status
Simulation time 45323360278 ps
CPU time 72.12 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:32:26 PM PDT 24
Peak memory 182624 kb
Host smart-2153c26b-6227-4002-84ea-973bfd5a38b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854580705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3854580705
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2821163316
Short name T110
Test name
Test status
Simulation time 739398168862 ps
CPU time 455.06 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:38:52 PM PDT 24
Peak memory 190836 kb
Host smart-6c46d9cd-1b2b-47ef-9c9b-07ece62ad09d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821163316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2821163316
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1246442892
Short name T326
Test name
Test status
Simulation time 177019130207 ps
CPU time 268.71 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:35:54 PM PDT 24
Peak memory 190824 kb
Host smart-1a531005-db62-441a-9171-84840063c506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246442892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1246442892
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1215629101
Short name T234
Test name
Test status
Simulation time 216246154396 ps
CPU time 224.29 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:35:04 PM PDT 24
Peak memory 194408 kb
Host smart-2fe192b9-f0f0-492c-a7ea-0a23f2fa8c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215629101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1215629101
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.265142715
Short name T336
Test name
Test status
Simulation time 122514485986 ps
CPU time 403.53 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 12:37:55 PM PDT 24
Peak memory 190800 kb
Host smart-b77e24ef-8425-4451-a8f0-f1a3da3cee42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265142715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.265142715
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2717175969
Short name T329
Test name
Test status
Simulation time 136068089523 ps
CPU time 74.08 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:32:29 PM PDT 24
Peak memory 182664 kb
Host smart-11458022-fd91-4221-acc7-45167575566b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717175969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2717175969
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1181370025
Short name T404
Test name
Test status
Simulation time 122618529801 ps
CPU time 49.77 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:32:04 PM PDT 24
Peak memory 182696 kb
Host smart-ab1779c1-f60a-4e9e-9645-f1738ca8d4ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181370025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1181370025
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2242329946
Short name T273
Test name
Test status
Simulation time 190577942784 ps
CPU time 499.07 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 12:39:30 PM PDT 24
Peak memory 190836 kb
Host smart-fa0b8c3b-4958-4818-8d57-245c1b746dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242329946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2242329946
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.442696250
Short name T155
Test name
Test status
Simulation time 312791171442 ps
CPU time 311.59 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:35:47 PM PDT 24
Peak memory 182576 kb
Host smart-5651a96e-0327-4e71-909d-fa528c24f63b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442696250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.442696250
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1906930364
Short name T379
Test name
Test status
Simulation time 78826815427 ps
CPU time 58.25 seconds
Started Mar 31 12:30:46 PM PDT 24
Finished Mar 31 12:31:49 PM PDT 24
Peak memory 182624 kb
Host smart-c2bca55c-6aff-41a8-bbdb-7c84344fbb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906930364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1906930364
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3632441431
Short name T358
Test name
Test status
Simulation time 185566456677 ps
CPU time 519.79 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 190832 kb
Host smart-e282e506-9572-4251-8e67-f2bd5b3a9338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632441431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3632441431
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2873801039
Short name T276
Test name
Test status
Simulation time 57691655645 ps
CPU time 83.65 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:32:00 PM PDT 24
Peak memory 190832 kb
Host smart-1bcdf583-63f5-4d6f-9e9e-3515aab74ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873801039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2873801039
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.756700322
Short name T422
Test name
Test status
Simulation time 3090141318896 ps
CPU time 595.95 seconds
Started Mar 31 12:31:03 PM PDT 24
Finished Mar 31 12:40:59 PM PDT 24
Peak memory 190844 kb
Host smart-757aa77c-0276-428f-a13c-b83b5d6bae20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756700322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.756700322
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.4277228926
Short name T32
Test name
Test status
Simulation time 19179801899 ps
CPU time 146.77 seconds
Started Mar 31 12:30:43 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 195824 kb
Host smart-7796aeee-d4d1-4d3e-994d-c159c11cd419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277228926 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.4277228926
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3427118579
Short name T277
Test name
Test status
Simulation time 319031536520 ps
CPU time 420.72 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:38:17 PM PDT 24
Peak memory 190824 kb
Host smart-1b8ca997-70e5-4038-93af-e34971f6327f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427118579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3427118579
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.825089868
Short name T305
Test name
Test status
Simulation time 156132209997 ps
CPU time 240.49 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:35:16 PM PDT 24
Peak memory 190752 kb
Host smart-19dc7633-71a0-49df-87d0-0fa3ec2b96d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825089868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.825089868
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2822488814
Short name T280
Test name
Test status
Simulation time 471299103850 ps
CPU time 851.83 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:45:32 PM PDT 24
Peak memory 190816 kb
Host smart-82089b10-8a7f-4464-83e2-443ef1437755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822488814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2822488814
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1727023456
Short name T114
Test name
Test status
Simulation time 357078073875 ps
CPU time 413.88 seconds
Started Mar 31 12:31:18 PM PDT 24
Finished Mar 31 12:38:12 PM PDT 24
Peak memory 190816 kb
Host smart-28e26cef-3ff1-4cb4-b77c-f1b2781196cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727023456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1727023456
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1415524177
Short name T128
Test name
Test status
Simulation time 89567901557 ps
CPU time 1720.41 seconds
Started Mar 31 12:31:15 PM PDT 24
Finished Mar 31 12:59:56 PM PDT 24
Peak memory 190760 kb
Host smart-ec30cb26-c367-4b08-ba9e-684d713f7845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415524177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1415524177
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3508928304
Short name T198
Test name
Test status
Simulation time 633958450161 ps
CPU time 578.35 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:40:50 PM PDT 24
Peak memory 190868 kb
Host smart-b59d77a5-e29e-4924-ab10-864071e388d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508928304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3508928304
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.808650853
Short name T168
Test name
Test status
Simulation time 273374401826 ps
CPU time 1755.93 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 01:00:27 PM PDT 24
Peak memory 190820 kb
Host smart-95361a61-3e60-465e-9bb6-04c32190d1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808650853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.808650853
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3907607339
Short name T237
Test name
Test status
Simulation time 5414373676 ps
CPU time 6.39 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:31:21 PM PDT 24
Peak memory 182612 kb
Host smart-5f6ab973-51b9-43ef-9ebe-fc27def49d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907607339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3907607339
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2691880881
Short name T230
Test name
Test status
Simulation time 197759279312 ps
CPU time 245.9 seconds
Started Mar 31 12:31:16 PM PDT 24
Finished Mar 31 12:35:23 PM PDT 24
Peak memory 190848 kb
Host smart-d0ad23cf-7e23-45ed-8804-7b170e34a7fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691880881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2691880881
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.429796113
Short name T166
Test name
Test status
Simulation time 388554195092 ps
CPU time 396.57 seconds
Started Mar 31 12:31:10 PM PDT 24
Finished Mar 31 12:37:47 PM PDT 24
Peak memory 190744 kb
Host smart-fc5a01f9-42c4-47e1-9f64-5d4958919677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429796113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.429796113
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1228551535
Short name T112
Test name
Test status
Simulation time 19491557285 ps
CPU time 37.49 seconds
Started Mar 31 12:31:07 PM PDT 24
Finished Mar 31 12:31:45 PM PDT 24
Peak memory 182696 kb
Host smart-0ea28403-dea1-431b-af8c-a6fb481939a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228551535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1228551535
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.793564212
Short name T431
Test name
Test status
Simulation time 48757417567 ps
CPU time 68.57 seconds
Started Mar 31 12:30:47 PM PDT 24
Finished Mar 31 12:31:56 PM PDT 24
Peak memory 182684 kb
Host smart-8a9cb424-4114-4e28-ac72-76e8388f7529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793564212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.793564212
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3243391753
Short name T227
Test name
Test status
Simulation time 103479651280 ps
CPU time 368.37 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:36:49 PM PDT 24
Peak memory 190804 kb
Host smart-8b1dfd84-d407-49f2-9d8c-82086eda3046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243391753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3243391753
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.377422100
Short name T213
Test name
Test status
Simulation time 748928613841 ps
CPU time 755.84 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:43:09 PM PDT 24
Peak memory 190904 kb
Host smart-f9291767-199c-4a68-b499-9970132b32d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377422100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.377422100
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3976033838
Short name T158
Test name
Test status
Simulation time 726714457517 ps
CPU time 347.46 seconds
Started Mar 31 12:31:11 PM PDT 24
Finished Mar 31 12:36:59 PM PDT 24
Peak memory 193424 kb
Host smart-4786302e-67e7-44ab-bb8d-c533b916d61c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976033838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3976033838
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2260264644
Short name T7
Test name
Test status
Simulation time 193338916746 ps
CPU time 139.22 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:33:37 PM PDT 24
Peak memory 190860 kb
Host smart-23cd684a-8723-484d-b704-f658a9333151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260264644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2260264644
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1185389074
Short name T22
Test name
Test status
Simulation time 558443255231 ps
CPU time 1591.81 seconds
Started Mar 31 12:31:13 PM PDT 24
Finished Mar 31 12:57:46 PM PDT 24
Peak memory 190876 kb
Host smart-48d49047-0d3b-45f7-a194-8414fc4883f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185389074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1185389074
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3280653805
Short name T243
Test name
Test status
Simulation time 402187585162 ps
CPU time 648.42 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:42:05 PM PDT 24
Peak memory 190880 kb
Host smart-08f2d2a4-d989-4f28-bfd9-16f7ac14412f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280653805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3280653805
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4084933396
Short name T356
Test name
Test status
Simulation time 110963326736 ps
CPU time 201.95 seconds
Started Mar 31 12:31:12 PM PDT 24
Finished Mar 31 12:34:34 PM PDT 24
Peak memory 190884 kb
Host smart-c9f16d01-6829-4c71-96ee-c402ef3b0c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084933396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4084933396
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2310697570
Short name T113
Test name
Test status
Simulation time 32581150802 ps
CPU time 53.36 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:32:19 PM PDT 24
Peak memory 182628 kb
Host smart-7ad6961c-65d5-468a-a426-e5ef6a1df5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310697570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2310697570
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2842523157
Short name T102
Test name
Test status
Simulation time 84259355133 ps
CPU time 139.56 seconds
Started Mar 31 12:31:18 PM PDT 24
Finished Mar 31 12:33:38 PM PDT 24
Peak memory 190808 kb
Host smart-e087747b-8e25-4d0a-936a-bcefaa18ded1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842523157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2842523157
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2868048605
Short name T438
Test name
Test status
Simulation time 105854619293 ps
CPU time 93.58 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:32:51 PM PDT 24
Peak memory 190788 kb
Host smart-287549db-3244-485c-b17e-833c87848b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868048605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2868048605
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3810545495
Short name T132
Test name
Test status
Simulation time 1189583902850 ps
CPU time 710.88 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:42:25 PM PDT 24
Peak memory 182636 kb
Host smart-3cd6c514-0335-47c4-9e00-87823218c385
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810545495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3810545495
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3203400177
Short name T364
Test name
Test status
Simulation time 59564011589 ps
CPU time 87.09 seconds
Started Mar 31 12:30:39 PM PDT 24
Finished Mar 31 12:32:06 PM PDT 24
Peak memory 182620 kb
Host smart-9a588e0e-1825-4ca6-af82-367bad0dd7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203400177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3203400177
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2397948096
Short name T348
Test name
Test status
Simulation time 319071332461 ps
CPU time 1189.14 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:50:25 PM PDT 24
Peak memory 190808 kb
Host smart-35ab5bae-374f-4c98-a6f3-dad5bc1498a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397948096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2397948096
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1190786633
Short name T372
Test name
Test status
Simulation time 802618319 ps
CPU time 0.81 seconds
Started Mar 31 12:30:50 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 190996 kb
Host smart-874da07d-0b61-4e5b-a130-586e8599920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190786633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1190786633
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.938495567
Short name T369
Test name
Test status
Simulation time 17978704287 ps
CPU time 16.92 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 182644 kb
Host smart-d4bc3bc0-e98a-42c9-84f9-214c64f92c8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938495567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.938495567
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.149989142
Short name T207
Test name
Test status
Simulation time 33566041939 ps
CPU time 50.34 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:32:04 PM PDT 24
Peak memory 190736 kb
Host smart-01904f45-3a03-43bf-9818-0e2763fcead6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149989142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.149989142
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2765370800
Short name T41
Test name
Test status
Simulation time 269914501039 ps
CPU time 225.89 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:35:06 PM PDT 24
Peak memory 190896 kb
Host smart-b3c539f6-145f-4613-88f5-c55459543431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765370800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2765370800
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3685922347
Short name T322
Test name
Test status
Simulation time 194384733202 ps
CPU time 614.53 seconds
Started Mar 31 12:31:18 PM PDT 24
Finished Mar 31 12:41:32 PM PDT 24
Peak memory 190760 kb
Host smart-af768284-3ecc-4f4c-ba24-17cb051edc4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685922347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3685922347
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.742917134
Short name T342
Test name
Test status
Simulation time 131015752900 ps
CPU time 1675.92 seconds
Started Mar 31 12:31:19 PM PDT 24
Finished Mar 31 12:59:15 PM PDT 24
Peak memory 190792 kb
Host smart-b8053208-5dcf-44d4-8b74-d4cbc8cee5cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742917134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.742917134
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2571887105
Short name T238
Test name
Test status
Simulation time 1352421857808 ps
CPU time 317.67 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 190792 kb
Host smart-4ed75f5e-119d-429b-a2b1-046a618fd7f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571887105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2571887105
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3324204896
Short name T236
Test name
Test status
Simulation time 3137674250021 ps
CPU time 914.71 seconds
Started Mar 31 12:31:29 PM PDT 24
Finished Mar 31 12:46:44 PM PDT 24
Peak memory 190860 kb
Host smart-529359a8-9807-4aa1-abe4-63746674721e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324204896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3324204896
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.91926566
Short name T287
Test name
Test status
Simulation time 99315152865 ps
CPU time 177.72 seconds
Started Mar 31 12:31:17 PM PDT 24
Finished Mar 31 12:34:15 PM PDT 24
Peak memory 190828 kb
Host smart-cb65fccb-f310-4e75-89f4-2fbd829675e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91926566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.91926566
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.202609181
Short name T330
Test name
Test status
Simulation time 129242606642 ps
CPU time 407.46 seconds
Started Mar 31 12:31:21 PM PDT 24
Finished Mar 31 12:38:09 PM PDT 24
Peak memory 190868 kb
Host smart-1dde65c1-4216-4d18-a8f5-0b5318b398ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202609181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.202609181
Directory /workspace/99.rv_timer_random/latest
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