Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T505 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2260672689 Apr 02 12:24:29 PM PDT 24 Apr 02 12:24:30 PM PDT 24 57087705 ps
T506 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2317739554 Apr 02 12:24:51 PM PDT 24 Apr 02 12:24:52 PM PDT 24 36739990 ps
T507 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4061085283 Apr 02 12:24:50 PM PDT 24 Apr 02 12:24:51 PM PDT 24 53139339 ps
T508 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2117974660 Apr 02 12:26:05 PM PDT 24 Apr 02 12:26:06 PM PDT 24 12788311 ps
T509 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.36453370 Apr 02 12:24:48 PM PDT 24 Apr 02 12:24:49 PM PDT 24 579772161 ps
T510 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.923666274 Apr 02 12:24:33 PM PDT 24 Apr 02 12:24:35 PM PDT 24 41015947 ps
T511 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2553694672 Apr 02 12:24:44 PM PDT 24 Apr 02 12:24:45 PM PDT 24 92697699 ps
T512 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.325941678 Apr 02 12:24:38 PM PDT 24 Apr 02 12:24:39 PM PDT 24 62676417 ps
T513 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3050163175 Apr 02 12:24:51 PM PDT 24 Apr 02 12:24:52 PM PDT 24 62077169 ps
T514 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3220323445 Apr 02 12:24:46 PM PDT 24 Apr 02 12:24:52 PM PDT 24 2479297391 ps
T515 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3580390568 Apr 02 12:24:22 PM PDT 24 Apr 02 12:24:23 PM PDT 24 48464125 ps
T516 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.517738982 Apr 02 12:24:53 PM PDT 24 Apr 02 12:24:54 PM PDT 24 20930149 ps
T517 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.323785473 Apr 02 12:24:53 PM PDT 24 Apr 02 12:24:54 PM PDT 24 49524420 ps
T518 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1663490762 Apr 02 12:24:55 PM PDT 24 Apr 02 12:24:55 PM PDT 24 11637778 ps
T519 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.319463678 Apr 02 12:24:27 PM PDT 24 Apr 02 12:24:27 PM PDT 24 14711230 ps
T520 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3023245872 Apr 02 12:24:25 PM PDT 24 Apr 02 12:24:27 PM PDT 24 193043771 ps
T99 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4264441039 Apr 02 12:24:31 PM PDT 24 Apr 02 12:24:32 PM PDT 24 343977831 ps
T87 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1016813902 Apr 02 12:25:08 PM PDT 24 Apr 02 12:25:09 PM PDT 24 45495356 ps
T521 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2481729408 Apr 02 12:24:36 PM PDT 24 Apr 02 12:24:37 PM PDT 24 43967054 ps
T522 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2781265542 Apr 02 12:24:49 PM PDT 24 Apr 02 12:24:49 PM PDT 24 13637719 ps
T523 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2744039427 Apr 02 12:25:09 PM PDT 24 Apr 02 12:25:12 PM PDT 24 36625172 ps
T524 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3738464450 Apr 02 12:24:27 PM PDT 24 Apr 02 12:24:27 PM PDT 24 14538823 ps
T525 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.528900224 Apr 02 12:24:49 PM PDT 24 Apr 02 12:24:50 PM PDT 24 18090810 ps
T526 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3702212766 Apr 02 12:24:23 PM PDT 24 Apr 02 12:24:25 PM PDT 24 348295160 ps
T527 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1934836432 Apr 02 12:24:36 PM PDT 24 Apr 02 12:24:37 PM PDT 24 134845291 ps
T528 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3400117394 Apr 02 12:24:58 PM PDT 24 Apr 02 12:25:00 PM PDT 24 33298046 ps
T529 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1383741595 Apr 02 12:24:39 PM PDT 24 Apr 02 12:24:40 PM PDT 24 15110958 ps
T530 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.536454159 Apr 02 12:24:33 PM PDT 24 Apr 02 12:24:33 PM PDT 24 153010969 ps
T531 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3063212076 Apr 02 12:24:21 PM PDT 24 Apr 02 12:24:22 PM PDT 24 384845863 ps
T532 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.775621429 Apr 02 12:24:47 PM PDT 24 Apr 02 12:24:48 PM PDT 24 19728992 ps
T533 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2704723084 Apr 02 12:24:56 PM PDT 24 Apr 02 12:24:57 PM PDT 24 208214642 ps
T534 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3080660942 Apr 02 12:24:56 PM PDT 24 Apr 02 12:24:57 PM PDT 24 33574015 ps
T535 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3232410365 Apr 02 12:24:49 PM PDT 24 Apr 02 12:24:50 PM PDT 24 72226827 ps
T536 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.5369561 Apr 02 12:24:31 PM PDT 24 Apr 02 12:24:31 PM PDT 24 32330701 ps
T537 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3873451841 Apr 02 12:24:21 PM PDT 24 Apr 02 12:24:22 PM PDT 24 20924821 ps
T538 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.265662315 Apr 02 12:24:25 PM PDT 24 Apr 02 12:24:26 PM PDT 24 78979176 ps
T539 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3019690560 Apr 02 12:24:20 PM PDT 24 Apr 02 12:24:21 PM PDT 24 48101122 ps
T540 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3495248521 Apr 02 12:24:47 PM PDT 24 Apr 02 12:24:47 PM PDT 24 20845198 ps
T541 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.271598569 Apr 02 12:24:26 PM PDT 24 Apr 02 12:24:27 PM PDT 24 103943452 ps
T542 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.998052981 Apr 02 12:24:55 PM PDT 24 Apr 02 12:24:57 PM PDT 24 86470129 ps
T543 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1833125515 Apr 02 12:24:41 PM PDT 24 Apr 02 12:24:41 PM PDT 24 38948222 ps
T544 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1269995478 Apr 02 12:25:03 PM PDT 24 Apr 02 12:25:04 PM PDT 24 13581483 ps
T545 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1283090532 Apr 02 12:24:25 PM PDT 24 Apr 02 12:24:26 PM PDT 24 13106109 ps
T546 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.490426550 Apr 02 12:24:59 PM PDT 24 Apr 02 12:24:59 PM PDT 24 44270986 ps
T547 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.661986777 Apr 02 12:25:07 PM PDT 24 Apr 02 12:25:08 PM PDT 24 139867784 ps
T548 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2656169302 Apr 02 12:24:46 PM PDT 24 Apr 02 12:24:47 PM PDT 24 129476774 ps
T549 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.603295232 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:07 PM PDT 24 41906853 ps
T88 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2718150714 Apr 02 12:26:03 PM PDT 24 Apr 02 12:26:03 PM PDT 24 76228739 ps
T550 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.175316419 Apr 02 12:24:29 PM PDT 24 Apr 02 12:24:32 PM PDT 24 206481739 ps
T551 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2658510462 Apr 02 12:24:24 PM PDT 24 Apr 02 12:24:24 PM PDT 24 16848783 ps
T552 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3910773872 Apr 02 12:24:33 PM PDT 24 Apr 02 12:24:34 PM PDT 24 110813219 ps
T553 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4187812027 Apr 02 12:24:27 PM PDT 24 Apr 02 12:24:28 PM PDT 24 96607103 ps
T554 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1920514859 Apr 02 12:24:54 PM PDT 24 Apr 02 12:24:55 PM PDT 24 377442772 ps
T555 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2459748750 Apr 02 12:24:39 PM PDT 24 Apr 02 12:24:40 PM PDT 24 26928397 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.556417719 Apr 02 12:24:33 PM PDT 24 Apr 02 12:24:34 PM PDT 24 57109088 ps
T557 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2036880899 Apr 02 12:24:58 PM PDT 24 Apr 02 12:24:59 PM PDT 24 56938438 ps
T558 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.250157886 Apr 02 12:24:55 PM PDT 24 Apr 02 12:24:56 PM PDT 24 90690763 ps
T559 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3707748524 Apr 02 12:25:13 PM PDT 24 Apr 02 12:25:14 PM PDT 24 158086944 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.42345788 Apr 02 12:24:24 PM PDT 24 Apr 02 12:24:24 PM PDT 24 22395908 ps
T560 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.177984059 Apr 02 12:24:23 PM PDT 24 Apr 02 12:24:24 PM PDT 24 17448956 ps
T561 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1188713229 Apr 02 12:24:44 PM PDT 24 Apr 02 12:24:45 PM PDT 24 19890570 ps
T562 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2239202722 Apr 02 12:24:25 PM PDT 24 Apr 02 12:24:25 PM PDT 24 69595189 ps
T563 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2852193014 Apr 02 12:24:25 PM PDT 24 Apr 02 12:24:26 PM PDT 24 644814658 ps
T564 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.859114867 Apr 02 12:24:57 PM PDT 24 Apr 02 12:24:58 PM PDT 24 143896402 ps
T565 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.352847118 Apr 02 12:24:36 PM PDT 24 Apr 02 12:24:37 PM PDT 24 14538562 ps
T566 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3312461367 Apr 02 12:24:55 PM PDT 24 Apr 02 12:24:56 PM PDT 24 61095137 ps
T567 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.695273474 Apr 02 12:24:47 PM PDT 24 Apr 02 12:24:48 PM PDT 24 271273971 ps
T568 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2141974331 Apr 02 12:24:22 PM PDT 24 Apr 02 12:24:23 PM PDT 24 51706627 ps
T569 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3313928724 Apr 02 12:24:33 PM PDT 24 Apr 02 12:24:34 PM PDT 24 15175002 ps
T570 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.280482895 Apr 02 12:25:41 PM PDT 24 Apr 02 12:25:45 PM PDT 24 845898444 ps
T571 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1432812518 Apr 02 12:24:42 PM PDT 24 Apr 02 12:24:43 PM PDT 24 30201132 ps
T572 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.503145474 Apr 02 12:24:28 PM PDT 24 Apr 02 12:24:29 PM PDT 24 10906132 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1047946313 Apr 02 12:24:28 PM PDT 24 Apr 02 12:24:29 PM PDT 24 58421081 ps
T574 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1846586429 Apr 02 12:24:54 PM PDT 24 Apr 02 12:24:56 PM PDT 24 600150816 ps
T575 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3850023311 Apr 02 12:25:01 PM PDT 24 Apr 02 12:25:02 PM PDT 24 14981394 ps
T576 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1776169706 Apr 02 12:24:34 PM PDT 24 Apr 02 12:24:36 PM PDT 24 150467809 ps
T577 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4278600058 Apr 02 12:24:33 PM PDT 24 Apr 02 12:24:33 PM PDT 24 19614309 ps
T578 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.325872491 Apr 02 12:25:10 PM PDT 24 Apr 02 12:25:11 PM PDT 24 32179103 ps
T579 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1852777022 Apr 02 12:24:46 PM PDT 24 Apr 02 12:24:49 PM PDT 24 427146768 ps
T580 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2970120774 Apr 02 12:24:22 PM PDT 24 Apr 02 12:24:23 PM PDT 24 50487979 ps
T581 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.919661504 Apr 02 12:25:01 PM PDT 24 Apr 02 12:25:03 PM PDT 24 105975356 ps

Test location /workspace/coverage/default/121.rv_timer_random.2033680036
Short name T1
Test name
Test status
Simulation time 212612475373 ps
CPU time 477.77 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 12:40:26 PM PDT 24
Peak memory 190736 kb
Host smart-3c3f1070-8538-4245-b009-aca088bd4ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033680036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2033680036
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.4234658239
Short name T11
Test name
Test status
Simulation time 51947826994 ps
CPU time 283.26 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:36:52 PM PDT 24
Peak memory 197236 kb
Host smart-6dc9e398-cc9a-4199-ae4a-98bb9b520039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234658239 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.4234658239
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1649243198
Short name T6
Test name
Test status
Simulation time 1252406803153 ps
CPU time 3361.43 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 01:28:23 PM PDT 24
Peak memory 190800 kb
Host smart-be9e62e0-efbb-4e69-bd13-3c686f8e6e34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649243198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1649243198
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3716423158
Short name T28
Test name
Test status
Simulation time 160875484 ps
CPU time 1.11 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 195132 kb
Host smart-22dafeaf-99c2-4b66-ae44-d0d4d5981cb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716423158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3716423158
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3848267102
Short name T192
Test name
Test status
Simulation time 750982443528 ps
CPU time 3355.46 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 01:28:01 PM PDT 24
Peak memory 190816 kb
Host smart-4f97f063-dcd9-44bb-ad0d-620000d5223c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848267102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3848267102
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3231449595
Short name T140
Test name
Test status
Simulation time 704539102151 ps
CPU time 1918.75 seconds
Started Apr 02 12:32:14 PM PDT 24
Finished Apr 02 01:04:13 PM PDT 24
Peak memory 190820 kb
Host smart-e86b8e5f-3945-46ea-9ea3-29e72b8140af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231449595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3231449595
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1596609725
Short name T127
Test name
Test status
Simulation time 1903768564993 ps
CPU time 3585.06 seconds
Started Apr 02 12:32:09 PM PDT 24
Finished Apr 02 01:31:55 PM PDT 24
Peak memory 194488 kb
Host smart-2de2d027-34f7-4bc0-90e2-179b09fe8275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596609725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1596609725
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3285857349
Short name T117
Test name
Test status
Simulation time 2507982010709 ps
CPU time 1337.11 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:54:32 PM PDT 24
Peak memory 190760 kb
Host smart-61c9f1e2-f363-424b-8b50-53a7c539a5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285857349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3285857349
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1702742161
Short name T253
Test name
Test status
Simulation time 1006786131397 ps
CPU time 3077.01 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 01:23:38 PM PDT 24
Peak memory 190744 kb
Host smart-eaadc178-f3fe-49f1-b9db-b821cafe2c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702742161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1702742161
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.208273308
Short name T269
Test name
Test status
Simulation time 2003388051489 ps
CPU time 1210.4 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:52:29 PM PDT 24
Peak memory 190780 kb
Host smart-357377ae-9c88-4435-a332-c3e93b077546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208273308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
208273308
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1168831973
Short name T67
Test name
Test status
Simulation time 651844670996 ps
CPU time 1233.99 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:52:55 PM PDT 24
Peak memory 190804 kb
Host smart-ca77c5f2-39ff-439e-a0e8-2f11cc1410f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168831973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1168831973
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2238796212
Short name T167
Test name
Test status
Simulation time 572805703849 ps
CPU time 1261.56 seconds
Started Apr 02 12:32:26 PM PDT 24
Finished Apr 02 12:53:28 PM PDT 24
Peak memory 195628 kb
Host smart-6d31b368-c388-4932-9501-5ccf096db110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238796212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2238796212
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2331668299
Short name T34
Test name
Test status
Simulation time 426392747105 ps
CPU time 1053.6 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 12:49:49 PM PDT 24
Peak memory 213600 kb
Host smart-b9dc16b0-8669-448f-9357-0baad4097845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331668299 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2331668299
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2216369293
Short name T185
Test name
Test status
Simulation time 1208864998960 ps
CPU time 1331.09 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:54:15 PM PDT 24
Peak memory 195736 kb
Host smart-72aabbf1-f012-42e6-81e3-bcde4fecf671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216369293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2216369293
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.202453656
Short name T64
Test name
Test status
Simulation time 1454163038280 ps
CPU time 833.11 seconds
Started Apr 02 12:32:31 PM PDT 24
Finished Apr 02 12:46:24 PM PDT 24
Peak memory 190760 kb
Host smart-efc465b7-e756-4455-be14-64440f6ee3b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202453656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
202453656
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.379360516
Short name T16
Test name
Test status
Simulation time 371704048 ps
CPU time 0.96 seconds
Started Apr 02 12:31:38 PM PDT 24
Finished Apr 02 12:31:40 PM PDT 24
Peak memory 215388 kb
Host smart-5b412161-7fac-4d17-9fbb-2a201d3e4e23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379360516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.379360516
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2528527711
Short name T25
Test name
Test status
Simulation time 624300420860 ps
CPU time 1201.64 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:52:20 PM PDT 24
Peak memory 190800 kb
Host smart-9f731b08-903e-48fd-a1b1-8e5effc20c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528527711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2528527711
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3013081732
Short name T79
Test name
Test status
Simulation time 55541895 ps
CPU time 0.56 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 182568 kb
Host smart-58537c82-e28e-45b3-a484-4c319c16b240
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013081732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3013081732
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/147.rv_timer_random.4287672420
Short name T114
Test name
Test status
Simulation time 437083340114 ps
CPU time 415.27 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 190788 kb
Host smart-12a1f314-88ea-428d-b245-1c109f735210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287672420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4287672420
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3852895352
Short name T131
Test name
Test status
Simulation time 228773698989 ps
CPU time 265 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:36:49 PM PDT 24
Peak memory 190752 kb
Host smart-2d49321f-9eaa-4738-9df2-c47a7c1f8f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852895352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3852895352
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.702020805
Short name T19
Test name
Test status
Simulation time 91952176033 ps
CPU time 181.89 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 12:35:30 PM PDT 24
Peak memory 190748 kb
Host smart-612b6cfd-9941-485e-9f52-7ecc9e3d70c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702020805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.702020805
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3380627113
Short name T230
Test name
Test status
Simulation time 2679629162704 ps
CPU time 1231.51 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:52:50 PM PDT 24
Peak memory 190732 kb
Host smart-56b9bbc2-90ed-4877-92ee-a03e3b47bf3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380627113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3380627113
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_random.2727861862
Short name T177
Test name
Test status
Simulation time 712354320576 ps
CPU time 2497.58 seconds
Started Apr 02 12:32:14 PM PDT 24
Finished Apr 02 01:13:52 PM PDT 24
Peak memory 190752 kb
Host smart-9b79888c-ca82-4a75-b423-0997b1c667f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727861862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2727861862
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.316368182
Short name T146
Test name
Test status
Simulation time 361224888924 ps
CPU time 461.64 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 12:40:11 PM PDT 24
Peak memory 190752 kb
Host smart-d66cd327-04c2-41af-ad5e-d4476fcf0896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316368182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.316368182
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2443746012
Short name T214
Test name
Test status
Simulation time 497021734669 ps
CPU time 767.67 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 12:45:04 PM PDT 24
Peak memory 190772 kb
Host smart-054422b9-10fa-4c46-b91d-628070a4b240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443746012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2443746012
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1562231286
Short name T224
Test name
Test status
Simulation time 328779301224 ps
CPU time 617.11 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 12:42:47 PM PDT 24
Peak memory 190768 kb
Host smart-517b88d2-8865-4a85-a6f1-49c157e9ba1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562231286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1562231286
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2074807767
Short name T149
Test name
Test status
Simulation time 135539646938 ps
CPU time 302.57 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:37:26 PM PDT 24
Peak memory 190788 kb
Host smart-bdeb9a19-67cc-46fa-bf33-263a7b0ddd35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074807767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2074807767
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3871682299
Short name T171
Test name
Test status
Simulation time 807244530924 ps
CPU time 409.09 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 12:39:05 PM PDT 24
Peak memory 190788 kb
Host smart-18a13e26-9b4b-4300-b29d-3b5fc13d3220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871682299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3871682299
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2145257840
Short name T162
Test name
Test status
Simulation time 362793623045 ps
CPU time 2293.76 seconds
Started Apr 02 12:32:35 PM PDT 24
Finished Apr 02 01:10:49 PM PDT 24
Peak memory 190780 kb
Host smart-3661056b-46cf-4b73-9e0d-f88202963425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145257840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2145257840
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.2103278701
Short name T237
Test name
Test status
Simulation time 434853991705 ps
CPU time 541.39 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:41:25 PM PDT 24
Peak memory 190764 kb
Host smart-41853589-d848-437b-ad7a-75269a910bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103278701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2103278701
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2416053297
Short name T122
Test name
Test status
Simulation time 151628583385 ps
CPU time 265.29 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:36:45 PM PDT 24
Peak memory 193264 kb
Host smart-de851323-7996-4c73-833e-754c31e40a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416053297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2416053297
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2020316244
Short name T203
Test name
Test status
Simulation time 251549059278 ps
CPU time 531.69 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:41:09 PM PDT 24
Peak memory 194400 kb
Host smart-9b76b507-9797-438a-9deb-cd40798dd733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020316244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2020316244
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.684855517
Short name T236
Test name
Test status
Simulation time 110542605212 ps
CPU time 186.73 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:35:29 PM PDT 24
Peak memory 190792 kb
Host smart-8c27189e-06bc-4cdb-a8c3-8eadb0e3c0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684855517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.684855517
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1383933157
Short name T332
Test name
Test status
Simulation time 216232938086 ps
CPU time 107.11 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:34:15 PM PDT 24
Peak memory 190768 kb
Host smart-cca825c0-d22c-4f3e-901f-a14359c892bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383933157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1383933157
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.822711853
Short name T113
Test name
Test status
Simulation time 522367081204 ps
CPU time 294.87 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:37:16 PM PDT 24
Peak memory 190820 kb
Host smart-5fb3d6e9-b253-4815-b0ee-ec091cfcef77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822711853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.822711853
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2124168450
Short name T285
Test name
Test status
Simulation time 24924071250 ps
CPU time 184.58 seconds
Started Apr 02 12:32:30 PM PDT 24
Finished Apr 02 12:35:34 PM PDT 24
Peak memory 193120 kb
Host smart-8e887fad-ef63-4971-b88f-62bfb6282170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124168450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2124168450
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1549204729
Short name T174
Test name
Test status
Simulation time 145446751567 ps
CPU time 273.74 seconds
Started Apr 02 12:32:27 PM PDT 24
Finished Apr 02 12:37:01 PM PDT 24
Peak memory 190768 kb
Host smart-5eb11200-7a12-4fee-9671-8616270bc0a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549204729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1549204729
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.650242636
Short name T68
Test name
Test status
Simulation time 1766568096439 ps
CPU time 828.78 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:45:53 PM PDT 24
Peak memory 195224 kb
Host smart-ffca5778-6501-4dc2-9a4e-f8621d5894b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650242636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
650242636
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_random.227723175
Short name T218
Test name
Test status
Simulation time 176088292376 ps
CPU time 653.25 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:43:10 PM PDT 24
Peak memory 190780 kb
Host smart-dda9c767-7ca2-42c2-ba66-d1f594cd64f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227723175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.227723175
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.2624990311
Short name T223
Test name
Test status
Simulation time 232129936154 ps
CPU time 389.94 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:38:49 PM PDT 24
Peak memory 190740 kb
Host smart-d10d4fda-73a9-4967-b813-933f1ad5b50b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624990311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2624990311
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.1913878112
Short name T168
Test name
Test status
Simulation time 348139245756 ps
CPU time 441.34 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:39:43 PM PDT 24
Peak memory 190676 kb
Host smart-bb5536e0-c28d-4afa-9884-b5a4520dd48c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913878112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1913878112
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2124312080
Short name T243
Test name
Test status
Simulation time 116036966809 ps
CPU time 419.8 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:39:22 PM PDT 24
Peak memory 193016 kb
Host smart-a9ace892-dc40-42fd-886f-85f503acfb0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124312080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2124312080
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.6332615
Short name T151
Test name
Test status
Simulation time 115213251219 ps
CPU time 186.48 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:35:28 PM PDT 24
Peak memory 182476 kb
Host smart-7c213b1d-b750-4efa-8a0a-a45ab9f7e2f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6332615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
rv_timer_cfg_update_on_fly.6332615
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/59.rv_timer_random.2285983884
Short name T259
Test name
Test status
Simulation time 127709911053 ps
CPU time 2674.65 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 01:16:52 PM PDT 24
Peak memory 190760 kb
Host smart-b66396f9-910c-4da5-8e8b-f9459e5012a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285983884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2285983884
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.4099153300
Short name T220
Test name
Test status
Simulation time 307759114826 ps
CPU time 303.01 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:37:24 PM PDT 24
Peak memory 190776 kb
Host smart-f86dd807-eb7b-43de-bb9f-10561b30d75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099153300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.4099153300
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2852814538
Short name T43
Test name
Test status
Simulation time 746281004577 ps
CPU time 337.45 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:37:56 PM PDT 24
Peak memory 194024 kb
Host smart-f7238280-8844-4e97-bbc6-5a2b59241d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852814538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2852814538
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.255705069
Short name T184
Test name
Test status
Simulation time 437587918426 ps
CPU time 190.78 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:35:31 PM PDT 24
Peak memory 190792 kb
Host smart-923ff11f-6b67-45e1-94c8-dc29e220ba0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255705069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.255705069
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2361736806
Short name T257
Test name
Test status
Simulation time 143749962698 ps
CPU time 73.94 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:33:34 PM PDT 24
Peak memory 190792 kb
Host smart-b296d1d4-45ca-4dc1-8616-78fb93517ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361736806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2361736806
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.3406936809
Short name T216
Test name
Test status
Simulation time 287884277527 ps
CPU time 181.11 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:35:05 PM PDT 24
Peak memory 190768 kb
Host smart-415cae9f-d085-49c3-96b0-8f6fb2a3e389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406936809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3406936809
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3225443083
Short name T173
Test name
Test status
Simulation time 73420954308 ps
CPU time 113.25 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:34:19 PM PDT 24
Peak memory 190748 kb
Host smart-dcf432da-6f06-44ba-91db-8addb2ef40cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225443083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3225443083
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1884631431
Short name T110
Test name
Test status
Simulation time 316612440213 ps
CPU time 582.15 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:41:57 PM PDT 24
Peak memory 182588 kb
Host smart-bd9c2ae6-fbef-44a9-bf44-d4b33d032bd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884631431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1884631431
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_random.4239263079
Short name T208
Test name
Test status
Simulation time 747960568501 ps
CPU time 460.59 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:39:44 PM PDT 24
Peak memory 190724 kb
Host smart-57c5a911-b88f-4734-8441-c0e77cb73e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239263079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.4239263079
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.1151747184
Short name T154
Test name
Test status
Simulation time 1380779781792 ps
CPU time 661.12 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:43:21 PM PDT 24
Peak memory 190768 kb
Host smart-998f8818-89b0-4d6a-a5ac-291678c323d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151747184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1151747184
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.4137724675
Short name T248
Test name
Test status
Simulation time 611398828955 ps
CPU time 319.15 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:37:41 PM PDT 24
Peak memory 190776 kb
Host smart-cba04893-820a-47e0-a676-13ec0c0030fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137724675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4137724675
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2471288997
Short name T298
Test name
Test status
Simulation time 663522315629 ps
CPU time 226.28 seconds
Started Apr 02 12:32:43 PM PDT 24
Finished Apr 02 12:36:29 PM PDT 24
Peak memory 190792 kb
Host smart-8275c049-9043-4830-83cd-e7b390b11b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471288997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2471288997
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.3224561290
Short name T145
Test name
Test status
Simulation time 187604112184 ps
CPU time 827.91 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:46:09 PM PDT 24
Peak memory 190764 kb
Host smart-2894f56c-a6a7-4dba-84b4-a105445b21a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224561290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3224561290
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1321027650
Short name T143
Test name
Test status
Simulation time 279782665706 ps
CPU time 230.2 seconds
Started Apr 02 12:32:52 PM PDT 24
Finished Apr 02 12:36:42 PM PDT 24
Peak memory 190792 kb
Host smart-e28cab8b-f572-4823-a790-620e4eb7be41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321027650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1321027650
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1288162936
Short name T90
Test name
Test status
Simulation time 21032727 ps
CPU time 0.6 seconds
Started Apr 02 12:25:16 PM PDT 24
Finished Apr 02 12:25:17 PM PDT 24
Peak memory 191460 kb
Host smart-7fbff1a3-5653-4f38-9a0a-5c7f6bb3af56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288162936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1288162936
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1016813902
Short name T87
Test name
Test status
Simulation time 45495356 ps
CPU time 0.59 seconds
Started Apr 02 12:25:08 PM PDT 24
Finished Apr 02 12:25:09 PM PDT 24
Peak memory 182664 kb
Host smart-195a5f0d-dd6c-469c-aa98-829d285fe7b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016813902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1016813902
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4205226893
Short name T98
Test name
Test status
Simulation time 677736442 ps
CPU time 1.32 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 195216 kb
Host smart-eac24a48-4e0d-4a1d-ba12-da62db959475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205226893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.4205226893
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/101.rv_timer_random.2808077700
Short name T315
Test name
Test status
Simulation time 361796017165 ps
CPU time 228.95 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:36:14 PM PDT 24
Peak memory 190796 kb
Host smart-8fc0985a-50f4-49ef-8895-ed9ba0aa3e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808077700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2808077700
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.153286712
Short name T12
Test name
Test status
Simulation time 50120465776 ps
CPU time 384.36 seconds
Started Apr 02 12:32:10 PM PDT 24
Finished Apr 02 12:38:35 PM PDT 24
Peak memory 205412 kb
Host smart-99172a7f-3df7-404a-a11d-27b837e40860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153286712 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.153286712
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.2300010788
Short name T346
Test name
Test status
Simulation time 642012930018 ps
CPU time 274.62 seconds
Started Apr 02 12:32:51 PM PDT 24
Finished Apr 02 12:37:26 PM PDT 24
Peak memory 190748 kb
Host smart-0e3b75a3-1d01-4ed2-91c7-ff32f2694412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300010788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2300010788
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2108118836
Short name T207
Test name
Test status
Simulation time 235947223556 ps
CPU time 461.69 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:40:01 PM PDT 24
Peak memory 190628 kb
Host smart-de4ce31b-508d-4241-952c-8373e82fcb49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108118836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2108118836
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2755391898
Short name T121
Test name
Test status
Simulation time 109496395185 ps
CPU time 394.86 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:38:58 PM PDT 24
Peak memory 190776 kb
Host smart-9a195066-49cb-4f1c-95ec-e05a6f4e4012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755391898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2755391898
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.96105590
Short name T164
Test name
Test status
Simulation time 143924608251 ps
CPU time 246.34 seconds
Started Apr 02 12:32:34 PM PDT 24
Finished Apr 02 12:36:41 PM PDT 24
Peak memory 190784 kb
Host smart-897d2eb7-f667-4714-a516-5a199ca3eefd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96105590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.96105590
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1807408471
Short name T188
Test name
Test status
Simulation time 585604804350 ps
CPU time 1541.45 seconds
Started Apr 02 12:32:26 PM PDT 24
Finished Apr 02 12:58:08 PM PDT 24
Peak memory 190772 kb
Host smart-6ab9a19a-1f81-4f5b-a5a0-ed8dbb736db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807408471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1807408471
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.2971609624
Short name T219
Test name
Test status
Simulation time 101020251981 ps
CPU time 220.14 seconds
Started Apr 02 12:32:47 PM PDT 24
Finished Apr 02 12:36:27 PM PDT 24
Peak memory 190732 kb
Host smart-e51d92c2-6eb9-406a-bd1e-0f36a80732f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971609624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2971609624
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.691249933
Short name T289
Test name
Test status
Simulation time 113704628902 ps
CPU time 237.91 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:36:23 PM PDT 24
Peak memory 190856 kb
Host smart-a8e8d165-dd12-41d3-a0ef-3391f42dc2e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691249933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.691249933
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2333766913
Short name T135
Test name
Test status
Simulation time 123051376510 ps
CPU time 259.82 seconds
Started Apr 02 12:32:38 PM PDT 24
Finished Apr 02 12:36:58 PM PDT 24
Peak memory 190676 kb
Host smart-341a4637-5af7-4867-ab2f-f3067d96857a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333766913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2333766913
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1617834404
Short name T195
Test name
Test status
Simulation time 916219485696 ps
CPU time 290.89 seconds
Started Apr 02 12:32:47 PM PDT 24
Finished Apr 02 12:37:38 PM PDT 24
Peak memory 190748 kb
Host smart-136aff74-2b4b-4089-b051-3310a4a14200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617834404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1617834404
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.647865423
Short name T169
Test name
Test status
Simulation time 2276804054970 ps
CPU time 1430.33 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:56:16 PM PDT 24
Peak memory 190740 kb
Host smart-b7f4d04b-8e17-469e-b080-78da0071c6e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647865423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
647865423
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random.1681167625
Short name T132
Test name
Test status
Simulation time 106588242405 ps
CPU time 242.53 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:36:24 PM PDT 24
Peak memory 190684 kb
Host smart-2b928db3-4eb5-4a66-87cf-6257536e9a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681167625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1681167625
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random.751328617
Short name T344
Test name
Test status
Simulation time 229294353350 ps
CPU time 235.07 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:36:19 PM PDT 24
Peak memory 190760 kb
Host smart-07903000-16f0-45dd-9ac0-4feeba7e33f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751328617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.751328617
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1579414374
Short name T107
Test name
Test status
Simulation time 112853831559 ps
CPU time 192.16 seconds
Started Apr 02 12:32:27 PM PDT 24
Finished Apr 02 12:35:39 PM PDT 24
Peak memory 190784 kb
Host smart-67cbae40-74f7-49b9-ac07-6f739019c57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579414374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1579414374
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.929869797
Short name T180
Test name
Test status
Simulation time 1100281038266 ps
CPU time 536.85 seconds
Started Apr 02 12:32:35 PM PDT 24
Finished Apr 02 12:41:33 PM PDT 24
Peak memory 192968 kb
Host smart-e3acfb4c-dbbe-4434-abb7-9ab6a85c6dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929869797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.929869797
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.170117708
Short name T158
Test name
Test status
Simulation time 140363728518 ps
CPU time 217.48 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:36:01 PM PDT 24
Peak memory 190756 kb
Host smart-2f2011f1-4af4-4ad7-8152-4f2b8228d0b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170117708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.170117708
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2915973710
Short name T266
Test name
Test status
Simulation time 360891298956 ps
CPU time 943.64 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:48:05 PM PDT 24
Peak memory 190780 kb
Host smart-07c3c5ed-f86d-40b9-b117-f3ea9fafc309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915973710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2915973710
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1828283461
Short name T293
Test name
Test status
Simulation time 1594922692817 ps
CPU time 857.71 seconds
Started Apr 02 12:32:05 PM PDT 24
Finished Apr 02 12:46:23 PM PDT 24
Peak memory 190800 kb
Host smart-1714197c-4ab6-4a9c-9c14-61133d24b2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828283461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1828283461
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.127160015
Short name T271
Test name
Test status
Simulation time 405538909881 ps
CPU time 780.12 seconds
Started Apr 02 12:32:02 PM PDT 24
Finished Apr 02 12:45:03 PM PDT 24
Peak memory 182600 kb
Host smart-17dc5ef2-cc53-445b-b71f-db9208c49335
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127160015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.127160015
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/116.rv_timer_random.2099938122
Short name T72
Test name
Test status
Simulation time 116261704927 ps
CPU time 371.66 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 12:38:40 PM PDT 24
Peak memory 190740 kb
Host smart-a9936022-2af2-4017-9d8b-e1d82ff6acde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099938122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2099938122
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.43162852
Short name T196
Test name
Test status
Simulation time 684647243470 ps
CPU time 365.76 seconds
Started Apr 02 12:32:12 PM PDT 24
Finished Apr 02 12:38:18 PM PDT 24
Peak memory 190792 kb
Host smart-cb1c7c1b-0a97-4f29-8ba2-b42e9344a485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43162852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.43162852
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1266066750
Short name T352
Test name
Test status
Simulation time 342765378667 ps
CPU time 206.92 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:35:50 PM PDT 24
Peak memory 190792 kb
Host smart-32f6990b-86f2-4986-a430-bc1cdd30ac4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266066750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1266066750
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3798886543
Short name T323
Test name
Test status
Simulation time 66438944142 ps
CPU time 116.59 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:34:11 PM PDT 24
Peak memory 182600 kb
Host smart-811c0618-74e6-40da-9e2d-b24774e9dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798886543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3798886543
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.185418757
Short name T254
Test name
Test status
Simulation time 239128772863 ps
CPU time 2528.08 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 01:14:30 PM PDT 24
Peak memory 190796 kb
Host smart-b12ad3db-9e9e-4ee8-a37f-b798b2dbd647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185418757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.185418757
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2744346048
Short name T278
Test name
Test status
Simulation time 751096440328 ps
CPU time 411.65 seconds
Started Apr 02 12:32:05 PM PDT 24
Finished Apr 02 12:38:58 PM PDT 24
Peak memory 182612 kb
Host smart-5d41938b-8bbd-41ce-ae7d-cde221c08096
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744346048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2744346048
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/173.rv_timer_random.683740136
Short name T234
Test name
Test status
Simulation time 5168696079 ps
CPU time 8.61 seconds
Started Apr 02 12:32:30 PM PDT 24
Finished Apr 02 12:32:39 PM PDT 24
Peak memory 182588 kb
Host smart-24c03ff3-0686-4269-8848-9f88188415d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683740136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.683740136
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3713591313
Short name T202
Test name
Test status
Simulation time 84567341390 ps
CPU time 295.18 seconds
Started Apr 02 12:32:41 PM PDT 24
Finished Apr 02 12:37:36 PM PDT 24
Peak memory 190752 kb
Host smart-ff464022-7fae-4632-a8c2-4af8f3b20103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713591313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3713591313
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3922713230
Short name T102
Test name
Test status
Simulation time 140221148300 ps
CPU time 425.74 seconds
Started Apr 02 12:32:53 PM PDT 24
Finished Apr 02 12:40:00 PM PDT 24
Peak memory 190784 kb
Host smart-7c7307c1-983d-4507-87a3-ad7b23542a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922713230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3922713230
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2727789143
Short name T189
Test name
Test status
Simulation time 418100000572 ps
CPU time 224.25 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:36:03 PM PDT 24
Peak memory 182584 kb
Host smart-7c45b2bb-463f-4490-a458-0fb14558c1b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727789143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2727789143
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1339266375
Short name T44
Test name
Test status
Simulation time 1642424213137 ps
CPU time 2551.85 seconds
Started Apr 02 12:31:55 PM PDT 24
Finished Apr 02 01:14:28 PM PDT 24
Peak memory 190800 kb
Host smart-75b4aa8e-b641-4961-9408-eb974dbb14c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339266375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1339266375
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2257860279
Short name T229
Test name
Test status
Simulation time 642752418494 ps
CPU time 332.33 seconds
Started Apr 02 12:32:06 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 190736 kb
Host smart-6ddc980e-9596-49c5-b929-1c05a1a307b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257860279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2257860279
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3704140223
Short name T124
Test name
Test status
Simulation time 99740175983 ps
CPU time 112 seconds
Started Apr 02 12:32:10 PM PDT 24
Finished Apr 02 12:34:02 PM PDT 24
Peak memory 190836 kb
Host smart-e03e8722-2a5d-4fe9-87cf-f69ff553c135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704140223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3704140223
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.414709009
Short name T136
Test name
Test status
Simulation time 621585438689 ps
CPU time 1779.31 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 01:01:56 PM PDT 24
Peak memory 190824 kb
Host smart-fd6fa4ff-645b-4ad2-a53c-27999574d4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414709009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
414709009
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.777627994
Short name T186
Test name
Test status
Simulation time 42196846191 ps
CPU time 66.91 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:33:36 PM PDT 24
Peak memory 182592 kb
Host smart-c9dbe5fe-f62c-4030-81c8-0117456ead41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777627994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.777627994
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3437909601
Short name T46
Test name
Test status
Simulation time 9378454601335 ps
CPU time 2121.26 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 01:07:49 PM PDT 24
Peak memory 182596 kb
Host smart-b2503216-f164-41a3-9eca-880c800edc4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437909601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3437909601
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/55.rv_timer_random.153221137
Short name T287
Test name
Test status
Simulation time 108919433229 ps
CPU time 171.47 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:35:09 PM PDT 24
Peak memory 190712 kb
Host smart-31384256-7f17-4b78-ad59-bb55d8a37a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153221137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.153221137
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3689731721
Short name T84
Test name
Test status
Simulation time 42137581 ps
CPU time 0.82 seconds
Started Apr 02 12:25:08 PM PDT 24
Finished Apr 02 12:25:10 PM PDT 24
Peak memory 182604 kb
Host smart-978ce24b-bd4f-4b51-a54b-c2a792ff5f47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689731721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3689731721
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2744039427
Short name T523
Test name
Test status
Simulation time 36625172 ps
CPU time 1.44 seconds
Started Apr 02 12:25:09 PM PDT 24
Finished Apr 02 12:25:12 PM PDT 24
Peak memory 192168 kb
Host smart-a23e607b-5b25-4586-be9b-3911b03b8077
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744039427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2744039427
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.483831217
Short name T462
Test name
Test status
Simulation time 90288500 ps
CPU time 1.09 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:20 PM PDT 24
Peak memory 197540 kb
Host smart-1cdd437d-f83d-4116-89e5-e44e06e8f4e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483831217 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.483831217
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.260165913
Short name T82
Test name
Test status
Simulation time 40408545 ps
CPU time 0.54 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 182592 kb
Host smart-2f098db2-8dfb-41cb-bd66-fbaf39bbd9b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260165913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.260165913
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.859114867
Short name T564
Test name
Test status
Simulation time 143896402 ps
CPU time 0.5 seconds
Started Apr 02 12:24:57 PM PDT 24
Finished Apr 02 12:24:58 PM PDT 24
Peak memory 181972 kb
Host smart-69fabf2d-d496-42f9-a01c-03be6d4bfae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859114867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.859114867
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1846586429
Short name T574
Test name
Test status
Simulation time 600150816 ps
CPU time 2.14 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 197488 kb
Host smart-143353a9-34ba-418e-b5d0-719136c5012b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846586429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1846586429
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.536454159
Short name T530
Test name
Test status
Simulation time 153010969 ps
CPU time 0.63 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:33 PM PDT 24
Peak memory 182468 kb
Host smart-a253f2b5-386c-453b-9344-a8f55871e839
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536454159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.536454159
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3299421212
Short name T470
Test name
Test status
Simulation time 70057549 ps
CPU time 1.41 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:24:25 PM PDT 24
Peak memory 190972 kb
Host smart-408027f6-e268-4a76-80d7-2bf4272bfaff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299421212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3299421212
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1047946313
Short name T573
Test name
Test status
Simulation time 58421081 ps
CPU time 0.53 seconds
Started Apr 02 12:24:28 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 182636 kb
Host smart-f8c451a4-7888-46b5-9a94-a94a85d280ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047946313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1047946313
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.556417719
Short name T556
Test name
Test status
Simulation time 57109088 ps
CPU time 1.41 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:34 PM PDT 24
Peak memory 197500 kb
Host smart-a056c746-6e21-4057-9f62-7f304a2277d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556417719 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.556417719
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.503145474
Short name T572
Test name
Test status
Simulation time 10906132 ps
CPU time 0.52 seconds
Started Apr 02 12:24:28 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 182632 kb
Host smart-069cd2c6-18bf-4875-bc91-6072c615d63f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503145474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.503145474
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2481729408
Short name T521
Test name
Test status
Simulation time 43967054 ps
CPU time 0.52 seconds
Started Apr 02 12:24:36 PM PDT 24
Finished Apr 02 12:24:37 PM PDT 24
Peak memory 181956 kb
Host smart-5b921186-ae52-4d53-bdfb-6b3205a0fb62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481729408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2481729408
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2239202722
Short name T562
Test name
Test status
Simulation time 69595189 ps
CPU time 0.64 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:24:25 PM PDT 24
Peak memory 192104 kb
Host smart-9c968134-3a67-41cc-a3f6-a2bd562b888a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239202722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2239202722
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2527036910
Short name T499
Test name
Test status
Simulation time 38072630 ps
CPU time 1.74 seconds
Started Apr 02 12:24:36 PM PDT 24
Finished Apr 02 12:24:37 PM PDT 24
Peak memory 197448 kb
Host smart-6bf4c02b-5d87-47bd-a7fd-29831be64a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527036910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2527036910
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.919661504
Short name T581
Test name
Test status
Simulation time 105975356 ps
CPU time 1.06 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 194812 kb
Host smart-d30641bd-19a7-44f5-8fc9-1244f5012b31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919661504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.919661504
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3313928724
Short name T569
Test name
Test status
Simulation time 15175002 ps
CPU time 0.6 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:34 PM PDT 24
Peak memory 194004 kb
Host smart-5b539dc2-3e96-46fa-830c-54612f18bdad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313928724 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3313928724
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2658510462
Short name T551
Test name
Test status
Simulation time 16848783 ps
CPU time 0.55 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 182608 kb
Host smart-ee6a0d87-66cb-46aa-abb5-88bf3863e162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658510462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2658510462
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2262004469
Short name T463
Test name
Test status
Simulation time 21580461 ps
CPU time 0.56 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:24:26 PM PDT 24
Peak memory 182608 kb
Host smart-ec024dad-0fd4-412a-b66b-dfd074c0e567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262004469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2262004469
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3355208241
Short name T55
Test name
Test status
Simulation time 29889835 ps
CPU time 0.62 seconds
Started Apr 02 12:24:49 PM PDT 24
Finished Apr 02 12:24:49 PM PDT 24
Peak memory 192024 kb
Host smart-783f07af-2541-44e3-b3a2-077e66ad368c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355208241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3355208241
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.175316419
Short name T550
Test name
Test status
Simulation time 206481739 ps
CPU time 2.08 seconds
Started Apr 02 12:24:29 PM PDT 24
Finished Apr 02 12:24:32 PM PDT 24
Peak memory 192140 kb
Host smart-81da0b35-8fd6-46c8-a892-4ca15ec36081
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175316419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.175316419
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4237004165
Short name T487
Test name
Test status
Simulation time 47950108 ps
CPU time 0.83 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:34 PM PDT 24
Peak memory 193376 kb
Host smart-6207e04c-6b89-4962-99d5-6b53189d8756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237004165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4237004165
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2318385093
Short name T31
Test name
Test status
Simulation time 22202156 ps
CPU time 0.64 seconds
Started Apr 02 12:24:29 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 193876 kb
Host smart-5a3bfeb9-5db7-4f24-b777-f647c8bc8efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318385093 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2318385093
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4195999553
Short name T493
Test name
Test status
Simulation time 39820424 ps
CPU time 0.54 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 182348 kb
Host smart-99bc7bab-02e1-4aeb-830f-992ea4f2e741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195999553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4195999553
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.944256738
Short name T481
Test name
Test status
Simulation time 55140670 ps
CPU time 0.56 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 182488 kb
Host smart-6ad115bb-34b0-4b27-bea7-1dc0882b912b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944256738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.944256738
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.517738982
Short name T516
Test name
Test status
Simulation time 20930149 ps
CPU time 0.62 seconds
Started Apr 02 12:24:53 PM PDT 24
Finished Apr 02 12:24:54 PM PDT 24
Peak memory 191852 kb
Host smart-af904e85-947f-41f8-a560-b84dc8f151ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517738982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.517738982
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2656169302
Short name T548
Test name
Test status
Simulation time 129476774 ps
CPU time 1.2 seconds
Started Apr 02 12:24:46 PM PDT 24
Finished Apr 02 12:24:47 PM PDT 24
Peak memory 197476 kb
Host smart-b73903f8-7d11-400c-a0e1-83be4d127990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656169302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2656169302
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3686315041
Short name T490
Test name
Test status
Simulation time 61872584 ps
CPU time 0.8 seconds
Started Apr 02 12:24:27 PM PDT 24
Finished Apr 02 12:24:28 PM PDT 24
Peak memory 192740 kb
Host smart-a9f7d24c-fcb3-4d2f-b428-7101d37b43eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686315041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3686315041
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3063212076
Short name T531
Test name
Test status
Simulation time 384845863 ps
CPU time 1.04 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 197432 kb
Host smart-ac2af8a9-e0a4-43b4-87f0-307d004dde16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063212076 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3063212076
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2974038894
Short name T489
Test name
Test status
Simulation time 53798555 ps
CPU time 0.51 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 182396 kb
Host smart-f4c48090-d61b-493b-bfcb-d72531ea7657
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974038894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2974038894
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4066516882
Short name T473
Test name
Test status
Simulation time 50644426 ps
CPU time 0.53 seconds
Started Apr 02 12:24:27 PM PDT 24
Finished Apr 02 12:24:32 PM PDT 24
Peak memory 182488 kb
Host smart-7e8316c9-a14f-45cc-a720-b16af6689229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066516882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.4066516882
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1649713509
Short name T80
Test name
Test status
Simulation time 33903454 ps
CPU time 0.59 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 191468 kb
Host smart-4b32a811-549b-403f-87e9-2e4dfbac4e74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649713509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1649713509
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1991290033
Short name T477
Test name
Test status
Simulation time 93724685 ps
CPU time 2.17 seconds
Started Apr 02 12:24:53 PM PDT 24
Finished Apr 02 12:24:55 PM PDT 24
Peak memory 191192 kb
Host smart-86bac998-d652-45ed-b142-5c73a1591641
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991290033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1991290033
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3910773872
Short name T552
Test name
Test status
Simulation time 110813219 ps
CPU time 0.83 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:34 PM PDT 24
Peak memory 183112 kb
Host smart-969f5b24-2bab-41f0-b5a1-0644f69230a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910773872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3910773872
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.299305616
Short name T452
Test name
Test status
Simulation time 40412858 ps
CPU time 0.63 seconds
Started Apr 02 12:24:29 PM PDT 24
Finished Apr 02 12:24:30 PM PDT 24
Peak memory 194504 kb
Host smart-50694847-f317-442b-b41e-98bed57eee23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299305616 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.299305616
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2009690814
Short name T497
Test name
Test status
Simulation time 23490486 ps
CPU time 0.52 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:24:25 PM PDT 24
Peak memory 182424 kb
Host smart-695c5973-3cb2-42e3-91b2-a19422266ef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009690814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2009690814
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.319463678
Short name T519
Test name
Test status
Simulation time 14711230 ps
CPU time 0.52 seconds
Started Apr 02 12:24:27 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 181972 kb
Host smart-98eef98b-f485-4c76-9c97-fcac0e216ef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319463678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.319463678
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.155906043
Short name T81
Test name
Test status
Simulation time 217044415 ps
CPU time 0.7 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:24:25 PM PDT 24
Peak memory 193192 kb
Host smart-a94b910d-9506-444a-bc54-6e61bcf073d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155906043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.155906043
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.923666274
Short name T510
Test name
Test status
Simulation time 41015947 ps
CPU time 1.98 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:35 PM PDT 24
Peak memory 196960 kb
Host smart-2238b6c8-8be3-43e1-8f89-a00e57f41dca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923666274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.923666274
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1582428564
Short name T96
Test name
Test status
Simulation time 124180548 ps
CPU time 1.25 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:24:26 PM PDT 24
Peak memory 183252 kb
Host smart-e8f61a66-0c68-45a4-90a0-62c4175003b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582428564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1582428564
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3400117394
Short name T528
Test name
Test status
Simulation time 33298046 ps
CPU time 1.42 seconds
Started Apr 02 12:24:58 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 197560 kb
Host smart-5d2dd918-4f79-444f-ba64-b1a58ae807ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400117394 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3400117394
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2330261690
Short name T91
Test name
Test status
Simulation time 109229496 ps
CPU time 0.57 seconds
Started Apr 02 12:24:29 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 182608 kb
Host smart-605e5af2-7846-4e63-a056-fc4c65defee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330261690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2330261690
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2141974331
Short name T568
Test name
Test status
Simulation time 51706627 ps
CPU time 0.58 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 182460 kb
Host smart-2f6707c1-f399-409f-9670-be4737f08fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141974331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2141974331
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2164001359
Short name T504
Test name
Test status
Simulation time 72599194 ps
CPU time 0.8 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 191640 kb
Host smart-a2cc90b5-babf-4017-98e4-138299289b69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164001359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2164001359
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2978991086
Short name T469
Test name
Test status
Simulation time 229290987 ps
CPU time 2.02 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:35 PM PDT 24
Peak memory 197400 kb
Host smart-5d8dce53-f112-4dc3-b2ad-e067b6d341b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978991086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2978991086
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3702212766
Short name T526
Test name
Test status
Simulation time 348295160 ps
CPU time 1.03 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:25 PM PDT 24
Peak memory 195092 kb
Host smart-ace9703b-c016-49a1-8aa3-74a5de318cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702212766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3702212766
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.802811379
Short name T496
Test name
Test status
Simulation time 94671573 ps
CPU time 0.74 seconds
Started Apr 02 12:24:58 PM PDT 24
Finished Apr 02 12:24:58 PM PDT 24
Peak memory 196112 kb
Host smart-2ceedb7a-4646-4960-b588-c31250a8dfda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802811379 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.802811379
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2173172526
Short name T86
Test name
Test status
Simulation time 32692758 ps
CPU time 0.57 seconds
Started Apr 02 12:24:45 PM PDT 24
Finished Apr 02 12:24:46 PM PDT 24
Peak memory 182560 kb
Host smart-7498d465-acd3-4f8c-8446-9f0d13ffcba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173172526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2173172526
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1677300456
Short name T460
Test name
Test status
Simulation time 11706483 ps
CPU time 0.52 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 182180 kb
Host smart-8cd4cfd3-564e-4370-a863-4fd5b67f6f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677300456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1677300456
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2781265542
Short name T522
Test name
Test status
Simulation time 13637719 ps
CPU time 0.59 seconds
Started Apr 02 12:24:49 PM PDT 24
Finished Apr 02 12:24:49 PM PDT 24
Peak memory 191580 kb
Host smart-8e5c68c0-09e3-4210-9a59-43d26964c56e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781265542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2781265542
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2313515802
Short name T53
Test name
Test status
Simulation time 342115212 ps
CPU time 2.8 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 197488 kb
Host smart-24585f3c-f73c-401c-9486-cca897ce76f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313515802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2313515802
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4264441039
Short name T99
Test name
Test status
Simulation time 343977831 ps
CPU time 0.78 seconds
Started Apr 02 12:24:31 PM PDT 24
Finished Apr 02 12:24:32 PM PDT 24
Peak memory 193316 kb
Host smart-5c8e59a3-59b6-4aab-a0b6-acf34bf70944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264441039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4264441039
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3714118114
Short name T476
Test name
Test status
Simulation time 27307440 ps
CPU time 0.81 seconds
Started Apr 02 12:24:35 PM PDT 24
Finished Apr 02 12:24:36 PM PDT 24
Peak memory 195448 kb
Host smart-7fac15d7-2e8a-48b7-abd0-593777e0fbf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714118114 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3714118114
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3738464450
Short name T524
Test name
Test status
Simulation time 14538823 ps
CPU time 0.56 seconds
Started Apr 02 12:24:27 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 182568 kb
Host smart-ac8ac11b-653a-4664-bcbb-b137b3f6c121
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738464450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3738464450
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4155353940
Short name T495
Test name
Test status
Simulation time 34051600 ps
CPU time 0.56 seconds
Started Apr 02 12:24:27 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 182472 kb
Host smart-19d88266-91db-439f-950a-6e912dc03e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155353940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4155353940
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2700476040
Short name T94
Test name
Test status
Simulation time 31052165 ps
CPU time 0.74 seconds
Started Apr 02 12:24:28 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 193284 kb
Host smart-f54140a9-a017-42c7-b8fb-751d6748786f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700476040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2700476040
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.603295232
Short name T549
Test name
Test status
Simulation time 41906853 ps
CPU time 1.02 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 197004 kb
Host smart-4c61a68e-95c3-46db-9adb-b3692bbf5d16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603295232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.603295232
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.267930475
Short name T30
Test name
Test status
Simulation time 173122565 ps
CPU time 0.79 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:55 PM PDT 24
Peak memory 193496 kb
Host smart-c71d1bc8-06b5-4278-b09d-208e7c1416aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267930475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.267930475
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4061085283
Short name T507
Test name
Test status
Simulation time 53139339 ps
CPU time 0.98 seconds
Started Apr 02 12:24:50 PM PDT 24
Finished Apr 02 12:24:51 PM PDT 24
Peak memory 197320 kb
Host smart-a6e519fa-d845-401e-95c9-0edf14f0bd56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061085283 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4061085283
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2580316440
Short name T78
Test name
Test status
Simulation time 22315628 ps
CPU time 0.57 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 182636 kb
Host smart-4b85efb6-14ac-4e4d-a23b-0149f87d6450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580316440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2580316440
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1833125515
Short name T543
Test name
Test status
Simulation time 38948222 ps
CPU time 0.57 seconds
Started Apr 02 12:24:41 PM PDT 24
Finished Apr 02 12:24:41 PM PDT 24
Peak memory 182412 kb
Host smart-28445543-6740-4501-9edd-4e624820413c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833125515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1833125515
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1188713229
Short name T561
Test name
Test status
Simulation time 19890570 ps
CPU time 0.74 seconds
Started Apr 02 12:24:44 PM PDT 24
Finished Apr 02 12:24:45 PM PDT 24
Peak memory 193760 kb
Host smart-1a728a62-191a-4b92-a82d-b4b3a4fc422d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188713229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1188713229
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.140672782
Short name T456
Test name
Test status
Simulation time 231243604 ps
CPU time 2.48 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 197512 kb
Host smart-f7bff102-6a40-4e19-96dd-88881dfe0331
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140672782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.140672782
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.912759679
Short name T97
Test name
Test status
Simulation time 82514937 ps
CPU time 0.98 seconds
Started Apr 02 12:24:58 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 183300 kb
Host smart-0bc3b539-3333-4aa5-bbf4-79816723a0bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912759679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.912759679
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3050163175
Short name T513
Test name
Test status
Simulation time 62077169 ps
CPU time 1.37 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 197488 kb
Host smart-f08dff2d-845b-4ec1-9e08-fa8ae89b9d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050163175 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3050163175
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1695289411
Short name T472
Test name
Test status
Simulation time 49491304 ps
CPU time 0.55 seconds
Started Apr 02 12:24:29 PM PDT 24
Finished Apr 02 12:24:30 PM PDT 24
Peak memory 182616 kb
Host smart-da28f3da-aaea-4003-b6d8-26513475081c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695289411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1695289411
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.344152378
Short name T482
Test name
Test status
Simulation time 12143301 ps
CPU time 0.59 seconds
Started Apr 02 12:25:00 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 182492 kb
Host smart-1850b07f-f032-4eaf-a3f7-fed6c5908468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344152378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.344152378
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1749364724
Short name T95
Test name
Test status
Simulation time 99694007 ps
CPU time 0.81 seconds
Started Apr 02 12:24:45 PM PDT 24
Finished Apr 02 12:24:46 PM PDT 24
Peak memory 193364 kb
Host smart-2e857ef7-8f4a-48bb-a2a4-a5963079b989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749364724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1749364724
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.265662315
Short name T538
Test name
Test status
Simulation time 78979176 ps
CPU time 0.99 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:24:26 PM PDT 24
Peak memory 196304 kb
Host smart-0996668c-357f-46ef-bfca-4d2df64aa65a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265662315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.265662315
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1920514859
Short name T554
Test name
Test status
Simulation time 377442772 ps
CPU time 1.1 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:55 PM PDT 24
Peak memory 194132 kb
Host smart-0133f03d-06c3-491b-a13e-032909d88e36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920514859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1920514859
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2553694672
Short name T511
Test name
Test status
Simulation time 92697699 ps
CPU time 0.72 seconds
Started Apr 02 12:24:44 PM PDT 24
Finished Apr 02 12:24:45 PM PDT 24
Peak memory 195504 kb
Host smart-02566d1e-6e2e-4a0d-8f31-30ce3b1ca186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553694672 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2553694672
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2704723084
Short name T533
Test name
Test status
Simulation time 208214642 ps
CPU time 0.56 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 182620 kb
Host smart-c7a61a01-5adb-4ab1-9311-880038f021eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704723084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2704723084
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2388530035
Short name T492
Test name
Test status
Simulation time 82960442 ps
CPU time 0.56 seconds
Started Apr 02 12:24:48 PM PDT 24
Finished Apr 02 12:24:48 PM PDT 24
Peak memory 182408 kb
Host smart-05e13804-bb87-45f2-bbbd-9cb9c8f629ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388530035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2388530035
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2899833522
Short name T52
Test name
Test status
Simulation time 334356538 ps
CPU time 0.79 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:34 PM PDT 24
Peak memory 191636 kb
Host smart-88258a56-356f-4a1c-b907-6f65c131b2ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899833522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2899833522
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3635972777
Short name T471
Test name
Test status
Simulation time 87843947 ps
CPU time 2.26 seconds
Started Apr 02 12:24:32 PM PDT 24
Finished Apr 02 12:24:34 PM PDT 24
Peak memory 197488 kb
Host smart-fc9a6b7e-5c01-4c34-835e-fc48ef0baea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635972777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3635972777
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2852193014
Short name T563
Test name
Test status
Simulation time 644814658 ps
CPU time 1.42 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:24:26 PM PDT 24
Peak memory 183308 kb
Host smart-82927c1d-1c1a-4978-83f6-5e27fae21901
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852193014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2852193014
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.42345788
Short name T89
Test name
Test status
Simulation time 22395908 ps
CPU time 0.62 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 191772 kb
Host smart-138dd124-1b6f-4e0d-a280-ef01f5794e0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasi
ng.42345788
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3220323445
Short name T514
Test name
Test status
Simulation time 2479297391 ps
CPU time 3.44 seconds
Started Apr 02 12:24:46 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 191040 kb
Host smart-df363833-e6ec-4c54-87a5-4e1f0d9d8abc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220323445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3220323445
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.490426550
Short name T546
Test name
Test status
Simulation time 44270986 ps
CPU time 0.55 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 182664 kb
Host smart-52a821b5-64ec-484b-8908-1187e3425abc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490426550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.490426550
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1205514771
Short name T454
Test name
Test status
Simulation time 29471813 ps
CPU time 0.8 seconds
Started Apr 02 12:24:31 PM PDT 24
Finished Apr 02 12:24:32 PM PDT 24
Peak memory 196616 kb
Host smart-3e067b29-6a36-466d-a4bc-ee3286c442f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205514771 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1205514771
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2081058786
Short name T503
Test name
Test status
Simulation time 30329273 ps
CPU time 0.59 seconds
Started Apr 02 12:24:30 PM PDT 24
Finished Apr 02 12:24:31 PM PDT 24
Peak memory 191744 kb
Host smart-589b802b-4210-4516-a1bb-e37ba2202016
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081058786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2081058786
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3938008208
Short name T480
Test name
Test status
Simulation time 12556052 ps
CPU time 0.55 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 182460 kb
Host smart-25330af1-300b-4733-a58d-31ee6dc1bba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938008208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3938008208
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2260672689
Short name T505
Test name
Test status
Simulation time 57087705 ps
CPU time 0.74 seconds
Started Apr 02 12:24:29 PM PDT 24
Finished Apr 02 12:24:30 PM PDT 24
Peak memory 193364 kb
Host smart-2d560783-8b04-4d38-a4d0-cfc36dbd3255
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260672689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2260672689
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3487729948
Short name T494
Test name
Test status
Simulation time 1304030584 ps
CPU time 2.53 seconds
Started Apr 02 12:24:58 PM PDT 24
Finished Apr 02 12:25:01 PM PDT 24
Peak memory 191324 kb
Host smart-44d8a423-9676-491d-8135-690acf6ee85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487729948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3487729948
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1281076620
Short name T29
Test name
Test status
Simulation time 214592174 ps
CPU time 1.13 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 183364 kb
Host smart-531dca76-11c4-4a34-88e9-ae17141dfc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281076620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1281076620
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.930022896
Short name T500
Test name
Test status
Simulation time 60668079 ps
CPU time 0.56 seconds
Started Apr 02 12:24:45 PM PDT 24
Finished Apr 02 12:24:45 PM PDT 24
Peak memory 182532 kb
Host smart-6208e3b2-454b-4d2e-97e9-153590c8fc39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930022896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.930022896
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.325872491
Short name T578
Test name
Test status
Simulation time 32179103 ps
CPU time 0.54 seconds
Started Apr 02 12:25:10 PM PDT 24
Finished Apr 02 12:25:11 PM PDT 24
Peak memory 181976 kb
Host smart-88237cda-80cc-43d5-88f5-801c9f374862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325872491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.325872491
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.83603652
Short name T474
Test name
Test status
Simulation time 31254351 ps
CPU time 0.51 seconds
Started Apr 02 12:24:31 PM PDT 24
Finished Apr 02 12:24:32 PM PDT 24
Peak memory 182468 kb
Host smart-9db02bf8-f45a-4f7e-a553-0b5da212e5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83603652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.83603652
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1663490762
Short name T518
Test name
Test status
Simulation time 11637778 ps
CPU time 0.57 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:55 PM PDT 24
Peak memory 182116 kb
Host smart-a62f2420-9b28-4975-b4d7-60e05f6e8049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663490762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1663490762
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.775621429
Short name T532
Test name
Test status
Simulation time 19728992 ps
CPU time 0.58 seconds
Started Apr 02 12:24:47 PM PDT 24
Finished Apr 02 12:24:48 PM PDT 24
Peak memory 182164 kb
Host smart-483c445b-6230-4654-acf4-38027ba2c407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775621429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.775621429
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3495248521
Short name T540
Test name
Test status
Simulation time 20845198 ps
CPU time 0.55 seconds
Started Apr 02 12:24:47 PM PDT 24
Finished Apr 02 12:24:47 PM PDT 24
Peak memory 182456 kb
Host smart-bb1f3754-823d-4020-83b5-f9e49eda65df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495248521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3495248521
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1927759761
Short name T464
Test name
Test status
Simulation time 24871829 ps
CPU time 0.58 seconds
Started Apr 02 12:24:38 PM PDT 24
Finished Apr 02 12:24:38 PM PDT 24
Peak memory 182456 kb
Host smart-29ebeabe-4bf5-4c87-bfe2-0e28ed746c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927759761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1927759761
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.592170841
Short name T479
Test name
Test status
Simulation time 31679013 ps
CPU time 0.6 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 182464 kb
Host smart-b35d46e5-8d5e-408f-a682-1a58651e92b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592170841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.592170841
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1383741595
Short name T529
Test name
Test status
Simulation time 15110958 ps
CPU time 0.58 seconds
Started Apr 02 12:24:39 PM PDT 24
Finished Apr 02 12:24:40 PM PDT 24
Peak memory 182644 kb
Host smart-60e0093d-2757-4372-a262-8b76a962b6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383741595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1383741595
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.5369561
Short name T536
Test name
Test status
Simulation time 32330701 ps
CPU time 0.51 seconds
Started Apr 02 12:24:31 PM PDT 24
Finished Apr 02 12:24:31 PM PDT 24
Peak memory 182148 kb
Host smart-60672cc6-7a06-4286-93b8-89faa0b817ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5369561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.5369561
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2718150714
Short name T88
Test name
Test status
Simulation time 76228739 ps
CPU time 0.6 seconds
Started Apr 02 12:26:03 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 191812 kb
Host smart-ebeb445f-b31c-4f74-9904-bc2eee0751e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718150714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2718150714
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.998052981
Short name T542
Test name
Test status
Simulation time 86470129 ps
CPU time 1.43 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 192052 kb
Host smart-1bf31574-8b42-4ffd-81f1-24b3a950e498
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998052981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.998052981
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4278600058
Short name T577
Test name
Test status
Simulation time 19614309 ps
CPU time 0.57 seconds
Started Apr 02 12:24:33 PM PDT 24
Finished Apr 02 12:24:33 PM PDT 24
Peak memory 182512 kb
Host smart-50df4fd9-fde1-42c7-aa15-cc5d07e1662b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278600058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4278600058
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3580390568
Short name T515
Test name
Test status
Simulation time 48464125 ps
CPU time 0.75 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 194212 kb
Host smart-e94d5aad-fe9d-4e2b-8506-38665c1f8299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580390568 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3580390568
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1936481188
Short name T461
Test name
Test status
Simulation time 17102424 ps
CPU time 0.6 seconds
Started Apr 02 12:24:37 PM PDT 24
Finished Apr 02 12:24:38 PM PDT 24
Peak memory 191880 kb
Host smart-4d33c2e7-2438-4cdb-8dd6-d9b1bab53bab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936481188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1936481188
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.429533427
Short name T491
Test name
Test status
Simulation time 31657155 ps
CPU time 0.54 seconds
Started Apr 02 12:25:03 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 182164 kb
Host smart-52145292-89c6-4b64-9a7e-644bc90370de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429533427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.429533427
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1432812518
Short name T571
Test name
Test status
Simulation time 30201132 ps
CPU time 0.7 seconds
Started Apr 02 12:24:42 PM PDT 24
Finished Apr 02 12:24:43 PM PDT 24
Peak memory 193376 kb
Host smart-3e09352a-b9be-4034-86b3-209bd6eced04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432812518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1432812518
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4290586756
Short name T498
Test name
Test status
Simulation time 68664455 ps
CPU time 1.81 seconds
Started Apr 02 12:24:31 PM PDT 24
Finished Apr 02 12:24:33 PM PDT 24
Peak memory 197520 kb
Host smart-ee6514fe-09de-4bf0-b243-ed5e41d64823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290586756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4290586756
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3268246549
Short name T478
Test name
Test status
Simulation time 139884985 ps
CPU time 1.03 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 183100 kb
Host smart-daec7397-b140-4502-824a-00338173bae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268246549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3268246549
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1082479189
Short name T453
Test name
Test status
Simulation time 19536134 ps
CPU time 0.52 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 182016 kb
Host smart-562c514e-fbfe-4378-8302-c51daadf8f50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082479189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1082479189
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1934836432
Short name T527
Test name
Test status
Simulation time 134845291 ps
CPU time 0.55 seconds
Started Apr 02 12:24:36 PM PDT 24
Finished Apr 02 12:24:37 PM PDT 24
Peak memory 182524 kb
Host smart-663d16e9-a559-43c7-b8b8-bc73226435d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934836432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1934836432
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2459748750
Short name T555
Test name
Test status
Simulation time 26928397 ps
CPU time 0.55 seconds
Started Apr 02 12:24:39 PM PDT 24
Finished Apr 02 12:24:40 PM PDT 24
Peak memory 182452 kb
Host smart-2e364a5e-f14f-4ead-bd3d-470da910372c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459748750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2459748750
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3312461367
Short name T566
Test name
Test status
Simulation time 61095137 ps
CPU time 0.55 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 182580 kb
Host smart-9c9bcae6-cc69-44e7-bfc6-33335c2213d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312461367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3312461367
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.896954883
Short name T451
Test name
Test status
Simulation time 33182372 ps
CPU time 0.55 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 182520 kb
Host smart-a1599197-5269-4fa6-be14-46fbf8f4f6f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896954883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.896954883
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.521929809
Short name T449
Test name
Test status
Simulation time 113857348 ps
CPU time 0.53 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 182436 kb
Host smart-a83b7e1a-f066-4253-823d-e7d5f44de850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521929809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.521929809
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.528900224
Short name T525
Test name
Test status
Simulation time 18090810 ps
CPU time 0.59 seconds
Started Apr 02 12:24:49 PM PDT 24
Finished Apr 02 12:24:50 PM PDT 24
Peak memory 182416 kb
Host smart-6875b2be-841c-455c-9036-f76e5c1fe371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528900224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.528900224
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1945724674
Short name T502
Test name
Test status
Simulation time 60887007 ps
CPU time 0.56 seconds
Started Apr 02 12:24:45 PM PDT 24
Finished Apr 02 12:24:46 PM PDT 24
Peak memory 182556 kb
Host smart-38181e47-a735-41b3-96be-88d67623fccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945724674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1945724674
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3080660942
Short name T534
Test name
Test status
Simulation time 33574015 ps
CPU time 0.57 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 182468 kb
Host smart-7ec24ed5-7429-4d0f-b20a-ae52847c6377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080660942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3080660942
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1269995478
Short name T544
Test name
Test status
Simulation time 13581483 ps
CPU time 0.52 seconds
Started Apr 02 12:25:03 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 182212 kb
Host smart-68285e4e-e7c9-4383-9b5b-71192662ef6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269995478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1269995478
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2473217427
Short name T83
Test name
Test status
Simulation time 71368664 ps
CPU time 0.61 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 182620 kb
Host smart-1940be67-5c2d-4d0d-a302-deb7721a655b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473217427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2473217427
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3023245872
Short name T520
Test name
Test status
Simulation time 193043771 ps
CPU time 1.49 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 190948 kb
Host smart-5b7e11ec-c7d7-4b21-b733-950bbeafa9c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023245872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3023245872
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.681156387
Short name T465
Test name
Test status
Simulation time 22488186 ps
CPU time 0.55 seconds
Started Apr 02 12:24:34 PM PDT 24
Finished Apr 02 12:24:35 PM PDT 24
Peak memory 182620 kb
Host smart-d6bc4324-8d0e-466c-ae0e-8c5227fccabb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681156387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.681156387
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.522143182
Short name T483
Test name
Test status
Simulation time 106968726 ps
CPU time 0.79 seconds
Started Apr 02 12:24:52 PM PDT 24
Finished Apr 02 12:24:53 PM PDT 24
Peak memory 195888 kb
Host smart-8729874e-2e01-4b2a-9d72-8d61b2cf6a48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522143182 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.522143182
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2317739554
Short name T506
Test name
Test status
Simulation time 36739990 ps
CPU time 0.56 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 182596 kb
Host smart-ef8ed2f7-6a37-4870-b0d3-71fae9924fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317739554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2317739554
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2398795188
Short name T450
Test name
Test status
Simulation time 15471937 ps
CPU time 0.55 seconds
Started Apr 02 12:24:44 PM PDT 24
Finished Apr 02 12:24:45 PM PDT 24
Peak memory 182564 kb
Host smart-81392801-f3a7-43c7-9873-f65e1eaab820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398795188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2398795188
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.323785473
Short name T517
Test name
Test status
Simulation time 49524420 ps
CPU time 0.65 seconds
Started Apr 02 12:24:53 PM PDT 24
Finished Apr 02 12:24:54 PM PDT 24
Peak memory 193184 kb
Host smart-17f047b6-779d-4c8a-be97-d3123613a56a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323785473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.323785473
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.36453370
Short name T509
Test name
Test status
Simulation time 579772161 ps
CPU time 1.22 seconds
Started Apr 02 12:24:48 PM PDT 24
Finished Apr 02 12:24:49 PM PDT 24
Peak memory 197568 kb
Host smart-a4e483ef-44bf-4108-ba59-c3d2d968a9d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36453370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.36453370
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2762568881
Short name T484
Test name
Test status
Simulation time 139833127 ps
CPU time 0.83 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 193472 kb
Host smart-285f83a2-fc42-45ca-a5bd-ab2d4769c61c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762568881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2762568881
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.352847118
Short name T565
Test name
Test status
Simulation time 14538562 ps
CPU time 0.56 seconds
Started Apr 02 12:24:36 PM PDT 24
Finished Apr 02 12:24:37 PM PDT 24
Peak memory 182552 kb
Host smart-ab4aaee8-3ab2-4d13-911c-e3d8a2a9febf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352847118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.352847118
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.380338952
Short name T467
Test name
Test status
Simulation time 34505551 ps
CPU time 0.51 seconds
Started Apr 02 12:24:38 PM PDT 24
Finished Apr 02 12:24:39 PM PDT 24
Peak memory 181712 kb
Host smart-8aec710b-4f13-45b1-bc11-0046cda3ee7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380338952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.380338952
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3924659512
Short name T488
Test name
Test status
Simulation time 24497583 ps
CPU time 0.55 seconds
Started Apr 02 12:24:52 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 182556 kb
Host smart-021353c8-b67e-4c44-a2dc-cfa2fec801e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924659512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3924659512
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.888527644
Short name T468
Test name
Test status
Simulation time 18658586 ps
CPU time 0.54 seconds
Started Apr 02 12:24:40 PM PDT 24
Finished Apr 02 12:24:46 PM PDT 24
Peak memory 182516 kb
Host smart-329d8aba-949f-41b8-8ccb-b34ff475af69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888527644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.888527644
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.673637962
Short name T458
Test name
Test status
Simulation time 11845044 ps
CPU time 0.57 seconds
Started Apr 02 12:24:57 PM PDT 24
Finished Apr 02 12:24:58 PM PDT 24
Peak memory 182508 kb
Host smart-177e5755-f44e-4cdf-9227-98281ff41dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673637962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.673637962
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3850023311
Short name T575
Test name
Test status
Simulation time 14981394 ps
CPU time 0.54 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:02 PM PDT 24
Peak memory 182460 kb
Host smart-8ad477c2-71a8-4414-9c69-dfb6c7807982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850023311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3850023311
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.325941678
Short name T512
Test name
Test status
Simulation time 62676417 ps
CPU time 0.57 seconds
Started Apr 02 12:24:38 PM PDT 24
Finished Apr 02 12:24:39 PM PDT 24
Peak memory 182464 kb
Host smart-c48e344f-fa69-49cc-a17a-21b6ccf38ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325941678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.325941678
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.677235258
Short name T457
Test name
Test status
Simulation time 38754379 ps
CPU time 0.55 seconds
Started Apr 02 12:24:50 PM PDT 24
Finished Apr 02 12:24:51 PM PDT 24
Peak memory 182104 kb
Host smart-f7ce54c3-4185-4183-b22b-9c68872ded25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677235258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.677235258
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.600749625
Short name T485
Test name
Test status
Simulation time 18954857 ps
CPU time 0.52 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 181972 kb
Host smart-1857170c-c76c-46d2-9740-fab6c9fa72c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600749625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.600749625
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1789394560
Short name T455
Test name
Test status
Simulation time 17340798 ps
CPU time 0.58 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 182444 kb
Host smart-fae7109a-1af2-4250-8335-bb6fff90c604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789394560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1789394560
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.250157886
Short name T558
Test name
Test status
Simulation time 90690763 ps
CPU time 0.73 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 195536 kb
Host smart-2c0b4a18-b008-43a5-8f10-31139e170329
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250157886 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.250157886
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1283090532
Short name T545
Test name
Test status
Simulation time 13106109 ps
CPU time 0.53 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:24:26 PM PDT 24
Peak memory 182356 kb
Host smart-8c1d73be-b9ef-4e4e-945c-38092c78712a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283090532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1283090532
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2036880899
Short name T557
Test name
Test status
Simulation time 56938438 ps
CPU time 0.53 seconds
Started Apr 02 12:24:58 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 181980 kb
Host smart-e78ccebe-514b-4cfc-ae04-ce1fddbc95c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036880899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2036880899
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1541640867
Short name T92
Test name
Test status
Simulation time 113131257 ps
CPU time 0.84 seconds
Started Apr 02 12:24:58 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 191684 kb
Host smart-882cbaf5-7588-439c-bd05-98c2cfb79ffe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541640867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1541640867
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2012272363
Short name T501
Test name
Test status
Simulation time 100198267 ps
CPU time 2.23 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 197504 kb
Host smart-04963a11-8a61-4dcb-ad0d-01a90bc426f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012272363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2012272363
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4113643581
Short name T466
Test name
Test status
Simulation time 448079053 ps
CPU time 1.49 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 183336 kb
Host smart-354c9bde-c72d-4021-9b64-96e619aa41c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113643581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.4113643581
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.695273474
Short name T567
Test name
Test status
Simulation time 271273971 ps
CPU time 0.69 seconds
Started Apr 02 12:24:47 PM PDT 24
Finished Apr 02 12:24:48 PM PDT 24
Peak memory 195028 kb
Host smart-9dacc558-78e1-4c40-81bd-1ea0e4043ff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695273474 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.695273474
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3052865137
Short name T459
Test name
Test status
Simulation time 14802239 ps
CPU time 0.54 seconds
Started Apr 02 12:24:37 PM PDT 24
Finished Apr 02 12:24:38 PM PDT 24
Peak memory 182468 kb
Host smart-f2f68a4f-9ff6-465a-b533-f2938b88700e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052865137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3052865137
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3707748524
Short name T559
Test name
Test status
Simulation time 158086944 ps
CPU time 0.8 seconds
Started Apr 02 12:25:13 PM PDT 24
Finished Apr 02 12:25:14 PM PDT 24
Peak memory 193392 kb
Host smart-c7bde0d8-6502-4d17-996a-b7577ff604ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707748524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3707748524
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.271598569
Short name T541
Test name
Test status
Simulation time 103943452 ps
CPU time 1.28 seconds
Started Apr 02 12:24:26 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 197240 kb
Host smart-352d6518-36f9-4c60-b79e-1e7d501993c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271598569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.271598569
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.661986777
Short name T547
Test name
Test status
Simulation time 139867784 ps
CPU time 0.79 seconds
Started Apr 02 12:25:07 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 193272 kb
Host smart-cc56822d-274d-417a-aded-06a9263a582d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661986777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.661986777
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3873451841
Short name T537
Test name
Test status
Simulation time 20924821 ps
CPU time 0.91 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 197048 kb
Host smart-3a3b3b67-d611-4e52-aa73-aed38494284a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873451841 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3873451841
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1157923371
Short name T85
Test name
Test status
Simulation time 155614779 ps
CPU time 0.53 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 182632 kb
Host smart-b113a138-2373-488a-b186-fb737da1c8a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157923371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1157923371
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2535943976
Short name T475
Test name
Test status
Simulation time 19702956 ps
CPU time 0.52 seconds
Started Apr 02 12:26:03 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 182528 kb
Host smart-96613b44-3f9c-408d-98bc-1518a25a1feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535943976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2535943976
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3232410365
Short name T535
Test name
Test status
Simulation time 72226827 ps
CPU time 0.75 seconds
Started Apr 02 12:24:49 PM PDT 24
Finished Apr 02 12:24:50 PM PDT 24
Peak memory 193288 kb
Host smart-a020d6af-16a8-4c96-a4b6-28b42ad34135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232410365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3232410365
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.280482895
Short name T570
Test name
Test status
Simulation time 845898444 ps
CPU time 2.58 seconds
Started Apr 02 12:25:41 PM PDT 24
Finished Apr 02 12:25:45 PM PDT 24
Peak memory 196588 kb
Host smart-bd6a8cc6-8384-4b89-a635-5acd51e41bc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280482895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.280482895
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4187812027
Short name T553
Test name
Test status
Simulation time 96607103 ps
CPU time 1.18 seconds
Started Apr 02 12:24:27 PM PDT 24
Finished Apr 02 12:24:28 PM PDT 24
Peak memory 197500 kb
Host smart-fa431820-724a-4d24-bc1d-e50254bc9ff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187812027 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4187812027
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.117981452
Short name T32
Test name
Test status
Simulation time 46289422 ps
CPU time 0.57 seconds
Started Apr 02 12:24:53 PM PDT 24
Finished Apr 02 12:24:54 PM PDT 24
Peak memory 182664 kb
Host smart-1f7454e1-545f-4d01-9b9b-ac3f5dbdee68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117981452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.117981452
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2117974660
Short name T508
Test name
Test status
Simulation time 12788311 ps
CPU time 0.52 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 181980 kb
Host smart-caa818ce-ecdb-4c73-bc26-bc9763dbddc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117974660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2117974660
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.865960312
Short name T93
Test name
Test status
Simulation time 22065159 ps
CPU time 0.6 seconds
Started Apr 02 12:24:27 PM PDT 24
Finished Apr 02 12:24:38 PM PDT 24
Peak memory 192140 kb
Host smart-18497971-8f4e-4eaf-9c94-6ab4c63c53de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865960312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.865960312
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.206120795
Short name T486
Test name
Test status
Simulation time 159273331 ps
CPU time 2.52 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 197512 kb
Host smart-234780d9-991d-4770-a436-68802e4d6778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206120795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.206120795
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4194493894
Short name T54
Test name
Test status
Simulation time 144759776 ps
CPU time 1.37 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 183160 kb
Host smart-481efe0c-d6b2-452e-9dd5-29bf11fcf5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194493894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4194493894
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3019690560
Short name T539
Test name
Test status
Simulation time 48101122 ps
CPU time 0.77 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:24:21 PM PDT 24
Peak memory 196840 kb
Host smart-fe02f85c-9ba0-4b39-b09b-0f6f1ff9c253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019690560 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3019690560
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2353630636
Short name T65
Test name
Test status
Simulation time 19383151 ps
CPU time 0.53 seconds
Started Apr 02 12:24:28 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 182492 kb
Host smart-5a68405b-b98c-4389-846f-50b1a50f5fa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353630636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2353630636
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.177984059
Short name T560
Test name
Test status
Simulation time 17448956 ps
CPU time 0.54 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 182484 kb
Host smart-1bb30049-45e1-49f1-bbc1-04ba5b88eb30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177984059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.177984059
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2970120774
Short name T580
Test name
Test status
Simulation time 50487979 ps
CPU time 0.68 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 191608 kb
Host smart-753a9e7e-4dd7-4d09-a175-d824722ef518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970120774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2970120774
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1852777022
Short name T579
Test name
Test status
Simulation time 427146768 ps
CPU time 2.21 seconds
Started Apr 02 12:24:46 PM PDT 24
Finished Apr 02 12:24:49 PM PDT 24
Peak memory 197452 kb
Host smart-3fdb0746-25e9-4f09-aa09-e894f854b1e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852777022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1852777022
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1776169706
Short name T576
Test name
Test status
Simulation time 150467809 ps
CPU time 1.31 seconds
Started Apr 02 12:24:34 PM PDT 24
Finished Apr 02 12:24:36 PM PDT 24
Peak memory 183388 kb
Host smart-a7ff37c0-1d73-44bd-9c34-31593566df8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776169706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1776169706
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1265276923
Short name T59
Test name
Test status
Simulation time 706913920233 ps
CPU time 372.91 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:38:26 PM PDT 24
Peak memory 182604 kb
Host smart-724e1717-0148-4379-83ee-53c9581cd085
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265276923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1265276923
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.567984198
Short name T394
Test name
Test status
Simulation time 87290814782 ps
CPU time 136.4 seconds
Started Apr 02 12:32:02 PM PDT 24
Finished Apr 02 12:34:19 PM PDT 24
Peak memory 182592 kb
Host smart-35806c59-4722-4570-b681-314a26ba666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567984198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.567984198
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1844450575
Short name T258
Test name
Test status
Simulation time 139384500744 ps
CPU time 77.03 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:33:21 PM PDT 24
Peak memory 190736 kb
Host smart-29b8c1c0-7ed3-4603-b4fe-1fc4aa2fa428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844450575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1844450575
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2566510065
Short name T294
Test name
Test status
Simulation time 41694997170 ps
CPU time 77.25 seconds
Started Apr 02 12:31:57 PM PDT 24
Finished Apr 02 12:33:14 PM PDT 24
Peak memory 182556 kb
Host smart-c8a03f27-96b4-4089-aea7-38212ec02894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566510065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2566510065
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3882382969
Short name T408
Test name
Test status
Simulation time 568536912039 ps
CPU time 292.44 seconds
Started Apr 02 12:32:01 PM PDT 24
Finished Apr 02 12:36:53 PM PDT 24
Peak memory 182548 kb
Host smart-55fde251-f2e2-4c1c-90f3-d88f9376faf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882382969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3882382969
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.2709667782
Short name T37
Test name
Test status
Simulation time 198378492498 ps
CPU time 1320.85 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:54:10 PM PDT 24
Peak memory 213416 kb
Host smart-74df18bc-5c64-4a6b-a5ab-e798bdf54d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709667782 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2709667782
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3803695859
Short name T380
Test name
Test status
Simulation time 20767899562 ps
CPU time 9.15 seconds
Started Apr 02 12:31:49 PM PDT 24
Finished Apr 02 12:31:58 PM PDT 24
Peak memory 182572 kb
Host smart-8b1018e0-962e-4389-b50a-39f5330989e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803695859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3803695859
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1291861821
Short name T398
Test name
Test status
Simulation time 189500068497 ps
CPU time 210.67 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:35:43 PM PDT 24
Peak memory 182476 kb
Host smart-e1ac42be-afa3-49bc-8b8c-1d35eb233b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291861821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1291861821
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2125122705
Short name T423
Test name
Test status
Simulation time 1599141009 ps
CPU time 2.91 seconds
Started Apr 02 12:31:56 PM PDT 24
Finished Apr 02 12:31:59 PM PDT 24
Peak memory 182496 kb
Host smart-f047c960-d87c-4a8e-8b26-eb30a13a0fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125122705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2125122705
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1754033663
Short name T14
Test name
Test status
Simulation time 902884607 ps
CPU time 1.02 seconds
Started Apr 02 12:32:05 PM PDT 24
Finished Apr 02 12:32:07 PM PDT 24
Peak memory 213112 kb
Host smart-b23e1873-db7e-4740-95d7-f3c4db455ff9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754033663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1754033663
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1455766462
Short name T442
Test name
Test status
Simulation time 144248659254 ps
CPU time 904.38 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:47:09 PM PDT 24
Peak memory 195036 kb
Host smart-b02c7e18-786d-4ce8-b573-7ab8ca9aa946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455766462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1455766462
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3189570851
Short name T433
Test name
Test status
Simulation time 6239681280 ps
CPU time 11.11 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:32:20 PM PDT 24
Peak memory 182628 kb
Host smart-2b486832-1efd-4335-a849-ffb610b5a412
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189570851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3189570851
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.731659003
Short name T426
Test name
Test status
Simulation time 695334031259 ps
CPU time 169.07 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:35:08 PM PDT 24
Peak memory 182588 kb
Host smart-befe58df-df60-44f2-9b02-08b59c1a230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731659003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.731659003
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.759325708
Short name T100
Test name
Test status
Simulation time 317057554089 ps
CPU time 567.34 seconds
Started Apr 02 12:32:12 PM PDT 24
Finished Apr 02 12:41:39 PM PDT 24
Peak memory 190704 kb
Host smart-b188b33f-74b3-4eab-a567-59d670187c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759325708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.759325708
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.549826739
Short name T416
Test name
Test status
Simulation time 208930963 ps
CPU time 0.81 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:32:09 PM PDT 24
Peak memory 182380 kb
Host smart-4a6004d4-7153-4cb0-b64d-14a9a73be23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549826739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.549826739
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.688832466
Short name T235
Test name
Test status
Simulation time 289430511422 ps
CPU time 454.83 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 195224 kb
Host smart-cbd19ffe-204a-4b1c-be42-b53b14cb230b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688832466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
688832466
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.2768778191
Short name T281
Test name
Test status
Simulation time 81688760134 ps
CPU time 143.13 seconds
Started Apr 02 12:32:51 PM PDT 24
Finished Apr 02 12:35:14 PM PDT 24
Peak memory 194084 kb
Host smart-bf3149f4-8020-4ac2-ad4d-b79b46450034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768778191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2768778191
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1769053682
Short name T181
Test name
Test status
Simulation time 461706340561 ps
CPU time 820.19 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 12:45:56 PM PDT 24
Peak memory 190620 kb
Host smart-1de5adbf-c2c8-4c3a-b4cf-8890eccca524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769053682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1769053682
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2141601115
Short name T328
Test name
Test status
Simulation time 600334710992 ps
CPU time 301.3 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:37:17 PM PDT 24
Peak memory 190744 kb
Host smart-48e9b0b9-1d15-4651-b0aa-373ca4239ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141601115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2141601115
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1805434471
Short name T197
Test name
Test status
Simulation time 50822309628 ps
CPU time 43.84 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:33:02 PM PDT 24
Peak memory 182644 kb
Host smart-610fc04d-4ba3-4c66-b8b1-c85bc11971b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805434471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1805434471
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.407192627
Short name T199
Test name
Test status
Simulation time 167723932667 ps
CPU time 948.55 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 12:48:17 PM PDT 24
Peak memory 190748 kb
Host smart-03f173b4-34d5-4236-908d-70a5d505a2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407192627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.407192627
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.196709616
Short name T427
Test name
Test status
Simulation time 154590048227 ps
CPU time 412.63 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:39:11 PM PDT 24
Peak memory 190776 kb
Host smart-cdacc63c-6222-4dac-a672-fee9793893b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196709616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.196709616
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3828185391
Short name T329
Test name
Test status
Simulation time 198921079483 ps
CPU time 331.52 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:37:55 PM PDT 24
Peak memory 194120 kb
Host smart-1041f274-5c28-45f7-b00d-faac73e47648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828185391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3828185391
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.497285359
Short name T286
Test name
Test status
Simulation time 546928742658 ps
CPU time 1942.58 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 190824 kb
Host smart-d4e29654-93bc-44d2-9aa7-21223c39e864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497285359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.497285359
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1030772033
Short name T105
Test name
Test status
Simulation time 946599991552 ps
CPU time 1070.92 seconds
Started Apr 02 12:32:10 PM PDT 24
Finished Apr 02 12:50:01 PM PDT 24
Peak memory 182332 kb
Host smart-934134cb-b24e-46c5-901d-3c86022c1efe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030772033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1030772033
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2599903117
Short name T74
Test name
Test status
Simulation time 93244435873 ps
CPU time 133.12 seconds
Started Apr 02 12:32:05 PM PDT 24
Finished Apr 02 12:34:18 PM PDT 24
Peak memory 182564 kb
Host smart-7beb1b53-118a-4f23-b5e3-a74a7669bbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599903117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2599903117
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2796947446
Short name T274
Test name
Test status
Simulation time 13988396219 ps
CPU time 18.89 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:32:32 PM PDT 24
Peak memory 190840 kb
Host smart-a8bcaf5f-e35e-4eae-90f3-eee645d66616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796947446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2796947446
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2017260481
Short name T201
Test name
Test status
Simulation time 51212410081 ps
CPU time 81.86 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:33:45 PM PDT 24
Peak memory 182400 kb
Host smart-5fc16acc-e33b-476c-8813-4b7231d4cea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017260481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2017260481
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2359965765
Short name T103
Test name
Test status
Simulation time 7771710040 ps
CPU time 13.42 seconds
Started Apr 02 12:32:33 PM PDT 24
Finished Apr 02 12:32:46 PM PDT 24
Peak memory 182540 kb
Host smart-4f8e2551-30ac-4beb-879e-393b9f432078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359965765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2359965765
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3034014065
Short name T221
Test name
Test status
Simulation time 43624308508 ps
CPU time 394.99 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:38:59 PM PDT 24
Peak memory 182572 kb
Host smart-08fb9e70-a198-447d-9f4b-7e2bcad3ea3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034014065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3034014065
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1174495950
Short name T276
Test name
Test status
Simulation time 108765192794 ps
CPU time 110.2 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:34:10 PM PDT 24
Peak memory 190628 kb
Host smart-1e4d6efc-d23f-428e-ab10-fcff745b0c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174495950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1174495950
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1815131197
Short name T183
Test name
Test status
Simulation time 56947776105 ps
CPU time 99.1 seconds
Started Apr 02 12:31:58 PM PDT 24
Finished Apr 02 12:33:37 PM PDT 24
Peak memory 182532 kb
Host smart-b5d29dda-d43d-4f00-a06a-b66f03423a22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815131197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1815131197
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1558517188
Short name T418
Test name
Test status
Simulation time 306620489076 ps
CPU time 254.2 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:36:19 PM PDT 24
Peak memory 182544 kb
Host smart-2b33eb9a-1fde-4ae0-95bf-12caef067dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558517188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1558517188
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1864482057
Short name T350
Test name
Test status
Simulation time 316795241092 ps
CPU time 128.51 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:34:26 PM PDT 24
Peak memory 190736 kb
Host smart-27738371-f770-4ca4-8f5c-c175f8738502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864482057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1864482057
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2324441792
Short name T198
Test name
Test status
Simulation time 775257979937 ps
CPU time 673.51 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:43:17 PM PDT 24
Peak memory 190780 kb
Host smart-970960e8-93e8-4262-95ab-ca70b4e3a314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324441792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2324441792
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.2706818330
Short name T212
Test name
Test status
Simulation time 508889356269 ps
CPU time 251.33 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 12:36:41 PM PDT 24
Peak memory 190748 kb
Host smart-fb878e70-bddb-4509-921d-9243d617b4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706818330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2706818330
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.4260583573
Short name T20
Test name
Test status
Simulation time 98405566928 ps
CPU time 505.68 seconds
Started Apr 02 12:32:31 PM PDT 24
Finished Apr 02 12:40:57 PM PDT 24
Peak memory 190748 kb
Host smart-4ff9949b-62be-48c3-a759-397b9d141347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260583573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4260583573
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.807835374
Short name T252
Test name
Test status
Simulation time 147519617504 ps
CPU time 322.45 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 190756 kb
Host smart-3090e981-fe3d-4940-acd0-76a5fa94ac8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807835374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.807835374
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1088646620
Short name T111
Test name
Test status
Simulation time 30474130579 ps
CPU time 54.45 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:33:16 PM PDT 24
Peak memory 182588 kb
Host smart-1ff88cba-bf46-48d4-a249-c56d8862385b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088646620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1088646620
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2152099059
Short name T295
Test name
Test status
Simulation time 1683833842 ps
CPU time 3.53 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:32:28 PM PDT 24
Peak memory 182516 kb
Host smart-a1238f71-5f78-4999-b435-4dcba97180da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152099059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2152099059
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1160413832
Short name T213
Test name
Test status
Simulation time 90507264205 ps
CPU time 150.13 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:34:48 PM PDT 24
Peak memory 190740 kb
Host smart-64d23fae-029b-40fd-bd3a-0df35b601791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160413832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1160413832
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.97629529
Short name T291
Test name
Test status
Simulation time 151278125316 ps
CPU time 653.54 seconds
Started Apr 02 12:32:27 PM PDT 24
Finished Apr 02 12:43:21 PM PDT 24
Peak memory 190744 kb
Host smart-d2eea255-2fd8-4633-9d47-305b5c01f96b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97629529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.97629529
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2393636096
Short name T288
Test name
Test status
Simulation time 1397125631491 ps
CPU time 611.35 seconds
Started Apr 02 12:32:42 PM PDT 24
Finished Apr 02 12:42:53 PM PDT 24
Peak memory 190780 kb
Host smart-65b5a8ef-c45f-4f8a-a007-8b765768486b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393636096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2393636096
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3114751610
Short name T306
Test name
Test status
Simulation time 119667247065 ps
CPU time 53.08 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:33:18 PM PDT 24
Peak memory 182596 kb
Host smart-f4540548-f7d1-4584-b8a4-fbc489263925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114751610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3114751610
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.649700550
Short name T372
Test name
Test status
Simulation time 83866690918 ps
CPU time 142.99 seconds
Started Apr 02 12:32:11 PM PDT 24
Finished Apr 02 12:34:34 PM PDT 24
Peak memory 182580 kb
Host smart-f9af6fdc-bc82-48c7-9598-4b4847716406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649700550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.649700550
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2538703516
Short name T4
Test name
Test status
Simulation time 13660937831 ps
CPU time 461.44 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 182572 kb
Host smart-9f97b07a-2851-4fb7-baf9-e965680e6360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538703516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2538703516
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.276670853
Short name T7
Test name
Test status
Simulation time 256359438411 ps
CPU time 294.71 seconds
Started Apr 02 12:32:11 PM PDT 24
Finished Apr 02 12:37:06 PM PDT 24
Peak memory 194956 kb
Host smart-53d1d8c7-6754-40b2-b619-543982f16454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276670853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
276670853
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.3537570939
Short name T290
Test name
Test status
Simulation time 17902146767 ps
CPU time 13.13 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:32:34 PM PDT 24
Peak memory 182592 kb
Host smart-fa67d1ee-4d19-4361-a47c-4e75fae48432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537570939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3537570939
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.852850363
Short name T101
Test name
Test status
Simulation time 182194772392 ps
CPU time 679.6 seconds
Started Apr 02 12:32:34 PM PDT 24
Finished Apr 02 12:43:54 PM PDT 24
Peak memory 194340 kb
Host smart-9c4b4209-e909-46ad-9bf5-ed0199ba2aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852850363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.852850363
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1148583781
Short name T163
Test name
Test status
Simulation time 38149551762 ps
CPU time 72.29 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:33:33 PM PDT 24
Peak memory 190784 kb
Host smart-acf6eb1f-03d0-4ce6-8fd6-0667d758567b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148583781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1148583781
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.383523943
Short name T120
Test name
Test status
Simulation time 135169574056 ps
CPU time 470.77 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:40:11 PM PDT 24
Peak memory 190836 kb
Host smart-c57826e7-2b8c-43ea-a6c1-77dd171ecb05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383523943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.383523943
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3614239473
Short name T343
Test name
Test status
Simulation time 9542056792 ps
CPU time 12.42 seconds
Started Apr 02 12:32:26 PM PDT 24
Finished Apr 02 12:32:39 PM PDT 24
Peak memory 182580 kb
Host smart-48d811b3-ecf0-4bab-ab0d-c5e288524054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614239473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3614239473
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.829310255
Short name T264
Test name
Test status
Simulation time 110948933674 ps
CPU time 171.87 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:35:14 PM PDT 24
Peak memory 190744 kb
Host smart-a3970063-6922-4567-87ca-680304c760b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829310255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.829310255
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4065029963
Short name T284
Test name
Test status
Simulation time 181640281503 ps
CPU time 156.11 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:34:54 PM PDT 24
Peak memory 190696 kb
Host smart-5a922331-184e-484e-a705-7e8eb2bb34e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065029963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4065029963
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3044066179
Short name T447
Test name
Test status
Simulation time 393611379240 ps
CPU time 390.02 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:38:45 PM PDT 24
Peak memory 182576 kb
Host smart-20a0f91b-e8be-4ee1-8d00-d480a6bc781f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044066179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3044066179
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1825251671
Short name T431
Test name
Test status
Simulation time 99838339699 ps
CPU time 141.4 seconds
Started Apr 02 12:32:12 PM PDT 24
Finished Apr 02 12:34:33 PM PDT 24
Peak memory 182616 kb
Host smart-074fc804-f71a-41b1-9c30-4d205700a9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825251671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1825251671
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2100205282
Short name T351
Test name
Test status
Simulation time 3089095839 ps
CPU time 2.86 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:32:16 PM PDT 24
Peak memory 182456 kb
Host smart-54b0eb00-9555-4b0b-ba0f-cb42953a4f28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100205282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2100205282
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1210148972
Short name T441
Test name
Test status
Simulation time 67212528401 ps
CPU time 51.55 seconds
Started Apr 02 12:32:12 PM PDT 24
Finished Apr 02 12:33:03 PM PDT 24
Peak memory 182596 kb
Host smart-552ac9f6-43fb-4541-b907-a46ed209e0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210148972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1210148972
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.3255277023
Short name T348
Test name
Test status
Simulation time 129618354950 ps
CPU time 70.09 seconds
Started Apr 02 12:32:40 PM PDT 24
Finished Apr 02 12:33:50 PM PDT 24
Peak memory 182588 kb
Host smart-1b910bbd-06ca-4c85-a936-832fb00bef28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255277023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3255277023
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.503973859
Short name T227
Test name
Test status
Simulation time 30250178785 ps
CPU time 55.79 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:33:14 PM PDT 24
Peak memory 190752 kb
Host smart-cd0b93ec-0355-4d98-abbf-369ecb2240b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503973859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.503973859
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3126703035
Short name T260
Test name
Test status
Simulation time 198405578711 ps
CPU time 134.91 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:34:39 PM PDT 24
Peak memory 190760 kb
Host smart-3b8d6f10-e0c5-44d9-b1d1-545387ebd927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126703035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3126703035
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.924991204
Short name T10
Test name
Test status
Simulation time 42104775580 ps
CPU time 68.18 seconds
Started Apr 02 12:32:39 PM PDT 24
Finished Apr 02 12:33:47 PM PDT 24
Peak memory 182592 kb
Host smart-e2b9d09a-a5fe-44e1-b4cf-5d69d54de6b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924991204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.924991204
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2122594444
Short name T9
Test name
Test status
Simulation time 1381984362571 ps
CPU time 800.18 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 12:45:49 PM PDT 24
Peak memory 190760 kb
Host smart-6fc6835f-fcd7-4a64-93a3-d935a71535e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122594444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2122594444
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1712999980
Short name T155
Test name
Test status
Simulation time 693505364101 ps
CPU time 385.99 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:38:43 PM PDT 24
Peak memory 182628 kb
Host smart-47198b1e-2542-4f12-a717-4fddc7d6ee49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712999980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1712999980
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1420136200
Short name T438
Test name
Test status
Simulation time 214688360520 ps
CPU time 270.72 seconds
Started Apr 02 12:32:01 PM PDT 24
Finished Apr 02 12:36:32 PM PDT 24
Peak memory 182576 kb
Host smart-df49ecaa-91c9-4fd7-a91f-a1114470386d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420136200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1420136200
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2046097117
Short name T434
Test name
Test status
Simulation time 1260435448787 ps
CPU time 550.45 seconds
Started Apr 02 12:32:02 PM PDT 24
Finished Apr 02 12:41:12 PM PDT 24
Peak memory 190688 kb
Host smart-27ef6b73-3dff-4d1a-afef-52cedefdb78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046097117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2046097117
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/152.rv_timer_random.600213944
Short name T304
Test name
Test status
Simulation time 57620359925 ps
CPU time 64.41 seconds
Started Apr 02 12:32:32 PM PDT 24
Finished Apr 02 12:33:37 PM PDT 24
Peak memory 182492 kb
Host smart-390f0759-0533-46d1-83c9-d90a71d1bd52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600213944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.600213944
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2541732365
Short name T129
Test name
Test status
Simulation time 604194024131 ps
CPU time 863.08 seconds
Started Apr 02 12:32:30 PM PDT 24
Finished Apr 02 12:46:53 PM PDT 24
Peak memory 190736 kb
Host smart-a7f6c128-3caa-4fba-a178-cd56bd30064e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541732365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2541732365
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2424834721
Short name T251
Test name
Test status
Simulation time 98972400442 ps
CPU time 898.21 seconds
Started Apr 02 12:32:35 PM PDT 24
Finished Apr 02 12:47:33 PM PDT 24
Peak memory 190760 kb
Host smart-2a762608-e919-4c7f-acb3-ad178a57c5fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424834721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2424834721
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1946355072
Short name T296
Test name
Test status
Simulation time 85820252043 ps
CPU time 280.38 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:37:06 PM PDT 24
Peak memory 190776 kb
Host smart-1c04c6be-5081-4095-b940-ca4af2d8dc49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946355072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1946355072
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3229616984
Short name T444
Test name
Test status
Simulation time 17797682259 ps
CPU time 61.41 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:33:26 PM PDT 24
Peak memory 182572 kb
Host smart-9206b345-0362-442e-a0e0-2d8dfca998b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229616984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3229616984
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.657098888
Short name T267
Test name
Test status
Simulation time 608922355375 ps
CPU time 477.55 seconds
Started Apr 02 12:32:35 PM PDT 24
Finished Apr 02 12:40:33 PM PDT 24
Peak memory 190852 kb
Host smart-80ce066c-2657-4b10-afa8-7050814503e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657098888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.657098888
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.857457528
Short name T116
Test name
Test status
Simulation time 204386273353 ps
CPU time 99.14 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:34:02 PM PDT 24
Peak memory 190736 kb
Host smart-bfac3278-6f00-4268-97d5-028785110dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857457528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.857457528
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1958605151
Short name T308
Test name
Test status
Simulation time 885335154851 ps
CPU time 860.88 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:46:34 PM PDT 24
Peak memory 182616 kb
Host smart-9dab4a52-8f77-4b8c-a759-ba6b9a6f016f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958605151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1958605151
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2509565560
Short name T358
Test name
Test status
Simulation time 182489911016 ps
CPU time 223.83 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:36:02 PM PDT 24
Peak memory 182620 kb
Host smart-465efc0a-08df-44f7-bd34-c49023c4721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509565560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2509565560
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3430899511
Short name T385
Test name
Test status
Simulation time 134665060994 ps
CPU time 73.55 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:33:27 PM PDT 24
Peak memory 194232 kb
Host smart-ba6cf16c-4b3d-480d-8916-dbbdd96d6ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430899511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3430899511
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3629245937
Short name T297
Test name
Test status
Simulation time 177693028643 ps
CPU time 185.95 seconds
Started Apr 02 12:32:34 PM PDT 24
Finished Apr 02 12:35:40 PM PDT 24
Peak memory 190760 kb
Host smart-546ad9de-9b14-454e-adb3-88d764bfd5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629245937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3629245937
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3701251856
Short name T282
Test name
Test status
Simulation time 190283389903 ps
CPU time 105.7 seconds
Started Apr 02 12:32:37 PM PDT 24
Finished Apr 02 12:34:23 PM PDT 24
Peak memory 182484 kb
Host smart-dcd59d59-e9cb-475f-93f3-304170606ba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701251856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3701251856
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3649058918
Short name T141
Test name
Test status
Simulation time 72742625688 ps
CPU time 121.31 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:34:26 PM PDT 24
Peak memory 190768 kb
Host smart-41be5772-d6a2-42c2-85cf-3a1725676e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649058918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3649058918
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2726067420
Short name T389
Test name
Test status
Simulation time 83759696695 ps
CPU time 76.27 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:33:40 PM PDT 24
Peak memory 182576 kb
Host smart-ab32bf61-8b21-47c0-8e17-16f860b6e96b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726067420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2726067420
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3142721757
Short name T144
Test name
Test status
Simulation time 97923097972 ps
CPU time 33.1 seconds
Started Apr 02 12:32:48 PM PDT 24
Finished Apr 02 12:33:21 PM PDT 24
Peak memory 182368 kb
Host smart-21238d79-2b7c-44b7-9ed4-4251fe5e4667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142721757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3142721757
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3768034742
Short name T275
Test name
Test status
Simulation time 856043479493 ps
CPU time 775.23 seconds
Started Apr 02 12:32:26 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 190824 kb
Host smart-54bc4f7c-483a-466b-8381-4e71115b405f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768034742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3768034742
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.825965047
Short name T123
Test name
Test status
Simulation time 342202028932 ps
CPU time 446.6 seconds
Started Apr 02 12:32:51 PM PDT 24
Finished Apr 02 12:40:18 PM PDT 24
Peak memory 190756 kb
Host smart-c20ffa3b-1ae6-4772-b1e0-60a5789f093b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825965047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.825965047
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3811733811
Short name T386
Test name
Test status
Simulation time 172486484253 ps
CPU time 240.6 seconds
Started Apr 02 12:32:14 PM PDT 24
Finished Apr 02 12:36:14 PM PDT 24
Peak memory 182568 kb
Host smart-8b7ec3cb-4ab5-494b-bb82-fc4586ef20a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811733811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3811733811
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1841534114
Short name T387
Test name
Test status
Simulation time 5627946472 ps
CPU time 10.05 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:32:31 PM PDT 24
Peak memory 182584 kb
Host smart-de1767a1-e573-4d05-9c16-7719e0f1f38e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841534114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1841534114
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3666853227
Short name T365
Test name
Test status
Simulation time 11637113 ps
CPU time 0.53 seconds
Started Apr 02 12:32:07 PM PDT 24
Finished Apr 02 12:32:08 PM PDT 24
Peak memory 182416 kb
Host smart-5f8ef3a3-d968-4cd9-91ca-d285ec158464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666853227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3666853227
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.1576449426
Short name T73
Test name
Test status
Simulation time 4302652156 ps
CPU time 151.42 seconds
Started Apr 02 12:32:36 PM PDT 24
Finished Apr 02 12:35:08 PM PDT 24
Peak memory 182592 kb
Host smart-dbfa5ce8-86d4-4f0d-a2d2-3cf4c1f65cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576449426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1576449426
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3347568024
Short name T150
Test name
Test status
Simulation time 615687021018 ps
CPU time 1067.72 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:50:12 PM PDT 24
Peak memory 190724 kb
Host smart-ff839494-cca1-443a-a0c2-e8ea7edca62c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347568024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3347568024
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.310308922
Short name T333
Test name
Test status
Simulation time 85166931353 ps
CPU time 233.3 seconds
Started Apr 02 12:32:40 PM PDT 24
Finished Apr 02 12:36:34 PM PDT 24
Peak memory 190688 kb
Host smart-2043e5c3-aa8a-41c1-9a88-a231e8ab2bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310308922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.310308922
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.251383210
Short name T178
Test name
Test status
Simulation time 59921577834 ps
CPU time 108.35 seconds
Started Apr 02 12:32:26 PM PDT 24
Finished Apr 02 12:34:19 PM PDT 24
Peak memory 190816 kb
Host smart-8ef9425a-05a4-483a-b80e-2d6f35065a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251383210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.251383210
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1852359802
Short name T137
Test name
Test status
Simulation time 87139628635 ps
CPU time 519.73 seconds
Started Apr 02 12:32:36 PM PDT 24
Finished Apr 02 12:41:16 PM PDT 24
Peak memory 193404 kb
Host smart-ed93dd42-2f18-4d8e-a799-ec188c5166e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852359802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1852359802
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.707804245
Short name T331
Test name
Test status
Simulation time 163435327103 ps
CPU time 154.01 seconds
Started Apr 02 12:32:51 PM PDT 24
Finished Apr 02 12:35:26 PM PDT 24
Peak memory 190736 kb
Host smart-9a79a724-3c28-4c3b-8eb8-33792580600b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707804245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.707804245
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1414395645
Short name T57
Test name
Test status
Simulation time 3015257583 ps
CPU time 5.2 seconds
Started Apr 02 12:32:33 PM PDT 24
Finished Apr 02 12:32:39 PM PDT 24
Peak memory 182484 kb
Host smart-c6cd81c2-1b02-4cad-ab5e-cc1049c7c0f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414395645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1414395645
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.4064396561
Short name T347
Test name
Test status
Simulation time 137169546260 ps
CPU time 65.24 seconds
Started Apr 02 12:32:42 PM PDT 24
Finished Apr 02 12:33:48 PM PDT 24
Peak memory 190784 kb
Host smart-aa1bd544-fedb-4298-b667-553d28cf9c1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064396561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4064396561
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1489954952
Short name T170
Test name
Test status
Simulation time 539376605271 ps
CPU time 1765.3 seconds
Started Apr 02 12:32:45 PM PDT 24
Finished Apr 02 01:02:10 PM PDT 24
Peak memory 190804 kb
Host smart-951a880a-ad85-44c8-80cd-ae886ca21407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489954952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1489954952
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1548201031
Short name T75
Test name
Test status
Simulation time 549153660767 ps
CPU time 304.82 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:37:13 PM PDT 24
Peak memory 182628 kb
Host smart-6ea31e62-d6d8-48c5-a098-dbc2a9348b07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548201031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1548201031
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.373348434
Short name T357
Test name
Test status
Simulation time 69960225470 ps
CPU time 24.87 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:32:38 PM PDT 24
Peak memory 182632 kb
Host smart-dd57509f-f928-42cf-b0f5-fcf0e24960cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373348434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.373348434
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3535287183
Short name T265
Test name
Test status
Simulation time 35909627826 ps
CPU time 63.23 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:33:25 PM PDT 24
Peak memory 182616 kb
Host smart-0058c9ee-245a-4e3d-950b-add775a4b583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535287183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3535287183
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3103328194
Short name T406
Test name
Test status
Simulation time 351380036 ps
CPU time 0.7 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:32:10 PM PDT 24
Peak memory 182356 kb
Host smart-4fff9d78-147b-4987-afa7-73642aa732fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103328194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3103328194
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/184.rv_timer_random.1555130981
Short name T232
Test name
Test status
Simulation time 520194344323 ps
CPU time 1960.09 seconds
Started Apr 02 12:32:37 PM PDT 24
Finished Apr 02 01:05:18 PM PDT 24
Peak memory 190760 kb
Host smart-343f6a4c-ac10-4251-abf5-1cae65cdfbca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555130981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1555130981
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3362111423
Short name T200
Test name
Test status
Simulation time 267343427424 ps
CPU time 138.04 seconds
Started Apr 02 12:32:41 PM PDT 24
Finished Apr 02 12:34:59 PM PDT 24
Peak memory 190784 kb
Host smart-8bba4e86-6092-4697-9724-448dabad8ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362111423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3362111423
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2083968265
Short name T261
Test name
Test status
Simulation time 191628606942 ps
CPU time 458.74 seconds
Started Apr 02 12:32:35 PM PDT 24
Finished Apr 02 12:40:15 PM PDT 24
Peak memory 190792 kb
Host smart-b863d3b8-a129-48c8-ad88-76b2ab1db18e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083968265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2083968265
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.4187483805
Short name T421
Test name
Test status
Simulation time 165494707825 ps
CPU time 66.78 seconds
Started Apr 02 12:32:07 PM PDT 24
Finished Apr 02 12:33:14 PM PDT 24
Peak memory 182596 kb
Host smart-441f9a13-474c-4431-b02e-41126d705be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187483805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4187483805
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.668635447
Short name T299
Test name
Test status
Simulation time 121871592737 ps
CPU time 181.34 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:35:16 PM PDT 24
Peak memory 190816 kb
Host smart-94929ba0-3a47-410f-8074-e2de29fe65f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668635447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.668635447
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.257386926
Short name T361
Test name
Test status
Simulation time 671616202 ps
CPU time 1.48 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:32:20 PM PDT 24
Peak memory 182404 kb
Host smart-3575e9fb-7ddc-4e0e-92d5-59fedbe24c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257386926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.257386926
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3184401484
Short name T128
Test name
Test status
Simulation time 519421778321 ps
CPU time 2376.02 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 01:12:00 PM PDT 24
Peak memory 190756 kb
Host smart-d21f718a-787d-4f35-a7ad-333cc48cb96c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184401484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3184401484
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1004372371
Short name T38
Test name
Test status
Simulation time 69114603922 ps
CPU time 526.78 seconds
Started Apr 02 12:32:14 PM PDT 24
Finished Apr 02 12:41:01 PM PDT 24
Peak memory 206460 kb
Host smart-c05e85a9-3976-4136-a416-be897bcd9782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004372371 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1004372371
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.3234541280
Short name T322
Test name
Test status
Simulation time 119083818798 ps
CPU time 177.13 seconds
Started Apr 02 12:32:33 PM PDT 24
Finished Apr 02 12:35:30 PM PDT 24
Peak memory 190780 kb
Host smart-2e2d8855-ae13-4fb6-9a80-c4e0fde9c913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234541280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3234541280
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.278871790
Short name T48
Test name
Test status
Simulation time 537513934520 ps
CPU time 862.05 seconds
Started Apr 02 12:32:46 PM PDT 24
Finished Apr 02 12:47:08 PM PDT 24
Peak memory 190676 kb
Host smart-68b92846-33f4-4b1c-a167-bca88afdce15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278871790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.278871790
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.532242788
Short name T310
Test name
Test status
Simulation time 84078292112 ps
CPU time 428.42 seconds
Started Apr 02 12:32:39 PM PDT 24
Finished Apr 02 12:39:48 PM PDT 24
Peak memory 190792 kb
Host smart-4a6e9416-20d7-46a4-9d6c-71e3e3060b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532242788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.532242788
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1155058018
Short name T249
Test name
Test status
Simulation time 126351348730 ps
CPU time 855.4 seconds
Started Apr 02 12:32:49 PM PDT 24
Finished Apr 02 12:47:04 PM PDT 24
Peak memory 190844 kb
Host smart-2b0c61cd-6a32-4140-832c-9c5cde5b0233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155058018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1155058018
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2388308778
Short name T325
Test name
Test status
Simulation time 82036624394 ps
CPU time 166.48 seconds
Started Apr 02 12:32:50 PM PDT 24
Finished Apr 02 12:35:37 PM PDT 24
Peak memory 182580 kb
Host smart-79640ddd-0bca-494c-9b03-2e2aeb0793da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388308778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2388308778
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4009980477
Short name T126
Test name
Test status
Simulation time 293573706325 ps
CPU time 45.48 seconds
Started Apr 02 12:32:55 PM PDT 24
Finished Apr 02 12:33:41 PM PDT 24
Peak memory 182584 kb
Host smart-15d835c7-6852-449f-b540-b66df3ef4dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009980477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4009980477
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3035205176
Short name T340
Test name
Test status
Simulation time 35519161584 ps
CPU time 55.69 seconds
Started Apr 02 12:32:44 PM PDT 24
Finished Apr 02 12:33:40 PM PDT 24
Peak memory 190780 kb
Host smart-c4e8b39d-b04f-4882-b55b-77d81467292d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035205176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3035205176
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2367422441
Short name T160
Test name
Test status
Simulation time 105243351285 ps
CPU time 202.91 seconds
Started Apr 02 12:32:37 PM PDT 24
Finished Apr 02 12:36:01 PM PDT 24
Peak memory 182604 kb
Host smart-f85a9c55-1b62-4a09-90e1-ce495fee0c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367422441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2367422441
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2556722656
Short name T283
Test name
Test status
Simulation time 534046094553 ps
CPU time 477.25 seconds
Started Apr 02 12:31:47 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 182528 kb
Host smart-a7c83fa1-15d9-44b6-8117-ade55f7cd76b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556722656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2556722656
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3231582434
Short name T396
Test name
Test status
Simulation time 254596344286 ps
CPU time 165.86 seconds
Started Apr 02 12:31:51 PM PDT 24
Finished Apr 02 12:34:37 PM PDT 24
Peak memory 182536 kb
Host smart-37f09c91-0f69-499a-af07-37c8051036ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231582434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3231582434
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1926477611
Short name T245
Test name
Test status
Simulation time 311606616520 ps
CPU time 922.05 seconds
Started Apr 02 12:31:57 PM PDT 24
Finished Apr 02 12:47:19 PM PDT 24
Peak memory 190788 kb
Host smart-9a21a4ef-5f01-4218-93cd-edf2c95e85c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926477611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1926477611
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2553535530
Short name T381
Test name
Test status
Simulation time 132523556 ps
CPU time 0.59 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:32:01 PM PDT 24
Peak memory 182296 kb
Host smart-48a57e20-5636-43b2-9138-b6292c18e9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553535530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2553535530
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1097342515
Short name T17
Test name
Test status
Simulation time 681784649 ps
CPU time 0.84 seconds
Started Apr 02 12:32:12 PM PDT 24
Finished Apr 02 12:32:13 PM PDT 24
Peak memory 213176 kb
Host smart-4c455725-bb67-4275-bcf2-670ffb4c9eb1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097342515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1097342515
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3231519376
Short name T397
Test name
Test status
Simulation time 25983348783 ps
CPU time 20.15 seconds
Started Apr 02 12:32:14 PM PDT 24
Finished Apr 02 12:32:35 PM PDT 24
Peak memory 182612 kb
Host smart-0ddc9834-61fd-485d-98a6-ce84ab10b88f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231519376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3231519376
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.368072042
Short name T356
Test name
Test status
Simulation time 851379434216 ps
CPU time 230.31 seconds
Started Apr 02 12:32:10 PM PDT 24
Finished Apr 02 12:36:01 PM PDT 24
Peak memory 182320 kb
Host smart-1c835c8f-f68a-478d-8847-1c06431a08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368072042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.368072042
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.977206142
Short name T407
Test name
Test status
Simulation time 92856842772 ps
CPU time 53.1 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:33:08 PM PDT 24
Peak memory 182644 kb
Host smart-fbd571ba-83ae-4133-b88c-170a72a08757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977206142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.977206142
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1759592307
Short name T317
Test name
Test status
Simulation time 1101359535763 ps
CPU time 779.89 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 190848 kb
Host smart-03e68b63-4c18-46d6-b217-66f188f2dc7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759592307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1759592307
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.90389691
Short name T118
Test name
Test status
Simulation time 434590149488 ps
CPU time 248.21 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:36:32 PM PDT 24
Peak memory 182532 kb
Host smart-9d3dd7f1-c934-4c64-8b6b-015c425fa11e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90389691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.rv_timer_cfg_update_on_fly.90389691
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3997378587
Short name T384
Test name
Test status
Simulation time 43278474592 ps
CPU time 64.54 seconds
Started Apr 02 12:32:11 PM PDT 24
Finished Apr 02 12:33:16 PM PDT 24
Peak memory 182624 kb
Host smart-0b5e634f-f6d8-4f08-bcf1-3c7b7f9ba86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997378587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3997378587
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3463325152
Short name T23
Test name
Test status
Simulation time 35667025386 ps
CPU time 100.87 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:33:58 PM PDT 24
Peak memory 190776 kb
Host smart-53f3fbde-e02e-4123-be41-1672d9fe623c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463325152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3463325152
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3060180474
Short name T320
Test name
Test status
Simulation time 66568797284 ps
CPU time 36.1 seconds
Started Apr 02 12:32:05 PM PDT 24
Finished Apr 02 12:32:41 PM PDT 24
Peak memory 182620 kb
Host smart-aaca8efd-9b3a-4a3d-9af8-cb2da082e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060180474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3060180474
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1254371536
Short name T70
Test name
Test status
Simulation time 134566698015 ps
CPU time 203.85 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 12:35:40 PM PDT 24
Peak memory 194592 kb
Host smart-04679d77-6c88-41b3-a7d1-7b6367418e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254371536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1254371536
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3601247735
Short name T190
Test name
Test status
Simulation time 931682138819 ps
CPU time 363.87 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:38:26 PM PDT 24
Peak memory 182600 kb
Host smart-eee4b619-37f2-41d8-99f5-8a6dfa570e7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601247735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3601247735
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2267753895
Short name T366
Test name
Test status
Simulation time 100307671957 ps
CPU time 155.88 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 12:34:52 PM PDT 24
Peak memory 182952 kb
Host smart-d20c2ae4-91d8-49ce-b310-6bd33c9c8d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267753895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2267753895
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1008477089
Short name T316
Test name
Test status
Simulation time 327755252999 ps
CPU time 284.89 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 190776 kb
Host smart-347cae9a-b88e-4568-b768-994b65eca98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008477089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1008477089
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3927692845
Short name T39
Test name
Test status
Simulation time 46444642100 ps
CPU time 200 seconds
Started Apr 02 12:32:09 PM PDT 24
Finished Apr 02 12:35:29 PM PDT 24
Peak memory 205440 kb
Host smart-ce9647bd-b48a-4998-8419-7f6eb33f580f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927692845 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3927692845
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1225091461
Short name T305
Test name
Test status
Simulation time 1161608148036 ps
CPU time 630.84 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:42:49 PM PDT 24
Peak memory 182632 kb
Host smart-8f4c2be3-6086-41df-a1dc-91f47360304c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225091461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1225091461
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.4172545692
Short name T370
Test name
Test status
Simulation time 235662367961 ps
CPU time 153.52 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:34:53 PM PDT 24
Peak memory 182612 kb
Host smart-dbc07449-65cd-45f2-a868-a99544506cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172545692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4172545692
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1793728506
Short name T309
Test name
Test status
Simulation time 288688269334 ps
CPU time 688.55 seconds
Started Apr 02 12:32:10 PM PDT 24
Finished Apr 02 12:43:39 PM PDT 24
Peak memory 190776 kb
Host smart-4e2c7d6c-de6b-49b9-8368-6da37815b69d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793728506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1793728506
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1283064379
Short name T354
Test name
Test status
Simulation time 695047671 ps
CPU time 1.38 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:32:22 PM PDT 24
Peak memory 182436 kb
Host smart-4d5b8014-2de3-4890-a41c-661c8c336e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283064379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1283064379
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2998108300
Short name T148
Test name
Test status
Simulation time 2838973352 ps
CPU time 4.92 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:32:25 PM PDT 24
Peak memory 182524 kb
Host smart-63caae74-af39-49f3-8ac8-f39fbf67348c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998108300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2998108300
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3444890557
Short name T404
Test name
Test status
Simulation time 281559447068 ps
CPU time 223.65 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 12:35:59 PM PDT 24
Peak memory 182612 kb
Host smart-f34de149-0d4c-49c1-b217-3c2b5b3dbe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444890557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3444890557
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2368391805
Short name T161
Test name
Test status
Simulation time 259141418586 ps
CPU time 404.49 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:39:07 PM PDT 24
Peak memory 190752 kb
Host smart-a7657ad8-0c96-4119-931f-56adb3ff536a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368391805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2368391805
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1244792890
Short name T263
Test name
Test status
Simulation time 343599047135 ps
CPU time 87.05 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:33:48 PM PDT 24
Peak memory 194196 kb
Host smart-085a46a2-8716-49d3-82c9-154c04a68ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244792890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1244792890
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2096840500
Short name T400
Test name
Test status
Simulation time 969832671 ps
CPU time 1.25 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:32:22 PM PDT 24
Peak memory 182320 kb
Host smart-825a6ab2-27d1-4fe9-b78f-8e642b5f15e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096840500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2096840500
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.25052582
Short name T364
Test name
Test status
Simulation time 290223660823 ps
CPU time 224.83 seconds
Started Apr 02 12:32:09 PM PDT 24
Finished Apr 02 12:35:54 PM PDT 24
Peak memory 182588 kb
Host smart-b794af7b-eade-4791-9aa4-ac599ca5d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25052582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.25052582
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2750759179
Short name T61
Test name
Test status
Simulation time 155045798674 ps
CPU time 155.25 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:35:03 PM PDT 24
Peak memory 190780 kb
Host smart-24c4ee8c-17d5-46f0-8b04-4a14d6290082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750759179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2750759179
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.20486236
Short name T50
Test name
Test status
Simulation time 130672203961 ps
CPU time 220.64 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:36:00 PM PDT 24
Peak memory 205404 kb
Host smart-48658417-cfce-4be3-b1fc-f14ba3072442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486236 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.20486236
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3215576533
Short name T3
Test name
Test status
Simulation time 887266539929 ps
CPU time 485.75 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:40:30 PM PDT 24
Peak memory 182568 kb
Host smart-9ac26f9b-b82d-4019-aafa-4ebba8089b9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215576533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3215576533
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2345707525
Short name T355
Test name
Test status
Simulation time 235367525931 ps
CPU time 293.52 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 182632 kb
Host smart-afa26a19-faff-47d7-9338-1e3e685e90d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345707525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2345707525
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3630321331
Short name T250
Test name
Test status
Simulation time 81713265918 ps
CPU time 140.07 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:34:41 PM PDT 24
Peak memory 190708 kb
Host smart-3023c556-0208-4354-9700-08d7dc1c5525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630321331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3630321331
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.12021725
Short name T36
Test name
Test status
Simulation time 50570074695 ps
CPU time 526.52 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:41:10 PM PDT 24
Peak memory 197252 kb
Host smart-8df53413-bff6-480b-998e-7a87c59d2fd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12021725 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.12021725
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2862433492
Short name T307
Test name
Test status
Simulation time 60036860698 ps
CPU time 92.97 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:33:55 PM PDT 24
Peak memory 182604 kb
Host smart-1f41990d-d0ef-4dfb-9bf9-d15d49f5a0f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862433492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2862433492
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1689496349
Short name T413
Test name
Test status
Simulation time 198850962118 ps
CPU time 142.01 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:34:42 PM PDT 24
Peak memory 182536 kb
Host smart-08218681-a969-46fa-a66b-5ef63bf235e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689496349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1689496349
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1876660747
Short name T437
Test name
Test status
Simulation time 56317440116 ps
CPU time 90.55 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:33:50 PM PDT 24
Peak memory 190744 kb
Host smart-ddc363e7-a3a7-4f95-bda8-8b58b69572a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876660747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1876660747
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.513971746
Short name T42
Test name
Test status
Simulation time 11337241946 ps
CPU time 48.33 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:33:07 PM PDT 24
Peak memory 182548 kb
Host smart-213894f1-46c5-4804-a6cd-e9dbf88501f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513971746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.513971746
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2799071273
Short name T445
Test name
Test status
Simulation time 1192741541420 ps
CPU time 1156.78 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:51:38 PM PDT 24
Peak memory 182568 kb
Host smart-e30da72c-18ae-48ff-b047-0a533d1b060b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799071273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2799071273
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2719843285
Short name T368
Test name
Test status
Simulation time 120670107144 ps
CPU time 183.11 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:35:33 PM PDT 24
Peak memory 182540 kb
Host smart-f11429a8-af43-40c4-a74b-9a936196fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719843285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2719843285
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.4007761680
Short name T312
Test name
Test status
Simulation time 1164192936442 ps
CPU time 505.4 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:40:47 PM PDT 24
Peak memory 190716 kb
Host smart-f12e6456-cac1-48a4-aaa6-19acc0b79d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007761680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4007761680
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3439641633
Short name T313
Test name
Test status
Simulation time 485940174199 ps
CPU time 102.57 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:33:58 PM PDT 24
Peak memory 190752 kb
Host smart-88f7e095-c331-4c5f-94f1-81c08951e4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439641633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3439641633
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3546149479
Short name T432
Test name
Test status
Simulation time 500036499710 ps
CPU time 393.96 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:38:52 PM PDT 24
Peak memory 190748 kb
Host smart-6ec70c56-6c97-437e-b47a-c3f005689841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546149479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3546149479
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2887415512
Short name T439
Test name
Test status
Simulation time 227425854878 ps
CPU time 109.85 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:34:09 PM PDT 24
Peak memory 182632 kb
Host smart-65c2bb38-51be-4875-b05c-d5a655ac8020
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887415512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2887415512
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2544289690
Short name T47
Test name
Test status
Simulation time 182892331019 ps
CPU time 74.7 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:33:33 PM PDT 24
Peak memory 182592 kb
Host smart-e15d99e3-ef9e-45c8-a684-0c210ab42f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544289690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2544289690
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3766950114
Short name T175
Test name
Test status
Simulation time 417772533692 ps
CPU time 206.54 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:35:47 PM PDT 24
Peak memory 190712 kb
Host smart-dad1b97b-ed7c-4699-b654-6b6741a68384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766950114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3766950114
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3091394654
Short name T429
Test name
Test status
Simulation time 490217212 ps
CPU time 1.35 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:32:23 PM PDT 24
Peak memory 182464 kb
Host smart-9d85d034-6d2c-4acc-8ee5-7d15177b3a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091394654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3091394654
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.743511338
Short name T40
Test name
Test status
Simulation time 3614633186590 ps
CPU time 1233.39 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:52:54 PM PDT 24
Peak memory 190776 kb
Host smart-9ba8e37b-5613-436b-bb3f-7eae31babc76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743511338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
743511338
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2270270672
Short name T327
Test name
Test status
Simulation time 149830757914 ps
CPU time 183.9 seconds
Started Apr 02 12:32:11 PM PDT 24
Finished Apr 02 12:35:16 PM PDT 24
Peak memory 182648 kb
Host smart-db296b7b-5cff-4062-b8a7-cf419cd1fe87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270270672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2270270672
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1879435983
Short name T436
Test name
Test status
Simulation time 66784745915 ps
CPU time 91.85 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:33:47 PM PDT 24
Peak memory 182596 kb
Host smart-7b08862a-d2a6-430a-b6ca-642db6da5c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879435983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1879435983
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.637054253
Short name T157
Test name
Test status
Simulation time 92057342734 ps
CPU time 545.78 seconds
Started Apr 02 12:32:09 PM PDT 24
Finished Apr 02 12:41:15 PM PDT 24
Peak memory 194308 kb
Host smart-5a09cde2-5f11-459e-864e-01df1b2b932f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637054253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.637054253
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1208681618
Short name T166
Test name
Test status
Simulation time 920287566205 ps
CPU time 399.38 seconds
Started Apr 02 12:32:11 PM PDT 24
Finished Apr 02 12:38:51 PM PDT 24
Peak memory 190840 kb
Host smart-dcf66319-ec70-4456-a5e0-9b8b6c9108c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208681618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1208681618
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3973044157
Short name T15
Test name
Test status
Simulation time 114561049 ps
CPU time 0.95 seconds
Started Apr 02 12:31:59 PM PDT 24
Finished Apr 02 12:32:00 PM PDT 24
Peak memory 213788 kb
Host smart-97ffb3b7-2b61-47fd-8a7c-26967ff16d3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973044157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3973044157
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1917156386
Short name T422
Test name
Test status
Simulation time 472071540750 ps
CPU time 386.17 seconds
Started Apr 02 12:32:06 PM PDT 24
Finished Apr 02 12:38:32 PM PDT 24
Peak memory 190712 kb
Host smart-f7b07358-36da-4cd0-b9ab-dfa8fc8d6113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917156386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1917156386
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3728022822
Short name T424
Test name
Test status
Simulation time 309493677690 ps
CPU time 315.41 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:37:36 PM PDT 24
Peak memory 182584 kb
Host smart-09c85822-4580-41ce-a4dd-c78ffbb5b23c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728022822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3728022822
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.158040001
Short name T377
Test name
Test status
Simulation time 143140257281 ps
CPU time 34.06 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:32:54 PM PDT 24
Peak memory 182488 kb
Host smart-52127541-c2d8-43bc-8a58-f8ef83821eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158040001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.158040001
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3269873667
Short name T345
Test name
Test status
Simulation time 349391565605 ps
CPU time 332.37 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:37:55 PM PDT 24
Peak memory 190792 kb
Host smart-f65add43-46f5-4b44-bc7d-30d9944a8be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269873667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3269873667
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3197539142
Short name T420
Test name
Test status
Simulation time 37405182179 ps
CPU time 24.46 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:32:44 PM PDT 24
Peak memory 190776 kb
Host smart-ecf47267-15c1-4e1b-80f4-b5c959c7c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197539142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3197539142
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2921777832
Short name T69
Test name
Test status
Simulation time 81673000650 ps
CPU time 109.95 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:34:12 PM PDT 24
Peak memory 190680 kb
Host smart-68ba4d96-a176-4b7e-898f-e2a850077b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921777832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2921777832
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1587217423
Short name T58
Test name
Test status
Simulation time 4123401352 ps
CPU time 7.94 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:32:25 PM PDT 24
Peak memory 182576 kb
Host smart-5d2326ce-fc31-405a-b0f0-adba80b1c5d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587217423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1587217423
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2920147429
Short name T378
Test name
Test status
Simulation time 428764595213 ps
CPU time 181.34 seconds
Started Apr 02 12:32:14 PM PDT 24
Finished Apr 02 12:35:16 PM PDT 24
Peak memory 182612 kb
Host smart-7d874e7b-8ade-4e9e-87fd-9d303bedd070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920147429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2920147429
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3045027593
Short name T336
Test name
Test status
Simulation time 162306858930 ps
CPU time 150.1 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:34:55 PM PDT 24
Peak memory 190664 kb
Host smart-11657ca1-733e-406c-8429-0c916c302b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045027593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3045027593
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3128196232
Short name T446
Test name
Test status
Simulation time 3617222654560 ps
CPU time 542.32 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:41:23 PM PDT 24
Peak memory 190800 kb
Host smart-279a854e-0191-42b3-b710-8ae2c309b0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128196232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3128196232
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3620909354
Short name T395
Test name
Test status
Simulation time 27596896390 ps
CPU time 14.54 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:32:34 PM PDT 24
Peak memory 182584 kb
Host smart-e828ee7b-bdb2-42f6-9fa8-721f38ef7e7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620909354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3620909354
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2228488288
Short name T369
Test name
Test status
Simulation time 167397421170 ps
CPU time 259.62 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:36:41 PM PDT 24
Peak memory 182604 kb
Host smart-8df0267e-fe5e-4f7a-aa22-b2f12ea084c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228488288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2228488288
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2993423103
Short name T324
Test name
Test status
Simulation time 126168949082 ps
CPU time 649.61 seconds
Started Apr 02 12:32:18 PM PDT 24
Finished Apr 02 12:43:07 PM PDT 24
Peak memory 190776 kb
Host smart-65098e41-ec24-46bd-a2e7-e99bd59c2fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993423103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2993423103
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2079948979
Short name T231
Test name
Test status
Simulation time 29185286832 ps
CPU time 40.65 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:33:05 PM PDT 24
Peak memory 182592 kb
Host smart-ef1e23b4-101b-4525-9843-a636d44732e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079948979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2079948979
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.3304838416
Short name T13
Test name
Test status
Simulation time 4563768899 ps
CPU time 19.03 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:32:44 PM PDT 24
Peak memory 197192 kb
Host smart-0bca744f-44cb-4ab5-b024-3cce28770c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304838416 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.3304838416
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3626617410
Short name T205
Test name
Test status
Simulation time 579621662217 ps
CPU time 945.4 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:48:09 PM PDT 24
Peak memory 182572 kb
Host smart-842cfed3-20e5-44ea-a0f1-b9ff753ca2d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626617410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3626617410
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2959924846
Short name T399
Test name
Test status
Simulation time 252087440636 ps
CPU time 208.06 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:35:50 PM PDT 24
Peak memory 182596 kb
Host smart-79cbe178-3906-4d91-a112-6d02fabc0efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959924846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2959924846
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.112962861
Short name T326
Test name
Test status
Simulation time 18672239121 ps
CPU time 117.89 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:34:18 PM PDT 24
Peak memory 190752 kb
Host smart-548a7ba8-f815-4fa4-860d-30f757326e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112962861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.112962861
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1164239624
Short name T374
Test name
Test status
Simulation time 518690508 ps
CPU time 0.89 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:32:21 PM PDT 24
Peak memory 191208 kb
Host smart-991ed52e-73de-4ab7-9bdf-4ca13b281a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164239624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1164239624
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3480405939
Short name T191
Test name
Test status
Simulation time 115465383505 ps
CPU time 249.87 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:36:32 PM PDT 24
Peak memory 194204 kb
Host smart-0e72dd98-1d15-4925-9e3e-f980ce67e296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480405939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3480405939
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3654840871
Short name T242
Test name
Test status
Simulation time 1512604881688 ps
CPU time 521.96 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:41:02 PM PDT 24
Peak memory 182628 kb
Host smart-9aef11db-fdea-45e7-8d9c-75f871a45e8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654840871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3654840871
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1701056668
Short name T383
Test name
Test status
Simulation time 479246765142 ps
CPU time 214.59 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:35:55 PM PDT 24
Peak memory 182548 kb
Host smart-a1dc963b-2fb9-4d15-b038-46b9ec81404a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701056668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1701056668
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1813098113
Short name T390
Test name
Test status
Simulation time 26673833905 ps
CPU time 129.67 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:34:27 PM PDT 24
Peak memory 190708 kb
Host smart-5de63132-4d89-4f81-a1d0-3c3f23c94368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813098113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1813098113
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3346282853
Short name T66
Test name
Test status
Simulation time 968728427590 ps
CPU time 437.86 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 195368 kb
Host smart-ad296010-ce8e-41e3-a1c5-57b9ecc23bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346282853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3346282853
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.633248501
Short name T311
Test name
Test status
Simulation time 1080846200108 ps
CPU time 674.44 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:43:36 PM PDT 24
Peak memory 182600 kb
Host smart-199a8f51-0e49-44f4-aa07-637ddeae9d2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633248501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.633248501
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.453548179
Short name T448
Test name
Test status
Simulation time 88905774058 ps
CPU time 118.71 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:34:19 PM PDT 24
Peak memory 182580 kb
Host smart-26a7040b-b5e1-4119-90c4-d7d698d0c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453548179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.453548179
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3198437974
Short name T376
Test name
Test status
Simulation time 385054371 ps
CPU time 1.03 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:32:23 PM PDT 24
Peak memory 182400 kb
Host smart-36e29ba3-946a-4a4f-a87f-3e73b0a89dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198437974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3198437974
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1374786344
Short name T375
Test name
Test status
Simulation time 199212161306 ps
CPU time 288.28 seconds
Started Apr 02 12:32:16 PM PDT 24
Finished Apr 02 12:37:05 PM PDT 24
Peak memory 190788 kb
Host smart-c78f884b-85f9-48ce-844d-e9c529518c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374786344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1374786344
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1755929587
Short name T142
Test name
Test status
Simulation time 39689045695 ps
CPU time 70.12 seconds
Started Apr 02 12:32:27 PM PDT 24
Finished Apr 02 12:33:37 PM PDT 24
Peak memory 182568 kb
Host smart-c4085a66-db38-4868-8578-40c35f07f66c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755929587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1755929587
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2004006384
Short name T363
Test name
Test status
Simulation time 105375156861 ps
CPU time 149.5 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:34:53 PM PDT 24
Peak memory 182576 kb
Host smart-f566da35-b59f-4a8e-b749-655aa030322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004006384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2004006384
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3041949852
Short name T22
Test name
Test status
Simulation time 147657923 ps
CPU time 0.77 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:32:21 PM PDT 24
Peak memory 182356 kb
Host smart-b8dc349c-b58e-4f3c-a07c-2f872781016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041949852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3041949852
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2847487638
Short name T405
Test name
Test status
Simulation time 541487337072 ps
CPU time 388.95 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:38:42 PM PDT 24
Peak memory 195596 kb
Host smart-b84a6c50-0b12-4ef5-bc5b-b6b550d06bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847487638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2847487638
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.963137363
Short name T35
Test name
Test status
Simulation time 600576738977 ps
CPU time 1126.79 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:51:08 PM PDT 24
Peak memory 213292 kb
Host smart-c38d32f0-8e81-45cd-9a08-c7d31c20335c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963137363 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.963137363
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.501145507
Short name T425
Test name
Test status
Simulation time 1265206521426 ps
CPU time 719.48 seconds
Started Apr 02 12:32:54 PM PDT 24
Finished Apr 02 12:44:54 PM PDT 24
Peak memory 182504 kb
Host smart-3d125f12-6185-45ef-85d3-4e7d61f0ffff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501145507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.501145507
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2950303820
Short name T388
Test name
Test status
Simulation time 147008571224 ps
CPU time 222.63 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:36:05 PM PDT 24
Peak memory 182584 kb
Host smart-c1a7a6bc-dfa6-4e58-b8a8-2445a63803e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950303820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2950303820
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3578418606
Short name T206
Test name
Test status
Simulation time 10571403418 ps
CPU time 119.16 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:34:21 PM PDT 24
Peak memory 182564 kb
Host smart-a452d099-f446-4435-a3cb-a4bacbddb0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578418606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3578418606
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.3306935290
Short name T51
Test name
Test status
Simulation time 66588932186 ps
CPU time 520.56 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:41:01 PM PDT 24
Peak memory 205440 kb
Host smart-37c1f9b3-3ca7-4f33-bd94-0ad571ceeaba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306935290 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.3306935290
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.472943845
Short name T247
Test name
Test status
Simulation time 225181688739 ps
CPU time 403.89 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:39:06 PM PDT 24
Peak memory 182600 kb
Host smart-897af5d7-df67-4834-8f1f-2f79d503ed23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472943845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.472943845
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.342010099
Short name T371
Test name
Test status
Simulation time 253000007290 ps
CPU time 119.02 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:34:22 PM PDT 24
Peak memory 182536 kb
Host smart-b3a14e47-c072-4493-822e-643d9df402c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342010099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.342010099
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2366487358
Short name T153
Test name
Test status
Simulation time 219890399908 ps
CPU time 426.06 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:39:27 PM PDT 24
Peak memory 190756 kb
Host smart-acaf1cf3-2c48-45e4-a0da-c2c4275db6dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366487358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2366487358
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2308386659
Short name T353
Test name
Test status
Simulation time 109778058 ps
CPU time 0.7 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:32:23 PM PDT 24
Peak memory 190784 kb
Host smart-6c484d15-ece5-4c7f-bd60-fdfb4883bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308386659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2308386659
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3411437906
Short name T159
Test name
Test status
Simulation time 2574266916623 ps
CPU time 2428.64 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 01:12:53 PM PDT 24
Peak memory 190788 kb
Host smart-fb15e926-43a4-427c-a3cc-27d93030823b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411437906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3411437906
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.255524193
Short name T228
Test name
Test status
Simulation time 312994828223 ps
CPU time 307.11 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:37:28 PM PDT 24
Peak memory 182588 kb
Host smart-c619dd66-b545-4d0c-ade0-25bc4e8187ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255524193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.255524193
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1602695069
Short name T409
Test name
Test status
Simulation time 153492866226 ps
CPU time 135.71 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:34:40 PM PDT 24
Peak memory 182588 kb
Host smart-f5bd9db5-812c-4e6a-a1f9-b06a12640672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602695069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1602695069
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.290447812
Short name T172
Test name
Test status
Simulation time 236343281628 ps
CPU time 118.07 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:34:32 PM PDT 24
Peak memory 190784 kb
Host smart-c04160ee-248c-4cfb-8cb2-1c1e2124b2e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290447812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.290447812
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2691590614
Short name T403
Test name
Test status
Simulation time 2892527488 ps
CPU time 5.25 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:32:27 PM PDT 24
Peak memory 182556 kb
Host smart-f3e3c1ee-854f-4415-8796-ba29ebf16089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691590614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2691590614
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2324896327
Short name T187
Test name
Test status
Simulation time 186746725398 ps
CPU time 306.32 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:37:28 PM PDT 24
Peak memory 195568 kb
Host smart-9ece3da2-dfeb-4b88-9f62-80ad5409fb43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324896327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2324896327
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3787180678
Short name T330
Test name
Test status
Simulation time 238143578809 ps
CPU time 452.78 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:39:37 PM PDT 24
Peak memory 182652 kb
Host smart-acc08e3a-3616-4c0c-990f-2242cbf8c0d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787180678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3787180678
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2689183620
Short name T401
Test name
Test status
Simulation time 692496010759 ps
CPU time 256.62 seconds
Started Apr 02 12:32:09 PM PDT 24
Finished Apr 02 12:36:26 PM PDT 24
Peak memory 182544 kb
Host smart-9430aebc-7408-496b-abe1-e590587ea9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689183620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2689183620
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2517374139
Short name T300
Test name
Test status
Simulation time 89851446586 ps
CPU time 557.79 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:41:18 PM PDT 24
Peak memory 190776 kb
Host smart-88313d72-0feb-4ac3-a6be-d76011baf2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517374139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2517374139
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2087086787
Short name T109
Test name
Test status
Simulation time 31828186052 ps
CPU time 254.1 seconds
Started Apr 02 12:32:01 PM PDT 24
Finished Apr 02 12:36:16 PM PDT 24
Peak memory 194172 kb
Host smart-18618f01-72cc-455b-ac03-763f2730cf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087086787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2087086787
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.697272443
Short name T18
Test name
Test status
Simulation time 123305003 ps
CPU time 0.77 seconds
Started Apr 02 12:32:10 PM PDT 24
Finished Apr 02 12:32:11 PM PDT 24
Peak memory 212988 kb
Host smart-eb89bdce-7568-4074-a0d4-e0db7f59eef3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697272443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.697272443
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1967236408
Short name T77
Test name
Test status
Simulation time 118875692740 ps
CPU time 792.7 seconds
Started Apr 02 12:32:09 PM PDT 24
Finished Apr 02 12:45:22 PM PDT 24
Peak memory 205500 kb
Host smart-6f1e0626-a5f4-47e5-ab4e-748d6c80640a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967236408 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1967236408
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.174550766
Short name T8
Test name
Test status
Simulation time 222827029203 ps
CPU time 262.09 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:36:40 PM PDT 24
Peak memory 182596 kb
Host smart-09b1592c-8bc7-4ad8-9747-21581745e977
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174550766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.174550766
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2273940366
Short name T412
Test name
Test status
Simulation time 153567667836 ps
CPU time 127.78 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:34:29 PM PDT 24
Peak memory 182576 kb
Host smart-be417212-f3c0-4200-afc4-7ebf16e514c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273940366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2273940366
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3638980292
Short name T56
Test name
Test status
Simulation time 88505496593 ps
CPU time 288.88 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:37:04 PM PDT 24
Peak memory 190764 kb
Host smart-ab40237e-ceb9-482c-a7a8-a44839b19da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638980292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3638980292
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.52697882
Short name T45
Test name
Test status
Simulation time 1178796356331 ps
CPU time 2201.18 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 01:09:06 PM PDT 24
Peak memory 190756 kb
Host smart-e3061b3f-ac27-4c2d-bff3-5048fc46e598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52697882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.52697882
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1408383946
Short name T209
Test name
Test status
Simulation time 138668011015 ps
CPU time 208.32 seconds
Started Apr 02 12:32:26 PM PDT 24
Finished Apr 02 12:35:55 PM PDT 24
Peak memory 182560 kb
Host smart-f4243af1-7feb-42c8-aee6-97dea352c79a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408383946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1408383946
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3964809171
Short name T367
Test name
Test status
Simulation time 132337291037 ps
CPU time 177.67 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 12:35:26 PM PDT 24
Peak memory 182576 kb
Host smart-8c052d51-b77d-4967-8f55-07d2b31dd513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964809171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3964809171
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.947895153
Short name T256
Test name
Test status
Simulation time 57473861364 ps
CPU time 100.67 seconds
Started Apr 02 12:32:26 PM PDT 24
Finished Apr 02 12:34:07 PM PDT 24
Peak memory 190752 kb
Host smart-bf6a9dce-a588-494e-af07-a06ef1cd9fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947895153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.947895153
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2683223305
Short name T319
Test name
Test status
Simulation time 197792110657 ps
CPU time 255.48 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:36:41 PM PDT 24
Peak memory 182572 kb
Host smart-2c5dd92f-d506-42aa-9489-fae2ce5fb2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683223305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2683223305
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.909775367
Short name T302
Test name
Test status
Simulation time 794514798156 ps
CPU time 889.66 seconds
Started Apr 02 12:32:26 PM PDT 24
Finished Apr 02 12:47:16 PM PDT 24
Peak memory 194032 kb
Host smart-799915f6-9eff-405f-b905-1b07dd21b502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909775367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
909775367
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2064913700
Short name T211
Test name
Test status
Simulation time 1113010615310 ps
CPU time 645.15 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:43:06 PM PDT 24
Peak memory 182564 kb
Host smart-a4a5fe51-ddcd-4128-8529-bef6ad16ef9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064913700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2064913700
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1782749958
Short name T62
Test name
Test status
Simulation time 121411221141 ps
CPU time 187.5 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:35:27 PM PDT 24
Peak memory 182528 kb
Host smart-85ba0310-ffda-483f-928d-2adde7d91ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782749958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1782749958
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2281765085
Short name T277
Test name
Test status
Simulation time 968085587896 ps
CPU time 450.66 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:39:56 PM PDT 24
Peak memory 190752 kb
Host smart-c1caeda0-98e1-489e-800d-53bfe7e9ae16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281765085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2281765085
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2198424748
Short name T41
Test name
Test status
Simulation time 220632704748 ps
CPU time 115.43 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:34:14 PM PDT 24
Peak memory 182532 kb
Host smart-081b6960-0a0a-4361-9f9e-3e700d539d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198424748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2198424748
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1985063848
Short name T33
Test name
Test status
Simulation time 21382513420 ps
CPU time 256.07 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:36:36 PM PDT 24
Peak memory 197248 kb
Host smart-2038c15c-ecc1-4bb6-b141-1030a8004828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985063848 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1985063848
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.4156524418
Short name T241
Test name
Test status
Simulation time 6271441747063 ps
CPU time 1656.74 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 01:00:02 PM PDT 24
Peak memory 182600 kb
Host smart-29a45c3a-1d95-42e2-bc56-275f2aa909df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156524418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.4156524418
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.4076419245
Short name T359
Test name
Test status
Simulation time 91130507279 ps
CPU time 139.35 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:34:39 PM PDT 24
Peak memory 182524 kb
Host smart-d585fb1b-48c6-483f-adc9-5244b1cafb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076419245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4076419245
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.100486018
Short name T147
Test name
Test status
Simulation time 918759025620 ps
CPU time 407.3 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:39:10 PM PDT 24
Peak memory 190760 kb
Host smart-f3d1cc55-516d-44fa-b3cc-8d90d59292ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100486018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.100486018
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.628985220
Short name T204
Test name
Test status
Simulation time 3760044389 ps
CPU time 12.94 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:32:36 PM PDT 24
Peak memory 182600 kb
Host smart-023141c3-f248-43fb-bded-3a907e54378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628985220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.628985220
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3277113687
Short name T5
Test name
Test status
Simulation time 855489758817 ps
CPU time 224.03 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:36:04 PM PDT 24
Peak memory 190700 kb
Host smart-8972898c-1f80-44cb-a1fc-b29e08e6b8fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277113687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3277113687
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2105145897
Short name T226
Test name
Test status
Simulation time 20179231603 ps
CPU time 21.1 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:32:44 PM PDT 24
Peak memory 182608 kb
Host smart-38aed149-4ba5-4da0-854e-1da94cec728d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105145897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2105145897
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2502008569
Short name T379
Test name
Test status
Simulation time 75662338265 ps
CPU time 112.72 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:34:14 PM PDT 24
Peak memory 182584 kb
Host smart-6efa929e-5c21-4fe2-b6c1-001697ae823e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502008569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2502008569
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3614725869
Short name T238
Test name
Test status
Simulation time 181481449400 ps
CPU time 739.68 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:44:39 PM PDT 24
Peak memory 190784 kb
Host smart-0dec0050-0293-40ea-89d0-7157b2749029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614725869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3614725869
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1914861280
Short name T63
Test name
Test status
Simulation time 12161648 ps
CPU time 0.5 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:32:23 PM PDT 24
Peak memory 182300 kb
Host smart-0d50054e-ad6d-454c-96c8-251323c98f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914861280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1914861280
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3772917623
Short name T402
Test name
Test status
Simulation time 90669104679 ps
CPU time 142.48 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:34:45 PM PDT 24
Peak memory 182536 kb
Host smart-36e8cac0-d971-47de-8dc8-5401619c5545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772917623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3772917623
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.634744744
Short name T349
Test name
Test status
Simulation time 198243101335 ps
CPU time 63.22 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:33:28 PM PDT 24
Peak memory 182568 kb
Host smart-3a23f945-a5e4-4ff3-8a9f-9510ba91b002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634744744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.634744744
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1679947246
Short name T112
Test name
Test status
Simulation time 786084979898 ps
CPU time 1022.61 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:49:24 PM PDT 24
Peak memory 190804 kb
Host smart-405bf722-a3dc-4fc5-968e-e567d8fa1a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679947246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1679947246
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.4062218104
Short name T334
Test name
Test status
Simulation time 698148483731 ps
CPU time 459.83 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:40:04 PM PDT 24
Peak memory 182656 kb
Host smart-ea5b6d0b-7309-4fae-98ec-9310907dbfc2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062218104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.4062218104
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.666368882
Short name T411
Test name
Test status
Simulation time 280734334198 ps
CPU time 223.14 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:36:02 PM PDT 24
Peak memory 182540 kb
Host smart-a18ec1ba-0a4b-42f4-a6fd-aefae42ba6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666368882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.666368882
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.853553914
Short name T76
Test name
Test status
Simulation time 238893333197 ps
CPU time 397.08 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:38:58 PM PDT 24
Peak memory 190792 kb
Host smart-a87d6be9-a776-4627-b07c-f73cd638fd11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853553914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.853553914
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2442855360
Short name T339
Test name
Test status
Simulation time 283923608797 ps
CPU time 111.82 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:34:16 PM PDT 24
Peak memory 190788 kb
Host smart-b03c4dc8-95eb-487b-83aa-aa2a566e6796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442855360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2442855360
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2170410341
Short name T21
Test name
Test status
Simulation time 757215751973 ps
CPU time 1097.43 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:50:38 PM PDT 24
Peak memory 195144 kb
Host smart-32f050b3-6371-4e81-83a4-5531a2a42264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170410341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2170410341
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.1098212843
Short name T49
Test name
Test status
Simulation time 32299532360 ps
CPU time 115.08 seconds
Started Apr 02 12:32:43 PM PDT 24
Finished Apr 02 12:34:39 PM PDT 24
Peak memory 197260 kb
Host smart-2a061757-a474-43c4-8160-b505fc9b61fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098212843 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.1098212843
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3615498743
Short name T152
Test name
Test status
Simulation time 382252010241 ps
CPU time 221.66 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:36:07 PM PDT 24
Peak memory 182616 kb
Host smart-02aa43a8-ced4-4692-a6e0-33638428298c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615498743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3615498743
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3627974356
Short name T428
Test name
Test status
Simulation time 209574844882 ps
CPU time 290.87 seconds
Started Apr 02 12:32:39 PM PDT 24
Finished Apr 02 12:37:30 PM PDT 24
Peak memory 182532 kb
Host smart-9dbe6092-a94f-4744-8e5d-1b7f7f1a043d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627974356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3627974356
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.676090845
Short name T292
Test name
Test status
Simulation time 720282114544 ps
CPU time 496.52 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:40:46 PM PDT 24
Peak memory 190768 kb
Host smart-bcb1ddec-bbc2-41b7-8508-821326c4a00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676090845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.676090845
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.795851222
Short name T392
Test name
Test status
Simulation time 284417864 ps
CPU time 0.93 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:32:26 PM PDT 24
Peak memory 182348 kb
Host smart-52d5c37a-dbfb-4c9a-bd37-fb22e00cfe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795851222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.795851222
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.299778579
Short name T391
Test name
Test status
Simulation time 328069072379 ps
CPU time 123.67 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:34:28 PM PDT 24
Peak memory 182592 kb
Host smart-6b446e45-b2e0-41b6-8441-94603fdeb855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299778579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.299778579
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.235960154
Short name T138
Test name
Test status
Simulation time 148052082933 ps
CPU time 511.4 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:40:51 PM PDT 24
Peak memory 190780 kb
Host smart-7827c537-80d2-4977-933b-04a306c7c815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235960154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.235960154
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3781048133
Short name T139
Test name
Test status
Simulation time 303728065755 ps
CPU time 626.46 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:42:50 PM PDT 24
Peak memory 193844 kb
Host smart-3ef62a59-5f2a-4442-ae60-19e42035b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781048133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3781048133
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3417313951
Short name T179
Test name
Test status
Simulation time 1355381570857 ps
CPU time 1893.49 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 01:03:54 PM PDT 24
Peak memory 190740 kb
Host smart-9112fee4-019a-4343-93d5-70d8028def6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417313951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3417313951
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4066806157
Short name T104
Test name
Test status
Simulation time 1400055118913 ps
CPU time 725.98 seconds
Started Apr 02 12:32:31 PM PDT 24
Finished Apr 02 12:44:37 PM PDT 24
Peak memory 182600 kb
Host smart-6c5b0a68-ee52-4bfa-848e-0187115fac86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066806157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4066806157
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1691415160
Short name T362
Test name
Test status
Simulation time 49178341490 ps
CPU time 78.58 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:33:42 PM PDT 24
Peak memory 182560 kb
Host smart-a54d9d6b-9a21-4af9-9b4b-c52524b64d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691415160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1691415160
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3539297041
Short name T415
Test name
Test status
Simulation time 39287421166 ps
CPU time 623.21 seconds
Started Apr 02 12:32:35 PM PDT 24
Finished Apr 02 12:42:58 PM PDT 24
Peak memory 182592 kb
Host smart-fc9961c0-f439-4627-8525-f8c7099750dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539297041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3539297041
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1942689047
Short name T335
Test name
Test status
Simulation time 35673162798 ps
CPU time 61.11 seconds
Started Apr 02 12:32:27 PM PDT 24
Finished Apr 02 12:33:29 PM PDT 24
Peak memory 182580 kb
Host smart-30b8490a-c2fa-4c80-9219-6471f5e275cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942689047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1942689047
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1185242922
Short name T321
Test name
Test status
Simulation time 83722830469 ps
CPU time 135.25 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:34:20 PM PDT 24
Peak memory 182568 kb
Host smart-f8fe7878-3937-437d-abad-7c4032c813bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185242922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1185242922
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3015101333
Short name T382
Test name
Test status
Simulation time 735615145249 ps
CPU time 310.17 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:37:14 PM PDT 24
Peak memory 182580 kb
Host smart-8f7c811f-ce95-4414-9f78-e00c46cbfdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015101333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3015101333
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.782292430
Short name T156
Test name
Test status
Simulation time 270402870384 ps
CPU time 1675.15 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 01:00:13 PM PDT 24
Peak memory 190768 kb
Host smart-e4048710-1709-4c7c-8e28-3652f9160e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782292430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.782292430
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.3877140542
Short name T176
Test name
Test status
Simulation time 108998503844 ps
CPU time 98.91 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:33:59 PM PDT 24
Peak memory 190820 kb
Host smart-28c74886-b1ee-4d29-9b0a-c83dcdca2284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877140542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3877140542
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.706219426
Short name T435
Test name
Test status
Simulation time 65914878881 ps
CPU time 70.91 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:33:33 PM PDT 24
Peak memory 182636 kb
Host smart-182f8a8c-84d1-476f-8084-81bad5d57bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706219426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.706219426
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2455684768
Short name T268
Test name
Test status
Simulation time 71940292873 ps
CPU time 122.57 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:34:26 PM PDT 24
Peak memory 190744 kb
Host smart-cdaf9021-4820-4438-b0d2-62c7c9f2b8ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455684768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2455684768
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2544136287
Short name T338
Test name
Test status
Simulation time 110003340505 ps
CPU time 49.67 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:33:12 PM PDT 24
Peak memory 182568 kb
Host smart-4f25ea52-d6c1-438a-9f6f-57045742395a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544136287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2544136287
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2595125145
Short name T272
Test name
Test status
Simulation time 174444519135 ps
CPU time 312.51 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 12:37:42 PM PDT 24
Peak memory 190744 kb
Host smart-d6f68841-1c23-490a-bc13-12ca8116ec35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595125145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2595125145
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.292428008
Short name T303
Test name
Test status
Simulation time 91988573129 ps
CPU time 951.36 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:48:19 PM PDT 24
Peak memory 190760 kb
Host smart-d9a7a6cc-f1ee-4c9c-a057-84e1f43051f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292428008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.292428008
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.306304958
Short name T244
Test name
Test status
Simulation time 186421236991 ps
CPU time 306.33 seconds
Started Apr 02 12:32:05 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 182532 kb
Host smart-0b2d4107-fb2f-4a34-8649-e17782fec048
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306304958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.306304958
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.317994725
Short name T373
Test name
Test status
Simulation time 198898936214 ps
CPU time 331.27 seconds
Started Apr 02 12:32:07 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 182568 kb
Host smart-bf462dad-c106-4f2b-8c51-eb4e996e8451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317994725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.317994725
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1133124967
Short name T262
Test name
Test status
Simulation time 483612917914 ps
CPU time 3051.34 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 01:22:57 PM PDT 24
Peak memory 190788 kb
Host smart-daf2dc2e-6b26-4b0e-b0f2-7ab941a59d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133124967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1133124967
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3856004459
Short name T430
Test name
Test status
Simulation time 162854315 ps
CPU time 1.04 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:32:01 PM PDT 24
Peak memory 192472 kb
Host smart-6fab66a9-f5fb-4cb1-8d04-42a25be96e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856004459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3856004459
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2911420795
Short name T443
Test name
Test status
Simulation time 161955177658 ps
CPU time 581.58 seconds
Started Apr 02 12:32:14 PM PDT 24
Finished Apr 02 12:41:55 PM PDT 24
Peak memory 190764 kb
Host smart-483b5123-8af7-452a-88ee-804cf173be0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911420795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2911420795
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.521768392
Short name T71
Test name
Test status
Simulation time 1003553176371 ps
CPU time 623.6 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:42:45 PM PDT 24
Peak memory 190744 kb
Host smart-0de01df2-86a4-4554-9e70-a9b31e25bedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521768392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.521768392
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3661050837
Short name T279
Test name
Test status
Simulation time 317037805443 ps
CPU time 712.51 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:44:13 PM PDT 24
Peak memory 190788 kb
Host smart-0aa9c5d7-48b8-449f-bad1-0ebdf110d5a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661050837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3661050837
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2799715992
Short name T440
Test name
Test status
Simulation time 502652392867 ps
CPU time 1830.54 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 01:03:00 PM PDT 24
Peak memory 190744 kb
Host smart-9f24b2dd-46ba-4b61-ba5a-eabadd6bd7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799715992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2799715992
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.494985534
Short name T26
Test name
Test status
Simulation time 135898432588 ps
CPU time 95.93 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:34:01 PM PDT 24
Peak memory 182584 kb
Host smart-c4b90233-4667-4c5c-8c58-25052da20ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494985534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.494985534
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3639700373
Short name T246
Test name
Test status
Simulation time 344939315721 ps
CPU time 460.34 seconds
Started Apr 02 12:32:21 PM PDT 24
Finished Apr 02 12:40:02 PM PDT 24
Peak memory 190784 kb
Host smart-a932c3cf-9826-4fd3-b303-315c25383329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639700373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3639700373
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3258563264
Short name T115
Test name
Test status
Simulation time 36637924044 ps
CPU time 14.62 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:32:37 PM PDT 24
Peak memory 182432 kb
Host smart-3311bc66-61e5-4e3d-8e9c-63b542c8c609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258563264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3258563264
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1103822431
Short name T134
Test name
Test status
Simulation time 33457642706 ps
CPU time 32.62 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:32:56 PM PDT 24
Peak memory 182560 kb
Host smart-7de105ad-bc59-4308-9097-038aa19d5b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103822431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1103822431
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.4044877392
Short name T133
Test name
Test status
Simulation time 49726770348 ps
CPU time 65.07 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:33:29 PM PDT 24
Peak memory 182636 kb
Host smart-56d9a2d8-4a71-410c-9064-7aa489ccb327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044877392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4044877392
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2640156917
Short name T24
Test name
Test status
Simulation time 191794025828 ps
CPU time 1101.77 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 12:50:51 PM PDT 24
Peak memory 190756 kb
Host smart-b6bc321c-ce52-48af-8a4c-bb9986b8b8ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640156917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2640156917
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2503170119
Short name T222
Test name
Test status
Simulation time 25613062379 ps
CPU time 33.68 seconds
Started Apr 02 12:32:01 PM PDT 24
Finished Apr 02 12:32:35 PM PDT 24
Peak memory 182608 kb
Host smart-341bf1d9-cfed-42d6-86f6-8578f132d96f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503170119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2503170119
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.596084248
Short name T419
Test name
Test status
Simulation time 62307084870 ps
CPU time 83.33 seconds
Started Apr 02 12:32:12 PM PDT 24
Finished Apr 02 12:33:35 PM PDT 24
Peak memory 182620 kb
Host smart-0b9aad93-785e-4a6d-822a-29001b4a1bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596084248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.596084248
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.892894984
Short name T194
Test name
Test status
Simulation time 105203749518 ps
CPU time 1352.97 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:54:33 PM PDT 24
Peak memory 190776 kb
Host smart-ab70744d-6fb4-40ba-a3e0-1728a81f525a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892894984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.892894984
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3963349049
Short name T233
Test name
Test status
Simulation time 25302352555 ps
CPU time 39.56 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:32:43 PM PDT 24
Peak memory 182448 kb
Host smart-1924757c-a5f0-4886-ab0d-e025c2652878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963349049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3963349049
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.280322771
Short name T60
Test name
Test status
Simulation time 250283692684 ps
CPU time 401.29 seconds
Started Apr 02 12:32:12 PM PDT 24
Finished Apr 02 12:38:53 PM PDT 24
Peak memory 194972 kb
Host smart-f23bd8c9-6774-414a-8685-d9412c6f623e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280322771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.280322771
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3720084568
Short name T193
Test name
Test status
Simulation time 49565561129 ps
CPU time 548.57 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:41:33 PM PDT 24
Peak memory 190724 kb
Host smart-f5535270-92ad-47c9-ade4-0e0286a39331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720084568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3720084568
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3397365442
Short name T410
Test name
Test status
Simulation time 115065709993 ps
CPU time 60.17 seconds
Started Apr 02 12:32:17 PM PDT 24
Finished Apr 02 12:33:17 PM PDT 24
Peak memory 182628 kb
Host smart-e913a6ae-071f-45e8-9c13-b8c0f77ec5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397365442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3397365442
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1198323964
Short name T182
Test name
Test status
Simulation time 137773554049 ps
CPU time 849.34 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:46:31 PM PDT 24
Peak memory 190788 kb
Host smart-32932e99-e4a6-49e8-a09e-58a718052289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198323964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1198323964
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.472515263
Short name T280
Test name
Test status
Simulation time 341105182740 ps
CPU time 125.02 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:34:30 PM PDT 24
Peak memory 190784 kb
Host smart-957ce2e4-38e1-42b1-a1de-b5dd7a6788b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472515263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.472515263
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.4007343298
Short name T301
Test name
Test status
Simulation time 99194583223 ps
CPU time 1594.61 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:58:54 PM PDT 24
Peak memory 182588 kb
Host smart-b788c6fd-0b05-42e0-8633-d62b1800942b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007343298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.4007343298
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3492381032
Short name T337
Test name
Test status
Simulation time 170185064532 ps
CPU time 128.23 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:34:32 PM PDT 24
Peak memory 191776 kb
Host smart-932ab86b-205f-43dd-990a-0e9ce62e307b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492381032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3492381032
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1802914286
Short name T314
Test name
Test status
Simulation time 130194921492 ps
CPU time 389.21 seconds
Started Apr 02 12:32:22 PM PDT 24
Finished Apr 02 12:38:52 PM PDT 24
Peak memory 190796 kb
Host smart-5b8e9022-c70d-4b95-a499-878259b8696c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802914286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1802914286
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1370502306
Short name T414
Test name
Test status
Simulation time 1356825469 ps
CPU time 2.62 seconds
Started Apr 02 12:32:10 PM PDT 24
Finished Apr 02 12:32:12 PM PDT 24
Peak memory 182364 kb
Host smart-775254df-b418-46e6-80d7-2dd4e98a61fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370502306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1370502306
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1850332670
Short name T393
Test name
Test status
Simulation time 68218041036 ps
CPU time 42.58 seconds
Started Apr 02 12:31:58 PM PDT 24
Finished Apr 02 12:32:41 PM PDT 24
Peak memory 182644 kb
Host smart-3dcac970-76c9-45ec-8098-a1e99a69f8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850332670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1850332670
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1614752376
Short name T119
Test name
Test status
Simulation time 203749622143 ps
CPU time 751.17 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:44:35 PM PDT 24
Peak memory 190728 kb
Host smart-d32059d1-dc37-499c-8b8e-c6761dd0d7a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614752376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1614752376
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2640308016
Short name T342
Test name
Test status
Simulation time 426788790631 ps
CPU time 2795.31 seconds
Started Apr 02 12:32:01 PM PDT 24
Finished Apr 02 01:18:37 PM PDT 24
Peak memory 190736 kb
Host smart-d43cd724-a342-4442-84ab-cbfb4e7a4d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640308016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2640308016
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3185695790
Short name T217
Test name
Test status
Simulation time 325010770061 ps
CPU time 297.51 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:37:17 PM PDT 24
Peak memory 194256 kb
Host smart-019cce47-88b3-4668-b6c0-6c1bbc3dbdff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185695790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3185695790
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2807775613
Short name T210
Test name
Test status
Simulation time 281668744110 ps
CPU time 127.73 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:34:32 PM PDT 24
Peak memory 190756 kb
Host smart-504e9665-1905-4d31-bfb4-21599c609027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807775613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2807775613
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3328375749
Short name T255
Test name
Test status
Simulation time 436170128214 ps
CPU time 3534.11 seconds
Started Apr 02 12:32:32 PM PDT 24
Finished Apr 02 01:31:27 PM PDT 24
Peak memory 190752 kb
Host smart-aa240abe-86e8-4051-8c23-225435335cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328375749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3328375749
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1268797179
Short name T215
Test name
Test status
Simulation time 79659652634 ps
CPU time 48.55 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:33:13 PM PDT 24
Peak memory 190780 kb
Host smart-71ff6a4d-1e69-4ca4-8159-b52e13c3a8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268797179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1268797179
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3838506816
Short name T273
Test name
Test status
Simulation time 50225056768 ps
CPU time 78.77 seconds
Started Apr 02 12:32:19 PM PDT 24
Finished Apr 02 12:33:38 PM PDT 24
Peak memory 193376 kb
Host smart-5340f171-f72a-4146-8eaa-a8bc102e7148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838506816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3838506816
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3714703915
Short name T225
Test name
Test status
Simulation time 20069246577 ps
CPU time 17.23 seconds
Started Apr 02 12:32:29 PM PDT 24
Finished Apr 02 12:32:46 PM PDT 24
Peak memory 182556 kb
Host smart-be5d62bd-ac8c-4f95-958a-2d2d3c124eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714703915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3714703915
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1800213610
Short name T108
Test name
Test status
Simulation time 188404303387 ps
CPU time 310.12 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:37:30 PM PDT 24
Peak memory 191860 kb
Host smart-1e02fd6a-cbb7-45de-b0fd-f37cfe64d2aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800213610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1800213610
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1178136330
Short name T341
Test name
Test status
Simulation time 13765435823 ps
CPU time 5.31 seconds
Started Apr 02 12:32:11 PM PDT 24
Finished Apr 02 12:32:17 PM PDT 24
Peak memory 182580 kb
Host smart-9897f895-d2c5-401b-986b-47260aea1d9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178136330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1178136330
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2553843466
Short name T27
Test name
Test status
Simulation time 6450688790 ps
CPU time 5.88 seconds
Started Apr 02 12:32:11 PM PDT 24
Finished Apr 02 12:32:17 PM PDT 24
Peak memory 182556 kb
Host smart-9ecffc21-abe8-41b7-808e-31d25f90b979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553843466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2553843466
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3495700588
Short name T270
Test name
Test status
Simulation time 56035082394 ps
CPU time 364.94 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:38:14 PM PDT 24
Peak memory 190752 kb
Host smart-f60635d7-48c3-49fb-9222-7096913ae784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495700588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3495700588
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2114734700
Short name T360
Test name
Test status
Simulation time 378085909 ps
CPU time 0.7 seconds
Started Apr 02 12:31:50 PM PDT 24
Finished Apr 02 12:31:51 PM PDT 24
Peak memory 182372 kb
Host smart-7ff08844-af31-473b-9e88-2fabe94b2bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114734700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2114734700
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.3606934387
Short name T125
Test name
Test status
Simulation time 233125561575 ps
CPU time 330.76 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 12:37:58 PM PDT 24
Peak memory 190816 kb
Host smart-97bbc9dc-91be-4f01-8a9b-dd4cc23e6f03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606934387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3606934387
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.383287107
Short name T2
Test name
Test status
Simulation time 34988350640 ps
CPU time 98.31 seconds
Started Apr 02 12:32:25 PM PDT 24
Finished Apr 02 12:34:04 PM PDT 24
Peak memory 190756 kb
Host smart-64fcd7b3-f544-4f5f-a138-48d0a5b266f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383287107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.383287107
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2281240431
Short name T165
Test name
Test status
Simulation time 57837149413 ps
CPU time 47.72 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:33:11 PM PDT 24
Peak memory 182612 kb
Host smart-d0bfa936-e994-457b-8839-90e6b0d41a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281240431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2281240431
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3047064244
Short name T106
Test name
Test status
Simulation time 114923854960 ps
CPU time 54.48 seconds
Started Apr 02 12:32:20 PM PDT 24
Finished Apr 02 12:33:14 PM PDT 24
Peak memory 190764 kb
Host smart-fcac4fb8-c1b1-4abc-a434-a1e8a45055b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047064244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3047064244
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.730381531
Short name T417
Test name
Test status
Simulation time 808128372 ps
CPU time 1.8 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:32:25 PM PDT 24
Peak memory 182360 kb
Host smart-44498608-9718-4aa9-a30e-1c0d60197502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730381531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.730381531
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2807562318
Short name T130
Test name
Test status
Simulation time 1161151680533 ps
CPU time 237.82 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:36:21 PM PDT 24
Peak memory 190676 kb
Host smart-e9ebff24-0e45-4c35-b8c4-af00c30a6c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807562318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2807562318
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2024983438
Short name T239
Test name
Test status
Simulation time 49166789553 ps
CPU time 108.48 seconds
Started Apr 02 12:32:28 PM PDT 24
Finished Apr 02 12:34:17 PM PDT 24
Peak memory 190792 kb
Host smart-8d751275-a047-4f15-8411-02d4d532429e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024983438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2024983438
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3869803675
Short name T240
Test name
Test status
Simulation time 689784618978 ps
CPU time 2093.11 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 01:07:17 PM PDT 24
Peak memory 192800 kb
Host smart-990bf6e6-052f-4381-925d-f323836bf8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869803675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3869803675
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3233910990
Short name T318
Test name
Test status
Simulation time 48163910196 ps
CPU time 45.26 seconds
Started Apr 02 12:32:27 PM PDT 24
Finished Apr 02 12:33:13 PM PDT 24
Peak memory 182644 kb
Host smart-b5ecb445-e02c-4089-b3fa-36842cf05285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233910990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3233910990
Directory /workspace/99.rv_timer_random/latest
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