Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 584
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T513 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3754284924 Apr 15 12:20:33 PM PDT 24 Apr 15 12:20:35 PM PDT 24 40398177 ps
T514 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.900036374 Apr 15 12:20:09 PM PDT 24 Apr 15 12:20:12 PM PDT 24 135302481 ps
T515 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3583276995 Apr 15 12:20:11 PM PDT 24 Apr 15 12:20:13 PM PDT 24 25208114 ps
T516 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2868181163 Apr 15 12:20:22 PM PDT 24 Apr 15 12:20:23 PM PDT 24 93567792 ps
T517 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3768576777 Apr 15 12:20:15 PM PDT 24 Apr 15 12:20:17 PM PDT 24 16474332 ps
T518 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2480166143 Apr 15 12:20:11 PM PDT 24 Apr 15 12:20:13 PM PDT 24 13869318 ps
T98 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.58079968 Apr 15 12:20:42 PM PDT 24 Apr 15 12:20:44 PM PDT 24 153957671 ps
T519 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2427098714 Apr 15 12:20:15 PM PDT 24 Apr 15 12:20:19 PM PDT 24 223378450 ps
T520 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.542407738 Apr 15 12:20:29 PM PDT 24 Apr 15 12:20:30 PM PDT 24 25839651 ps
T521 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1338316600 Apr 15 12:20:11 PM PDT 24 Apr 15 12:20:13 PM PDT 24 56411011 ps
T76 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3601768938 Apr 15 12:20:24 PM PDT 24 Apr 15 12:20:25 PM PDT 24 49757011 ps
T522 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1980180755 Apr 15 12:20:33 PM PDT 24 Apr 15 12:20:34 PM PDT 24 13044545 ps
T94 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3813922746 Apr 15 12:20:24 PM PDT 24 Apr 15 12:20:26 PM PDT 24 427337549 ps
T523 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1575254382 Apr 15 12:20:08 PM PDT 24 Apr 15 12:20:10 PM PDT 24 33189285 ps
T524 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2700140896 Apr 15 12:19:54 PM PDT 24 Apr 15 12:19:57 PM PDT 24 62460672 ps
T77 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3265486290 Apr 15 12:20:06 PM PDT 24 Apr 15 12:20:07 PM PDT 24 39228266 ps
T78 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1009462391 Apr 15 12:20:10 PM PDT 24 Apr 15 12:20:13 PM PDT 24 16774983 ps
T525 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.153501182 Apr 15 12:20:06 PM PDT 24 Apr 15 12:20:08 PM PDT 24 22510290 ps
T526 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.989831176 Apr 15 12:20:09 PM PDT 24 Apr 15 12:20:12 PM PDT 24 12622765 ps
T527 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2190185495 Apr 15 12:20:37 PM PDT 24 Apr 15 12:20:39 PM PDT 24 133930526 ps
T528 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.187790015 Apr 15 12:20:11 PM PDT 24 Apr 15 12:20:15 PM PDT 24 269825131 ps
T529 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.385864898 Apr 15 12:20:16 PM PDT 24 Apr 15 12:20:23 PM PDT 24 83536664 ps
T530 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.310105296 Apr 15 12:20:11 PM PDT 24 Apr 15 12:20:13 PM PDT 24 42098609 ps
T531 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.40442813 Apr 15 12:20:27 PM PDT 24 Apr 15 12:20:29 PM PDT 24 43883525 ps
T532 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1055041922 Apr 15 12:20:09 PM PDT 24 Apr 15 12:20:11 PM PDT 24 70992295 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3911764039 Apr 15 12:20:37 PM PDT 24 Apr 15 12:20:38 PM PDT 24 363210327 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2725788532 Apr 15 12:20:18 PM PDT 24 Apr 15 12:20:20 PM PDT 24 117010386 ps
T535 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2255201099 Apr 15 12:20:05 PM PDT 24 Apr 15 12:20:07 PM PDT 24 13516082 ps
T536 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2767713636 Apr 15 12:20:16 PM PDT 24 Apr 15 12:20:18 PM PDT 24 14520992 ps
T537 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1340501519 Apr 15 12:20:11 PM PDT 24 Apr 15 12:20:14 PM PDT 24 40931734 ps
T538 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2175255125 Apr 15 12:20:14 PM PDT 24 Apr 15 12:20:15 PM PDT 24 188339349 ps
T79 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1449590832 Apr 15 12:20:12 PM PDT 24 Apr 15 12:20:14 PM PDT 24 14474116 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3680966622 Apr 15 12:20:14 PM PDT 24 Apr 15 12:20:18 PM PDT 24 170010349 ps
T80 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1982556912 Apr 15 12:20:16 PM PDT 24 Apr 15 12:20:18 PM PDT 24 28489875 ps
T540 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2096891930 Apr 15 12:20:18 PM PDT 24 Apr 15 12:20:20 PM PDT 24 62834574 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.437074076 Apr 15 12:20:03 PM PDT 24 Apr 15 12:20:04 PM PDT 24 15290639 ps
T542 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2423279873 Apr 15 12:20:13 PM PDT 24 Apr 15 12:20:15 PM PDT 24 12837608 ps
T543 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2798768229 Apr 15 12:20:04 PM PDT 24 Apr 15 12:20:05 PM PDT 24 40319651 ps
T544 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3871532297 Apr 15 12:20:14 PM PDT 24 Apr 15 12:20:17 PM PDT 24 216391243 ps
T81 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4265135617 Apr 15 12:20:05 PM PDT 24 Apr 15 12:20:08 PM PDT 24 149409120 ps
T545 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.489302944 Apr 15 12:20:16 PM PDT 24 Apr 15 12:20:18 PM PDT 24 13821886 ps
T546 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2185287886 Apr 15 12:20:07 PM PDT 24 Apr 15 12:20:09 PM PDT 24 43806568 ps
T547 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2934765309 Apr 15 12:20:33 PM PDT 24 Apr 15 12:20:34 PM PDT 24 46765924 ps
T548 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.516457367 Apr 15 12:20:36 PM PDT 24 Apr 15 12:20:37 PM PDT 24 16163199 ps
T549 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2517023645 Apr 15 12:20:15 PM PDT 24 Apr 15 12:20:17 PM PDT 24 15967481 ps
T550 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4077046239 Apr 15 12:20:06 PM PDT 24 Apr 15 12:20:08 PM PDT 24 19500724 ps
T551 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1860863731 Apr 15 12:20:22 PM PDT 24 Apr 15 12:20:23 PM PDT 24 65547066 ps
T552 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4176236821 Apr 15 12:20:10 PM PDT 24 Apr 15 12:20:13 PM PDT 24 26642633 ps
T553 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.151515082 Apr 15 12:20:27 PM PDT 24 Apr 15 12:20:28 PM PDT 24 103917231 ps
T554 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1182315796 Apr 15 12:20:14 PM PDT 24 Apr 15 12:20:17 PM PDT 24 24384041 ps
T555 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3407436446 Apr 15 12:20:07 PM PDT 24 Apr 15 12:20:09 PM PDT 24 24799584 ps
T556 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2754599708 Apr 15 12:20:34 PM PDT 24 Apr 15 12:20:35 PM PDT 24 50917612 ps
T557 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3697329524 Apr 15 12:20:27 PM PDT 24 Apr 15 12:20:28 PM PDT 24 181180195 ps
T558 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.495503428 Apr 15 12:20:13 PM PDT 24 Apr 15 12:20:15 PM PDT 24 29186363 ps
T559 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3915394108 Apr 15 12:20:28 PM PDT 24 Apr 15 12:20:30 PM PDT 24 43068515 ps
T560 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2399152384 Apr 15 12:20:40 PM PDT 24 Apr 15 12:20:41 PM PDT 24 17772035 ps
T561 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1067149035 Apr 15 12:20:10 PM PDT 24 Apr 15 12:20:13 PM PDT 24 223582054 ps
T562 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1137845918 Apr 15 12:20:09 PM PDT 24 Apr 15 12:20:11 PM PDT 24 785501509 ps
T82 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3983128136 Apr 15 12:20:05 PM PDT 24 Apr 15 12:20:08 PM PDT 24 447688562 ps
T563 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1107519149 Apr 15 12:20:24 PM PDT 24 Apr 15 12:20:25 PM PDT 24 181239673 ps
T564 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.936905251 Apr 15 12:20:36 PM PDT 24 Apr 15 12:20:37 PM PDT 24 38783228 ps
T565 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4239492502 Apr 15 12:20:25 PM PDT 24 Apr 15 12:20:26 PM PDT 24 13440302 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1457238452 Apr 15 12:20:10 PM PDT 24 Apr 15 12:20:14 PM PDT 24 187761898 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1955555506 Apr 15 12:20:39 PM PDT 24 Apr 15 12:20:41 PM PDT 24 16542023 ps
T83 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1658989746 Apr 15 12:20:12 PM PDT 24 Apr 15 12:20:15 PM PDT 24 35746455 ps
T568 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3730265239 Apr 15 12:20:30 PM PDT 24 Apr 15 12:20:31 PM PDT 24 22845884 ps
T569 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.832702191 Apr 15 12:20:15 PM PDT 24 Apr 15 12:20:17 PM PDT 24 13958002 ps
T570 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1789825107 Apr 15 12:20:22 PM PDT 24 Apr 15 12:20:23 PM PDT 24 14854166 ps
T571 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3561503652 Apr 15 12:20:20 PM PDT 24 Apr 15 12:20:22 PM PDT 24 147438341 ps
T572 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2056351849 Apr 15 12:20:06 PM PDT 24 Apr 15 12:20:08 PM PDT 24 86310645 ps
T573 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1330219516 Apr 15 12:20:08 PM PDT 24 Apr 15 12:20:10 PM PDT 24 68759450 ps
T574 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1317376110 Apr 15 12:19:55 PM PDT 24 Apr 15 12:19:58 PM PDT 24 108854186 ps
T575 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.436325253 Apr 15 12:20:06 PM PDT 24 Apr 15 12:20:08 PM PDT 24 21882983 ps
T576 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2363097628 Apr 15 12:19:52 PM PDT 24 Apr 15 12:19:56 PM PDT 24 24634710 ps
T577 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.940634896 Apr 15 12:20:28 PM PDT 24 Apr 15 12:20:30 PM PDT 24 20556593 ps
T95 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.155036009 Apr 15 12:20:09 PM PDT 24 Apr 15 12:20:13 PM PDT 24 273711682 ps
T578 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1537966060 Apr 15 12:20:08 PM PDT 24 Apr 15 12:20:10 PM PDT 24 162102160 ps
T579 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3523436500 Apr 15 12:20:37 PM PDT 24 Apr 15 12:20:38 PM PDT 24 61282810 ps
T580 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.812397917 Apr 15 12:20:07 PM PDT 24 Apr 15 12:20:09 PM PDT 24 71726547 ps
T581 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.471359861 Apr 15 12:20:28 PM PDT 24 Apr 15 12:20:30 PM PDT 24 29653956 ps
T582 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.255926541 Apr 15 12:20:14 PM PDT 24 Apr 15 12:20:16 PM PDT 24 706799707 ps
T583 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.4092221413 Apr 15 12:20:13 PM PDT 24 Apr 15 12:20:15 PM PDT 24 186474369 ps
T84 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4185313780 Apr 15 12:20:50 PM PDT 24 Apr 15 12:20:51 PM PDT 24 11776567 ps
T584 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1831588443 Apr 15 12:20:28 PM PDT 24 Apr 15 12:20:29 PM PDT 24 16662104 ps

Test location /workspace/coverage/default/116.rv_timer_random.2480416758
Short name T2
Test name
Test status
Simulation time 66207459285 ps
CPU time 121.47 seconds
Started Apr 15 12:25:14 PM PDT 24
Finished Apr 15 12:27:16 PM PDT 24
Peak memory 182456 kb
Host smart-5c9b0334-c8d1-4abb-8ad5-afc8001c5b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480416758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2480416758
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.419634791
Short name T14
Test name
Test status
Simulation time 50498583451 ps
CPU time 458.93 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:32:11 PM PDT 24
Peak memory 205396 kb
Host smart-a35130de-16d2-42a2-9d0e-0280cefacdde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419634791 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.419634791
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3658221980
Short name T62
Test name
Test status
Simulation time 2709540706548 ps
CPU time 1922.12 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:56:45 PM PDT 24
Peak memory 190512 kb
Host smart-28f52eb8-87f0-47a0-bb79-b90a57829e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658221980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3658221980
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random.3356608715
Short name T120
Test name
Test status
Simulation time 733151798957 ps
CPU time 373.37 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 190716 kb
Host smart-deec5726-d5d9-4540-99f0-e2d4d32d14e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356608715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3356608715
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1286332564
Short name T29
Test name
Test status
Simulation time 48147882 ps
CPU time 0.84 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 193456 kb
Host smart-21a956c1-7535-4599-aecc-5702b01b2270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286332564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1286332564
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.417138076
Short name T118
Test name
Test status
Simulation time 2741359120936 ps
CPU time 4400.35 seconds
Started Apr 15 12:24:59 PM PDT 24
Finished Apr 15 01:38:21 PM PDT 24
Peak memory 195284 kb
Host smart-e709c73f-a3b7-4ad3-a078-dc6d7569d4b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417138076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
417138076
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2845262464
Short name T150
Test name
Test status
Simulation time 2316888148817 ps
CPU time 1443.45 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:48:36 PM PDT 24
Peak memory 195600 kb
Host smart-f7aeb52b-55d0-4604-a97d-15a920b521f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845262464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2845262464
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1521590533
Short name T191
Test name
Test status
Simulation time 1539385281263 ps
CPU time 4730.72 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 01:43:34 PM PDT 24
Peak memory 190708 kb
Host smart-76a2122c-f34c-4cfb-91ab-a9d81e9f8677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521590533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1521590533
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2633188898
Short name T233
Test name
Test status
Simulation time 537090359620 ps
CPU time 2005.72 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:57:56 PM PDT 24
Peak memory 195160 kb
Host smart-f00abe4a-5c34-4816-a8f9-267be710b981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633188898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2633188898
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1411856276
Short name T193
Test name
Test status
Simulation time 342354614527 ps
CPU time 2623.62 seconds
Started Apr 15 12:24:51 PM PDT 24
Finished Apr 15 01:08:35 PM PDT 24
Peak memory 190792 kb
Host smart-cb0d525c-a295-4f57-9859-a48cabebd3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411856276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1411856276
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.501401659
Short name T243
Test name
Test status
Simulation time 1957616956516 ps
CPU time 4812.12 seconds
Started Apr 15 12:24:25 PM PDT 24
Finished Apr 15 01:44:38 PM PDT 24
Peak memory 193892 kb
Host smart-82c20519-b430-493a-b811-471dad027c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501401659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
501401659
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2049166845
Short name T125
Test name
Test status
Simulation time 397783129040 ps
CPU time 739.49 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 182456 kb
Host smart-761630eb-3ab3-4bea-a893-75691e98adab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049166845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2049166845
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2363217811
Short name T174
Test name
Test status
Simulation time 859230036639 ps
CPU time 2108.62 seconds
Started Apr 15 12:24:36 PM PDT 24
Finished Apr 15 12:59:45 PM PDT 24
Peak memory 190712 kb
Host smart-762886d5-1fe3-4651-8713-99d8b0159883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363217811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2363217811
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.919606704
Short name T144
Test name
Test status
Simulation time 6181389665301 ps
CPU time 1825.36 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:54:54 PM PDT 24
Peak memory 190676 kb
Host smart-fd741249-96f4-49d2-884e-279f9059b246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919606704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.919606704
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3111856497
Short name T17
Test name
Test status
Simulation time 35634564 ps
CPU time 0.74 seconds
Started Apr 15 12:24:23 PM PDT 24
Finished Apr 15 12:24:24 PM PDT 24
Peak memory 213596 kb
Host smart-dad5d60b-4933-471e-92af-c13a0fe7281d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111856497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3111856497
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1495251461
Short name T108
Test name
Test status
Simulation time 1001682796343 ps
CPU time 2715.05 seconds
Started Apr 15 12:24:50 PM PDT 24
Finished Apr 15 01:10:06 PM PDT 24
Peak memory 196000 kb
Host smart-00d93022-7dd7-40be-a9bf-65c59c511244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495251461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1495251461
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2734522539
Short name T35
Test name
Test status
Simulation time 291444577 ps
CPU time 0.73 seconds
Started Apr 15 12:19:57 PM PDT 24
Finished Apr 15 12:19:59 PM PDT 24
Peak memory 193144 kb
Host smart-2d863f34-7419-49cf-b665-309742d7a48f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734522539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2734522539
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1789958925
Short name T198
Test name
Test status
Simulation time 2839817173481 ps
CPU time 948.82 seconds
Started Apr 15 12:24:37 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 190668 kb
Host smart-7e6a4fac-baff-4dd5-b825-30c45fb9dd3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789958925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1789958925
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random.2174014777
Short name T9
Test name
Test status
Simulation time 89776838673 ps
CPU time 154.33 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:27:16 PM PDT 24
Peak memory 190596 kb
Host smart-f2f7dc49-feca-40f1-8193-129dac9e8c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174014777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2174014777
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2889670176
Short name T152
Test name
Test status
Simulation time 743601833161 ps
CPU time 2344.54 seconds
Started Apr 15 12:24:51 PM PDT 24
Finished Apr 15 01:03:57 PM PDT 24
Peak memory 192736 kb
Host smart-fa47cbc1-458c-4c41-b182-461416041e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889670176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2889670176
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3410714617
Short name T137
Test name
Test status
Simulation time 560566712049 ps
CPU time 1066.31 seconds
Started Apr 15 12:26:10 PM PDT 24
Finished Apr 15 12:43:57 PM PDT 24
Peak memory 190132 kb
Host smart-12f6c7fe-7897-4651-9a2c-9393b0e5e577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410714617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3410714617
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1655509522
Short name T159
Test name
Test status
Simulation time 318769105148 ps
CPU time 325.44 seconds
Started Apr 15 12:25:14 PM PDT 24
Finished Apr 15 12:30:40 PM PDT 24
Peak memory 190700 kb
Host smart-622dc822-f6fa-4261-b33b-c1fc97f6a117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655509522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1655509522
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2493858574
Short name T115
Test name
Test status
Simulation time 909208294596 ps
CPU time 249.53 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:29:22 PM PDT 24
Peak memory 190660 kb
Host smart-eb2f9b35-4a75-4128-8edd-acd2d1fba505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493858574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2493858574
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2426542970
Short name T230
Test name
Test status
Simulation time 305559354618 ps
CPU time 1373.93 seconds
Started Apr 15 12:24:59 PM PDT 24
Finished Apr 15 12:47:54 PM PDT 24
Peak memory 190608 kb
Host smart-99303403-c264-4ee5-8bab-629a2e63d785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426542970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2426542970
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1688083300
Short name T172
Test name
Test status
Simulation time 216924234467 ps
CPU time 602.25 seconds
Started Apr 15 12:25:18 PM PDT 24
Finished Apr 15 12:35:21 PM PDT 24
Peak memory 190700 kb
Host smart-59ab478f-003e-41cb-99a9-b2c3b0852feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688083300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1688083300
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.848306833
Short name T205
Test name
Test status
Simulation time 5045337355787 ps
CPU time 1296.88 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:46:08 PM PDT 24
Peak memory 190784 kb
Host smart-11c8bbc8-1419-430c-8d94-31e36b8bd3f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848306833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
848306833
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3438269105
Short name T326
Test name
Test status
Simulation time 1007501616592 ps
CPU time 2402.16 seconds
Started Apr 15 12:24:38 PM PDT 24
Finished Apr 15 01:04:41 PM PDT 24
Peak memory 195244 kb
Host smart-fc103abc-ebb9-4796-ae7e-e7ed4af083b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438269105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3438269105
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/194.rv_timer_random.876837119
Short name T216
Test name
Test status
Simulation time 107107334744 ps
CPU time 255.09 seconds
Started Apr 15 12:25:14 PM PDT 24
Finished Apr 15 12:29:29 PM PDT 24
Peak memory 190700 kb
Host smart-801d7c54-785f-4a0e-b010-22c6e8847ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876837119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.876837119
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3069753864
Short name T212
Test name
Test status
Simulation time 2838217815840 ps
CPU time 756.83 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:37:04 PM PDT 24
Peak memory 190688 kb
Host smart-90186a27-c923-4c30-8164-c9c10b720874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069753864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3069753864
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/79.rv_timer_random.2781708724
Short name T109
Test name
Test status
Simulation time 758700982914 ps
CPU time 276.22 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:29:27 PM PDT 24
Peak memory 190708 kb
Host smart-a0231c7a-79ff-4ded-b003-f84144d5c300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781708724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2781708724
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3262176997
Short name T103
Test name
Test status
Simulation time 997287716119 ps
CPU time 1513.6 seconds
Started Apr 15 12:25:02 PM PDT 24
Finished Apr 15 12:50:16 PM PDT 24
Peak memory 190364 kb
Host smart-c36a6ca0-89a1-4015-806c-e47138763a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262176997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3262176997
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.524863575
Short name T209
Test name
Test status
Simulation time 1518784806818 ps
CPU time 829.61 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 190700 kb
Host smart-4509e03d-3de2-4b79-9889-1919e9e459b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524863575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
524863575
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_random.3979409824
Short name T179
Test name
Test status
Simulation time 177217879154 ps
CPU time 302.07 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:29:36 PM PDT 24
Peak memory 182516 kb
Host smart-c1dcb77a-b186-4c5d-a1df-ee0e992113a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979409824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3979409824
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1762277169
Short name T127
Test name
Test status
Simulation time 152514868192 ps
CPU time 82.99 seconds
Started Apr 15 12:25:19 PM PDT 24
Finished Apr 15 12:26:42 PM PDT 24
Peak memory 190696 kb
Host smart-5b1f8e52-0d46-45a2-8ae1-218a96abe5f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762277169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1762277169
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3883676001
Short name T52
Test name
Test status
Simulation time 424114030068 ps
CPU time 393.46 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:31:04 PM PDT 24
Peak memory 190708 kb
Host smart-64714ce3-f276-43c6-8e6a-6dcabffebe44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883676001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3883676001
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3983128136
Short name T82
Test name
Test status
Simulation time 447688562 ps
CPU time 1.45 seconds
Started Apr 15 12:20:05 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 191932 kb
Host smart-14b531db-3829-4702-94df-1638c90f8e45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983128136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3983128136
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/106.rv_timer_random.2341991872
Short name T135
Test name
Test status
Simulation time 106058258765 ps
CPU time 276.15 seconds
Started Apr 15 12:26:20 PM PDT 24
Finished Apr 15 12:30:56 PM PDT 24
Peak memory 190268 kb
Host smart-4dae2fea-2ac9-48b9-bd69-cce98fdc7642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341991872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2341991872
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.2891725941
Short name T286
Test name
Test status
Simulation time 146594101017 ps
CPU time 491.16 seconds
Started Apr 15 12:25:06 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 190692 kb
Host smart-2a4c3ca7-2d03-4404-b02e-a6e27af5bb22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891725941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2891725941
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2120062441
Short name T10
Test name
Test status
Simulation time 428538331279 ps
CPU time 216.78 seconds
Started Apr 15 12:25:10 PM PDT 24
Finished Apr 15 12:28:48 PM PDT 24
Peak memory 190708 kb
Host smart-7ec56af7-1cca-4d54-8fe7-5e3b24b201ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120062441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2120062441
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.747294746
Short name T156
Test name
Test status
Simulation time 453924565016 ps
CPU time 803.56 seconds
Started Apr 15 12:25:14 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 190692 kb
Host smart-3cbf28cc-c1d2-43c4-a298-a0c7ef0a1231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747294746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.747294746
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.918774575
Short name T113
Test name
Test status
Simulation time 384631903864 ps
CPU time 384.43 seconds
Started Apr 15 12:25:19 PM PDT 24
Finished Apr 15 12:31:44 PM PDT 24
Peak memory 190692 kb
Host smart-bb3e6e98-efef-4947-8ae6-b53c310217fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918774575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.918774575
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4280413372
Short name T175
Test name
Test status
Simulation time 480260203714 ps
CPU time 683.25 seconds
Started Apr 15 12:24:49 PM PDT 24
Finished Apr 15 12:36:13 PM PDT 24
Peak memory 190716 kb
Host smart-fa3377b7-a6f3-48ef-becb-85d633dd1048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280413372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4280413372
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/76.rv_timer_random.241042140
Short name T328
Test name
Test status
Simulation time 81437241311 ps
CPU time 383.62 seconds
Started Apr 15 12:24:58 PM PDT 24
Finished Apr 15 12:31:22 PM PDT 24
Peak memory 190664 kb
Host smart-3ee60212-9898-4b52-b48f-22b7586ad13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241042140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.241042140
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.980805407
Short name T226
Test name
Test status
Simulation time 525206980544 ps
CPU time 294.15 seconds
Started Apr 15 12:25:09 PM PDT 24
Finished Apr 15 12:30:04 PM PDT 24
Peak memory 190716 kb
Host smart-056a38b6-1bb2-44af-a95e-4a2a950fed97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980805407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.980805407
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.4050789180
Short name T245
Test name
Test status
Simulation time 1483977718770 ps
CPU time 281.97 seconds
Started Apr 15 12:25:14 PM PDT 24
Finished Apr 15 12:29:57 PM PDT 24
Peak memory 190680 kb
Host smart-2bc5471a-4a93-4414-a35b-4aad9ea657aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050789180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.4050789180
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2123261016
Short name T177
Test name
Test status
Simulation time 68140679016 ps
CPU time 180.02 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:28:13 PM PDT 24
Peak memory 190680 kb
Host smart-345656f1-90d3-4a9f-9ea4-7fb38d72931f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123261016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2123261016
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1666731310
Short name T222
Test name
Test status
Simulation time 1354442090220 ps
CPU time 1038.98 seconds
Started Apr 15 12:24:33 PM PDT 24
Finished Apr 15 12:41:53 PM PDT 24
Peak memory 190696 kb
Host smart-5287000e-2502-4e04-8760-d3bb0db54cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666731310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1666731310
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1967261354
Short name T110
Test name
Test status
Simulation time 156604523204 ps
CPU time 251.49 seconds
Started Apr 15 12:24:25 PM PDT 24
Finished Apr 15 12:28:37 PM PDT 24
Peak memory 190724 kb
Host smart-97ee129a-1bf2-4944-aeeb-a797fa921ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967261354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1967261354
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.621079823
Short name T182
Test name
Test status
Simulation time 169193373813 ps
CPU time 886.58 seconds
Started Apr 15 12:24:51 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 190684 kb
Host smart-c69d0513-163e-4795-b6b0-4890fa766583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621079823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.621079823
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.984301386
Short name T123
Test name
Test status
Simulation time 402237655659 ps
CPU time 799.28 seconds
Started Apr 15 12:25:02 PM PDT 24
Finished Apr 15 12:38:22 PM PDT 24
Peak memory 190272 kb
Host smart-86edaa34-83c3-4b98-82e8-c988f08e32d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984301386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.984301386
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.4017288526
Short name T141
Test name
Test status
Simulation time 133588753256 ps
CPU time 313.81 seconds
Started Apr 15 12:26:10 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 188356 kb
Host smart-09c93931-a8ac-4708-bc72-ceee4afb5530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017288526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.4017288526
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.420461053
Short name T101
Test name
Test status
Simulation time 526104121548 ps
CPU time 793.92 seconds
Started Apr 15 12:25:01 PM PDT 24
Finished Apr 15 12:38:16 PM PDT 24
Peak memory 190716 kb
Host smart-bd7dbedb-3209-4e4e-bedd-627bccd431a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420461053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.420461053
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1573916990
Short name T258
Test name
Test status
Simulation time 58633968502 ps
CPU time 102.58 seconds
Started Apr 15 12:25:40 PM PDT 24
Finished Apr 15 12:27:23 PM PDT 24
Peak memory 190700 kb
Host smart-083d76f4-0538-494b-a0d8-608c7a95df8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573916990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1573916990
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.3229987043
Short name T99
Test name
Test status
Simulation time 590753634888 ps
CPU time 340.27 seconds
Started Apr 15 12:25:16 PM PDT 24
Finished Apr 15 12:30:56 PM PDT 24
Peak memory 193912 kb
Host smart-9b6a73ca-7030-495d-bb1d-1aeb0146cd29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229987043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3229987043
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1612741492
Short name T196
Test name
Test status
Simulation time 78704771116 ps
CPU time 322.94 seconds
Started Apr 15 12:25:15 PM PDT 24
Finished Apr 15 12:30:39 PM PDT 24
Peak memory 190676 kb
Host smart-0754e795-3e74-4301-a970-0f1e74e47f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612741492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1612741492
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.3165339341
Short name T157
Test name
Test status
Simulation time 213956755862 ps
CPU time 797.06 seconds
Started Apr 15 12:24:34 PM PDT 24
Finished Apr 15 12:37:52 PM PDT 24
Peak memory 190696 kb
Host smart-3b2f421d-ac1a-4712-bbd5-7f29c0c05c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165339341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3165339341
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3222363743
Short name T303
Test name
Test status
Simulation time 114621637766 ps
CPU time 323.66 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:30:00 PM PDT 24
Peak memory 190708 kb
Host smart-2643fab9-24fc-4956-bbfa-e866075f7f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222363743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3222363743
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/62.rv_timer_random.3066120202
Short name T158
Test name
Test status
Simulation time 279152123631 ps
CPU time 406.87 seconds
Started Apr 15 12:26:10 PM PDT 24
Finished Apr 15 12:32:57 PM PDT 24
Peak memory 189440 kb
Host smart-3b1272f4-abe4-47f7-867e-fd16ea70063f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066120202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3066120202
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1950760232
Short name T148
Test name
Test status
Simulation time 55689152607 ps
CPU time 98.72 seconds
Started Apr 15 12:25:00 PM PDT 24
Finished Apr 15 12:26:39 PM PDT 24
Peak memory 190756 kb
Host smart-2e8ae617-2e93-4f1a-ad37-c784e768000b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950760232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1950760232
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.902330861
Short name T93
Test name
Test status
Simulation time 275171834 ps
CPU time 1.14 seconds
Started Apr 15 12:20:08 PM PDT 24
Finished Apr 15 12:20:11 PM PDT 24
Peak memory 195120 kb
Host smart-48d53086-f661-4c36-a685-722050aaf690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902330861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.902330861
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_timer_random.1279228528
Short name T237
Test name
Test status
Simulation time 376071619578 ps
CPU time 225.18 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:28:14 PM PDT 24
Peak memory 190684 kb
Host smart-66ea6e60-e132-4c80-8ac5-b42708717a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279228528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1279228528
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1280470468
Short name T273
Test name
Test status
Simulation time 77047451538 ps
CPU time 117.27 seconds
Started Apr 15 12:25:06 PM PDT 24
Finished Apr 15 12:27:04 PM PDT 24
Peak memory 194400 kb
Host smart-d5346973-744c-4415-a1ac-cf73e32e0624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280470468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1280470468
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1411259928
Short name T250
Test name
Test status
Simulation time 34207628957 ps
CPU time 48.71 seconds
Started Apr 15 12:25:09 PM PDT 24
Finished Apr 15 12:25:58 PM PDT 24
Peak memory 190712 kb
Host smart-c150c2f7-5583-440f-8b92-c5df0b559f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411259928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1411259928
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3753437771
Short name T343
Test name
Test status
Simulation time 64043924700 ps
CPU time 1036.41 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:42:29 PM PDT 24
Peak memory 190668 kb
Host smart-a57299b4-30f1-4d96-8a8b-7e20e083af2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753437771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3753437771
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2854592114
Short name T132
Test name
Test status
Simulation time 60265394666 ps
CPU time 357.71 seconds
Started Apr 15 12:25:18 PM PDT 24
Finished Apr 15 12:31:17 PM PDT 24
Peak memory 182364 kb
Host smart-e9e70374-ef1a-4628-ab6b-5f90c38055cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854592114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2854592114
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4063056195
Short name T66
Test name
Test status
Simulation time 2250931391204 ps
CPU time 1551.53 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:50:22 PM PDT 24
Peak memory 190784 kb
Host smart-add2387b-41ec-4077-ba75-58a3d0c462f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063056195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4063056195
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.821983972
Short name T299
Test name
Test status
Simulation time 195247862452 ps
CPU time 92.87 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:26:04 PM PDT 24
Peak memory 190688 kb
Host smart-b163629e-fa9e-4280-9b8e-fa5e460bfff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821983972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.821983972
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_random.2989136313
Short name T47
Test name
Test status
Simulation time 148946534422 ps
CPU time 561 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:33:54 PM PDT 24
Peak memory 193312 kb
Host smart-f6ade15e-a10c-43c0-8b93-de982de038c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989136313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2989136313
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3146079081
Short name T163
Test name
Test status
Simulation time 613849463420 ps
CPU time 1375.4 seconds
Started Apr 15 12:26:11 PM PDT 24
Finished Apr 15 12:49:07 PM PDT 24
Peak memory 190288 kb
Host smart-96aa316f-67bf-4854-963e-da85a089c54b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146079081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3146079081
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.240880523
Short name T298
Test name
Test status
Simulation time 665514733029 ps
CPU time 366.87 seconds
Started Apr 15 12:24:52 PM PDT 24
Finished Apr 15 12:30:59 PM PDT 24
Peak memory 190716 kb
Host smart-d57cffe3-807a-4060-902d-a0017394e5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240880523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.240880523
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1137845918
Short name T562
Test name
Test status
Simulation time 785501509 ps
CPU time 0.82 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:11 PM PDT 24
Peak memory 192620 kb
Host smart-fe199b44-5d38-4034-b95f-f1074aea3764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137845918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1137845918
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3477618950
Short name T310
Test name
Test status
Simulation time 638624924918 ps
CPU time 374.27 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 182548 kb
Host smart-0d02dbab-3adc-4986-8e54-ef6fee7255c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477618950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3477618950
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3322670699
Short name T395
Test name
Test status
Simulation time 16886260937 ps
CPU time 17.19 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:24:45 PM PDT 24
Peak memory 182464 kb
Host smart-db81565e-63b1-4092-b072-54fb298d2897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322670699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3322670699
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/104.rv_timer_random.659941578
Short name T287
Test name
Test status
Simulation time 120141319064 ps
CPU time 211.73 seconds
Started Apr 15 12:25:04 PM PDT 24
Finished Apr 15 12:28:36 PM PDT 24
Peak memory 190676 kb
Host smart-bdd7fdae-3af3-4300-88ff-0d01ed822f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659941578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.659941578
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3278524335
Short name T139
Test name
Test status
Simulation time 539036364343 ps
CPU time 1629.9 seconds
Started Apr 15 12:26:10 PM PDT 24
Finished Apr 15 12:53:20 PM PDT 24
Peak memory 188396 kb
Host smart-ddccaeb2-e9e3-444e-a2ea-d8b1aa35f73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278524335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3278524335
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3349101494
Short name T331
Test name
Test status
Simulation time 7054186744 ps
CPU time 4.41 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:24:38 PM PDT 24
Peak memory 182448 kb
Host smart-ff64a6f5-3c0c-4b2f-84d9-d297f0af7149
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349101494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3349101494
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/117.rv_timer_random.4232068059
Short name T153
Test name
Test status
Simulation time 506647519170 ps
CPU time 991.63 seconds
Started Apr 15 12:24:58 PM PDT 24
Finished Apr 15 12:41:30 PM PDT 24
Peak memory 190768 kb
Host smart-4ee8a695-17aa-44af-9e86-522742d8c3e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232068059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4232068059
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3764073506
Short name T313
Test name
Test status
Simulation time 73794633857 ps
CPU time 112.29 seconds
Started Apr 15 12:25:01 PM PDT 24
Finished Apr 15 12:26:54 PM PDT 24
Peak memory 190704 kb
Host smart-c1ffff66-d3cf-4e66-b3d7-0c8c62040e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764073506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3764073506
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.597120885
Short name T204
Test name
Test status
Simulation time 518481609615 ps
CPU time 1429.79 seconds
Started Apr 15 12:25:04 PM PDT 24
Finished Apr 15 12:48:54 PM PDT 24
Peak memory 190696 kb
Host smart-9c691b99-a43f-48d1-8a3f-b087bcb53e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597120885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.597120885
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.2316043823
Short name T352
Test name
Test status
Simulation time 55778181445 ps
CPU time 113 seconds
Started Apr 15 12:24:33 PM PDT 24
Finished Apr 15 12:26:32 PM PDT 24
Peak memory 182452 kb
Host smart-419805f3-fdf1-4318-9103-74a9818a40d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316043823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2316043823
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3755210315
Short name T102
Test name
Test status
Simulation time 24954787082 ps
CPU time 41.28 seconds
Started Apr 15 12:26:20 PM PDT 24
Finished Apr 15 12:27:02 PM PDT 24
Peak memory 190616 kb
Host smart-b00d8f80-0377-473e-add4-18188f083ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755210315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3755210315
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1225694248
Short name T241
Test name
Test status
Simulation time 82467876792 ps
CPU time 136.94 seconds
Started Apr 15 12:25:15 PM PDT 24
Finished Apr 15 12:27:33 PM PDT 24
Peak memory 190676 kb
Host smart-7f67dcc9-dc3f-4373-b28c-b1aa52e9eaf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225694248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1225694248
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3503532904
Short name T355
Test name
Test status
Simulation time 37780264113 ps
CPU time 61.97 seconds
Started Apr 15 12:25:13 PM PDT 24
Finished Apr 15 12:26:16 PM PDT 24
Peak memory 182488 kb
Host smart-b1b51055-85b9-4a1e-b3e8-0ed9a4051c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503532904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3503532904
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.519129760
Short name T45
Test name
Test status
Simulation time 59938510734 ps
CPU time 179.36 seconds
Started Apr 15 12:25:10 PM PDT 24
Finished Apr 15 12:28:10 PM PDT 24
Peak memory 190704 kb
Host smart-4ecb769d-79fd-45d6-bc73-e9f375d923e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519129760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.519129760
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1395016753
Short name T185
Test name
Test status
Simulation time 142043936174 ps
CPU time 221.28 seconds
Started Apr 15 12:25:15 PM PDT 24
Finished Apr 15 12:28:57 PM PDT 24
Peak memory 190688 kb
Host smart-60842677-972c-49b5-b405-0aa8db10ad7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395016753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1395016753
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.727623953
Short name T1
Test name
Test status
Simulation time 99245276851 ps
CPU time 403.87 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:31:56 PM PDT 24
Peak memory 190668 kb
Host smart-1f2d5108-d132-4978-a543-4bd14f0f8e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727623953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.727623953
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.421946683
Short name T262
Test name
Test status
Simulation time 122763015392 ps
CPU time 104.25 seconds
Started Apr 15 12:25:17 PM PDT 24
Finished Apr 15 12:27:02 PM PDT 24
Peak memory 190712 kb
Host smart-5a491a84-1678-4e4e-825f-a96bb5d0450c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421946683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.421946683
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3710747856
Short name T357
Test name
Test status
Simulation time 85033548687 ps
CPU time 148.84 seconds
Started Apr 15 12:25:11 PM PDT 24
Finished Apr 15 12:27:40 PM PDT 24
Peak memory 193000 kb
Host smart-820e22c6-3758-4da7-8060-a020429a7843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710747856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3710747856
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.3422667777
Short name T236
Test name
Test status
Simulation time 183265945542 ps
CPU time 163.94 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:27:57 PM PDT 24
Peak memory 191000 kb
Host smart-f4e7d935-157c-42cf-95ff-c7d834b8203b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422667777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3422667777
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.669334977
Short name T439
Test name
Test status
Simulation time 391897982166 ps
CPU time 584.52 seconds
Started Apr 15 12:24:25 PM PDT 24
Finished Apr 15 12:34:10 PM PDT 24
Peak memory 182488 kb
Host smart-410bc55c-fd0c-407e-878a-ea600b6c2c45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669334977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.669334977
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4154528687
Short name T149
Test name
Test status
Simulation time 566698799599 ps
CPU time 766.59 seconds
Started Apr 15 12:24:33 PM PDT 24
Finished Apr 15 12:37:21 PM PDT 24
Peak memory 194284 kb
Host smart-a16c0b3b-b499-4de2-adaf-8ab36098f8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154528687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4154528687
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1380848895
Short name T200
Test name
Test status
Simulation time 25130432581 ps
CPU time 46.73 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:25:28 PM PDT 24
Peak memory 182504 kb
Host smart-9c24f997-66bb-4308-a4fe-13e2e885ca90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380848895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1380848895
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.2434749859
Short name T170
Test name
Test status
Simulation time 379763601168 ps
CPU time 200.79 seconds
Started Apr 15 12:24:37 PM PDT 24
Finished Apr 15 12:27:58 PM PDT 24
Peak memory 190708 kb
Host smart-e8f384fc-2798-43af-8a69-3b86e271a576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434749859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2434749859
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2342280394
Short name T238
Test name
Test status
Simulation time 287497013552 ps
CPU time 161.56 seconds
Started Apr 15 12:24:36 PM PDT 24
Finished Apr 15 12:27:18 PM PDT 24
Peak memory 182504 kb
Host smart-0a464c71-41d4-4442-a911-2ed0266634fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342280394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2342280394
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random.2606303378
Short name T263
Test name
Test status
Simulation time 138233115272 ps
CPU time 447.94 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:32:04 PM PDT 24
Peak memory 192976 kb
Host smart-e66b66d2-f194-4fd9-b8d1-c40ba5166867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606303378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2606303378
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.774651443
Short name T173
Test name
Test status
Simulation time 1741213897053 ps
CPU time 901.49 seconds
Started Apr 15 12:24:22 PM PDT 24
Finished Apr 15 12:39:24 PM PDT 24
Peak memory 182504 kb
Host smart-97dcc319-0b26-46ec-bf58-e40b33c8c376
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774651443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.774651443
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/64.rv_timer_random.2339426643
Short name T267
Test name
Test status
Simulation time 208772631254 ps
CPU time 429.79 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:31:53 PM PDT 24
Peak memory 190600 kb
Host smart-1438c6b0-15bd-499d-9ea4-abba696a1ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339426643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2339426643
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2076229585
Short name T317
Test name
Test status
Simulation time 370359904554 ps
CPU time 152.77 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:27:03 PM PDT 24
Peak memory 190704 kb
Host smart-3a336476-2681-4ae9-8356-64e81bc9a2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076229585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2076229585
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/88.rv_timer_random.3334910585
Short name T290
Test name
Test status
Simulation time 99946830441 ps
CPU time 278.14 seconds
Started Apr 15 12:25:04 PM PDT 24
Finished Apr 15 12:29:43 PM PDT 24
Peak memory 190684 kb
Host smart-23bf204e-3829-4e67-a6c2-954fcf8bea66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334910585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3334910585
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3401738099
Short name T75
Test name
Test status
Simulation time 70400064 ps
CPU time 0.59 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:12 PM PDT 24
Peak memory 182512 kb
Host smart-42df55ff-45e3-4c18-9066-713f23a7864f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401738099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3401738099
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2702074941
Short name T502
Test name
Test status
Simulation time 40331161 ps
CPU time 0.56 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:07 PM PDT 24
Peak memory 181996 kb
Host smart-27bcd1b9-9fe7-4af6-ad25-c9cabc6fcc2e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702074941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2702074941
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2363097628
Short name T576
Test name
Test status
Simulation time 24634710 ps
CPU time 0.7 seconds
Started Apr 15 12:19:52 PM PDT 24
Finished Apr 15 12:19:56 PM PDT 24
Peak memory 194600 kb
Host smart-89356968-3985-49b8-b7f1-47997149c52f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363097628 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2363097628
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3601768938
Short name T76
Test name
Test status
Simulation time 49757011 ps
CPU time 0.6 seconds
Started Apr 15 12:20:24 PM PDT 24
Finished Apr 15 12:20:25 PM PDT 24
Peak memory 182548 kb
Host smart-a84b2246-2ce9-4bfb-b8a8-cef73f29dfba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601768938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3601768938
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1317376110
Short name T574
Test name
Test status
Simulation time 108854186 ps
CPU time 0.57 seconds
Started Apr 15 12:19:55 PM PDT 24
Finished Apr 15 12:19:58 PM PDT 24
Peak memory 182148 kb
Host smart-f6af20cc-ec52-4866-a4f7-9c87c1d8e0e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317376110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1317376110
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1099221084
Short name T88
Test name
Test status
Simulation time 15256034 ps
CPU time 0.6 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:18 PM PDT 24
Peak memory 191784 kb
Host smart-2d78d51c-3cf7-4ef3-8ac8-ef0142db32b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099221084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1099221084
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2700140896
Short name T524
Test name
Test status
Simulation time 62460672 ps
CPU time 1.21 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 197404 kb
Host smart-4c6dcf3e-1d95-4b80-aa6a-afc204e7f203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700140896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2700140896
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2629687443
Short name T30
Test name
Test status
Simulation time 272754181 ps
CPU time 0.75 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:14 PM PDT 24
Peak memory 183072 kb
Host smart-abde0172-4c52-4042-a675-a9976f50e286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629687443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2629687443
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3407436446
Short name T555
Test name
Test status
Simulation time 24799584 ps
CPU time 0.7 seconds
Started Apr 15 12:20:07 PM PDT 24
Finished Apr 15 12:20:09 PM PDT 24
Peak memory 192200 kb
Host smart-22e87e08-30a3-4042-b908-6eabccef3a26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407436446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3407436446
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3934409714
Short name T507
Test name
Test status
Simulation time 289313524 ps
CPU time 3.66 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 193792 kb
Host smart-6826fbc5-dd46-4452-bb6a-f27adac53ff6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934409714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3934409714
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.159830599
Short name T472
Test name
Test status
Simulation time 21747682 ps
CPU time 0.59 seconds
Started Apr 15 12:20:03 PM PDT 24
Finished Apr 15 12:20:04 PM PDT 24
Peak memory 182520 kb
Host smart-f76a744e-08c7-4573-87bc-a8be66190e7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159830599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.159830599
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.70257683
Short name T501
Test name
Test status
Simulation time 53382315 ps
CPU time 0.92 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 197176 kb
Host smart-e417eff9-fa37-40fe-a2c1-7e39ccc98d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70257683 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.70257683
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.989831176
Short name T526
Test name
Test status
Simulation time 12622765 ps
CPU time 0.54 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:12 PM PDT 24
Peak memory 182528 kb
Host smart-c55fcdee-6531-4d6e-b5c8-6a7c98108883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989831176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.989831176
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3583276995
Short name T515
Test name
Test status
Simulation time 25208114 ps
CPU time 0.54 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 182368 kb
Host smart-b5893be8-b5fa-48b0-b943-82d423b8d74a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583276995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3583276995
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2612069658
Short name T488
Test name
Test status
Simulation time 115255943 ps
CPU time 1.51 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 197396 kb
Host smart-a2d0c7f6-6d27-4233-a9f3-4050106ce3e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612069658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2612069658
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.153501182
Short name T525
Test name
Test status
Simulation time 22510290 ps
CPU time 0.76 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 195244 kb
Host smart-3118ec6b-381c-43bc-b300-52229f1be349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153501182 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.153501182
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.437074076
Short name T541
Test name
Test status
Simulation time 15290639 ps
CPU time 0.59 seconds
Started Apr 15 12:20:03 PM PDT 24
Finished Apr 15 12:20:04 PM PDT 24
Peak memory 182480 kb
Host smart-5793021b-ecb2-415d-9b73-c9f1800340b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437074076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.437074076
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.812397917
Short name T580
Test name
Test status
Simulation time 71726547 ps
CPU time 0.55 seconds
Started Apr 15 12:20:07 PM PDT 24
Finished Apr 15 12:20:09 PM PDT 24
Peak memory 182436 kb
Host smart-6b3ceb0b-ee7e-4812-94a8-52f964cf328f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812397917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.812397917
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1330219516
Short name T573
Test name
Test status
Simulation time 68759450 ps
CPU time 0.61 seconds
Started Apr 15 12:20:08 PM PDT 24
Finished Apr 15 12:20:10 PM PDT 24
Peak memory 191316 kb
Host smart-51419086-2718-4056-b47a-0463c44ce5f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330219516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1330219516
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1067149035
Short name T561
Test name
Test status
Simulation time 223582054 ps
CPU time 1.29 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 196992 kb
Host smart-7f82ef1b-8c08-489c-b150-7992b01d080d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067149035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1067149035
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.155036009
Short name T95
Test name
Test status
Simulation time 273711682 ps
CPU time 1.43 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 195260 kb
Host smart-157482eb-0a5e-4708-9b76-0ea0e98791b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155036009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.155036009
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2443208713
Short name T34
Test name
Test status
Simulation time 35547693 ps
CPU time 0.62 seconds
Started Apr 15 12:20:05 PM PDT 24
Finished Apr 15 12:20:07 PM PDT 24
Peak memory 193136 kb
Host smart-503da743-9655-4659-b8dd-46a642e3f9c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443208713 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2443208713
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2056351849
Short name T572
Test name
Test status
Simulation time 86310645 ps
CPU time 0.61 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 182620 kb
Host smart-684f3e8d-9fad-4c0e-8af4-6e34abae6d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056351849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2056351849
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1448778837
Short name T495
Test name
Test status
Simulation time 45491466 ps
CPU time 0.54 seconds
Started Apr 15 12:20:16 PM PDT 24
Finished Apr 15 12:20:18 PM PDT 24
Peak memory 182368 kb
Host smart-d49233e6-307b-465a-b32a-996a1794266d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448778837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1448778837
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2725788532
Short name T534
Test name
Test status
Simulation time 117010386 ps
CPU time 0.79 seconds
Started Apr 15 12:20:18 PM PDT 24
Finished Apr 15 12:20:20 PM PDT 24
Peak memory 191476 kb
Host smart-819155f7-1592-492d-bce1-005b075680f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725788532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2725788532
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.763242660
Short name T463
Test name
Test status
Simulation time 463981616 ps
CPU time 2.46 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:16 PM PDT 24
Peak memory 197404 kb
Host smart-c322c1ba-d03b-4b79-864b-6736aabc1d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763242660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.763242660
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4176236821
Short name T552
Test name
Test status
Simulation time 26642633 ps
CPU time 1.21 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 197392 kb
Host smart-b0def66f-f009-4e64-8c37-7ac0cc431733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176236821 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.4176236821
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2255201099
Short name T535
Test name
Test status
Simulation time 13516082 ps
CPU time 0.59 seconds
Started Apr 15 12:20:05 PM PDT 24
Finished Apr 15 12:20:07 PM PDT 24
Peak memory 182620 kb
Host smart-ee693c4e-5c5a-4d33-81e4-98a7a24058c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255201099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2255201099
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.997147192
Short name T477
Test name
Test status
Simulation time 115377377 ps
CPU time 0.54 seconds
Started Apr 15 12:20:07 PM PDT 24
Finished Apr 15 12:20:09 PM PDT 24
Peak memory 182384 kb
Host smart-643719a0-e4f6-431f-b9fa-b9e742109f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997147192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.997147192
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2016184581
Short name T87
Test name
Test status
Simulation time 84660542 ps
CPU time 0.6 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 191688 kb
Host smart-a763e9d4-2b00-4e60-a031-c5b663efe4d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016184581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2016184581
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2653188702
Short name T510
Test name
Test status
Simulation time 237890285 ps
CPU time 2.08 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 197388 kb
Host smart-b91e17f3-65af-418c-be02-a18250f0dd84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653188702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2653188702
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1340501519
Short name T537
Test name
Test status
Simulation time 40931734 ps
CPU time 0.74 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:14 PM PDT 24
Peak memory 195192 kb
Host smart-32544354-89bd-4ebf-bc77-b58da5ed6506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340501519 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1340501519
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3341730107
Short name T71
Test name
Test status
Simulation time 37346824 ps
CPU time 0.57 seconds
Started Apr 15 12:20:37 PM PDT 24
Finished Apr 15 12:20:38 PM PDT 24
Peak memory 182532 kb
Host smart-73e4685e-4fb2-4607-ad3c-a9de6afd2083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341730107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3341730107
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2185287886
Short name T546
Test name
Test status
Simulation time 43806568 ps
CPU time 0.56 seconds
Started Apr 15 12:20:07 PM PDT 24
Finished Apr 15 12:20:09 PM PDT 24
Peak memory 181828 kb
Host smart-a3c36ed5-7792-4c94-aec9-f1d3abaa2a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185287886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2185287886
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.299210714
Short name T73
Test name
Test status
Simulation time 192995061 ps
CPU time 0.71 seconds
Started Apr 15 12:20:08 PM PDT 24
Finished Apr 15 12:20:10 PM PDT 24
Peak memory 191056 kb
Host smart-72414598-9727-4149-9125-58eb85fbe880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299210714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.299210714
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1457238452
Short name T566
Test name
Test status
Simulation time 187761898 ps
CPU time 2.91 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:14 PM PDT 24
Peak memory 197112 kb
Host smart-3a7928e5-56bc-4876-8330-9d633fd7bc64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457238452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1457238452
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3561503652
Short name T571
Test name
Test status
Simulation time 147438341 ps
CPU time 1.36 seconds
Started Apr 15 12:20:20 PM PDT 24
Finished Apr 15 12:20:22 PM PDT 24
Peak memory 183176 kb
Host smart-22ae1563-3d4d-48f3-be66-40423a81412c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561503652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3561503652
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1537966060
Short name T578
Test name
Test status
Simulation time 162102160 ps
CPU time 0.95 seconds
Started Apr 15 12:20:08 PM PDT 24
Finished Apr 15 12:20:10 PM PDT 24
Peak memory 196632 kb
Host smart-4a068471-70f1-45d9-bd30-93a59f39023f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537966060 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1537966060
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1982556912
Short name T80
Test name
Test status
Simulation time 28489875 ps
CPU time 0.57 seconds
Started Apr 15 12:20:16 PM PDT 24
Finished Apr 15 12:20:18 PM PDT 24
Peak memory 182532 kb
Host smart-26de4f9b-fd5d-489e-9004-30704f77d40e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982556912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1982556912
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.436325253
Short name T575
Test name
Test status
Simulation time 21882983 ps
CPU time 0.6 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 182388 kb
Host smart-1e0bea7d-ec9c-4603-b8fc-7aad931f5c43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436325253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.436325253
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.471359861
Short name T581
Test name
Test status
Simulation time 29653956 ps
CPU time 0.74 seconds
Started Apr 15 12:20:28 PM PDT 24
Finished Apr 15 12:20:30 PM PDT 24
Peak memory 193080 kb
Host smart-c73ef517-0bbc-4e30-9975-baf5fc136d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471359861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.471359861
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2868181163
Short name T516
Test name
Test status
Simulation time 93567792 ps
CPU time 1.21 seconds
Started Apr 15 12:20:22 PM PDT 24
Finished Apr 15 12:20:23 PM PDT 24
Peak memory 197180 kb
Host smart-6ce8bca2-260a-4ba1-bf4b-608bc1124e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868181163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2868181163
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.40442813
Short name T531
Test name
Test status
Simulation time 43883525 ps
CPU time 0.86 seconds
Started Apr 15 12:20:27 PM PDT 24
Finished Apr 15 12:20:29 PM PDT 24
Peak memory 193512 kb
Host smart-03ff0db3-63c6-48ab-9c4b-f1a7f8857c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40442813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_int
g_err.40442813
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3927848168
Short name T461
Test name
Test status
Simulation time 27061806 ps
CPU time 0.71 seconds
Started Apr 15 12:20:28 PM PDT 24
Finished Apr 15 12:20:29 PM PDT 24
Peak memory 195120 kb
Host smart-db398112-bccc-4c54-9db9-1218b7e6a1f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927848168 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3927848168
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1133204333
Short name T473
Test name
Test status
Simulation time 17942702 ps
CPU time 0.61 seconds
Started Apr 15 12:20:33 PM PDT 24
Finished Apr 15 12:20:34 PM PDT 24
Peak memory 191688 kb
Host smart-6ef78ff9-e1ed-40d3-b270-9bed9b407cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133204333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1133204333
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2601244815
Short name T490
Test name
Test status
Simulation time 16460882 ps
CPU time 0.54 seconds
Started Apr 15 12:20:13 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 182384 kb
Host smart-3b3cb58d-46b7-4b3f-94a9-0a0693241810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601244815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2601244815
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2190185495
Short name T527
Test name
Test status
Simulation time 133930526 ps
CPU time 0.7 seconds
Started Apr 15 12:20:37 PM PDT 24
Finished Apr 15 12:20:39 PM PDT 24
Peak memory 192916 kb
Host smart-df3f6e97-ca88-44b3-88f4-34e8858836ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190185495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2190185495
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3871532297
Short name T544
Test name
Test status
Simulation time 216391243 ps
CPU time 1.85 seconds
Started Apr 15 12:20:14 PM PDT 24
Finished Apr 15 12:20:17 PM PDT 24
Peak memory 197400 kb
Host smart-541a5328-8afb-4a79-a4db-8c1d83378be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871532297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3871532297
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.385864898
Short name T529
Test name
Test status
Simulation time 83536664 ps
CPU time 1.08 seconds
Started Apr 15 12:20:16 PM PDT 24
Finished Apr 15 12:20:23 PM PDT 24
Peak memory 182976 kb
Host smart-96c3a698-a48f-4b12-8bb0-ee18f02aaa6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385864898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.385864898
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1107519149
Short name T563
Test name
Test status
Simulation time 181239673 ps
CPU time 1.19 seconds
Started Apr 15 12:20:24 PM PDT 24
Finished Apr 15 12:20:25 PM PDT 24
Peak memory 197340 kb
Host smart-43ef3926-c8b3-454e-b7a7-432f640f64b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107519149 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1107519149
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1987304248
Short name T91
Test name
Test status
Simulation time 15264010 ps
CPU time 0.7 seconds
Started Apr 15 12:20:30 PM PDT 24
Finished Apr 15 12:20:31 PM PDT 24
Peak memory 181684 kb
Host smart-e6a22ba3-a44f-4c4b-a110-798c13f3eaa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987304248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1987304248
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.925620229
Short name T491
Test name
Test status
Simulation time 31439962 ps
CPU time 0.55 seconds
Started Apr 15 12:20:29 PM PDT 24
Finished Apr 15 12:20:31 PM PDT 24
Peak memory 182432 kb
Host smart-09c5d4cd-7ca4-48e8-a57d-c5412bfa1711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925620229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.925620229
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2395541711
Short name T89
Test name
Test status
Simulation time 78924187 ps
CPU time 0.88 seconds
Started Apr 15 12:20:42 PM PDT 24
Finished Apr 15 12:20:43 PM PDT 24
Peak memory 193092 kb
Host smart-7655e943-8fe5-48c7-adb4-9bde0f72e6d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395541711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2395541711
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1496389713
Short name T489
Test name
Test status
Simulation time 332131629 ps
CPU time 2.97 seconds
Started Apr 15 12:20:49 PM PDT 24
Finished Apr 15 12:20:52 PM PDT 24
Peak memory 197288 kb
Host smart-ba67abc3-af74-4d72-92b7-29b7a1073ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496389713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1496389713
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3911764039
Short name T533
Test name
Test status
Simulation time 363210327 ps
CPU time 1.08 seconds
Started Apr 15 12:20:37 PM PDT 24
Finished Apr 15 12:20:38 PM PDT 24
Peak memory 194976 kb
Host smart-13782484-d84e-41a4-81a6-bda693d56531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911764039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3911764039
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3697329524
Short name T557
Test name
Test status
Simulation time 181180195 ps
CPU time 0.74 seconds
Started Apr 15 12:20:27 PM PDT 24
Finished Apr 15 12:20:28 PM PDT 24
Peak memory 194200 kb
Host smart-4f273c69-3380-4ffb-9dc9-fbbe2e809d75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697329524 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3697329524
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1955555506
Short name T567
Test name
Test status
Simulation time 16542023 ps
CPU time 0.6 seconds
Started Apr 15 12:20:39 PM PDT 24
Finished Apr 15 12:20:41 PM PDT 24
Peak memory 182524 kb
Host smart-39b69865-c758-46be-bdc2-6727899de2b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955555506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1955555506
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1980180755
Short name T522
Test name
Test status
Simulation time 13044545 ps
CPU time 0.57 seconds
Started Apr 15 12:20:33 PM PDT 24
Finished Apr 15 12:20:34 PM PDT 24
Peak memory 182316 kb
Host smart-e723cb6d-d269-4439-92df-85db8fe65778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980180755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1980180755
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3915394108
Short name T559
Test name
Test status
Simulation time 43068515 ps
CPU time 0.64 seconds
Started Apr 15 12:20:28 PM PDT 24
Finished Apr 15 12:20:30 PM PDT 24
Peak memory 191488 kb
Host smart-d319bb69-377a-4b45-ab43-b43f8c94a0bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915394108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3915394108
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.338663422
Short name T476
Test name
Test status
Simulation time 25987988 ps
CPU time 1.16 seconds
Started Apr 15 12:20:35 PM PDT 24
Finished Apr 15 12:20:37 PM PDT 24
Peak memory 197348 kb
Host smart-512edcb3-cd68-4e51-8c3f-e7a0aa70da97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338663422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.338663422
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2427098714
Short name T519
Test name
Test status
Simulation time 223378450 ps
CPU time 1.35 seconds
Started Apr 15 12:20:15 PM PDT 24
Finished Apr 15 12:20:19 PM PDT 24
Peak memory 183208 kb
Host smart-952e9d60-0c0e-4f99-a474-bb4d8ca711e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427098714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2427098714
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1446923577
Short name T470
Test name
Test status
Simulation time 73120738 ps
CPU time 0.69 seconds
Started Apr 15 12:20:29 PM PDT 24
Finished Apr 15 12:20:30 PM PDT 24
Peak memory 195356 kb
Host smart-96916c10-3860-475e-a4c4-0a43ef3d3000
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446923577 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1446923577
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1182315796
Short name T554
Test name
Test status
Simulation time 24384041 ps
CPU time 0.63 seconds
Started Apr 15 12:20:14 PM PDT 24
Finished Apr 15 12:20:17 PM PDT 24
Peak memory 182516 kb
Host smart-98213c46-ac4c-4791-a01c-158ceca8bb3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182315796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1182315796
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3754284924
Short name T513
Test name
Test status
Simulation time 40398177 ps
CPU time 0.53 seconds
Started Apr 15 12:20:33 PM PDT 24
Finished Apr 15 12:20:35 PM PDT 24
Peak memory 182408 kb
Host smart-f489b845-614c-4f78-b7ad-56db30fac80d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754284924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3754284924
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1293670902
Short name T508
Test name
Test status
Simulation time 39078254 ps
CPU time 0.9 seconds
Started Apr 15 12:20:14 PM PDT 24
Finished Apr 15 12:20:16 PM PDT 24
Peak memory 194356 kb
Host smart-6551d31a-8bf1-4eba-bfb7-941321156c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293670902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1293670902
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2846846712
Short name T498
Test name
Test status
Simulation time 104592425 ps
CPU time 1.48 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:14 PM PDT 24
Peak memory 197400 kb
Host smart-35144219-a656-4fdc-a222-2a304ede93dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846846712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2846846712
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2175255125
Short name T538
Test name
Test status
Simulation time 188339349 ps
CPU time 0.81 seconds
Started Apr 15 12:20:14 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 193672 kb
Host smart-c9e6f80a-c5b2-4eff-9135-f1e4e781289a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175255125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2175255125
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1031518472
Short name T493
Test name
Test status
Simulation time 26279903 ps
CPU time 1.2 seconds
Started Apr 15 12:20:23 PM PDT 24
Finished Apr 15 12:20:25 PM PDT 24
Peak memory 197348 kb
Host smart-6dd19117-0a9c-41c4-9462-bfa697657dbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031518472 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1031518472
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4185313780
Short name T84
Test name
Test status
Simulation time 11776567 ps
CPU time 0.52 seconds
Started Apr 15 12:20:50 PM PDT 24
Finished Apr 15 12:20:51 PM PDT 24
Peak memory 182232 kb
Host smart-4b1ae257-54e8-4a19-8b5a-bbf4d7ab999d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185313780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.4185313780
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.151515082
Short name T553
Test name
Test status
Simulation time 103917231 ps
CPU time 0.55 seconds
Started Apr 15 12:20:27 PM PDT 24
Finished Apr 15 12:20:28 PM PDT 24
Peak memory 181824 kb
Host smart-870cce95-5478-41be-8ca1-10f8d8dfb9c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151515082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.151515082
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.767416989
Short name T86
Test name
Test status
Simulation time 39390547 ps
CPU time 0.81 seconds
Started Apr 15 12:20:43 PM PDT 24
Finished Apr 15 12:20:45 PM PDT 24
Peak memory 193252 kb
Host smart-50d899bb-59ae-4abc-92b9-4d13a5205bbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767416989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.767416989
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2584141428
Short name T479
Test name
Test status
Simulation time 547977062 ps
CPU time 1.34 seconds
Started Apr 15 12:20:34 PM PDT 24
Finished Apr 15 12:20:36 PM PDT 24
Peak memory 197172 kb
Host smart-bef97ec3-4d64-4650-bd07-8c21c1832ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584141428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2584141428
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1706911431
Short name T97
Test name
Test status
Simulation time 499451795 ps
CPU time 1.24 seconds
Started Apr 15 12:20:22 PM PDT 24
Finished Apr 15 12:20:23 PM PDT 24
Peak memory 195176 kb
Host smart-ec1a1f1f-f514-4c12-be60-da5162c3e996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706911431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1706911431
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1753422800
Short name T74
Test name
Test status
Simulation time 45438433 ps
CPU time 0.82 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 182516 kb
Host smart-899a9b39-2c0e-4099-a2cd-cdb95d6ccdc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753422800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1753422800
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3999788333
Short name T69
Test name
Test status
Simulation time 287911764 ps
CPU time 2.49 seconds
Started Apr 15 12:20:07 PM PDT 24
Finished Apr 15 12:20:11 PM PDT 24
Peak memory 193628 kb
Host smart-f7ec30e7-cf0e-4809-a760-c234d5094df5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999788333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3999788333
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1449590832
Short name T79
Test name
Test status
Simulation time 14474116 ps
CPU time 0.56 seconds
Started Apr 15 12:20:12 PM PDT 24
Finished Apr 15 12:20:14 PM PDT 24
Peak memory 182416 kb
Host smart-14bcbea1-c5a4-4e9d-adcb-7fd083b0cd1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449590832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1449590832
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1400408150
Short name T481
Test name
Test status
Simulation time 85751195 ps
CPU time 0.64 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 194096 kb
Host smart-c7e4be0a-0171-47ff-8d7b-05bb4b979402
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400408150 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1400408150
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1029365470
Short name T475
Test name
Test status
Simulation time 10770608 ps
CPU time 0.56 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 182336 kb
Host smart-3ca78967-c2b8-4c46-a2bc-3f19c2b3d4ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029365470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1029365470
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1860863731
Short name T551
Test name
Test status
Simulation time 65547066 ps
CPU time 0.54 seconds
Started Apr 15 12:20:22 PM PDT 24
Finished Apr 15 12:20:23 PM PDT 24
Peak memory 182452 kb
Host smart-b4b8e4fe-59b7-48e0-b851-3c5842a8630e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860863731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1860863731
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1826778657
Short name T50
Test name
Test status
Simulation time 85386947 ps
CPU time 0.85 seconds
Started Apr 15 12:20:15 PM PDT 24
Finished Apr 15 12:20:17 PM PDT 24
Peak memory 191476 kb
Host smart-77fde577-718d-41fc-a5ee-c98c0af8cc5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826778657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1826778657
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.900036374
Short name T514
Test name
Test status
Simulation time 135302481 ps
CPU time 1.71 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:12 PM PDT 24
Peak memory 197368 kb
Host smart-8f927417-cbf4-42b4-a5d5-11bf35da966e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900036374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.900036374
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3772861889
Short name T474
Test name
Test status
Simulation time 604182852 ps
CPU time 1.02 seconds
Started Apr 15 12:20:01 PM PDT 24
Finished Apr 15 12:20:03 PM PDT 24
Peak memory 182884 kb
Host smart-cacec02b-c156-4ff5-b0cd-a9258d44a1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772861889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3772861889
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3341409063
Short name T487
Test name
Test status
Simulation time 170225755 ps
CPU time 0.54 seconds
Started Apr 15 12:20:44 PM PDT 24
Finished Apr 15 12:20:45 PM PDT 24
Peak memory 182408 kb
Host smart-ca0b00dc-166c-40e0-b5e9-28b0fe06d025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341409063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3341409063
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.991005153
Short name T505
Test name
Test status
Simulation time 11930325 ps
CPU time 0.55 seconds
Started Apr 15 12:20:34 PM PDT 24
Finished Apr 15 12:20:35 PM PDT 24
Peak memory 182272 kb
Host smart-5e4ebaa4-cea8-4f6c-ac11-d6d520c0db0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991005153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.991005153
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.936905251
Short name T564
Test name
Test status
Simulation time 38783228 ps
CPU time 0.54 seconds
Started Apr 15 12:20:36 PM PDT 24
Finished Apr 15 12:20:37 PM PDT 24
Peak memory 181876 kb
Host smart-3b02d256-c59e-4665-8742-b4b4f936a59d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936905251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.936905251
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2517023645
Short name T549
Test name
Test status
Simulation time 15967481 ps
CPU time 0.58 seconds
Started Apr 15 12:20:15 PM PDT 24
Finished Apr 15 12:20:17 PM PDT 24
Peak memory 182456 kb
Host smart-c2e21026-ab29-403f-a29c-5f4ef531cce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517023645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2517023645
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.466287580
Short name T469
Test name
Test status
Simulation time 14886743 ps
CPU time 0.54 seconds
Started Apr 15 12:20:40 PM PDT 24
Finished Apr 15 12:20:41 PM PDT 24
Peak memory 181268 kb
Host smart-6e2d0107-7ce1-401e-a68c-a21c45ebfb19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466287580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.466287580
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4239492502
Short name T565
Test name
Test status
Simulation time 13440302 ps
CPU time 0.57 seconds
Started Apr 15 12:20:25 PM PDT 24
Finished Apr 15 12:20:26 PM PDT 24
Peak memory 182028 kb
Host smart-24237444-a0e5-49e1-bed9-d81bad587165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239492502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4239492502
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.426006662
Short name T500
Test name
Test status
Simulation time 33195633 ps
CPU time 0.52 seconds
Started Apr 15 12:20:33 PM PDT 24
Finished Apr 15 12:20:34 PM PDT 24
Peak memory 181772 kb
Host smart-44e754d4-9b48-4196-bd6a-6ed47408244f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426006662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.426006662
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1612776634
Short name T467
Test name
Test status
Simulation time 13607487 ps
CPU time 0.57 seconds
Started Apr 15 12:20:39 PM PDT 24
Finished Apr 15 12:20:40 PM PDT 24
Peak memory 182420 kb
Host smart-9f82f23e-dda5-48f3-91f0-a61631f9d30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612776634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1612776634
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2423279873
Short name T542
Test name
Test status
Simulation time 12837608 ps
CPU time 0.53 seconds
Started Apr 15 12:20:13 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 181812 kb
Host smart-d7286693-4c78-439a-82ba-7d305d77ffb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423279873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2423279873
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2934765309
Short name T547
Test name
Test status
Simulation time 46765924 ps
CPU time 0.54 seconds
Started Apr 15 12:20:33 PM PDT 24
Finished Apr 15 12:20:34 PM PDT 24
Peak memory 181812 kb
Host smart-c1ae04bd-74c3-4cbc-a6fa-82b6f1851fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934765309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2934765309
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3005385717
Short name T503
Test name
Test status
Simulation time 16891864 ps
CPU time 0.75 seconds
Started Apr 15 12:20:16 PM PDT 24
Finished Apr 15 12:20:22 PM PDT 24
Peak memory 192176 kb
Host smart-6e3f63f0-d950-4d11-8120-e4843b900abe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005385717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3005385717
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1658989746
Short name T83
Test name
Test status
Simulation time 35746455 ps
CPU time 1.36 seconds
Started Apr 15 12:20:12 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 190836 kb
Host smart-76005960-ab05-418f-a2a1-d12962369191
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658989746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1658989746
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2313757244
Short name T33
Test name
Test status
Simulation time 16041091 ps
CPU time 0.58 seconds
Started Apr 15 12:20:15 PM PDT 24
Finished Apr 15 12:20:21 PM PDT 24
Peak memory 182444 kb
Host smart-f860259a-5a96-424d-845d-8c51d136fa67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313757244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2313757244
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1338316600
Short name T521
Test name
Test status
Simulation time 56411011 ps
CPU time 0.79 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 196428 kb
Host smart-19023f13-afdf-49db-a6c0-a6d1a29480fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338316600 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1338316600
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2592200318
Short name T68
Test name
Test status
Simulation time 13692187 ps
CPU time 0.56 seconds
Started Apr 15 12:20:00 PM PDT 24
Finished Apr 15 12:20:02 PM PDT 24
Peak memory 182300 kb
Host smart-187100fb-6453-4aed-91e4-c7feaf44d875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592200318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2592200318
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2114207234
Short name T499
Test name
Test status
Simulation time 13132699 ps
CPU time 0.55 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 182428 kb
Host smart-f660ae68-1807-4cef-a09d-86c04a1db225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114207234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2114207234
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1343204992
Short name T511
Test name
Test status
Simulation time 40111973 ps
CPU time 0.62 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:12 PM PDT 24
Peak memory 191936 kb
Host smart-4de10dd3-d44c-4b15-a093-6c2662450835
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343204992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1343204992
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3502593693
Short name T60
Test name
Test status
Simulation time 59400414 ps
CPU time 1.12 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:11 PM PDT 24
Peak memory 197244 kb
Host smart-c7a76a19-bc26-4b8d-ae00-0448bdc4dba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502593693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3502593693
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1003827046
Short name T92
Test name
Test status
Simulation time 423675759 ps
CPU time 0.77 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:12 PM PDT 24
Peak memory 182872 kb
Host smart-c546e987-6038-4867-8871-07feab04bd00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003827046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1003827046
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3125127431
Short name T486
Test name
Test status
Simulation time 12921760 ps
CPU time 0.54 seconds
Started Apr 15 12:20:21 PM PDT 24
Finished Apr 15 12:20:22 PM PDT 24
Peak memory 182076 kb
Host smart-ebd2d690-b3ff-42b7-bd0f-7a95b6215be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125127431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3125127431
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3327358448
Short name T478
Test name
Test status
Simulation time 53622330 ps
CPU time 0.55 seconds
Started Apr 15 12:20:32 PM PDT 24
Finished Apr 15 12:20:33 PM PDT 24
Peak memory 182340 kb
Host smart-d765c37a-073b-451f-a7b9-75108755a4d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327358448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3327358448
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2769761369
Short name T459
Test name
Test status
Simulation time 23373846 ps
CPU time 0.56 seconds
Started Apr 15 12:20:38 PM PDT 24
Finished Apr 15 12:20:40 PM PDT 24
Peak memory 182016 kb
Host smart-aaa8a928-e53d-4611-a973-32e3f3e71a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769761369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2769761369
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1831588443
Short name T584
Test name
Test status
Simulation time 16662104 ps
CPU time 0.56 seconds
Started Apr 15 12:20:28 PM PDT 24
Finished Apr 15 12:20:29 PM PDT 24
Peak memory 182428 kb
Host smart-41040e5e-74e8-46b6-a2d7-5c2f66d70384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831588443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1831588443
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.621121051
Short name T480
Test name
Test status
Simulation time 18603055 ps
CPU time 0.58 seconds
Started Apr 15 12:20:25 PM PDT 24
Finished Apr 15 12:20:26 PM PDT 24
Peak memory 182360 kb
Host smart-d312f86c-8a6c-41b6-ae78-4c02b8eb3615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621121051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.621121051
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2754599708
Short name T556
Test name
Test status
Simulation time 50917612 ps
CPU time 0.54 seconds
Started Apr 15 12:20:34 PM PDT 24
Finished Apr 15 12:20:35 PM PDT 24
Peak memory 182268 kb
Host smart-5c60d9b3-9782-477d-94d3-3b0d50387899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754599708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2754599708
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.907614544
Short name T496
Test name
Test status
Simulation time 16438540 ps
CPU time 0.55 seconds
Started Apr 15 12:20:30 PM PDT 24
Finished Apr 15 12:20:32 PM PDT 24
Peak memory 182328 kb
Host smart-70a4a08f-64f7-4622-b22a-9d3febe21bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907614544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.907614544
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.489302944
Short name T545
Test name
Test status
Simulation time 13821886 ps
CPU time 0.52 seconds
Started Apr 15 12:20:16 PM PDT 24
Finished Apr 15 12:20:18 PM PDT 24
Peak memory 181868 kb
Host smart-76d11c35-bda5-4b9a-9557-9af9a28ebe0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489302944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.489302944
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2608391164
Short name T468
Test name
Test status
Simulation time 25255553 ps
CPU time 0.55 seconds
Started Apr 15 12:20:18 PM PDT 24
Finished Apr 15 12:20:20 PM PDT 24
Peak memory 182428 kb
Host smart-8ec9d685-6978-4986-ab8d-894244d70c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608391164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2608391164
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3730265239
Short name T568
Test name
Test status
Simulation time 22845884 ps
CPU time 0.55 seconds
Started Apr 15 12:20:30 PM PDT 24
Finished Apr 15 12:20:31 PM PDT 24
Peak memory 182384 kb
Host smart-9af055a2-31ca-438a-bfe2-52c900d5c323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730265239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3730265239
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2197710096
Short name T72
Test name
Test status
Simulation time 26373506 ps
CPU time 0.79 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:14 PM PDT 24
Peak memory 192156 kb
Host smart-11d29f36-9b96-4b6f-8358-252527c1201d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197710096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2197710096
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4265135617
Short name T81
Test name
Test status
Simulation time 149409120 ps
CPU time 1.49 seconds
Started Apr 15 12:20:05 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 193248 kb
Host smart-357cbc40-6151-4125-8eb1-7cc456e7f24c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265135617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.4265135617
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2767713636
Short name T536
Test name
Test status
Simulation time 14520992 ps
CPU time 0.54 seconds
Started Apr 15 12:20:16 PM PDT 24
Finished Apr 15 12:20:18 PM PDT 24
Peak memory 182508 kb
Host smart-2c6f1bd1-ad33-40fa-b8ea-aa0fccbebc7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767713636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2767713636
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3445218955
Short name T466
Test name
Test status
Simulation time 59139248 ps
CPU time 0.8 seconds
Started Apr 15 12:20:23 PM PDT 24
Finished Apr 15 12:20:24 PM PDT 24
Peak memory 194840 kb
Host smart-90245045-b185-4048-86e2-bae295f10460
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445218955 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3445218955
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1055041922
Short name T532
Test name
Test status
Simulation time 70992295 ps
CPU time 0.59 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:11 PM PDT 24
Peak memory 182504 kb
Host smart-aab6f1a5-a4fa-4285-9df2-4faf1edbbd5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055041922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1055041922
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.495503428
Short name T558
Test name
Test status
Simulation time 29186363 ps
CPU time 0.5 seconds
Started Apr 15 12:20:13 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 181840 kb
Host smart-dbd658f0-2e61-417d-bd76-20a8a98c0803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495503428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.495503428
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1739531172
Short name T85
Test name
Test status
Simulation time 26215740 ps
CPU time 0.68 seconds
Started Apr 15 12:20:15 PM PDT 24
Finished Apr 15 12:20:17 PM PDT 24
Peak memory 191816 kb
Host smart-9548b54c-d5fe-48fc-8b3a-4322dd62cf1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739531172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1739531172
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.187790015
Short name T528
Test name
Test status
Simulation time 269825131 ps
CPU time 1.96 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 197368 kb
Host smart-8caef95f-a411-4fa1-9a3e-66b72549a7eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187790015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.187790015
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.58079968
Short name T98
Test name
Test status
Simulation time 153957671 ps
CPU time 1.1 seconds
Started Apr 15 12:20:42 PM PDT 24
Finished Apr 15 12:20:44 PM PDT 24
Peak memory 194508 kb
Host smart-9e07cce6-1f4d-4ec1-ba06-3376c70f25a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58079968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg
_err.58079968
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1789825107
Short name T570
Test name
Test status
Simulation time 14854166 ps
CPU time 0.56 seconds
Started Apr 15 12:20:22 PM PDT 24
Finished Apr 15 12:20:23 PM PDT 24
Peak memory 182404 kb
Host smart-b7943d11-feb5-4cd3-86e8-54c6dac0d73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789825107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1789825107
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2732517988
Short name T509
Test name
Test status
Simulation time 28312427 ps
CPU time 0.52 seconds
Started Apr 15 12:20:28 PM PDT 24
Finished Apr 15 12:20:30 PM PDT 24
Peak memory 182480 kb
Host smart-f6c5f076-6d46-40e9-8fce-073707bd20fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732517988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2732517988
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.317366420
Short name T492
Test name
Test status
Simulation time 111374363 ps
CPU time 0.53 seconds
Started Apr 15 12:20:40 PM PDT 24
Finished Apr 15 12:20:41 PM PDT 24
Peak memory 182348 kb
Host smart-ac66ae8c-6f4e-400f-9ead-c3411c1024c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317366420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.317366420
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4044024904
Short name T485
Test name
Test status
Simulation time 15031131 ps
CPU time 0.61 seconds
Started Apr 15 12:20:31 PM PDT 24
Finished Apr 15 12:20:32 PM PDT 24
Peak memory 181868 kb
Host smart-c6cbb62b-9680-488b-b56f-aa2c2771667d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044024904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4044024904
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3064317654
Short name T506
Test name
Test status
Simulation time 17534368 ps
CPU time 0.54 seconds
Started Apr 15 12:20:19 PM PDT 24
Finished Apr 15 12:20:20 PM PDT 24
Peak memory 182348 kb
Host smart-ca3ffa5e-4e80-48db-86ad-0f9dbb96d234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064317654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3064317654
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2399152384
Short name T560
Test name
Test status
Simulation time 17772035 ps
CPU time 0.54 seconds
Started Apr 15 12:20:40 PM PDT 24
Finished Apr 15 12:20:41 PM PDT 24
Peak memory 181496 kb
Host smart-2589f87e-7579-4703-961f-04094351fd94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399152384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2399152384
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.361969380
Short name T483
Test name
Test status
Simulation time 54982517 ps
CPU time 0.51 seconds
Started Apr 15 12:20:46 PM PDT 24
Finished Apr 15 12:20:52 PM PDT 24
Peak memory 181836 kb
Host smart-f41129af-0d8a-4d11-8068-3fdd59ffc525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361969380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.361969380
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.501776577
Short name T462
Test name
Test status
Simulation time 33680403 ps
CPU time 0.51 seconds
Started Apr 15 12:20:45 PM PDT 24
Finished Apr 15 12:20:46 PM PDT 24
Peak memory 181960 kb
Host smart-3a47f038-2592-4b11-92af-8032bca2e9e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501776577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.501776577
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3523436500
Short name T579
Test name
Test status
Simulation time 61282810 ps
CPU time 0.54 seconds
Started Apr 15 12:20:37 PM PDT 24
Finished Apr 15 12:20:38 PM PDT 24
Peak memory 182384 kb
Host smart-f43ae567-a864-4045-8386-d5b130246728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523436500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3523436500
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.516457367
Short name T548
Test name
Test status
Simulation time 16163199 ps
CPU time 0.54 seconds
Started Apr 15 12:20:36 PM PDT 24
Finished Apr 15 12:20:37 PM PDT 24
Peak memory 182412 kb
Host smart-04afa3f8-1a9d-4587-b4a2-89824f7a7062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516457367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.516457367
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1171535021
Short name T504
Test name
Test status
Simulation time 19817894 ps
CPU time 0.72 seconds
Started Apr 15 12:20:14 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 193924 kb
Host smart-6ff7ec8d-2383-416b-b324-4fb4cbd84da3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171535021 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1171535021
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3265486290
Short name T77
Test name
Test status
Simulation time 39228266 ps
CPU time 0.54 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:07 PM PDT 24
Peak memory 181968 kb
Host smart-ebca84bc-e269-4426-9f88-72e3be8cef80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265486290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3265486290
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4077046239
Short name T550
Test name
Test status
Simulation time 19500724 ps
CPU time 0.52 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:08 PM PDT 24
Peak memory 181772 kb
Host smart-117f5360-caeb-445c-81ad-f782d6a911bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077046239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4077046239
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3374120603
Short name T70
Test name
Test status
Simulation time 15235245 ps
CPU time 0.71 seconds
Started Apr 15 12:20:15 PM PDT 24
Finished Apr 15 12:20:17 PM PDT 24
Peak memory 191468 kb
Host smart-28f364b5-df5b-4334-b9ec-bc1f840eb42e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374120603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3374120603
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1303387489
Short name T460
Test name
Test status
Simulation time 638971812 ps
CPU time 2.65 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:14 PM PDT 24
Peak memory 197436 kb
Host smart-2f1f9077-00d2-4dc3-9514-3798ec1626d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303387489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1303387489
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3813922746
Short name T94
Test name
Test status
Simulation time 427337549 ps
CPU time 1.31 seconds
Started Apr 15 12:20:24 PM PDT 24
Finished Apr 15 12:20:26 PM PDT 24
Peak memory 195224 kb
Host smart-07191d93-e053-4ca0-b46e-856e14f8e2ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813922746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3813922746
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2798768229
Short name T543
Test name
Test status
Simulation time 40319651 ps
CPU time 0.92 seconds
Started Apr 15 12:20:04 PM PDT 24
Finished Apr 15 12:20:05 PM PDT 24
Peak memory 197052 kb
Host smart-a6a5a42d-90ba-4c77-9b50-60165fdc7199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798768229 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2798768229
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3768576777
Short name T517
Test name
Test status
Simulation time 16474332 ps
CPU time 0.54 seconds
Started Apr 15 12:20:15 PM PDT 24
Finished Apr 15 12:20:17 PM PDT 24
Peak memory 182516 kb
Host smart-e64af856-ac69-4ce0-a019-c7fd9c2cf791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768576777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3768576777
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.832702191
Short name T569
Test name
Test status
Simulation time 13958002 ps
CPU time 0.53 seconds
Started Apr 15 12:20:15 PM PDT 24
Finished Apr 15 12:20:17 PM PDT 24
Peak memory 182412 kb
Host smart-1240bd25-ca4b-4ce6-9071-fd63c7aa2024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832702191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.832702191
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.310105296
Short name T530
Test name
Test status
Simulation time 42098609 ps
CPU time 0.7 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 192884 kb
Host smart-c50a63c6-2a4e-44d0-a6e7-01d3fc6c7d00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310105296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.310105296
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3616070112
Short name T482
Test name
Test status
Simulation time 386230646 ps
CPU time 2.08 seconds
Started Apr 15 12:20:07 PM PDT 24
Finished Apr 15 12:20:10 PM PDT 24
Peak memory 197348 kb
Host smart-35d5ac4b-180a-4edd-9e83-5e6910e7b67f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616070112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3616070112
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.216750901
Short name T494
Test name
Test status
Simulation time 613424769 ps
CPU time 0.81 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 192428 kb
Host smart-7a212e91-3d32-423c-a7a0-ee9a3d744c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216750901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.216750901
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.940634896
Short name T577
Test name
Test status
Simulation time 20556593 ps
CPU time 0.83 seconds
Started Apr 15 12:20:28 PM PDT 24
Finished Apr 15 12:20:30 PM PDT 24
Peak memory 196976 kb
Host smart-aaaded97-4ad9-4dfa-9ee1-2c087769c5a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940634896 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.940634896
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1009462391
Short name T78
Test name
Test status
Simulation time 16774983 ps
CPU time 0.55 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 182448 kb
Host smart-775831bb-fb02-4cd1-bce6-390f9bde752d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009462391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1009462391
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.4092221413
Short name T583
Test name
Test status
Simulation time 186474369 ps
CPU time 0.54 seconds
Started Apr 15 12:20:13 PM PDT 24
Finished Apr 15 12:20:15 PM PDT 24
Peak memory 182076 kb
Host smart-68a94a3b-6bba-4643-b375-f27e9c0ce850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092221413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.4092221413
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.542407738
Short name T520
Test name
Test status
Simulation time 25839651 ps
CPU time 0.6 seconds
Started Apr 15 12:20:29 PM PDT 24
Finished Apr 15 12:20:30 PM PDT 24
Peak memory 191744 kb
Host smart-908bf98a-4984-4ce8-947b-158b304bc751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542407738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.542407738
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.757996058
Short name T497
Test name
Test status
Simulation time 198692942 ps
CPU time 1.08 seconds
Started Apr 15 12:20:16 PM PDT 24
Finished Apr 15 12:20:18 PM PDT 24
Peak memory 196844 kb
Host smart-d94f6aad-7929-4609-88c1-1ab1834ec3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757996058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.757996058
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.273321687
Short name T96
Test name
Test status
Simulation time 810590257 ps
CPU time 1.37 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 195308 kb
Host smart-7fb78ef3-1571-497f-beb4-81018ada109a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273321687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.273321687
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3921558596
Short name T471
Test name
Test status
Simulation time 87051371 ps
CPU time 0.95 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 197160 kb
Host smart-855aa1c2-fa87-454c-9434-5b757622de33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921558596 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3921558596
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.666841632
Short name T465
Test name
Test status
Simulation time 39007335 ps
CPU time 0.56 seconds
Started Apr 15 12:20:20 PM PDT 24
Finished Apr 15 12:20:21 PM PDT 24
Peak memory 182524 kb
Host smart-203591e3-c990-4eac-b5d9-8962f49741a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666841632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.666841632
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3647651241
Short name T512
Test name
Test status
Simulation time 57385285 ps
CPU time 0.59 seconds
Started Apr 15 12:20:10 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 182384 kb
Host smart-3d69591a-557a-4ffe-9e6e-a5faa4776d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647651241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3647651241
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2096891930
Short name T540
Test name
Test status
Simulation time 62834574 ps
CPU time 0.67 seconds
Started Apr 15 12:20:18 PM PDT 24
Finished Apr 15 12:20:20 PM PDT 24
Peak memory 191824 kb
Host smart-2d537c65-fb7f-4fc9-9a81-e45b132a1728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096891930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2096891930
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3680966622
Short name T539
Test name
Test status
Simulation time 170010349 ps
CPU time 1.77 seconds
Started Apr 15 12:20:14 PM PDT 24
Finished Apr 15 12:20:18 PM PDT 24
Peak memory 197428 kb
Host smart-919b2d83-155c-4c82-8d81-63e2741fa021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680966622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3680966622
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2767105882
Short name T31
Test name
Test status
Simulation time 348793601 ps
CPU time 1.29 seconds
Started Apr 15 12:20:04 PM PDT 24
Finished Apr 15 12:20:06 PM PDT 24
Peak memory 195160 kb
Host smart-c96763b9-b6a0-4cda-a7e7-939e30662df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767105882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2767105882
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2645177213
Short name T484
Test name
Test status
Simulation time 53485976 ps
CPU time 0.76 seconds
Started Apr 15 12:20:04 PM PDT 24
Finished Apr 15 12:20:05 PM PDT 24
Peak memory 194904 kb
Host smart-25250f41-d6ac-4cc2-860e-960c1e88d941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645177213 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2645177213
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2658772920
Short name T67
Test name
Test status
Simulation time 24213655 ps
CPU time 0.58 seconds
Started Apr 15 12:20:22 PM PDT 24
Finished Apr 15 12:20:23 PM PDT 24
Peak memory 182524 kb
Host smart-bb8e2574-5451-4036-b2dc-60cc1c19d233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658772920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2658772920
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2480166143
Short name T518
Test name
Test status
Simulation time 13869318 ps
CPU time 0.52 seconds
Started Apr 15 12:20:11 PM PDT 24
Finished Apr 15 12:20:13 PM PDT 24
Peak memory 182368 kb
Host smart-c4641d17-6443-4ff3-9ac9-67f4d52a9d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480166143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2480166143
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1575254382
Short name T523
Test name
Test status
Simulation time 33189285 ps
CPU time 0.76 seconds
Started Apr 15 12:20:08 PM PDT 24
Finished Apr 15 12:20:10 PM PDT 24
Peak memory 193144 kb
Host smart-3ed05b11-9e04-48f2-846d-3182c43d395a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575254382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1575254382
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3313421121
Short name T464
Test name
Test status
Simulation time 48185226 ps
CPU time 1.26 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:12 PM PDT 24
Peak memory 197272 kb
Host smart-f0c2b946-bcd4-45c2-8c43-a75008dd98a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313421121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3313421121
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.255926541
Short name T582
Test name
Test status
Simulation time 706799707 ps
CPU time 1.35 seconds
Started Apr 15 12:20:14 PM PDT 24
Finished Apr 15 12:20:16 PM PDT 24
Peak memory 195232 kb
Host smart-2dd835fd-4be2-49e4-9374-8b59c055eedb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255926541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.255926541
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3907115604
Short name T46
Test name
Test status
Simulation time 17165078932 ps
CPU time 30.54 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:24:57 PM PDT 24
Peak memory 182496 kb
Host smart-949ad3de-986f-4ba3-bc38-645c0485a604
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907115604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3907115604
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2980199310
Short name T371
Test name
Test status
Simulation time 658610590928 ps
CPU time 291.96 seconds
Started Apr 15 12:24:37 PM PDT 24
Finished Apr 15 12:29:30 PM PDT 24
Peak memory 182444 kb
Host smart-e422359e-a032-4342-8886-2532797c7949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980199310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2980199310
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1511885072
Short name T247
Test name
Test status
Simulation time 541378383241 ps
CPU time 1786.53 seconds
Started Apr 15 12:24:39 PM PDT 24
Finished Apr 15 12:54:26 PM PDT 24
Peak memory 190588 kb
Host smart-82a8e608-eea2-4c26-9328-d9134e828ece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511885072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1511885072
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3883496138
Short name T43
Test name
Test status
Simulation time 19212331 ps
CPU time 0.53 seconds
Started Apr 15 12:24:19 PM PDT 24
Finished Apr 15 12:24:20 PM PDT 24
Peak memory 182208 kb
Host smart-334db48f-653b-4014-a520-c20661fbb8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883496138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3883496138
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.1105201067
Short name T337
Test name
Test status
Simulation time 152776303254 ps
CPU time 409.46 seconds
Started Apr 15 12:24:16 PM PDT 24
Finished Apr 15 12:31:07 PM PDT 24
Peak memory 197168 kb
Host smart-dd202277-30b3-4452-a993-c6df9f74e233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105201067 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.1105201067
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.194134475
Short name T414
Test name
Test status
Simulation time 627490948441 ps
CPU time 242.71 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:28:35 PM PDT 24
Peak memory 182384 kb
Host smart-274ece79-072d-4562-b1d6-ba61c9fd8002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194134475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.194134475
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.167480818
Short name T251
Test name
Test status
Simulation time 54547357115 ps
CPU time 66.93 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:25:43 PM PDT 24
Peak memory 182436 kb
Host smart-321b397d-1176-4417-925c-7362f066d067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167480818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.167480818
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1846716103
Short name T21
Test name
Test status
Simulation time 137504813 ps
CPU time 0.83 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:24:33 PM PDT 24
Peak memory 213080 kb
Host smart-1f82b12a-de46-4b48-824d-7e05ef23ccda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846716103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1846716103
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3655218117
Short name T312
Test name
Test status
Simulation time 439837003534 ps
CPU time 531.66 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 190608 kb
Host smart-12b192ae-4106-472f-b3ee-0d4d7da4620f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655218117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3655218117
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.120911552
Short name T423
Test name
Test status
Simulation time 327066384558 ps
CPU time 133.41 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:26:54 PM PDT 24
Peak memory 182500 kb
Host smart-53b88006-3d08-4c80-9bc0-556edb376891
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120911552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.120911552
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3571755430
Short name T426
Test name
Test status
Simulation time 106960197598 ps
CPU time 142.39 seconds
Started Apr 15 12:24:36 PM PDT 24
Finished Apr 15 12:26:59 PM PDT 24
Peak memory 182460 kb
Host smart-f714c91d-33eb-46fc-a6bc-5335c068ac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571755430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3571755430
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2216156988
Short name T457
Test name
Test status
Simulation time 159025536735 ps
CPU time 280.24 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:29:27 PM PDT 24
Peak memory 190692 kb
Host smart-4f1d67d4-89c1-4c09-b152-1f85e080b06c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216156988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2216156988
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2090726116
Short name T385
Test name
Test status
Simulation time 713042733 ps
CPU time 0.98 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:24:34 PM PDT 24
Peak memory 182176 kb
Host smart-d6c2111d-a378-4c3d-83ab-9538e6bceece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090726116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2090726116
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1115099106
Short name T447
Test name
Test status
Simulation time 397035581434 ps
CPU time 242.96 seconds
Started Apr 15 12:24:51 PM PDT 24
Finished Apr 15 12:28:55 PM PDT 24
Peak memory 190700 kb
Host smart-601359b7-d446-4fad-b37d-9b9c9196beb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115099106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1115099106
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1387219168
Short name T316
Test name
Test status
Simulation time 21203720873 ps
CPU time 43.24 seconds
Started Apr 15 12:25:02 PM PDT 24
Finished Apr 15 12:25:46 PM PDT 24
Peak memory 182484 kb
Host smart-6f5ba620-c46d-4602-b549-95be55760462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387219168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1387219168
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1806916955
Short name T130
Test name
Test status
Simulation time 57509039345 ps
CPU time 90.37 seconds
Started Apr 15 12:25:06 PM PDT 24
Finished Apr 15 12:26:37 PM PDT 24
Peak memory 190720 kb
Host smart-c0cb7336-ab36-4bbc-93d2-70e8be544133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806916955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1806916955
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2221636928
Short name T246
Test name
Test status
Simulation time 10452106269 ps
CPU time 16.92 seconds
Started Apr 15 12:25:06 PM PDT 24
Finished Apr 15 12:25:23 PM PDT 24
Peak memory 182500 kb
Host smart-e66b5dba-ac61-4d48-992b-d14c164bcca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221636928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2221636928
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3701095895
Short name T305
Test name
Test status
Simulation time 104885981078 ps
CPU time 1116.91 seconds
Started Apr 15 12:26:10 PM PDT 24
Finished Apr 15 12:44:47 PM PDT 24
Peak memory 188840 kb
Host smart-6419789c-1d83-412c-8cf4-89edd7dcef23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701095895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3701095895
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1934982876
Short name T57
Test name
Test status
Simulation time 2845937509 ps
CPU time 4.36 seconds
Started Apr 15 12:24:33 PM PDT 24
Finished Apr 15 12:24:39 PM PDT 24
Peak memory 182300 kb
Host smart-c06eef85-825a-48a7-b401-e9c996fbe5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934982876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1934982876
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2017539792
Short name T244
Test name
Test status
Simulation time 101475213301 ps
CPU time 180.01 seconds
Started Apr 15 12:24:36 PM PDT 24
Finished Apr 15 12:27:36 PM PDT 24
Peak memory 190692 kb
Host smart-4d84b5e7-6caf-4551-9b8c-7ef11db3f6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017539792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2017539792
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1756201813
Short name T183
Test name
Test status
Simulation time 119540727984 ps
CPU time 225.56 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:28:13 PM PDT 24
Peak memory 194472 kb
Host smart-892fb04c-c63a-4d69-b5f9-1b544707d261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756201813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1756201813
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.4021399998
Short name T41
Test name
Test status
Simulation time 31866995709 ps
CPU time 343.97 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:30:17 PM PDT 24
Peak memory 205296 kb
Host smart-519dd716-246e-4824-999d-618e750be670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021399998 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.4021399998
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1749983153
Short name T264
Test name
Test status
Simulation time 400093900968 ps
CPU time 175.97 seconds
Started Apr 15 12:25:03 PM PDT 24
Finished Apr 15 12:27:59 PM PDT 24
Peak memory 182492 kb
Host smart-1a992071-0d4e-4525-ba78-b73e8466d9d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749983153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1749983153
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3866939286
Short name T221
Test name
Test status
Simulation time 213603033497 ps
CPU time 690.3 seconds
Started Apr 15 12:26:10 PM PDT 24
Finished Apr 15 12:37:41 PM PDT 24
Peak memory 190140 kb
Host smart-eb2e3b3d-09bd-4309-a3e7-add9e7bc2c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866939286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3866939286
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.182757592
Short name T134
Test name
Test status
Simulation time 66981103487 ps
CPU time 80.46 seconds
Started Apr 15 12:24:51 PM PDT 24
Finished Apr 15 12:26:12 PM PDT 24
Peak memory 182512 kb
Host smart-9235a395-f416-4b5e-9114-2cd2a8a76f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182757592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.182757592
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3852925270
Short name T455
Test name
Test status
Simulation time 112717126442 ps
CPU time 1009.59 seconds
Started Apr 15 12:25:06 PM PDT 24
Finished Apr 15 12:41:56 PM PDT 24
Peak memory 190628 kb
Host smart-45f4f64b-b450-463b-9251-6530ca6142d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852925270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3852925270
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.4261131387
Short name T282
Test name
Test status
Simulation time 35020351674 ps
CPU time 30.12 seconds
Started Apr 15 12:24:59 PM PDT 24
Finished Apr 15 12:25:30 PM PDT 24
Peak memory 182508 kb
Host smart-7eb8ef0b-c1a9-497d-a564-cfd255b56338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261131387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4261131387
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3157693245
Short name T398
Test name
Test status
Simulation time 24760248307 ps
CPU time 11.57 seconds
Started Apr 15 12:25:04 PM PDT 24
Finished Apr 15 12:25:16 PM PDT 24
Peak memory 182496 kb
Host smart-c3d67bd3-f14a-460c-8581-1e5c1fab7e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157693245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3157693245
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1917595993
Short name T112
Test name
Test status
Simulation time 714285730620 ps
CPU time 405.23 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:31:16 PM PDT 24
Peak memory 182512 kb
Host smart-99848755-548e-496c-a5ca-5a33a2a38213
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917595993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1917595993
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3118809016
Short name T433
Test name
Test status
Simulation time 34665142059 ps
CPU time 25.21 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:25:00 PM PDT 24
Peak memory 182500 kb
Host smart-7af76f8d-f261-4417-b4e9-ddefa8bf924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118809016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3118809016
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1222826730
Short name T354
Test name
Test status
Simulation time 25350650093 ps
CPU time 35.12 seconds
Started Apr 15 12:24:34 PM PDT 24
Finished Apr 15 12:25:10 PM PDT 24
Peak memory 182312 kb
Host smart-0333ffcf-7787-45ef-9cdf-cca9a73f197b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222826730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1222826730
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2613451099
Short name T406
Test name
Test status
Simulation time 52371134508 ps
CPU time 11.39 seconds
Started Apr 15 12:24:50 PM PDT 24
Finished Apr 15 12:25:02 PM PDT 24
Peak memory 191320 kb
Host smart-26cf3373-58b2-4120-925f-9bae877dd0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613451099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2613451099
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1062200911
Short name T145
Test name
Test status
Simulation time 3302353777562 ps
CPU time 1514.35 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:49:45 PM PDT 24
Peak memory 190700 kb
Host smart-4805ef79-fdb8-42d7-9cd0-5f7e7e520243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062200911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1062200911
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.749362431
Short name T427
Test name
Test status
Simulation time 42400724421 ps
CPU time 119.35 seconds
Started Apr 15 12:25:14 PM PDT 24
Finished Apr 15 12:27:14 PM PDT 24
Peak memory 182504 kb
Host smart-d1b4e6da-b00c-4106-8937-2b21c481ad17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749362431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.749362431
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.924634739
Short name T409
Test name
Test status
Simulation time 89826067594 ps
CPU time 37.23 seconds
Started Apr 15 12:25:02 PM PDT 24
Finished Apr 15 12:25:40 PM PDT 24
Peak memory 182504 kb
Host smart-ff226596-fad0-4e28-9923-1825c60af695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924634739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.924634739
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1076610914
Short name T415
Test name
Test status
Simulation time 2851761061 ps
CPU time 3.44 seconds
Started Apr 15 12:26:13 PM PDT 24
Finished Apr 15 12:26:17 PM PDT 24
Peak memory 181600 kb
Host smart-e491106b-8979-40f4-b965-1b7c2e23a516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076610914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1076610914
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1263121908
Short name T4
Test name
Test status
Simulation time 120707448457 ps
CPU time 702.87 seconds
Started Apr 15 12:25:01 PM PDT 24
Finished Apr 15 12:36:45 PM PDT 24
Peak memory 190752 kb
Host smart-4ec09c3d-f168-4abf-8009-96286ea77544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263121908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1263121908
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1327067513
Short name T59
Test name
Test status
Simulation time 187930908981 ps
CPU time 352.24 seconds
Started Apr 15 12:25:06 PM PDT 24
Finished Apr 15 12:30:59 PM PDT 24
Peak memory 190688 kb
Host smart-474ddbd1-34a1-4514-82d6-9d48e14ea6f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327067513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1327067513
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2622090718
Short name T161
Test name
Test status
Simulation time 106687122538 ps
CPU time 71.24 seconds
Started Apr 15 12:25:10 PM PDT 24
Finished Apr 15 12:26:21 PM PDT 24
Peak memory 190752 kb
Host smart-dbb9b6d5-a1fb-4fad-b669-5130969326aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622090718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2622090718
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2406286781
Short name T190
Test name
Test status
Simulation time 211821021699 ps
CPU time 197.62 seconds
Started Apr 15 12:24:33 PM PDT 24
Finished Apr 15 12:27:52 PM PDT 24
Peak memory 182472 kb
Host smart-ecc26ed8-e982-4670-9749-5c7e175716eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406286781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2406286781
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3263123018
Short name T28
Test name
Test status
Simulation time 413172218957 ps
CPU time 228.66 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:28:33 PM PDT 24
Peak memory 182468 kb
Host smart-413f8d86-4cc0-484d-8025-b9b385e90eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263123018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3263123018
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.269031670
Short name T379
Test name
Test status
Simulation time 863478313 ps
CPU time 0.81 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:24:33 PM PDT 24
Peak memory 182140 kb
Host smart-9a4f55b6-f334-4b0b-998b-45352685b9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269031670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.269031670
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.2810554198
Short name T219
Test name
Test status
Simulation time 264578232138 ps
CPU time 155.41 seconds
Started Apr 15 12:25:13 PM PDT 24
Finished Apr 15 12:27:49 PM PDT 24
Peak memory 194008 kb
Host smart-9e65cc16-8046-45fa-be12-091ee3138903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810554198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2810554198
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1813520951
Short name T304
Test name
Test status
Simulation time 67852273493 ps
CPU time 103.25 seconds
Started Apr 15 12:25:01 PM PDT 24
Finished Apr 15 12:26:45 PM PDT 24
Peak memory 190712 kb
Host smart-38eac0d9-5b92-4382-874c-d8601ddc614d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813520951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1813520951
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3322444555
Short name T210
Test name
Test status
Simulation time 86244517704 ps
CPU time 485.98 seconds
Started Apr 15 12:25:06 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 190696 kb
Host smart-f71be651-e838-4ae7-8db2-3d23def2a05c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322444555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3322444555
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.275423615
Short name T253
Test name
Test status
Simulation time 8173933130 ps
CPU time 14.52 seconds
Started Apr 15 12:25:11 PM PDT 24
Finished Apr 15 12:25:26 PM PDT 24
Peak memory 182508 kb
Host smart-0e19186e-a416-444d-91f7-71f4a637386d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275423615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.275423615
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3647192256
Short name T434
Test name
Test status
Simulation time 235985470191 ps
CPU time 1657.82 seconds
Started Apr 15 12:25:07 PM PDT 24
Finished Apr 15 12:52:45 PM PDT 24
Peak memory 190676 kb
Host smart-1094ecee-e301-4299-86c3-c17a449cb0f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647192256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3647192256
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3887915356
Short name T274
Test name
Test status
Simulation time 148643341435 ps
CPU time 239.65 seconds
Started Apr 15 12:25:13 PM PDT 24
Finished Apr 15 12:29:14 PM PDT 24
Peak memory 190692 kb
Host smart-e89dde98-453e-4491-8aae-c0c68893bc10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887915356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3887915356
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3559909202
Short name T419
Test name
Test status
Simulation time 39115392607 ps
CPU time 41.91 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:25:13 PM PDT 24
Peak memory 182472 kb
Host smart-378231dc-309a-423c-bca2-032f41dd9bc9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559909202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3559909202
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random.597638859
Short name T240
Test name
Test status
Simulation time 9943039679 ps
CPU time 23.57 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:25:05 PM PDT 24
Peak memory 190668 kb
Host smart-39574d76-3580-4fed-a3ca-003b1cce35f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597638859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.597638859
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3752005790
Short name T231
Test name
Test status
Simulation time 114421986644 ps
CPU time 309.71 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:29:36 PM PDT 24
Peak memory 190692 kb
Host smart-1f60fc25-7046-4e96-b088-c56eb0a485b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752005790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3752005790
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.245734355
Short name T64
Test name
Test status
Simulation time 308473148824 ps
CPU time 308.57 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:29:43 PM PDT 24
Peak memory 194896 kb
Host smart-73863fd1-5e6c-4df2-b5fc-b98dac2ac517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245734355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
245734355
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.2980631576
Short name T23
Test name
Test status
Simulation time 324532176869 ps
CPU time 159.53 seconds
Started Apr 15 12:25:08 PM PDT 24
Finished Apr 15 12:27:48 PM PDT 24
Peak memory 194228 kb
Host smart-be0a8087-4032-4fa0-a05d-bfef78283a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980631576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2980631576
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3988231247
Short name T7
Test name
Test status
Simulation time 162762689784 ps
CPU time 121.69 seconds
Started Apr 15 12:25:11 PM PDT 24
Finished Apr 15 12:27:13 PM PDT 24
Peak memory 190708 kb
Host smart-bd1ec892-feb5-44e9-ba8e-fcb37a32ce00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988231247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3988231247
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3785895939
Short name T291
Test name
Test status
Simulation time 262646961412 ps
CPU time 76.63 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:26:30 PM PDT 24
Peak memory 190704 kb
Host smart-8c4936e3-572e-46c0-a2d2-881b318c5c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785895939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3785895939
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.647642656
Short name T129
Test name
Test status
Simulation time 145971033536 ps
CPU time 268.73 seconds
Started Apr 15 12:25:08 PM PDT 24
Finished Apr 15 12:29:37 PM PDT 24
Peak memory 190712 kb
Host smart-198512dc-1504-45a1-a495-df76b48a1e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647642656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.647642656
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.524706727
Short name T208
Test name
Test status
Simulation time 123060249973 ps
CPU time 400.81 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:31:53 PM PDT 24
Peak memory 190712 kb
Host smart-9f970bbc-de83-414b-bbb8-6952bd8b3ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524706727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.524706727
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2899299194
Short name T332
Test name
Test status
Simulation time 61397692459 ps
CPU time 33.27 seconds
Started Apr 15 12:25:13 PM PDT 24
Finished Apr 15 12:25:47 PM PDT 24
Peak memory 182500 kb
Host smart-4c6a3fc0-9ac2-4931-b7b6-6bb2ee927e72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899299194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2899299194
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2438372997
Short name T381
Test name
Test status
Simulation time 409424451796 ps
CPU time 149.24 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:27:06 PM PDT 24
Peak memory 182460 kb
Host smart-cef7670f-ea2d-4e1e-b6e0-430c65622ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438372997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2438372997
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3310874055
Short name T330
Test name
Test status
Simulation time 184584712896 ps
CPU time 116.64 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:26:28 PM PDT 24
Peak memory 190668 kb
Host smart-c7e32a62-fb00-47a3-b078-9fd27e452fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310874055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3310874055
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3044931613
Short name T405
Test name
Test status
Simulation time 14491512120 ps
CPU time 13.01 seconds
Started Apr 15 12:25:00 PM PDT 24
Finished Apr 15 12:25:14 PM PDT 24
Peak memory 182492 kb
Host smart-dbd80c39-c5ff-4480-9022-2195249f37d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044931613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3044931613
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.996760017
Short name T124
Test name
Test status
Simulation time 791413642013 ps
CPU time 2493.02 seconds
Started Apr 15 12:25:01 PM PDT 24
Finished Apr 15 01:06:35 PM PDT 24
Peak memory 190696 kb
Host smart-1ce33121-0818-44a0-a9c1-3e07c2955ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996760017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
996760017
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1466667613
Short name T329
Test name
Test status
Simulation time 70463516573 ps
CPU time 53.38 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:26:06 PM PDT 24
Peak memory 182312 kb
Host smart-6be3bb29-9b2a-4987-a764-54c35de8c104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466667613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1466667613
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.437757483
Short name T171
Test name
Test status
Simulation time 919288258034 ps
CPU time 223.78 seconds
Started Apr 15 12:25:18 PM PDT 24
Finished Apr 15 12:29:03 PM PDT 24
Peak memory 190552 kb
Host smart-ccfbf23b-1881-4a2e-b5e7-b6dd3ff5bccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437757483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.437757483
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.717022380
Short name T275
Test name
Test status
Simulation time 302689859998 ps
CPU time 240.06 seconds
Started Apr 15 12:25:18 PM PDT 24
Finished Apr 15 12:29:19 PM PDT 24
Peak memory 190700 kb
Host smart-43ea7f5c-f336-4ec1-8e46-3d2768ac7a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717022380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.717022380
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1928673689
Short name T266
Test name
Test status
Simulation time 85860033158 ps
CPU time 137.24 seconds
Started Apr 15 12:25:15 PM PDT 24
Finished Apr 15 12:27:32 PM PDT 24
Peak memory 194188 kb
Host smart-49a0db60-3bca-423f-afd5-16afe916ef7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928673689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1928673689
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2594350372
Short name T162
Test name
Test status
Simulation time 89874994165 ps
CPU time 140.93 seconds
Started Apr 15 12:26:38 PM PDT 24
Finished Apr 15 12:28:59 PM PDT 24
Peak memory 190624 kb
Host smart-48e33e41-02b1-4c0b-8e02-c2c08a49dc7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594350372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2594350372
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3277899319
Short name T140
Test name
Test status
Simulation time 317336228401 ps
CPU time 239.33 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 182480 kb
Host smart-7195cad5-6772-44e2-ad45-41cea46a1ba8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277899319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3277899319
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3541818335
Short name T445
Test name
Test status
Simulation time 483350639341 ps
CPU time 179.41 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:27:33 PM PDT 24
Peak memory 182432 kb
Host smart-8a677783-270a-4f09-b1e7-921fcc18e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541818335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3541818335
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.4095365916
Short name T256
Test name
Test status
Simulation time 178552320377 ps
CPU time 175.24 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:27:30 PM PDT 24
Peak memory 190636 kb
Host smart-aa25119a-3d1a-4410-9d76-aad74f15b40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095365916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4095365916
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2633627075
Short name T128
Test name
Test status
Simulation time 264367724299 ps
CPU time 158.18 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:27:14 PM PDT 24
Peak memory 182508 kb
Host smart-6b3aa6ce-fa8e-4b2c-8c78-0393038bd324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633627075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2633627075
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2629361438
Short name T176
Test name
Test status
Simulation time 115441312007 ps
CPU time 188.5 seconds
Started Apr 15 12:24:33 PM PDT 24
Finished Apr 15 12:27:47 PM PDT 24
Peak memory 182456 kb
Host smart-4633ad1c-2cd7-4ca1-82ce-fb694faf8292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629361438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2629361438
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.3393462404
Short name T106
Test name
Test status
Simulation time 393747053192 ps
CPU time 179.66 seconds
Started Apr 15 12:25:13 PM PDT 24
Finished Apr 15 12:28:13 PM PDT 24
Peak memory 190668 kb
Host smart-47fff5e8-ef79-4210-8cb3-1bd8480d3fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393462404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3393462404
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1896477942
Short name T197
Test name
Test status
Simulation time 1548284466571 ps
CPU time 183.07 seconds
Started Apr 15 12:25:11 PM PDT 24
Finished Apr 15 12:28:15 PM PDT 24
Peak memory 192108 kb
Host smart-2aa958bf-40fb-4a08-ac0f-e744894b9d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896477942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1896477942
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1394420088
Short name T265
Test name
Test status
Simulation time 277412096492 ps
CPU time 274.52 seconds
Started Apr 15 12:26:21 PM PDT 24
Finished Apr 15 12:30:56 PM PDT 24
Peak memory 190616 kb
Host smart-0e255f6a-161c-43de-a06d-2d1f153c3e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394420088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1394420088
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1098057486
Short name T207
Test name
Test status
Simulation time 340369317193 ps
CPU time 195.89 seconds
Started Apr 15 12:26:21 PM PDT 24
Finished Apr 15 12:29:37 PM PDT 24
Peak memory 190496 kb
Host smart-b3fe4758-c5ba-4921-995b-b9f9413e4058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098057486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1098057486
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.87620470
Short name T188
Test name
Test status
Simulation time 404935883259 ps
CPU time 725.4 seconds
Started Apr 15 12:25:13 PM PDT 24
Finished Apr 15 12:37:19 PM PDT 24
Peak memory 190688 kb
Host smart-5c3e9c5a-7681-4bcf-b782-2cf8db008fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87620470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.87620470
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1710872063
Short name T309
Test name
Test status
Simulation time 476303881414 ps
CPU time 77.84 seconds
Started Apr 15 12:25:18 PM PDT 24
Finished Apr 15 12:26:37 PM PDT 24
Peak memory 190680 kb
Host smart-d8662024-9bd1-4eef-be32-86b35ef06261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710872063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1710872063
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3365248801
Short name T322
Test name
Test status
Simulation time 332012337274 ps
CPU time 246.96 seconds
Started Apr 15 12:26:21 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 190616 kb
Host smart-b310a2f8-8ab2-4773-a2e9-38993eec3095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365248801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3365248801
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2659469833
Short name T301
Test name
Test status
Simulation time 10262383262 ps
CPU time 17.28 seconds
Started Apr 15 12:25:16 PM PDT 24
Finished Apr 15 12:25:34 PM PDT 24
Peak memory 182308 kb
Host smart-d27c6c7b-b102-4d7f-93df-ab0832207e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659469833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2659469833
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.196926868
Short name T335
Test name
Test status
Simulation time 34368772937 ps
CPU time 17.42 seconds
Started Apr 15 12:24:36 PM PDT 24
Finished Apr 15 12:24:54 PM PDT 24
Peak memory 182452 kb
Host smart-5a433373-5d8d-43c7-ac81-690674d6e3fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196926868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.196926868
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2217724336
Short name T387
Test name
Test status
Simulation time 275614087830 ps
CPU time 78.61 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:25:47 PM PDT 24
Peak memory 182480 kb
Host smart-6333e81c-59af-4aad-b12a-500fa8d11165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217724336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2217724336
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3864998654
Short name T119
Test name
Test status
Simulation time 531481593742 ps
CPU time 530.5 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:33:37 PM PDT 24
Peak memory 190704 kb
Host smart-e1409c5f-09f9-42ee-94ad-c7a15c8c8af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864998654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3864998654
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3146360037
Short name T368
Test name
Test status
Simulation time 23505921 ps
CPU time 0.55 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:24:47 PM PDT 24
Peak memory 182236 kb
Host smart-f6ec224d-8fbb-4ace-8fbc-e9b1c6e2b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146360037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3146360037
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3212177048
Short name T394
Test name
Test status
Simulation time 17795585463 ps
CPU time 22.3 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:24:56 PM PDT 24
Peak memory 182500 kb
Host smart-ef87c154-24ad-44c9-96c5-7ca693b410f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212177048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3212177048
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.2775736560
Short name T169
Test name
Test status
Simulation time 19359784166 ps
CPU time 30.61 seconds
Started Apr 15 12:25:09 PM PDT 24
Finished Apr 15 12:25:40 PM PDT 24
Peak memory 182276 kb
Host smart-62456910-2e15-421f-b040-e8486d688560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775736560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2775736560
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1471036104
Short name T342
Test name
Test status
Simulation time 86055799128 ps
CPU time 87.79 seconds
Started Apr 15 12:26:21 PM PDT 24
Finished Apr 15 12:27:49 PM PDT 24
Peak memory 190452 kb
Host smart-0a892f0a-c546-4bab-907b-c027e8716089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471036104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1471036104
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1627283141
Short name T187
Test name
Test status
Simulation time 176673520523 ps
CPU time 743.65 seconds
Started Apr 15 12:25:15 PM PDT 24
Finished Apr 15 12:37:40 PM PDT 24
Peak memory 190724 kb
Host smart-d18f0502-5c50-466d-bae9-9445b8608fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627283141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1627283141
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3021244755
Short name T280
Test name
Test status
Simulation time 101349344202 ps
CPU time 66.74 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:26:19 PM PDT 24
Peak memory 182268 kb
Host smart-715094ab-b99e-49f1-b981-5ba9b143e3e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021244755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3021244755
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1031830523
Short name T340
Test name
Test status
Simulation time 189966389038 ps
CPU time 602.91 seconds
Started Apr 15 12:25:14 PM PDT 24
Finished Apr 15 12:35:17 PM PDT 24
Peak memory 190700 kb
Host smart-eeaa7192-3437-4784-ab8d-28055445df3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031830523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1031830523
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3625605055
Short name T165
Test name
Test status
Simulation time 163510069270 ps
CPU time 294.29 seconds
Started Apr 15 12:25:18 PM PDT 24
Finished Apr 15 12:30:13 PM PDT 24
Peak memory 190684 kb
Host smart-1d8efe03-9afe-41f1-baf5-3ed7dc994854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625605055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3625605055
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3873324648
Short name T333
Test name
Test status
Simulation time 36365268179 ps
CPU time 683.67 seconds
Started Apr 15 12:25:18 PM PDT 24
Finished Apr 15 12:36:42 PM PDT 24
Peak memory 190688 kb
Host smart-53a04cc5-fcc3-41d6-bb50-863eb28ba207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873324648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3873324648
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.434686733
Short name T346
Test name
Test status
Simulation time 403973963882 ps
CPU time 357.67 seconds
Started Apr 15 12:24:37 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 182496 kb
Host smart-cbc528ed-77ac-4d16-8987-2b1c80366461
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434686733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.434686733
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2815536431
Short name T432
Test name
Test status
Simulation time 377271135816 ps
CPU time 145.46 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:27:06 PM PDT 24
Peak memory 182492 kb
Host smart-3637a071-32a3-469c-91b2-7e0b9432ae19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815536431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2815536431
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.10661424
Short name T297
Test name
Test status
Simulation time 367553118234 ps
CPU time 190.92 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:27:39 PM PDT 24
Peak memory 190708 kb
Host smart-9be4ff3e-b95f-4745-b964-ab757eb07475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10661424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.10661424
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.2471654335
Short name T189
Test name
Test status
Simulation time 737251339495 ps
CPU time 248.5 seconds
Started Apr 15 12:25:21 PM PDT 24
Finished Apr 15 12:29:30 PM PDT 24
Peak memory 190696 kb
Host smart-7d210113-b70b-47c6-8ca9-8322221fcb75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471654335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2471654335
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1184007311
Short name T181
Test name
Test status
Simulation time 11030234800 ps
CPU time 18.67 seconds
Started Apr 15 12:25:25 PM PDT 24
Finished Apr 15 12:25:44 PM PDT 24
Peak memory 190592 kb
Host smart-8efac143-80d5-4eb0-9ecd-02c550f7c1b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184007311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1184007311
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3188382538
Short name T218
Test name
Test status
Simulation time 79891334791 ps
CPU time 82.04 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:26:34 PM PDT 24
Peak memory 190668 kb
Host smart-4acfd63d-6c2d-4e6f-8ea0-b58d06be02ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188382538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3188382538
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1976646504
Short name T294
Test name
Test status
Simulation time 54872810597 ps
CPU time 45.4 seconds
Started Apr 15 12:25:23 PM PDT 24
Finished Apr 15 12:26:09 PM PDT 24
Peak memory 190652 kb
Host smart-427fb086-9afc-4396-a5c8-0ec0f6dd97db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976646504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1976646504
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.124476482
Short name T315
Test name
Test status
Simulation time 244812857218 ps
CPU time 230.46 seconds
Started Apr 15 12:25:21 PM PDT 24
Finished Apr 15 12:29:12 PM PDT 24
Peak memory 190704 kb
Host smart-43341c26-e4c0-48f3-a6fc-08399bc784e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124476482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.124476482
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1080997326
Short name T203
Test name
Test status
Simulation time 160941411421 ps
CPU time 179.18 seconds
Started Apr 15 12:25:18 PM PDT 24
Finished Apr 15 12:28:17 PM PDT 24
Peak memory 190712 kb
Host smart-f1e9a84e-6fb8-4a68-a3e2-cd9da628ea5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080997326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1080997326
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1435053242
Short name T321
Test name
Test status
Simulation time 10031360340 ps
CPU time 18.68 seconds
Started Apr 15 12:24:38 PM PDT 24
Finished Apr 15 12:24:58 PM PDT 24
Peak memory 182500 kb
Host smart-17862bed-37d3-4b0b-b3ed-da49258be921
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435053242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1435053242
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2299327404
Short name T435
Test name
Test status
Simulation time 541112728833 ps
CPU time 235.18 seconds
Started Apr 15 12:24:34 PM PDT 24
Finished Apr 15 12:28:35 PM PDT 24
Peak memory 182468 kb
Host smart-f8c3c91c-1e3f-4402-a8ac-6f5bbc5a4be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299327404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2299327404
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.828903660
Short name T167
Test name
Test status
Simulation time 275934080443 ps
CPU time 286.34 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:29:30 PM PDT 24
Peak memory 182384 kb
Host smart-43590e30-5e7d-4f9b-8095-e001fb73479d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828903660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.828903660
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.4168041201
Short name T227
Test name
Test status
Simulation time 459873997525 ps
CPU time 393.16 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:31:04 PM PDT 24
Peak memory 194740 kb
Host smart-09cd8ff0-0f93-486e-a421-5f3c2bc8c925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168041201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4168041201
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1790356638
Short name T358
Test name
Test status
Simulation time 590732733879 ps
CPU time 404.9 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:31:13 PM PDT 24
Peak memory 190720 kb
Host smart-885bf29d-21c4-41a1-9bbf-b7b42c325516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790356638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1790356638
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3700744751
Short name T48
Test name
Test status
Simulation time 118867057944 ps
CPU time 852.96 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 210476 kb
Host smart-67f3d847-3ae3-474c-964b-582da231cfe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700744751 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3700744751
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.rv_timer_random.3866274176
Short name T27
Test name
Test status
Simulation time 435068268215 ps
CPU time 342.58 seconds
Started Apr 15 12:25:21 PM PDT 24
Finished Apr 15 12:31:04 PM PDT 24
Peak memory 190672 kb
Host smart-3d1cae5b-8ad6-4040-8bf9-09293d5e6daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866274176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3866274176
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3459053588
Short name T122
Test name
Test status
Simulation time 69610162868 ps
CPU time 63.51 seconds
Started Apr 15 12:25:16 PM PDT 24
Finished Apr 15 12:26:20 PM PDT 24
Peak memory 190796 kb
Host smart-f9ace9d0-25c2-4740-831e-6a033b0619bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459053588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3459053588
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1815406791
Short name T211
Test name
Test status
Simulation time 87340416411 ps
CPU time 132.1 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 194236 kb
Host smart-f3c38bb1-53ba-4d17-ab08-f03fabd65578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815406791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1815406791
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.106282748
Short name T142
Test name
Test status
Simulation time 142211107891 ps
CPU time 314.68 seconds
Started Apr 15 12:25:20 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 190676 kb
Host smart-04868eaf-ae54-4758-a1b5-c6141bc6057c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106282748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.106282748
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4100980939
Short name T220
Test name
Test status
Simulation time 129124087027 ps
CPU time 562.99 seconds
Started Apr 15 12:25:22 PM PDT 24
Finished Apr 15 12:34:45 PM PDT 24
Peak memory 194280 kb
Host smart-62144fec-9cce-4aba-8d76-fa9bdfeda40a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100980939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4100980939
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3467915450
Short name T319
Test name
Test status
Simulation time 9978705393 ps
CPU time 19.62 seconds
Started Apr 15 12:25:11 PM PDT 24
Finished Apr 15 12:25:31 PM PDT 24
Peak memory 182468 kb
Host smart-69d406c5-b26b-4ad0-a8d1-48357f942d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467915450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3467915450
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.194582630
Short name T397
Test name
Test status
Simulation time 103487774733 ps
CPU time 157.94 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:27:09 PM PDT 24
Peak memory 182496 kb
Host smart-f9f6a017-7e7e-4abe-af2e-ee9515b89f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194582630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.194582630
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3839110344
Short name T308
Test name
Test status
Simulation time 267872847037 ps
CPU time 449.69 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:32:02 PM PDT 24
Peak memory 190640 kb
Host smart-208c2293-96ad-4b80-ac0f-a7928bd0acf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839110344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3839110344
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3376300899
Short name T448
Test name
Test status
Simulation time 193337624675 ps
CPU time 129.49 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:26:34 PM PDT 24
Peak memory 182420 kb
Host smart-97d12b45-8b97-48d9-9673-76989059326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376300899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3376300899
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3484396186
Short name T19
Test name
Test status
Simulation time 43612274 ps
CPU time 0.74 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:24:30 PM PDT 24
Peak memory 213056 kb
Host smart-4acd84ad-e6a2-4da4-a872-fa816719f200
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484396186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3484396186
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.222519826
Short name T16
Test name
Test status
Simulation time 206301330954 ps
CPU time 376.97 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:30:41 PM PDT 24
Peak memory 205240 kb
Host smart-dc4eec95-a957-4418-8535-0fe0b5b59f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222519826 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.222519826
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1739710264
Short name T412
Test name
Test status
Simulation time 229448663794 ps
CPU time 168.69 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:27:21 PM PDT 24
Peak memory 182468 kb
Host smart-d15478eb-11de-42f8-b16d-037c10c03244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739710264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1739710264
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2587851297
Short name T339
Test name
Test status
Simulation time 121707223866 ps
CPU time 368.22 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:30:39 PM PDT 24
Peak memory 190600 kb
Host smart-115f2a04-0eb4-41ee-9492-8e9982a9edc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587851297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2587851297
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.803076006
Short name T383
Test name
Test status
Simulation time 257678056 ps
CPU time 0.74 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:24:26 PM PDT 24
Peak memory 182540 kb
Host smart-fcf02cd3-8cf1-4f18-b3b2-77cd969cb9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803076006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.803076006
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.1541101471
Short name T38
Test name
Test status
Simulation time 43731624717 ps
CPU time 468.49 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:32:15 PM PDT 24
Peak memory 205368 kb
Host smart-8f0664e9-4ec6-4278-9940-04bcf7c4a7a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541101471 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.1541101471
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2017433911
Short name T178
Test name
Test status
Simulation time 2771309673115 ps
CPU time 1023.95 seconds
Started Apr 15 12:24:38 PM PDT 24
Finished Apr 15 12:41:43 PM PDT 24
Peak memory 182500 kb
Host smart-0a83d307-f6e9-43e9-af36-c10d42629a3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017433911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2017433911
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2002643251
Short name T376
Test name
Test status
Simulation time 163374353256 ps
CPU time 281.09 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:29:17 PM PDT 24
Peak memory 182492 kb
Host smart-0966f7c6-ce99-4b1e-9626-b622ba0a4630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002643251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2002643251
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1985535549
Short name T442
Test name
Test status
Simulation time 33693826597 ps
CPU time 202.37 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:27:52 PM PDT 24
Peak memory 190704 kb
Host smart-675663e8-a850-4923-868d-1678e1e67b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985535549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1985535549
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2285970284
Short name T272
Test name
Test status
Simulation time 140208799806 ps
CPU time 234.54 seconds
Started Apr 15 12:24:33 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 182468 kb
Host smart-17edd583-78ac-4a0f-bee1-a088e3e45b24
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285970284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2285970284
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3360285809
Short name T384
Test name
Test status
Simulation time 76364019860 ps
CPU time 35.48 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:25:19 PM PDT 24
Peak memory 182392 kb
Host smart-f4917acf-f09f-43b1-97e4-2601a78f0418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360285809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3360285809
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1872594843
Short name T199
Test name
Test status
Simulation time 298008417219 ps
CPU time 638.39 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:35:22 PM PDT 24
Peak memory 190700 kb
Host smart-6fd786bb-065e-413f-9bed-c894a6e63396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872594843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1872594843
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1932230630
Short name T214
Test name
Test status
Simulation time 41412083379 ps
CPU time 488.25 seconds
Started Apr 15 12:24:34 PM PDT 24
Finished Apr 15 12:32:43 PM PDT 24
Peak memory 190672 kb
Host smart-1f35e6b9-af43-4aa4-b35d-a2e10326e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932230630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1932230630
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1255028358
Short name T12
Test name
Test status
Simulation time 31389910298 ps
CPU time 48.89 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:25:29 PM PDT 24
Peak memory 182484 kb
Host smart-6a299e4f-1b68-4c20-934d-cbe1f89d6b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255028358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1255028358
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1879713781
Short name T390
Test name
Test status
Simulation time 33300247 ps
CPU time 0.57 seconds
Started Apr 15 12:24:50 PM PDT 24
Finished Apr 15 12:24:51 PM PDT 24
Peak memory 182236 kb
Host smart-96ddc416-f844-42d5-b399-e1ad016e9514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879713781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1879713781
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2191541384
Short name T56
Test name
Test status
Simulation time 1049495393826 ps
CPU time 2019.56 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:58:12 PM PDT 24
Peak memory 190712 kb
Host smart-36ef444c-7125-4499-a9aa-ce3d950185dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191541384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2191541384
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2766812877
Short name T325
Test name
Test status
Simulation time 572642621541 ps
CPU time 576.06 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:34:21 PM PDT 24
Peak memory 182500 kb
Host smart-b59f09a0-98c7-44e7-b95a-0e9192cba086
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766812877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2766812877
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3866160655
Short name T360
Test name
Test status
Simulation time 105575498823 ps
CPU time 151.95 seconds
Started Apr 15 12:24:38 PM PDT 24
Finished Apr 15 12:27:11 PM PDT 24
Peak memory 182492 kb
Host smart-549f1ca1-fd8e-4c32-8aa1-29cf42e66013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866160655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3866160655
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3106404667
Short name T302
Test name
Test status
Simulation time 101651426213 ps
CPU time 268.49 seconds
Started Apr 15 12:24:34 PM PDT 24
Finished Apr 15 12:29:03 PM PDT 24
Peak memory 182508 kb
Host smart-e9d4ed17-88c6-433e-813d-40181d37df86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106404667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3106404667
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1526376863
Short name T327
Test name
Test status
Simulation time 12316154248 ps
CPU time 20.37 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:25:04 PM PDT 24
Peak memory 192600 kb
Host smart-83b23112-5cce-4651-904e-d59dbbb217b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526376863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1526376863
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.903616767
Short name T15
Test name
Test status
Simulation time 69618519326 ps
CPU time 485.41 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:32:50 PM PDT 24
Peak memory 197120 kb
Host smart-639b9911-a607-4a88-9444-22e6d47b9459
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903616767 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.903616767
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.29714711
Short name T344
Test name
Test status
Simulation time 21664942258 ps
CPU time 12.57 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:24:45 PM PDT 24
Peak memory 182424 kb
Host smart-b4faade5-550e-4583-b96d-503174819490
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29714711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.rv_timer_cfg_update_on_fly.29714711
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3264776615
Short name T389
Test name
Test status
Simulation time 147818136222 ps
CPU time 116.12 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:26:39 PM PDT 24
Peak memory 182492 kb
Host smart-c79a31f7-29e3-470d-afea-d9cbdc2ea2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264776615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3264776615
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3052110765
Short name T288
Test name
Test status
Simulation time 55148929541 ps
CPU time 76.13 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:25:58 PM PDT 24
Peak memory 182468 kb
Host smart-cb19b790-b5fb-4348-9d98-ee2ef29a124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052110765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3052110765
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.172920910
Short name T285
Test name
Test status
Simulation time 1154282193229 ps
CPU time 668.38 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:35:49 PM PDT 24
Peak memory 182504 kb
Host smart-11dab986-1a31-429c-8f3d-69c5b37602f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172920910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.172920910
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3756964116
Short name T408
Test name
Test status
Simulation time 850400190580 ps
CPU time 211.89 seconds
Started Apr 15 12:24:38 PM PDT 24
Finished Apr 15 12:28:10 PM PDT 24
Peak memory 182472 kb
Host smart-d4ce20b5-5603-45bd-a20d-a7a0d1451f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756964116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3756964116
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.791591065
Short name T307
Test name
Test status
Simulation time 102119904930 ps
CPU time 144.54 seconds
Started Apr 15 12:24:39 PM PDT 24
Finished Apr 15 12:27:04 PM PDT 24
Peak memory 190692 kb
Host smart-e9ab5ddf-5298-4ec2-b508-6a0514fe8575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791591065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.791591065
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1330227335
Short name T283
Test name
Test status
Simulation time 16872082064 ps
CPU time 30.86 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:25:02 PM PDT 24
Peak memory 182460 kb
Host smart-14cd2b67-78eb-409f-b44c-e1a4d0647d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330227335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1330227335
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2726940834
Short name T65
Test name
Test status
Simulation time 278642272953 ps
CPU time 382.22 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:31:06 PM PDT 24
Peak memory 190712 kb
Host smart-e46df346-a81e-472f-a94a-10c1e74b30d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726940834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2726940834
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2609121288
Short name T431
Test name
Test status
Simulation time 37493682649 ps
CPU time 422.23 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:31:48 PM PDT 24
Peak memory 205488 kb
Host smart-2acc0df9-808c-40b6-876d-1ff6037596bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609121288 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.2609121288
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.139940095
Short name T452
Test name
Test status
Simulation time 130117683562 ps
CPU time 123.81 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:26:51 PM PDT 24
Peak memory 182428 kb
Host smart-de30826c-e2c2-43e8-89f0-d72697963180
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139940095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.139940095
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1804354509
Short name T364
Test name
Test status
Simulation time 122200887401 ps
CPU time 197.53 seconds
Started Apr 15 12:24:23 PM PDT 24
Finished Apr 15 12:27:42 PM PDT 24
Peak memory 182476 kb
Host smart-087ff0cb-a8fd-4485-9525-84ee82d2d153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804354509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1804354509
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3916706549
Short name T271
Test name
Test status
Simulation time 140011060174 ps
CPU time 496.16 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:33:00 PM PDT 24
Peak memory 190796 kb
Host smart-cfc7bdfa-8099-45eb-bdb4-fc23adfc1028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916706549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3916706549
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1485774016
Short name T430
Test name
Test status
Simulation time 20771496373 ps
CPU time 34.48 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:25:10 PM PDT 24
Peak memory 194872 kb
Host smart-b2bd4851-d429-43f4-9f94-9da1fb55aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485774016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1485774016
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3977290129
Short name T206
Test name
Test status
Simulation time 15917211287 ps
CPU time 29.95 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:25:15 PM PDT 24
Peak memory 182468 kb
Host smart-5666f778-d1fa-4786-9c83-8d284f07de9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977290129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3977290129
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.140847750
Short name T410
Test name
Test status
Simulation time 84971670073 ps
CPU time 135.18 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:26:46 PM PDT 24
Peak memory 182452 kb
Host smart-18bfc2a6-56c8-4c7f-842e-2abf4b656608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140847750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.140847750
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3930067375
Short name T8
Test name
Test status
Simulation time 93963410782 ps
CPU time 491.21 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:32:54 PM PDT 24
Peak memory 190700 kb
Host smart-e030f83f-a340-46e3-b420-44bda52270e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930067375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3930067375
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.746118797
Short name T116
Test name
Test status
Simulation time 838828770402 ps
CPU time 530.34 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:33:37 PM PDT 24
Peak memory 194708 kb
Host smart-0a54ad9f-ac5d-4ed4-8c42-c3d80dc9bcdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746118797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
746118797
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2944899111
Short name T228
Test name
Test status
Simulation time 237666450633 ps
CPU time 332.28 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:30:19 PM PDT 24
Peak memory 182452 kb
Host smart-35be708d-05f0-4af4-a366-da91181fe6fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944899111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2944899111
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2182019083
Short name T450
Test name
Test status
Simulation time 10668054129 ps
CPU time 17.9 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:25:04 PM PDT 24
Peak memory 182492 kb
Host smart-db54accc-167f-4fd3-a23e-1df13a99e4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182019083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2182019083
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2528258435
Short name T58
Test name
Test status
Simulation time 67434212143 ps
CPU time 365.14 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 190652 kb
Host smart-305bbb41-25e1-4ee6-afc1-2c54b27ba64d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528258435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2528258435
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2890480759
Short name T351
Test name
Test status
Simulation time 246756849602 ps
CPU time 103.89 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:26:16 PM PDT 24
Peak memory 190696 kb
Host smart-2e456d27-a427-4b46-b292-1308de8199cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890480759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2890480759
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2006162965
Short name T5
Test name
Test status
Simulation time 483312501661 ps
CPU time 381.72 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:30:54 PM PDT 24
Peak memory 190712 kb
Host smart-5d98f84e-f38e-4a95-8eaa-8a7c231baa24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006162965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2006162965
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2376354546
Short name T40
Test name
Test status
Simulation time 63323733629 ps
CPU time 455.39 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 205312 kb
Host smart-21a932b1-8e11-47d2-892f-5029cd4dba2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376354546 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2376354546
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3853774490
Short name T418
Test name
Test status
Simulation time 282781745785 ps
CPU time 517.82 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:33:03 PM PDT 24
Peak memory 182460 kb
Host smart-d7f37b8c-7640-4564-becf-0c55719e89ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853774490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3853774490
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3243021986
Short name T373
Test name
Test status
Simulation time 575485550391 ps
CPU time 237.73 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:28:22 PM PDT 24
Peak memory 182472 kb
Host smart-0e0f5dd8-0855-455e-8551-b0b497af1a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243021986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3243021986
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.276422731
Short name T284
Test name
Test status
Simulation time 618239415861 ps
CPU time 283.12 seconds
Started Apr 15 12:24:19 PM PDT 24
Finished Apr 15 12:29:03 PM PDT 24
Peak memory 190712 kb
Host smart-2a012428-498b-4d99-9b03-c4007b070cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276422731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.276422731
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3353594238
Short name T428
Test name
Test status
Simulation time 103282033 ps
CPU time 0.98 seconds
Started Apr 15 12:24:21 PM PDT 24
Finished Apr 15 12:24:22 PM PDT 24
Peak memory 182224 kb
Host smart-950de866-5a89-4ee8-a7f6-c69232775f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353594238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3353594238
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.64929883
Short name T20
Test name
Test status
Simulation time 166355164 ps
CPU time 0.75 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:24:30 PM PDT 24
Peak memory 212992 kb
Host smart-b92177ee-445f-42cf-b5ce-d460c87b667e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64929883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.64929883
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.131375429
Short name T348
Test name
Test status
Simulation time 57215762556 ps
CPU time 1690.93 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:52:40 PM PDT 24
Peak memory 190664 kb
Host smart-874f3c24-77cf-4f71-9cf8-4442aa432b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131375429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.131375429
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1415808508
Short name T42
Test name
Test status
Simulation time 63700328609 ps
CPU time 459.92 seconds
Started Apr 15 12:24:22 PM PDT 24
Finished Apr 15 12:32:02 PM PDT 24
Peak memory 205336 kb
Host smart-d0cef67c-cd05-4168-b673-fb36cf910fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415808508 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1415808508
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1634934482
Short name T300
Test name
Test status
Simulation time 661163001657 ps
CPU time 653.14 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:35:27 PM PDT 24
Peak memory 182492 kb
Host smart-40ada3b1-912e-4050-ba0c-b717401280fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634934482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1634934482
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2398531740
Short name T392
Test name
Test status
Simulation time 827620506123 ps
CPU time 292.15 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:29:35 PM PDT 24
Peak memory 182392 kb
Host smart-716b9945-00a6-461f-8666-26c248e34e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398531740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2398531740
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2357548856
Short name T249
Test name
Test status
Simulation time 1400339723335 ps
CPU time 547.52 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:33:43 PM PDT 24
Peak memory 190796 kb
Host smart-79f74793-4104-4edf-96dc-b4f4b4c2113e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357548856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2357548856
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.981028206
Short name T324
Test name
Test status
Simulation time 190899730644 ps
CPU time 515.03 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:33:05 PM PDT 24
Peak memory 182504 kb
Host smart-9e7b69ee-2214-4535-aa16-308b9bbc82f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981028206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.981028206
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.82566588
Short name T345
Test name
Test status
Simulation time 498173173872 ps
CPU time 905.38 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:39:48 PM PDT 24
Peak memory 182504 kb
Host smart-dac63e6f-1f50-4c65-bec2-7d729b1681f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82566588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.rv_timer_cfg_update_on_fly.82566588
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1008502333
Short name T402
Test name
Test status
Simulation time 974693217767 ps
CPU time 218.09 seconds
Started Apr 15 12:24:39 PM PDT 24
Finished Apr 15 12:28:18 PM PDT 24
Peak memory 182484 kb
Host smart-e0815b0e-5355-479b-ab2b-9fd9a4d7e803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008502333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1008502333
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2126342302
Short name T201
Test name
Test status
Simulation time 149050392009 ps
CPU time 197.69 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:27:51 PM PDT 24
Peak memory 190688 kb
Host smart-136f1345-64d9-4002-8143-2e1dd1004ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126342302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2126342302
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.604496474
Short name T400
Test name
Test status
Simulation time 296337869 ps
CPU time 0.92 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:24:34 PM PDT 24
Peak memory 182228 kb
Host smart-a835fd04-a3af-44e5-922e-dae2f5e9f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604496474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.604496474
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2852645470
Short name T375
Test name
Test status
Simulation time 167273045243 ps
CPU time 45.42 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:25:16 PM PDT 24
Peak memory 182468 kb
Host smart-df049474-230e-4c6b-9415-19eb82d62041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852645470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2852645470
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1039361601
Short name T55
Test name
Test status
Simulation time 243153674796 ps
CPU time 103.49 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:26:16 PM PDT 24
Peak memory 182492 kb
Host smart-d3ffc27a-105c-448e-8e83-71f471d0f5b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039361601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1039361601
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.820979554
Short name T416
Test name
Test status
Simulation time 25527055321 ps
CPU time 13.88 seconds
Started Apr 15 12:24:53 PM PDT 24
Finished Apr 15 12:25:07 PM PDT 24
Peak memory 194240 kb
Host smart-d6e80035-87cd-40ed-ba76-62a42b56b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820979554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.820979554
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2336767831
Short name T391
Test name
Test status
Simulation time 64951647629 ps
CPU time 49.33 seconds
Started Apr 15 12:24:53 PM PDT 24
Finished Apr 15 12:25:43 PM PDT 24
Peak memory 182576 kb
Host smart-2dd59dc2-c98d-4872-ab36-f1bbc03c5025
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336767831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2336767831
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.4020095644
Short name T365
Test name
Test status
Simulation time 174223902761 ps
CPU time 149.58 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:26:54 PM PDT 24
Peak memory 182488 kb
Host smart-535c5488-440f-45ce-b605-d3579b85b959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020095644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4020095644
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.94420919
Short name T192
Test name
Test status
Simulation time 3204522982 ps
CPU time 2.3 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:24:44 PM PDT 24
Peak memory 192440 kb
Host smart-bed53f2c-4b8c-48cc-a8fe-7c71924d770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94420919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.94420919
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1648700345
Short name T168
Test name
Test status
Simulation time 693026924871 ps
CPU time 1093.59 seconds
Started Apr 15 12:24:34 PM PDT 24
Finished Apr 15 12:42:48 PM PDT 24
Peak memory 195464 kb
Host smart-73c7a226-6b41-4582-a298-fb3f820f1ac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648700345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1648700345
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3320019640
Short name T320
Test name
Test status
Simulation time 296377232197 ps
CPU time 301.53 seconds
Started Apr 15 12:24:50 PM PDT 24
Finished Apr 15 12:29:52 PM PDT 24
Peak memory 182524 kb
Host smart-646a6848-7dcc-4b77-950f-828a3a5875b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320019640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3320019640
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3171214614
Short name T370
Test name
Test status
Simulation time 436146247487 ps
CPU time 136.85 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:27:04 PM PDT 24
Peak memory 182496 kb
Host smart-c33eaad1-6138-4de0-b53a-06dabbfed8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171214614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3171214614
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.214247877
Short name T195
Test name
Test status
Simulation time 327250288416 ps
CPU time 1786.12 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:54:17 PM PDT 24
Peak memory 190692 kb
Host smart-b9d3f068-8589-418b-888c-1f4e0630408f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214247877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.214247877
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1239506352
Short name T341
Test name
Test status
Simulation time 46462876864 ps
CPU time 125.9 seconds
Started Apr 15 12:24:44 PM PDT 24
Finished Apr 15 12:26:51 PM PDT 24
Peak memory 182448 kb
Host smart-c473f769-e499-4234-a014-fae60d9547b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239506352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1239506352
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1165942441
Short name T334
Test name
Test status
Simulation time 720442900100 ps
CPU time 376.23 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 182508 kb
Host smart-e9eed289-ee7e-40b2-bc14-42c670ebcae2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165942441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1165942441
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1239413907
Short name T396
Test name
Test status
Simulation time 993197810185 ps
CPU time 335.77 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:30:06 PM PDT 24
Peak memory 182436 kb
Host smart-334ce310-714e-4a5c-ba55-dcdd36efad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239413907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1239413907
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.464667595
Short name T235
Test name
Test status
Simulation time 242352000034 ps
CPU time 236.59 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:28:38 PM PDT 24
Peak memory 190780 kb
Host smart-5073649d-e4f3-4b20-ab0e-73b6a834e43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464667595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.464667595
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3743640654
Short name T366
Test name
Test status
Simulation time 402945665 ps
CPU time 0.69 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:24:42 PM PDT 24
Peak memory 182240 kb
Host smart-bb321785-7a6a-4699-88db-bf8b91418ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743640654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3743640654
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.4054801645
Short name T39
Test name
Test status
Simulation time 34944378508 ps
CPU time 79.48 seconds
Started Apr 15 12:24:44 PM PDT 24
Finished Apr 15 12:26:04 PM PDT 24
Peak memory 197132 kb
Host smart-754fe1be-8475-4815-bd51-77e0c29b71b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054801645 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.4054801645
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2387750725
Short name T54
Test name
Test status
Simulation time 197753254404 ps
CPU time 161.54 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:27:17 PM PDT 24
Peak memory 182512 kb
Host smart-55ceefd2-8be8-45b5-bd1a-62790c168814
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387750725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2387750725
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2624082152
Short name T425
Test name
Test status
Simulation time 78885084330 ps
CPU time 113.61 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:26:40 PM PDT 24
Peak memory 182460 kb
Host smart-c756ebf6-2d84-4bd8-85b2-bab77a47b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624082152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2624082152
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3806553189
Short name T359
Test name
Test status
Simulation time 11024129887 ps
CPU time 20.14 seconds
Started Apr 15 12:24:57 PM PDT 24
Finished Apr 15 12:25:18 PM PDT 24
Peak memory 182600 kb
Host smart-f35b82c7-5475-427d-b6d4-566a811636a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806553189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3806553189
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.207528935
Short name T3
Test name
Test status
Simulation time 115440738904 ps
CPU time 419.66 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 193920 kb
Host smart-70240363-3992-4aaf-bf22-d8706fcede7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207528935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.207528935
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2797018594
Short name T100
Test name
Test status
Simulation time 2217653259727 ps
CPU time 709.05 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:36:32 PM PDT 24
Peak memory 190712 kb
Host smart-a3343684-020d-4bce-9396-f1130775b255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797018594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2797018594
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1002328812
Short name T133
Test name
Test status
Simulation time 931121889318 ps
CPU time 462.68 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:32:10 PM PDT 24
Peak memory 182508 kb
Host smart-140dec16-fcfd-4aad-8534-437ce55c3f93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002328812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1002328812
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1791559104
Short name T449
Test name
Test status
Simulation time 329940722026 ps
CPU time 135.51 seconds
Started Apr 15 12:25:03 PM PDT 24
Finished Apr 15 12:27:19 PM PDT 24
Peak memory 182496 kb
Host smart-02eb80c7-8ab0-46d1-9c58-2a97fd734573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791559104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1791559104
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1077157484
Short name T293
Test name
Test status
Simulation time 547066339441 ps
CPU time 305.94 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:29:39 PM PDT 24
Peak memory 190668 kb
Host smart-88958592-fc3c-4eb3-959e-bfd11898edf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077157484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1077157484
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2163153628
Short name T424
Test name
Test status
Simulation time 1699007271 ps
CPU time 1.12 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:24:34 PM PDT 24
Peak memory 182432 kb
Host smart-84080db3-7754-491d-a5da-78a7b3efe5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163153628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2163153628
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2606998469
Short name T441
Test name
Test status
Simulation time 566169264835 ps
CPU time 204.47 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:28:04 PM PDT 24
Peak memory 182516 kb
Host smart-219a76f6-8834-441d-84e0-b326627f3c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606998469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2606998469
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3735531587
Short name T131
Test name
Test status
Simulation time 37448753993 ps
CPU time 61.07 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:25:26 PM PDT 24
Peak memory 182496 kb
Host smart-05cb4b31-34ae-426b-b55e-744f8fe7ec16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735531587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3735531587
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2896045857
Short name T362
Test name
Test status
Simulation time 756337864245 ps
CPU time 313.43 seconds
Started Apr 15 12:24:50 PM PDT 24
Finished Apr 15 12:30:04 PM PDT 24
Peak memory 182200 kb
Host smart-0906f866-f3b1-4490-a9bd-b3ee84b43682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896045857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2896045857
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1264161406
Short name T277
Test name
Test status
Simulation time 98616283964 ps
CPU time 161.16 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:27:11 PM PDT 24
Peak memory 190668 kb
Host smart-5cf955a5-b895-4597-89d8-9dfa46e7fd37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264161406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1264161406
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4119367030
Short name T44
Test name
Test status
Simulation time 1583925013 ps
CPU time 1.45 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:24:33 PM PDT 24
Peak memory 182184 kb
Host smart-48201aba-4664-44da-9750-52333169577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119367030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4119367030
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2748057869
Short name T260
Test name
Test status
Simulation time 1228352240789 ps
CPU time 614.82 seconds
Started Apr 15 12:24:52 PM PDT 24
Finished Apr 15 12:35:07 PM PDT 24
Peak memory 182508 kb
Host smart-7de4d50c-a532-4679-a36d-713e3810cd18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748057869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2748057869
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.4090031404
Short name T372
Test name
Test status
Simulation time 116911383614 ps
CPU time 52.11 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:25:22 PM PDT 24
Peak memory 182488 kb
Host smart-87fde935-cb4b-4bd7-9fbf-a0ba2458eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090031404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.4090031404
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.774066150
Short name T380
Test name
Test status
Simulation time 439470955 ps
CPU time 0.72 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:25:13 PM PDT 24
Peak memory 182232 kb
Host smart-30d5eb8c-37eb-425d-806f-95eaf72b07e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774066150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.774066150
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1157077256
Short name T255
Test name
Test status
Simulation time 2576448152629 ps
CPU time 1241.36 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:45:12 PM PDT 24
Peak memory 182484 kb
Host smart-266ecb12-1158-4b82-b3aa-79d264470383
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157077256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1157077256
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2323806682
Short name T32
Test name
Test status
Simulation time 25819780428 ps
CPU time 35.48 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:25:03 PM PDT 24
Peak memory 182480 kb
Host smart-7d50296f-43dd-4f4c-bd3d-ad5059bff2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323806682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2323806682
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2077676988
Short name T166
Test name
Test status
Simulation time 93124570246 ps
CPU time 272.51 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:28:57 PM PDT 24
Peak memory 190664 kb
Host smart-9fd9b14f-4706-49f9-9b78-fb9f88d28d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077676988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2077676988
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1789439067
Short name T281
Test name
Test status
Simulation time 97615986720 ps
CPU time 232.91 seconds
Started Apr 15 12:24:36 PM PDT 24
Finished Apr 15 12:28:29 PM PDT 24
Peak memory 190696 kb
Host smart-cea01935-434a-4e74-924d-0a59acd83896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789439067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1789439067
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.820080401
Short name T18
Test name
Test status
Simulation time 93645114 ps
CPU time 0.73 seconds
Started Apr 15 12:24:13 PM PDT 24
Finished Apr 15 12:24:14 PM PDT 24
Peak memory 212988 kb
Host smart-578222a7-c2eb-481d-913c-cfb8e4363256
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820080401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.820080401
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2991587334
Short name T49
Test name
Test status
Simulation time 279830036109 ps
CPU time 296.9 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:29:23 PM PDT 24
Peak memory 197160 kb
Host smart-650010c8-e722-4988-9450-c5b2b4815e32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991587334 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.2991587334
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3419652868
Short name T160
Test name
Test status
Simulation time 31417341697 ps
CPU time 31.46 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:25:04 PM PDT 24
Peak memory 182512 kb
Host smart-c17b4dfd-695c-4637-98cf-4464eb5a33e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419652868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3419652868
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.61758736
Short name T22
Test name
Test status
Simulation time 133098404169 ps
CPU time 224.96 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:28:14 PM PDT 24
Peak memory 182456 kb
Host smart-f9969cdc-1ad0-45de-888f-ed49a8f260ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61758736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.61758736
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.4031824269
Short name T268
Test name
Test status
Simulation time 914168336173 ps
CPU time 346.87 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:30:27 PM PDT 24
Peak memory 190636 kb
Host smart-05a9cd52-917a-42fa-b824-c5c47048f98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031824269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.4031824269
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.7001270
Short name T388
Test name
Test status
Simulation time 50231362 ps
CPU time 0.59 seconds
Started Apr 15 12:25:15 PM PDT 24
Finished Apr 15 12:25:16 PM PDT 24
Peak memory 182240 kb
Host smart-b3dbff8b-a42d-4660-8a9e-aca1efbcabc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7001270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.7001270
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1527937323
Short name T292
Test name
Test status
Simulation time 557240835285 ps
CPU time 899.01 seconds
Started Apr 15 12:25:08 PM PDT 24
Finished Apr 15 12:40:07 PM PDT 24
Peak memory 190708 kb
Host smart-a1bc0a4d-3faa-4d97-9b8b-3a4089ec8816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527937323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1527937323
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3796179433
Short name T446
Test name
Test status
Simulation time 164897029382 ps
CPU time 84.06 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:26:07 PM PDT 24
Peak memory 182496 kb
Host smart-a7855ad4-2a5a-4025-b6b3-4ef4db75a8e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796179433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3796179433
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.815038815
Short name T438
Test name
Test status
Simulation time 84734757042 ps
CPU time 42.86 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:25:10 PM PDT 24
Peak memory 182484 kb
Host smart-c2fa7066-a113-4896-816b-6205dacce982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815038815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.815038815
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3609271469
Short name T347
Test name
Test status
Simulation time 149228315176 ps
CPU time 227.93 seconds
Started Apr 15 12:25:10 PM PDT 24
Finished Apr 15 12:28:59 PM PDT 24
Peak memory 193160 kb
Host smart-f35220b7-422c-4ff8-9458-cc1fd087e39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609271469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3609271469
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1900664677
Short name T456
Test name
Test status
Simulation time 214615798 ps
CPU time 1.31 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:24:43 PM PDT 24
Peak memory 182388 kb
Host smart-18efd61a-f207-4abe-9e8c-d60c4e062303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900664677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1900664677
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1394415656
Short name T61
Test name
Test status
Simulation time 129237334588 ps
CPU time 183.73 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:27:37 PM PDT 24
Peak memory 195324 kb
Host smart-08197203-52ec-4b3c-b5eb-29b02c836b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394415656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1394415656
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.4184654150
Short name T242
Test name
Test status
Simulation time 41307197927 ps
CPU time 64.97 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:25:49 PM PDT 24
Peak memory 182524 kb
Host smart-2c3567c3-55e1-46dd-8a17-1b079f1c8bea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184654150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.4184654150
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2398824807
Short name T378
Test name
Test status
Simulation time 57377631789 ps
CPU time 93.78 seconds
Started Apr 15 12:25:00 PM PDT 24
Finished Apr 15 12:26:34 PM PDT 24
Peak memory 182440 kb
Host smart-7db90039-bab2-4ed9-a95d-b483f3ef89e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398824807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2398824807
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2620255496
Short name T336
Test name
Test status
Simulation time 101416589353 ps
CPU time 107.41 seconds
Started Apr 15 12:24:38 PM PDT 24
Finished Apr 15 12:26:27 PM PDT 24
Peak memory 190676 kb
Host smart-a0823a36-1a41-4450-b5e7-04dabb42874c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620255496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2620255496
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.979565178
Short name T184
Test name
Test status
Simulation time 82885028420 ps
CPU time 141.06 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:27:07 PM PDT 24
Peak memory 192992 kb
Host smart-7b7a94a8-d073-4cb5-a6d2-46ef16d1ae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979565178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.979565178
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3282572652
Short name T374
Test name
Test status
Simulation time 143387188949 ps
CPU time 215.38 seconds
Started Apr 15 12:24:33 PM PDT 24
Finished Apr 15 12:28:10 PM PDT 24
Peak memory 182448 kb
Host smart-41ed1e1e-12b4-4c4c-bb37-b64b139faba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282572652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3282572652
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3329919294
Short name T454
Test name
Test status
Simulation time 461654917178 ps
CPU time 483.49 seconds
Started Apr 15 12:24:47 PM PDT 24
Finished Apr 15 12:32:51 PM PDT 24
Peak memory 182500 kb
Host smart-90dd637b-a9c2-4c46-a936-f1db4dae3e1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329919294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3329919294
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3682385225
Short name T361
Test name
Test status
Simulation time 53541299418 ps
CPU time 77.33 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:25:50 PM PDT 24
Peak memory 182488 kb
Host smart-392d019a-7d36-40ee-a204-2a838e1aab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682385225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3682385225
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3273968519
Short name T338
Test name
Test status
Simulation time 133499304905 ps
CPU time 708.39 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:36:35 PM PDT 24
Peak memory 190672 kb
Host smart-d066680b-5d31-476b-aa59-a69093c3d1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273968519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3273968519
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1230577550
Short name T367
Test name
Test status
Simulation time 251832837 ps
CPU time 1.07 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:24:43 PM PDT 24
Peak memory 182428 kb
Host smart-2776e8d5-e7ed-4091-9a44-07c9d470ca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230577550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1230577550
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2376710031
Short name T413
Test name
Test status
Simulation time 2450151729 ps
CPU time 3.89 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:24:51 PM PDT 24
Peak memory 192192 kb
Host smart-a81007a7-df6e-4390-815a-d3878a5a1e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376710031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2376710031
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.4081045563
Short name T90
Test name
Test status
Simulation time 27341365043 ps
CPU time 209.39 seconds
Started Apr 15 12:24:48 PM PDT 24
Finished Apr 15 12:28:18 PM PDT 24
Peak memory 197160 kb
Host smart-93dc2399-ce66-4d55-b7db-367934ec9079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081045563 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.4081045563
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.878733391
Short name T234
Test name
Test status
Simulation time 664710096372 ps
CPU time 381.62 seconds
Started Apr 15 12:24:56 PM PDT 24
Finished Apr 15 12:31:18 PM PDT 24
Peak memory 182592 kb
Host smart-aabbcc08-cf38-4993-aca1-563897e2f920
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878733391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.878733391
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3836507315
Short name T401
Test name
Test status
Simulation time 307805243044 ps
CPU time 175.78 seconds
Started Apr 15 12:24:58 PM PDT 24
Finished Apr 15 12:27:55 PM PDT 24
Peak memory 182448 kb
Host smart-c61ecf00-0ca9-456e-bf71-06b39e3b09de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836507315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3836507315
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2862077156
Short name T420
Test name
Test status
Simulation time 27784441171 ps
CPU time 18.6 seconds
Started Apr 15 12:24:34 PM PDT 24
Finished Apr 15 12:24:53 PM PDT 24
Peak memory 194032 kb
Host smart-4204eacc-5132-4110-8c3c-bddd6c483541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862077156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2862077156
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1201294515
Short name T223
Test name
Test status
Simulation time 342108137334 ps
CPU time 1072.87 seconds
Started Apr 15 12:24:47 PM PDT 24
Finished Apr 15 12:42:41 PM PDT 24
Peak memory 190712 kb
Host smart-6f4c63c7-62b3-473d-9d99-7d9c82d34413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201294515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1201294515
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1403641935
Short name T270
Test name
Test status
Simulation time 78258211018 ps
CPU time 41.14 seconds
Started Apr 15 12:24:38 PM PDT 24
Finished Apr 15 12:25:20 PM PDT 24
Peak memory 182508 kb
Host smart-1261116e-cebf-4b65-9516-803d559cea5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403641935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1403641935
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.250616371
Short name T440
Test name
Test status
Simulation time 216684866926 ps
CPU time 269.54 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:28:58 PM PDT 24
Peak memory 182496 kb
Host smart-81e5ce14-6a67-4de9-a584-d9fdfd5e823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250616371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.250616371
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.925938515
Short name T229
Test name
Test status
Simulation time 168475502202 ps
CPU time 984.83 seconds
Started Apr 15 12:25:13 PM PDT 24
Finished Apr 15 12:41:38 PM PDT 24
Peak memory 182484 kb
Host smart-5dde6281-1fea-4e4d-b187-077f26aeac1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925938515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.925938515
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3769558197
Short name T186
Test name
Test status
Simulation time 45207313685 ps
CPU time 33.65 seconds
Started Apr 15 12:24:59 PM PDT 24
Finished Apr 15 12:25:33 PM PDT 24
Peak memory 190672 kb
Host smart-fffba7bf-70e5-4d52-9dbc-ea008972261a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769558197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3769558197
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.4033091764
Short name T399
Test name
Test status
Simulation time 31770472 ps
CPU time 0.54 seconds
Started Apr 15 12:24:48 PM PDT 24
Finished Apr 15 12:24:49 PM PDT 24
Peak memory 181812 kb
Host smart-86745f3c-345f-41b0-99b4-41a48b093f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033091764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.4033091764
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1441843765
Short name T37
Test name
Test status
Simulation time 98436931984 ps
CPU time 380.42 seconds
Started Apr 15 12:24:58 PM PDT 24
Finished Apr 15 12:31:19 PM PDT 24
Peak memory 197240 kb
Host smart-1b934c25-301f-4538-9ff9-2894d61a5930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441843765 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1441843765
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.915688407
Short name T13
Test name
Test status
Simulation time 988694946061 ps
CPU time 502.17 seconds
Started Apr 15 12:24:49 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 182500 kb
Host smart-52ac12dd-4013-4b2a-94e8-621cbe0ca192
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915688407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.915688407
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1400704944
Short name T393
Test name
Test status
Simulation time 765538588922 ps
CPU time 242.29 seconds
Started Apr 15 12:24:59 PM PDT 24
Finished Apr 15 12:29:02 PM PDT 24
Peak memory 182492 kb
Host smart-0ce447a1-8fc9-4a4d-a7f5-8b2e6e1abba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400704944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1400704944
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2250363483
Short name T111
Test name
Test status
Simulation time 679086155982 ps
CPU time 671.29 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:35:44 PM PDT 24
Peak memory 193808 kb
Host smart-3ba05d0f-01a1-4058-a1cc-c990141b49da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250363483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2250363483
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3627704033
Short name T147
Test name
Test status
Simulation time 200169105420 ps
CPU time 165.49 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:27:19 PM PDT 24
Peak memory 194248 kb
Host smart-d4e6d523-9aa8-413f-a4f8-c794c4d87427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627704033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3627704033
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4050210293
Short name T382
Test name
Test status
Simulation time 19856904 ps
CPU time 0.51 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:24:44 PM PDT 24
Peak memory 182236 kb
Host smart-71165455-ddb5-4f7d-9625-f39117e33cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050210293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4050210293
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2437564110
Short name T213
Test name
Test status
Simulation time 95821488346 ps
CPU time 289.93 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:29:26 PM PDT 24
Peak memory 197116 kb
Host smart-1b44b8ac-f3f0-45bf-8092-4dc03bf3965c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437564110 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2437564110
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2402291865
Short name T104
Test name
Test status
Simulation time 496357701619 ps
CPU time 870.37 seconds
Started Apr 15 12:25:00 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 182488 kb
Host smart-805003be-6b25-45f5-80ad-41fd1edf48e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402291865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2402291865
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3664467879
Short name T369
Test name
Test status
Simulation time 682459632496 ps
CPU time 257.26 seconds
Started Apr 15 12:24:32 PM PDT 24
Finished Apr 15 12:28:50 PM PDT 24
Peak memory 182480 kb
Host smart-d7768869-084c-49a0-9f70-5ddacd7161d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664467879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3664467879
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1326308297
Short name T164
Test name
Test status
Simulation time 146173748006 ps
CPU time 173.76 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:27:29 PM PDT 24
Peak memory 190696 kb
Host smart-3fc1109a-836b-4852-9937-b5bb8af69419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326308297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1326308297
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.240192645
Short name T215
Test name
Test status
Simulation time 66692823918 ps
CPU time 48.05 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:25:31 PM PDT 24
Peak memory 190688 kb
Host smart-be4ffc3e-c5e2-4a83-bcbc-0073a04d3fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240192645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.240192645
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3426242596
Short name T254
Test name
Test status
Simulation time 388230135461 ps
CPU time 695.55 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 182504 kb
Host smart-3d210317-3d63-4fc0-bff7-ba9ca9012bef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426242596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3426242596
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2789745120
Short name T422
Test name
Test status
Simulation time 42002948622 ps
CPU time 59.35 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:25:41 PM PDT 24
Peak memory 182480 kb
Host smart-b6f848f3-81c7-4fe2-91c9-9811bfa633c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789745120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2789745120
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3054879547
Short name T350
Test name
Test status
Simulation time 176553140684 ps
CPU time 524.78 seconds
Started Apr 15 12:24:59 PM PDT 24
Finished Apr 15 12:33:45 PM PDT 24
Peak memory 182516 kb
Host smart-d8287cd3-87cd-410e-b1a6-80f72c40ab23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054879547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3054879547
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3761648221
Short name T453
Test name
Test status
Simulation time 268468250 ps
CPU time 1.08 seconds
Started Apr 15 12:24:39 PM PDT 24
Finished Apr 15 12:24:41 PM PDT 24
Peak memory 193596 kb
Host smart-d8dfd588-d19b-4d3c-a057-4b422a7958a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761648221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3761648221
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1771590572
Short name T154
Test name
Test status
Simulation time 2040128249994 ps
CPU time 2374.99 seconds
Started Apr 15 12:24:55 PM PDT 24
Finished Apr 15 01:04:31 PM PDT 24
Peak memory 194900 kb
Host smart-99291723-2b0c-42ea-a85e-24472ba75fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771590572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1771590572
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1074808528
Short name T107
Test name
Test status
Simulation time 94201592487 ps
CPU time 151.4 seconds
Started Apr 15 12:24:41 PM PDT 24
Finished Apr 15 12:27:14 PM PDT 24
Peak memory 182504 kb
Host smart-d9592bf5-8a49-40c0-b927-1f8a64b34cfe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074808528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1074808528
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3487008317
Short name T363
Test name
Test status
Simulation time 632945800441 ps
CPU time 160.04 seconds
Started Apr 15 12:24:37 PM PDT 24
Finished Apr 15 12:27:17 PM PDT 24
Peak memory 182468 kb
Host smart-5782b444-f229-46da-89d5-5542fcc72585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487008317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3487008317
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2274380618
Short name T136
Test name
Test status
Simulation time 113463942331 ps
CPU time 177.34 seconds
Started Apr 15 12:24:39 PM PDT 24
Finished Apr 15 12:27:37 PM PDT 24
Peak memory 190700 kb
Host smart-a208af47-ed4e-4f96-90b6-d3caea9d1eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274380618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2274380618
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2543371133
Short name T421
Test name
Test status
Simulation time 144694755513 ps
CPU time 59.12 seconds
Started Apr 15 12:24:58 PM PDT 24
Finished Apr 15 12:25:58 PM PDT 24
Peak memory 182344 kb
Host smart-edbab909-3272-4077-9134-2cce0ed9f3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543371133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2543371133
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3956674368
Short name T417
Test name
Test status
Simulation time 199382307570 ps
CPU time 146.22 seconds
Started Apr 15 12:24:23 PM PDT 24
Finished Apr 15 12:26:50 PM PDT 24
Peak memory 182404 kb
Host smart-f5ead6dc-0da6-4a09-8a31-4a7eab1f4f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956674368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3956674368
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2728443031
Short name T26
Test name
Test status
Simulation time 54684689889 ps
CPU time 54.43 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:25:22 PM PDT 24
Peak memory 182504 kb
Host smart-d7263f44-f6d9-4f26-ac8e-a8b359981a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728443031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2728443031
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1514671176
Short name T404
Test name
Test status
Simulation time 676305875 ps
CPU time 1.6 seconds
Started Apr 15 12:24:40 PM PDT 24
Finished Apr 15 12:24:42 PM PDT 24
Peak memory 193296 kb
Host smart-a0cccda8-5dca-46a3-9dfe-b7f68161d2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514671176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1514671176
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1940853345
Short name T11
Test name
Test status
Simulation time 1947913637836 ps
CPU time 1892.68 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:56:17 PM PDT 24
Peak memory 190680 kb
Host smart-6e02ecf0-591a-4f97-a838-f77b5e617c58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940853345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1940853345
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1994591611
Short name T138
Test name
Test status
Simulation time 85711591552 ps
CPU time 570 seconds
Started Apr 15 12:24:47 PM PDT 24
Finished Apr 15 12:34:18 PM PDT 24
Peak memory 190704 kb
Host smart-564dcf50-d3b3-4034-b004-b0b47094a8ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994591611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1994591611
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1445116561
Short name T114
Test name
Test status
Simulation time 290828023185 ps
CPU time 567.11 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:34:13 PM PDT 24
Peak memory 190668 kb
Host smart-ce3bc03e-f498-45da-93af-47361485cd17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445116561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1445116561
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2820361769
Short name T356
Test name
Test status
Simulation time 997420268662 ps
CPU time 164.03 seconds
Started Apr 15 12:24:53 PM PDT 24
Finished Apr 15 12:27:37 PM PDT 24
Peak memory 182572 kb
Host smart-886463b2-bb29-4d57-a1fe-e0e1fec6339c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820361769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2820361769
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2828076319
Short name T53
Test name
Test status
Simulation time 36031608694 ps
CPU time 15.23 seconds
Started Apr 15 12:24:51 PM PDT 24
Finished Apr 15 12:25:07 PM PDT 24
Peak memory 182324 kb
Host smart-d749fc9c-45b1-447f-9fc3-d55c9d723f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828076319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2828076319
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1207629051
Short name T146
Test name
Test status
Simulation time 218851698805 ps
CPU time 884.18 seconds
Started Apr 15 12:26:10 PM PDT 24
Finished Apr 15 12:40:55 PM PDT 24
Peak memory 188956 kb
Host smart-3c54e20e-d2e6-45f8-9f9a-7d06fdda679a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207629051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1207629051
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2981972687
Short name T252
Test name
Test status
Simulation time 133372045217 ps
CPU time 497.6 seconds
Started Apr 15 12:25:05 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 190692 kb
Host smart-a76cc52f-2e7a-4015-a677-c4aa9654d776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981972687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2981972687
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.327092806
Short name T180
Test name
Test status
Simulation time 325510149015 ps
CPU time 345.36 seconds
Started Apr 15 12:24:47 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 190688 kb
Host smart-d35ef190-4dac-4a99-b4ad-f9652f174bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327092806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.327092806
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3975020155
Short name T239
Test name
Test status
Simulation time 192351962966 ps
CPU time 177.4 seconds
Started Apr 15 12:24:47 PM PDT 24
Finished Apr 15 12:27:45 PM PDT 24
Peak memory 194256 kb
Host smart-2ec1e9f6-37c3-405f-bd2d-c2d800ab32d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975020155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3975020155
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3667717566
Short name T126
Test name
Test status
Simulation time 69413075051 ps
CPU time 15.01 seconds
Started Apr 15 12:24:51 PM PDT 24
Finished Apr 15 12:25:06 PM PDT 24
Peak memory 182468 kb
Host smart-114d77e1-e23a-421c-b18e-703ad64fcee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667717566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3667717566
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3299853525
Short name T429
Test name
Test status
Simulation time 126540328851 ps
CPU time 35.52 seconds
Started Apr 15 12:26:20 PM PDT 24
Finished Apr 15 12:26:56 PM PDT 24
Peak memory 182024 kb
Host smart-5209f85a-c9e3-4e72-bb56-9e6e3839375f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299853525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3299853525
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2084248254
Short name T295
Test name
Test status
Simulation time 151640419454 ps
CPU time 260.14 seconds
Started Apr 15 12:24:29 PM PDT 24
Finished Apr 15 12:28:51 PM PDT 24
Peak memory 182428 kb
Host smart-f43bc2d4-4a91-46d9-a0bd-f362202d6e70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084248254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2084248254
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1912654760
Short name T437
Test name
Test status
Simulation time 261224274610 ps
CPU time 94.24 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:26:04 PM PDT 24
Peak memory 182500 kb
Host smart-c50abba4-048a-4e97-8d6f-0e037b91755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912654760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1912654760
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1174720057
Short name T51
Test name
Test status
Simulation time 217625136220 ps
CPU time 196.97 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:27:47 PM PDT 24
Peak memory 190696 kb
Host smart-0bf6c316-892b-4fdd-a352-45375381f725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174720057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1174720057
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1902576636
Short name T407
Test name
Test status
Simulation time 37148447223 ps
CPU time 63.96 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:25:34 PM PDT 24
Peak memory 182496 kb
Host smart-d46dd82c-aaf4-404f-a246-2cdd755a1f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902576636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1902576636
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1368588228
Short name T63
Test name
Test status
Simulation time 1054403849959 ps
CPU time 824.42 seconds
Started Apr 15 12:24:22 PM PDT 24
Finished Apr 15 12:38:08 PM PDT 24
Peak memory 190688 kb
Host smart-8b0b8d57-e4e4-4782-9afe-aed13f2e3653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368588228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1368588228
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.311807756
Short name T225
Test name
Test status
Simulation time 262895464671 ps
CPU time 197.26 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:28:00 PM PDT 24
Peak memory 190664 kb
Host smart-94567006-1cd2-4865-9dba-56c04f08885f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311807756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.311807756
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2018850976
Short name T386
Test name
Test status
Simulation time 3764324760 ps
CPU time 133.33 seconds
Started Apr 15 12:26:10 PM PDT 24
Finished Apr 15 12:28:24 PM PDT 24
Peak memory 180732 kb
Host smart-7c2fa425-c245-4aa7-95c6-fb5bbcdacca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018850976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2018850976
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2950086673
Short name T279
Test name
Test status
Simulation time 85893579272 ps
CPU time 146.02 seconds
Started Apr 15 12:24:55 PM PDT 24
Finished Apr 15 12:27:22 PM PDT 24
Peak memory 190712 kb
Host smart-da12596a-a83f-4ea4-b665-0d74de224770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950086673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2950086673
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2626115275
Short name T296
Test name
Test status
Simulation time 50162701551 ps
CPU time 240.26 seconds
Started Apr 15 12:24:58 PM PDT 24
Finished Apr 15 12:28:59 PM PDT 24
Peak memory 190700 kb
Host smart-a7e1acec-8a6a-4346-b6be-230472f9a790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626115275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2626115275
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.14382249
Short name T117
Test name
Test status
Simulation time 109642953519 ps
CPU time 456.73 seconds
Started Apr 15 12:24:42 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 190664 kb
Host smart-c11c3764-26dc-4737-a70e-a1b0cae496fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14382249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.14382249
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3158339031
Short name T194
Test name
Test status
Simulation time 669105898548 ps
CPU time 720.91 seconds
Started Apr 15 12:24:35 PM PDT 24
Finished Apr 15 12:36:37 PM PDT 24
Peak memory 190712 kb
Host smart-f64bddcd-a0c3-4414-857a-674f0bf02408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158339031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3158339031
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2317856498
Short name T306
Test name
Test status
Simulation time 51929821792 ps
CPU time 47.47 seconds
Started Apr 15 12:24:44 PM PDT 24
Finished Apr 15 12:25:32 PM PDT 24
Peak memory 190980 kb
Host smart-03f53c6e-e453-4ebd-8301-cb0bfc4c89bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317856498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2317856498
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1833507
Short name T143
Test name
Test status
Simulation time 1094115737520 ps
CPU time 607.43 seconds
Started Apr 15 12:24:30 PM PDT 24
Finished Apr 15 12:34:39 PM PDT 24
Peak memory 182504 kb
Host smart-3c9f2a84-d358-488b-8f5c-956751398f80
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.r
v_timer_cfg_update_on_fly.1833507
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3130672602
Short name T377
Test name
Test status
Simulation time 706935322316 ps
CPU time 275.5 seconds
Started Apr 15 12:24:23 PM PDT 24
Finished Apr 15 12:28:59 PM PDT 24
Peak memory 182456 kb
Host smart-3f1b05de-3975-48b8-8a57-f224c7726ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130672602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3130672602
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2879976095
Short name T105
Test name
Test status
Simulation time 177737204913 ps
CPU time 519.83 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 190708 kb
Host smart-4d2fc0fd-8c40-4017-866f-cca2a50b629a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879976095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2879976095
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.456603363
Short name T349
Test name
Test status
Simulation time 69504017873 ps
CPU time 121.47 seconds
Started Apr 15 12:24:27 PM PDT 24
Finished Apr 15 12:26:29 PM PDT 24
Peak memory 182512 kb
Host smart-04508ed0-c854-433f-a6c6-369b1e0deff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456603363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.456603363
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3944873197
Short name T36
Test name
Test status
Simulation time 69248649465 ps
CPU time 365.03 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:30:31 PM PDT 24
Peak memory 205328 kb
Host smart-3f79fca0-6261-4b6a-ac70-c0467dafd885
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944873197 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3944873197
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3107111280
Short name T318
Test name
Test status
Simulation time 341525885257 ps
CPU time 633.37 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:35:18 PM PDT 24
Peak memory 190624 kb
Host smart-82aadff4-d4c5-40a5-a8be-d411cdf9b8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107111280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3107111280
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.429302871
Short name T259
Test name
Test status
Simulation time 427344887732 ps
CPU time 109.83 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:26:34 PM PDT 24
Peak memory 182416 kb
Host smart-e4fbd69d-4639-4f58-84c7-906830fdc78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429302871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.429302871
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.381499701
Short name T411
Test name
Test status
Simulation time 23400785912 ps
CPU time 183.63 seconds
Started Apr 15 12:25:12 PM PDT 24
Finished Apr 15 12:28:17 PM PDT 24
Peak memory 182480 kb
Host smart-94fe44f6-9304-4d5b-b4f1-8a23eb338d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381499701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.381499701
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.67694748
Short name T451
Test name
Test status
Simulation time 93171946687 ps
CPU time 304.58 seconds
Started Apr 15 12:24:56 PM PDT 24
Finished Apr 15 12:30:01 PM PDT 24
Peak memory 190716 kb
Host smart-99f35e40-ccbe-42e0-acc2-97110cae79be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67694748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.67694748
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.453357655
Short name T6
Test name
Test status
Simulation time 26887241871 ps
CPU time 22.81 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:25:08 PM PDT 24
Peak memory 182492 kb
Host smart-96ae01c5-238f-4b30-a5d3-181a3f679955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453357655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.453357655
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3477812926
Short name T276
Test name
Test status
Simulation time 626193433252 ps
CPU time 2309.13 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 01:03:15 PM PDT 24
Peak memory 190696 kb
Host smart-0a63c45b-a7b8-4c0d-8668-de9953f90fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477812926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3477812926
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3746067587
Short name T257
Test name
Test status
Simulation time 305119385251 ps
CPU time 675.31 seconds
Started Apr 15 12:24:46 PM PDT 24
Finished Apr 15 12:36:02 PM PDT 24
Peak memory 190688 kb
Host smart-9a113ac7-c95b-4b4d-bf70-cb9e039d191f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746067587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3746067587
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1823876812
Short name T444
Test name
Test status
Simulation time 922615909392 ps
CPU time 238.58 seconds
Started Apr 15 12:24:26 PM PDT 24
Finished Apr 15 12:28:26 PM PDT 24
Peak memory 182464 kb
Host smart-391d1612-eaca-4ab0-964c-67ca5e6d0dbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823876812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1823876812
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_random.464480800
Short name T269
Test name
Test status
Simulation time 32064597700 ps
CPU time 53.67 seconds
Started Apr 15 12:24:28 PM PDT 24
Finished Apr 15 12:25:24 PM PDT 24
Peak memory 182468 kb
Host smart-3be7b5e3-e427-4ed1-af3f-72f0c0c092db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464480800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.464480800
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2283575102
Short name T289
Test name
Test status
Simulation time 142120798718 ps
CPU time 76.3 seconds
Started Apr 15 12:24:24 PM PDT 24
Finished Apr 15 12:25:41 PM PDT 24
Peak memory 190628 kb
Host smart-9c87ef4e-d22f-45c7-bef1-a6f0d2d2b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283575102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2283575102
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1908409575
Short name T232
Test name
Test status
Simulation time 202813273094 ps
CPU time 260.62 seconds
Started Apr 15 12:24:50 PM PDT 24
Finished Apr 15 12:29:11 PM PDT 24
Peak memory 190704 kb
Host smart-0c3ddf50-d32b-4720-8db9-4133daad9ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908409575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1908409575
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1343916709
Short name T353
Test name
Test status
Simulation time 329593799539 ps
CPU time 234.02 seconds
Started Apr 15 12:25:02 PM PDT 24
Finished Apr 15 12:28:57 PM PDT 24
Peak memory 193664 kb
Host smart-84332835-d74c-47ca-a1da-a7d9ff9a05d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343916709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1343916709
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1187490071
Short name T121
Test name
Test status
Simulation time 47550322202 ps
CPU time 268.23 seconds
Started Apr 15 12:24:59 PM PDT 24
Finished Apr 15 12:29:28 PM PDT 24
Peak memory 190660 kb
Host smart-c2245cba-6cb3-4a0c-8454-c21ebedefeae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187490071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1187490071
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3819863619
Short name T224
Test name
Test status
Simulation time 124424212892 ps
CPU time 386.76 seconds
Started Apr 15 12:24:43 PM PDT 24
Finished Apr 15 12:31:11 PM PDT 24
Peak memory 190660 kb
Host smart-099314c5-ed5d-4ce2-a5d3-7f15b8fdf1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819863619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3819863619
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2401259329
Short name T323
Test name
Test status
Simulation time 203682946769 ps
CPU time 175.39 seconds
Started Apr 15 12:24:45 PM PDT 24
Finished Apr 15 12:27:41 PM PDT 24
Peak memory 190696 kb
Host smart-257258ad-9ffb-44b6-8623-5ccc99a84bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401259329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2401259329
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2259300730
Short name T155
Test name
Test status
Simulation time 89644244523 ps
CPU time 1873.68 seconds
Started Apr 15 12:24:56 PM PDT 24
Finished Apr 15 12:56:10 PM PDT 24
Peak memory 190800 kb
Host smart-24d4cec2-5bb7-4d74-a7e6-0b57e1bd6c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259300730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2259300730
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.853414703
Short name T217
Test name
Test status
Simulation time 474300604034 ps
CPU time 227.78 seconds
Started Apr 15 12:25:00 PM PDT 24
Finished Apr 15 12:28:48 PM PDT 24
Peak memory 190684 kb
Host smart-5375a498-a0df-41b2-bffb-c507aaed2d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853414703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.853414703
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.685946385
Short name T278
Test name
Test status
Simulation time 262450499038 ps
CPU time 322.89 seconds
Started Apr 15 12:24:50 PM PDT 24
Finished Apr 15 12:30:14 PM PDT 24
Peak memory 190684 kb
Host smart-4c4fedb9-0167-4ee4-ba60-6df55c26678e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685946385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.685946385
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3495637587
Short name T202
Test name
Test status
Simulation time 366261086660 ps
CPU time 404.09 seconds
Started Apr 15 12:24:50 PM PDT 24
Finished Apr 15 12:31:35 PM PDT 24
Peak memory 190676 kb
Host smart-8c775ff7-6b10-456c-b952-1d850afceb58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495637587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3495637587
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.718936672
Short name T443
Test name
Test status
Simulation time 642291917491 ps
CPU time 325.65 seconds
Started Apr 15 12:24:23 PM PDT 24
Finished Apr 15 12:29:49 PM PDT 24
Peak memory 182500 kb
Host smart-714734f7-e83a-407d-bf61-a0d9fe5f2631
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718936672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.718936672
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1729580883
Short name T25
Test name
Test status
Simulation time 172425636101 ps
CPU time 124.62 seconds
Started Apr 15 12:24:31 PM PDT 24
Finished Apr 15 12:26:38 PM PDT 24
Peak memory 182472 kb
Host smart-abecce96-3d19-4ed3-9787-602fa3cf03b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729580883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1729580883
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3214940810
Short name T311
Test name
Test status
Simulation time 324567121992 ps
CPU time 255.33 seconds
Started Apr 15 12:24:38 PM PDT 24
Finished Apr 15 12:28:55 PM PDT 24
Peak memory 190696 kb
Host smart-54ee6a8e-d392-4ba7-9190-69dd7188aceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214940810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3214940810
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2937182170
Short name T458
Test name
Test status
Simulation time 54804749 ps
CPU time 0.62 seconds
Started Apr 15 12:24:37 PM PDT 24
Finished Apr 15 12:24:38 PM PDT 24
Peak memory 182204 kb
Host smart-4b64048e-ccb6-4bd3-8e81-69996c61303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937182170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2937182170
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.1397522541
Short name T314
Test name
Test status
Simulation time 104966790316 ps
CPU time 90.96 seconds
Started Apr 15 12:24:52 PM PDT 24
Finished Apr 15 12:26:23 PM PDT 24
Peak memory 190788 kb
Host smart-dd9cd23f-c57e-40db-a2e7-2cbd31499af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397522541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1397522541
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1985771307
Short name T403
Test name
Test status
Simulation time 160472233139 ps
CPU time 77.77 seconds
Started Apr 15 12:24:56 PM PDT 24
Finished Apr 15 12:26:15 PM PDT 24
Peak memory 182532 kb
Host smart-7c82e6dc-7c08-4cd7-a386-1fa37d2d10bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985771307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1985771307
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.227636119
Short name T24
Test name
Test status
Simulation time 65555580952 ps
CPU time 112.69 seconds
Started Apr 15 12:25:04 PM PDT 24
Finished Apr 15 12:26:57 PM PDT 24
Peak memory 190684 kb
Host smart-8e8e0ddd-e9a0-49e8-9709-3f6ac38e1fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227636119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.227636119
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1531968163
Short name T436
Test name
Test status
Simulation time 442013206821 ps
CPU time 311.3 seconds
Started Apr 15 12:24:48 PM PDT 24
Finished Apr 15 12:30:00 PM PDT 24
Peak memory 190700 kb
Host smart-7d216365-6c95-4627-8d76-ef7cb81ec8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531968163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1531968163
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.504186119
Short name T248
Test name
Test status
Simulation time 316523947080 ps
CPU time 165.01 seconds
Started Apr 15 12:25:04 PM PDT 24
Finished Apr 15 12:27:49 PM PDT 24
Peak memory 190724 kb
Host smart-bb4e01b9-9e13-44f1-aaae-c5603fae3054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504186119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.504186119
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3708576221
Short name T151
Test name
Test status
Simulation time 61741981585 ps
CPU time 2148.86 seconds
Started Apr 15 12:25:01 PM PDT 24
Finished Apr 15 01:00:51 PM PDT 24
Peak memory 190684 kb
Host smart-2e349f8d-c3d7-42a9-bf31-48b26a39a986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708576221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3708576221
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.420427872
Short name T261
Test name
Test status
Simulation time 832319128436 ps
CPU time 334.61 seconds
Started Apr 15 12:24:59 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 190684 kb
Host smart-0271fcb5-6cf1-4e06-9c21-4a316aab81eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420427872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.420427872
Directory /workspace/99.rv_timer_random/latest
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