Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.36	98.73	100.00		100.00	100.00	99.77

Total test records in report: 582

T508	/workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2532534924	Apr 16 12:25:02 PM PDT 24	Apr 16 12:25:07 PM PDT 24	46491049 ps
T509	/workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1627232360	Apr 16 12:21:01 PM PDT 24	Apr 16 12:21:04 PM PDT 24	32732362 ps
T100	/workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1713826904	Apr 16 12:21:05 PM PDT 24	Apr 16 12:21:09 PM PDT 24	414898839 ps
T80	/workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2610319059	Apr 16 12:24:36 PM PDT 24	Apr 16 12:24:40 PM PDT 24	54973026 ps
T510	/workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3410411300	Apr 16 12:24:37 PM PDT 24	Apr 16 12:24:40 PM PDT 24	34390362 ps
T88	/workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4069819232	Apr 16 12:21:43 PM PDT 24	Apr 16 12:21:46 PM PDT 24	17327371 ps
T511	/workspace/coverage/cover_reg_top/0.rv_timer_intr_test.631602108	Apr 16 12:17:54 PM PDT 24	Apr 16 12:17:56 PM PDT 24	51897426 ps
T512	/workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.698482820	Apr 16 12:25:03 PM PDT 24	Apr 16 12:25:08 PM PDT 24	33776422 ps
T513	/workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3401408164	Apr 16 12:25:14 PM PDT 24	Apr 16 12:25:18 PM PDT 24	58820624 ps
T514	/workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3414783711	Apr 16 12:24:34 PM PDT 24	Apr 16 12:24:37 PM PDT 24	35812208 ps
T515	/workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1571812807	Apr 16 12:24:43 PM PDT 24	Apr 16 12:24:45 PM PDT 24	74927118 ps
T516	/workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2040065243	Apr 16 12:19:01 PM PDT 24	Apr 16 12:19:02 PM PDT 24	31969800 ps
T517	/workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3979564830	Apr 16 12:25:10 PM PDT 24	Apr 16 12:25:15 PM PDT 24	33788644 ps
T81	/workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.412671712	Apr 16 12:24:52 PM PDT 24	Apr 16 12:24:54 PM PDT 24	11057415 ps
T518	/workspace/coverage/cover_reg_top/28.rv_timer_intr_test.656678299	Apr 16 12:24:56 PM PDT 24	Apr 16 12:24:59 PM PDT 24	17675809 ps
T519	/workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2156736991	Apr 16 12:22:59 PM PDT 24	Apr 16 12:23:03 PM PDT 24	13388148 ps
T520	/workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1436563838	Apr 16 12:24:56 PM PDT 24	Apr 16 12:24:59 PM PDT 24	15426107 ps
T521	/workspace/coverage/cover_reg_top/2.rv_timer_intr_test.343411556	Apr 16 12:22:24 PM PDT 24	Apr 16 12:22:27 PM PDT 24	46576190 ps
T522	/workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3237376058	Apr 16 12:24:43 PM PDT 24	Apr 16 12:24:45 PM PDT 24	16428804 ps
T523	/workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.667248369	Apr 16 12:24:35 PM PDT 24	Apr 16 12:24:40 PM PDT 24	199967014 ps
T524	/workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1753086721	Apr 16 12:24:49 PM PDT 24	Apr 16 12:24:52 PM PDT 24	108332624 ps
T525	/workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3925271706	Apr 16 12:25:01 PM PDT 24	Apr 16 12:25:07 PM PDT 24	164024082 ps
T526	/workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2896006739	Apr 16 12:24:47 PM PDT 24	Apr 16 12:24:48 PM PDT 24	43129394 ps
T527	/workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2373844017	Apr 16 12:24:57 PM PDT 24	Apr 16 12:25:01 PM PDT 24	247134819 ps
T528	/workspace/coverage/cover_reg_top/35.rv_timer_intr_test.563438496	Apr 16 12:24:52 PM PDT 24	Apr 16 12:24:53 PM PDT 24	25362193 ps
T529	/workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1923709850	Apr 16 12:24:32 PM PDT 24	Apr 16 12:24:35 PM PDT 24	13723559 ps
T530	/workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.143464931	Apr 16 12:24:52 PM PDT 24	Apr 16 12:24:54 PM PDT 24	57884069 ps
T531	/workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.985322226	Apr 16 12:25:02 PM PDT 24	Apr 16 12:25:07 PM PDT 24	23415229 ps
T532	/workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2951003297	Apr 16 12:24:36 PM PDT 24	Apr 16 12:24:41 PM PDT 24	201089030 ps
T533	/workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2651481106	Apr 16 12:25:01 PM PDT 24	Apr 16 12:25:05 PM PDT 24	15143928 ps
T534	/workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1042611004	Apr 16 12:24:45 PM PDT 24	Apr 16 12:24:47 PM PDT 24	16300368 ps
T535	/workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1765350714	Apr 16 12:24:32 PM PDT 24	Apr 16 12:24:37 PM PDT 24	403616449 ps
T536	/workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2720823054	Apr 16 12:24:42 PM PDT 24	Apr 16 12:24:44 PM PDT 24	39956272 ps
T537	/workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4066062210	Apr 16 12:25:21 PM PDT 24	Apr 16 12:25:26 PM PDT 24	85089938 ps
T538	/workspace/coverage/cover_reg_top/42.rv_timer_intr_test.995676418	Apr 16 12:25:02 PM PDT 24	Apr 16 12:25:07 PM PDT 24	10993250 ps
T539	/workspace/coverage/cover_reg_top/15.rv_timer_intr_test.838781122	Apr 16 12:24:57 PM PDT 24	Apr 16 12:24:59 PM PDT 24	50329231 ps
T540	/workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1659870975	Apr 16 12:25:14 PM PDT 24	Apr 16 12:25:17 PM PDT 24	51753298 ps
T83	/workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.44645590	Apr 16 12:22:42 PM PDT 24	Apr 16 12:22:48 PM PDT 24	20699734 ps
T541	/workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2065756889	Apr 16 12:24:56 PM PDT 24	Apr 16 12:24:59 PM PDT 24	16334187 ps
T542	/workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1957011383	Apr 16 12:24:32 PM PDT 24	Apr 16 12:24:36 PM PDT 24	169690393 ps
T543	/workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3375794188	Apr 16 12:24:29 PM PDT 24	Apr 16 12:24:33 PM PDT 24	22380147 ps
T544	/workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3966211488	Apr 16 12:25:12 PM PDT 24	Apr 16 12:25:16 PM PDT 24	65519407 ps
T545	/workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.309519406	Apr 16 12:20:33 PM PDT 24	Apr 16 12:20:34 PM PDT 24	44743125 ps
T546	/workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3450328750	Apr 16 12:24:29 PM PDT 24	Apr 16 12:24:33 PM PDT 24	16334422 ps
T547	/workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3129217127	Apr 16 12:25:02 PM PDT 24	Apr 16 12:25:06 PM PDT 24	130773170 ps
T548	/workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2717310829	Apr 16 12:24:58 PM PDT 24	Apr 16 12:25:01 PM PDT 24	33642983 ps
T549	/workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.669381888	Apr 16 12:25:00 PM PDT 24	Apr 16 12:25:04 PM PDT 24	44504341 ps
T550	/workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.608696338	Apr 16 12:24:31 PM PDT 24	Apr 16 12:24:35 PM PDT 24	26741107 ps
T551	/workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.709439976	Apr 16 12:24:38 PM PDT 24	Apr 16 12:24:41 PM PDT 24	67202525 ps
T101	/workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1256078368	Apr 16 12:24:49 PM PDT 24	Apr 16 12:24:52 PM PDT 24	397362658 ps
T552	/workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1593544633	Apr 16 12:24:42 PM PDT 24	Apr 16 12:24:44 PM PDT 24	16297067 ps
T553	/workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2833173585	Apr 16 12:21:43 PM PDT 24	Apr 16 12:21:47 PM PDT 24	75531468 ps
T554	/workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2905424403	Apr 16 12:24:40 PM PDT 24	Apr 16 12:24:43 PM PDT 24	58952802 ps
T555	/workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4069097396	Apr 16 12:24:56 PM PDT 24	Apr 16 12:24:59 PM PDT 24	21017828 ps
T556	/workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4248517223	Apr 16 12:24:59 PM PDT 24	Apr 16 12:25:01 PM PDT 24	51232911 ps
T557	/workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1813907178	Apr 16 12:24:29 PM PDT 24	Apr 16 12:24:35 PM PDT 24	62315543 ps
T558	/workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.967620322	Apr 16 12:24:37 PM PDT 24	Apr 16 12:24:41 PM PDT 24	227687990 ps
T559	/workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4059997920	Apr 16 12:25:18 PM PDT 24	Apr 16 12:25:24 PM PDT 24	83815946 ps
T560	/workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1187710958	Apr 16 12:24:46 PM PDT 24	Apr 16 12:24:48 PM PDT 24	336683794 ps
T561	/workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1132959726	Apr 16 12:22:24 PM PDT 24	Apr 16 12:22:27 PM PDT 24	34773447 ps
T562	/workspace/coverage/cover_reg_top/12.rv_timer_intr_test.155668129	Apr 16 12:25:03 PM PDT 24	Apr 16 12:25:08 PM PDT 24	38815309 ps
T563	/workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1049693130	Apr 16 12:25:14 PM PDT 24	Apr 16 12:25:18 PM PDT 24	16920820 ps
T564	/workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1866611361	Apr 16 12:25:00 PM PDT 24	Apr 16 12:25:03 PM PDT 24	19946852 ps
T565	/workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3141281397	Apr 16 12:24:41 PM PDT 24	Apr 16 12:24:44 PM PDT 24	76997076 ps
T566	/workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2338616575	Apr 16 12:25:12 PM PDT 24	Apr 16 12:25:16 PM PDT 24	56450147 ps
T567	/workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.359584645	Apr 16 12:24:58 PM PDT 24	Apr 16 12:25:01 PM PDT 24	86482358 ps
T568	/workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3840366991	Apr 16 12:20:56 PM PDT 24	Apr 16 12:20:59 PM PDT 24	18221623 ps
T569	/workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2809895489	Apr 16 12:24:40 PM PDT 24	Apr 16 12:24:43 PM PDT 24	55485846 ps
T570	/workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.298056814	Apr 16 12:24:30 PM PDT 24	Apr 16 12:24:35 PM PDT 24	125513767 ps
T571	/workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2028154350	Apr 16 12:24:34 PM PDT 24	Apr 16 12:24:38 PM PDT 24	566012472 ps
T572	/workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.58456979	Apr 16 12:24:56 PM PDT 24	Apr 16 12:24:58 PM PDT 24	70029487 ps
T573	/workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4112924528	Apr 16 12:20:57 PM PDT 24	Apr 16 12:20:59 PM PDT 24	412277915 ps
T574	/workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3786414838	Apr 16 12:24:55 PM PDT 24	Apr 16 12:24:59 PM PDT 24	20419840 ps
T575	/workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.777472358	Apr 16 12:24:57 PM PDT 24	Apr 16 12:25:00 PM PDT 24	24550043 ps
T82	/workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3789890507	Apr 16 12:24:47 PM PDT 24	Apr 16 12:24:48 PM PDT 24	17169582 ps
T576	/workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2620805025	Apr 16 12:24:59 PM PDT 24	Apr 16 12:25:03 PM PDT 24	30527902 ps
T577	/workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2981407268	Apr 16 12:24:48 PM PDT 24	Apr 16 12:24:50 PM PDT 24	18707145 ps
T578	/workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2306469304	Apr 16 12:24:41 PM PDT 24	Apr 16 12:24:43 PM PDT 24	47248933 ps
T579	/workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.444060589	Apr 16 12:24:56 PM PDT 24	Apr 16 12:24:58 PM PDT 24	33858415 ps
T580	/workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3670812210	Apr 16 12:25:01 PM PDT 24	Apr 16 12:25:05 PM PDT 24	29778453 ps
T581	/workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1846088058	Apr 16 12:24:32 PM PDT 24	Apr 16 12:24:37 PM PDT 24	34983573 ps
T582	/workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1255738946	Apr 16 12:24:55 PM PDT 24	Apr 16 12:24:57 PM PDT 24	32765067 ps

Test location	/workspace/coverage/default/25.rv_timer_random.2938049359
Short name	T4
Test name
Test status
Simulation time	335082984258 ps
CPU time	154.82 seconds
Started	Apr 16 12:27:27 PM PDT 24
Finished	Apr 16 12:30:05 PM PDT 24
Peak memory	190772 kb
Host	smart-84d00772-ca20-46ca-9605-033f0bb932a0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938049359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2938049359
Directory	/workspace/25.rv_timer_random/latest

Test location	/workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3253387857
Short name	T39
Test name
Test status
Simulation time	392205966318 ps
CPU time	667.87 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:39:03 PM PDT 24
Peak memory	208684 kb
Host	smart-5e11b752-1d1a-4bbf-ad51-72433a5bb06d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253387857 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3253387857
Directory	/workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.rv_timer_stress_all.2198308527
Short name	T50
Test name
Test status
Simulation time	801080350810 ps
CPU time	2257.98 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 01:05:41 PM PDT 24
Peak memory	190816 kb
Host	smart-2bc90cdd-2630-48a5-9358-9897422aa98e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198308527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all .2198308527
Directory	/workspace/48.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/9.rv_timer_stress_all.1603616464
Short name	T118
Test name
Test status
Simulation time	7724918832546 ps
CPU time	7389.91 seconds
Started	Apr 16 12:27:11 PM PDT 24
Finished	Apr 16 02:30:26 PM PDT 24
Peak memory	190800 kb
Host	smart-a9d6d1db-397b-4815-b8bc-fbfd766a7134
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603616464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 1603616464
Directory	/workspace/9.rv_timer_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1282025567
Short name	T30
Test name
Test status
Simulation time	101008692 ps
CPU time	1.35 seconds
Started	Apr 16 12:24:34 PM PDT 24
Finished	Apr 16 12:24:39 PM PDT 24
Peak memory	183044 kb
Host	smart-5403700c-d452-45dc-a6b5-7004ec06f60f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282025567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in tg_err.1282025567
Directory	/workspace/7.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rv_timer_stress_all.1407202131
Short name	T146
Test name
Test status
Simulation time	1965045227404 ps
CPU time	1668.95 seconds
Started	Apr 16 12:22:47 PM PDT 24
Finished	Apr 16 12:50:41 PM PDT 24
Peak memory	189380 kb
Host	smart-114f5961-6907-46aa-bc12-efc7a66a630b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407202131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 1407202131
Directory	/workspace/0.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/11.rv_timer_stress_all.2484731019
Short name	T186
Test name
Test status
Simulation time	853348081960 ps
CPU time	2475.13 seconds
Started	Apr 16 12:27:13 PM PDT 24
Finished	Apr 16 01:08:33 PM PDT 24
Peak memory	195336 kb
Host	smart-fc552bcd-8e90-482a-8c74-7ee418b3626d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484731019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .2484731019
Directory	/workspace/11.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/6.rv_timer_stress_all.4292405242
Short name	T243
Test name
Test status
Simulation time	2175992203465 ps
CPU time	1521.4 seconds
Started	Apr 16 12:27:13 PM PDT 24
Finished	Apr 16 12:52:40 PM PDT 24
Peak memory	194420 kb
Host	smart-ddd396e8-70ba-42b3-aaab-c5a0f5ba0b6c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292405242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all. 4292405242
Directory	/workspace/6.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/116.rv_timer_random.512768951
Short name	T112
Test name
Test status
Simulation time	306852482651 ps
CPU time	256.57 seconds
Started	Apr 16 12:28:03 PM PDT 24
Finished	Apr 16 12:32:22 PM PDT 24
Peak memory	190624 kb
Host	smart-955ea2c5-9906-4469-b92e-2a7b67173bcd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512768951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.512768951
Directory	/workspace/116.rv_timer_random/latest

Test location	/workspace/coverage/default/23.rv_timer_stress_all.3490913553
Short name	T196
Test name
Test status
Simulation time	1929601271836 ps
CPU time	2232.81 seconds
Started	Apr 16 12:27:34 PM PDT 24
Finished	Apr 16 01:04:50 PM PDT 24
Peak memory	196380 kb
Host	smart-4f7a278a-1342-4c26-ac46-347c81519608
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490913553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .3490913553
Directory	/workspace/23.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/24.rv_timer_stress_all.1616572662
Short name	T149
Test name
Test status
Simulation time	568057953340 ps
CPU time	1527.26 seconds
Started	Apr 16 12:27:26 PM PDT 24
Finished	Apr 16 12:52:57 PM PDT 24
Peak memory	194764 kb
Host	smart-5e8a679f-f148-4d15-bc8d-27ba25b92f59
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616572662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all .1616572662
Directory	/workspace/24.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/46.rv_timer_stress_all.2515152785
Short name	T45
Test name
Test status
Simulation time	1396431018774 ps
CPU time	4173.23 seconds
Started	Apr 16 12:28:00 PM PDT 24
Finished	Apr 16 01:37:35 PM PDT 24
Peak memory	190788 kb
Host	smart-199b7772-25e7-4354-9879-e05a2906c4ac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515152785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all .2515152785
Directory	/workspace/46.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/16.rv_timer_stress_all.2821145963
Short name	T184
Test name
Test status
Simulation time	951582768120 ps
CPU time	1510.53 seconds
Started	Apr 16 12:27:18 PM PDT 24
Finished	Apr 16 12:52:34 PM PDT 24
Peak memory	190788 kb
Host	smart-3b29a2e3-24ce-4876-8e51-f069058a132e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821145963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all .2821145963
Directory	/workspace/16.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/17.rv_timer_stress_all.894319948
Short name	T36
Test name
Test status
Simulation time	2310551818465 ps
CPU time	808.82 seconds
Started	Apr 16 12:27:15 PM PDT 24
Finished	Apr 16 12:40:49 PM PDT 24
Peak memory	190732 kb
Host	smart-cdcfbf55-e8e3-41ed-ab27-d0bd3a40f387
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894319948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all. 894319948
Directory	/workspace/17.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/0.rv_timer_sec_cm.2841473003
Short name	T19
Test name
Test status
Simulation time	251808356 ps
CPU time	0.81 seconds
Started	Apr 16 12:21:24 PM PDT 24
Finished	Apr 16 12:21:26 PM PDT 24
Peak memory	213060 kb
Host	smart-d16e4344-1f7a-45fd-ba72-6135a1e527ed
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841473003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2841473003
Directory	/workspace/0.rv_timer_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.412671712
Short name	T81
Test name
Test status
Simulation time	11057415 ps
CPU time	0.56 seconds
Started	Apr 16 12:24:52 PM PDT 24
Finished	Apr 16 12:24:54 PM PDT 24
Peak memory	182648 kb
Host	smart-95fcb939-2161-4f5c-a8e1-3c198ccd3552
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412671712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.412671712
Directory	/workspace/11.rv_timer_csr_rw/latest

Test location	/workspace/coverage/default/22.rv_timer_stress_all.946961668
Short name	T204
Test name
Test status
Simulation time	724756085379 ps
CPU time	1853.65 seconds
Started	Apr 16 12:27:39 PM PDT 24
Finished	Apr 16 12:58:37 PM PDT 24
Peak memory	194844 kb
Host	smart-840618f9-bc2b-4a1f-b7ac-ab7fe4452d6e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946961668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all. 946961668
Directory	/workspace/22.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/26.rv_timer_stress_all.4189374017
Short name	T159
Test name
Test status
Simulation time	435643069247 ps
CPU time	1141.78 seconds
Started	Apr 16 12:27:50 PM PDT 24
Finished	Apr 16 12:46:55 PM PDT 24
Peak memory	190804 kb
Host	smart-d43f84b0-9936-4dec-abed-d45b9cad5d1a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189374017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all .4189374017
Directory	/workspace/26.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/8.rv_timer_stress_all.3425687886
Short name	T150
Test name
Test status
Simulation time	825605738755 ps
CPU time	1087.26 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:45:32 PM PDT 24
Peak memory	190764 kb
Host	smart-e875a809-7516-427a-869d-c31b4b008192
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425687886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 3425687886
Directory	/workspace/8.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/177.rv_timer_random.92815456
Short name	T126
Test name
Test status
Simulation time	410468948099 ps
CPU time	277.4 seconds
Started	Apr 16 12:28:23 PM PDT 24
Finished	Apr 16 12:33:01 PM PDT 24
Peak memory	190684 kb
Host	smart-11c69c2e-7a4f-4b58-82bf-a2367514fd1d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92815456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.92815456
Directory	/workspace/177.rv_timer_random/latest

Test location	/workspace/coverage/default/7.rv_timer_stress_all.1101522727
Short name	T166
Test name
Test status
Simulation time	879268599691 ps
CPU time	1880.63 seconds
Started	Apr 16 12:27:16 PM PDT 24
Finished	Apr 16 12:58:42 PM PDT 24
Peak memory	190664 kb
Host	smart-f495a516-0b37-4b0a-9472-994226032067
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101522727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all. 1101522727
Directory	/workspace/7.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/10.rv_timer_stress_all.443690233
Short name	T61
Test name
Test status
Simulation time	876675978260 ps
CPU time	1166.56 seconds
Started	Apr 16 12:27:17 PM PDT 24
Finished	Apr 16 12:46:49 PM PDT 24
Peak memory	190668 kb
Host	smart-5cba3d1c-992d-47a0-94ae-8704f0b78413
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443690233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all. 443690233
Directory	/workspace/10.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/81.rv_timer_random.1433025919
Short name	T274
Test name
Test status
Simulation time	587717182540 ps
CPU time	388.66 seconds
Started	Apr 16 12:28:04 PM PDT 24
Finished	Apr 16 12:34:35 PM PDT 24
Peak memory	190648 kb
Host	smart-96ab6e05-8d6a-4b2c-b54a-6436ae6536c7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433025919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1433025919
Directory	/workspace/81.rv_timer_random/latest

Test location	/workspace/coverage/default/110.rv_timer_random.3666767963
Short name	T170
Test name
Test status
Simulation time	491786550182 ps
CPU time	630.42 seconds
Started	Apr 16 12:28:03 PM PDT 24
Finished	Apr 16 12:38:35 PM PDT 24
Peak memory	190756 kb
Host	smart-70cf2679-70ac-46f0-af14-01f241297755
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666767963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3666767963
Directory	/workspace/110.rv_timer_random/latest

Test location	/workspace/coverage/default/12.rv_timer_stress_all.2036315380
Short name	T109
Test name
Test status
Simulation time	2209185818067 ps
CPU time	1274.08 seconds
Started	Apr 16 12:27:12 PM PDT 24
Finished	Apr 16 12:48:32 PM PDT 24
Peak memory	194656 kb
Host	smart-07f1ecfa-15c2-4d58-96a0-e3d94d0abdf5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036315380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .2036315380
Directory	/workspace/12.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/197.rv_timer_random.3478766562
Short name	T238
Test name
Test status
Simulation time	157332941943 ps
CPU time	674.34 seconds
Started	Apr 16 12:28:32 PM PDT 24
Finished	Apr 16 12:39:47 PM PDT 24
Peak memory	193588 kb
Host	smart-fdf9602a-052e-4a25-9bf2-97153feb739c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478766562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3478766562
Directory	/workspace/197.rv_timer_random/latest

Test location	/workspace/coverage/default/49.rv_timer_stress_all.4134796203
Short name	T200
Test name
Test status
Simulation time	1724741339413 ps
CPU time	793.02 seconds
Started	Apr 16 12:27:57 PM PDT 24
Finished	Apr 16 12:41:12 PM PDT 24
Peak memory	190684 kb
Host	smart-885d229e-89dd-4416-851f-5c13bb1ac65c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134796203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all .4134796203
Directory	/workspace/49.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/90.rv_timer_random.1881573378
Short name	T218
Test name
Test status
Simulation time	1159402133848 ps
CPU time	445.72 seconds
Started	Apr 16 12:27:56 PM PDT 24
Finished	Apr 16 12:35:24 PM PDT 24
Peak memory	190740 kb
Host	smart-98d7e49a-d3c5-48fd-a1ba-b5b1a3fe59cf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881573378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1881573378
Directory	/workspace/90.rv_timer_random/latest

Test location	/workspace/coverage/default/14.rv_timer_stress_all.628865837
Short name	T58
Test name
Test status
Simulation time	593824004135 ps
CPU time	1394.54 seconds
Started	Apr 16 12:27:17 PM PDT 24
Finished	Apr 16 12:50:37 PM PDT 24
Peak memory	190768 kb
Host	smart-767abb11-c138-428a-9c8d-18a1caaefaaa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628865837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all. 628865837
Directory	/workspace/14.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/194.rv_timer_random.91786176
Short name	T145
Test name
Test status
Simulation time	191029788149 ps
CPU time	430.22 seconds
Started	Apr 16 12:28:33 PM PDT 24
Finished	Apr 16 12:35:44 PM PDT 24
Peak memory	190680 kb
Host	smart-23868f46-6463-4ab5-bf9e-77db1d0baa62
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91786176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.91786176
Directory	/workspace/194.rv_timer_random/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1677306217
Short name	T72
Test name
Test status
Simulation time	88395402 ps
CPU time	0.8 seconds
Started	Apr 16 12:25:03 PM PDT 24
Finished	Apr 16 12:25:08 PM PDT 24
Peak memory	193168 kb
Host	smart-5c2c2d21-284f-4c09-9954-9cbbe23844c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677306217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.1677306217
Directory	/workspace/11.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/default/111.rv_timer_random.1117352722
Short name	T182
Test name
Test status
Simulation time	143470921554 ps
CPU time	931.19 seconds
Started	Apr 16 12:28:04 PM PDT 24
Finished	Apr 16 12:43:37 PM PDT 24
Peak memory	190756 kb
Host	smart-9460f69c-a779-4bce-9f7e-8d54870a06eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117352722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1117352722
Directory	/workspace/111.rv_timer_random/latest

Test location	/workspace/coverage/default/115.rv_timer_random.4252248951
Short name	T169
Test name
Test status
Simulation time	628853429507 ps
CPU time	620.04 seconds
Started	Apr 16 12:28:09 PM PDT 24
Finished	Apr 16 12:38:31 PM PDT 24
Peak memory	194212 kb
Host	smart-e355dd12-f8c8-4072-80bb-0896d7b9e3ed
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252248951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4252248951
Directory	/workspace/115.rv_timer_random/latest

Test location	/workspace/coverage/default/165.rv_timer_random.591467248
Short name	T144
Test name
Test status
Simulation time	92648771820 ps
CPU time	192.05 seconds
Started	Apr 16 12:28:21 PM PDT 24
Finished	Apr 16 12:31:35 PM PDT 24
Peak memory	190780 kb
Host	smart-8354a989-889f-4936-a796-8d59339d7dad
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591467248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.591467248
Directory	/workspace/165.rv_timer_random/latest

Test location	/workspace/coverage/default/32.rv_timer_stress_all.2416241158
Short name	T108
Test name
Test status
Simulation time	550520953192 ps
CPU time	709.54 seconds
Started	Apr 16 12:27:44 PM PDT 24
Finished	Apr 16 12:39:36 PM PDT 24
Peak memory	194560 kb
Host	smart-b0f433d1-c118-4244-a2dd-5b4cc08be210
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416241158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all .2416241158
Directory	/workspace/32.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2647924985
Short name	T227
Test name
Test status
Simulation time	1321961204512 ps
CPU time	712.42 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:39:48 PM PDT 24
Peak memory	182564 kb
Host	smart-debc6244-f9d4-4e88-ab28-5ffa14f2af9d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647924985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.2647924985
Directory	/workspace/44.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/107.rv_timer_random.2050509323
Short name	T89
Test name
Test status
Simulation time	500303479479 ps
CPU time	260.97 seconds
Started	Apr 16 12:29:16 PM PDT 24
Finished	Apr 16 12:33:39 PM PDT 24
Peak memory	189068 kb
Host	smart-cb9819a0-8a2e-4f82-9d25-3ea9c91a30c8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050509323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2050509323
Directory	/workspace/107.rv_timer_random/latest

Test location	/workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3559863960
Short name	T191
Test name
Test status
Simulation time	1090145219984 ps
CPU time	603.88 seconds
Started	Apr 16 12:27:16 PM PDT 24
Finished	Apr 16 12:37:25 PM PDT 24
Peak memory	182460 kb
Host	smart-db203fb9-41bf-402a-be4d-eb1c191b0690
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559863960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.3559863960
Directory	/workspace/13.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/137.rv_timer_random.2197260341
Short name	T198
Test name
Test status
Simulation time	2137637535545 ps
CPU time	511.8 seconds
Started	Apr 16 12:28:09 PM PDT 24
Finished	Apr 16 12:36:42 PM PDT 24
Peak memory	190688 kb
Host	smart-bc28922e-4fda-4eb0-9d17-4597b1f621b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197260341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2197260341
Directory	/workspace/137.rv_timer_random/latest

Test location	/workspace/coverage/default/151.rv_timer_random.1715095675
Short name	T21
Test name
Test status
Simulation time	125680621678 ps
CPU time	179.54 seconds
Started	Apr 16 12:28:16 PM PDT 24
Finished	Apr 16 12:31:18 PM PDT 24
Peak memory	192872 kb
Host	smart-8eb68dbc-acd0-43cf-8de7-bc6abb981ee4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715095675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1715095675
Directory	/workspace/151.rv_timer_random/latest

Test location	/workspace/coverage/default/36.rv_timer_stress_all.3040060321
Short name	T201
Test name
Test status
Simulation time	1198797257038 ps
CPU time	3086.62 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 01:19:21 PM PDT 24
Peak memory	190760 kb
Host	smart-c348149f-03b5-45ce-bc9f-9ee24d62daab
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040060321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .3040060321
Directory	/workspace/36.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/64.rv_timer_random.2375807185
Short name	T229
Test name
Test status
Simulation time	125770751676 ps
CPU time	168.37 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:30:52 PM PDT 24
Peak memory	193836 kb
Host	smart-0e08d836-ec3f-4c7e-9bb6-5b420241aa1e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375807185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2375807185
Directory	/workspace/64.rv_timer_random/latest

Test location	/workspace/coverage/default/127.rv_timer_random.852268674
Short name	T104
Test name
Test status
Simulation time	278988942634 ps
CPU time	448.07 seconds
Started	Apr 16 12:28:12 PM PDT 24
Finished	Apr 16 12:35:43 PM PDT 24
Peak memory	190364 kb
Host	smart-64e4c9bb-24bb-4b5d-90d8-40ee418da4a4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852268674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.852268674
Directory	/workspace/127.rv_timer_random/latest

Test location	/workspace/coverage/default/141.rv_timer_random.2252065278
Short name	T246
Test name
Test status
Simulation time	427409000574 ps
CPU time	603.96 seconds
Started	Apr 16 12:28:09 PM PDT 24
Finished	Apr 16 12:38:14 PM PDT 24
Peak memory	190760 kb
Host	smart-74f5c3f1-460c-4bde-b911-0991e76507e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252065278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2252065278
Directory	/workspace/141.rv_timer_random/latest

Test location	/workspace/coverage/default/144.rv_timer_random.2569238731
Short name	T335
Test name
Test status
Simulation time	588054917141 ps
CPU time	675.73 seconds
Started	Apr 16 12:28:08 PM PDT 24
Finished	Apr 16 12:39:25 PM PDT 24
Peak memory	190660 kb
Host	smart-6a299733-0a1b-46d9-8e3a-94f6a5ac4993
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569238731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2569238731
Directory	/workspace/144.rv_timer_random/latest

Test location	/workspace/coverage/default/147.rv_timer_random.610790589
Short name	T271
Test name
Test status
Simulation time	293600720381 ps
CPU time	730.35 seconds
Started	Apr 16 12:28:15 PM PDT 24
Finished	Apr 16 12:40:29 PM PDT 24
Peak memory	190764 kb
Host	smart-61493c1d-71df-417e-bb73-b597a5caf758
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610790589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.610790589
Directory	/workspace/147.rv_timer_random/latest

Test location	/workspace/coverage/default/155.rv_timer_random.2740056277
Short name	T173
Test name
Test status
Simulation time	117380450570 ps
CPU time	127.9 seconds
Started	Apr 16 12:28:15 PM PDT 24
Finished	Apr 16 12:30:26 PM PDT 24
Peak memory	190692 kb
Host	smart-5344a9c6-7835-4663-84ac-12c278856130
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740056277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2740056277
Directory	/workspace/155.rv_timer_random/latest

Test location	/workspace/coverage/default/188.rv_timer_random.1327793804
Short name	T207
Test name
Test status
Simulation time	91791510723 ps
CPU time	148.34 seconds
Started	Apr 16 12:28:27 PM PDT 24
Finished	Apr 16 12:30:57 PM PDT 24
Peak memory	190724 kb
Host	smart-70e4c813-f11e-4f37-afc1-d1a3aa859b72
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327793804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1327793804
Directory	/workspace/188.rv_timer_random/latest

Test location	/workspace/coverage/default/196.rv_timer_random.3543707688
Short name	T124
Test name
Test status
Simulation time	96309596420 ps
CPU time	392.26 seconds
Started	Apr 16 12:28:32 PM PDT 24
Finished	Apr 16 12:35:06 PM PDT 24
Peak memory	190796 kb
Host	smart-501b2e91-ff32-43cf-8d58-5f24ba04a2b5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543707688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3543707688
Directory	/workspace/196.rv_timer_random/latest

Test location	/workspace/coverage/default/4.rv_timer_stress_all.1260431111
Short name	T60
Test name
Test status
Simulation time	2119405181881 ps
CPU time	1057.21 seconds
Started	Apr 16 12:27:15 PM PDT 24
Finished	Apr 16 12:44:57 PM PDT 24
Peak memory	190780 kb
Host	smart-54e70df1-bb84-4c58-83fa-c3426ea42e31
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260431111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 1260431111
Directory	/workspace/4.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/46.rv_timer_random.2459254981
Short name	T48
Test name
Test status
Simulation time	497204713222 ps
CPU time	395.74 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:34:32 PM PDT 24
Peak memory	194256 kb
Host	smart-6259ff76-b079-4dc3-b8b3-d6d977ffa607
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459254981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2459254981
Directory	/workspace/46.rv_timer_random/latest

Test location	/workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3872600455
Short name	T27
Test name
Test status
Simulation time	1668995319653 ps
CPU time	851.95 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:42:08 PM PDT 24
Peak memory	182464 kb
Host	smart-ee07f443-29cb-4948-91f5-83d66bb1a5ad
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872600455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3872600455
Directory	/workspace/49.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/52.rv_timer_random.2503881580
Short name	T199
Test name
Test status
Simulation time	477262745467 ps
CPU time	1822.28 seconds
Started	Apr 16 12:27:59 PM PDT 24
Finished	Apr 16 12:58:23 PM PDT 24
Peak memory	190656 kb
Host	smart-733e691a-3ea7-413a-bc34-aab06f865147
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503881580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2503881580
Directory	/workspace/52.rv_timer_random/latest

Test location	/workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2058804469
Short name	T240
Test name
Test status
Simulation time	256243593915 ps
CPU time	472.42 seconds
Started	Apr 16 12:27:08 PM PDT 24
Finished	Apr 16 12:35:06 PM PDT 24
Peak memory	182420 kb
Host	smart-91e810f1-3fc1-47d3-97de-d589b751735c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058804469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.2058804469
Directory	/workspace/7.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/10.rv_timer_random_reset.3420904075
Short name	T165
Test name
Test status
Simulation time	468105959932 ps
CPU time	443.33 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:34:47 PM PDT 24
Peak memory	190748 kb
Host	smart-fee1009d-cbdf-4464-84b6-cbbd6af6d477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420904075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3420904075
Directory	/workspace/10.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/118.rv_timer_random.996827486
Short name	T281
Test name
Test status
Simulation time	264254730201 ps
CPU time	1872.4 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:59:15 PM PDT 24
Peak memory	190696 kb
Host	smart-b78bea16-ce37-487d-a411-a33533ca0edd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996827486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.996827486
Directory	/workspace/118.rv_timer_random/latest

Test location	/workspace/coverage/default/123.rv_timer_random.2527476534
Short name	T94
Test name
Test status
Simulation time	96912276143 ps
CPU time	1537.45 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:53:42 PM PDT 24
Peak memory	190608 kb
Host	smart-bd636ea9-c531-4ddf-8130-c9dc8d9e077f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527476534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2527476534
Directory	/workspace/123.rv_timer_random/latest

Test location	/workspace/coverage/default/13.rv_timer_stress_all.3582258725
Short name	T237
Test name
Test status
Simulation time	1500152703065 ps
CPU time	1918.61 seconds
Started	Apr 16 12:27:08 PM PDT 24
Finished	Apr 16 12:59:12 PM PDT 24
Peak memory	190628 kb
Host	smart-d43a580e-0c53-410e-86cc-2481b576b612
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582258725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all .3582258725
Directory	/workspace/13.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/173.rv_timer_random.2975408785
Short name	T314
Test name
Test status
Simulation time	870928681038 ps
CPU time	422.52 seconds
Started	Apr 16 12:28:20 PM PDT 24
Finished	Apr 16 12:35:25 PM PDT 24
Peak memory	190660 kb
Host	smart-75115392-34ff-4d16-ac61-89d38d0f4654
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975408785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2975408785
Directory	/workspace/173.rv_timer_random/latest

Test location	/workspace/coverage/default/184.rv_timer_random.2957622941
Short name	T211
Test name
Test status
Simulation time	78390599117 ps
CPU time	609.72 seconds
Started	Apr 16 12:28:25 PM PDT 24
Finished	Apr 16 12:38:37 PM PDT 24
Peak memory	190804 kb
Host	smart-593e9af8-8dd3-4fa0-8222-611ee6b1600b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957622941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2957622941
Directory	/workspace/184.rv_timer_random/latest

Test location	/workspace/coverage/default/19.rv_timer_random.4099131967
Short name	T178
Test name
Test status
Simulation time	523189075074 ps
CPU time	265.48 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:31:50 PM PDT 24
Peak memory	190752 kb
Host	smart-4e41a7d1-c855-4c06-a1ed-217fac90c6e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099131967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.4099131967
Directory	/workspace/19.rv_timer_random/latest

Test location	/workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1384167319
Short name	T208
Test name
Test status
Simulation time	1427421600006 ps
CPU time	309.7 seconds
Started	Apr 16 12:27:26 PM PDT 24
Finished	Apr 16 12:32:39 PM PDT 24
Peak memory	182564 kb
Host	smart-a6fe2a2d-895c-4589-82c9-bc0ff6a668d2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384167319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1384167319
Directory	/workspace/26.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/3.rv_timer_stress_all.3490530746
Short name	T254
Test name
Test status
Simulation time	802898566633 ps
CPU time	810.64 seconds
Started	Apr 16 12:27:07 PM PDT 24
Finished	Apr 16 12:40:43 PM PDT 24
Peak memory	190696 kb
Host	smart-4c801623-a9b9-441a-ad54-7e1fab50b2da
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490530746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 3490530746
Directory	/workspace/3.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2448744233
Short name	T180
Test name
Test status
Simulation time	182927168829 ps
CPU time	351.55 seconds
Started	Apr 16 12:27:44 PM PDT 24
Finished	Apr 16 12:33:37 PM PDT 24
Peak memory	182552 kb
Host	smart-e061b9bc-4973-428a-9a57-eb7847f6ad96
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448744233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.2448744233
Directory	/workspace/30.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/69.rv_timer_random.104409881
Short name	T299
Test name
Test status
Simulation time	143929880571 ps
CPU time	121.24 seconds
Started	Apr 16 12:27:58 PM PDT 24
Finished	Apr 16 12:30:01 PM PDT 24
Peak memory	190784 kb
Host	smart-6bde6fc9-c423-47a2-a279-e55e7878a458
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104409881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.104409881
Directory	/workspace/69.rv_timer_random/latest

Test location	/workspace/coverage/default/7.rv_timer_random.2122132354
Short name	T233
Test name
Test status
Simulation time	348971011117 ps
CPU time	194.04 seconds
Started	Apr 16 12:27:17 PM PDT 24
Finished	Apr 16 12:30:36 PM PDT 24
Peak memory	190752 kb
Host	smart-d2fbf782-7e08-4e74-a200-41471abe8baa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122132354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2122132354
Directory	/workspace/7.rv_timer_random/latest

Test location	/workspace/coverage/default/79.rv_timer_random.445092054
Short name	T156
Test name
Test status
Simulation time	281933961398 ps
CPU time	332.98 seconds
Started	Apr 16 12:28:03 PM PDT 24
Finished	Apr 16 12:33:38 PM PDT 24
Peak memory	190784 kb
Host	smart-cc2afd38-9fcb-49b7-9988-6feb6e77524a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445092054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.445092054
Directory	/workspace/79.rv_timer_random/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.967620322
Short name	T558
Test name
Test status
Simulation time	227687990 ps
CPU time	1.25 seconds
Started	Apr 16 12:24:37 PM PDT 24
Finished	Apr 16 12:24:41 PM PDT 24
Peak memory	195380 kb
Host	smart-5078e6e0-18c9-4b1c-9111-8deafdffe284
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967620322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in tg_err.967620322
Directory	/workspace/10.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rv_timer_random.3476242498
Short name	T174
Test name
Test status
Simulation time	188549844989 ps
CPU time	53.9 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:23:41 PM PDT 24
Peak memory	182136 kb
Host	smart-15c2bb3c-0530-4b06-9950-e076ad7a9a73
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476242498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3476242498
Directory	/workspace/0.rv_timer_random/latest

Test location	/workspace/coverage/default/1.rv_timer_random.2171778732
Short name	T307
Test name
Test status
Simulation time	415546963246 ps
CPU time	505.72 seconds
Started	Apr 16 12:21:14 PM PDT 24
Finished	Apr 16 12:29:41 PM PDT 24
Peak memory	190580 kb
Host	smart-d50f7305-a52d-4b52-ab4d-b53ea1816bf6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171778732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2171778732
Directory	/workspace/1.rv_timer_random/latest

Test location	/workspace/coverage/default/100.rv_timer_random.2513258159
Short name	T320
Test name
Test status
Simulation time	10332010266 ps
CPU time	49.07 seconds
Started	Apr 16 12:27:56 PM PDT 24
Finished	Apr 16 12:28:47 PM PDT 24
Peak memory	182608 kb
Host	smart-eb95944b-2ece-4b09-8e5c-577d9a0e73fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513258159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2513258159
Directory	/workspace/100.rv_timer_random/latest

Test location	/workspace/coverage/default/101.rv_timer_random.2906653711
Short name	T262
Test name
Test status
Simulation time	297116011280 ps
CPU time	386.58 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:34:30 PM PDT 24
Peak memory	190800 kb
Host	smart-1e75626d-28d5-4554-b207-ecd366b42577
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906653711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2906653711
Directory	/workspace/101.rv_timer_random/latest

Test location	/workspace/coverage/default/102.rv_timer_random.3118600626
Short name	T257
Test name
Test status
Simulation time	462503651667 ps
CPU time	274.76 seconds
Started	Apr 16 12:27:57 PM PDT 24
Finished	Apr 16 12:32:33 PM PDT 24
Peak memory	190668 kb
Host	smart-88ab3a5a-0fa2-466c-a3c8-cc497b966ea9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118600626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3118600626
Directory	/workspace/102.rv_timer_random/latest

Test location	/workspace/coverage/default/105.rv_timer_random.3724376303
Short name	T122
Test name
Test status
Simulation time	2258826599726 ps
CPU time	1211.38 seconds
Started	Apr 16 12:28:08 PM PDT 24
Finished	Apr 16 12:48:22 PM PDT 24
Peak memory	190540 kb
Host	smart-741134a5-9901-4c29-b4dc-807a25f25b21
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724376303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3724376303
Directory	/workspace/105.rv_timer_random/latest

Test location	/workspace/coverage/default/11.rv_timer_random.2435872377
Short name	T305
Test name
Test status
Simulation time	52277464795 ps
CPU time	84.59 seconds
Started	Apr 16 12:27:17 PM PDT 24
Finished	Apr 16 12:28:47 PM PDT 24
Peak memory	190548 kb
Host	smart-ddc3c846-4b72-4ec9-bc99-339a83cb4d21
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435872377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2435872377
Directory	/workspace/11.rv_timer_random/latest

Test location	/workspace/coverage/default/119.rv_timer_random.2626906584
Short name	T110
Test name
Test status
Simulation time	225963921852 ps
CPU time	791.16 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:41:15 PM PDT 24
Peak memory	190672 kb
Host	smart-b360258a-c203-4d22-aa83-039b3692d282
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626906584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2626906584
Directory	/workspace/119.rv_timer_random/latest

Test location	/workspace/coverage/default/13.rv_timer_random.321972401
Short name	T219
Test name
Test status
Simulation time	754938103009 ps
CPU time	350.08 seconds
Started	Apr 16 12:27:11 PM PDT 24
Finished	Apr 16 12:33:07 PM PDT 24
Peak memory	190632 kb
Host	smart-271d5ab7-53ef-46ae-9cd6-f22f5be4d453
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321972401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.321972401
Directory	/workspace/13.rv_timer_random/latest

Test location	/workspace/coverage/default/130.rv_timer_random.1785628479
Short name	T323
Test name
Test status
Simulation time	179832824423 ps
CPU time	530.28 seconds
Started	Apr 16 12:28:08 PM PDT 24
Finished	Apr 16 12:36:59 PM PDT 24
Peak memory	192808 kb
Host	smart-43aca185-750c-4b37-ad5a-3c10d559aef3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785628479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1785628479
Directory	/workspace/130.rv_timer_random/latest

Test location	/workspace/coverage/default/138.rv_timer_random.2315284318
Short name	T275
Test name
Test status
Simulation time	146751244277 ps
CPU time	239.54 seconds
Started	Apr 16 12:28:09 PM PDT 24
Finished	Apr 16 12:32:10 PM PDT 24
Peak memory	190616 kb
Host	smart-89b9b1b8-9577-45d6-8318-79299a11cbc2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315284318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2315284318
Directory	/workspace/138.rv_timer_random/latest

Test location	/workspace/coverage/default/139.rv_timer_random.1415015074
Short name	T290
Test name
Test status
Simulation time	148423966685 ps
CPU time	954.75 seconds
Started	Apr 16 12:28:10 PM PDT 24
Finished	Apr 16 12:44:06 PM PDT 24
Peak memory	190660 kb
Host	smart-577c5514-73ac-4be4-ae34-26c6fc96091a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415015074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1415015074
Directory	/workspace/139.rv_timer_random/latest

Test location	/workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3392370174
Short name	T154
Test name
Test status
Simulation time	5354050500259 ps
CPU time	1212.73 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:47:37 PM PDT 24
Peak memory	182612 kb
Host	smart-d06c1a0c-cfa7-4148-adb3-2c2454c189ab
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392370174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.3392370174
Directory	/workspace/14.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/143.rv_timer_random.2741325468
Short name	T203
Test name
Test status
Simulation time	52048344949 ps
CPU time	255.3 seconds
Started	Apr 16 12:28:08 PM PDT 24
Finished	Apr 16 12:32:25 PM PDT 24
Peak memory	190760 kb
Host	smart-ea41f8d6-73ed-473e-81eb-95c76ce7f5c4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741325468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2741325468
Directory	/workspace/143.rv_timer_random/latest

Test location	/workspace/coverage/default/146.rv_timer_random.1712177000
Short name	T140
Test name
Test status
Simulation time	498606375417 ps
CPU time	766.41 seconds
Started	Apr 16 12:28:13 PM PDT 24
Finished	Apr 16 12:41:01 PM PDT 24
Peak memory	190716 kb
Host	smart-248d7d99-5484-4a96-a5bb-9e29d7e194f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712177000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1712177000
Directory	/workspace/146.rv_timer_random/latest

Test location	/workspace/coverage/default/150.rv_timer_random.3720721216
Short name	T160
Test name
Test status
Simulation time	266839261762 ps
CPU time	298.82 seconds
Started	Apr 16 12:28:14 PM PDT 24
Finished	Apr 16 12:33:16 PM PDT 24
Peak memory	193284 kb
Host	smart-738f17c1-932c-45f7-8ec7-a1bed78874ce
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720721216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3720721216
Directory	/workspace/150.rv_timer_random/latest

Test location	/workspace/coverage/default/17.rv_timer_random.4226585841
Short name	T339
Test name
Test status
Simulation time	58668102793 ps
CPU time	55.18 seconds
Started	Apr 16 12:27:18 PM PDT 24
Finished	Apr 16 12:28:19 PM PDT 24
Peak memory	182452 kb
Host	smart-87969de5-38d9-48dd-896b-213c56e8d313
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226585841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4226585841
Directory	/workspace/17.rv_timer_random/latest

Test location	/workspace/coverage/default/180.rv_timer_random.754485675
Short name	T279
Test name
Test status
Simulation time	7960844108 ps
CPU time	16.98 seconds
Started	Apr 16 12:28:25 PM PDT 24
Finished	Apr 16 12:28:43 PM PDT 24
Peak memory	190668 kb
Host	smart-e7cc2c97-821f-4d36-84aa-3f67a468eae2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754485675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.754485675
Directory	/workspace/180.rv_timer_random/latest

Test location	/workspace/coverage/default/193.rv_timer_random.1711153889
Short name	T253
Test name
Test status
Simulation time	112086378349 ps
CPU time	153.93 seconds
Started	Apr 16 12:28:25 PM PDT 24
Finished	Apr 16 12:31:01 PM PDT 24
Peak memory	190768 kb
Host	smart-2662d860-63ba-4961-bcf7-d7f2f7071871
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711153889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1711153889
Directory	/workspace/193.rv_timer_random/latest

Test location	/workspace/coverage/default/23.rv_timer_random.1594643143
Short name	T171
Test name
Test status
Simulation time	96084948943 ps
CPU time	241.37 seconds
Started	Apr 16 12:27:23 PM PDT 24
Finished	Apr 16 12:31:28 PM PDT 24
Peak memory	190720 kb
Host	smart-c350cbc1-06d7-4da6-a068-3da6a19db339
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594643143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1594643143
Directory	/workspace/23.rv_timer_random/latest

Test location	/workspace/coverage/default/28.rv_timer_random.4133661056
Short name	T106
Test name
Test status
Simulation time	66153662038 ps
CPU time	99.53 seconds
Started	Apr 16 12:27:33 PM PDT 24
Finished	Apr 16 12:29:15 PM PDT 24
Peak memory	193288 kb
Host	smart-11266296-67d8-4c1e-9d88-4e5939ea6976
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133661056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4133661056
Directory	/workspace/28.rv_timer_random/latest

Test location	/workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2236572530
Short name	T306
Test name
Test status
Simulation time	682738239125 ps
CPU time	309.21 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:33:06 PM PDT 24
Peak memory	182624 kb
Host	smart-01e0e9d9-f06e-4cbc-8009-0fbb69f20fda
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236572530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.2236572530
Directory	/workspace/42.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/53.rv_timer_random.2038155686
Short name	T327
Test name
Test status
Simulation time	129496254324 ps
CPU time	108.03 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:29:44 PM PDT 24
Peak memory	190200 kb
Host	smart-33c82672-71c0-40e5-8f6e-e6ea8083a6ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038155686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2038155686
Directory	/workspace/53.rv_timer_random/latest

Test location	/workspace/coverage/default/66.rv_timer_random.864108505
Short name	T129
Test name
Test status
Simulation time	244356833264 ps
CPU time	1446.32 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:52:02 PM PDT 24
Peak memory	190756 kb
Host	smart-71d74ea9-7c9f-49b1-8afc-b8a2364ab189
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864108505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.864108505
Directory	/workspace/66.rv_timer_random/latest

Test location	/workspace/coverage/default/76.rv_timer_random.916328979
Short name	T162
Test name
Test status
Simulation time	214474251893 ps
CPU time	2032.36 seconds
Started	Apr 16 12:27:56 PM PDT 24
Finished	Apr 16 01:01:51 PM PDT 24
Peak memory	190676 kb
Host	smart-689bf0ba-a2cb-4d1a-95ef-4256c69b73c5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916328979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.916328979
Directory	/workspace/76.rv_timer_random/latest

Test location	/workspace/coverage/default/9.rv_timer_random.507428316
Short name	T287
Test name
Test status
Simulation time	105915129830 ps
CPU time	1579.13 seconds
Started	Apr 16 12:27:11 PM PDT 24
Finished	Apr 16 12:53:36 PM PDT 24
Peak memory	190644 kb
Host	smart-f247dd75-21fa-4b20-b4ba-0540cb3178eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507428316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.507428316
Directory	/workspace/9.rv_timer_random/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.679432411
Short name	T76
Test name
Test status
Simulation time	107779820 ps
CPU time	0.69 seconds
Started	Apr 16 12:20:57 PM PDT 24
Finished	Apr 16 12:20:59 PM PDT 24
Peak memory	182024 kb
Host	smart-5ae1e541-7295-40d1-9c02-4f7450325564
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679432411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias ing.679432411
Directory	/workspace/0.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1439175615
Short name	T495
Test name
Test status
Simulation time	956129076 ps
CPU time	3.66 seconds
Started	Apr 16 12:20:18 PM PDT 24
Finished	Apr 16 12:20:23 PM PDT 24
Peak memory	191308 kb
Host	smart-66791db0-e621-4b94-853d-7c20e0f7e85c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439175615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ bash.1439175615
Directory	/workspace/0.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3840366991
Short name	T568
Test name
Test status
Simulation time	18221623 ps
CPU time	0.68 seconds
Started	Apr 16 12:20:56 PM PDT 24
Finished	Apr 16 12:20:59 PM PDT 24
Peak memory	180524 kb
Host	smart-02e446f4-296d-4678-8986-71d8b8cacff5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840366991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.3840366991
Directory	/workspace/0.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1171531986
Short name	T468
Test name
Test status
Simulation time	13435898 ps
CPU time	0.59 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:22:06 PM PDT 24
Peak memory	193036 kb
Host	smart-1df6285a-1ea2-4887-9d58-3cddaf2ec152
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171531986 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1171531986
Directory	/workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1772480807
Short name	T98
Test name
Test status
Simulation time	17532163 ps
CPU time	0.56 seconds
Started	Apr 16 12:21:29 PM PDT 24
Finished	Apr 16 12:21:31 PM PDT 24
Peak memory	182468 kb
Host	smart-b4247ea2-cff5-4e1d-adb8-6a41b16d0507
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772480807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1772480807
Directory	/workspace/0.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_intr_test.631602108
Short name	T511
Test name
Test status
Simulation time	51897426 ps
CPU time	0.57 seconds
Started	Apr 16 12:17:54 PM PDT 24
Finished	Apr 16 12:17:56 PM PDT 24
Peak memory	182352 kb
Host	smart-2b9e75bf-9c98-4a52-bc0d-a4f8f6777bdc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631602108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.631602108
Directory	/workspace/0.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3950276436
Short name	T87
Test name
Test status
Simulation time	94744507 ps
CPU time	0.67 seconds
Started	Apr 16 12:21:06 PM PDT 24
Finished	Apr 16 12:21:09 PM PDT 24
Peak memory	191544 kb
Host	smart-709c2dfb-c704-4109-b45d-2410edb9070a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950276436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti mer_same_csr_outstanding.3950276436
Directory	/workspace/0.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1627232360
Short name	T509
Test name
Test status
Simulation time	32732362 ps
CPU time	1.6 seconds
Started	Apr 16 12:21:01 PM PDT 24
Finished	Apr 16 12:21:04 PM PDT 24
Peak memory	197176 kb
Host	smart-b8b947ef-9dfc-402e-9e8b-052c69b3c449
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627232360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1627232360
Directory	/workspace/0.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4112924528
Short name	T573
Test name
Test status
Simulation time	412277915 ps
CPU time	1.31 seconds
Started	Apr 16 12:20:57 PM PDT 24
Finished	Apr 16 12:20:59 PM PDT 24
Peak memory	194512 kb
Host	smart-207e84bd-6b9e-4791-bf06-36daf2452a79
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112924528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in tg_err.4112924528
Directory	/workspace/0.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.725293791
Short name	T71
Test name
Test status
Simulation time	19502581 ps
CPU time	0.82 seconds
Started	Apr 16 12:21:25 PM PDT 24
Finished	Apr 16 12:21:28 PM PDT 24
Peak memory	182920 kb
Host	smart-9d9769c4-be81-4049-8d6e-6a72bfab02ef
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725293791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias ing.725293791
Directory	/workspace/1.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1221925954
Short name	T505
Test name
Test status
Simulation time	228685315 ps
CPU time	2.3 seconds
Started	Apr 16 12:21:06 PM PDT 24
Finished	Apr 16 12:21:10 PM PDT 24
Peak memory	181860 kb
Host	smart-121a0e31-ad24-4c1b-a7ac-7c40abe7822c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221925954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ bash.1221925954
Directory	/workspace/1.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.44645590
Short name	T83
Test name
Test status
Simulation time	20699734 ps
CPU time	0.64 seconds
Started	Apr 16 12:22:42 PM PDT 24
Finished	Apr 16 12:22:48 PM PDT 24
Peak memory	180592 kb
Host	smart-1a661a26-b3bc-4ea6-a721-1339e43f5533
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44645590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_res et.44645590
Directory	/workspace/1.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4145253644
Short name	T474
Test name
Test status
Simulation time	70976476 ps
CPU time	0.72 seconds
Started	Apr 16 12:17:57 PM PDT 24
Finished	Apr 16 12:17:58 PM PDT 24
Peak memory	194624 kb
Host	smart-3766b6b5-1298-42a2-aff0-11a8b7fc0c65
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145253644 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4145253644
Directory	/workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.309519406
Short name	T545
Test name
Test status
Simulation time	44743125 ps
CPU time	0.62 seconds
Started	Apr 16 12:20:33 PM PDT 24
Finished	Apr 16 12:20:34 PM PDT 24
Peak memory	182548 kb
Host	smart-65cc7198-48b0-41dd-a988-42e79ad58f68
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309519406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.309519406
Directory	/workspace/1.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2040065243
Short name	T516
Test name
Test status
Simulation time	31969800 ps
CPU time	0.58 seconds
Started	Apr 16 12:19:01 PM PDT 24
Finished	Apr 16 12:19:02 PM PDT 24
Peak memory	182368 kb
Host	smart-08058ed6-14aa-4023-af8d-7ebb9c865a98
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040065243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2040065243
Directory	/workspace/1.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4069819232
Short name	T88
Test name
Test status
Simulation time	17327371 ps
CPU time	0.69 seconds
Started	Apr 16 12:21:43 PM PDT 24
Finished	Apr 16 12:21:46 PM PDT 24
Peak memory	190736 kb
Host	smart-715e1298-eb4b-4e5f-aaca-bb5c8f6c61f0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069819232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.4069819232
Directory	/workspace/1.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1757678710
Short name	T482
Test name
Test status
Simulation time	60782386 ps
CPU time	2.4 seconds
Started	Apr 16 12:21:07 PM PDT 24
Finished	Apr 16 12:21:12 PM PDT 24
Peak memory	197056 kb
Host	smart-d5b267b0-4810-4300-a8ad-ae02a64c5176
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757678710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1757678710
Directory	/workspace/1.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2833173585
Short name	T553
Test name
Test status
Simulation time	75531468 ps
CPU time	0.77 seconds
Started	Apr 16 12:21:43 PM PDT 24
Finished	Apr 16 12:21:47 PM PDT 24
Peak memory	181916 kb
Host	smart-1a3564a9-2091-4a12-b72e-b74ee9c4a228
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833173585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in tg_err.2833173585
Directory	/workspace/1.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3626934974
Short name	T502
Test name
Test status
Simulation time	33855732 ps
CPU time	0.72 seconds
Started	Apr 16 12:24:30 PM PDT 24
Finished	Apr 16 12:24:34 PM PDT 24
Peak memory	195032 kb
Host	smart-e8d6b4a1-0d21-4b03-b14d-48acd5ac23de
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626934974 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3626934974
Directory	/workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1042611004
Short name	T534
Test name
Test status
Simulation time	16300368 ps
CPU time	0.58 seconds
Started	Apr 16 12:24:45 PM PDT 24
Finished	Apr 16 12:24:47 PM PDT 24
Peak memory	182468 kb
Host	smart-9c7e38e2-9786-420f-86bd-168635768fbf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042611004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1042611004
Directory	/workspace/10.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3414783711
Short name	T514
Test name
Test status
Simulation time	35812208 ps
CPU time	0.52 seconds
Started	Apr 16 12:24:34 PM PDT 24
Finished	Apr 16 12:24:37 PM PDT 24
Peak memory	181972 kb
Host	smart-3f09e156-9349-4399-899a-4cb1686d5562
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414783711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3414783711
Directory	/workspace/10.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3062647656
Short name	T85
Test name
Test status
Simulation time	15613295 ps
CPU time	0.65 seconds
Started	Apr 16 12:24:29 PM PDT 24
Finished	Apr 16 12:24:34 PM PDT 24
Peak memory	191408 kb
Host	smart-862c423f-db92-499b-926e-3f088877b73a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062647656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t imer_same_csr_outstanding.3062647656
Directory	/workspace/10.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1513006986
Short name	T466
Test name
Test status
Simulation time	47716694 ps
CPU time	1.02 seconds
Started	Apr 16 12:24:32 PM PDT 24
Finished	Apr 16 12:24:36 PM PDT 24
Peak memory	190908 kb
Host	smart-a6e7e4d0-9b67-4a3e-af93-aeb98f58309a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513006986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1513006986
Directory	/workspace/10.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4069097396
Short name	T555
Test name
Test status
Simulation time	21017828 ps
CPU time	0.63 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	192916 kb
Host	smart-ca853fad-a60a-477b-9104-67223789afcf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069097396 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4069097396
Directory	/workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_intr_test.169560767
Short name	T457
Test name
Test status
Simulation time	32022166 ps
CPU time	0.54 seconds
Started	Apr 16 12:24:31 PM PDT 24
Finished	Apr 16 12:24:35 PM PDT 24
Peak memory	182448 kb
Host	smart-7d2acbdd-2edf-4e44-bbc8-5bd01649dd7c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169560767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.169560767
Directory	/workspace/11.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.298056814
Short name	T570
Test name
Test status
Simulation time	125513767 ps
CPU time	1.42 seconds
Started	Apr 16 12:24:30 PM PDT 24
Finished	Apr 16 12:24:35 PM PDT 24
Peak memory	197476 kb
Host	smart-8be2e48a-8ea8-402e-ac0f-cbd29de67e07
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298056814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.298056814
Directory	/workspace/11.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.709439976
Short name	T551
Test name
Test status
Simulation time	67202525 ps
CPU time	1.07 seconds
Started	Apr 16 12:24:38 PM PDT 24
Finished	Apr 16 12:24:41 PM PDT 24
Peak memory	195240 kb
Host	smart-16e99650-7943-4ee1-afab-37c668dc8c72
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709439976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in tg_err.709439976
Directory	/workspace/11.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.359584645
Short name	T567
Test name
Test status
Simulation time	86482358 ps
CPU time	0.8 seconds
Started	Apr 16 12:24:58 PM PDT 24
Finished	Apr 16 12:25:01 PM PDT 24
Peak memory	195364 kb
Host	smart-1e7e85ac-ed94-4c0c-b2d3-150abe17517c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359584645 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.359584645
Directory	/workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4240535973
Short name	T97
Test name
Test status
Simulation time	18537901 ps
CPU time	0.55 seconds
Started	Apr 16 12:25:04 PM PDT 24
Finished	Apr 16 12:25:10 PM PDT 24
Peak memory	182552 kb
Host	smart-8e1676f6-5e81-41fa-a6b0-7f92bf342c8c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240535973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4240535973
Directory	/workspace/12.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_intr_test.155668129
Short name	T562
Test name
Test status
Simulation time	38815309 ps
CPU time	0.53 seconds
Started	Apr 16 12:25:03 PM PDT 24
Finished	Apr 16 12:25:08 PM PDT 24
Peak memory	182176 kb
Host	smart-d7598922-f90e-4ae7-9ae3-94dcd98a6643
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155668129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.155668129
Directory	/workspace/12.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.8061537
Short name	T73
Test name
Test status
Simulation time	20728478 ps
CPU time	0.6 seconds
Started	Apr 16 12:24:55 PM PDT 24
Finished	Apr 16 12:24:57 PM PDT 24
Peak memory	191584 kb
Host	smart-11197aa7-e8f6-486a-be2f-1693461fb9fd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8061537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_time r_same_csr_outstanding.8061537
Directory	/workspace/12.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3925271706
Short name	T525
Test name
Test status
Simulation time	164024082 ps
CPU time	2.65 seconds
Started	Apr 16 12:25:01 PM PDT 24
Finished	Apr 16 12:25:07 PM PDT 24
Peak memory	197468 kb
Host	smart-f3dfd975-4a9c-4ffe-a511-7dd5944a4aec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925271706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3925271706
Directory	/workspace/12.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1187710958
Short name	T560
Test name
Test status
Simulation time	336683794 ps
CPU time	1.15 seconds
Started	Apr 16 12:24:46 PM PDT 24
Finished	Apr 16 12:24:48 PM PDT 24
Peak memory	195200 kb
Host	smart-7e6887da-f585-4a89-82dc-9be7cd202e0b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187710958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.1187710958
Directory	/workspace/12.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.58456979
Short name	T572
Test name
Test status
Simulation time	70029487 ps
CPU time	0.7 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:24:58 PM PDT 24
Peak memory	194900 kb
Host	smart-8f7770dc-656b-47af-a677-c29609fc391e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58456979 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.58456979
Directory	/workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3496310892
Short name	T56
Test name
Test status
Simulation time	52761338 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:54 PM PDT 24
Finished	Apr 16 12:24:56 PM PDT 24
Peak memory	182640 kb
Host	smart-b6b6b314-fc1d-459b-af35-422619748ae6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496310892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3496310892
Directory	/workspace/13.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2372740748
Short name	T453
Test name
Test status
Simulation time	48362101 ps
CPU time	0.56 seconds
Started	Apr 16 12:24:49 PM PDT 24
Finished	Apr 16 12:24:52 PM PDT 24
Peak memory	182492 kb
Host	smart-257838ed-316b-4cb7-8885-ba67facf0b8f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372740748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2372740748
Directory	/workspace/13.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4227744619
Short name	T84
Test name
Test status
Simulation time	98040218 ps
CPU time	0.7 seconds
Started	Apr 16 12:25:06 PM PDT 24
Finished	Apr 16 12:25:12 PM PDT 24
Peak memory	191932 kb
Host	smart-fd4f36fa-ae71-4263-a571-f71559f23c98
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227744619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t imer_same_csr_outstanding.4227744619
Directory	/workspace/13.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.343391913
Short name	T464
Test name
Test status
Simulation time	366743806 ps
CPU time	1.88 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:25:00 PM PDT 24
Peak memory	197540 kb
Host	smart-1413b106-920b-4d4c-865a-8d0f04415994
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343391913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.343391913
Directory	/workspace/13.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2378013634
Short name	T31
Test name
Test status
Simulation time	295014780 ps
CPU time	1.1 seconds
Started	Apr 16 12:25:02 PM PDT 24
Finished	Apr 16 12:25:06 PM PDT 24
Peak memory	194172 kb
Host	smart-1ec0c49d-ecf7-4ed0-9091-9bb4f85e4a25
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378013634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.2378013634
Directory	/workspace/13.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.777472358
Short name	T575
Test name
Test status
Simulation time	24550043 ps
CPU time	1.17 seconds
Started	Apr 16 12:24:57 PM PDT 24
Finished	Apr 16 12:25:00 PM PDT 24
Peak memory	197272 kb
Host	smart-6f34dc18-7304-45bc-be8d-f87be75be5ac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777472358 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.777472358
Directory	/workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1436563838
Short name	T520
Test name
Test status
Simulation time	15426107 ps
CPU time	0.58 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	182656 kb
Host	smart-e14112c1-ba11-4dce-b199-9812cf7f1f81
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436563838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1436563838
Directory	/workspace/14.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2469269272
Short name	T486
Test name
Test status
Simulation time	207295582 ps
CPU time	0.59 seconds
Started	Apr 16 12:24:49 PM PDT 24
Finished	Apr 16 12:24:52 PM PDT 24
Peak memory	182536 kb
Host	smart-92ce0f21-26d7-4b91-b410-a384441069f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469269272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2469269272
Directory	/workspace/14.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1753086721
Short name	T524
Test name
Test status
Simulation time	108332624 ps
CPU time	0.68 seconds
Started	Apr 16 12:24:49 PM PDT 24
Finished	Apr 16 12:24:52 PM PDT 24
Peak memory	191536 kb
Host	smart-96cec939-3cc6-41eb-bb00-03b2170482ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753086721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.1753086721
Directory	/workspace/14.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2775777540
Short name	T469
Test name
Test status
Simulation time	463393290 ps
CPU time	2.64 seconds
Started	Apr 16 12:24:57 PM PDT 24
Finished	Apr 16 12:25:02 PM PDT 24
Peak memory	197428 kb
Host	smart-3dc44d5a-8b85-4e37-b81a-08835d3b32c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775777540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2775777540
Directory	/workspace/14.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2373844017
Short name	T527
Test name
Test status
Simulation time	247134819 ps
CPU time	1.36 seconds
Started	Apr 16 12:24:57 PM PDT 24
Finished	Apr 16 12:25:01 PM PDT 24
Peak memory	183212 kb
Host	smart-7b28283c-b9dd-48f9-9c72-a434c66f33f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373844017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.2373844017
Directory	/workspace/14.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.305061930
Short name	T497
Test name
Test status
Simulation time	34519090 ps
CPU time	0.86 seconds
Started	Apr 16 12:24:46 PM PDT 24
Finished	Apr 16 12:24:48 PM PDT 24
Peak memory	196676 kb
Host	smart-b104e011-473c-49ab-a770-cac7a0062f04
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305061930 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.305061930
Directory	/workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.57024908
Short name	T77
Test name
Test status
Simulation time	18974752 ps
CPU time	0.53 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	182564 kb
Host	smart-046227ce-2c4c-4ebc-850b-68e6ddb1b824
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57024908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.57024908
Directory	/workspace/15.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_intr_test.838781122
Short name	T539
Test name
Test status
Simulation time	50329231 ps
CPU time	0.56 seconds
Started	Apr 16 12:24:57 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	182508 kb
Host	smart-dff56be5-b2a7-47ea-b464-6d8387a9c2e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838781122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.838781122
Directory	/workspace/15.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.698482820
Short name	T512
Test name
Test status
Simulation time	33776422 ps
CPU time	0.61 seconds
Started	Apr 16 12:25:03 PM PDT 24
Finished	Apr 16 12:25:08 PM PDT 24
Peak memory	191588 kb
Host	smart-0054d931-1925-4b02-9ca8-f7a16456c378
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698482820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti mer_same_csr_outstanding.698482820
Directory	/workspace/15.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1436766887
Short name	T492
Test name
Test status
Simulation time	217927198 ps
CPU time	2.37 seconds
Started	Apr 16 12:25:13 PM PDT 24
Finished	Apr 16 12:25:19 PM PDT 24
Peak memory	197372 kb
Host	smart-5a7a31db-0e42-4232-9b35-db33795aabb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436766887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1436766887
Directory	/workspace/15.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.669381888
Short name	T549
Test name
Test status
Simulation time	44504341 ps
CPU time	0.9 seconds
Started	Apr 16 12:25:00 PM PDT 24
Finished	Apr 16 12:25:04 PM PDT 24
Peak memory	193004 kb
Host	smart-33b76877-6331-48ea-87e4-20dcc336d603
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669381888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in tg_err.669381888
Directory	/workspace/15.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3263770196
Short name	T475
Test name
Test status
Simulation time	22148975 ps
CPU time	0.66 seconds
Started	Apr 16 12:24:57 PM PDT 24
Finished	Apr 16 12:25:00 PM PDT 24
Peak memory	194396 kb
Host	smart-06b5fe50-343c-45b4-afda-a386c30f11d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263770196 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3263770196
Directory	/workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4248517223
Short name	T556
Test name
Test status
Simulation time	51232911 ps
CPU time	0.61 seconds
Started	Apr 16 12:24:59 PM PDT 24
Finished	Apr 16 12:25:01 PM PDT 24
Peak memory	182536 kb
Host	smart-bbc3229b-3287-4d07-b053-d595ba50e37a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248517223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4248517223
Directory	/workspace/16.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2709659512
Short name	T494
Test name
Test status
Simulation time	87774217 ps
CPU time	0.62 seconds
Started	Apr 16 12:25:02 PM PDT 24
Finished	Apr 16 12:25:06 PM PDT 24
Peak memory	182144 kb
Host	smart-351aaa05-1513-40a3-9de7-3fb1d0e46a17
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709659512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2709659512
Directory	/workspace/16.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1049693130
Short name	T563
Test name
Test status
Simulation time	16920820 ps
CPU time	0.61 seconds
Started	Apr 16 12:25:14 PM PDT 24
Finished	Apr 16 12:25:18 PM PDT 24
Peak memory	191256 kb
Host	smart-c64ea48d-7f66-4f9e-bdc0-a21d266bdf46
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049693130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t imer_same_csr_outstanding.1049693130
Directory	/workspace/16.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3786414838
Short name	T574
Test name
Test status
Simulation time	20419840 ps
CPU time	0.98 seconds
Started	Apr 16 12:24:55 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	197280 kb
Host	smart-41d3c825-71e9-439f-972e-78fde59e6913
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786414838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3786414838
Directory	/workspace/16.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.948239419
Short name	T102
Test name
Test status
Simulation time	135860968 ps
CPU time	1.07 seconds
Started	Apr 16 12:24:49 PM PDT 24
Finished	Apr 16 12:24:52 PM PDT 24
Peak memory	194988 kb
Host	smart-e5a7d2cd-9087-431d-a34c-41c9235b8800
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948239419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in tg_err.948239419
Directory	/workspace/16.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.641866195
Short name	T478
Test name
Test status
Simulation time	17454972 ps
CPU time	0.61 seconds
Started	Apr 16 12:24:58 PM PDT 24
Finished	Apr 16 12:25:01 PM PDT 24
Peak memory	193020 kb
Host	smart-3596aa6c-6c95-4f53-8d26-e1f7c4d8e1af
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641866195 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.641866195
Directory	/workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3141281397
Short name	T565
Test name
Test status
Simulation time	76997076 ps
CPU time	0.61 seconds
Started	Apr 16 12:24:41 PM PDT 24
Finished	Apr 16 12:24:44 PM PDT 24
Peak memory	182644 kb
Host	smart-5680a81d-b170-4682-bbc3-5e1d6fe832ca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141281397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3141281397
Directory	/workspace/17.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_intr_test.601346640
Short name	T506
Test name
Test status
Simulation time	15817891 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:59 PM PDT 24
Finished	Apr 16 12:25:02 PM PDT 24
Peak memory	182408 kb
Host	smart-bcf49d55-b377-46d7-9ff9-6633a6c91dee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601346640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.601346640
Directory	/workspace/17.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2717310829
Short name	T548
Test name
Test status
Simulation time	33642983 ps
CPU time	0.78 seconds
Started	Apr 16 12:24:58 PM PDT 24
Finished	Apr 16 12:25:01 PM PDT 24
Peak memory	193184 kb
Host	smart-72378377-b7aa-4250-945f-852035c86d71
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717310829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t imer_same_csr_outstanding.2717310829
Directory	/workspace/17.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.603285423
Short name	T487
Test name
Test status
Simulation time	222558796 ps
CPU time	1.36 seconds
Started	Apr 16 12:24:48 PM PDT 24
Finished	Apr 16 12:24:50 PM PDT 24
Peak memory	197536 kb
Host	smart-2c27105f-7f28-490f-ad36-2bc63cb05725
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603285423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.603285423
Directory	/workspace/17.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1138962789
Short name	T504
Test name
Test status
Simulation time	1181440734 ps
CPU time	1.09 seconds
Started	Apr 16 12:24:51 PM PDT 24
Finished	Apr 16 12:24:53 PM PDT 24
Peak memory	194924 kb
Host	smart-0c01054f-5706-4b66-ac9c-8a1ed8d4aedd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138962789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i ntg_err.1138962789
Directory	/workspace/17.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3883567959
Short name	T501
Test name
Test status
Simulation time	70955863 ps
CPU time	0.79 seconds
Started	Apr 16 12:25:00 PM PDT 24
Finished	Apr 16 12:25:03 PM PDT 24
Peak memory	196536 kb
Host	smart-383aec8c-5daf-4321-b9b2-fd32faaa5ead
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883567959 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3883567959
Directory	/workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.985322226
Short name	T531
Test name
Test status
Simulation time	23415229 ps
CPU time	0.54 seconds
Started	Apr 16 12:25:02 PM PDT 24
Finished	Apr 16 12:25:07 PM PDT 24
Peak memory	182388 kb
Host	smart-e4d7f251-a9d8-4355-aa81-7230b6d00290
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985322226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.985322226
Directory	/workspace/18.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3401408164
Short name	T513
Test name
Test status
Simulation time	58820624 ps
CPU time	0.55 seconds
Started	Apr 16 12:25:14 PM PDT 24
Finished	Apr 16 12:25:18 PM PDT 24
Peak memory	181916 kb
Host	smart-fbcdaccd-7647-48e8-9377-689245a4780c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401408164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3401408164
Directory	/workspace/18.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3468998396
Short name	T74
Test name
Test status
Simulation time	125821244 ps
CPU time	0.67 seconds
Started	Apr 16 12:24:50 PM PDT 24
Finished	Apr 16 12:24:52 PM PDT 24
Peak memory	191948 kb
Host	smart-b1a8e58c-b7f1-4266-becb-9928e387c7bd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468998396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.3468998396
Directory	/workspace/18.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2620805025
Short name	T576
Test name
Test status
Simulation time	30527902 ps
CPU time	1.47 seconds
Started	Apr 16 12:24:59 PM PDT 24
Finished	Apr 16 12:25:03 PM PDT 24
Peak memory	197540 kb
Host	smart-d4062bf0-424d-4913-988b-fac45b0e2506
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620805025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2620805025
Directory	/workspace/18.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4059997920
Short name	T559
Test name
Test status
Simulation time	83815946 ps
CPU time	1.09 seconds
Started	Apr 16 12:25:18 PM PDT 24
Finished	Apr 16 12:25:24 PM PDT 24
Peak memory	194672 kb
Host	smart-ade0e26f-d29e-4079-8de4-0755056f758a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059997920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i ntg_err.4059997920
Directory	/workspace/18.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4069645686
Short name	T462
Test name
Test status
Simulation time	65527294 ps
CPU time	1.44 seconds
Started	Apr 16 12:25:10 PM PDT 24
Finished	Apr 16 12:25:16 PM PDT 24
Peak memory	197532 kb
Host	smart-50b090f6-e0ec-4e65-acd8-5e20505ce46c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069645686 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4069645686
Directory	/workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1261452176
Short name	T488
Test name
Test status
Simulation time	39279592 ps
CPU time	0.56 seconds
Started	Apr 16 12:25:03 PM PDT 24
Finished	Apr 16 12:25:08 PM PDT 24
Peak memory	182632 kb
Host	smart-59cec466-f19f-4dd1-9387-147b4171a144
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261452176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1261452176
Directory	/workspace/19.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2895383454
Short name	T460
Test name
Test status
Simulation time	12358237 ps
CPU time	0.6 seconds
Started	Apr 16 12:25:05 PM PDT 24
Finished	Apr 16 12:25:10 PM PDT 24
Peak memory	182560 kb
Host	smart-289a16a8-0543-4503-8713-09d285d0e3d7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895383454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2895383454
Directory	/workspace/19.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3129217127
Short name	T547
Test name
Test status
Simulation time	130773170 ps
CPU time	0.76 seconds
Started	Apr 16 12:25:02 PM PDT 24
Finished	Apr 16 12:25:06 PM PDT 24
Peak memory	192832 kb
Host	smart-efcdc929-615f-423f-97a6-3f7574c7d123
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129217127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.3129217127
Directory	/workspace/19.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3670812210
Short name	T580
Test name
Test status
Simulation time	29778453 ps
CPU time	1.43 seconds
Started	Apr 16 12:25:01 PM PDT 24
Finished	Apr 16 12:25:05 PM PDT 24
Peak memory	197464 kb
Host	smart-a2697b18-e49b-4877-8958-0ae8ea3d1453
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670812210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3670812210
Directory	/workspace/19.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.97862146
Short name	T103
Test name
Test status
Simulation time	147313552 ps
CPU time	0.78 seconds
Started	Apr 16 12:25:04 PM PDT 24
Finished	Apr 16 12:25:09 PM PDT 24
Peak memory	193304 kb
Host	smart-0e71b1bb-6fa1-43b2-9548-c3673bc53c6c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97862146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_int g_err.97862146
Directory	/workspace/19.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1132959726
Short name	T561
Test name
Test status
Simulation time	34773447 ps
CPU time	0.83 seconds
Started	Apr 16 12:22:24 PM PDT 24
Finished	Apr 16 12:22:27 PM PDT 24
Peak memory	190464 kb
Host	smart-07dc7fc4-966f-4021-8824-ed5710113bb6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132959726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia sing.1132959726
Directory	/workspace/2.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3549193597
Short name	T481
Test name
Test status
Simulation time	175787500 ps
CPU time	3.16 seconds
Started	Apr 16 12:20:07 PM PDT 24
Finished	Apr 16 12:20:11 PM PDT 24
Peak memory	182864 kb
Host	smart-cb8d38b8-cb48-4cd1-9fb9-2315136cf6f9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549193597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ bash.3549193597
Directory	/workspace/2.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2156736991
Short name	T519
Test name
Test status
Simulation time	13388148 ps
CPU time	0.54 seconds
Started	Apr 16 12:22:59 PM PDT 24
Finished	Apr 16 12:23:03 PM PDT 24
Peak memory	180752 kb
Host	smart-461f96b1-69ec-4159-a00e-b7cf45d66bbe
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156736991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r eset.2156736991
Directory	/workspace/2.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.938321105
Short name	T55
Test name
Test status
Simulation time	56326184 ps
CPU time	0.8 seconds
Started	Apr 16 12:22:47 PM PDT 24
Finished	Apr 16 12:22:53 PM PDT 24
Peak memory	193592 kb
Host	smart-1b610791-f05e-4deb-be1b-a0b559c455f1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938321105 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.938321105
Directory	/workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1885938315
Short name	T79
Test name
Test status
Simulation time	18772641 ps
CPU time	0.6 seconds
Started	Apr 16 12:22:59 PM PDT 24
Finished	Apr 16 12:23:03 PM PDT 24
Peak memory	181084 kb
Host	smart-926986fe-30bc-46c4-87fe-34054482b6a7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885938315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1885938315
Directory	/workspace/2.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_intr_test.343411556
Short name	T521
Test name
Test status
Simulation time	46576190 ps
CPU time	0.6 seconds
Started	Apr 16 12:22:24 PM PDT 24
Finished	Apr 16 12:22:27 PM PDT 24
Peak memory	180804 kb
Host	smart-61420d2d-30f6-40a4-8fc3-d7f79ff2d25d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343411556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.343411556
Directory	/workspace/2.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.214455532
Short name	T86
Test name
Test status
Simulation time	104178838 ps
CPU time	0.69 seconds
Started	Apr 16 12:21:13 PM PDT 24
Finished	Apr 16 12:21:15 PM PDT 24
Peak memory	192736 kb
Host	smart-7545d354-3947-401d-a832-a03eda427b76
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214455532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim er_same_csr_outstanding.214455532
Directory	/workspace/2.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.220702153
Short name	T461
Test name
Test status
Simulation time	99052362 ps
CPU time	2.33 seconds
Started	Apr 16 12:22:40 PM PDT 24
Finished	Apr 16 12:22:48 PM PDT 24
Peak memory	197392 kb
Host	smart-e371e8a6-88e8-4af6-bcdf-4d6682fa1c0d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220702153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.220702153
Directory	/workspace/2.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1274928010
Short name	T32
Test name
Test status
Simulation time	99053335 ps
CPU time	1.37 seconds
Started	Apr 16 12:22:59 PM PDT 24
Finished	Apr 16 12:23:04 PM PDT 24
Peak memory	192600 kb
Host	smart-b1aec268-2653-4991-b5fe-ca78ca2d3524
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274928010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in tg_err.1274928010
Directory	/workspace/2.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4190773399
Short name	T498
Test name
Test status
Simulation time	18006157 ps
CPU time	0.51 seconds
Started	Apr 16 12:25:14 PM PDT 24
Finished	Apr 16 12:25:17 PM PDT 24
Peak memory	182012 kb
Host	smart-8d6989e5-99dd-45a3-a096-c962afb14cfe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190773399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4190773399
Directory	/workspace/20.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2651481106
Short name	T533
Test name
Test status
Simulation time	15143928 ps
CPU time	0.6 seconds
Started	Apr 16 12:25:01 PM PDT 24
Finished	Apr 16 12:25:05 PM PDT 24
Peak memory	182456 kb
Host	smart-7dbbde08-5c68-4d3a-92b1-4a80d71f1879
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651481106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2651481106
Directory	/workspace/21.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.rv_timer_intr_test.27089645
Short name	T507
Test name
Test status
Simulation time	156399328 ps
CPU time	0.51 seconds
Started	Apr 16 12:25:18 PM PDT 24
Finished	Apr 16 12:25:22 PM PDT 24
Peak memory	182256 kb
Host	smart-846e5a86-974f-4334-859d-1026b3f79edf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27089645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.27089645
Directory	/workspace/22.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2338616575
Short name	T566
Test name
Test status
Simulation time	56450147 ps
CPU time	0.53 seconds
Started	Apr 16 12:25:12 PM PDT 24
Finished	Apr 16 12:25:16 PM PDT 24
Peak memory	181856 kb
Host	smart-195f8a08-dbfe-4c61-9f1f-47fed057db77
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338616575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2338616575
Directory	/workspace/23.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1779928900
Short name	T456
Test name
Test status
Simulation time	124663491 ps
CPU time	0.55 seconds
Started	Apr 16 12:25:03 PM PDT 24
Finished	Apr 16 12:25:08 PM PDT 24
Peak memory	182448 kb
Host	smart-a0e8f8b3-6ef6-42c9-84f8-2f85e80cf4a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779928900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1779928900
Directory	/workspace/24.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4021788509
Short name	T476
Test name
Test status
Simulation time	34854678 ps
CPU time	0.55 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	182532 kb
Host	smart-d1b67226-6fb9-472c-82c8-ce1d2f5fc043
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021788509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4021788509
Directory	/workspace/25.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1282654760
Short name	T463
Test name
Test status
Simulation time	17980717 ps
CPU time	0.53 seconds
Started	Apr 16 12:25:18 PM PDT 24
Finished	Apr 16 12:25:23 PM PDT 24
Peak memory	181896 kb
Host	smart-d33c5a9b-136c-4a39-9deb-eeec28aa738d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282654760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1282654760
Directory	/workspace/26.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3900051498
Short name	T465
Test name
Test status
Simulation time	68927227 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:50 PM PDT 24
Finished	Apr 16 12:24:52 PM PDT 24
Peak memory	182524 kb
Host	smart-5011505e-a7bb-4a35-b148-2b99754de731
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900051498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3900051498
Directory	/workspace/27.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.rv_timer_intr_test.656678299
Short name	T518
Test name
Test status
Simulation time	17675809 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	182352 kb
Host	smart-a0445df3-c9d0-49e9-8b05-9d62dbfa0ae1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656678299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.656678299
Directory	/workspace/28.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1696121016
Short name	T493
Test name
Test status
Simulation time	18891431 ps
CPU time	0.53 seconds
Started	Apr 16 12:25:10 PM PDT 24
Finished	Apr 16 12:25:15 PM PDT 24
Peak memory	182100 kb
Host	smart-483d01b4-b479-4e85-ac55-c2e72f070ac7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696121016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1696121016
Directory	/workspace/29.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1957011383
Short name	T542
Test name
Test status
Simulation time	169690393 ps
CPU time	0.59 seconds
Started	Apr 16 12:24:32 PM PDT 24
Finished	Apr 16 12:24:36 PM PDT 24
Peak memory	182536 kb
Host	smart-09d92ce2-3d64-48f0-8a53-f4d96962e753
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957011383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.1957011383
Directory	/workspace/3.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2951003297
Short name	T532
Test name
Test status
Simulation time	201089030 ps
CPU time	1.55 seconds
Started	Apr 16 12:24:36 PM PDT 24
Finished	Apr 16 12:24:41 PM PDT 24
Peak memory	191100 kb
Host	smart-3037753a-c9c4-4d07-99ae-78088cb2c370
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951003297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.2951003297
Directory	/workspace/3.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1923709850
Short name	T529
Test name
Test status
Simulation time	13723559 ps
CPU time	0.56 seconds
Started	Apr 16 12:24:32 PM PDT 24
Finished	Apr 16 12:24:35 PM PDT 24
Peak memory	182104 kb
Host	smart-bfa6ccac-9299-4cdd-8fae-05cbebcef058
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923709850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.1923709850
Directory	/workspace/3.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.850132158
Short name	T35
Test name
Test status
Simulation time	273159229 ps
CPU time	1.58 seconds
Started	Apr 16 12:24:31 PM PDT 24
Finished	Apr 16 12:24:41 PM PDT 24
Peak memory	197528 kb
Host	smart-940935c1-c1d7-4d2c-93dc-2b1ebeaa9fff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850132158 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.850132158
Directory	/workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.464868143
Short name	T33
Test name
Test status
Simulation time	42457203 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:29 PM PDT 24
Finished	Apr 16 12:24:33 PM PDT 24
Peak memory	182656 kb
Host	smart-0345707d-88d2-4e02-9627-827fa9cd0ed9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464868143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.464868143
Directory	/workspace/3.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1553672174
Short name	T496
Test name
Test status
Simulation time	18561134 ps
CPU time	0.53 seconds
Started	Apr 16 12:21:04 PM PDT 24
Finished	Apr 16 12:21:07 PM PDT 24
Peak memory	180772 kb
Host	smart-0b29a06b-5f40-44ad-b4b7-2841ef013ec5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553672174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1553672174
Directory	/workspace/3.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.232727949
Short name	T75
Test name
Test status
Simulation time	145700601 ps
CPU time	0.73 seconds
Started	Apr 16 12:24:38 PM PDT 24
Finished	Apr 16 12:24:41 PM PDT 24
Peak memory	193116 kb
Host	smart-10a592c5-1241-40cd-a59a-cef4910c45cc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232727949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim er_same_csr_outstanding.232727949
Directory	/workspace/3.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2200382301
Short name	T57
Test name
Test status
Simulation time	61743459 ps
CPU time	1.3 seconds
Started	Apr 16 12:21:12 PM PDT 24
Finished	Apr 16 12:21:14 PM PDT 24
Peak memory	196536 kb
Host	smart-c3a116c8-5e59-4836-81ee-3ec391531582
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200382301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2200382301
Directory	/workspace/3.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1713826904
Short name	T100
Test name
Test status
Simulation time	414898839 ps
CPU time	1.11 seconds
Started	Apr 16 12:21:05 PM PDT 24
Finished	Apr 16 12:21:09 PM PDT 24
Peak memory	182916 kb
Host	smart-7a501b5e-fdd0-42db-b75d-5b35001222f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713826904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.1713826904
Directory	/workspace/3.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1659870975
Short name	T540
Test name
Test status
Simulation time	51753298 ps
CPU time	0.54 seconds
Started	Apr 16 12:25:14 PM PDT 24
Finished	Apr 16 12:25:17 PM PDT 24
Peak memory	182552 kb
Host	smart-dfc81dfc-c4e5-4629-aed6-ea3b9994c6aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659870975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1659870975
Directory	/workspace/30.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3015441155
Short name	T491
Test name
Test status
Simulation time	28186645 ps
CPU time	0.57 seconds
Started	Apr 16 12:25:04 PM PDT 24
Finished	Apr 16 12:25:09 PM PDT 24
Peak memory	182496 kb
Host	smart-03fa391c-1ca7-44dc-8518-36b11b0b294e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015441155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3015441155
Directory	/workspace/31.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3979564830
Short name	T517
Test name
Test status
Simulation time	33788644 ps
CPU time	0.57 seconds
Started	Apr 16 12:25:10 PM PDT 24
Finished	Apr 16 12:25:15 PM PDT 24
Peak memory	182476 kb
Host	smart-162e10be-dc9d-4d42-b497-28ebdec17815
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979564830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3979564830
Directory	/workspace/32.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3966211488
Short name	T544
Test name
Test status
Simulation time	65519407 ps
CPU time	0.57 seconds
Started	Apr 16 12:25:12 PM PDT 24
Finished	Apr 16 12:25:16 PM PDT 24
Peak memory	182472 kb
Host	smart-25649c30-33fe-4540-8901-e700a1dee380
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966211488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3966211488
Directory	/workspace/33.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2994409971
Short name	T458
Test name
Test status
Simulation time	40680942 ps
CPU time	0.53 seconds
Started	Apr 16 12:25:16 PM PDT 24
Finished	Apr 16 12:25:20 PM PDT 24
Peak memory	182492 kb
Host	smart-a9eba588-c7ee-4847-afa3-4e4843b15038
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994409971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2994409971
Directory	/workspace/34.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.rv_timer_intr_test.563438496
Short name	T528
Test name
Test status
Simulation time	25362193 ps
CPU time	0.52 seconds
Started	Apr 16 12:24:52 PM PDT 24
Finished	Apr 16 12:24:53 PM PDT 24
Peak memory	181984 kb
Host	smart-0b5370e4-9d1b-4855-951c-59049bf1de45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563438496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.563438496
Directory	/workspace/35.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2010230226
Short name	T500
Test name
Test status
Simulation time	100145815 ps
CPU time	0.55 seconds
Started	Apr 16 12:24:55 PM PDT 24
Finished	Apr 16 12:24:57 PM PDT 24
Peak memory	182528 kb
Host	smart-029607fb-abf6-4945-8bd8-559b96af7b86
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010230226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2010230226
Directory	/workspace/36.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3835415647
Short name	T483
Test name
Test status
Simulation time	18329567 ps
CPU time	0.56 seconds
Started	Apr 16 12:25:02 PM PDT 24
Finished	Apr 16 12:25:06 PM PDT 24
Peak memory	182300 kb
Host	smart-550cbe43-75eb-40f0-b1a3-63d98b283c90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835415647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3835415647
Directory	/workspace/37.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1600928777
Short name	T472
Test name
Test status
Simulation time	91125793 ps
CPU time	0.53 seconds
Started	Apr 16 12:24:57 PM PDT 24
Finished	Apr 16 12:25:00 PM PDT 24
Peak memory	182484 kb
Host	smart-380df6cc-ec32-401f-8f44-415c5f9534ef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600928777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1600928777
Directory	/workspace/38.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2896006739
Short name	T526
Test name
Test status
Simulation time	43129394 ps
CPU time	0.56 seconds
Started	Apr 16 12:24:47 PM PDT 24
Finished	Apr 16 12:24:48 PM PDT 24
Peak memory	181984 kb
Host	smart-93d334d3-07bb-41d3-93fc-9dada6c6dbc3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896006739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2896006739
Directory	/workspace/39.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3410411300
Short name	T510
Test name
Test status
Simulation time	34390362 ps
CPU time	0.62 seconds
Started	Apr 16 12:24:37 PM PDT 24
Finished	Apr 16 12:24:40 PM PDT 24
Peak memory	182580 kb
Host	smart-a8f3f967-3dd7-4890-8f99-6f22e3d747fa
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410411300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.3410411300
Directory	/workspace/4.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1813907178
Short name	T557
Test name
Test status
Simulation time	62315543 ps
CPU time	2.26 seconds
Started	Apr 16 12:24:29 PM PDT 24
Finished	Apr 16 12:24:35 PM PDT 24
Peak memory	193148 kb
Host	smart-b4b80c87-9993-414b-baf7-f879317f95d2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813907178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.1813907178
Directory	/workspace/4.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2610319059
Short name	T80
Test name
Test status
Simulation time	54973026 ps
CPU time	0.55 seconds
Started	Apr 16 12:24:36 PM PDT 24
Finished	Apr 16 12:24:40 PM PDT 24
Peak memory	182520 kb
Host	smart-4cf49e48-2d76-4ff7-af5d-fd6ed4c3d347
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610319059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.2610319059
Directory	/workspace/4.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1846088058
Short name	T581
Test name
Test status
Simulation time	34983573 ps
CPU time	1.51 seconds
Started	Apr 16 12:24:32 PM PDT 24
Finished	Apr 16 12:24:37 PM PDT 24
Peak memory	197200 kb
Host	smart-dc3af583-36cf-4e9b-abc7-801952fbee3d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846088058 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1846088058
Directory	/workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3308112182
Short name	T54
Test name
Test status
Simulation time	76706515 ps
CPU time	0.54 seconds
Started	Apr 16 12:24:34 PM PDT 24
Finished	Apr 16 12:24:37 PM PDT 24
Peak memory	182336 kb
Host	smart-82e9c1e0-ab65-4992-a214-840f7cf1a07d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308112182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3308112182
Directory	/workspace/4.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_intr_test.65817021
Short name	T490
Test name
Test status
Simulation time	28134316 ps
CPU time	0.56 seconds
Started	Apr 16 12:24:48 PM PDT 24
Finished	Apr 16 12:24:50 PM PDT 24
Peak memory	181800 kb
Host	smart-e601e9f1-408c-4fe5-9d04-1e99c04515d2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65817021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.65817021
Directory	/workspace/4.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.143464931
Short name	T530
Test name
Test status
Simulation time	57884069 ps
CPU time	0.71 seconds
Started	Apr 16 12:24:52 PM PDT 24
Finished	Apr 16 12:24:54 PM PDT 24
Peak memory	191464 kb
Host	smart-22c1e506-404c-4293-9c90-30356720e84c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143464931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim er_same_csr_outstanding.143464931
Directory	/workspace/4.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.667248369
Short name	T523
Test name
Test status
Simulation time	199967014 ps
CPU time	2.04 seconds
Started	Apr 16 12:24:35 PM PDT 24
Finished	Apr 16 12:24:40 PM PDT 24
Peak memory	197516 kb
Host	smart-c0444fd0-19bd-4459-80ab-cc914adb3732
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667248369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.667248369
Directory	/workspace/4.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1765350714
Short name	T535
Test name
Test status
Simulation time	403616449 ps
CPU time	1.26 seconds
Started	Apr 16 12:24:32 PM PDT 24
Finished	Apr 16 12:24:37 PM PDT 24
Peak memory	182892 kb
Host	smart-9b865e2c-b33d-4783-9927-8d28502c4202
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765350714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.1765350714
Directory	/workspace/4.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.rv_timer_intr_test.635969385
Short name	T455
Test name
Test status
Simulation time	41733818 ps
CPU time	0.59 seconds
Started	Apr 16 12:24:54 PM PDT 24
Finished	Apr 16 12:24:57 PM PDT 24
Peak memory	181988 kb
Host	smart-3d609805-2f25-48bc-ad5b-b1960a319cf5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635969385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.635969385
Directory	/workspace/40.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2065756889
Short name	T541
Test name
Test status
Simulation time	16334187 ps
CPU time	0.59 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	182532 kb
Host	smart-5753a12a-a436-4c51-ae46-568306c35353
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065756889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2065756889
Directory	/workspace/41.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.rv_timer_intr_test.995676418
Short name	T538
Test name
Test status
Simulation time	10993250 ps
CPU time	0.54 seconds
Started	Apr 16 12:25:02 PM PDT 24
Finished	Apr 16 12:25:07 PM PDT 24
Peak memory	182480 kb
Host	smart-c30ff43b-8bb9-4be7-801b-a7332aee55fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995676418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.995676418
Directory	/workspace/42.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2246951812
Short name	T499
Test name
Test status
Simulation time	16203182 ps
CPU time	0.64 seconds
Started	Apr 16 12:24:54 PM PDT 24
Finished	Apr 16 12:24:56 PM PDT 24
Peak memory	182476 kb
Host	smart-15fd0cb8-5488-4b78-99d0-dea2e9afdb29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246951812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2246951812
Directory	/workspace/43.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1866611361
Short name	T564
Test name
Test status
Simulation time	19946852 ps
CPU time	0.57 seconds
Started	Apr 16 12:25:00 PM PDT 24
Finished	Apr 16 12:25:03 PM PDT 24
Peak memory	182432 kb
Host	smart-f04fbadb-9f57-4e0d-a5c9-8796f20a2a25
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866611361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1866611361
Directory	/workspace/44.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1255738946
Short name	T582
Test name
Test status
Simulation time	32765067 ps
CPU time	0.51 seconds
Started	Apr 16 12:24:55 PM PDT 24
Finished	Apr 16 12:24:57 PM PDT 24
Peak memory	181880 kb
Host	smart-fd83a156-5843-4d82-9fc3-17a7b7f27986
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255738946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1255738946
Directory	/workspace/45.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.rv_timer_intr_test.559567631
Short name	T485
Test name
Test status
Simulation time	14176538 ps
CPU time	0.6 seconds
Started	Apr 16 12:25:17 PM PDT 24
Finished	Apr 16 12:25:22 PM PDT 24
Peak memory	182508 kb
Host	smart-1efb5732-3c82-4cde-8984-8de6c29fdb06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559567631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.559567631
Directory	/workspace/46.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.rv_timer_intr_test.423336336
Short name	T467
Test name
Test status
Simulation time	73115048 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:57 PM PDT 24
Finished	Apr 16 12:25:00 PM PDT 24
Peak memory	182464 kb
Host	smart-9364a63b-2562-47b9-8b63-c770abe973b6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423336336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.423336336
Directory	/workspace/47.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.rv_timer_intr_test.147364641
Short name	T454
Test name
Test status
Simulation time	13399115 ps
CPU time	0.58 seconds
Started	Apr 16 12:25:18 PM PDT 24
Finished	Apr 16 12:25:23 PM PDT 24
Peak memory	181848 kb
Host	smart-e8222d9f-ac5e-49da-abf7-ffee677fea01
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147364641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.147364641
Directory	/workspace/48.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4066062210
Short name	T537
Test name
Test status
Simulation time	85089938 ps
CPU time	0.55 seconds
Started	Apr 16 12:25:21 PM PDT 24
Finished	Apr 16 12:25:26 PM PDT 24
Peak memory	182396 kb
Host	smart-63ab251c-3a28-4e06-af33-6cb6b93687ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066062210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4066062210
Directory	/workspace/49.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2532534924
Short name	T508
Test name
Test status
Simulation time	46491049 ps
CPU time	0.99 seconds
Started	Apr 16 12:25:02 PM PDT 24
Finished	Apr 16 12:25:07 PM PDT 24
Peak memory	197016 kb
Host	smart-4885ee08-0389-48fb-ad17-5cf906747ec3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532534924 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2532534924
Directory	/workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2698960692
Short name	T489
Test name
Test status
Simulation time	81453532 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:32 PM PDT 24
Finished	Apr 16 12:24:35 PM PDT 24
Peak memory	182620 kb
Host	smart-d6db543f-6907-46a9-b55a-e0a3e5b1001b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698960692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2698960692
Directory	/workspace/5.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2306469304
Short name	T578
Test name
Test status
Simulation time	47248933 ps
CPU time	0.55 seconds
Started	Apr 16 12:24:41 PM PDT 24
Finished	Apr 16 12:24:43 PM PDT 24
Peak memory	182424 kb
Host	smart-f83c3b90-d744-4506-9943-d9910de3b119
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306469304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2306469304
Directory	/workspace/5.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1618365269
Short name	T34
Test name
Test status
Simulation time	27796142 ps
CPU time	0.62 seconds
Started	Apr 16 12:24:30 PM PDT 24
Finished	Apr 16 12:24:34 PM PDT 24
Peak memory	191544 kb
Host	smart-d3441c19-b64d-441a-a3c7-415ad4be0e55
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618365269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.1618365269
Directory	/workspace/5.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2627513567
Short name	T503
Test name
Test status
Simulation time	338682099 ps
CPU time	1.79 seconds
Started	Apr 16 12:24:34 PM PDT 24
Finished	Apr 16 12:24:39 PM PDT 24
Peak memory	197400 kb
Host	smart-56398914-502a-401b-838e-c00261ffc3af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627513567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2627513567
Directory	/workspace/5.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2028154350
Short name	T571
Test name
Test status
Simulation time	566012472 ps
CPU time	0.81 seconds
Started	Apr 16 12:24:34 PM PDT 24
Finished	Apr 16 12:24:38 PM PDT 24
Peak memory	193432 kb
Host	smart-8440d701-6f22-42e7-bdd5-e0b1d9e89463
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028154350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in tg_err.2028154350
Directory	/workspace/5.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2809895489
Short name	T569
Test name
Test status
Simulation time	55485846 ps
CPU time	0.64 seconds
Started	Apr 16 12:24:40 PM PDT 24
Finished	Apr 16 12:24:43 PM PDT 24
Peak memory	194080 kb
Host	smart-b3139600-ee1e-4c20-8f65-eee467ee7eba
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809895489 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2809895489
Directory	/workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3375794188
Short name	T543
Test name
Test status
Simulation time	22380147 ps
CPU time	0.54 seconds
Started	Apr 16 12:24:29 PM PDT 24
Finished	Apr 16 12:24:33 PM PDT 24
Peak memory	182468 kb
Host	smart-e56f116b-c8a3-4481-8f0a-fafcd56990ac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375794188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3375794188
Directory	/workspace/6.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3450328750
Short name	T546
Test name
Test status
Simulation time	16334422 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:29 PM PDT 24
Finished	Apr 16 12:24:33 PM PDT 24
Peak memory	182432 kb
Host	smart-d35691fb-8165-404e-b5d9-40cca3fc2e9d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450328750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3450328750
Directory	/workspace/6.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.444060589
Short name	T579
Test name
Test status
Simulation time	33858415 ps
CPU time	0.64 seconds
Started	Apr 16 12:24:56 PM PDT 24
Finished	Apr 16 12:24:58 PM PDT 24
Peak memory	191828 kb
Host	smart-e3a6636b-3163-49f7-8efb-d3913307e5ca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444060589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim er_same_csr_outstanding.444060589
Directory	/workspace/6.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4134323547
Short name	T470
Test name
Test status
Simulation time	446393709 ps
CPU time	2.37 seconds
Started	Apr 16 12:24:55 PM PDT 24
Finished	Apr 16 12:24:59 PM PDT 24
Peak memory	197456 kb
Host	smart-32be1cd6-c87b-4f5a-9ba5-9434989b8105
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134323547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4134323547
Directory	/workspace/6.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1256078368
Short name	T101
Test name
Test status
Simulation time	397362658 ps
CPU time	1.31 seconds
Started	Apr 16 12:24:49 PM PDT 24
Finished	Apr 16 12:24:52 PM PDT 24
Peak memory	195188 kb
Host	smart-c66bb9b2-372d-455a-83e9-3c69dde34c00
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256078368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.1256078368
Directory	/workspace/6.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1571812807
Short name	T515
Test name
Test status
Simulation time	74927118 ps
CPU time	0.98 seconds
Started	Apr 16 12:24:43 PM PDT 24
Finished	Apr 16 12:24:45 PM PDT 24
Peak memory	197356 kb
Host	smart-9166f799-1593-46f0-bbd4-eb7569c21c59
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571812807 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1571812807
Directory	/workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3789890507
Short name	T82
Test name
Test status
Simulation time	17169582 ps
CPU time	0.52 seconds
Started	Apr 16 12:24:47 PM PDT 24
Finished	Apr 16 12:24:48 PM PDT 24
Peak memory	182660 kb
Host	smart-fefc8819-c248-49b5-ab64-5a9b3a07f61d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789890507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3789890507
Directory	/workspace/7.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1593544633
Short name	T552
Test name
Test status
Simulation time	16297067 ps
CPU time	0.56 seconds
Started	Apr 16 12:24:42 PM PDT 24
Finished	Apr 16 12:24:44 PM PDT 24
Peak memory	182416 kb
Host	smart-22298972-f7b7-4451-8eb3-861fb71e2436
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593544633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1593544633
Directory	/workspace/7.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2981407268
Short name	T577
Test name
Test status
Simulation time	18707145 ps
CPU time	0.71 seconds
Started	Apr 16 12:24:48 PM PDT 24
Finished	Apr 16 12:24:50 PM PDT 24
Peak memory	192032 kb
Host	smart-1d7cf619-e0b4-4672-a910-0908e3630f09
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981407268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti mer_same_csr_outstanding.2981407268
Directory	/workspace/7.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.988284090
Short name	T473
Test name
Test status
Simulation time	744649125 ps
CPU time	1.92 seconds
Started	Apr 16 12:24:49 PM PDT 24
Finished	Apr 16 12:24:53 PM PDT 24
Peak memory	197476 kb
Host	smart-8cd902d4-970c-40fb-b553-46c5f1a4c0ac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988284090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.988284090
Directory	/workspace/7.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2720823054
Short name	T536
Test name
Test status
Simulation time	39956272 ps
CPU time	0.73 seconds
Started	Apr 16 12:24:42 PM PDT 24
Finished	Apr 16 12:24:44 PM PDT 24
Peak memory	195064 kb
Host	smart-844f3778-e3d7-4620-aca5-7410817c6a64
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720823054 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2720823054
Directory	/workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.10051153
Short name	T480
Test name
Test status
Simulation time	13954758 ps
CPU time	0.54 seconds
Started	Apr 16 12:24:30 PM PDT 24
Finished	Apr 16 12:24:34 PM PDT 24
Peak memory	182640 kb
Host	smart-8284afe6-7468-42ab-9769-b20db6fc95c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10051153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.10051153
Directory	/workspace/8.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3905409137
Short name	T479
Test name
Test status
Simulation time	16445271 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:54 PM PDT 24
Finished	Apr 16 12:24:57 PM PDT 24
Peak memory	182340 kb
Host	smart-18e32479-5609-482c-a9c6-6b2e9f915450
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905409137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3905409137
Directory	/workspace/8.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.608696338
Short name	T550
Test name
Test status
Simulation time	26741107 ps
CPU time	0.69 seconds
Started	Apr 16 12:24:31 PM PDT 24
Finished	Apr 16 12:24:35 PM PDT 24
Peak memory	191652 kb
Host	smart-76259125-708d-43c0-a8d6-620c5745213b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608696338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim er_same_csr_outstanding.608696338
Directory	/workspace/8.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3407584683
Short name	T477
Test name
Test status
Simulation time	377652605 ps
CPU time	1.96 seconds
Started	Apr 16 12:24:51 PM PDT 24
Finished	Apr 16 12:24:54 PM PDT 24
Peak memory	197432 kb
Host	smart-ae0de732-383d-4b74-a42c-6536ce54bcb6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407584683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3407584683
Directory	/workspace/8.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.240929419
Short name	T484
Test name
Test status
Simulation time	87361742 ps
CPU time	1.08 seconds
Started	Apr 16 12:24:32 PM PDT 24
Finished	Apr 16 12:24:36 PM PDT 24
Peak memory	183104 kb
Host	smart-0dc67433-43c5-47b3-bfbd-8f1780aaa0ac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240929419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int g_err.240929419
Directory	/workspace/8.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3592147039
Short name	T471
Test name
Test status
Simulation time	38971651 ps
CPU time	0.7 seconds
Started	Apr 16 12:24:44 PM PDT 24
Finished	Apr 16 12:24:46 PM PDT 24
Peak memory	194720 kb
Host	smart-d0022b03-a323-430d-ba0a-f1c1166dc823
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592147039 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3592147039
Directory	/workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3819256011
Short name	T78
Test name
Test status
Simulation time	27114617 ps
CPU time	0.57 seconds
Started	Apr 16 12:24:34 PM PDT 24
Finished	Apr 16 12:24:38 PM PDT 24
Peak memory	182536 kb
Host	smart-0ce4f449-9f65-4a01-88c5-ccefafe6ea05
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819256011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3819256011
Directory	/workspace/9.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3237376058
Short name	T522
Test name
Test status
Simulation time	16428804 ps
CPU time	0.55 seconds
Started	Apr 16 12:24:43 PM PDT 24
Finished	Apr 16 12:24:45 PM PDT 24
Peak memory	182328 kb
Host	smart-8b9b87ae-2bf6-4e8f-851b-2102bdbfac96
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237376058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3237376058
Directory	/workspace/9.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2905424403
Short name	T554
Test name
Test status
Simulation time	58952802 ps
CPU time	0.59 seconds
Started	Apr 16 12:24:40 PM PDT 24
Finished	Apr 16 12:24:43 PM PDT 24
Peak memory	191212 kb
Host	smart-c9baf062-de7a-4d80-91bf-aa6c530f9289
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905424403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.2905424403
Directory	/workspace/9.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1688764067
Short name	T459
Test name
Test status
Simulation time	145771793 ps
CPU time	2.62 seconds
Started	Apr 16 12:24:32 PM PDT 24
Finished	Apr 16 12:24:37 PM PDT 24
Peak memory	197524 kb
Host	smart-ce5cfefb-827c-4a65-9fd9-1bc7d764b0dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688764067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1688764067
Directory	/workspace/9.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3520387768
Short name	T99
Test name
Test status
Simulation time	116051714 ps
CPU time	1.42 seconds
Started	Apr 16 12:24:31 PM PDT 24
Finished	Apr 16 12:24:36 PM PDT 24
Peak memory	183196 kb
Host	smart-049d47ac-27a6-4791-9436-6a7b4656b66a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520387768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.3520387768
Directory	/workspace/9.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1989273828
Short name	T332
Test name
Test status
Simulation time	22924092243 ps
CPU time	42.36 seconds
Started	Apr 16 12:19:26 PM PDT 24
Finished	Apr 16 12:20:09 PM PDT 24
Peak memory	182384 kb
Host	smart-41c5fe50-c267-4842-be50-811bbec8d10c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989273828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.1989273828
Directory	/workspace/0.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/0.rv_timer_disabled.2597034097
Short name	T398
Test name
Test status
Simulation time	431172853536 ps
CPU time	97.98 seconds
Started	Apr 16 12:22:40 PM PDT 24
Finished	Apr 16 12:24:24 PM PDT 24
Peak memory	182440 kb
Host	smart-29675499-a321-49b1-96f1-905ea5b8ec6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597034097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2597034097
Directory	/workspace/0.rv_timer_disabled/latest

Test location	/workspace/coverage/default/0.rv_timer_random_reset.2286253287
Short name	T373
Test name
Test status
Simulation time	25524849 ps
CPU time	0.52 seconds
Started	Apr 16 12:21:05 PM PDT 24
Finished	Apr 16 12:21:07 PM PDT 24
Peak memory	181228 kb
Host	smart-489d5503-59f0-4ab8-b266-7bd8c55e194a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286253287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2286253287
Directory	/workspace/0.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1685896661
Short name	T338
Test name
Test status
Simulation time	583074612242 ps
CPU time	290.66 seconds
Started	Apr 16 12:21:37 PM PDT 24
Finished	Apr 16 12:26:29 PM PDT 24
Peak memory	182384 kb
Host	smart-06256d7e-0175-4c84-896a-10a9427cf790
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685896661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.1685896661
Directory	/workspace/1.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/1.rv_timer_disabled.533859549
Short name	T354
Test name
Test status
Simulation time	94800864714 ps
CPU time	42.03 seconds
Started	Apr 16 12:22:47 PM PDT 24
Finished	Apr 16 12:23:34 PM PDT 24
Peak memory	180700 kb
Host	smart-3efb1ccb-52e0-450d-a22d-0420303f97cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=533859549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.533859549
Directory	/workspace/1.rv_timer_disabled/latest

Test location	/workspace/coverage/default/1.rv_timer_random_reset.604058577
Short name	T47
Test name
Test status
Simulation time	330415212 ps
CPU time	1.01 seconds
Started	Apr 16 12:19:17 PM PDT 24
Finished	Apr 16 12:19:18 PM PDT 24
Peak memory	190440 kb
Host	smart-3267f4a5-caa6-4206-8477-ab0fbb7c1848
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604058577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.604058577
Directory	/workspace/1.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/1.rv_timer_sec_cm.3737671478
Short name	T16
Test name
Test status
Simulation time	194546345 ps
CPU time	1 seconds
Started	Apr 16 12:27:08 PM PDT 24
Finished	Apr 16 12:27:15 PM PDT 24
Peak memory	215452 kb
Host	smart-95484249-df42-45c1-b8ec-a2183de60dc0
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737671478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3737671478
Directory	/workspace/1.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/1.rv_timer_stress_all.3679926018
Short name	T1
Test name
Test status
Simulation time	418882090625 ps
CPU time	371 seconds
Started	Apr 16 12:21:15 PM PDT 24
Finished	Apr 16 12:27:27 PM PDT 24
Peak memory	190280 kb
Host	smart-cd5d52d8-0cad-40c5-8ccd-4b517e716683
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679926018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 3679926018
Directory	/workspace/1.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2027898374
Short name	T147
Test name
Test status
Simulation time	7634221313 ps
CPU time	13.1 seconds
Started	Apr 16 12:27:09 PM PDT 24
Finished	Apr 16 12:27:27 PM PDT 24
Peak memory	182560 kb
Host	smart-f099a63e-74a2-4e69-ba97-f047d4d6a327
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027898374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.2027898374
Directory	/workspace/10.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/10.rv_timer_disabled.450541586
Short name	T446
Test name
Test status
Simulation time	62150469722 ps
CPU time	93.83 seconds
Started	Apr 16 12:27:12 PM PDT 24
Finished	Apr 16 12:28:51 PM PDT 24
Peak memory	182448 kb
Host	smart-44db21f9-2891-4a49-a848-78741e720f3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450541586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.450541586
Directory	/workspace/10.rv_timer_disabled/latest

Test location	/workspace/coverage/default/10.rv_timer_random.1427971221
Short name	T228
Test name
Test status
Simulation time	197953347352 ps
CPU time	462.57 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:35:07 PM PDT 24
Peak memory	182452 kb
Host	smart-eb8c49df-5db0-426e-9185-95d2bd2f769a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427971221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1427971221
Directory	/workspace/10.rv_timer_random/latest

Test location	/workspace/coverage/default/103.rv_timer_random.2302604680
Short name	T133
Test name
Test status
Simulation time	168006966530 ps
CPU time	62.03 seconds
Started	Apr 16 12:28:04 PM PDT 24
Finished	Apr 16 12:29:08 PM PDT 24
Peak memory	182380 kb
Host	smart-a7bee5d0-a665-4cdc-8ab9-ddf7261a4e1a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302604680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2302604680
Directory	/workspace/103.rv_timer_random/latest

Test location	/workspace/coverage/default/104.rv_timer_random.317082822
Short name	T96
Test name
Test status
Simulation time	520658859514 ps
CPU time	372.4 seconds
Started	Apr 16 12:28:11 PM PDT 24
Finished	Apr 16 12:34:25 PM PDT 24
Peak memory	190772 kb
Host	smart-1a94d20c-deda-4fab-b1aa-e81cd5575dd2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317082822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.317082822
Directory	/workspace/104.rv_timer_random/latest

Test location	/workspace/coverage/default/106.rv_timer_random.2730849119
Short name	T334
Test name
Test status
Simulation time	45424579559 ps
CPU time	926.32 seconds
Started	Apr 16 12:28:05 PM PDT 24
Finished	Apr 16 12:43:33 PM PDT 24
Peak memory	182556 kb
Host	smart-b88d0eda-1617-4c41-83b8-0c06b09d2fe2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730849119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2730849119
Directory	/workspace/106.rv_timer_random/latest

Test location	/workspace/coverage/default/108.rv_timer_random.3559665691
Short name	T185
Test name
Test status
Simulation time	185674943172 ps
CPU time	286.24 seconds
Started	Apr 16 12:28:03 PM PDT 24
Finished	Apr 16 12:32:51 PM PDT 24
Peak memory	190700 kb
Host	smart-29f66b95-70f5-47ae-8924-2ac3400d08b5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559665691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3559665691
Directory	/workspace/108.rv_timer_random/latest

Test location	/workspace/coverage/default/109.rv_timer_random.3559274702
Short name	T65
Test name
Test status
Simulation time	95042881024 ps
CPU time	172.74 seconds
Started	Apr 16 12:28:05 PM PDT 24
Finished	Apr 16 12:31:00 PM PDT 24
Peak memory	190756 kb
Host	smart-5aec8225-0221-4ac3-9866-61549530675b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559274702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3559274702
Directory	/workspace/109.rv_timer_random/latest

Test location	/workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2967998942
Short name	T269
Test name
Test status
Simulation time	321964730699 ps
CPU time	592.6 seconds
Started	Apr 16 12:27:17 PM PDT 24
Finished	Apr 16 12:37:15 PM PDT 24
Peak memory	182472 kb
Host	smart-c264332f-8847-4349-8328-9d01f7ce0112
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967998942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.2967998942
Directory	/workspace/11.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/11.rv_timer_disabled.658699504
Short name	T412
Test name
Test status
Simulation time	348853077946 ps
CPU time	157.82 seconds
Started	Apr 16 12:27:13 PM PDT 24
Finished	Apr 16 12:29:56 PM PDT 24
Peak memory	182508 kb
Host	smart-62adb0f7-ae35-40b5-912c-c6f576b63af5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=658699504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.658699504
Directory	/workspace/11.rv_timer_disabled/latest

Test location	/workspace/coverage/default/11.rv_timer_random_reset.3980292098
Short name	T347
Test name
Test status
Simulation time	111807013 ps
CPU time	1.41 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:27:25 PM PDT 24
Peak memory	182580 kb
Host	smart-2a964905-9397-4e94-9725-750e2babc9dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980292098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3980292098
Directory	/workspace/11.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3746437209
Short name	T15
Test name
Test status
Simulation time	59875237200 ps
CPU time	341.35 seconds
Started	Apr 16 12:27:11 PM PDT 24
Finished	Apr 16 12:32:57 PM PDT 24
Peak memory	197168 kb
Host	smart-20a97581-9b91-4027-9962-5f8c2bad2cce
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746437209 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3746437209
Directory	/workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/112.rv_timer_random.1335677380
Short name	T284
Test name
Test status
Simulation time	137547991041 ps
CPU time	2355.03 seconds
Started	Apr 16 12:28:11 PM PDT 24
Finished	Apr 16 01:07:29 PM PDT 24
Peak memory	190580 kb
Host	smart-45cff471-ad25-4bbf-bcec-7844ec876fdb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335677380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1335677380
Directory	/workspace/112.rv_timer_random/latest

Test location	/workspace/coverage/default/113.rv_timer_random.3264504202
Short name	T235
Test name
Test status
Simulation time	143842458953 ps
CPU time	359.35 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:34:04 PM PDT 24
Peak memory	190704 kb
Host	smart-ef890a77-b9a0-49fd-a638-d305b7795546
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264504202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3264504202
Directory	/workspace/113.rv_timer_random/latest

Test location	/workspace/coverage/default/114.rv_timer_random.30964593
Short name	T210
Test name
Test status
Simulation time	89736392693 ps
CPU time	143.2 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:30:28 PM PDT 24
Peak memory	190752 kb
Host	smart-031d371f-5a2e-494a-a404-d14967a4cb64
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30964593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.30964593
Directory	/workspace/114.rv_timer_random/latest

Test location	/workspace/coverage/default/117.rv_timer_random.1291284402
Short name	T285
Test name
Test status
Simulation time	32115320766 ps
CPU time	106.76 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:29:49 PM PDT 24
Peak memory	182580 kb
Host	smart-0c08bbf4-c0f3-4b5c-b8f3-c1d8972ebe96
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291284402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1291284402
Directory	/workspace/117.rv_timer_random/latest

Test location	/workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1474448768
Short name	T213
Test name
Test status
Simulation time	37026375343 ps
CPU time	67.54 seconds
Started	Apr 16 12:27:13 PM PDT 24
Finished	Apr 16 12:28:26 PM PDT 24
Peak memory	182472 kb
Host	smart-c69a2575-924b-43ca-a6c2-75d26bbc6f04
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474448768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1474448768
Directory	/workspace/12.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/12.rv_timer_disabled.3990659059
Short name	T351
Test name
Test status
Simulation time	137159655768 ps
CPU time	187.24 seconds
Started	Apr 16 12:27:12 PM PDT 24
Finished	Apr 16 12:30:25 PM PDT 24
Peak memory	182448 kb
Host	smart-22330158-bafd-4fd8-84c3-eb9084b11af8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990659059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3990659059
Directory	/workspace/12.rv_timer_disabled/latest

Test location	/workspace/coverage/default/12.rv_timer_random.633820035
Short name	T8
Test name
Test status
Simulation time	125442262649 ps
CPU time	192.89 seconds
Started	Apr 16 12:27:09 PM PDT 24
Finished	Apr 16 12:30:27 PM PDT 24
Peak memory	190556 kb
Host	smart-a071dd36-937c-46cd-9fc6-84b8b436f085
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633820035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.633820035
Directory	/workspace/12.rv_timer_random/latest

Test location	/workspace/coverage/default/12.rv_timer_random_reset.943667140
Short name	T197
Test name
Test status
Simulation time	209966560450 ps
CPU time	97.12 seconds
Started	Apr 16 12:27:10 PM PDT 24
Finished	Apr 16 12:28:53 PM PDT 24
Peak memory	190636 kb
Host	smart-3e84f265-98e4-4fd2-90fa-28a2a42ed8c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943667140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.943667140
Directory	/workspace/12.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/120.rv_timer_random.3434386292
Short name	T215
Test name
Test status
Simulation time	66881522027 ps
CPU time	63.29 seconds
Started	Apr 16 12:29:24 PM PDT 24
Finished	Apr 16 12:30:29 PM PDT 24
Peak memory	190308 kb
Host	smart-24971c23-3e62-4b78-ae93-ea3f6bfe9314
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434386292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3434386292
Directory	/workspace/120.rv_timer_random/latest

Test location	/workspace/coverage/default/121.rv_timer_random.690930063
Short name	T315
Test name
Test status
Simulation time	62057842160 ps
CPU time	107.44 seconds
Started	Apr 16 12:28:06 PM PDT 24
Finished	Apr 16 12:29:55 PM PDT 24
Peak memory	190696 kb
Host	smart-1c0352d9-e552-470e-be00-c7276067bbfc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690930063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.690930063
Directory	/workspace/121.rv_timer_random/latest

Test location	/workspace/coverage/default/122.rv_timer_random.3233432546
Short name	T9
Test name
Test status
Simulation time	70961818112 ps
CPU time	224.95 seconds
Started	Apr 16 12:29:16 PM PDT 24
Finished	Apr 16 12:33:03 PM PDT 24
Peak memory	189024 kb
Host	smart-aa29417d-2905-46e5-972e-367ae678b56b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233432546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3233432546
Directory	/workspace/122.rv_timer_random/latest

Test location	/workspace/coverage/default/124.rv_timer_random.392143169
Short name	T311
Test name
Test status
Simulation time	44171121012 ps
CPU time	99.28 seconds
Started	Apr 16 12:28:06 PM PDT 24
Finished	Apr 16 12:29:47 PM PDT 24
Peak memory	182580 kb
Host	smart-b4cc0140-9830-40df-8144-48495468586b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392143169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.392143169
Directory	/workspace/124.rv_timer_random/latest

Test location	/workspace/coverage/default/125.rv_timer_random.4291540325
Short name	T418
Test name
Test status
Simulation time	1414246833147 ps
CPU time	670.31 seconds
Started	Apr 16 12:28:13 PM PDT 24
Finished	Apr 16 12:39:25 PM PDT 24
Peak memory	190720 kb
Host	smart-e3514b41-8afa-4c26-ad6f-4493328e0400
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291540325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.4291540325
Directory	/workspace/125.rv_timer_random/latest

Test location	/workspace/coverage/default/126.rv_timer_random.634402360
Short name	T223
Test name
Test status
Simulation time	555306587322 ps
CPU time	620.04 seconds
Started	Apr 16 12:28:11 PM PDT 24
Finished	Apr 16 12:38:32 PM PDT 24
Peak memory	190692 kb
Host	smart-e16cc0c8-5e40-4d2b-bd6a-36f2d6d0e29f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634402360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.634402360
Directory	/workspace/126.rv_timer_random/latest

Test location	/workspace/coverage/default/128.rv_timer_random.1852412264
Short name	T261
Test name
Test status
Simulation time	121135805808 ps
CPU time	923 seconds
Started	Apr 16 12:28:09 PM PDT 24
Finished	Apr 16 12:43:34 PM PDT 24
Peak memory	190784 kb
Host	smart-ae1a3289-5895-440b-9e24-2fc3b7a1b18d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852412264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1852412264
Directory	/workspace/128.rv_timer_random/latest

Test location	/workspace/coverage/default/129.rv_timer_random.3169700930
Short name	T168
Test name
Test status
Simulation time	245710941639 ps
CPU time	596.57 seconds
Started	Apr 16 12:28:08 PM PDT 24
Finished	Apr 16 12:38:06 PM PDT 24
Peak memory	190656 kb
Host	smart-a12ccac8-a622-424e-9f5a-493c3a948473
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169700930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3169700930
Directory	/workspace/129.rv_timer_random/latest

Test location	/workspace/coverage/default/13.rv_timer_disabled.3051175779
Short name	T409
Test name
Test status
Simulation time	245494945432 ps
CPU time	165.4 seconds
Started	Apr 16 12:27:16 PM PDT 24
Finished	Apr 16 12:30:07 PM PDT 24
Peak memory	182508 kb
Host	smart-851b41c7-bd1a-48d8-8863-41db8798006b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051175779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3051175779
Directory	/workspace/13.rv_timer_disabled/latest

Test location	/workspace/coverage/default/13.rv_timer_random_reset.3535725556
Short name	T142
Test name
Test status
Simulation time	36248942920 ps
CPU time	415.47 seconds
Started	Apr 16 12:27:12 PM PDT 24
Finished	Apr 16 12:34:13 PM PDT 24
Peak memory	182376 kb
Host	smart-073e7af4-4816-45ff-b872-8bda6841d10b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535725556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3535725556
Directory	/workspace/13.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/131.rv_timer_random.2104580724
Short name	T425
Test name
Test status
Simulation time	480906564982 ps
CPU time	483.4 seconds
Started	Apr 16 12:28:08 PM PDT 24
Finished	Apr 16 12:36:14 PM PDT 24
Peak memory	190684 kb
Host	smart-38b686cd-1125-4523-a044-6c3bef7dce65
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104580724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2104580724
Directory	/workspace/131.rv_timer_random/latest

Test location	/workspace/coverage/default/132.rv_timer_random.1012018712
Short name	T175
Test name
Test status
Simulation time	34738252586 ps
CPU time	73.94 seconds
Started	Apr 16 12:28:08 PM PDT 24
Finished	Apr 16 12:29:24 PM PDT 24
Peak memory	182556 kb
Host	smart-4a0504e5-47af-4619-a4c6-c3d1c12bb619
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012018712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1012018712
Directory	/workspace/132.rv_timer_random/latest

Test location	/workspace/coverage/default/133.rv_timer_random.1448010118
Short name	T66
Test name
Test status
Simulation time	109445359033 ps
CPU time	97.03 seconds
Started	Apr 16 12:28:11 PM PDT 24
Finished	Apr 16 12:29:50 PM PDT 24
Peak memory	182552 kb
Host	smart-949331e6-6c0f-422d-a396-4a1404c5a6b0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448010118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1448010118
Directory	/workspace/133.rv_timer_random/latest

Test location	/workspace/coverage/default/134.rv_timer_random.2189789067
Short name	T167
Test name
Test status
Simulation time	66281563664 ps
CPU time	657.52 seconds
Started	Apr 16 12:28:12 PM PDT 24
Finished	Apr 16 12:39:13 PM PDT 24
Peak memory	190652 kb
Host	smart-2c715f00-18dd-4edc-9b39-fa9f521a45a0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189789067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2189789067
Directory	/workspace/134.rv_timer_random/latest

Test location	/workspace/coverage/default/135.rv_timer_random.4255632218
Short name	T389
Test name
Test status
Simulation time	15733973261 ps
CPU time	22.45 seconds
Started	Apr 16 12:28:10 PM PDT 24
Finished	Apr 16 12:28:34 PM PDT 24
Peak memory	182492 kb
Host	smart-4fe30783-da19-49d1-9efc-57876635e59c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255632218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4255632218
Directory	/workspace/135.rv_timer_random/latest

Test location	/workspace/coverage/default/136.rv_timer_random.2652275316
Short name	T115
Test name
Test status
Simulation time	1049800988856 ps
CPU time	849.72 seconds
Started	Apr 16 12:28:09 PM PDT 24
Finished	Apr 16 12:42:21 PM PDT 24
Peak memory	190624 kb
Host	smart-a711cb73-2e95-4257-bf9c-3c137fb58520
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652275316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2652275316
Directory	/workspace/136.rv_timer_random/latest

Test location	/workspace/coverage/default/14.rv_timer_disabled.4058255993
Short name	T402
Test name
Test status
Simulation time	107551733339 ps
CPU time	152.93 seconds
Started	Apr 16 12:27:12 PM PDT 24
Finished	Apr 16 12:29:50 PM PDT 24
Peak memory	182492 kb
Host	smart-e7563c44-48a1-47fa-954e-02237fab787a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058255993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4058255993
Directory	/workspace/14.rv_timer_disabled/latest

Test location	/workspace/coverage/default/14.rv_timer_random.3319969375
Short name	T263
Test name
Test status
Simulation time	55205039393 ps
CPU time	90.07 seconds
Started	Apr 16 12:27:10 PM PDT 24
Finished	Apr 16 12:28:46 PM PDT 24
Peak memory	191080 kb
Host	smart-b2802a3b-e8a9-46fb-b6cc-9533523d6898
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319969375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3319969375
Directory	/workspace/14.rv_timer_random/latest

Test location	/workspace/coverage/default/14.rv_timer_random_reset.528981338
Short name	T343
Test name
Test status
Simulation time	26362167870 ps
CPU time	73.58 seconds
Started	Apr 16 12:27:23 PM PDT 24
Finished	Apr 16 12:28:40 PM PDT 24
Peak memory	182560 kb
Host	smart-35568b81-c7b3-4beb-9d77-92bbf46df2a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528981338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.528981338
Directory	/workspace/14.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/140.rv_timer_random.2345848332
Short name	T344
Test name
Test status
Simulation time	177820505948 ps
CPU time	102.87 seconds
Started	Apr 16 12:28:10 PM PDT 24
Finished	Apr 16 12:29:54 PM PDT 24
Peak memory	190784 kb
Host	smart-0f7e5259-b5cc-4ee4-8a64-da226459bb93
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345848332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2345848332
Directory	/workspace/140.rv_timer_random/latest

Test location	/workspace/coverage/default/142.rv_timer_random.1609682148
Short name	T433
Test name
Test status
Simulation time	229117131897 ps
CPU time	66.78 seconds
Started	Apr 16 12:28:07 PM PDT 24
Finished	Apr 16 12:29:15 PM PDT 24
Peak memory	194304 kb
Host	smart-1bb232ab-7498-4fe2-af4c-0cfb0cc1d7c0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609682148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1609682148
Directory	/workspace/142.rv_timer_random/latest

Test location	/workspace/coverage/default/145.rv_timer_random.1845882885
Short name	T317
Test name
Test status
Simulation time	13949587430 ps
CPU time	24.35 seconds
Started	Apr 16 12:28:12 PM PDT 24
Finished	Apr 16 12:28:39 PM PDT 24
Peak memory	182232 kb
Host	smart-253c4ce1-30d7-440d-b8f0-45f31a99dd4a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845882885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1845882885
Directory	/workspace/145.rv_timer_random/latest

Test location	/workspace/coverage/default/148.rv_timer_random.1424458641
Short name	T216
Test name
Test status
Simulation time	106885439784 ps
CPU time	86.41 seconds
Started	Apr 16 12:28:15 PM PDT 24
Finished	Apr 16 12:29:44 PM PDT 24
Peak memory	190692 kb
Host	smart-8e9d3f4f-5606-4c35-bbb3-5345cd74b87e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424458641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1424458641
Directory	/workspace/148.rv_timer_random/latest

Test location	/workspace/coverage/default/149.rv_timer_random.2627023672
Short name	T375
Test name
Test status
Simulation time	135885104006 ps
CPU time	192.46 seconds
Started	Apr 16 12:28:14 PM PDT 24
Finished	Apr 16 12:31:30 PM PDT 24
Peak memory	190720 kb
Host	smart-51df50e3-b6e0-4e83-aa6c-bcd1f72bffd8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627023672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2627023672
Directory	/workspace/149.rv_timer_random/latest

Test location	/workspace/coverage/default/15.rv_timer_cfg_update_on_fly.708568427
Short name	T333
Test name
Test status
Simulation time	1374940358769 ps
CPU time	743.48 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:39:47 PM PDT 24
Peak memory	182572 kb
Host	smart-0657797a-e2eb-44af-bed5-bf3091591882
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708568427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.rv_timer_cfg_update_on_fly.708568427
Directory	/workspace/15.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/15.rv_timer_disabled.4177666227
Short name	T368
Test name
Test status
Simulation time	340990727653 ps
CPU time	258.63 seconds
Started	Apr 16 12:27:14 PM PDT 24
Finished	Apr 16 12:31:38 PM PDT 24
Peak memory	182476 kb
Host	smart-99ab3e70-1ceb-4e19-83e6-8d523a1fa5d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177666227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.4177666227
Directory	/workspace/15.rv_timer_disabled/latest

Test location	/workspace/coverage/default/15.rv_timer_random.4172195695
Short name	T292
Test name
Test status
Simulation time	387852548953 ps
CPU time	564.69 seconds
Started	Apr 16 12:27:18 PM PDT 24
Finished	Apr 16 12:36:48 PM PDT 24
Peak memory	190708 kb
Host	smart-6a3a9efc-871e-4099-8c7e-b32356e3d05d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172195695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4172195695
Directory	/workspace/15.rv_timer_random/latest

Test location	/workspace/coverage/default/15.rv_timer_random_reset.2975109049
Short name	T276
Test name
Test status
Simulation time	18615109472 ps
CPU time	41.35 seconds
Started	Apr 16 12:27:23 PM PDT 24
Finished	Apr 16 12:28:08 PM PDT 24
Peak memory	194292 kb
Host	smart-5efbce13-8602-4a54-963a-bc742a4162e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2975109049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2975109049
Directory	/workspace/15.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/15.rv_timer_stress_all.1660986836
Short name	T179
Test name
Test status
Simulation time	2923642694229 ps
CPU time	1477.14 seconds
Started	Apr 16 12:27:15 PM PDT 24
Finished	Apr 16 12:51:57 PM PDT 24
Peak memory	194768 kb
Host	smart-cc827448-7078-4e19-a93a-ba22ce170f95
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660986836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .1660986836
Directory	/workspace/15.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/152.rv_timer_random.594336529
Short name	T272
Test name
Test status
Simulation time	40845988091 ps
CPU time	229.72 seconds
Started	Apr 16 12:28:15 PM PDT 24
Finished	Apr 16 12:32:07 PM PDT 24
Peak memory	190772 kb
Host	smart-181ce240-76f9-41cc-9b1a-e5d508f949fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594336529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.594336529
Directory	/workspace/152.rv_timer_random/latest

Test location	/workspace/coverage/default/153.rv_timer_random.4108420644
Short name	T324
Test name
Test status
Simulation time	1722231600607 ps
CPU time	1356.69 seconds
Started	Apr 16 12:28:16 PM PDT 24
Finished	Apr 16 12:50:56 PM PDT 24
Peak memory	190664 kb
Host	smart-54211cd3-1d47-41d9-b1ac-1cd9be8bdde8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108420644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4108420644
Directory	/workspace/153.rv_timer_random/latest

Test location	/workspace/coverage/default/154.rv_timer_random.2308810441
Short name	T105
Test name
Test status
Simulation time	598278110390 ps
CPU time	639.78 seconds
Started	Apr 16 12:28:16 PM PDT 24
Finished	Apr 16 12:38:58 PM PDT 24
Peak memory	190652 kb
Host	smart-07972af6-ec9a-4052-95ff-27b3ba3096f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308810441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2308810441
Directory	/workspace/154.rv_timer_random/latest

Test location	/workspace/coverage/default/156.rv_timer_random.4121209593
Short name	T190
Test name
Test status
Simulation time	97408607705 ps
CPU time	179.64 seconds
Started	Apr 16 12:28:15 PM PDT 24
Finished	Apr 16 12:31:17 PM PDT 24
Peak memory	190756 kb
Host	smart-6675f9ce-c1d6-4402-836a-85c71c2393cf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121209593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.4121209593
Directory	/workspace/156.rv_timer_random/latest

Test location	/workspace/coverage/default/157.rv_timer_random.2098687416
Short name	T225
Test name
Test status
Simulation time	378446786570 ps
CPU time	856.78 seconds
Started	Apr 16 12:28:15 PM PDT 24
Finished	Apr 16 12:42:35 PM PDT 24
Peak memory	190624 kb
Host	smart-f0c30f26-6ce7-4004-9eb9-76da9f461a22
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098687416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2098687416
Directory	/workspace/157.rv_timer_random/latest

Test location	/workspace/coverage/default/158.rv_timer_random.1742031922
Short name	T12
Test name
Test status
Simulation time	173589303338 ps
CPU time	263.93 seconds
Started	Apr 16 12:28:15 PM PDT 24
Finished	Apr 16 12:32:42 PM PDT 24
Peak memory	190716 kb
Host	smart-2128dd6a-53b9-4603-a6f1-930e7ba6e049
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742031922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1742031922
Directory	/workspace/158.rv_timer_random/latest

Test location	/workspace/coverage/default/159.rv_timer_random.1907705640
Short name	T188
Test name
Test status
Simulation time	433841935878 ps
CPU time	187.16 seconds
Started	Apr 16 12:28:16 PM PDT 24
Finished	Apr 16 12:31:26 PM PDT 24
Peak memory	190660 kb
Host	smart-2374949a-5bf1-4bd1-ad7f-abbeca166c2e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907705640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1907705640
Directory	/workspace/159.rv_timer_random/latest

Test location	/workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2429198334
Short name	T67
Test name
Test status
Simulation time	37451819194 ps
CPU time	66.78 seconds
Started	Apr 16 12:27:16 PM PDT 24
Finished	Apr 16 12:28:28 PM PDT 24
Peak memory	182480 kb
Host	smart-3457639b-bed8-4cc0-865b-c4c7ee87939d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429198334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.2429198334
Directory	/workspace/16.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/16.rv_timer_disabled.3406113546
Short name	T348
Test name
Test status
Simulation time	110872945315 ps
CPU time	93.7 seconds
Started	Apr 16 12:27:16 PM PDT 24
Finished	Apr 16 12:28:55 PM PDT 24
Peak memory	182448 kb
Host	smart-5fd6dbdc-62e5-40bc-abac-b80aa0b7f769
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3406113546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3406113546
Directory	/workspace/16.rv_timer_disabled/latest

Test location	/workspace/coverage/default/16.rv_timer_random.3162630985
Short name	T95
Test name
Test status
Simulation time	141857833289 ps
CPU time	362.62 seconds
Started	Apr 16 12:27:35 PM PDT 24
Finished	Apr 16 12:33:41 PM PDT 24
Peak memory	190852 kb
Host	smart-1db3f706-4596-4948-aeec-145614016b2c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162630985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3162630985
Directory	/workspace/16.rv_timer_random/latest

Test location	/workspace/coverage/default/16.rv_timer_random_reset.899401154
Short name	T441
Test name
Test status
Simulation time	184182370 ps
CPU time	0.77 seconds
Started	Apr 16 12:27:13 PM PDT 24
Finished	Apr 16 12:27:19 PM PDT 24
Peak memory	182284 kb
Host	smart-a2f22767-b300-41af-bbfb-de8d32851cb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899401154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.899401154
Directory	/workspace/16.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/160.rv_timer_random.3529195993
Short name	T2
Test name
Test status
Simulation time	141203102908 ps
CPU time	249.15 seconds
Started	Apr 16 12:28:16 PM PDT 24
Finished	Apr 16 12:32:28 PM PDT 24
Peak memory	190788 kb
Host	smart-63009662-9607-45d4-9075-0f3cd5ce9689
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529195993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3529195993
Directory	/workspace/160.rv_timer_random/latest

Test location	/workspace/coverage/default/161.rv_timer_random.4153034253
Short name	T289
Test name
Test status
Simulation time	152274268440 ps
CPU time	272.17 seconds
Started	Apr 16 12:28:16 PM PDT 24
Finished	Apr 16 12:32:50 PM PDT 24
Peak memory	190784 kb
Host	smart-9ffe5833-9483-42be-8d5d-bd4605781f73
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153034253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4153034253
Directory	/workspace/161.rv_timer_random/latest

Test location	/workspace/coverage/default/162.rv_timer_random.3228733734
Short name	T164
Test name
Test status
Simulation time	92839023882 ps
CPU time	498.22 seconds
Started	Apr 16 12:28:16 PM PDT 24
Finished	Apr 16 12:36:37 PM PDT 24
Peak memory	191080 kb
Host	smart-a62c8d0c-29fa-4bc2-b74e-193ea8fd2a2b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228733734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3228733734
Directory	/workspace/162.rv_timer_random/latest

Test location	/workspace/coverage/default/163.rv_timer_random.2624637607
Short name	T123
Test name
Test status
Simulation time	125878144531 ps
CPU time	84.62 seconds
Started	Apr 16 12:28:15 PM PDT 24
Finished	Apr 16 12:29:43 PM PDT 24
Peak memory	182468 kb
Host	smart-cd9344f3-7943-4d86-b82e-2c5fcc33ee0e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624637607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2624637607
Directory	/workspace/163.rv_timer_random/latest

Test location	/workspace/coverage/default/164.rv_timer_random.125343798
Short name	T130
Test name
Test status
Simulation time	45581843878 ps
CPU time	38.64 seconds
Started	Apr 16 12:28:16 PM PDT 24
Finished	Apr 16 12:28:57 PM PDT 24
Peak memory	182524 kb
Host	smart-c9a7953a-23eb-4fa7-a178-8b74c63604a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125343798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.125343798
Directory	/workspace/164.rv_timer_random/latest

Test location	/workspace/coverage/default/166.rv_timer_random.3430476824
Short name	T119
Test name
Test status
Simulation time	97429282410 ps
CPU time	266.18 seconds
Started	Apr 16 12:28:21 PM PDT 24
Finished	Apr 16 12:32:48 PM PDT 24
Peak memory	182496 kb
Host	smart-26cc1e9a-31d6-4129-a2f3-b68d6ebe288f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430476824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3430476824
Directory	/workspace/166.rv_timer_random/latest

Test location	/workspace/coverage/default/167.rv_timer_random.2230832753
Short name	T438
Test name
Test status
Simulation time	14606047001 ps
CPU time	21.56 seconds
Started	Apr 16 12:28:24 PM PDT 24
Finished	Apr 16 12:28:46 PM PDT 24
Peak memory	181940 kb
Host	smart-d78f9c9b-00a2-4a5a-89ad-9a911d4a7b83
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230832753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2230832753
Directory	/workspace/167.rv_timer_random/latest

Test location	/workspace/coverage/default/168.rv_timer_random.2075241102
Short name	T319
Test name
Test status
Simulation time	343532253043 ps
CPU time	280.88 seconds
Started	Apr 16 12:28:20 PM PDT 24
Finished	Apr 16 12:33:03 PM PDT 24
Peak memory	190664 kb
Host	smart-e3886160-ee3d-4922-9b78-76a4e094781e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075241102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2075241102
Directory	/workspace/168.rv_timer_random/latest

Test location	/workspace/coverage/default/169.rv_timer_random.2578728922
Short name	T260
Test name
Test status
Simulation time	77442015172 ps
CPU time	118.59 seconds
Started	Apr 16 12:28:24 PM PDT 24
Finished	Apr 16 12:30:23 PM PDT 24
Peak memory	190224 kb
Host	smart-8e8e1054-a55d-4e5e-9b66-8d22cd887eb6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578728922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2578728922
Directory	/workspace/169.rv_timer_random/latest

Test location	/workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3436623773
Short name	T3
Test name
Test status
Simulation time	960433970490 ps
CPU time	550.28 seconds
Started	Apr 16 12:27:18 PM PDT 24
Finished	Apr 16 12:36:34 PM PDT 24
Peak memory	182480 kb
Host	smart-ad112f2d-1cce-41a4-a5dd-1977524c7d3f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436623773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.3436623773
Directory	/workspace/17.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/17.rv_timer_disabled.3923281932
Short name	T386
Test name
Test status
Simulation time	27405091075 ps
CPU time	37.64 seconds
Started	Apr 16 12:27:21 PM PDT 24
Finished	Apr 16 12:28:03 PM PDT 24
Peak memory	182552 kb
Host	smart-8a498903-84e0-46d6-91a7-949f8e8c92f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3923281932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3923281932
Directory	/workspace/17.rv_timer_disabled/latest

Test location	/workspace/coverage/default/17.rv_timer_random_reset.796937522
Short name	T296
Test name
Test status
Simulation time	144017740107 ps
CPU time	143.62 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:29:48 PM PDT 24
Peak memory	190732 kb
Host	smart-8e0988cf-ab85-49c7-8a9a-f4f091817acb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796937522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.796937522
Directory	/workspace/17.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/170.rv_timer_random.599170390
Short name	T202
Test name
Test status
Simulation time	79662692518 ps
CPU time	586.49 seconds
Started	Apr 16 12:28:21 PM PDT 24
Finished	Apr 16 12:38:09 PM PDT 24
Peak memory	190772 kb
Host	smart-d4980623-7d74-464d-ae07-1ab70e296eb1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599170390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.599170390
Directory	/workspace/170.rv_timer_random/latest

Test location	/workspace/coverage/default/171.rv_timer_random.3926837234
Short name	T452
Test name
Test status
Simulation time	82483152722 ps
CPU time	90.28 seconds
Started	Apr 16 12:28:20 PM PDT 24
Finished	Apr 16 12:29:52 PM PDT 24
Peak memory	190540 kb
Host	smart-08e7bcc3-3d94-49a8-ad49-f71457ee63ad
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926837234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3926837234
Directory	/workspace/171.rv_timer_random/latest

Test location	/workspace/coverage/default/172.rv_timer_random.988279554
Short name	T131
Test name
Test status
Simulation time	364509567315 ps
CPU time	199.29 seconds
Started	Apr 16 12:28:21 PM PDT 24
Finished	Apr 16 12:31:42 PM PDT 24
Peak memory	190620 kb
Host	smart-6ffb325b-e329-47f7-8af6-b1f45c2061e4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988279554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.988279554
Directory	/workspace/172.rv_timer_random/latest

Test location	/workspace/coverage/default/174.rv_timer_random.896156613
Short name	T127
Test name
Test status
Simulation time	241892088878 ps
CPU time	182.98 seconds
Started	Apr 16 12:28:24 PM PDT 24
Finished	Apr 16 12:31:28 PM PDT 24
Peak memory	193452 kb
Host	smart-67c61d3a-4a26-497b-b3e7-15ec3a88114b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896156613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.896156613
Directory	/workspace/174.rv_timer_random/latest

Test location	/workspace/coverage/default/175.rv_timer_random.1739399285
Short name	T128
Test name
Test status
Simulation time	172510338064 ps
CPU time	705.62 seconds
Started	Apr 16 12:28:21 PM PDT 24
Finished	Apr 16 12:40:08 PM PDT 24
Peak memory	190652 kb
Host	smart-e15b2109-240e-4743-ac51-d74b766bfbac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739399285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1739399285
Directory	/workspace/175.rv_timer_random/latest

Test location	/workspace/coverage/default/176.rv_timer_random.587089417
Short name	T447
Test name
Test status
Simulation time	39913625047 ps
CPU time	24.2 seconds
Started	Apr 16 12:28:19 PM PDT 24
Finished	Apr 16 12:28:45 PM PDT 24
Peak memory	182476 kb
Host	smart-6a25b179-d483-40b4-92be-f18a22e4dc60
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587089417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.587089417
Directory	/workspace/176.rv_timer_random/latest

Test location	/workspace/coverage/default/178.rv_timer_random.3602817583
Short name	T177
Test name
Test status
Simulation time	692544553263 ps
CPU time	481.21 seconds
Started	Apr 16 12:28:21 PM PDT 24
Finished	Apr 16 12:36:23 PM PDT 24
Peak memory	190692 kb
Host	smart-999de89d-9045-4994-865a-233b8391f7f8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602817583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3602817583
Directory	/workspace/178.rv_timer_random/latest

Test location	/workspace/coverage/default/179.rv_timer_random.1187025363
Short name	T288
Test name
Test status
Simulation time	178212178020 ps
CPU time	471.84 seconds
Started	Apr 16 12:28:20 PM PDT 24
Finished	Apr 16 12:36:13 PM PDT 24
Peak memory	190676 kb
Host	smart-885150b7-4558-4aaa-bf1c-93a54b71dadd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187025363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1187025363
Directory	/workspace/179.rv_timer_random/latest

Test location	/workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3796697291
Short name	T116
Test name
Test status
Simulation time	3996033413 ps
CPU time	7.82 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:27:33 PM PDT 24
Peak memory	182484 kb
Host	smart-92f1fe57-8f46-42d9-8c5a-8e91efb5213f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796697291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3796697291
Directory	/workspace/18.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/18.rv_timer_disabled.365202492
Short name	T394
Test name
Test status
Simulation time	425079065129 ps
CPU time	112.63 seconds
Started	Apr 16 12:27:29 PM PDT 24
Finished	Apr 16 12:29:24 PM PDT 24
Peak memory	182556 kb
Host	smart-a809b2f3-5b6b-44e3-84fb-424b2349a034
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365202492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.365202492
Directory	/workspace/18.rv_timer_disabled/latest

Test location	/workspace/coverage/default/18.rv_timer_random.4035783839
Short name	T64
Test name
Test status
Simulation time	273720359956 ps
CPU time	360.51 seconds
Started	Apr 16 12:27:18 PM PDT 24
Finished	Apr 16 12:33:24 PM PDT 24
Peak memory	190796 kb
Host	smart-8df524e2-2090-450d-8ec1-1009d40c2da4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035783839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4035783839
Directory	/workspace/18.rv_timer_random/latest

Test location	/workspace/coverage/default/18.rv_timer_random_reset.4020597243
Short name	T424
Test name
Test status
Simulation time	6002082903 ps
CPU time	10.01 seconds
Started	Apr 16 12:27:17 PM PDT 24
Finished	Apr 16 12:27:32 PM PDT 24
Peak memory	190640 kb
Host	smart-413667f7-aece-4d4d-b75d-90c925ea51bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020597243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4020597243
Directory	/workspace/18.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/18.rv_timer_stress_all.2691091073
Short name	T313
Test name
Test status
Simulation time	95313620299 ps
CPU time	418.27 seconds
Started	Apr 16 12:27:44 PM PDT 24
Finished	Apr 16 12:34:44 PM PDT 24
Peak memory	194288 kb
Host	smart-2e2b95d3-036c-4c78-8cb6-18d43563441a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691091073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all .2691091073
Directory	/workspace/18.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/181.rv_timer_random.2329128105
Short name	T209
Test name
Test status
Simulation time	59506360897 ps
CPU time	44.4 seconds
Started	Apr 16 12:28:25 PM PDT 24
Finished	Apr 16 12:29:11 PM PDT 24
Peak memory	182608 kb
Host	smart-5261aee0-179f-4bd6-b5d4-8cdfc1882132
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329128105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2329128105
Directory	/workspace/181.rv_timer_random/latest

Test location	/workspace/coverage/default/182.rv_timer_random.402258403
Short name	T92
Test name
Test status
Simulation time	404251733280 ps
CPU time	404.55 seconds
Started	Apr 16 12:28:26 PM PDT 24
Finished	Apr 16 12:35:13 PM PDT 24
Peak memory	190852 kb
Host	smart-699b1a4f-456f-431c-aeff-00f29d615e13
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402258403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.402258403
Directory	/workspace/182.rv_timer_random/latest

Test location	/workspace/coverage/default/183.rv_timer_random.1701095840
Short name	T137
Test name
Test status
Simulation time	84656144068 ps
CPU time	345.3 seconds
Started	Apr 16 12:28:26 PM PDT 24
Finished	Apr 16 12:34:13 PM PDT 24
Peak memory	190660 kb
Host	smart-0febd444-3433-4907-8412-079d7f0593f3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701095840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1701095840
Directory	/workspace/183.rv_timer_random/latest

Test location	/workspace/coverage/default/185.rv_timer_random.3169687393
Short name	T157
Test name
Test status
Simulation time	297139053066 ps
CPU time	1182.33 seconds
Started	Apr 16 12:28:25 PM PDT 24
Finished	Apr 16 12:48:09 PM PDT 24
Peak memory	190572 kb
Host	smart-87898602-3e89-4c3a-9c43-70e9ba5ff395
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169687393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3169687393
Directory	/workspace/185.rv_timer_random/latest

Test location	/workspace/coverage/default/186.rv_timer_random.2070573056
Short name	T413
Test name
Test status
Simulation time	125507739052 ps
CPU time	478.37 seconds
Started	Apr 16 12:28:27 PM PDT 24
Finished	Apr 16 12:36:27 PM PDT 24
Peak memory	190776 kb
Host	smart-4a3cc830-e6d3-4b32-9218-fc2988a01346
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070573056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2070573056
Directory	/workspace/186.rv_timer_random/latest

Test location	/workspace/coverage/default/187.rv_timer_random.5703312
Short name	T309
Test name
Test status
Simulation time	64284293747 ps
CPU time	98.66 seconds
Started	Apr 16 12:28:25 PM PDT 24
Finished	Apr 16 12:30:05 PM PDT 24
Peak memory	190764 kb
Host	smart-064c07ca-28b8-4d59-9a89-ab641a036bb4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5703312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.5703312
Directory	/workspace/187.rv_timer_random/latest

Test location	/workspace/coverage/default/189.rv_timer_random.3998081571
Short name	T329
Test name
Test status
Simulation time	9228085720 ps
CPU time	18.89 seconds
Started	Apr 16 12:28:26 PM PDT 24
Finished	Apr 16 12:28:46 PM PDT 24
Peak memory	182536 kb
Host	smart-d9411072-4c6b-4a63-b240-36d505917d75
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998081571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3998081571
Directory	/workspace/189.rv_timer_random/latest

Test location	/workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2397275362
Short name	T214
Test name
Test status
Simulation time	318043389486 ps
CPU time	185.93 seconds
Started	Apr 16 12:27:15 PM PDT 24
Finished	Apr 16 12:30:26 PM PDT 24
Peak memory	182532 kb
Host	smart-7e662e54-76fd-4982-8576-b66cea2677fb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397275362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.2397275362
Directory	/workspace/19.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/19.rv_timer_disabled.709123186
Short name	T426
Test name
Test status
Simulation time	421929283213 ps
CPU time	108.82 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:29:14 PM PDT 24
Peak memory	182492 kb
Host	smart-e7a61408-04aa-49d1-8165-5ed7714b27c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=709123186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.709123186
Directory	/workspace/19.rv_timer_disabled/latest

Test location	/workspace/coverage/default/19.rv_timer_random_reset.1020410210
Short name	T404
Test name
Test status
Simulation time	302636291941 ps
CPU time	454.6 seconds
Started	Apr 16 12:27:21 PM PDT 24
Finished	Apr 16 12:35:00 PM PDT 24
Peak memory	193840 kb
Host	smart-1ca1df9b-5d27-4451-b2de-f814dece81ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020410210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1020410210
Directory	/workspace/19.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/19.rv_timer_stress_all.885210150
Short name	T183
Test name
Test status
Simulation time	953828620116 ps
CPU time	6552.31 seconds
Started	Apr 16 12:27:29 PM PDT 24
Finished	Apr 16 02:16:45 PM PDT 24
Peak memory	190580 kb
Host	smart-0360d2ec-249c-482e-8e76-76a2743d6258
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885210150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all. 885210150
Directory	/workspace/19.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.529300841
Short name	T37
Test name
Test status
Simulation time	132917991391 ps
CPU time	456.38 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:35:00 PM PDT 24
Peak memory	205428 kb
Host	smart-569c6952-e1ec-405f-85f9-1e93196009a4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529300841 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.529300841
Directory	/workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/190.rv_timer_random.3058225860
Short name	T250
Test name
Test status
Simulation time	1323826116908 ps
CPU time	965.67 seconds
Started	Apr 16 12:28:26 PM PDT 24
Finished	Apr 16 12:44:33 PM PDT 24
Peak memory	190608 kb
Host	smart-3783c1f6-14e2-40da-b11d-27c7a123ad2c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058225860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3058225860
Directory	/workspace/190.rv_timer_random/latest

Test location	/workspace/coverage/default/191.rv_timer_random.572528191
Short name	T420
Test name
Test status
Simulation time	143201053748 ps
CPU time	84.43 seconds
Started	Apr 16 12:28:26 PM PDT 24
Finished	Apr 16 12:29:52 PM PDT 24
Peak memory	182588 kb
Host	smart-3dc51c4d-9454-496a-8139-a68898a6f041
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572528191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.572528191
Directory	/workspace/191.rv_timer_random/latest

Test location	/workspace/coverage/default/192.rv_timer_random.3238718980
Short name	T217
Test name
Test status
Simulation time	179489779738 ps
CPU time	170.98 seconds
Started	Apr 16 12:28:26 PM PDT 24
Finished	Apr 16 12:31:19 PM PDT 24
Peak memory	194284 kb
Host	smart-49221a27-5539-4625-b7ed-7ce423f5fc0b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238718980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3238718980
Directory	/workspace/192.rv_timer_random/latest

Test location	/workspace/coverage/default/195.rv_timer_random.3093992440
Short name	T234
Test name
Test status
Simulation time	192328340923 ps
CPU time	879.3 seconds
Started	Apr 16 12:28:33 PM PDT 24
Finished	Apr 16 12:43:13 PM PDT 24
Peak memory	190776 kb
Host	smart-31c367d7-9638-4670-8923-4fa6a6507eea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093992440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3093992440
Directory	/workspace/195.rv_timer_random/latest

Test location	/workspace/coverage/default/198.rv_timer_random.1068094236
Short name	T245
Test name
Test status
Simulation time	81235791431 ps
CPU time	451.34 seconds
Started	Apr 16 12:28:32 PM PDT 24
Finished	Apr 16 12:36:04 PM PDT 24
Peak memory	190548 kb
Host	smart-81895afc-eb98-4dfe-a866-c8f840d47874
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068094236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1068094236
Directory	/workspace/198.rv_timer_random/latest

Test location	/workspace/coverage/default/199.rv_timer_random.3131318119
Short name	T195
Test name
Test status
Simulation time	163974217595 ps
CPU time	97.01 seconds
Started	Apr 16 12:28:36 PM PDT 24
Finished	Apr 16 12:30:14 PM PDT 24
Peak memory	193904 kb
Host	smart-92c8e958-a460-41d3-87c4-101654da8358
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131318119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3131318119
Directory	/workspace/199.rv_timer_random/latest

Test location	/workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1670552867
Short name	T155
Test name
Test status
Simulation time	579452573326 ps
CPU time	567.84 seconds
Started	Apr 16 12:20:36 PM PDT 24
Finished	Apr 16 12:30:04 PM PDT 24
Peak memory	182588 kb
Host	smart-48a713de-96a5-4990-86bf-27e3a211e012
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670552867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.1670552867
Directory	/workspace/2.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/2.rv_timer_disabled.2452097095
Short name	T90
Test name
Test status
Simulation time	101211395640 ps
CPU time	155.11 seconds
Started	Apr 16 12:27:06 PM PDT 24
Finished	Apr 16 12:29:47 PM PDT 24
Peak memory	182492 kb
Host	smart-63807108-d066-4f63-8d7a-a5e698578ac1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452097095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2452097095
Directory	/workspace/2.rv_timer_disabled/latest

Test location	/workspace/coverage/default/2.rv_timer_random.2648339273
Short name	T222
Test name
Test status
Simulation time	257591269163 ps
CPU time	237.61 seconds
Started	Apr 16 12:22:59 PM PDT 24
Finished	Apr 16 12:27:00 PM PDT 24
Peak memory	188492 kb
Host	smart-1f50e8da-3bce-4921-9f5b-481670d24cb8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648339273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2648339273
Directory	/workspace/2.rv_timer_random/latest

Test location	/workspace/coverage/default/2.rv_timer_random_reset.1598732079
Short name	T442
Test name
Test status
Simulation time	98933839 ps
CPU time	0.52 seconds
Started	Apr 16 12:27:05 PM PDT 24
Finished	Apr 16 12:27:11 PM PDT 24
Peak memory	182292 kb
Host	smart-eb20cb9e-4ec9-4170-be04-f299dd6816cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598732079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1598732079
Directory	/workspace/2.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/2.rv_timer_sec_cm.1282291979
Short name	T17
Test name
Test status
Simulation time	41578424 ps
CPU time	0.75 seconds
Started	Apr 16 12:27:05 PM PDT 24
Finished	Apr 16 12:27:11 PM PDT 24
Peak memory	212944 kb
Host	smart-32ad620e-6da5-4be5-a509-88f0c3f81450
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282291979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1282291979
Directory	/workspace/2.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/2.rv_timer_stress_all.3908787509
Short name	T136
Test name
Test status
Simulation time	290951831165 ps
CPU time	1968.89 seconds
Started	Apr 16 12:27:03 PM PDT 24
Finished	Apr 16 12:59:57 PM PDT 24
Peak memory	190568 kb
Host	smart-00c47e1c-dd01-4cf4-a1df-5214b1037374
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908787509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 3908787509
Directory	/workspace/2.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2803689600
Short name	T230
Test name
Test status
Simulation time	1168025728469 ps
CPU time	1177.05 seconds
Started	Apr 16 12:27:22 PM PDT 24
Finished	Apr 16 12:47:03 PM PDT 24
Peak memory	182472 kb
Host	smart-e6d8ebd7-bb73-4ee0-adfb-036ad6322a80
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803689600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2803689600
Directory	/workspace/20.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/20.rv_timer_disabled.2083844700
Short name	T391
Test name
Test status
Simulation time	39476618648 ps
CPU time	29.99 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:27:55 PM PDT 24
Peak memory	182436 kb
Host	smart-8344f6be-3890-4b5c-b790-4e358dc8abc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083844700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2083844700
Directory	/workspace/20.rv_timer_disabled/latest

Test location	/workspace/coverage/default/20.rv_timer_random.848480363
Short name	T152
Test name
Test status
Simulation time	353674064767 ps
CPU time	311.44 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:32:36 PM PDT 24
Peak memory	190760 kb
Host	smart-2db7e0c0-2d16-4aea-9151-6fc6487895ea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848480363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.848480363
Directory	/workspace/20.rv_timer_random/latest

Test location	/workspace/coverage/default/20.rv_timer_random_reset.3457917156
Short name	T242
Test name
Test status
Simulation time	130912121255 ps
CPU time	276.16 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:32:00 PM PDT 24
Peak memory	190772 kb
Host	smart-d983b521-e01d-46c3-a5b6-118cf1d3710d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457917156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3457917156
Directory	/workspace/20.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/20.rv_timer_stress_all.3716849313
Short name	T444
Test name
Test status
Simulation time	168641975679 ps
CPU time	51.06 seconds
Started	Apr 16 12:27:22 PM PDT 24
Finished	Apr 16 12:28:17 PM PDT 24
Peak memory	182572 kb
Host	smart-d1543d92-7b03-47b3-8bfd-f655119e7f3a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716849313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all .3716849313
Directory	/workspace/20.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/21.rv_timer_cfg_update_on_fly.4058469678
Short name	T135
Test name
Test status
Simulation time	524458542018 ps
CPU time	276.52 seconds
Started	Apr 16 12:27:22 PM PDT 24
Finished	Apr 16 12:32:02 PM PDT 24
Peak memory	182580 kb
Host	smart-3ab0a58c-66c8-4426-9231-7588663c23f5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058469678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.4058469678
Directory	/workspace/21.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/21.rv_timer_disabled.1787443367
Short name	T416
Test name
Test status
Simulation time	48871161794 ps
CPU time	68.52 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:28:33 PM PDT 24
Peak memory	182496 kb
Host	smart-1b79458b-5814-4260-8aae-8947fbb6b9ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787443367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1787443367
Directory	/workspace/21.rv_timer_disabled/latest

Test location	/workspace/coverage/default/21.rv_timer_random.2731138162
Short name	T163
Test name
Test status
Simulation time	119262796443 ps
CPU time	143.08 seconds
Started	Apr 16 12:27:21 PM PDT 24
Finished	Apr 16 12:29:48 PM PDT 24
Peak memory	190740 kb
Host	smart-e8911c09-1e41-4525-a198-86977335599a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731138162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2731138162
Directory	/workspace/21.rv_timer_random/latest

Test location	/workspace/coverage/default/21.rv_timer_random_reset.2705176058
Short name	T23
Test name
Test status
Simulation time	22229148317 ps
CPU time	37.92 seconds
Started	Apr 16 12:27:22 PM PDT 24
Finished	Apr 16 12:28:04 PM PDT 24
Peak memory	190740 kb
Host	smart-0d2a2a87-4642-4869-a8b6-3baefe559a48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705176058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2705176058
Directory	/workspace/21.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/21.rv_timer_stress_all.3182400028
Short name	T448
Test name
Test status
Simulation time	4843357883325 ps
CPU time	785.21 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:40:30 PM PDT 24
Peak memory	195140 kb
Host	smart-480df1be-139f-4034-a4b0-40ae589b2c2d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182400028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all .3182400028
Directory	/workspace/21.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/22.rv_timer_cfg_update_on_fly.187332823
Short name	T331
Test name
Test status
Simulation time	41162431554 ps
CPU time	23.77 seconds
Started	Apr 16 12:27:25 PM PDT 24
Finished	Apr 16 12:27:52 PM PDT 24
Peak memory	182464 kb
Host	smart-3a225b6e-b9cd-4ef5-bdbe-37f48dfe458d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187332823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.rv_timer_cfg_update_on_fly.187332823
Directory	/workspace/22.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/22.rv_timer_disabled.105587946
Short name	T365
Test name
Test status
Simulation time	25343926089 ps
CPU time	39.83 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:28:04 PM PDT 24
Peak memory	182408 kb
Host	smart-6c891157-a7d7-4519-b03b-a940a67b9276
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105587946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.105587946
Directory	/workspace/22.rv_timer_disabled/latest

Test location	/workspace/coverage/default/22.rv_timer_random.916424113
Short name	T443
Test name
Test status
Simulation time	187768769620 ps
CPU time	74.2 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:29:08 PM PDT 24
Peak memory	194368 kb
Host	smart-ea2f285f-7b78-4b04-a918-6f56a453aac8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916424113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.916424113
Directory	/workspace/22.rv_timer_random/latest

Test location	/workspace/coverage/default/22.rv_timer_random_reset.604160690
Short name	T26
Test name
Test status
Simulation time	609133609565 ps
CPU time	1707.42 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:55:52 PM PDT 24
Peak memory	191088 kb
Host	smart-d0991019-25ca-4f6f-bc53-cd6662fb50ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604160690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.604160690
Directory	/workspace/22.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2708943512
Short name	T14
Test name
Test status
Simulation time	54061394394 ps
CPU time	431.54 seconds
Started	Apr 16 12:27:34 PM PDT 24
Finished	Apr 16 12:34:48 PM PDT 24
Peak memory	205392 kb
Host	smart-820fc9ba-a984-4856-b02f-f83cbd390386
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708943512 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2708943512
Directory	/workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.rv_timer_cfg_update_on_fly.580374418
Short name	T298
Test name
Test status
Simulation time	1650593870606 ps
CPU time	616.53 seconds
Started	Apr 16 12:27:37 PM PDT 24
Finished	Apr 16 12:37:56 PM PDT 24
Peak memory	182540 kb
Host	smart-88e75c1d-02b5-459d-b34e-38684eae7e80
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580374418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.rv_timer_cfg_update_on_fly.580374418
Directory	/workspace/23.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/23.rv_timer_disabled.3270471427
Short name	T445
Test name
Test status
Simulation time	929050445253 ps
CPU time	213.93 seconds
Started	Apr 16 12:27:23 PM PDT 24
Finished	Apr 16 12:31:01 PM PDT 24
Peak memory	182416 kb
Host	smart-b593ab79-c62c-491d-aa58-65c3b96955a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270471427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3270471427
Directory	/workspace/23.rv_timer_disabled/latest

Test location	/workspace/coverage/default/23.rv_timer_random_reset.1397535203
Short name	T353
Test name
Test status
Simulation time	67158025 ps
CPU time	0.61 seconds
Started	Apr 16 12:27:43 PM PDT 24
Finished	Apr 16 12:27:46 PM PDT 24
Peak memory	182336 kb
Host	smart-bd9f0a93-34df-4341-a0be-f39a226d7c35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397535203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1397535203
Directory	/workspace/23.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3198728341
Short name	T430
Test name
Test status
Simulation time	560259014212 ps
CPU time	327.67 seconds
Started	Apr 16 12:27:27 PM PDT 24
Finished	Apr 16 12:32:58 PM PDT 24
Peak memory	182584 kb
Host	smart-4a8ee526-6a67-4fff-8883-c8ea83cd1a17
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198728341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.3198728341
Directory	/workspace/24.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/24.rv_timer_disabled.2678672254
Short name	T380
Test name
Test status
Simulation time	395421919437 ps
CPU time	149.1 seconds
Started	Apr 16 12:27:24 PM PDT 24
Finished	Apr 16 12:29:57 PM PDT 24
Peak memory	182572 kb
Host	smart-d0552204-2a95-4a69-9dd8-2b15b943ab41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678672254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2678672254
Directory	/workspace/24.rv_timer_disabled/latest

Test location	/workspace/coverage/default/24.rv_timer_random.1895881419
Short name	T143
Test name
Test status
Simulation time	124260978979 ps
CPU time	87.5 seconds
Started	Apr 16 12:27:29 PM PDT 24
Finished	Apr 16 12:28:59 PM PDT 24
Peak memory	182572 kb
Host	smart-5617b86a-9f11-4854-b929-7d7ceab4462b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895881419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1895881419
Directory	/workspace/24.rv_timer_random/latest

Test location	/workspace/coverage/default/24.rv_timer_random_reset.4249109069
Short name	T267
Test name
Test status
Simulation time	99533216618 ps
CPU time	173.66 seconds
Started	Apr 16 12:27:29 PM PDT 24
Finished	Apr 16 12:30:25 PM PDT 24
Peak memory	182544 kb
Host	smart-7ae43e9b-045c-4e02-9c1b-61ac6156f72d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249109069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4249109069
Directory	/workspace/24.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2822263720
Short name	T341
Test name
Test status
Simulation time	91056585994 ps
CPU time	1046.94 seconds
Started	Apr 16 12:27:41 PM PDT 24
Finished	Apr 16 12:45:10 PM PDT 24
Peak memory	212736 kb
Host	smart-ab4ceedc-025e-4dc7-a4ae-c2a627c02b67
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822263720 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2822263720
Directory	/workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2459572806
Short name	T205
Test name
Test status
Simulation time	540077057752 ps
CPU time	986.32 seconds
Started	Apr 16 12:27:26 PM PDT 24
Finished	Apr 16 12:43:55 PM PDT 24
Peak memory	182536 kb
Host	smart-4b7c06ab-0dea-4253-8936-a51515726ad8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459572806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2459572806
Directory	/workspace/25.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/25.rv_timer_disabled.63115826
Short name	T364
Test name
Test status
Simulation time	73354080173 ps
CPU time	108.81 seconds
Started	Apr 16 12:27:43 PM PDT 24
Finished	Apr 16 12:29:34 PM PDT 24
Peak memory	182476 kb
Host	smart-31093d87-1e89-4355-8265-10580305ef2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63115826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.63115826
Directory	/workspace/25.rv_timer_disabled/latest

Test location	/workspace/coverage/default/25.rv_timer_random_reset.2952125913
Short name	T220
Test name
Test status
Simulation time	499951567962 ps
CPU time	417.51 seconds
Started	Apr 16 12:27:26 PM PDT 24
Finished	Apr 16 12:34:27 PM PDT 24
Peak memory	190624 kb
Host	smart-7a5345df-1b2b-4f11-abef-f9fbe1b3d34d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952125913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2952125913
Directory	/workspace/25.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/25.rv_timer_stress_all.330895714
Short name	T59
Test name
Test status
Simulation time	83977354 ps
CPU time	0.57 seconds
Started	Apr 16 12:27:35 PM PDT 24
Finished	Apr 16 12:27:39 PM PDT 24
Peak memory	182236 kb
Host	smart-a2bc9da1-44d3-42db-b7b8-4d06c41e9896
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330895714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all. 330895714
Directory	/workspace/25.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.1802531268
Short name	T40
Test name
Test status
Simulation time	32019264111 ps
CPU time	173.35 seconds
Started	Apr 16 12:27:47 PM PDT 24
Finished	Apr 16 12:30:42 PM PDT 24
Peak memory	205416 kb
Host	smart-7398ce1d-4d0a-4380-91a4-8c68bf36ae34
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802531268 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.1802531268
Directory	/workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.rv_timer_random.3690767607
Short name	T158
Test name
Test status
Simulation time	69335268718 ps
CPU time	107.73 seconds
Started	Apr 16 12:27:39 PM PDT 24
Finished	Apr 16 12:29:30 PM PDT 24
Peak memory	190756 kb
Host	smart-10729630-2ee5-49b8-8449-031a0b8c5d92
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690767607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3690767607
Directory	/workspace/26.rv_timer_random/latest

Test location	/workspace/coverage/default/26.rv_timer_random_reset.3158761732
Short name	T401
Test name
Test status
Simulation time	678834767 ps
CPU time	2.52 seconds
Started	Apr 16 12:27:28 PM PDT 24
Finished	Apr 16 12:27:34 PM PDT 24
Peak memory	182840 kb
Host	smart-1693e1ef-0929-4bb6-8ab0-e236417e7c4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158761732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3158761732
Directory	/workspace/26.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1263137259
Short name	T134
Test name
Test status
Simulation time	938689992517 ps
CPU time	316.02 seconds
Started	Apr 16 12:27:43 PM PDT 24
Finished	Apr 16 12:33:01 PM PDT 24
Peak memory	182384 kb
Host	smart-e49a199b-a6b2-4ee7-bfaa-8d1b0cb33467
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263137259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.1263137259
Directory	/workspace/27.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/27.rv_timer_disabled.2705808201
Short name	T362
Test name
Test status
Simulation time	613717181838 ps
CPU time	130.28 seconds
Started	Apr 16 12:27:31 PM PDT 24
Finished	Apr 16 12:29:44 PM PDT 24
Peak memory	182460 kb
Host	smart-7e36ce95-afe6-4fc0-8883-ff684ab726ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705808201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2705808201
Directory	/workspace/27.rv_timer_disabled/latest

Test location	/workspace/coverage/default/27.rv_timer_random.3763086138
Short name	T312
Test name
Test status
Simulation time	196389605044 ps
CPU time	604.05 seconds
Started	Apr 16 12:27:31 PM PDT 24
Finished	Apr 16 12:37:38 PM PDT 24
Peak memory	190612 kb
Host	smart-9c55d905-7905-4e17-b553-5626146e6149
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763086138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3763086138
Directory	/workspace/27.rv_timer_random/latest

Test location	/workspace/coverage/default/27.rv_timer_random_reset.3327380325
Short name	T432
Test name
Test status
Simulation time	8085452182 ps
CPU time	12.35 seconds
Started	Apr 16 12:27:32 PM PDT 24
Finished	Apr 16 12:27:47 PM PDT 24
Peak memory	194796 kb
Host	smart-c2c9a19c-487c-4c75-aff4-1f77d5d5b05a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3327380325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3327380325
Directory	/workspace/27.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/27.rv_timer_stress_all.3309179826
Short name	T369
Test name
Test status
Simulation time	434620601452 ps
CPU time	252.78 seconds
Started	Apr 16 12:27:31 PM PDT 24
Finished	Apr 16 12:31:47 PM PDT 24
Peak memory	194632 kb
Host	smart-d1d364fa-4e7f-4984-8859-c2bbded566ab
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309179826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .3309179826
Directory	/workspace/27.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1847280490
Short name	T405
Test name
Test status
Simulation time	6135028582 ps
CPU time	11.51 seconds
Started	Apr 16 12:27:31 PM PDT 24
Finished	Apr 16 12:27:46 PM PDT 24
Peak memory	182484 kb
Host	smart-ca02dad8-b65f-419b-9737-f171000a485c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847280490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1847280490
Directory	/workspace/28.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/28.rv_timer_disabled.2979458310
Short name	T419
Test name
Test status
Simulation time	157608532136 ps
CPU time	60.51 seconds
Started	Apr 16 12:27:46 PM PDT 24
Finished	Apr 16 12:28:48 PM PDT 24
Peak memory	182476 kb
Host	smart-96803ff2-6e28-40bb-a76d-160c79eef989
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979458310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2979458310
Directory	/workspace/28.rv_timer_disabled/latest

Test location	/workspace/coverage/default/28.rv_timer_random_reset.1395308608
Short name	T139
Test name
Test status
Simulation time	47550867794 ps
CPU time	71.01 seconds
Started	Apr 16 12:27:47 PM PDT 24
Finished	Apr 16 12:29:00 PM PDT 24
Peak memory	190652 kb
Host	smart-4f4b64d1-11a4-4bc9-b3c8-45384c1ca673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395308608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1395308608
Directory	/workspace/28.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/28.rv_timer_stress_all.3924836738
Short name	T52
Test name
Test status
Simulation time	226370213793 ps
CPU time	71 seconds
Started	Apr 16 12:27:45 PM PDT 24
Finished	Apr 16 12:28:58 PM PDT 24
Peak memory	182612 kb
Host	smart-652adc39-9e6b-47bf-8469-502ec08d37f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924836738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all .3924836738
Directory	/workspace/28.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3776297486
Short name	T42
Test name
Test status
Simulation time	140228959087 ps
CPU time	341.1 seconds
Started	Apr 16 12:27:32 PM PDT 24
Finished	Apr 16 12:33:16 PM PDT 24
Peak memory	205460 kb
Host	smart-c0bcb65b-b2e8-418b-9c67-211c7f04305c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776297486 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3776297486
Directory	/workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3741992843
Short name	T268
Test name
Test status
Simulation time	162991194228 ps
CPU time	251.21 seconds
Started	Apr 16 12:27:36 PM PDT 24
Finished	Apr 16 12:31:50 PM PDT 24
Peak memory	182604 kb
Host	smart-bda5f76f-71ea-444d-ba2a-aeaee29230d5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741992843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.3741992843
Directory	/workspace/29.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/29.rv_timer_disabled.2201647832
Short name	T68
Test name
Test status
Simulation time	222972193658 ps
CPU time	150.29 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:30:24 PM PDT 24
Peak memory	182376 kb
Host	smart-0496c876-eecd-490f-a525-a2fcc9602840
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201647832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2201647832
Directory	/workspace/29.rv_timer_disabled/latest

Test location	/workspace/coverage/default/29.rv_timer_random.4288853755
Short name	T308
Test name
Test status
Simulation time	139638549307 ps
CPU time	598.78 seconds
Started	Apr 16 12:27:34 PM PDT 24
Finished	Apr 16 12:37:36 PM PDT 24
Peak memory	190756 kb
Host	smart-bc37e312-dd44-4c93-9446-467c16c64c38
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288853755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.4288853755
Directory	/workspace/29.rv_timer_random/latest

Test location	/workspace/coverage/default/29.rv_timer_random_reset.1715439283
Short name	T51
Test name
Test status
Simulation time	60035435380 ps
CPU time	251.01 seconds
Started	Apr 16 12:27:47 PM PDT 24
Finished	Apr 16 12:32:00 PM PDT 24
Peak memory	182572 kb
Host	smart-df0775f2-c498-4d20-8c48-08105e780422
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715439283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1715439283
Directory	/workspace/29.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/29.rv_timer_stress_all.2559369761
Short name	T417
Test name
Test status
Simulation time	79803795 ps
CPU time	0.6 seconds
Started	Apr 16 12:27:32 PM PDT 24
Finished	Apr 16 12:27:35 PM PDT 24
Peak memory	182168 kb
Host	smart-963be868-e0cc-4064-94d4-b3b0e46ac3f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559369761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .2559369761
Directory	/workspace/29.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/3.rv_timer_cfg_update_on_fly.73342360
Short name	T316
Test name
Test status
Simulation time	630491128341 ps
CPU time	348.72 seconds
Started	Apr 16 12:27:11 PM PDT 24
Finished	Apr 16 12:33:06 PM PDT 24
Peak memory	182528 kb
Host	smart-ca257606-47da-46e2-b262-b56f88cba428
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73342360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. rv_timer_cfg_update_on_fly.73342360
Directory	/workspace/3.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/3.rv_timer_disabled.506467336
Short name	T360
Test name
Test status
Simulation time	92535100485 ps
CPU time	120.88 seconds
Started	Apr 16 12:27:07 PM PDT 24
Finished	Apr 16 12:29:14 PM PDT 24
Peak memory	182560 kb
Host	smart-ca02be82-5a69-408a-bad9-ed8f05dc7c9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506467336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.506467336
Directory	/workspace/3.rv_timer_disabled/latest

Test location	/workspace/coverage/default/3.rv_timer_random.341993217
Short name	T7
Test name
Test status
Simulation time	169355804947 ps
CPU time	162.17 seconds
Started	Apr 16 12:27:11 PM PDT 24
Finished	Apr 16 12:29:59 PM PDT 24
Peak memory	190696 kb
Host	smart-55458960-50dd-4f6e-a41d-162ce59973e7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341993217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.341993217
Directory	/workspace/3.rv_timer_random/latest

Test location	/workspace/coverage/default/3.rv_timer_random_reset.2849820563
Short name	T415
Test name
Test status
Simulation time	148921514981 ps
CPU time	439.76 seconds
Started	Apr 16 12:27:07 PM PDT 24
Finished	Apr 16 12:34:32 PM PDT 24
Peak memory	190760 kb
Host	smart-ceec0919-a30e-4092-a65e-3f7703f507e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2849820563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2849820563
Directory	/workspace/3.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/3.rv_timer_sec_cm.3831819884
Short name	T18
Test name
Test status
Simulation time	110220580 ps
CPU time	0.76 seconds
Started	Apr 16 12:27:09 PM PDT 24
Finished	Apr 16 12:27:15 PM PDT 24
Peak memory	213040 kb
Host	smart-84e97ccb-9204-4f3a-b625-08b76b75fe2a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831819884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3831819884
Directory	/workspace/3.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/30.rv_timer_disabled.1492622809
Short name	T372
Test name
Test status
Simulation time	112902572613 ps
CPU time	152.36 seconds
Started	Apr 16 12:27:45 PM PDT 24
Finished	Apr 16 12:30:20 PM PDT 24
Peak memory	182548 kb
Host	smart-9517bc42-6a9b-4696-8667-0175f86493af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492622809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1492622809
Directory	/workspace/30.rv_timer_disabled/latest

Test location	/workspace/coverage/default/30.rv_timer_random.3359160160
Short name	T301
Test name
Test status
Simulation time	339399998054 ps
CPU time	340.49 seconds
Started	Apr 16 12:27:48 PM PDT 24
Finished	Apr 16 12:33:30 PM PDT 24
Peak memory	190804 kb
Host	smart-565c8d9d-fb77-40bf-b3e0-35d32ce745d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359160160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3359160160
Directory	/workspace/30.rv_timer_random/latest

Test location	/workspace/coverage/default/30.rv_timer_random_reset.2270677935
Short name	T434
Test name
Test status
Simulation time	103138721863 ps
CPU time	130.53 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:30:13 PM PDT 24
Peak memory	190668 kb
Host	smart-0ef4b8bf-c146-43af-a020-45a233f347f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270677935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2270677935
Directory	/workspace/30.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/30.rv_timer_stress_all.2676710320
Short name	T363
Test name
Test status
Simulation time	574999629498 ps
CPU time	484.66 seconds
Started	Apr 16 12:27:30 PM PDT 24
Finished	Apr 16 12:35:38 PM PDT 24
Peak memory	191076 kb
Host	smart-cff93892-3ef1-466f-93d4-e4562a438053
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676710320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .2676710320
Directory	/workspace/30.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1008822770
Short name	T172
Test name
Test status
Simulation time	321451493397 ps
CPU time	177.2 seconds
Started	Apr 16 12:27:33 PM PDT 24
Finished	Apr 16 12:30:33 PM PDT 24
Peak memory	182588 kb
Host	smart-e30bc28f-9021-4f78-a593-9e3cf9b3c0e1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008822770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.1008822770
Directory	/workspace/31.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/31.rv_timer_disabled.586371553
Short name	T403
Test name
Test status
Simulation time	645542462209 ps
CPU time	291.31 seconds
Started	Apr 16 12:27:34 PM PDT 24
Finished	Apr 16 12:32:29 PM PDT 24
Peak memory	182496 kb
Host	smart-3107e8f9-4f67-49d2-9b82-d1d6f16a4b0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586371553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.586371553
Directory	/workspace/31.rv_timer_disabled/latest

Test location	/workspace/coverage/default/31.rv_timer_random.3237759265
Short name	T450
Test name
Test status
Simulation time	158122276387 ps
CPU time	151.73 seconds
Started	Apr 16 12:27:31 PM PDT 24
Finished	Apr 16 12:30:05 PM PDT 24
Peak memory	190788 kb
Host	smart-2aab8d51-235c-4a1b-b7f5-09cc4f346ed6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237759265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3237759265
Directory	/workspace/31.rv_timer_random/latest

Test location	/workspace/coverage/default/31.rv_timer_random_reset.2402543690
Short name	T436
Test name
Test status
Simulation time	20472351872 ps
CPU time	695.69 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:39:32 PM PDT 24
Peak memory	190796 kb
Host	smart-8c3f5098-bc42-4fbd-b301-3d62d2491843
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402543690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2402543690
Directory	/workspace/31.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/31.rv_timer_stress_all.2695437143
Short name	T385
Test name
Test status
Simulation time	82991162444 ps
CPU time	104.24 seconds
Started	Apr 16 12:27:48 PM PDT 24
Finished	Apr 16 12:29:33 PM PDT 24
Peak memory	194072 kb
Host	smart-157de80a-e7b9-4478-a0df-0734ab175dd9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695437143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all .2695437143
Directory	/workspace/31.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.162095526
Short name	T38
Test name
Test status
Simulation time	63008993877 ps
CPU time	646.85 seconds
Started	Apr 16 12:27:30 PM PDT 24
Finished	Apr 16 12:38:20 PM PDT 24
Peak memory	206180 kb
Host	smart-60ee224e-09b9-4f3b-a96c-55b008ed4eb8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162095526 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.162095526
Directory	/workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.rv_timer_cfg_update_on_fly.492834272
Short name	T138
Test name
Test status
Simulation time	470646498670 ps
CPU time	502.39 seconds
Started	Apr 16 12:27:43 PM PDT 24
Finished	Apr 16 12:36:08 PM PDT 24
Peak memory	182612 kb
Host	smart-d640d67c-81fd-4f99-9bad-ebca0a409eb0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492834272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.rv_timer_cfg_update_on_fly.492834272
Directory	/workspace/32.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/32.rv_timer_disabled.1395305446
Short name	T356
Test name
Test status
Simulation time	118020358152 ps
CPU time	157.57 seconds
Started	Apr 16 12:27:33 PM PDT 24
Finished	Apr 16 12:30:13 PM PDT 24
Peak memory	182524 kb
Host	smart-6a31dbb6-04ad-402e-ab9f-3d5b0d02fffb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395305446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1395305446
Directory	/workspace/32.rv_timer_disabled/latest

Test location	/workspace/coverage/default/32.rv_timer_random.1145236911
Short name	T192
Test name
Test status
Simulation time	152379775805 ps
CPU time	351.81 seconds
Started	Apr 16 12:27:50 PM PDT 24
Finished	Apr 16 12:33:44 PM PDT 24
Peak memory	190744 kb
Host	smart-91bfcdf0-1d1c-4d02-ac1d-eed5d4d17008
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145236911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1145236911
Directory	/workspace/32.rv_timer_random/latest

Test location	/workspace/coverage/default/32.rv_timer_random_reset.2127876784
Short name	T6
Test name
Test status
Simulation time	165431663238 ps
CPU time	33.86 seconds
Started	Apr 16 12:27:31 PM PDT 24
Finished	Apr 16 12:28:08 PM PDT 24
Peak memory	194172 kb
Host	smart-c8ae0f82-3394-45a8-9c61-9585457f6869
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127876784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2127876784
Directory	/workspace/32.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3619928933
Short name	T342
Test name
Test status
Simulation time	807544064913 ps
CPU time	196.47 seconds
Started	Apr 16 12:27:38 PM PDT 24
Finished	Apr 16 12:30:58 PM PDT 24
Peak memory	182436 kb
Host	smart-f992844b-1ddd-4836-8e23-0fcd55e39b7a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619928933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.3619928933
Directory	/workspace/33.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/33.rv_timer_disabled.1005652152
Short name	T421
Test name
Test status
Simulation time	31867007772 ps
CPU time	49.29 seconds
Started	Apr 16 12:27:37 PM PDT 24
Finished	Apr 16 12:28:30 PM PDT 24
Peak memory	182524 kb
Host	smart-6d42a151-3100-4641-b16a-00c10dccc61c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005652152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1005652152
Directory	/workspace/33.rv_timer_disabled/latest

Test location	/workspace/coverage/default/33.rv_timer_random.844952020
Short name	T297
Test name
Test status
Simulation time	109840133597 ps
CPU time	197.71 seconds
Started	Apr 16 12:27:56 PM PDT 24
Finished	Apr 16 12:31:16 PM PDT 24
Peak memory	190792 kb
Host	smart-761ff5ee-12a4-45ef-9194-d8b674b39218
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844952020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.844952020
Directory	/workspace/33.rv_timer_random/latest

Test location	/workspace/coverage/default/33.rv_timer_random_reset.2623145291
Short name	T423
Test name
Test status
Simulation time	65637172520 ps
CPU time	45.2 seconds
Started	Apr 16 12:27:39 PM PDT 24
Finished	Apr 16 12:28:27 PM PDT 24
Peak memory	190744 kb
Host	smart-39fd83e2-befe-4066-95f8-1274171a6e80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623145291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2623145291
Directory	/workspace/33.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/33.rv_timer_stress_all.25141372
Short name	T231
Test name
Test status
Simulation time	487949077234 ps
CPU time	1323.66 seconds
Started	Apr 16 12:27:38 PM PDT 24
Finished	Apr 16 12:49:45 PM PDT 24
Peak memory	190688 kb
Host	smart-68f563d3-2cab-451c-be0a-33387aebe7f3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25141372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.25141372
Directory	/workspace/33.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.4151855768
Short name	T53
Test name
Test status
Simulation time	374673251731 ps
CPU time	613.33 seconds
Started	Apr 16 12:27:38 PM PDT 24
Finished	Apr 16 12:37:55 PM PDT 24
Peak memory	206928 kb
Host	smart-5e689a2d-76b5-4d52-a340-25cb9888889f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151855768 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.4151855768
Directory	/workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.rv_timer_cfg_update_on_fly.4096568899
Short name	T322
Test name
Test status
Simulation time	887257739325 ps
CPU time	320.06 seconds
Started	Apr 16 12:27:40 PM PDT 24
Finished	Apr 16 12:33:03 PM PDT 24
Peak memory	182484 kb
Host	smart-a2266254-0a1b-44f9-9be9-066cd04bb0f4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096568899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.4096568899
Directory	/workspace/34.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/34.rv_timer_disabled.3682755870
Short name	T379
Test name
Test status
Simulation time	48820856800 ps
CPU time	76.18 seconds
Started	Apr 16 12:27:48 PM PDT 24
Finished	Apr 16 12:29:05 PM PDT 24
Peak memory	182572 kb
Host	smart-25c8bd86-3061-454d-b4af-00ee84e71062
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682755870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3682755870
Directory	/workspace/34.rv_timer_disabled/latest

Test location	/workspace/coverage/default/34.rv_timer_random.144944414
Short name	T181
Test name
Test status
Simulation time	340392059774 ps
CPU time	185.34 seconds
Started	Apr 16 12:27:39 PM PDT 24
Finished	Apr 16 12:30:47 PM PDT 24
Peak memory	194220 kb
Host	smart-ad2a783a-151d-48b5-b8ff-131b910a314c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144944414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.144944414
Directory	/workspace/34.rv_timer_random/latest

Test location	/workspace/coverage/default/34.rv_timer_random_reset.2027393272
Short name	T283
Test name
Test status
Simulation time	108041774170 ps
CPU time	96.75 seconds
Started	Apr 16 12:27:37 PM PDT 24
Finished	Apr 16 12:29:18 PM PDT 24
Peak memory	190752 kb
Host	smart-5c6c38b6-93ad-42ff-95b5-39d4f7d5ff9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027393272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2027393272
Directory	/workspace/34.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/34.rv_timer_stress_all.1693063285
Short name	T337
Test name
Test status
Simulation time	623750502468 ps
CPU time	410.37 seconds
Started	Apr 16 12:27:48 PM PDT 24
Finished	Apr 16 12:34:40 PM PDT 24
Peak memory	190680 kb
Host	smart-eb538531-2c42-4f3b-a6f5-e336c6f01930
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693063285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all .1693063285
Directory	/workspace/34.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/35.rv_timer_cfg_update_on_fly.354573284
Short name	T294
Test name
Test status
Simulation time	360320428654 ps
CPU time	186.86 seconds
Started	Apr 16 12:27:37 PM PDT 24
Finished	Apr 16 12:30:48 PM PDT 24
Peak memory	182508 kb
Host	smart-a85ac010-f553-4f2d-96f7-c38819916731
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354573284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.rv_timer_cfg_update_on_fly.354573284
Directory	/workspace/35.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/35.rv_timer_disabled.354177128
Short name	T46
Test name
Test status
Simulation time	113225966005 ps
CPU time	180.18 seconds
Started	Apr 16 12:27:46 PM PDT 24
Finished	Apr 16 12:30:48 PM PDT 24
Peak memory	182464 kb
Host	smart-6dd3f5cc-f56a-4066-ab0b-cffc24a5e854
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354177128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.354177128
Directory	/workspace/35.rv_timer_disabled/latest

Test location	/workspace/coverage/default/35.rv_timer_random.1553731752
Short name	T321
Test name
Test status
Simulation time	116123597453 ps
CPU time	771.52 seconds
Started	Apr 16 12:27:49 PM PDT 24
Finished	Apr 16 12:40:42 PM PDT 24
Peak memory	190684 kb
Host	smart-01fb01e1-fa61-4856-a136-52e9f56aa765
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553731752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1553731752
Directory	/workspace/35.rv_timer_random/latest

Test location	/workspace/coverage/default/35.rv_timer_random_reset.3267331845
Short name	T239
Test name
Test status
Simulation time	64189275968 ps
CPU time	63.47 seconds
Started	Apr 16 12:27:37 PM PDT 24
Finished	Apr 16 12:28:44 PM PDT 24
Peak memory	182448 kb
Host	smart-61c7a814-a82f-4efd-a4c6-338d072f1b2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267331845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3267331845
Directory	/workspace/35.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/35.rv_timer_stress_all.2303262799
Short name	T303
Test name
Test status
Simulation time	118680826257 ps
CPU time	185.33 seconds
Started	Apr 16 12:27:40 PM PDT 24
Finished	Apr 16 12:30:49 PM PDT 24
Peak memory	194544 kb
Host	smart-a18b2b79-855f-40c0-b1bc-9974b61245de
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303262799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all .2303262799
Directory	/workspace/35.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1988172184
Short name	T5
Test name
Test status
Simulation time	636136755668 ps
CPU time	620.66 seconds
Started	Apr 16 12:27:58 PM PDT 24
Finished	Apr 16 12:38:20 PM PDT 24
Peak memory	182540 kb
Host	smart-5b734165-b52c-4c66-b268-89e3836d562f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988172184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.1988172184
Directory	/workspace/36.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/36.rv_timer_disabled.19742196
Short name	T383
Test name
Test status
Simulation time	685854326305 ps
CPU time	213.65 seconds
Started	Apr 16 12:27:36 PM PDT 24
Finished	Apr 16 12:31:13 PM PDT 24
Peak memory	182572 kb
Host	smart-af728c95-1ed1-4e90-a8bb-d5f53a02e6f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19742196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.19742196
Directory	/workspace/36.rv_timer_disabled/latest

Test location	/workspace/coverage/default/36.rv_timer_random.1824976895
Short name	T346
Test name
Test status
Simulation time	64194096528 ps
CPU time	178.7 seconds
Started	Apr 16 12:27:39 PM PDT 24
Finished	Apr 16 12:30:41 PM PDT 24
Peak memory	182472 kb
Host	smart-0a5b0718-70fa-415c-a25f-5eeb51f4e9d7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824976895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1824976895
Directory	/workspace/36.rv_timer_random/latest

Test location	/workspace/coverage/default/36.rv_timer_random_reset.2007092444
Short name	T125
Test name
Test status
Simulation time	129401958598 ps
CPU time	287.94 seconds
Started	Apr 16 12:27:37 PM PDT 24
Finished	Apr 16 12:32:29 PM PDT 24
Peak memory	194500 kb
Host	smart-c4d7878b-0b9a-487d-8660-ed6efa7dd096
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007092444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2007092444
Directory	/workspace/36.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2439021533
Short name	T266
Test name
Test status
Simulation time	22741294987 ps
CPU time	33.97 seconds
Started	Apr 16 12:27:41 PM PDT 24
Finished	Apr 16 12:28:17 PM PDT 24
Peak memory	182480 kb
Host	smart-f71b6283-b86c-4e57-9cde-2e3b1cc63453
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439021533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2439021533
Directory	/workspace/37.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/37.rv_timer_disabled.1801197897
Short name	T377
Test name
Test status
Simulation time	171821331851 ps
CPU time	78.44 seconds
Started	Apr 16 12:27:42 PM PDT 24
Finished	Apr 16 12:29:03 PM PDT 24
Peak memory	182484 kb
Host	smart-0d782e0f-4b40-4d5f-9701-fad63a6a3190
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1801197897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1801197897
Directory	/workspace/37.rv_timer_disabled/latest

Test location	/workspace/coverage/default/37.rv_timer_random.2955646937
Short name	T374
Test name
Test status
Simulation time	123237128558 ps
CPU time	72.58 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:29:09 PM PDT 24
Peak memory	182524 kb
Host	smart-dee9a349-743a-446d-95bc-9613f375f7be
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955646937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2955646937
Directory	/workspace/37.rv_timer_random/latest

Test location	/workspace/coverage/default/37.rv_timer_random_reset.3130156520
Short name	T111
Test name
Test status
Simulation time	29331021725 ps
CPU time	28.56 seconds
Started	Apr 16 12:27:46 PM PDT 24
Finished	Apr 16 12:28:17 PM PDT 24
Peak memory	182576 kb
Host	smart-f6330609-3666-4f9e-bb67-6ff90ee66aa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130156520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3130156520
Directory	/workspace/37.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/37.rv_timer_stress_all.1146199659
Short name	T10
Test name
Test status
Simulation time	142310890086 ps
CPU time	121.05 seconds
Started	Apr 16 12:27:43 PM PDT 24
Finished	Apr 16 12:29:47 PM PDT 24
Peak memory	182576 kb
Host	smart-ca0b7c9b-7498-49a0-90cf-ac59e94482d8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146199659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .1146199659
Directory	/workspace/37.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/38.rv_timer_cfg_update_on_fly.528789061
Short name	T258
Test name
Test status
Simulation time	313935006269 ps
CPU time	161.4 seconds
Started	Apr 16 12:27:48 PM PDT 24
Finished	Apr 16 12:30:31 PM PDT 24
Peak memory	182592 kb
Host	smart-7451fac8-6528-433e-8bb5-320d846c63bd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528789061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.rv_timer_cfg_update_on_fly.528789061
Directory	/workspace/38.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/38.rv_timer_disabled.2431913828
Short name	T408
Test name
Test status
Simulation time	460776761255 ps
CPU time	183.15 seconds
Started	Apr 16 12:28:09 PM PDT 24
Finished	Apr 16 12:31:14 PM PDT 24
Peak memory	182476 kb
Host	smart-b664a1ef-2ce2-4445-b237-3780632e0b49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431913828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2431913828
Directory	/workspace/38.rv_timer_disabled/latest

Test location	/workspace/coverage/default/38.rv_timer_random.2877516930
Short name	T176
Test name
Test status
Simulation time	190846947724 ps
CPU time	204.67 seconds
Started	Apr 16 12:27:39 PM PDT 24
Finished	Apr 16 12:31:07 PM PDT 24
Peak memory	190764 kb
Host	smart-695e01ad-3d36-4770-86fe-9649cb50f797
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877516930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2877516930
Directory	/workspace/38.rv_timer_random/latest

Test location	/workspace/coverage/default/38.rv_timer_random_reset.19184648
Short name	T437
Test name
Test status
Simulation time	183976725178 ps
CPU time	475.65 seconds
Started	Apr 16 12:27:47 PM PDT 24
Finished	Apr 16 12:35:45 PM PDT 24
Peak memory	182396 kb
Host	smart-a097798f-3a1e-4cc4-adbb-29d1b15c9c60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19184648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.19184648
Directory	/workspace/38.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/38.rv_timer_stress_all.1961637161
Short name	T392
Test name
Test status
Simulation time	359784862165 ps
CPU time	563.63 seconds
Started	Apr 16 12:27:45 PM PDT 24
Finished	Apr 16 12:37:10 PM PDT 24
Peak memory	190776 kb
Host	smart-2bf61b5d-13ca-4930-9c03-bd5c907b4e45
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961637161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .1961637161
Directory	/workspace/38.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/39.rv_timer_cfg_update_on_fly.91861918
Short name	T273
Test name
Test status
Simulation time	78125075577 ps
CPU time	33.78 seconds
Started	Apr 16 12:27:44 PM PDT 24
Finished	Apr 16 12:28:20 PM PDT 24
Peak memory	182584 kb
Host	smart-c15e61b3-fca7-483c-8012-072807aac213
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91861918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .rv_timer_cfg_update_on_fly.91861918
Directory	/workspace/39.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/39.rv_timer_disabled.1831063857
Short name	T399
Test name
Test status
Simulation time	98601765855 ps
CPU time	37.91 seconds
Started	Apr 16 12:27:55 PM PDT 24
Finished	Apr 16 12:28:35 PM PDT 24
Peak memory	182460 kb
Host	smart-3cd59434-060a-4557-acab-c4e95827453b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831063857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1831063857
Directory	/workspace/39.rv_timer_disabled/latest

Test location	/workspace/coverage/default/39.rv_timer_random.4152284901
Short name	T259
Test name
Test status
Simulation time	13874021637 ps
CPU time	293.68 seconds
Started	Apr 16 12:27:45 PM PDT 24
Finished	Apr 16 12:32:40 PM PDT 24
Peak memory	190680 kb
Host	smart-17f8acc8-1310-4ed3-87b9-1b5e21aa7872
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152284901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4152284901
Directory	/workspace/39.rv_timer_random/latest

Test location	/workspace/coverage/default/39.rv_timer_random_reset.2296886096
Short name	T381
Test name
Test status
Simulation time	1729625890 ps
CPU time	0.89 seconds
Started	Apr 16 12:27:55 PM PDT 24
Finished	Apr 16 12:27:58 PM PDT 24
Peak memory	182300 kb
Host	smart-b9a20465-67c9-400f-b92a-b0c539961e4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2296886096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2296886096
Directory	/workspace/39.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/39.rv_timer_stress_all.3343588528
Short name	T251
Test name
Test status
Simulation time	1383878471416 ps
CPU time	359.81 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:33:55 PM PDT 24
Peak memory	190692 kb
Host	smart-58a24236-9f7d-4f03-a662-3a5140c708b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343588528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .3343588528
Directory	/workspace/39.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2504516534
Short name	T345
Test name
Test status
Simulation time	51300853833 ps
CPU time	49.36 seconds
Started	Apr 16 12:27:11 PM PDT 24
Finished	Apr 16 12:28:06 PM PDT 24
Peak memory	182476 kb
Host	smart-a4bfd593-c872-441d-a4a1-b00d09101e83
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504516534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.2504516534
Directory	/workspace/4.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/4.rv_timer_disabled.2616706884
Short name	T358
Test name
Test status
Simulation time	442675617870 ps
CPU time	177.7 seconds
Started	Apr 16 12:27:12 PM PDT 24
Finished	Apr 16 12:30:15 PM PDT 24
Peak memory	182484 kb
Host	smart-99231af1-0ce5-4eea-bee7-5f1692740e7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616706884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2616706884
Directory	/workspace/4.rv_timer_disabled/latest

Test location	/workspace/coverage/default/4.rv_timer_random.2683163809
Short name	T286
Test name
Test status
Simulation time	121291940170 ps
CPU time	1088.42 seconds
Started	Apr 16 12:27:08 PM PDT 24
Finished	Apr 16 12:45:22 PM PDT 24
Peak memory	190772 kb
Host	smart-3e8761ea-34dd-442a-abc3-ec3e01843335
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683163809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2683163809
Directory	/workspace/4.rv_timer_random/latest

Test location	/workspace/coverage/default/4.rv_timer_random_reset.2711640783
Short name	T359
Test name
Test status
Simulation time	110182688 ps
CPU time	1.43 seconds
Started	Apr 16 12:27:10 PM PDT 24
Finished	Apr 16 12:27:17 PM PDT 24
Peak memory	182532 kb
Host	smart-3009613f-879e-4a47-8cde-602f588961b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711640783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2711640783
Directory	/workspace/4.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/4.rv_timer_sec_cm.2862290142
Short name	T20
Test name
Test status
Simulation time	69076646 ps
CPU time	0.8 seconds
Started	Apr 16 12:27:08 PM PDT 24
Finished	Apr 16 12:27:14 PM PDT 24
Peak memory	213032 kb
Host	smart-5b1d2d4b-c6ee-4cf6-bd49-2e6099ef80f6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862290142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2862290142
Directory	/workspace/4.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2339795522
Short name	T247
Test name
Test status
Simulation time	284017201334 ps
CPU time	455.69 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:35:31 PM PDT 24
Peak memory	182556 kb
Host	smart-0bd28a95-28e9-469f-8f1c-719610dae958
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339795522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.2339795522
Directory	/workspace/40.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/40.rv_timer_disabled.3093172870
Short name	T361
Test name
Test status
Simulation time	138707615385 ps
CPU time	187.67 seconds
Started	Apr 16 12:27:45 PM PDT 24
Finished	Apr 16 12:30:55 PM PDT 24
Peak memory	182416 kb
Host	smart-2b1fedc1-eb7e-497e-b363-4152603ed121
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093172870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3093172870
Directory	/workspace/40.rv_timer_disabled/latest

Test location	/workspace/coverage/default/40.rv_timer_random.1597362736
Short name	T187
Test name
Test status
Simulation time	141544670636 ps
CPU time	580.62 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:37:35 PM PDT 24
Peak memory	190656 kb
Host	smart-19ab5112-7626-4850-811f-90608d222e93
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597362736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1597362736
Directory	/workspace/40.rv_timer_random/latest

Test location	/workspace/coverage/default/40.rv_timer_random_reset.443660421
Short name	T384
Test name
Test status
Simulation time	370296350 ps
CPU time	1.69 seconds
Started	Apr 16 12:27:50 PM PDT 24
Finished	Apr 16 12:27:55 PM PDT 24
Peak memory	182408 kb
Host	smart-9297d3ba-d9b4-4170-ace0-6df31e799679
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443660421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.443660421
Directory	/workspace/40.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/40.rv_timer_stress_all.3817153131
Short name	T451
Test name
Test status
Simulation time	331895892970 ps
CPU time	254.11 seconds
Started	Apr 16 12:27:47 PM PDT 24
Finished	Apr 16 12:32:03 PM PDT 24
Peak memory	194188 kb
Host	smart-84bfbf2f-122f-46dc-83d1-327f06185554
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817153131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all .3817153131
Directory	/workspace/40.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3901927313
Short name	T120
Test name
Test status
Simulation time	305229060337 ps
CPU time	267.09 seconds
Started	Apr 16 12:27:47 PM PDT 24
Finished	Apr 16 12:32:16 PM PDT 24
Peak memory	182508 kb
Host	smart-928e98a1-5fc8-4b21-8105-5b7f7369791f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901927313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3901927313
Directory	/workspace/41.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/41.rv_timer_disabled.3968050135
Short name	T355
Test name
Test status
Simulation time	268986581266 ps
CPU time	128.45 seconds
Started	Apr 16 12:27:46 PM PDT 24
Finished	Apr 16 12:29:57 PM PDT 24
Peak memory	182460 kb
Host	smart-f4b2ff09-dc65-4970-9514-8b5516bbeb92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968050135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3968050135
Directory	/workspace/41.rv_timer_disabled/latest

Test location	/workspace/coverage/default/41.rv_timer_random.3879355891
Short name	T189
Test name
Test status
Simulation time	58533617215 ps
CPU time	168.37 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:30:44 PM PDT 24
Peak memory	190716 kb
Host	smart-f8a7f42f-3d82-4295-8813-c1496428dbcb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879355891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3879355891
Directory	/workspace/41.rv_timer_random/latest

Test location	/workspace/coverage/default/41.rv_timer_random_reset.2844240059
Short name	T206
Test name
Test status
Simulation time	428074874640 ps
CPU time	443.44 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:35:26 PM PDT 24
Peak memory	193972 kb
Host	smart-a3d2df18-6fa5-45b0-989a-1a55d24e0a38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844240059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2844240059
Directory	/workspace/41.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/41.rv_timer_stress_all.1134376375
Short name	T91
Test name
Test status
Simulation time	1834476063896 ps
CPU time	1243.41 seconds
Started	Apr 16 12:27:45 PM PDT 24
Finished	Apr 16 12:48:31 PM PDT 24
Peak memory	190776 kb
Host	smart-c72fc88d-7602-431c-975c-cd0a30cee14c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134376375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all .1134376375
Directory	/workspace/41.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/42.rv_timer_disabled.596631730
Short name	T382
Test name
Test status
Simulation time	160124322356 ps
CPU time	44.1 seconds
Started	Apr 16 12:27:45 PM PDT 24
Finished	Apr 16 12:28:31 PM PDT 24
Peak memory	182460 kb
Host	smart-3b1ec436-8afe-4ce9-91e0-f63e0c52508b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596631730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.596631730
Directory	/workspace/42.rv_timer_disabled/latest

Test location	/workspace/coverage/default/42.rv_timer_random.542439291
Short name	T325
Test name
Test status
Simulation time	338884722987 ps
CPU time	238.77 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:31:55 PM PDT 24
Peak memory	190672 kb
Host	smart-6729f9c4-4023-4943-acd1-608f6a26c82d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542439291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.542439291
Directory	/workspace/42.rv_timer_random/latest

Test location	/workspace/coverage/default/42.rv_timer_random_reset.105111092
Short name	T422
Test name
Test status
Simulation time	31745827 ps
CPU time	0.51 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:28:05 PM PDT 24
Peak memory	182196 kb
Host	smart-d1dea0df-52e1-44b0-b666-4589db927c01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105111092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.105111092
Directory	/workspace/42.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/42.rv_timer_stress_all.783167716
Short name	T440
Test name
Test status
Simulation time	869243370198 ps
CPU time	345.12 seconds
Started	Apr 16 12:27:46 PM PDT 24
Finished	Apr 16 12:33:33 PM PDT 24
Peak memory	190664 kb
Host	smart-7ed1e5d9-efa9-4e61-9fac-ea43c80cecb2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783167716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all. 783167716
Directory	/workspace/42.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3071308847
Short name	T248
Test name
Test status
Simulation time	1156954862760 ps
CPU time	852.09 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:42:17 PM PDT 24
Peak memory	182532 kb
Host	smart-bddf95cf-582d-49f3-a3de-11fd93ba8a14
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071308847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3071308847
Directory	/workspace/43.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/43.rv_timer_disabled.3050988306
Short name	T371
Test name
Test status
Simulation time	118408389636 ps
CPU time	169.41 seconds
Started	Apr 16 12:27:50 PM PDT 24
Finished	Apr 16 12:30:42 PM PDT 24
Peak memory	182544 kb
Host	smart-745769e7-e6fa-42c0-b4b4-e6f54038f97a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050988306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3050988306
Directory	/workspace/43.rv_timer_disabled/latest

Test location	/workspace/coverage/default/43.rv_timer_random.3933554542
Short name	T212
Test name
Test status
Simulation time	77830625128 ps
CPU time	114.43 seconds
Started	Apr 16 12:27:47 PM PDT 24
Finished	Apr 16 12:29:43 PM PDT 24
Peak memory	190632 kb
Host	smart-c0546ec8-8e71-4ed2-9d39-25de43fcb704
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933554542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3933554542
Directory	/workspace/43.rv_timer_random/latest

Test location	/workspace/coverage/default/43.rv_timer_random_reset.1308159106
Short name	T252
Test name
Test status
Simulation time	9087763478 ps
CPU time	16.97 seconds
Started	Apr 16 12:27:45 PM PDT 24
Finished	Apr 16 12:28:04 PM PDT 24
Peak memory	190728 kb
Host	smart-5c8539e2-1cf7-46fa-a324-910565a4d084
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308159106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1308159106
Directory	/workspace/43.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/43.rv_timer_stress_all.3035998920
Short name	T63
Test name
Test status
Simulation time	270548158642 ps
CPU time	378.28 seconds
Started	Apr 16 12:27:48 PM PDT 24
Finished	Apr 16 12:34:08 PM PDT 24
Peak memory	194284 kb
Host	smart-8cb3d2aa-4765-4d44-9f79-d4f036ac38be
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035998920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all .3035998920
Directory	/workspace/43.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/44.rv_timer_disabled.2871382580
Short name	T370
Test name
Test status
Simulation time	630151647027 ps
CPU time	221.2 seconds
Started	Apr 16 12:27:50 PM PDT 24
Finished	Apr 16 12:31:33 PM PDT 24
Peak memory	182452 kb
Host	smart-e2c6069d-60f8-423a-8a78-211cc303daa0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871382580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2871382580
Directory	/workspace/44.rv_timer_disabled/latest

Test location	/workspace/coverage/default/44.rv_timer_random.282537646
Short name	T193
Test name
Test status
Simulation time	862297549361 ps
CPU time	1352.38 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:50:28 PM PDT 24
Peak memory	190784 kb
Host	smart-b27226d7-4592-457e-a3db-d32594e66b71
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282537646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.282537646
Directory	/workspace/44.rv_timer_random/latest

Test location	/workspace/coverage/default/44.rv_timer_random_reset.2909703838
Short name	T11
Test name
Test status
Simulation time	1078569960 ps
CPU time	4.2 seconds
Started	Apr 16 12:27:55 PM PDT 24
Finished	Apr 16 12:28:02 PM PDT 24
Peak memory	193320 kb
Host	smart-94b29ab8-9078-458c-8e1e-879cadfb2c7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909703838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2909703838
Directory	/workspace/44.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/44.rv_timer_stress_all.2417251662
Short name	T427
Test name
Test status
Simulation time	3949280778 ps
CPU time	8.39 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:28:04 PM PDT 24
Peak memory	182556 kb
Host	smart-f72ab300-eb9d-40d0-8710-b2d6eb96632b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417251662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all .2417251662
Directory	/workspace/44.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1870485592
Short name	T256
Test name
Test status
Simulation time	501082838497 ps
CPU time	281.15 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:32:36 PM PDT 24
Peak memory	182564 kb
Host	smart-25d9a765-e692-496a-bfcb-fa23bd507e40
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870485592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.1870485592
Directory	/workspace/45.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/45.rv_timer_disabled.1141733471
Short name	T400
Test name
Test status
Simulation time	611910677802 ps
CPU time	149.43 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:30:25 PM PDT 24
Peak memory	182540 kb
Host	smart-844885c1-9376-42a8-85f8-1f5d3bcdb3b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141733471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1141733471
Directory	/workspace/45.rv_timer_disabled/latest

Test location	/workspace/coverage/default/45.rv_timer_random.390432019
Short name	T121
Test name
Test status
Simulation time	183616378028 ps
CPU time	92 seconds
Started	Apr 16 12:28:03 PM PDT 24
Finished	Apr 16 12:29:37 PM PDT 24
Peak memory	190584 kb
Host	smart-1e844f8a-7ebb-4bda-963f-2ffe02d9fdd6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390432019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.390432019
Directory	/workspace/45.rv_timer_random/latest

Test location	/workspace/coverage/default/45.rv_timer_random_reset.3415632311
Short name	T302
Test name
Test status
Simulation time	20736372530 ps
CPU time	189.72 seconds
Started	Apr 16 12:27:50 PM PDT 24
Finished	Apr 16 12:31:03 PM PDT 24
Peak memory	182520 kb
Host	smart-44b97135-1f55-4934-ae39-9746f743a2e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415632311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3415632311
Directory	/workspace/45.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/45.rv_timer_stress_all.803723477
Short name	T366
Test name
Test status
Simulation time	425529538350 ps
CPU time	164.32 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:30:38 PM PDT 24
Peak memory	182420 kb
Host	smart-edfea136-3287-412f-bfd3-0ffc6680eb77
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803723477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all. 803723477
Directory	/workspace/45.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2378225528
Short name	T41
Test name
Test status
Simulation time	113406620333 ps
CPU time	834.5 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:41:49 PM PDT 24
Peak memory	205396 kb
Host	smart-1a37826a-6434-4ef5-9af1-47cdc0ee39cc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378225528 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.2378225528
Directory	/workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1333390708
Short name	T226
Test name
Test status
Simulation time	156878557732 ps
CPU time	263.85 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:32:18 PM PDT 24
Peak memory	182588 kb
Host	smart-4929e36b-1671-447e-854b-d94aa92bebe0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333390708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.1333390708
Directory	/workspace/46.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/46.rv_timer_disabled.2524358563
Short name	T397
Test name
Test status
Simulation time	39910746811 ps
CPU time	67.22 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:29:04 PM PDT 24
Peak memory	182564 kb
Host	smart-a176d83f-10e5-48db-bb58-e90e8081c713
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524358563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2524358563
Directory	/workspace/46.rv_timer_disabled/latest

Test location	/workspace/coverage/default/46.rv_timer_random_reset.1249600204
Short name	T352
Test name
Test status
Simulation time	112259059 ps
CPU time	1.17 seconds
Started	Apr 16 12:28:21 PM PDT 24
Finished	Apr 16 12:28:24 PM PDT 24
Peak memory	182500 kb
Host	smart-511c061c-a470-4c3d-9d64-c54146ca7172
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249600204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1249600204
Directory	/workspace/46.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/47.rv_timer_cfg_update_on_fly.800881790
Short name	T439
Test name
Test status
Simulation time	237452324069 ps
CPU time	120.48 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:30:05 PM PDT 24
Peak memory	182668 kb
Host	smart-2205aa79-7770-4486-b976-005279f1e732
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800881790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.rv_timer_cfg_update_on_fly.800881790
Directory	/workspace/47.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/47.rv_timer_disabled.2379417683
Short name	T378
Test name
Test status
Simulation time	14005432018 ps
CPU time	18.08 seconds
Started	Apr 16 12:27:54 PM PDT 24
Finished	Apr 16 12:28:15 PM PDT 24
Peak memory	182436 kb
Host	smart-36faefa2-ca25-4d55-996d-21e1edce6172
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2379417683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2379417683
Directory	/workspace/47.rv_timer_disabled/latest

Test location	/workspace/coverage/default/47.rv_timer_random.2812729401
Short name	T278
Test name
Test status
Simulation time	458477134427 ps
CPU time	285.91 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:32:40 PM PDT 24
Peak memory	190676 kb
Host	smart-6a3f52d4-c0dc-4258-a30b-f15fa58d0341
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812729401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2812729401
Directory	/workspace/47.rv_timer_random/latest

Test location	/workspace/coverage/default/47.rv_timer_random_reset.3328161031
Short name	T28
Test name
Test status
Simulation time	345255127597 ps
CPU time	448.09 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:35:23 PM PDT 24
Peak memory	190600 kb
Host	smart-7c9e2f04-9bcb-460e-a1ef-79fb6898e8bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328161031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3328161031
Directory	/workspace/47.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/47.rv_timer_stress_all.2437270214
Short name	T428
Test name
Test status
Simulation time	251374155789 ps
CPU time	187.86 seconds
Started	Apr 16 12:27:55 PM PDT 24
Finished	Apr 16 12:31:05 PM PDT 24
Peak memory	194892 kb
Host	smart-d9118919-92b8-4dcf-bcdc-4dbca75ad01b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437270214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all .2437270214
Directory	/workspace/47.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1072842354
Short name	T280
Test name
Test status
Simulation time	535459646772 ps
CPU time	458.82 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:35:34 PM PDT 24
Peak memory	182448 kb
Host	smart-8e18803e-dd70-478d-8dec-609d85bddbef
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072842354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1072842354
Directory	/workspace/48.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/48.rv_timer_disabled.246658335
Short name	T70
Test name
Test status
Simulation time	626239941935 ps
CPU time	276.63 seconds
Started	Apr 16 12:27:54 PM PDT 24
Finished	Apr 16 12:32:33 PM PDT 24
Peak memory	182464 kb
Host	smart-a4cdb9a9-4885-49ad-a19d-7a9d9faa690c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246658335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.246658335
Directory	/workspace/48.rv_timer_disabled/latest

Test location	/workspace/coverage/default/48.rv_timer_random.63299964
Short name	T340
Test name
Test status
Simulation time	26089946553 ps
CPU time	60.01 seconds
Started	Apr 16 12:28:04 PM PDT 24
Finished	Apr 16 12:29:06 PM PDT 24
Peak memory	182492 kb
Host	smart-a78e4240-ce79-4986-ac92-4bbb91db2e80
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63299964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.63299964
Directory	/workspace/48.rv_timer_random/latest

Test location	/workspace/coverage/default/48.rv_timer_random_reset.187392007
Short name	T396
Test name
Test status
Simulation time	56380149339 ps
CPU time	90.24 seconds
Started	Apr 16 12:28:00 PM PDT 24
Finished	Apr 16 12:29:32 PM PDT 24
Peak memory	182548 kb
Host	smart-9b432102-a4e8-4dc8-b2da-758c67bc3361
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187392007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.187392007
Directory	/workspace/48.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/49.rv_timer_disabled.1007188287
Short name	T388
Test name
Test status
Simulation time	163243231205 ps
CPU time	244.74 seconds
Started	Apr 16 12:28:00 PM PDT 24
Finished	Apr 16 12:32:07 PM PDT 24
Peak memory	182560 kb
Host	smart-76d1f5a0-b36a-4926-a0d7-19bbc1d26388
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1007188287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1007188287
Directory	/workspace/49.rv_timer_disabled/latest

Test location	/workspace/coverage/default/49.rv_timer_random.1908625598
Short name	T264
Test name
Test status
Simulation time	46829277206 ps
CPU time	70.62 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:29:15 PM PDT 24
Peak memory	182484 kb
Host	smart-b610f7cc-5e9b-4cdc-b0b1-67bd774c525e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908625598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1908625598
Directory	/workspace/49.rv_timer_random/latest

Test location	/workspace/coverage/default/49.rv_timer_random_reset.1742621158
Short name	T406
Test name
Test status
Simulation time	54715045417 ps
CPU time	245.58 seconds
Started	Apr 16 12:28:00 PM PDT 24
Finished	Apr 16 12:32:08 PM PDT 24
Peak memory	182592 kb
Host	smart-8e4bf1a8-5324-49ce-a532-53f688c59cee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742621158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1742621158
Directory	/workspace/49.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2539078121
Short name	T13
Test name
Test status
Simulation time	30493270316 ps
CPU time	57.34 seconds
Started	Apr 16 12:28:00 PM PDT 24
Finished	Apr 16 12:28:59 PM PDT 24
Peak memory	197288 kb
Host	smart-b0f4ead1-ddac-45dd-8ed1-84064421b924
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539078121 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2539078121
Directory	/workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.rv_timer_cfg_update_on_fly.141180761
Short name	T153
Test name
Test status
Simulation time	22273082241 ps
CPU time	20.59 seconds
Started	Apr 16 12:27:12 PM PDT 24
Finished	Apr 16 12:27:38 PM PDT 24
Peak memory	182508 kb
Host	smart-29e3f55b-84fc-4afb-bdef-d933f20378b3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141180761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .rv_timer_cfg_update_on_fly.141180761
Directory	/workspace/5.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/5.rv_timer_disabled.180853829
Short name	T350
Test name
Test status
Simulation time	184910952365 ps
CPU time	187.31 seconds
Started	Apr 16 12:27:09 PM PDT 24
Finished	Apr 16 12:30:22 PM PDT 24
Peak memory	182560 kb
Host	smart-64a769e5-3283-405e-a47f-73795aa7e7c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180853829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.180853829
Directory	/workspace/5.rv_timer_disabled/latest

Test location	/workspace/coverage/default/5.rv_timer_random.2362266466
Short name	T132
Test name
Test status
Simulation time	78541374790 ps
CPU time	62.98 seconds
Started	Apr 16 12:27:11 PM PDT 24
Finished	Apr 16 12:28:20 PM PDT 24
Peak memory	182456 kb
Host	smart-4aa8eb23-356d-4d1a-8bba-60219cc8e106
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362266466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2362266466
Directory	/workspace/5.rv_timer_random/latest

Test location	/workspace/coverage/default/5.rv_timer_random_reset.163742129
Short name	T141
Test name
Test status
Simulation time	58653640140 ps
CPU time	127.03 seconds
Started	Apr 16 12:27:12 PM PDT 24
Finished	Apr 16 12:29:24 PM PDT 24
Peak memory	190664 kb
Host	smart-dfba4905-5742-4ab9-9678-6b34bb7e3a98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163742129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.163742129
Directory	/workspace/5.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/5.rv_timer_stress_all.1889891428
Short name	T62
Test name
Test status
Simulation time	711894621405 ps
CPU time	608.85 seconds
Started	Apr 16 12:27:08 PM PDT 24
Finished	Apr 16 12:37:23 PM PDT 24
Peak memory	190784 kb
Host	smart-c25e7555-4349-4c3b-a020-8115f01b8dbb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889891428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 1889891428
Directory	/workspace/5.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/50.rv_timer_random.1600348120
Short name	T25
Test name
Test status
Simulation time	50932151019 ps
CPU time	214.28 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:31:30 PM PDT 24
Peak memory	190220 kb
Host	smart-c2b979f8-af4b-40ff-844d-c2dc4f15b97d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600348120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1600348120
Directory	/workspace/50.rv_timer_random/latest

Test location	/workspace/coverage/default/51.rv_timer_random.4102027376
Short name	T449
Test name
Test status
Simulation time	81565673974 ps
CPU time	131.31 seconds
Started	Apr 16 12:27:55 PM PDT 24
Finished	Apr 16 12:30:09 PM PDT 24
Peak memory	190652 kb
Host	smart-4507e0b2-3fc0-430a-b821-7962502aff46
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102027376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4102027376
Directory	/workspace/51.rv_timer_random/latest

Test location	/workspace/coverage/default/54.rv_timer_random.4273854881
Short name	T376
Test name
Test status
Simulation time	192627016479 ps
CPU time	1672.08 seconds
Started	Apr 16 12:28:03 PM PDT 24
Finished	Apr 16 12:55:57 PM PDT 24
Peak memory	182604 kb
Host	smart-adb67022-0e4a-4686-aba0-5726119979b7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273854881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4273854881
Directory	/workspace/54.rv_timer_random/latest

Test location	/workspace/coverage/default/55.rv_timer_random.191743573
Short name	T300
Test name
Test status
Simulation time	63069630472 ps
CPU time	73.13 seconds
Started	Apr 16 12:27:52 PM PDT 24
Finished	Apr 16 12:29:08 PM PDT 24
Peak memory	190632 kb
Host	smart-0d138140-eb79-4c7d-a05a-18374fa6c8ea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191743573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.191743573
Directory	/workspace/55.rv_timer_random/latest

Test location	/workspace/coverage/default/56.rv_timer_random.4175149153
Short name	T24
Test name
Test status
Simulation time	8430295337 ps
CPU time	97.58 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:29:34 PM PDT 24
Peak memory	182568 kb
Host	smart-d9638ab2-a8a0-41ef-b8e3-7640ff4a053c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175149153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4175149153
Directory	/workspace/56.rv_timer_random/latest

Test location	/workspace/coverage/default/57.rv_timer_random.1529487784
Short name	T93
Test name
Test status
Simulation time	389101394270 ps
CPU time	553.27 seconds
Started	Apr 16 12:27:50 PM PDT 24
Finished	Apr 16 12:37:06 PM PDT 24
Peak memory	190688 kb
Host	smart-513d7870-d3b7-4b7d-bf35-881e2aa8a45f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529487784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1529487784
Directory	/workspace/57.rv_timer_random/latest

Test location	/workspace/coverage/default/58.rv_timer_random.1965871936
Short name	T151
Test name
Test status
Simulation time	79160384518 ps
CPU time	143.23 seconds
Started	Apr 16 12:27:51 PM PDT 24
Finished	Apr 16 12:30:18 PM PDT 24
Peak memory	190700 kb
Host	smart-ea08f9f3-e414-4fd2-9553-61da5273be0b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965871936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1965871936
Directory	/workspace/58.rv_timer_random/latest

Test location	/workspace/coverage/default/59.rv_timer_random.1738114406
Short name	T410
Test name
Test status
Simulation time	76162133669 ps
CPU time	128.34 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:30:12 PM PDT 24
Peak memory	190736 kb
Host	smart-7770fa79-9b40-48c0-bdd4-3648953ef2c3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738114406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1738114406
Directory	/workspace/59.rv_timer_random/latest

Test location	/workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3883996805
Short name	T431
Test name
Test status
Simulation time	40363593210 ps
CPU time	36.74 seconds
Started	Apr 16 12:27:03 PM PDT 24
Finished	Apr 16 12:27:44 PM PDT 24
Peak memory	182340 kb
Host	smart-98e7a2c3-aa34-473e-8a55-113883ca0cfe
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883996805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.3883996805
Directory	/workspace/6.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/6.rv_timer_disabled.1155611305
Short name	T349
Test name
Test status
Simulation time	253913638907 ps
CPU time	176.74 seconds
Started	Apr 16 12:27:05 PM PDT 24
Finished	Apr 16 12:30:07 PM PDT 24
Peak memory	182500 kb
Host	smart-166c25bb-5b9a-4aa4-80ae-a65266847f96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155611305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1155611305
Directory	/workspace/6.rv_timer_disabled/latest

Test location	/workspace/coverage/default/6.rv_timer_random.86161897
Short name	T224
Test name
Test status
Simulation time	1237057935549 ps
CPU time	487.27 seconds
Started	Apr 16 12:27:17 PM PDT 24
Finished	Apr 16 12:35:29 PM PDT 24
Peak memory	190672 kb
Host	smart-eda0c11a-5b97-46f9-a7ec-9da615e64410
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86161897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.86161897
Directory	/workspace/6.rv_timer_random/latest

Test location	/workspace/coverage/default/6.rv_timer_random_reset.4129392222
Short name	T49
Test name
Test status
Simulation time	444493176337 ps
CPU time	860.72 seconds
Started	Apr 16 12:27:17 PM PDT 24
Finished	Apr 16 12:41:43 PM PDT 24
Peak memory	182548 kb
Host	smart-9d6ef844-9922-44d3-bab1-a462c03932eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129392222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4129392222
Directory	/workspace/6.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/60.rv_timer_random.844434674
Short name	T304
Test name
Test status
Simulation time	227429816360 ps
CPU time	214.1 seconds
Started	Apr 16 12:27:53 PM PDT 24
Finished	Apr 16 12:31:30 PM PDT 24
Peak memory	190768 kb
Host	smart-c656de4a-bd90-4982-b3a6-76c9eefce0ab
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844434674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.844434674
Directory	/workspace/60.rv_timer_random/latest

Test location	/workspace/coverage/default/61.rv_timer_random.2077286889
Short name	T293
Test name
Test status
Simulation time	21144695632 ps
CPU time	39.99 seconds
Started	Apr 16 12:28:09 PM PDT 24
Finished	Apr 16 12:28:51 PM PDT 24
Peak memory	182348 kb
Host	smart-4376224e-306a-42aa-97e0-1430b318318a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077286889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2077286889
Directory	/workspace/61.rv_timer_random/latest

Test location	/workspace/coverage/default/62.rv_timer_random.3004123136
Short name	T414
Test name
Test status
Simulation time	139873350531 ps
CPU time	209.43 seconds
Started	Apr 16 12:27:54 PM PDT 24
Finished	Apr 16 12:31:26 PM PDT 24
Peak memory	190756 kb
Host	smart-52d91984-dc9a-4a4c-b7e6-00b48d86ee79
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004123136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3004123136
Directory	/workspace/62.rv_timer_random/latest

Test location	/workspace/coverage/default/63.rv_timer_random.1557554999
Short name	T114
Test name
Test status
Simulation time	260936931914 ps
CPU time	1198.28 seconds
Started	Apr 16 12:27:57 PM PDT 24
Finished	Apr 16 12:47:58 PM PDT 24
Peak memory	190796 kb
Host	smart-7d925d7d-4061-4ca4-8326-9a5de36b929b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557554999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1557554999
Directory	/workspace/63.rv_timer_random/latest

Test location	/workspace/coverage/default/65.rv_timer_random.1436439136
Short name	T107
Test name
Test status
Simulation time	147858296598 ps
CPU time	130.33 seconds
Started	Apr 16 12:28:10 PM PDT 24
Finished	Apr 16 12:30:22 PM PDT 24
Peak memory	182568 kb
Host	smart-d111a02a-c94d-4115-985b-f98c8e72e414
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436439136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1436439136
Directory	/workspace/65.rv_timer_random/latest

Test location	/workspace/coverage/default/67.rv_timer_random.2340500065
Short name	T29
Test name
Test status
Simulation time	119401840432 ps
CPU time	116.86 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:30:00 PM PDT 24
Peak memory	190688 kb
Host	smart-6e2ae257-fed4-434a-982f-2b7179d5c093
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340500065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2340500065
Directory	/workspace/67.rv_timer_random/latest

Test location	/workspace/coverage/default/68.rv_timer_random.622416903
Short name	T22
Test name
Test status
Simulation time	191200219409 ps
CPU time	177.45 seconds
Started	Apr 16 12:27:55 PM PDT 24
Finished	Apr 16 12:30:55 PM PDT 24
Peak memory	190652 kb
Host	smart-6f49a54b-9a03-4a28-a411-08076e0314c7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622416903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.622416903
Directory	/workspace/68.rv_timer_random/latest

Test location	/workspace/coverage/default/7.rv_timer_disabled.1008038985
Short name	T357
Test name
Test status
Simulation time	213729300327 ps
CPU time	87.8 seconds
Started	Apr 16 12:27:09 PM PDT 24
Finished	Apr 16 12:28:43 PM PDT 24
Peak memory	182596 kb
Host	smart-76c44203-d881-4b13-8b5f-a6a1cbe4b214
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008038985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1008038985
Directory	/workspace/7.rv_timer_disabled/latest

Test location	/workspace/coverage/default/7.rv_timer_random_reset.3946015912
Short name	T387
Test name
Test status
Simulation time	51471521980 ps
CPU time	91.21 seconds
Started	Apr 16 12:27:20 PM PDT 24
Finished	Apr 16 12:28:56 PM PDT 24
Peak memory	190656 kb
Host	smart-bd1850be-0cf9-4d0e-a46d-f79383dc8d7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946015912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3946015912
Directory	/workspace/7.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1596297632
Short name	T43
Test name
Test status
Simulation time	53854204321 ps
CPU time	581.58 seconds
Started	Apr 16 12:27:15 PM PDT 24
Finished	Apr 16 12:37:02 PM PDT 24
Peak memory	207536 kb
Host	smart-5235c95b-e768-4b4a-9d8a-431ba158a93a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596297632 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1596297632
Directory	/workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/70.rv_timer_random.1002347177
Short name	T221
Test name
Test status
Simulation time	302015635362 ps
CPU time	1000.93 seconds
Started	Apr 16 12:27:54 PM PDT 24
Finished	Apr 16 12:44:38 PM PDT 24
Peak memory	190768 kb
Host	smart-4e17f308-9aae-403c-9b46-63c936e30194
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002347177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1002347177
Directory	/workspace/70.rv_timer_random/latest

Test location	/workspace/coverage/default/71.rv_timer_random.4122640902
Short name	T44
Test name
Test status
Simulation time	166752893096 ps
CPU time	156.14 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:30:40 PM PDT 24
Peak memory	190724 kb
Host	smart-d5ad8005-41b5-4680-b2ac-1dff87964d91
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122640902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.4122640902
Directory	/workspace/71.rv_timer_random/latest

Test location	/workspace/coverage/default/72.rv_timer_random.2649332916
Short name	T270
Test name
Test status
Simulation time	578524098729 ps
CPU time	440.2 seconds
Started	Apr 16 12:28:07 PM PDT 24
Finished	Apr 16 12:35:28 PM PDT 24
Peak memory	190652 kb
Host	smart-ebf6b29c-0cee-4570-afff-a04ba8a5f23c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649332916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2649332916
Directory	/workspace/72.rv_timer_random/latest

Test location	/workspace/coverage/default/73.rv_timer_random.1011760109
Short name	T148
Test name
Test status
Simulation time	385623063025 ps
CPU time	157.28 seconds
Started	Apr 16 12:27:58 PM PDT 24
Finished	Apr 16 12:30:37 PM PDT 24
Peak memory	190776 kb
Host	smart-c3566065-1108-4331-98fb-691d9c3ea97a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011760109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1011760109
Directory	/workspace/73.rv_timer_random/latest

Test location	/workspace/coverage/default/74.rv_timer_random.2714344073
Short name	T336
Test name
Test status
Simulation time	55959701035 ps
CPU time	1016.31 seconds
Started	Apr 16 12:27:55 PM PDT 24
Finished	Apr 16 12:44:54 PM PDT 24
Peak memory	190768 kb
Host	smart-70887861-da25-43eb-9711-26e6e1a07772
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714344073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2714344073
Directory	/workspace/74.rv_timer_random/latest

Test location	/workspace/coverage/default/75.rv_timer_random.1375105957
Short name	T390
Test name
Test status
Simulation time	23643324803 ps
CPU time	178.64 seconds
Started	Apr 16 12:27:57 PM PDT 24
Finished	Apr 16 12:30:58 PM PDT 24
Peak memory	190676 kb
Host	smart-da6b35af-7a08-4e82-b0e8-6aac2205f288
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375105957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1375105957
Directory	/workspace/75.rv_timer_random/latest

Test location	/workspace/coverage/default/77.rv_timer_random.533670915
Short name	T328
Test name
Test status
Simulation time	86559476630 ps
CPU time	316.49 seconds
Started	Apr 16 12:27:58 PM PDT 24
Finished	Apr 16 12:33:16 PM PDT 24
Peak memory	190768 kb
Host	smart-d7c32946-97a1-4082-8d7c-41dce23ca174
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533670915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.533670915
Directory	/workspace/77.rv_timer_random/latest

Test location	/workspace/coverage/default/78.rv_timer_random.74132607
Short name	T113
Test name
Test status
Simulation time	105522091633 ps
CPU time	331.1 seconds
Started	Apr 16 12:28:04 PM PDT 24
Finished	Apr 16 12:33:37 PM PDT 24
Peak memory	190780 kb
Host	smart-44efa35a-ab56-4b71-b230-6ecdb5b4d14a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74132607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.74132607
Directory	/workspace/78.rv_timer_random/latest

Test location	/workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3165955112
Short name	T318
Test name
Test status
Simulation time	9820690717 ps
CPU time	17.38 seconds
Started	Apr 16 12:27:13 PM PDT 24
Finished	Apr 16 12:27:36 PM PDT 24
Peak memory	182560 kb
Host	smart-f48e9f42-987a-407d-b96a-538c49cb6bfd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165955112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3165955112
Directory	/workspace/8.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/8.rv_timer_disabled.2018525488
Short name	T393
Test name
Test status
Simulation time	51129027042 ps
CPU time	78.15 seconds
Started	Apr 16 12:27:13 PM PDT 24
Finished	Apr 16 12:28:37 PM PDT 24
Peak memory	182524 kb
Host	smart-e4b9952e-c121-48df-b41f-ca1e88ba2840
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018525488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2018525488
Directory	/workspace/8.rv_timer_disabled/latest

Test location	/workspace/coverage/default/8.rv_timer_random.4268405930
Short name	T69
Test name
Test status
Simulation time	21955234803 ps
CPU time	45.67 seconds
Started	Apr 16 12:27:09 PM PDT 24
Finished	Apr 16 12:28:00 PM PDT 24
Peak memory	190696 kb
Host	smart-1b0e7290-1a63-4f23-9b8e-7154c580dbdb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268405930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.4268405930
Directory	/workspace/8.rv_timer_random/latest

Test location	/workspace/coverage/default/8.rv_timer_random_reset.637037209
Short name	T367
Test name
Test status
Simulation time	44799627 ps
CPU time	0.55 seconds
Started	Apr 16 12:27:19 PM PDT 24
Finished	Apr 16 12:27:24 PM PDT 24
Peak memory	182272 kb
Host	smart-8df49b96-53ba-4e4d-b8f6-c4bc9c637ecb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637037209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.637037209
Directory	/workspace/8.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/80.rv_timer_random.1648877403
Short name	T241
Test name
Test status
Simulation time	353815599347 ps
CPU time	64.01 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:29:07 PM PDT 24
Peak memory	190656 kb
Host	smart-14448ab2-d86f-471f-a4d2-54afa8b53c4d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648877403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1648877403
Directory	/workspace/80.rv_timer_random/latest

Test location	/workspace/coverage/default/82.rv_timer_random.2084236261
Short name	T310
Test name
Test status
Simulation time	113454287923 ps
CPU time	58.52 seconds
Started	Apr 16 12:27:57 PM PDT 24
Finished	Apr 16 12:28:57 PM PDT 24
Peak memory	182588 kb
Host	smart-3a313d1d-4086-4599-be94-97c4da386867
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084236261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2084236261
Directory	/workspace/82.rv_timer_random/latest

Test location	/workspace/coverage/default/83.rv_timer_random.2119103755
Short name	T255
Test name
Test status
Simulation time	165773640880 ps
CPU time	406.92 seconds
Started	Apr 16 12:28:05 PM PDT 24
Finished	Apr 16 12:34:54 PM PDT 24
Peak memory	190780 kb
Host	smart-6b08ec41-ceb9-4c28-bb2e-f9ed868f3835
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119103755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2119103755
Directory	/workspace/83.rv_timer_random/latest

Test location	/workspace/coverage/default/84.rv_timer_random.2038369724
Short name	T407
Test name
Test status
Simulation time	19897582292 ps
CPU time	109.57 seconds
Started	Apr 16 12:27:56 PM PDT 24
Finished	Apr 16 12:29:48 PM PDT 24
Peak memory	190680 kb
Host	smart-8c252ea4-5082-4640-858d-500c4499c9c7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038369724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2038369724
Directory	/workspace/84.rv_timer_random/latest

Test location	/workspace/coverage/default/85.rv_timer_random.923578682
Short name	T330
Test name
Test status
Simulation time	366754016307 ps
CPU time	159.5 seconds
Started	Apr 16 12:27:56 PM PDT 24
Finished	Apr 16 12:30:38 PM PDT 24
Peak memory	190672 kb
Host	smart-226b1257-e8bc-4ddc-8016-fd0947e03bd3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923578682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.923578682
Directory	/workspace/85.rv_timer_random/latest

Test location	/workspace/coverage/default/86.rv_timer_random.1986347377
Short name	T117
Test name
Test status
Simulation time	47908560881 ps
CPU time	61.58 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:29:05 PM PDT 24
Peak memory	182308 kb
Host	smart-1a3a4195-715f-418c-a873-73d0652309a5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986347377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1986347377
Directory	/workspace/86.rv_timer_random/latest

Test location	/workspace/coverage/default/87.rv_timer_random.4034617403
Short name	T265
Test name
Test status
Simulation time	115516345958 ps
CPU time	107.79 seconds
Started	Apr 16 12:28:00 PM PDT 24
Finished	Apr 16 12:29:49 PM PDT 24
Peak memory	190760 kb
Host	smart-9c6ef59e-44a5-468f-8da2-c77894d0b882
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034617403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.4034617403
Directory	/workspace/87.rv_timer_random/latest

Test location	/workspace/coverage/default/88.rv_timer_random.1237509930
Short name	T232
Test name
Test status
Simulation time	38774850322 ps
CPU time	158.32 seconds
Started	Apr 16 12:28:00 PM PDT 24
Finished	Apr 16 12:30:40 PM PDT 24
Peak memory	182456 kb
Host	smart-879b273a-1527-41b3-95ee-97930148f4fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237509930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1237509930
Directory	/workspace/88.rv_timer_random/latest

Test location	/workspace/coverage/default/89.rv_timer_random.8372666
Short name	T249
Test name
Test status
Simulation time	154266644478 ps
CPU time	87.97 seconds
Started	Apr 16 12:28:03 PM PDT 24
Finished	Apr 16 12:29:33 PM PDT 24
Peak memory	190788 kb
Host	smart-dde49328-88ed-4997-a8de-c1cbaab1d5ce
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8372666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.8372666
Directory	/workspace/89.rv_timer_random/latest

Test location	/workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1360822728
Short name	T395
Test name
Test status
Simulation time	595197451840 ps
CPU time	334.78 seconds
Started	Apr 16 12:27:09 PM PDT 24
Finished	Apr 16 12:32:50 PM PDT 24
Peak memory	182508 kb
Host	smart-e71052dd-b4d0-4ad3-af58-86921b2bce70
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360822728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.1360822728
Directory	/workspace/9.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/9.rv_timer_disabled.4198289312
Short name	T429
Test name
Test status
Simulation time	309095038667 ps
CPU time	134.35 seconds
Started	Apr 16 12:27:10 PM PDT 24
Finished	Apr 16 12:29:29 PM PDT 24
Peak memory	182468 kb
Host	smart-2e02f864-28fa-481c-a3be-82a008dd5370
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198289312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4198289312
Directory	/workspace/9.rv_timer_disabled/latest

Test location	/workspace/coverage/default/9.rv_timer_random_reset.3592806454
Short name	T411
Test name
Test status
Simulation time	47318311374 ps
CPU time	53.63 seconds
Started	Apr 16 12:27:21 PM PDT 24
Finished	Apr 16 12:28:19 PM PDT 24
Peak memory	190748 kb
Host	smart-702da26a-c164-49b4-abae-e4dd89aaf121
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592806454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3592806454
Directory	/workspace/9.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1584825813
Short name	T435
Test name
Test status
Simulation time	12621774837 ps
CPU time	106.32 seconds
Started	Apr 16 12:27:13 PM PDT 24
Finished	Apr 16 12:29:04 PM PDT 24
Peak memory	195200 kb
Host	smart-ab3246a7-81c3-49e5-8dc1-ed054eda1491
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584825813 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1584825813
Directory	/workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/91.rv_timer_random.548901660
Short name	T282
Test name
Test status
Simulation time	705107787932 ps
CPU time	885.32 seconds
Started	Apr 16 12:27:59 PM PDT 24
Finished	Apr 16 12:42:46 PM PDT 24
Peak memory	190748 kb
Host	smart-8c9e99ac-a47e-4d36-beb0-3542ed4119f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548901660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.548901660
Directory	/workspace/91.rv_timer_random/latest

Test location	/workspace/coverage/default/92.rv_timer_random.2435626182
Short name	T295
Test name
Test status
Simulation time	195534359254 ps
CPU time	304.91 seconds
Started	Apr 16 12:28:04 PM PDT 24
Finished	Apr 16 12:33:11 PM PDT 24
Peak memory	190784 kb
Host	smart-1afc48de-ca2a-4995-ab5c-7bf251df4985
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435626182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2435626182
Directory	/workspace/92.rv_timer_random/latest

Test location	/workspace/coverage/default/93.rv_timer_random.4243329933
Short name	T244
Test name
Test status
Simulation time	94745571367 ps
CPU time	169.79 seconds
Started	Apr 16 12:27:57 PM PDT 24
Finished	Apr 16 12:30:49 PM PDT 24
Peak memory	190548 kb
Host	smart-0fc0b87b-c2ea-464e-a39c-fa37f31a84d7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243329933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4243329933
Directory	/workspace/93.rv_timer_random/latest

Test location	/workspace/coverage/default/94.rv_timer_random.900875548
Short name	T277
Test name
Test status
Simulation time	97812499349 ps
CPU time	86.16 seconds
Started	Apr 16 12:28:02 PM PDT 24
Finished	Apr 16 12:29:31 PM PDT 24
Peak memory	182488 kb
Host	smart-d07b39d1-f851-49f7-b120-e8bbea25f0b9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900875548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.900875548
Directory	/workspace/94.rv_timer_random/latest

Test location	/workspace/coverage/default/95.rv_timer_random.2167804319
Short name	T161
Test name
Test status
Simulation time	61479638949 ps
CPU time	53.05 seconds
Started	Apr 16 12:27:59 PM PDT 24
Finished	Apr 16 12:28:53 PM PDT 24
Peak memory	190776 kb
Host	smart-c40be17f-7da0-4875-a436-dc070188a86d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167804319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2167804319
Directory	/workspace/95.rv_timer_random/latest

Test location	/workspace/coverage/default/96.rv_timer_random.906477788
Short name	T326
Test name
Test status
Simulation time	195352360495 ps
CPU time	885.4 seconds
Started	Apr 16 12:27:55 PM PDT 24
Finished	Apr 16 12:42:43 PM PDT 24
Peak memory	190600 kb
Host	smart-2ace6614-0b95-49b0-bb03-6274de47748d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906477788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.906477788
Directory	/workspace/96.rv_timer_random/latest

Test location	/workspace/coverage/default/97.rv_timer_random.1266790195
Short name	T291
Test name
Test status
Simulation time	81764825664 ps
CPU time	317.94 seconds
Started	Apr 16 12:27:54 PM PDT 24
Finished	Apr 16 12:33:15 PM PDT 24
Peak memory	190748 kb
Host	smart-070947ff-07a1-40bd-86d3-578cd37a7267
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266790195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1266790195
Directory	/workspace/97.rv_timer_random/latest

Test location	/workspace/coverage/default/98.rv_timer_random.1918914585
Short name	T194
Test name
Test status
Simulation time	649600599652 ps
CPU time	545.67 seconds
Started	Apr 16 12:28:01 PM PDT 24
Finished	Apr 16 12:37:09 PM PDT 24
Peak memory	190708 kb
Host	smart-dcdf308b-86c9-4f28-ba30-51dd19441e49
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918914585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1918914585
Directory	/workspace/98.rv_timer_random/latest

Test location	/workspace/coverage/default/99.rv_timer_random.635523320
Short name	T236
Test name
Test status
Simulation time	106021858006 ps
CPU time	202.95 seconds
Started	Apr 16 12:28:03 PM PDT 24
Finished	Apr 16 12:31:28 PM PDT 24
Peak memory	190776 kb
Host	smart-d1c112da-c1d8-4b60-85a8-93a4f2648351
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635523320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.635523320
Directory	/workspace/99.rv_timer_random/latest