Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.49 99.36 98.73 100.00 100.00 100.00 98.87


Total test records in report: 583
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1585602942 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:04 PM PDT 24 14220594 ps
T510 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.250476193 Apr 21 12:48:59 PM PDT 24 Apr 21 12:49:01 PM PDT 24 41966202 ps
T511 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2643720957 Apr 21 12:48:55 PM PDT 24 Apr 21 12:48:56 PM PDT 24 42026191 ps
T512 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.365647295 Apr 21 12:48:27 PM PDT 24 Apr 21 12:48:31 PM PDT 24 318644938 ps
T513 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2409274243 Apr 21 12:48:36 PM PDT 24 Apr 21 12:48:37 PM PDT 24 14676673 ps
T87 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3274521741 Apr 21 12:48:35 PM PDT 24 Apr 21 12:48:37 PM PDT 24 15570173 ps
T514 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1207089932 Apr 21 12:49:00 PM PDT 24 Apr 21 12:49:01 PM PDT 24 15237257 ps
T515 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.703261149 Apr 21 12:48:54 PM PDT 24 Apr 21 12:48:56 PM PDT 24 178871511 ps
T516 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2705930035 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:11 PM PDT 24 13657417 ps
T517 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1108711853 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:05 PM PDT 24 43046632 ps
T518 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1658433011 Apr 21 12:48:59 PM PDT 24 Apr 21 12:49:01 PM PDT 24 301651941 ps
T519 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1950303780 Apr 21 12:48:40 PM PDT 24 Apr 21 12:48:41 PM PDT 24 18289304 ps
T520 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1166270247 Apr 21 12:48:59 PM PDT 24 Apr 21 12:49:00 PM PDT 24 14492064 ps
T521 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.436117130 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:06 PM PDT 24 258006909 ps
T522 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3333502798 Apr 21 12:48:51 PM PDT 24 Apr 21 12:48:53 PM PDT 24 36689081 ps
T523 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.509089250 Apr 21 12:49:02 PM PDT 24 Apr 21 12:49:04 PM PDT 24 53036506 ps
T524 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3978873070 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:05 PM PDT 24 15438480 ps
T525 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3279513587 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:04 PM PDT 24 33042661 ps
T526 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2872668711 Apr 21 12:48:55 PM PDT 24 Apr 21 12:48:56 PM PDT 24 87866164 ps
T88 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2112723428 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:46 PM PDT 24 29978232 ps
T527 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3788283321 Apr 21 12:48:40 PM PDT 24 Apr 21 12:48:42 PM PDT 24 37272773 ps
T528 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4212525533 Apr 21 12:48:54 PM PDT 24 Apr 21 12:48:55 PM PDT 24 22182948 ps
T529 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.168963132 Apr 21 12:48:48 PM PDT 24 Apr 21 12:48:49 PM PDT 24 35537608 ps
T530 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1348517718 Apr 21 12:48:54 PM PDT 24 Apr 21 12:48:55 PM PDT 24 10701298 ps
T531 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2201984911 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:45 PM PDT 24 13423693 ps
T532 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.286169336 Apr 21 12:48:42 PM PDT 24 Apr 21 12:48:43 PM PDT 24 18160948 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3778317146 Apr 21 12:49:01 PM PDT 24 Apr 21 12:49:02 PM PDT 24 18090011 ps
T533 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2087072075 Apr 21 12:48:46 PM PDT 24 Apr 21 12:48:48 PM PDT 24 34005741 ps
T103 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1052413025 Apr 21 12:48:45 PM PDT 24 Apr 21 12:48:47 PM PDT 24 237888830 ps
T534 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3529374594 Apr 21 12:48:48 PM PDT 24 Apr 21 12:48:49 PM PDT 24 54135554 ps
T535 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1535442182 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:04 PM PDT 24 42312893 ps
T536 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3519010499 Apr 21 12:49:00 PM PDT 24 Apr 21 12:49:02 PM PDT 24 100884435 ps
T100 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3897565945 Apr 21 12:48:57 PM PDT 24 Apr 21 12:48:58 PM PDT 24 105069688 ps
T537 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4208374283 Apr 21 12:48:41 PM PDT 24 Apr 21 12:48:44 PM PDT 24 109957643 ps
T538 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1733903893 Apr 21 12:48:50 PM PDT 24 Apr 21 12:48:51 PM PDT 24 43251666 ps
T539 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2660592158 Apr 21 12:48:41 PM PDT 24 Apr 21 12:48:43 PM PDT 24 65532867 ps
T540 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3920296005 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:45 PM PDT 24 37634508 ps
T541 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3168205462 Apr 21 12:48:55 PM PDT 24 Apr 21 12:48:56 PM PDT 24 38287012 ps
T542 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3457229538 Apr 21 12:49:02 PM PDT 24 Apr 21 12:49:05 PM PDT 24 166761701 ps
T543 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1013298928 Apr 21 12:48:56 PM PDT 24 Apr 21 12:48:57 PM PDT 24 20893440 ps
T544 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2522378680 Apr 21 12:48:51 PM PDT 24 Apr 21 12:48:58 PM PDT 24 222745894 ps
T91 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.299845957 Apr 21 12:48:55 PM PDT 24 Apr 21 12:48:56 PM PDT 24 43369559 ps
T545 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1766680874 Apr 21 12:48:47 PM PDT 24 Apr 21 12:48:49 PM PDT 24 178757816 ps
T546 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4059479940 Apr 21 12:48:59 PM PDT 24 Apr 21 12:49:00 PM PDT 24 63072071 ps
T547 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1517415886 Apr 21 12:49:00 PM PDT 24 Apr 21 12:49:02 PM PDT 24 32396348 ps
T548 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1551695519 Apr 21 12:48:54 PM PDT 24 Apr 21 12:48:56 PM PDT 24 41443423 ps
T549 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2429604930 Apr 21 12:48:36 PM PDT 24 Apr 21 12:48:37 PM PDT 24 71862115 ps
T550 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1812883490 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:09 PM PDT 24 31910914 ps
T551 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2405572610 Apr 21 12:48:27 PM PDT 24 Apr 21 12:48:28 PM PDT 24 24158239 ps
T552 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1596825077 Apr 21 12:48:40 PM PDT 24 Apr 21 12:48:40 PM PDT 24 54519937 ps
T553 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.59496135 Apr 21 12:48:46 PM PDT 24 Apr 21 12:48:48 PM PDT 24 25535056 ps
T554 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1608952373 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:04 PM PDT 24 14600250 ps
T555 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3263621896 Apr 21 12:48:48 PM PDT 24 Apr 21 12:48:49 PM PDT 24 27512710 ps
T556 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.970232081 Apr 21 12:48:41 PM PDT 24 Apr 21 12:48:42 PM PDT 24 140521038 ps
T557 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3454856449 Apr 21 12:48:45 PM PDT 24 Apr 21 12:48:47 PM PDT 24 46339334 ps
T558 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.710553425 Apr 21 12:48:54 PM PDT 24 Apr 21 12:48:55 PM PDT 24 22131393 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2812381545 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:48 PM PDT 24 395607011 ps
T560 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3922304371 Apr 21 12:48:31 PM PDT 24 Apr 21 12:48:33 PM PDT 24 1618045898 ps
T561 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1758228911 Apr 21 12:48:49 PM PDT 24 Apr 21 12:48:50 PM PDT 24 29217440 ps
T562 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1031090121 Apr 21 12:48:49 PM PDT 24 Apr 21 12:48:50 PM PDT 24 48997034 ps
T563 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3732821305 Apr 21 12:48:56 PM PDT 24 Apr 21 12:48:57 PM PDT 24 14655844 ps
T564 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3269051593 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:09 PM PDT 24 53451620 ps
T565 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1717819274 Apr 21 12:48:59 PM PDT 24 Apr 21 12:49:00 PM PDT 24 126810085 ps
T566 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2016311364 Apr 21 12:48:42 PM PDT 24 Apr 21 12:48:43 PM PDT 24 42408812 ps
T567 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2855834232 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:46 PM PDT 24 72421777 ps
T568 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4280485830 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:08 PM PDT 24 34174051 ps
T569 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1557442963 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:10 PM PDT 24 24110836 ps
T570 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1062749856 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:45 PM PDT 24 53912492 ps
T571 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2627881626 Apr 21 12:48:56 PM PDT 24 Apr 21 12:48:58 PM PDT 24 18108395 ps
T572 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3831718711 Apr 21 12:48:57 PM PDT 24 Apr 21 12:48:58 PM PDT 24 34127175 ps
T573 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.703519357 Apr 21 12:48:57 PM PDT 24 Apr 21 12:48:58 PM PDT 24 99938202 ps
T574 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2169262986 Apr 21 12:49:06 PM PDT 24 Apr 21 12:49:08 PM PDT 24 81710089 ps
T90 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.540366793 Apr 21 12:48:54 PM PDT 24 Apr 21 12:48:58 PM PDT 24 1788608169 ps
T104 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3854359008 Apr 21 12:48:41 PM PDT 24 Apr 21 12:48:42 PM PDT 24 42395661 ps
T575 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2584799989 Apr 21 12:48:40 PM PDT 24 Apr 21 12:48:41 PM PDT 24 44003120 ps
T576 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.818727194 Apr 21 12:48:37 PM PDT 24 Apr 21 12:48:39 PM PDT 24 40728902 ps
T577 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1771801694 Apr 21 12:49:00 PM PDT 24 Apr 21 12:49:02 PM PDT 24 101815282 ps
T578 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1935568109 Apr 21 12:48:47 PM PDT 24 Apr 21 12:48:49 PM PDT 24 370432127 ps
T579 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1347757250 Apr 21 12:48:32 PM PDT 24 Apr 21 12:48:33 PM PDT 24 163489617 ps
T580 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1036681514 Apr 21 12:48:37 PM PDT 24 Apr 21 12:48:38 PM PDT 24 57207432 ps
T581 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3439209840 Apr 21 12:48:59 PM PDT 24 Apr 21 12:49:00 PM PDT 24 40534097 ps
T582 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2490795552 Apr 21 12:48:45 PM PDT 24 Apr 21 12:48:47 PM PDT 24 152734396 ps
T583 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1783335517 Apr 21 12:48:35 PM PDT 24 Apr 21 12:48:36 PM PDT 24 153338590 ps

Test location /workspace/coverage/default/26.rv_timer_stress_all.616056871
Short name T8
Test name
Test status
Simulation time 1977060292705 ps
CPU time 1866.15 seconds
Started Apr 21 02:30:24 PM PDT 24
Finished Apr 21 03:01:30 PM PDT 24
Peak memory 190884 kb
Host smart-9fb296b2-0da2-4919-a2cc-efcb4265a0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616056871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
616056871
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.1747444698
Short name T39
Test name
Test status
Simulation time 25259774783 ps
CPU time 167.5 seconds
Started Apr 21 02:28:44 PM PDT 24
Finished Apr 21 02:31:31 PM PDT 24
Peak memory 197268 kb
Host smart-3a67e7a4-17d5-469a-8f71-3b76b526fbc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747444698 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.1747444698
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.676746080
Short name T132
Test name
Test status
Simulation time 5940412413498 ps
CPU time 5391.68 seconds
Started Apr 21 02:32:02 PM PDT 24
Finished Apr 21 04:01:54 PM PDT 24
Peak memory 190876 kb
Host smart-6cc96ce9-afed-4c86-a3a8-78fcfe3607f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676746080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
676746080
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.807318382
Short name T28
Test name
Test status
Simulation time 95831453 ps
CPU time 1.18 seconds
Started Apr 21 12:48:36 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 195220 kb
Host smart-335af7de-5312-4ef7-bc5b-729e867a03b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807318382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.807318382
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.164994319
Short name T111
Test name
Test status
Simulation time 601531733469 ps
CPU time 1907.38 seconds
Started Apr 21 02:28:54 PM PDT 24
Finished Apr 21 03:00:43 PM PDT 24
Peak memory 195496 kb
Host smart-52055966-c180-4de7-8dae-acb4c9816d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164994319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
164994319
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2247692095
Short name T172
Test name
Test status
Simulation time 1143076416971 ps
CPU time 6077.59 seconds
Started Apr 21 02:29:15 PM PDT 24
Finished Apr 21 04:10:34 PM PDT 24
Peak memory 190828 kb
Host smart-b89673bc-f310-48fc-9c48-1ab99ffbceba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247692095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2247692095
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2081081271
Short name T189
Test name
Test status
Simulation time 3744139530823 ps
CPU time 3367.44 seconds
Started Apr 21 02:31:28 PM PDT 24
Finished Apr 21 03:27:37 PM PDT 24
Peak memory 190856 kb
Host smart-7db2dbc9-a8ff-4023-9dac-69e2dcb67596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081081271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2081081271
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4241262013
Short name T34
Test name
Test status
Simulation time 522566448068 ps
CPU time 1189.43 seconds
Started Apr 21 02:29:50 PM PDT 24
Finished Apr 21 02:49:40 PM PDT 24
Peak memory 195032 kb
Host smart-9f7feb44-716e-47d3-adba-f8b0d8580435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241262013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4241262013
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.368816912
Short name T198
Test name
Test status
Simulation time 780332030366 ps
CPU time 1689.04 seconds
Started Apr 21 02:33:08 PM PDT 24
Finished Apr 21 03:01:18 PM PDT 24
Peak memory 195196 kb
Host smart-3cb99dbb-d77b-40c2-bb8a-75d554d04b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368816912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
368816912
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.818229583
Short name T212
Test name
Test status
Simulation time 2023316605023 ps
CPU time 2293.77 seconds
Started Apr 21 02:32:03 PM PDT 24
Finished Apr 21 03:10:18 PM PDT 24
Peak memory 190852 kb
Host smart-5d711e70-9727-4ba0-b3a0-c89e93672c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818229583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
818229583
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/76.rv_timer_random.3429007155
Short name T67
Test name
Test status
Simulation time 445596911163 ps
CPU time 262.23 seconds
Started Apr 21 02:33:38 PM PDT 24
Finished Apr 21 02:38:01 PM PDT 24
Peak memory 190852 kb
Host smart-30ee5f48-0250-42e6-b2fc-59bbdc9319d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429007155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3429007155
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3610326555
Short name T59
Test name
Test status
Simulation time 2620505806539 ps
CPU time 1601.22 seconds
Started Apr 21 02:29:05 PM PDT 24
Finished Apr 21 02:55:47 PM PDT 24
Peak memory 190888 kb
Host smart-8be6b88b-54f8-48c7-a9cd-b51aea321ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610326555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3610326555
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3021800631
Short name T14
Test name
Test status
Simulation time 241089102 ps
CPU time 0.88 seconds
Started Apr 21 02:28:14 PM PDT 24
Finished Apr 21 02:28:15 PM PDT 24
Peak memory 214236 kb
Host smart-bd19385b-b403-45c5-aee9-9eeb2db0832d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021800631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3021800631
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2482262995
Short name T221
Test name
Test status
Simulation time 426570899947 ps
CPU time 1735.64 seconds
Started Apr 21 02:31:31 PM PDT 24
Finished Apr 21 03:00:27 PM PDT 24
Peak memory 190852 kb
Host smart-c7e99df8-2eef-40de-ac97-189c5baecbb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482262995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2482262995
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.930805620
Short name T128
Test name
Test status
Simulation time 1193987282062 ps
CPU time 554.04 seconds
Started Apr 21 02:29:32 PM PDT 24
Finished Apr 21 02:38:46 PM PDT 24
Peak memory 190820 kb
Host smart-00542863-8309-44b8-b771-b698068a4fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930805620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
930805620
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2651265181
Short name T170
Test name
Test status
Simulation time 762370312105 ps
CPU time 3237.76 seconds
Started Apr 21 02:30:12 PM PDT 24
Finished Apr 21 03:24:11 PM PDT 24
Peak memory 190836 kb
Host smart-f55ff57e-0d29-42d4-958c-decc7febda3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651265181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2651265181
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2232515398
Short name T60
Test name
Test status
Simulation time 1566159490363 ps
CPU time 577.46 seconds
Started Apr 21 02:32:06 PM PDT 24
Finished Apr 21 02:41:44 PM PDT 24
Peak memory 190872 kb
Host smart-4be996db-ca09-483c-873c-92fe0d762804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232515398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2232515398
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_random.2838209815
Short name T217
Test name
Test status
Simulation time 200290418493 ps
CPU time 1793.4 seconds
Started Apr 21 02:28:42 PM PDT 24
Finished Apr 21 02:58:36 PM PDT 24
Peak memory 190796 kb
Host smart-68203305-c14a-4c45-bae9-fdfb74d35cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838209815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2838209815
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2388221266
Short name T312
Test name
Test status
Simulation time 6601457842224 ps
CPU time 1982.3 seconds
Started Apr 21 02:28:46 PM PDT 24
Finished Apr 21 03:01:49 PM PDT 24
Peak memory 194900 kb
Host smart-386bd3a3-a1cd-43d4-ad11-eb6ccd0fd939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388221266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2388221266
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/109.rv_timer_random.167188700
Short name T319
Test name
Test status
Simulation time 759934352697 ps
CPU time 415.89 seconds
Started Apr 21 02:34:20 PM PDT 24
Finished Apr 21 02:41:16 PM PDT 24
Peak memory 190872 kb
Host smart-c9a630a6-d5e8-4c9e-b337-3146b8851d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167188700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.167188700
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2721159539
Short name T326
Test name
Test status
Simulation time 200987609242 ps
CPU time 767.38 seconds
Started Apr 21 02:34:57 PM PDT 24
Finished Apr 21 02:47:45 PM PDT 24
Peak memory 190808 kb
Host smart-14f7d5ca-367d-4052-a799-076d1cae1eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721159539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2721159539
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random.3856488150
Short name T140
Test name
Test status
Simulation time 3347180795046 ps
CPU time 735.02 seconds
Started Apr 21 02:28:30 PM PDT 24
Finished Apr 21 02:40:45 PM PDT 24
Peak memory 190828 kb
Host smart-b0abb6de-bfae-4d8c-851b-126afa095fff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856488150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3856488150
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3398674160
Short name T187
Test name
Test status
Simulation time 567552442499 ps
CPU time 1105.7 seconds
Started Apr 21 02:32:40 PM PDT 24
Finished Apr 21 02:51:06 PM PDT 24
Peak memory 190812 kb
Host smart-a478aad5-92b7-4947-97e2-a133a4e2304e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398674160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3398674160
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.755334503
Short name T197
Test name
Test status
Simulation time 1689772467471 ps
CPU time 1100.04 seconds
Started Apr 21 02:32:37 PM PDT 24
Finished Apr 21 02:50:58 PM PDT 24
Peak memory 190880 kb
Host smart-a4488d09-aeb0-449a-8163-37dd436b6301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755334503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
755334503
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.774614630
Short name T105
Test name
Test status
Simulation time 1036437285881 ps
CPU time 539.32 seconds
Started Apr 21 02:28:50 PM PDT 24
Finished Apr 21 02:37:50 PM PDT 24
Peak memory 182632 kb
Host smart-9dcfb35b-0747-4601-a5ef-458df508c41a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774614630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.774614630
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/149.rv_timer_random.3982098430
Short name T167
Test name
Test status
Simulation time 105462397581 ps
CPU time 426 seconds
Started Apr 21 02:35:12 PM PDT 24
Finished Apr 21 02:42:19 PM PDT 24
Peak memory 190828 kb
Host smart-389d8364-8c8a-4b4d-896b-5596537ce86b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982098430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3982098430
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2713976153
Short name T288
Test name
Test status
Simulation time 423642970516 ps
CPU time 564.62 seconds
Started Apr 21 02:36:05 PM PDT 24
Finished Apr 21 02:45:30 PM PDT 24
Peak memory 190880 kb
Host smart-7bc3596f-e11b-43ed-921d-8c8abf373e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713976153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2713976153
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.581650144
Short name T245
Test name
Test status
Simulation time 724434404860 ps
CPU time 1093.71 seconds
Started Apr 21 02:28:28 PM PDT 24
Finished Apr 21 02:46:42 PM PDT 24
Peak memory 190820 kb
Host smart-3ef17614-d6a7-4361-8ed1-4f495e5254e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581650144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.581650144
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_random.1899015686
Short name T130
Test name
Test status
Simulation time 1459742458937 ps
CPU time 290.56 seconds
Started Apr 21 02:30:41 PM PDT 24
Finished Apr 21 02:35:32 PM PDT 24
Peak memory 190812 kb
Host smart-215955ac-e70b-49c8-9b51-c6b23e1d0692
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899015686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1899015686
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1910517951
Short name T85
Test name
Test status
Simulation time 40121252 ps
CPU time 0.59 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 182656 kb
Host smart-26ad2a4f-fb0d-4cf8-8867-5432b1442a16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910517951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1910517951
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/110.rv_timer_random.4198560325
Short name T143
Test name
Test status
Simulation time 103816627978 ps
CPU time 399.43 seconds
Started Apr 21 02:34:21 PM PDT 24
Finished Apr 21 02:41:00 PM PDT 24
Peak memory 190872 kb
Host smart-a6d3a415-c81e-4b38-98be-f90b6272ff9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198560325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4198560325
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1787256183
Short name T347
Test name
Test status
Simulation time 117820142420 ps
CPU time 899.06 seconds
Started Apr 21 02:34:35 PM PDT 24
Finished Apr 21 02:49:35 PM PDT 24
Peak memory 190868 kb
Host smart-b1b0c47e-5e9a-4dda-9374-47b49bd0d5be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787256183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1787256183
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1213819750
Short name T4
Test name
Test status
Simulation time 472592795273 ps
CPU time 388.5 seconds
Started Apr 21 02:35:07 PM PDT 24
Finished Apr 21 02:41:36 PM PDT 24
Peak memory 190860 kb
Host smart-343e7afa-75a9-47e6-9d5e-44f1bf0d6f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213819750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1213819750
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.565826740
Short name T153
Test name
Test status
Simulation time 885981527997 ps
CPU time 1846.95 seconds
Started Apr 21 02:35:16 PM PDT 24
Finished Apr 21 03:06:04 PM PDT 24
Peak memory 190832 kb
Host smart-86ecaf7b-c13a-47ba-9dc6-e60f756d2c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565826740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.565826740
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1001927951
Short name T107
Test name
Test status
Simulation time 264645934586 ps
CPU time 298.24 seconds
Started Apr 21 02:35:58 PM PDT 24
Finished Apr 21 02:40:57 PM PDT 24
Peak memory 190880 kb
Host smart-89d45152-4692-41d8-af46-82cf3bd57b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001927951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1001927951
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3998042237
Short name T115
Test name
Test status
Simulation time 89823539480 ps
CPU time 159.99 seconds
Started Apr 21 02:33:18 PM PDT 24
Finished Apr 21 02:35:59 PM PDT 24
Peak memory 190856 kb
Host smart-c703bb55-4a4a-4b82-8064-6a97f3f3f49a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998042237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3998042237
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1298791218
Short name T137
Test name
Test status
Simulation time 3652897100568 ps
CPU time 1186.47 seconds
Started Apr 21 02:28:13 PM PDT 24
Finished Apr 21 02:48:00 PM PDT 24
Peak memory 190888 kb
Host smart-a8283b34-e7c8-4a18-b31d-66bbd583f970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298791218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1298791218
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/117.rv_timer_random.1581768467
Short name T199
Test name
Test status
Simulation time 172538654696 ps
CPU time 266.62 seconds
Started Apr 21 02:34:29 PM PDT 24
Finished Apr 21 02:38:56 PM PDT 24
Peak memory 190872 kb
Host smart-52bcaa99-b88e-4aba-98e0-a7dbd05d95fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581768467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1581768467
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.755076775
Short name T207
Test name
Test status
Simulation time 320049058277 ps
CPU time 292.72 seconds
Started Apr 21 02:29:01 PM PDT 24
Finished Apr 21 02:33:54 PM PDT 24
Peak memory 182656 kb
Host smart-51c6f831-d4b3-4a4f-a62d-051c561bd0c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755076775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.755076775
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/189.rv_timer_random.253910834
Short name T5
Test name
Test status
Simulation time 178243194792 ps
CPU time 761.24 seconds
Started Apr 21 02:36:05 PM PDT 24
Finished Apr 21 02:48:46 PM PDT 24
Peak memory 190884 kb
Host smart-201a9ec6-3dd2-4887-b713-af7bf03b6340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253910834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.253910834
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.4103435440
Short name T204
Test name
Test status
Simulation time 1335792500667 ps
CPU time 676.03 seconds
Started Apr 21 02:30:00 PM PDT 24
Finished Apr 21 02:41:16 PM PDT 24
Peak memory 190880 kb
Host smart-d0978cc7-be65-427d-a434-ebdedb71cc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103435440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.4103435440
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1058084149
Short name T118
Test name
Test status
Simulation time 2250211296952 ps
CPU time 1230.13 seconds
Started Apr 21 02:30:34 PM PDT 24
Finished Apr 21 02:51:05 PM PDT 24
Peak memory 190760 kb
Host smart-901e91fc-f075-45dc-8b1c-ff41e572159a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058084149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1058084149
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3166188874
Short name T235
Test name
Test status
Simulation time 42024177818 ps
CPU time 64.01 seconds
Started Apr 21 02:32:34 PM PDT 24
Finished Apr 21 02:33:38 PM PDT 24
Peak memory 182644 kb
Host smart-9cd9ee30-1dee-4ae8-a66c-4a363d01bf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166188874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3166188874
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.456791715
Short name T182
Test name
Test status
Simulation time 626157639920 ps
CPU time 578.52 seconds
Started Apr 21 02:33:12 PM PDT 24
Finished Apr 21 02:42:52 PM PDT 24
Peak memory 190860 kb
Host smart-0d690afa-3487-47a6-b90a-9b759ea49e04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456791715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.456791715
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1616097903
Short name T146
Test name
Test status
Simulation time 376838492219 ps
CPU time 335.59 seconds
Started Apr 21 02:33:22 PM PDT 24
Finished Apr 21 02:38:57 PM PDT 24
Peak memory 190820 kb
Host smart-dee008ef-9966-4ece-9eb1-9db080e4bb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616097903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1616097903
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3561205401
Short name T177
Test name
Test status
Simulation time 630880195690 ps
CPU time 397.79 seconds
Started Apr 21 02:34:04 PM PDT 24
Finished Apr 21 02:40:42 PM PDT 24
Peak memory 190884 kb
Host smart-a9c766d7-2ec4-49d3-ad35-4a4b52ae8c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561205401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3561205401
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4061884389
Short name T237
Test name
Test status
Simulation time 98510566315 ps
CPU time 183.45 seconds
Started Apr 21 02:28:12 PM PDT 24
Finished Apr 21 02:31:15 PM PDT 24
Peak memory 182640 kb
Host smart-95065e24-775d-4fa4-b743-eb946bc7b28d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061884389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4061884389
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1997207400
Short name T121
Test name
Test status
Simulation time 166176176505 ps
CPU time 304.06 seconds
Started Apr 21 02:28:54 PM PDT 24
Finished Apr 21 02:33:59 PM PDT 24
Peak memory 182660 kb
Host smart-e38e60d1-817d-4558-9c2f-3eb5d7b54561
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997207400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1997207400
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2218115550
Short name T307
Test name
Test status
Simulation time 914461621519 ps
CPU time 504.64 seconds
Started Apr 21 02:28:59 PM PDT 24
Finished Apr 21 02:37:24 PM PDT 24
Peak memory 182624 kb
Host smart-92f4e72e-d571-4dbf-8a3a-148722ec2247
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218115550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2218115550
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/114.rv_timer_random.64291698
Short name T251
Test name
Test status
Simulation time 210844906904 ps
CPU time 623.31 seconds
Started Apr 21 02:34:27 PM PDT 24
Finished Apr 21 02:44:50 PM PDT 24
Peak memory 194384 kb
Host smart-5eafafa3-f882-4aec-b206-b52f3880070c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64291698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.64291698
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3952683690
Short name T161
Test name
Test status
Simulation time 186408424592 ps
CPU time 3088.66 seconds
Started Apr 21 02:34:28 PM PDT 24
Finished Apr 21 03:25:57 PM PDT 24
Peak memory 190872 kb
Host smart-ae8837c3-476a-4d17-b912-4cc642f22c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952683690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3952683690
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2874142832
Short name T27
Test name
Test status
Simulation time 102334456492 ps
CPU time 635.78 seconds
Started Apr 21 02:34:51 PM PDT 24
Finished Apr 21 02:45:27 PM PDT 24
Peak memory 190812 kb
Host smart-9d4e5af0-4f6d-4aa9-880c-5da73dd4bfad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874142832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2874142832
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3140054016
Short name T210
Test name
Test status
Simulation time 3326439217954 ps
CPU time 906.11 seconds
Started Apr 21 02:29:21 PM PDT 24
Finished Apr 21 02:44:27 PM PDT 24
Peak memory 182688 kb
Host smart-12162319-0d0b-48cf-a97c-87829fefd418
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140054016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3140054016
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_random.396820832
Short name T188
Test name
Test status
Simulation time 52190162587 ps
CPU time 231.62 seconds
Started Apr 21 02:29:19 PM PDT 24
Finished Apr 21 02:33:11 PM PDT 24
Peak memory 190796 kb
Host smart-5d9370f6-d5d0-46f2-a7df-f5f800d7e175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396820832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.396820832
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2233615553
Short name T20
Test name
Test status
Simulation time 121503714969 ps
CPU time 556.94 seconds
Started Apr 21 02:35:45 PM PDT 24
Finished Apr 21 02:45:03 PM PDT 24
Peak memory 190872 kb
Host smart-86f77e57-6520-4935-b7cb-f1d2d783637a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233615553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2233615553
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.366182996
Short name T147
Test name
Test status
Simulation time 584821364008 ps
CPU time 491.53 seconds
Started Apr 21 02:29:37 PM PDT 24
Finished Apr 21 02:37:49 PM PDT 24
Peak memory 190864 kb
Host smart-f6f2d975-0553-465d-88bd-8e419478042a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366182996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.366182996
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.2361763527
Short name T244
Test name
Test status
Simulation time 667040672193 ps
CPU time 1468.31 seconds
Started Apr 21 02:30:12 PM PDT 24
Finished Apr 21 02:54:41 PM PDT 24
Peak memory 190844 kb
Host smart-162964e3-45e4-4468-b2e5-7cc38701c681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361763527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2361763527
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2350308970
Short name T249
Test name
Test status
Simulation time 55068112871 ps
CPU time 191.62 seconds
Started Apr 21 02:33:12 PM PDT 24
Finished Apr 21 02:36:24 PM PDT 24
Peak memory 190820 kb
Host smart-878c05bb-b733-4b01-8675-1a801b7a49c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350308970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2350308970
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2210668810
Short name T255
Test name
Test status
Simulation time 161781726342 ps
CPU time 2525.7 seconds
Started Apr 21 02:34:16 PM PDT 24
Finished Apr 21 03:16:22 PM PDT 24
Peak memory 190840 kb
Host smart-f1aca4dd-61d5-41f1-aadb-d7bb7615bad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210668810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2210668810
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1384875343
Short name T353
Test name
Test status
Simulation time 852352212408 ps
CPU time 747.81 seconds
Started Apr 21 02:34:17 PM PDT 24
Finished Apr 21 02:46:45 PM PDT 24
Peak memory 190884 kb
Host smart-15394d8c-3474-4b4a-84db-2083acc43bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384875343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1384875343
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.315048623
Short name T184
Test name
Test status
Simulation time 251320090501 ps
CPU time 205 seconds
Started Apr 21 02:28:55 PM PDT 24
Finished Apr 21 02:32:20 PM PDT 24
Peak memory 190864 kb
Host smart-fa213889-8083-4988-9020-56144885db56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315048623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.315048623
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.4072954649
Short name T229
Test name
Test status
Simulation time 156068108486 ps
CPU time 297.72 seconds
Started Apr 21 02:29:02 PM PDT 24
Finished Apr 21 02:34:00 PM PDT 24
Peak memory 190880 kb
Host smart-fe2b55e9-1843-418e-8abf-4264ca02d8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072954649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4072954649
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2425994264
Short name T318
Test name
Test status
Simulation time 96998180252 ps
CPU time 366.81 seconds
Started Apr 21 02:34:47 PM PDT 24
Finished Apr 21 02:40:54 PM PDT 24
Peak memory 190844 kb
Host smart-8b626ee1-0638-499a-9dcf-1739a0c63569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425994264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2425994264
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2454472556
Short name T222
Test name
Test status
Simulation time 47673781290 ps
CPU time 75.5 seconds
Started Apr 21 02:35:13 PM PDT 24
Finished Apr 21 02:36:29 PM PDT 24
Peak memory 190820 kb
Host smart-93fcc0d2-472a-4079-b958-f5c7bc17de5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454472556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2454472556
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.618281241
Short name T77
Test name
Test status
Simulation time 613178533246 ps
CPU time 1195.83 seconds
Started Apr 21 02:36:00 PM PDT 24
Finished Apr 21 02:55:57 PM PDT 24
Peak memory 190812 kb
Host smart-b26f0bd2-d985-4ef0-ad70-92931dec9ed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618281241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.618281241
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1267030840
Short name T180
Test name
Test status
Simulation time 207210828527 ps
CPU time 454.67 seconds
Started Apr 21 02:36:06 PM PDT 24
Finished Apr 21 02:43:41 PM PDT 24
Peak memory 190888 kb
Host smart-3d6617e2-955b-45df-9506-f7d16febc360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267030840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1267030840
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2379761854
Short name T323
Test name
Test status
Simulation time 34317255292 ps
CPU time 28.77 seconds
Started Apr 21 02:36:11 PM PDT 24
Finished Apr 21 02:36:40 PM PDT 24
Peak memory 194368 kb
Host smart-03bf092c-cb82-48e4-b87b-06a684e3a739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379761854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2379761854
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3110472628
Short name T257
Test name
Test status
Simulation time 94808846916 ps
CPU time 157.61 seconds
Started Apr 21 02:31:22 PM PDT 24
Finished Apr 21 02:34:00 PM PDT 24
Peak memory 190868 kb
Host smart-12ce4b75-3a14-4d1b-8b74-ced5176a96aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110472628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3110472628
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1935867688
Short name T160
Test name
Test status
Simulation time 682713339529 ps
CPU time 381.82 seconds
Started Apr 21 02:32:48 PM PDT 24
Finished Apr 21 02:39:10 PM PDT 24
Peak memory 182684 kb
Host smart-09a0fa1e-9b35-4c61-bd58-a6f3295de0e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935867688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1935867688
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/99.rv_timer_random.3494012755
Short name T126
Test name
Test status
Simulation time 118714607723 ps
CPU time 215.99 seconds
Started Apr 21 02:34:10 PM PDT 24
Finished Apr 21 02:37:46 PM PDT 24
Peak memory 190896 kb
Host smart-4831c740-22b5-43ae-80bd-7b9dc95ddb05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494012755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3494012755
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1927461093
Short name T490
Test name
Test status
Simulation time 108135569 ps
CPU time 1.18 seconds
Started Apr 21 12:48:37 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 195308 kb
Host smart-e8c1c6bd-bf75-4035-8eb3-81a1ffe2ffea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927461093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1927461093
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1052413025
Short name T103
Test name
Test status
Simulation time 237888830 ps
CPU time 1.42 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:47 PM PDT 24
Peak memory 195360 kb
Host smart-759e2cc0-a311-41c3-bb73-3e42d59ec54f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052413025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1052413025
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.1335918923
Short name T158
Test name
Test status
Simulation time 144981561169 ps
CPU time 276.77 seconds
Started Apr 21 02:28:09 PM PDT 24
Finished Apr 21 02:32:46 PM PDT 24
Peak memory 190876 kb
Host smart-caf49368-175d-4a03-954d-e96a0dc9a614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335918923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1335918923
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3836164305
Short name T194
Test name
Test status
Simulation time 389331467765 ps
CPU time 949.94 seconds
Started Apr 21 02:28:10 PM PDT 24
Finished Apr 21 02:44:00 PM PDT 24
Peak memory 190888 kb
Host smart-35b7ff4e-71e2-40f3-a299-bd6de6f9b90b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836164305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3836164305
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2766636783
Short name T339
Test name
Test status
Simulation time 5848015838 ps
CPU time 11.2 seconds
Started Apr 21 02:28:13 PM PDT 24
Finished Apr 21 02:28:25 PM PDT 24
Peak memory 182648 kb
Host smart-36a9852a-e9fa-4764-bcb1-eea8b7e0456a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766636783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2766636783
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.182903798
Short name T332
Test name
Test status
Simulation time 43968016658 ps
CPU time 352.97 seconds
Started Apr 21 02:28:11 PM PDT 24
Finished Apr 21 02:34:04 PM PDT 24
Peak memory 190792 kb
Host smart-91f369e0-dd14-4a06-b44c-9830ad1e936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182903798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.182903798
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1708842263
Short name T286
Test name
Test status
Simulation time 589867966044 ps
CPU time 290.96 seconds
Started Apr 21 02:28:55 PM PDT 24
Finished Apr 21 02:33:46 PM PDT 24
Peak memory 194540 kb
Host smart-a83897e8-1860-47df-a0d5-653496ed9d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708842263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1708842263
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/104.rv_timer_random.1804549339
Short name T290
Test name
Test status
Simulation time 143479000748 ps
CPU time 533.99 seconds
Started Apr 21 02:34:16 PM PDT 24
Finished Apr 21 02:43:11 PM PDT 24
Peak memory 190804 kb
Host smart-ab67bb2e-6192-4b1f-a812-54071080dd76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804549339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1804549339
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.3577371399
Short name T205
Test name
Test status
Simulation time 4146700115 ps
CPU time 10.01 seconds
Started Apr 21 02:34:32 PM PDT 24
Finished Apr 21 02:34:43 PM PDT 24
Peak memory 182648 kb
Host smart-86b002b4-1c03-4d01-ba14-d20563b3cc70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577371399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3577371399
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.723319287
Short name T254
Test name
Test status
Simulation time 266305548574 ps
CPU time 269.09 seconds
Started Apr 21 02:29:36 PM PDT 24
Finished Apr 21 02:34:05 PM PDT 24
Peak memory 191036 kb
Host smart-e83750ba-0722-4b58-a59d-0f33f48c4b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723319287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
723319287
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/137.rv_timer_random.2592185892
Short name T291
Test name
Test status
Simulation time 143910697407 ps
CPU time 963.49 seconds
Started Apr 21 02:34:50 PM PDT 24
Finished Apr 21 02:50:54 PM PDT 24
Peak memory 191028 kb
Host smart-228c34f2-2fc1-424a-b8aa-5843addb8a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592185892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2592185892
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2295216050
Short name T109
Test name
Test status
Simulation time 49381459079 ps
CPU time 140.01 seconds
Started Apr 21 02:34:54 PM PDT 24
Finished Apr 21 02:37:14 PM PDT 24
Peak memory 190872 kb
Host smart-07f9db40-a872-4850-8081-25bd392e26db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295216050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2295216050
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3080623647
Short name T141
Test name
Test status
Simulation time 159247405499 ps
CPU time 70.57 seconds
Started Apr 21 02:34:55 PM PDT 24
Finished Apr 21 02:36:06 PM PDT 24
Peak memory 194520 kb
Host smart-b77c645a-edf3-40f2-bf9a-b0a509262a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080623647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3080623647
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2319041887
Short name T310
Test name
Test status
Simulation time 1458236702352 ps
CPU time 581.6 seconds
Started Apr 21 02:29:12 PM PDT 24
Finished Apr 21 02:38:54 PM PDT 24
Peak memory 182684 kb
Host smart-58ec8b58-0b93-4c85-ad5c-d1a90f55cc7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319041887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2319041887
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3319376914
Short name T295
Test name
Test status
Simulation time 751663950554 ps
CPU time 420.25 seconds
Started Apr 21 02:29:18 PM PDT 24
Finished Apr 21 02:36:19 PM PDT 24
Peak memory 190852 kb
Host smart-93ab116c-6576-4de5-aee8-1845ba62a67d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319376914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3319376914
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/165.rv_timer_random.4017188803
Short name T299
Test name
Test status
Simulation time 112824595283 ps
CPU time 1003.18 seconds
Started Apr 21 02:35:37 PM PDT 24
Finished Apr 21 02:52:21 PM PDT 24
Peak memory 190880 kb
Host smart-9f196e67-6427-489d-b9aa-86b93e94f310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017188803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4017188803
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1058350179
Short name T248
Test name
Test status
Simulation time 144064006967 ps
CPU time 349.96 seconds
Started Apr 21 02:35:45 PM PDT 24
Finished Apr 21 02:41:35 PM PDT 24
Peak memory 190800 kb
Host smart-cf3de129-a212-49d0-a6a7-189e848e041f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058350179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1058350179
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3119964887
Short name T45
Test name
Test status
Simulation time 103051659272 ps
CPU time 195.24 seconds
Started Apr 21 02:35:47 PM PDT 24
Finished Apr 21 02:39:02 PM PDT 24
Peak memory 190844 kb
Host smart-aecd131e-3e29-41ef-994c-df9ca79480e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119964887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3119964887
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3268219494
Short name T169
Test name
Test status
Simulation time 127602891515 ps
CPU time 62.41 seconds
Started Apr 21 02:29:34 PM PDT 24
Finished Apr 21 02:30:37 PM PDT 24
Peak memory 190872 kb
Host smart-f335b138-ed48-4c56-b286-9d38943dcac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268219494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3268219494
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.353313535
Short name T246
Test name
Test status
Simulation time 239050054056 ps
CPU time 396.16 seconds
Started Apr 21 02:29:41 PM PDT 24
Finished Apr 21 02:36:17 PM PDT 24
Peak memory 182672 kb
Host smart-b0aa590c-4f3e-4e4e-b028-10d854433238
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353313535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.353313535
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.637461199
Short name T240
Test name
Test status
Simulation time 2787545449890 ps
CPU time 1593.99 seconds
Started Apr 21 02:29:44 PM PDT 24
Finished Apr 21 02:56:19 PM PDT 24
Peak memory 195340 kb
Host smart-3312bdb6-79c9-4f71-bd61-675b4281930b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637461199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
637461199
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/198.rv_timer_random.1802424225
Short name T281
Test name
Test status
Simulation time 165053249142 ps
CPU time 454.04 seconds
Started Apr 21 02:36:21 PM PDT 24
Finished Apr 21 02:43:56 PM PDT 24
Peak memory 190884 kb
Host smart-c69d2830-18cc-4774-b776-64e055e73d4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802424225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1802424225
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2333566063
Short name T350
Test name
Test status
Simulation time 195164285518 ps
CPU time 101.02 seconds
Started Apr 21 02:30:00 PM PDT 24
Finished Apr 21 02:31:41 PM PDT 24
Peak memory 182656 kb
Host smart-be984df8-f623-4c72-a54b-aefef60579bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333566063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2333566063
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.2324330948
Short name T219
Test name
Test status
Simulation time 2215057284140 ps
CPU time 685.43 seconds
Started Apr 21 02:29:59 PM PDT 24
Finished Apr 21 02:41:24 PM PDT 24
Peak memory 190872 kb
Host smart-f66d978e-edf8-4ef2-ad31-04397d0d6ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324330948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2324330948
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.602915092
Short name T358
Test name
Test status
Simulation time 797417542542 ps
CPU time 713.15 seconds
Started Apr 21 02:28:24 PM PDT 24
Finished Apr 21 02:40:18 PM PDT 24
Peak memory 182688 kb
Host smart-9346eeda-2b2c-4408-a5c1-6ad8566701f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602915092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.602915092
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.420675028
Short name T164
Test name
Test status
Simulation time 77142984591 ps
CPU time 121.33 seconds
Started Apr 21 02:31:14 PM PDT 24
Finished Apr 21 02:33:15 PM PDT 24
Peak memory 182700 kb
Host smart-564b50c0-e7cf-4233-b82b-4d504f06dd85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420675028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.420675028
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.854269446
Short name T277
Test name
Test status
Simulation time 393817802848 ps
CPU time 1514.4 seconds
Started Apr 21 02:31:43 PM PDT 24
Finished Apr 21 02:56:58 PM PDT 24
Peak memory 193052 kb
Host smart-c2db9c6c-b27a-4ea7-88d7-9a318e329f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854269446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
854269446
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1574307994
Short name T220
Test name
Test status
Simulation time 120158436245 ps
CPU time 220.43 seconds
Started Apr 21 02:32:17 PM PDT 24
Finished Apr 21 02:35:58 PM PDT 24
Peak memory 182680 kb
Host smart-85daabc2-5b75-4e2a-ba64-6f80ebf48946
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574307994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1574307994
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1361929901
Short name T331
Test name
Test status
Simulation time 509302645874 ps
CPU time 485.01 seconds
Started Apr 21 02:32:38 PM PDT 24
Finished Apr 21 02:40:43 PM PDT 24
Peak memory 182648 kb
Host smart-d920cc98-b1d2-4839-ba25-49d26fa2381b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361929901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1361929901
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3210554508
Short name T193
Test name
Test status
Simulation time 107319962044 ps
CPU time 218.38 seconds
Started Apr 21 02:33:03 PM PDT 24
Finished Apr 21 02:36:42 PM PDT 24
Peak memory 190876 kb
Host smart-8f808679-fde3-483b-a0ab-23c5d463d065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210554508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3210554508
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3499404119
Short name T329
Test name
Test status
Simulation time 274364285291 ps
CPU time 129.68 seconds
Started Apr 21 02:33:13 PM PDT 24
Finished Apr 21 02:35:23 PM PDT 24
Peak memory 194484 kb
Host smart-7cdc9797-d00c-47ff-a8fc-ba8b8fb62d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499404119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3499404119
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/69.rv_timer_random.3793448016
Short name T327
Test name
Test status
Simulation time 371040373702 ps
CPU time 424.35 seconds
Started Apr 21 02:33:31 PM PDT 24
Finished Apr 21 02:40:35 PM PDT 24
Peak memory 194180 kb
Host smart-4830bc1a-863c-4483-8e48-d7bfaddc2918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793448016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3793448016
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2350159744
Short name T261
Test name
Test status
Simulation time 20938495783 ps
CPU time 26.72 seconds
Started Apr 21 02:33:44 PM PDT 24
Finished Apr 21 02:34:11 PM PDT 24
Peak memory 182632 kb
Host smart-85dcbb7f-c58e-4d17-a48c-84733523586a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350159744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2350159744
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3274521741
Short name T87
Test name
Test status
Simulation time 15570173 ps
CPU time 0.69 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 191892 kb
Host smart-5314eb1f-1b44-498c-91b7-0f4a7e81961a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274521741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3274521741
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3922304371
Short name T560
Test name
Test status
Simulation time 1618045898 ps
CPU time 1.55 seconds
Started Apr 21 12:48:31 PM PDT 24
Finished Apr 21 12:48:33 PM PDT 24
Peak memory 190952 kb
Host smart-ea3e295e-e7f8-41af-825c-09ce303a4356
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922304371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3922304371
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2407729284
Short name T98
Test name
Test status
Simulation time 34734587 ps
CPU time 0.6 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 182516 kb
Host smart-e3b6dc10-e913-457c-bd04-264c191af2a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407729284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2407729284
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3966605393
Short name T500
Test name
Test status
Simulation time 70085439 ps
CPU time 0.72 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:55 PM PDT 24
Peak memory 194988 kb
Host smart-bb4dba6d-f922-41c5-8ebc-31a256e4f751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966605393 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3966605393
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2405572610
Short name T551
Test name
Test status
Simulation time 24158239 ps
CPU time 0.58 seconds
Started Apr 21 12:48:27 PM PDT 24
Finished Apr 21 12:48:28 PM PDT 24
Peak memory 182708 kb
Host smart-797b6c73-51e3-4365-bbac-b575522868ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405572610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2405572610
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.154071529
Short name T491
Test name
Test status
Simulation time 18633233 ps
CPU time 0.58 seconds
Started Apr 21 12:48:29 PM PDT 24
Finished Apr 21 12:48:30 PM PDT 24
Peak memory 182532 kb
Host smart-e59655f2-7f1b-4d62-a292-8e3dc91cae8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154071529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.154071529
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2618936808
Short name T485
Test name
Test status
Simulation time 29136863 ps
CPU time 0.59 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 191896 kb
Host smart-c4cd7ed9-9778-4f32-a3a2-486fa882dc5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618936808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2618936808
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.365647295
Short name T512
Test name
Test status
Simulation time 318644938 ps
CPU time 3.03 seconds
Started Apr 21 12:48:27 PM PDT 24
Finished Apr 21 12:48:31 PM PDT 24
Peak memory 197432 kb
Host smart-bc99fbf5-b7f5-4ec2-9ed0-5b5f4c318a04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365647295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.365647295
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1347757250
Short name T579
Test name
Test status
Simulation time 163489617 ps
CPU time 0.65 seconds
Started Apr 21 12:48:32 PM PDT 24
Finished Apr 21 12:48:33 PM PDT 24
Peak memory 182640 kb
Host smart-46a9488e-6daa-4e6f-9b6d-207af1043dcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347757250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1347757250
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3788283321
Short name T527
Test name
Test status
Simulation time 37272773 ps
CPU time 1.45 seconds
Started Apr 21 12:48:40 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 191000 kb
Host smart-f44bd8a1-1a61-4389-9377-59fb0cbd6fd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788283321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3788283321
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1036681514
Short name T580
Test name
Test status
Simulation time 57207432 ps
CPU time 0.55 seconds
Started Apr 21 12:48:37 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 182192 kb
Host smart-c8a1de10-458f-4c5e-8b70-79707cb656a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036681514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1036681514
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3796940471
Short name T493
Test name
Test status
Simulation time 149098650 ps
CPU time 1.02 seconds
Started Apr 21 12:48:42 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 197308 kb
Host smart-66953dd4-8496-4f94-9a45-7cd9d016fe24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796940471 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3796940471
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1721689833
Short name T483
Test name
Test status
Simulation time 19507359 ps
CPU time 0.53 seconds
Started Apr 21 12:48:40 PM PDT 24
Finished Apr 21 12:48:40 PM PDT 24
Peak memory 182308 kb
Host smart-cd0711e1-b36b-4272-a60b-12fd895b23ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721689833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1721689833
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1596825077
Short name T552
Test name
Test status
Simulation time 54519937 ps
CPU time 0.53 seconds
Started Apr 21 12:48:40 PM PDT 24
Finished Apr 21 12:48:40 PM PDT 24
Peak memory 182212 kb
Host smart-6a0931d1-c21c-4b7c-91ad-8e7b4e63d63b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596825077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1596825077
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3968624079
Short name T94
Test name
Test status
Simulation time 94475206 ps
CPU time 0.68 seconds
Started Apr 21 12:48:43 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 192952 kb
Host smart-220f39fe-b78f-4bc9-ae81-599ef6307f28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968624079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3968624079
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2331203098
Short name T468
Test name
Test status
Simulation time 651660907 ps
CPU time 2.78 seconds
Started Apr 21 12:48:28 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 197532 kb
Host smart-fe399374-f8a0-426f-8003-95ed08b361b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331203098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2331203098
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2169083675
Short name T474
Test name
Test status
Simulation time 93197443 ps
CPU time 0.84 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 195388 kb
Host smart-6fdac4f4-6a17-4cd3-b327-a941037dfffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169083675 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2169083675
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.59496135
Short name T553
Test name
Test status
Simulation time 25535056 ps
CPU time 0.58 seconds
Started Apr 21 12:48:46 PM PDT 24
Finished Apr 21 12:48:48 PM PDT 24
Peak memory 182564 kb
Host smart-6c1c2e5e-070e-43d4-bb92-f0250a2e646c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59496135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.59496135
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3495382704
Short name T476
Test name
Test status
Simulation time 25098010 ps
CPU time 0.55 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:01 PM PDT 24
Peak memory 182496 kb
Host smart-923b06d0-1eca-4371-a03d-36545308a054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495382704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3495382704
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3904597574
Short name T74
Test name
Test status
Simulation time 31089733 ps
CPU time 0.74 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 191712 kb
Host smart-1bec9bd1-cf29-474b-917f-00b701e4f358
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904597574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3904597574
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4208374283
Short name T537
Test name
Test status
Simulation time 109957643 ps
CPU time 1.47 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 197580 kb
Host smart-7ff56119-4578-457c-85a0-e02ef538ded5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208374283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4208374283
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.703261149
Short name T515
Test name
Test status
Simulation time 178871511 ps
CPU time 1.11 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 195084 kb
Host smart-95d7e9d6-4475-4d1f-97c6-548d55903829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703261149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.703261149
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1517415886
Short name T547
Test name
Test status
Simulation time 32396348 ps
CPU time 0.86 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 197036 kb
Host smart-b4667360-2c8d-4305-8153-82a6d6a1a98f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517415886 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1517415886
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4145668115
Short name T496
Test name
Test status
Simulation time 24417691 ps
CPU time 0.6 seconds
Started Apr 21 12:48:52 PM PDT 24
Finished Apr 21 12:48:53 PM PDT 24
Peak memory 182572 kb
Host smart-71f37f80-52d5-4de1-b5cf-80bffb11739e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145668115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4145668115
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2681046151
Short name T452
Test name
Test status
Simulation time 14986992 ps
CPU time 0.58 seconds
Started Apr 21 12:48:49 PM PDT 24
Finished Apr 21 12:48:50 PM PDT 24
Peak memory 182548 kb
Host smart-97a59bbe-300b-4e93-a4bd-4039b966ca01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681046151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2681046151
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3263621896
Short name T555
Test name
Test status
Simulation time 27512710 ps
CPU time 0.66 seconds
Started Apr 21 12:48:48 PM PDT 24
Finished Apr 21 12:48:49 PM PDT 24
Peak memory 191592 kb
Host smart-85d541e9-0771-426c-adfc-8a461fad2344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263621896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3263621896
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3457229538
Short name T542
Test name
Test status
Simulation time 166761701 ps
CPU time 2.09 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 197508 kb
Host smart-6b2f9383-e933-4bc2-b591-81a21c13ca34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457229538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3457229538
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3334710333
Short name T99
Test name
Test status
Simulation time 160896300 ps
CPU time 1.09 seconds
Started Apr 21 12:48:49 PM PDT 24
Finished Apr 21 12:48:50 PM PDT 24
Peak memory 195036 kb
Host smart-17ff65e6-0a49-4f71-b635-71b63ef4eef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334710333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3334710333
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2855834232
Short name T567
Test name
Test status
Simulation time 72421777 ps
CPU time 0.91 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 197212 kb
Host smart-415584c9-eebe-40f5-a2e4-a82d6f279767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855834232 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2855834232
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3168205462
Short name T541
Test name
Test status
Simulation time 38287012 ps
CPU time 0.56 seconds
Started Apr 21 12:48:55 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 182436 kb
Host smart-32a50ba4-a49b-4922-8228-b6473fd38104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168205462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3168205462
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3759285964
Short name T492
Test name
Test status
Simulation time 13415200 ps
CPU time 0.57 seconds
Started Apr 21 12:48:57 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 182548 kb
Host smart-1faced8b-2393-4b6d-a2f5-92673bd1248d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759285964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3759285964
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2429604930
Short name T549
Test name
Test status
Simulation time 71862115 ps
CPU time 0.6 seconds
Started Apr 21 12:48:36 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 191948 kb
Host smart-7d591498-bc54-45ee-aaf9-eb9c3fd230ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429604930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2429604930
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2200166972
Short name T482
Test name
Test status
Simulation time 139062097 ps
CPU time 1.36 seconds
Started Apr 21 12:48:56 PM PDT 24
Finished Apr 21 12:48:57 PM PDT 24
Peak memory 197532 kb
Host smart-8432486f-7540-47d1-a74b-3e432888eea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200166972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2200166972
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3831244551
Short name T499
Test name
Test status
Simulation time 197286863 ps
CPU time 1.46 seconds
Started Apr 21 12:48:48 PM PDT 24
Finished Apr 21 12:48:50 PM PDT 24
Peak memory 195412 kb
Host smart-654c3950-c644-4524-b0cb-318967bc29a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831244551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3831244551
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.168963132
Short name T529
Test name
Test status
Simulation time 35537608 ps
CPU time 0.85 seconds
Started Apr 21 12:48:48 PM PDT 24
Finished Apr 21 12:48:49 PM PDT 24
Peak memory 196304 kb
Host smart-a4fcc60a-c3b5-4790-a1dc-537f4c96eda6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168963132 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.168963132
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1062749856
Short name T570
Test name
Test status
Simulation time 53912492 ps
CPU time 0.59 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:45 PM PDT 24
Peak memory 182672 kb
Host smart-222bd71f-3821-4546-8534-482ee97d6922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062749856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1062749856
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3213255387
Short name T462
Test name
Test status
Simulation time 14551425 ps
CPU time 0.57 seconds
Started Apr 21 12:48:48 PM PDT 24
Finished Apr 21 12:48:49 PM PDT 24
Peak memory 182496 kb
Host smart-35eb4f42-297f-4e08-9db3-354a766a8eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213255387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3213255387
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3529374594
Short name T534
Test name
Test status
Simulation time 54135554 ps
CPU time 0.73 seconds
Started Apr 21 12:48:48 PM PDT 24
Finished Apr 21 12:48:49 PM PDT 24
Peak memory 193000 kb
Host smart-b3bb58b4-5bc1-4203-944a-d5c995411507
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529374594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3529374594
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2169262986
Short name T574
Test name
Test status
Simulation time 81710089 ps
CPU time 1.63 seconds
Started Apr 21 12:49:06 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 197480 kb
Host smart-a39d237e-e863-4f4d-b125-93131dca84f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169262986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2169262986
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2440237124
Short name T465
Test name
Test status
Simulation time 172218227 ps
CPU time 0.85 seconds
Started Apr 21 12:48:50 PM PDT 24
Finished Apr 21 12:48:51 PM PDT 24
Peak memory 182932 kb
Host smart-f72bc4b6-7f23-4193-9b4e-b93d548903ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440237124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2440237124
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4244087930
Short name T32
Test name
Test status
Simulation time 116833272 ps
CPU time 0.86 seconds
Started Apr 21 12:48:51 PM PDT 24
Finished Apr 21 12:48:52 PM PDT 24
Peak memory 197264 kb
Host smart-ddddfd2e-024c-4150-bf3f-7875ddc0e88f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244087930 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4244087930
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3595890435
Short name T477
Test name
Test status
Simulation time 22498122 ps
CPU time 0.53 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:00 PM PDT 24
Peak memory 182220 kb
Host smart-952fc022-c0f4-44cb-8c97-97def986bf3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595890435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3595890435
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4212525533
Short name T528
Test name
Test status
Simulation time 22182948 ps
CPU time 0.52 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:55 PM PDT 24
Peak memory 182044 kb
Host smart-ac112d3e-9af0-494f-a161-92b2316c0ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212525533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4212525533
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1892973648
Short name T69
Test name
Test status
Simulation time 27907248 ps
CPU time 0.78 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:55 PM PDT 24
Peak memory 193344 kb
Host smart-332b5eed-19dc-4454-b1c5-e05235a0124b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892973648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1892973648
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2501470730
Short name T454
Test name
Test status
Simulation time 77792097 ps
CPU time 1.27 seconds
Started Apr 21 12:48:58 PM PDT 24
Finished Apr 21 12:48:59 PM PDT 24
Peak memory 197576 kb
Host smart-c5e75cce-7e9f-4133-98fa-f824a5a43f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501470730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2501470730
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1551695519
Short name T548
Test name
Test status
Simulation time 41443423 ps
CPU time 0.89 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 192668 kb
Host smart-e68e2bf7-1f2d-4b0a-8f10-df92d68b06cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551695519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1551695519
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1658433011
Short name T518
Test name
Test status
Simulation time 301651941 ps
CPU time 0.87 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:01 PM PDT 24
Peak memory 197156 kb
Host smart-991292a4-b91f-45fc-b863-dd007432e247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658433011 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1658433011
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2823569495
Short name T488
Test name
Test status
Simulation time 19923243 ps
CPU time 0.56 seconds
Started Apr 21 12:48:43 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 182380 kb
Host smart-edb5d964-cc0a-49f0-adba-eecc19b4f15a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823569495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2823569495
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2627881626
Short name T571
Test name
Test status
Simulation time 18108395 ps
CPU time 0.58 seconds
Started Apr 21 12:48:56 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 182596 kb
Host smart-50f8592f-4375-424d-81cf-6fabda157867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627881626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2627881626
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3192190925
Short name T71
Test name
Test status
Simulation time 78419365 ps
CPU time 0.7 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:52 PM PDT 24
Peak memory 191696 kb
Host smart-f9622acc-2619-4917-94d2-d6a2e7d033e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192190925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3192190925
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2825537806
Short name T504
Test name
Test status
Simulation time 42013815 ps
CPU time 2.07 seconds
Started Apr 21 12:48:56 PM PDT 24
Finished Apr 21 12:48:59 PM PDT 24
Peak memory 197476 kb
Host smart-28d062b3-183c-46e8-9219-c44885193308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825537806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2825537806
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1733903893
Short name T538
Test name
Test status
Simulation time 43251666 ps
CPU time 0.81 seconds
Started Apr 21 12:48:50 PM PDT 24
Finished Apr 21 12:48:51 PM PDT 24
Peak memory 183048 kb
Host smart-6de9a468-0a27-416b-83ad-acd9746d36c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733903893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1733903893
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.876320653
Short name T478
Test name
Test status
Simulation time 18379051 ps
CPU time 0.78 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 196064 kb
Host smart-23bcf445-f3b8-4dcf-9ce5-d490597866c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876320653 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.876320653
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.590982333
Short name T53
Test name
Test status
Simulation time 30916086 ps
CPU time 0.61 seconds
Started Apr 21 12:48:56 PM PDT 24
Finished Apr 21 12:48:57 PM PDT 24
Peak memory 182640 kb
Host smart-ee1a2540-7b4c-4c89-91d7-2e4bd71d5137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590982333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.590982333
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1166270247
Short name T520
Test name
Test status
Simulation time 14492064 ps
CPU time 0.56 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:00 PM PDT 24
Peak memory 182036 kb
Host smart-3973043c-3d09-44d0-8284-67cce20e3034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166270247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1166270247
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1207089932
Short name T514
Test name
Test status
Simulation time 15237257 ps
CPU time 0.67 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:01 PM PDT 24
Peak memory 191960 kb
Host smart-ddbd3949-eaf2-4eaf-ab84-c3d3d2c60ece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207089932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1207089932
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2522378680
Short name T544
Test name
Test status
Simulation time 222745894 ps
CPU time 1.89 seconds
Started Apr 21 12:48:51 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 197552 kb
Host smart-aaa44c51-ec52-4f8c-9ebe-021f60b8220d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522378680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2522378680
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3897565945
Short name T100
Test name
Test status
Simulation time 105069688 ps
CPU time 0.85 seconds
Started Apr 21 12:48:57 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 183128 kb
Host smart-8659bdd2-e4b9-42e4-94f8-3b90058a4068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897565945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3897565945
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2359406373
Short name T471
Test name
Test status
Simulation time 56025831 ps
CPU time 0.63 seconds
Started Apr 21 12:48:55 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 192688 kb
Host smart-d2e5224b-4e21-4937-bdbe-b0d0d12065c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359406373 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2359406373
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3475187419
Short name T484
Test name
Test status
Simulation time 13088356 ps
CPU time 0.56 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:55 PM PDT 24
Peak memory 182672 kb
Host smart-eb1a7ef8-37b8-4398-a1a3-80f92784e0e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475187419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3475187419
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4280485830
Short name T568
Test name
Test status
Simulation time 34174051 ps
CPU time 0.54 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 182552 kb
Host smart-76738cb7-1ad0-4c81-8fad-9d8b6d5adbac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280485830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4280485830
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1480568261
Short name T495
Test name
Test status
Simulation time 21368751 ps
CPU time 0.67 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 191576 kb
Host smart-55a1257b-ef02-4d6f-868f-15e7946fcef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480568261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1480568261
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1289102358
Short name T475
Test name
Test status
Simulation time 123790094 ps
CPU time 1.76 seconds
Started Apr 21 12:48:57 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 197552 kb
Host smart-28b791c7-a8f1-427e-86f2-19412b5a4531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289102358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1289102358
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.4032111275
Short name T102
Test name
Test status
Simulation time 264315039 ps
CPU time 1.41 seconds
Started Apr 21 12:48:53 PM PDT 24
Finished Apr 21 12:48:54 PM PDT 24
Peak memory 195340 kb
Host smart-b64c30d7-1837-4c59-82a2-6051c38d1dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032111275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.4032111275
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.760706136
Short name T33
Test name
Test status
Simulation time 18486792 ps
CPU time 0.8 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:01 PM PDT 24
Peak memory 195800 kb
Host smart-32a9dd92-a371-497d-9b92-fb885541d2b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760706136 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.760706136
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3439209840
Short name T581
Test name
Test status
Simulation time 40534097 ps
CPU time 0.63 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:00 PM PDT 24
Peak memory 182664 kb
Host smart-f18e61bc-2c68-44ee-b8bc-ddfbf7421560
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439209840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3439209840
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1031480909
Short name T507
Test name
Test status
Simulation time 24931816 ps
CPU time 0.57 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 182584 kb
Host smart-2b349f27-c36a-4947-8110-800182cbff3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031480909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1031480909
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.228779930
Short name T92
Test name
Test status
Simulation time 46520652 ps
CPU time 0.7 seconds
Started Apr 21 12:48:55 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 191500 kb
Host smart-b4231670-2881-4432-9817-f8c373d7e08b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228779930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.228779930
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2682961394
Short name T459
Test name
Test status
Simulation time 57818513 ps
CPU time 1.62 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 197500 kb
Host smart-c6c6379f-7535-4efe-a6ae-fc1292720f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682961394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2682961394
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1717819274
Short name T565
Test name
Test status
Simulation time 126810085 ps
CPU time 1.14 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:00 PM PDT 24
Peak memory 194936 kb
Host smart-dbfda5a2-0018-40d7-9d60-a2bb0523928a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717819274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1717819274
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3269051593
Short name T564
Test name
Test status
Simulation time 53451620 ps
CPU time 0.62 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 193192 kb
Host smart-f6e94e56-a88b-4305-9af7-86bda71e1d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269051593 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3269051593
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3752333379
Short name T31
Test name
Test status
Simulation time 20043085 ps
CPU time 0.58 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 182604 kb
Host smart-4fbf76f7-cdc0-4882-906b-46b9831545d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752333379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3752333379
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.454532495
Short name T486
Test name
Test status
Simulation time 50846638 ps
CPU time 0.57 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:55 PM PDT 24
Peak memory 182460 kb
Host smart-a9a4212f-7c3d-4145-b667-cd4a1932a405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454532495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.454532495
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4059479940
Short name T546
Test name
Test status
Simulation time 63072071 ps
CPU time 0.62 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:00 PM PDT 24
Peak memory 191304 kb
Host smart-3f330b94-a895-4022-84e4-05d8a07263dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059479940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4059479940
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3519010499
Short name T536
Test name
Test status
Simulation time 100884435 ps
CPU time 1.31 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 196976 kb
Host smart-83befaab-ed3e-46af-a43a-0c5c674ff7ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519010499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3519010499
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1771801694
Short name T577
Test name
Test status
Simulation time 101815282 ps
CPU time 1.36 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 195364 kb
Host smart-8489b14a-f0eb-4bcc-a5bd-e1c7c32645c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771801694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1771801694
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2847083861
Short name T73
Test name
Test status
Simulation time 54755870 ps
CPU time 0.71 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:36 PM PDT 24
Peak memory 191876 kb
Host smart-fd7a5c88-39c3-4a78-af8c-549372edcbaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847083861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2847083861
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.540366793
Short name T90
Test name
Test status
Simulation time 1788608169 ps
CPU time 3.81 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 192496 kb
Host smart-6d4f703b-8056-4a42-9506-0715bb393309
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540366793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.540366793
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.299845957
Short name T91
Test name
Test status
Simulation time 43369559 ps
CPU time 0.58 seconds
Started Apr 21 12:48:55 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 191832 kb
Host smart-f66d0b6f-f28d-4967-a27b-4d220e7601fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299845957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.299845957
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2169950727
Short name T52
Test name
Test status
Simulation time 233074298 ps
CPU time 1.01 seconds
Started Apr 21 12:48:34 PM PDT 24
Finished Apr 21 12:48:36 PM PDT 24
Peak memory 197204 kb
Host smart-aa918a02-312f-466c-ac41-64dfdab8ff40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169950727 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2169950727
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3778317146
Short name T89
Test name
Test status
Simulation time 18090011 ps
CPU time 0.56 seconds
Started Apr 21 12:49:01 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 182184 kb
Host smart-8ac54277-230a-4ae6-9598-d544d7ff26d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778317146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3778317146
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3333502798
Short name T522
Test name
Test status
Simulation time 36689081 ps
CPU time 0.56 seconds
Started Apr 21 12:48:51 PM PDT 24
Finished Apr 21 12:48:53 PM PDT 24
Peak memory 182232 kb
Host smart-3e8645d9-b394-4ce7-b094-fbf083921334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333502798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3333502798
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1045935600
Short name T72
Test name
Test status
Simulation time 38203864 ps
CPU time 0.59 seconds
Started Apr 21 12:48:42 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 190952 kb
Host smart-35a3dd7b-c756-4d1b-824a-4f1187158f63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045935600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1045935600
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1935568109
Short name T578
Test name
Test status
Simulation time 370432127 ps
CPU time 1.17 seconds
Started Apr 21 12:48:47 PM PDT 24
Finished Apr 21 12:48:49 PM PDT 24
Peak memory 197452 kb
Host smart-9056a6c7-0013-4e8b-95dd-4438159f300e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935568109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1935568109
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2490795552
Short name T582
Test name
Test status
Simulation time 152734396 ps
CPU time 0.81 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:47 PM PDT 24
Peak memory 192768 kb
Host smart-84c9a587-9e23-422f-bf14-e59bfb476c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490795552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2490795552
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1557442963
Short name T569
Test name
Test status
Simulation time 24110836 ps
CPU time 0.55 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 182488 kb
Host smart-700dada7-9d71-4d6e-82d2-1cd8f9d4e7a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557442963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1557442963
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1633594431
Short name T473
Test name
Test status
Simulation time 31813138 ps
CPU time 0.55 seconds
Started Apr 21 12:49:01 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 182476 kb
Host smart-324a8d19-7565-4068-8896-bb71e1d495ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633594431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1633594431
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1159307043
Short name T501
Test name
Test status
Simulation time 15407741 ps
CPU time 0.59 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:49:26 PM PDT 24
Peak memory 182476 kb
Host smart-79d6fa48-e768-4bfc-b097-76de167316a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159307043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1159307043
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3831718711
Short name T572
Test name
Test status
Simulation time 34127175 ps
CPU time 0.53 seconds
Started Apr 21 12:48:57 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 182160 kb
Host smart-91e098a4-d75c-484e-a464-71e2c644d0ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831718711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3831718711
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2478316060
Short name T456
Test name
Test status
Simulation time 101185898 ps
CPU time 0.62 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 182504 kb
Host smart-bf65d7c0-f0e1-4217-b64f-10c091a28d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478316060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2478316060
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1835945486
Short name T458
Test name
Test status
Simulation time 49333662 ps
CPU time 0.55 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 182488 kb
Host smart-aa843a42-cf11-4c0a-8e24-285029312930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835945486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1835945486
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1812883490
Short name T550
Test name
Test status
Simulation time 31910914 ps
CPU time 0.57 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 182460 kb
Host smart-fc12ca12-cb1f-467e-822e-27b7b856b7db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812883490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1812883490
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.4205803862
Short name T463
Test name
Test status
Simulation time 28724866 ps
CPU time 0.56 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 182548 kb
Host smart-7153fb23-707d-4776-a8a5-c9721eaa7076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205803862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.4205803862
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2642070154
Short name T457
Test name
Test status
Simulation time 24130347 ps
CPU time 0.55 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 182488 kb
Host smart-5ad40955-6144-4e33-ba7b-d915c158520c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642070154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2642070154
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1535442182
Short name T535
Test name
Test status
Simulation time 42312893 ps
CPU time 0.55 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 182596 kb
Host smart-8f0abfe1-ae0b-4524-9cab-609838d46873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535442182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1535442182
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.436117130
Short name T521
Test name
Test status
Simulation time 258006909 ps
CPU time 0.83 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 182632 kb
Host smart-9739490b-e3f4-4f69-88aa-d472456cbb3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436117130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.436117130
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2812381545
Short name T559
Test name
Test status
Simulation time 395607011 ps
CPU time 2.55 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:48 PM PDT 24
Peak memory 190912 kb
Host smart-316815c4-c8e2-43f3-973c-636ec76d8439
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812381545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2812381545
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3920296005
Short name T540
Test name
Test status
Simulation time 37634508 ps
CPU time 0.55 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:45 PM PDT 24
Peak memory 182688 kb
Host smart-47889feb-e75c-45cc-9301-0edd30102475
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920296005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3920296005
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1766680874
Short name T545
Test name
Test status
Simulation time 178757816 ps
CPU time 1.26 seconds
Started Apr 21 12:48:47 PM PDT 24
Finished Apr 21 12:48:49 PM PDT 24
Peak memory 197576 kb
Host smart-15b1ef3c-3bd8-402e-8f98-e701b7950414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766680874 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1766680874
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2450177790
Short name T479
Test name
Test status
Simulation time 44523719 ps
CPU time 0.58 seconds
Started Apr 21 12:49:01 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 182576 kb
Host smart-4b9b98a0-d2cf-4879-a325-c5f1e365b158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450177790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2450177790
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.703519357
Short name T573
Test name
Test status
Simulation time 99938202 ps
CPU time 0.8 seconds
Started Apr 21 12:48:57 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 193012 kb
Host smart-78bf3335-7c60-43da-a089-fe6e5325ce3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703519357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.703519357
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4145187593
Short name T498
Test name
Test status
Simulation time 162400577 ps
CPU time 1.59 seconds
Started Apr 21 12:48:37 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 197496 kb
Host smart-a4f4c026-c525-40db-afbc-a0245898335f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145187593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4145187593
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.513714990
Short name T481
Test name
Test status
Simulation time 81988708 ps
CPU time 0.54 seconds
Started Apr 21 12:49:01 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 182012 kb
Host smart-b0dd0669-7405-4f93-af35-386d598becf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513714990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.513714990
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2872668711
Short name T526
Test name
Test status
Simulation time 87866164 ps
CPU time 0.61 seconds
Started Apr 21 12:48:55 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 182544 kb
Host smart-9a8d30d5-8791-41d4-99fb-d756fa622d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872668711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2872668711
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1585602942
Short name T509
Test name
Test status
Simulation time 14220594 ps
CPU time 0.55 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 181984 kb
Host smart-4625ce80-9061-4cdb-ab16-a738aff4134b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585602942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1585602942
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1446958657
Short name T460
Test name
Test status
Simulation time 36665868 ps
CPU time 0.54 seconds
Started Apr 21 12:49:01 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 182208 kb
Host smart-3d9db2c4-b059-4162-a2e0-c1f6b2d0a35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446958657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1446958657
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.182520063
Short name T470
Test name
Test status
Simulation time 41119058 ps
CPU time 0.55 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:03 PM PDT 24
Peak memory 182212 kb
Host smart-4d81e002-313b-4794-81af-86c73ba6fda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182520063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.182520063
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2705930035
Short name T516
Test name
Test status
Simulation time 13657417 ps
CPU time 0.52 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:11 PM PDT 24
Peak memory 182020 kb
Host smart-6aba1de6-b568-4bb5-8f2a-80bbd97ed599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705930035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2705930035
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1960558298
Short name T472
Test name
Test status
Simulation time 14833599 ps
CPU time 0.55 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:00 PM PDT 24
Peak memory 182004 kb
Host smart-dbbd5ff2-4a14-46fa-a16a-dc90d2d1bd5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960558298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1960558298
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.466558441
Short name T467
Test name
Test status
Simulation time 55203306 ps
CPU time 0.57 seconds
Started Apr 21 12:48:58 PM PDT 24
Finished Apr 21 12:48:59 PM PDT 24
Peak memory 182472 kb
Host smart-7ce8fe0e-1d06-4bcb-9b5a-2ee62aad28b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466558441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.466558441
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.710553425
Short name T558
Test name
Test status
Simulation time 22131393 ps
CPU time 0.53 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:55 PM PDT 24
Peak memory 182012 kb
Host smart-6192411a-5e6f-456c-b4f6-d9d5f795e100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710553425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.710553425
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2263383676
Short name T480
Test name
Test status
Simulation time 52875880 ps
CPU time 0.61 seconds
Started Apr 21 12:49:16 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 182184 kb
Host smart-c8fd25bd-b93c-4bed-9659-31691e73479c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263383676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2263383676
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2112723428
Short name T88
Test name
Test status
Simulation time 29978232 ps
CPU time 0.79 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 192444 kb
Host smart-c0dcc2f8-852b-40a0-a6c9-c1b4adfd36d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112723428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2112723428
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2793640444
Short name T84
Test name
Test status
Simulation time 1700082365 ps
CPU time 3.6 seconds
Started Apr 21 12:48:49 PM PDT 24
Finished Apr 21 12:48:53 PM PDT 24
Peak memory 192396 kb
Host smart-7741f6f1-f940-479e-802a-5d222bcb3fc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793640444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2793640444
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.444587800
Short name T505
Test name
Test status
Simulation time 18654520 ps
CPU time 0.58 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 182512 kb
Host smart-e9af09ed-32d9-4c09-b63f-b5ba98712903
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444587800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.444587800
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.250476193
Short name T510
Test name
Test status
Simulation time 41966202 ps
CPU time 0.6 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:01 PM PDT 24
Peak memory 192828 kb
Host smart-30af79ee-fad5-44c5-b8ff-272cb31349c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250476193 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.250476193
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2409274243
Short name T513
Test name
Test status
Simulation time 14676673 ps
CPU time 0.57 seconds
Started Apr 21 12:48:36 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 182184 kb
Host smart-e91bd4f7-c3fc-409b-8fb9-69f3bca85c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409274243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2409274243
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1348517718
Short name T530
Test name
Test status
Simulation time 10701298 ps
CPU time 0.55 seconds
Started Apr 21 12:48:54 PM PDT 24
Finished Apr 21 12:48:55 PM PDT 24
Peak memory 182160 kb
Host smart-1cbf95a7-b7ae-4c25-9e7e-66c77dfd79e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348517718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1348517718
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2011364833
Short name T95
Test name
Test status
Simulation time 53892746 ps
CPU time 0.68 seconds
Started Apr 21 12:48:57 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 191232 kb
Host smart-65d2baf6-b12e-4e85-a6d5-c3d9f8c8c17e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011364833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2011364833
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1987407441
Short name T455
Test name
Test status
Simulation time 49642548 ps
CPU time 1.42 seconds
Started Apr 21 12:48:52 PM PDT 24
Finished Apr 21 12:48:54 PM PDT 24
Peak memory 197564 kb
Host smart-9028605b-d334-4fe8-aad4-1f4b31161193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987407441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1987407441
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2134515348
Short name T30
Test name
Test status
Simulation time 74350058 ps
CPU time 1.06 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:47 PM PDT 24
Peak memory 194976 kb
Host smart-54ec64b9-0e55-4a10-a969-483a5c30ebe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134515348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2134515348
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3732821305
Short name T563
Test name
Test status
Simulation time 14655844 ps
CPU time 0.57 seconds
Started Apr 21 12:48:56 PM PDT 24
Finished Apr 21 12:48:57 PM PDT 24
Peak memory 182520 kb
Host smart-cdfb31c7-05a0-4ed5-814a-849ecbbfd643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732821305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3732821305
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2643720957
Short name T511
Test name
Test status
Simulation time 42026191 ps
CPU time 0.52 seconds
Started Apr 21 12:48:55 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 182016 kb
Host smart-1da97276-eabc-445d-968e-d51ccb670c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643720957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2643720957
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1608952373
Short name T554
Test name
Test status
Simulation time 14600250 ps
CPU time 0.56 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 182512 kb
Host smart-0fbf34d1-3581-4a5e-9dfb-de4f6fc0589c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608952373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1608952373
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3279513587
Short name T525
Test name
Test status
Simulation time 33042661 ps
CPU time 0.56 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 182604 kb
Host smart-fc54ac30-034a-4510-b6b1-bce08faa6476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279513587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3279513587
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.509089250
Short name T523
Test name
Test status
Simulation time 53036506 ps
CPU time 0.56 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 182548 kb
Host smart-0ed77bfd-7e7b-403a-956f-c6b27a330adf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509089250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.509089250
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3647387181
Short name T464
Test name
Test status
Simulation time 14329604 ps
CPU time 0.61 seconds
Started Apr 21 12:48:56 PM PDT 24
Finished Apr 21 12:48:57 PM PDT 24
Peak memory 182604 kb
Host smart-c1f3662e-2623-43e5-bc8e-6ce06d5ec9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647387181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3647387181
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3978873070
Short name T524
Test name
Test status
Simulation time 15438480 ps
CPU time 0.55 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 182512 kb
Host smart-840177e8-48dc-4ec6-8bad-c8cdc8f5bc87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978873070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3978873070
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1108711853
Short name T517
Test name
Test status
Simulation time 43046632 ps
CPU time 0.52 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 182208 kb
Host smart-2c1b9b1d-db61-4a78-a288-e0f75d1896a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108711853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1108711853
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2542078526
Short name T461
Test name
Test status
Simulation time 32611607 ps
CPU time 0.57 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 182480 kb
Host smart-90094074-5e9a-4efc-a583-d3c35d364edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542078526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2542078526
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1013298928
Short name T543
Test name
Test status
Simulation time 20893440 ps
CPU time 0.52 seconds
Started Apr 21 12:48:56 PM PDT 24
Finished Apr 21 12:48:57 PM PDT 24
Peak memory 182168 kb
Host smart-34794936-0cb4-4093-a069-516c0a43503b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013298928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1013298928
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3004502653
Short name T469
Test name
Test status
Simulation time 79915222 ps
CPU time 0.72 seconds
Started Apr 21 12:48:51 PM PDT 24
Finished Apr 21 12:48:52 PM PDT 24
Peak memory 194596 kb
Host smart-777a76a3-c875-4200-9094-015d295c4489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004502653 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3004502653
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1107221399
Short name T86
Test name
Test status
Simulation time 18404723 ps
CPU time 0.6 seconds
Started Apr 21 12:48:42 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 191888 kb
Host smart-9283891c-5f5c-4706-b28d-ebcd520dd568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107221399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1107221399
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.278725822
Short name T466
Test name
Test status
Simulation time 14606256 ps
CPU time 0.54 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 182548 kb
Host smart-48a9d0c6-910d-4848-ade8-46c5d1526941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278725822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.278725822
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2520334488
Short name T489
Test name
Test status
Simulation time 107494282 ps
CPU time 0.58 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 191956 kb
Host smart-55e85149-4cc0-4306-9d64-2b9c0dd0e6c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520334488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2520334488
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1783335517
Short name T583
Test name
Test status
Simulation time 153338590 ps
CPU time 1.31 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:36 PM PDT 24
Peak memory 197500 kb
Host smart-c9e38880-f8ea-412b-9e63-63b836844b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783335517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1783335517
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.342072420
Short name T487
Test name
Test status
Simulation time 508170892 ps
CPU time 0.92 seconds
Started Apr 21 12:48:33 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 183192 kb
Host smart-796b3cfd-e881-4af5-844d-886ef38c44c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342072420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.342072420
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1031090121
Short name T562
Test name
Test status
Simulation time 48997034 ps
CPU time 0.62 seconds
Started Apr 21 12:48:49 PM PDT 24
Finished Apr 21 12:48:50 PM PDT 24
Peak memory 193540 kb
Host smart-ecc3e8cf-0391-4b08-b804-cdd177a5fb13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031090121 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1031090121
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2201984911
Short name T531
Test name
Test status
Simulation time 13423693 ps
CPU time 0.58 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:45 PM PDT 24
Peak memory 182676 kb
Host smart-ba0b41f1-8cd4-459e-bf32-0c7979c3de78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201984911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2201984911
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2016311364
Short name T566
Test name
Test status
Simulation time 42408812 ps
CPU time 0.54 seconds
Started Apr 21 12:48:42 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 181972 kb
Host smart-a12d0c8e-fe24-4d35-98cc-fbb02bc21f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016311364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2016311364
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1950303780
Short name T519
Test name
Test status
Simulation time 18289304 ps
CPU time 0.79 seconds
Started Apr 21 12:48:40 PM PDT 24
Finished Apr 21 12:48:41 PM PDT 24
Peak memory 193168 kb
Host smart-9444124a-84c3-4d0c-8288-2349bab72b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950303780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1950303780
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2660592158
Short name T539
Test name
Test status
Simulation time 65532867 ps
CPU time 1.03 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 196028 kb
Host smart-74ee4c38-1661-42f9-bcb6-c8fada6cc70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660592158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2660592158
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4023545174
Short name T29
Test name
Test status
Simulation time 163820053 ps
CPU time 1.24 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:47 PM PDT 24
Peak memory 195272 kb
Host smart-61350994-f496-481c-ba82-8e9127501c23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023545174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.4023545174
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2087072075
Short name T533
Test name
Test status
Simulation time 34005741 ps
CPU time 0.85 seconds
Started Apr 21 12:48:46 PM PDT 24
Finished Apr 21 12:48:48 PM PDT 24
Peak memory 196964 kb
Host smart-f948a4c1-e2ca-4b9d-9546-a56553db8bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087072075 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2087072075
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2743769526
Short name T494
Test name
Test status
Simulation time 33602715 ps
CPU time 0.55 seconds
Started Apr 21 12:48:51 PM PDT 24
Finished Apr 21 12:48:52 PM PDT 24
Peak memory 182584 kb
Host smart-f1ea9c2d-420b-4b2f-98d1-047cb8c19add
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743769526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2743769526
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.970232081
Short name T556
Test name
Test status
Simulation time 140521038 ps
CPU time 0.53 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 181884 kb
Host smart-5c919f92-dfe5-46d4-b6a9-3122857f4f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970232081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.970232081
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1758228911
Short name T561
Test name
Test status
Simulation time 29217440 ps
CPU time 0.74 seconds
Started Apr 21 12:48:49 PM PDT 24
Finished Apr 21 12:48:50 PM PDT 24
Peak memory 191684 kb
Host smart-7c267d8d-5a0a-43e7-9f51-236d407a3abb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758228911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1758228911
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3299085832
Short name T508
Test name
Test status
Simulation time 705085339 ps
CPU time 2.89 seconds
Started Apr 21 12:48:46 PM PDT 24
Finished Apr 21 12:48:50 PM PDT 24
Peak memory 197476 kb
Host smart-99fbf09a-5adb-4445-b5cb-69ab03e27e73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299085832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3299085832
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3854359008
Short name T104
Test name
Test status
Simulation time 42395661 ps
CPU time 0.87 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 182912 kb
Host smart-3a795030-19fa-4f7f-8c7b-a0e17435415e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854359008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3854359008
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2584799989
Short name T575
Test name
Test status
Simulation time 44003120 ps
CPU time 0.95 seconds
Started Apr 21 12:48:40 PM PDT 24
Finished Apr 21 12:48:41 PM PDT 24
Peak memory 196692 kb
Host smart-4c3cfeb1-9571-4272-93b1-ace38684a7ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584799989 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2584799989
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1066758151
Short name T83
Test name
Test status
Simulation time 41739358 ps
CPU time 0.58 seconds
Started Apr 21 12:48:37 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 182640 kb
Host smart-e51bbf16-f26e-46c5-a79d-3d41c4c9de1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066758151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1066758151
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.286169336
Short name T532
Test name
Test status
Simulation time 18160948 ps
CPU time 0.6 seconds
Started Apr 21 12:48:42 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 182520 kb
Host smart-fc9e433f-cf71-424a-b662-84abe1709cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286169336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.286169336
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1771838672
Short name T497
Test name
Test status
Simulation time 47350357 ps
CPU time 0.61 seconds
Started Apr 21 12:48:37 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 191988 kb
Host smart-446631bf-1bf7-4447-b308-c7de8eb6bfaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771838672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1771838672
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.818727194
Short name T576
Test name
Test status
Simulation time 40728902 ps
CPU time 1.99 seconds
Started Apr 21 12:48:37 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 197492 kb
Host smart-4583dd43-c711-4bcc-bb8a-330530172c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818727194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.818727194
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.208329314
Short name T502
Test name
Test status
Simulation time 220762518 ps
CPU time 1.41 seconds
Started Apr 21 12:48:42 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 195556 kb
Host smart-bfd02485-fa02-4630-a017-87eb5db1c6d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208329314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.208329314
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1257155415
Short name T503
Test name
Test status
Simulation time 71726024 ps
CPU time 0.96 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 196728 kb
Host smart-56ebe99b-2456-47b4-8446-66d09d47d8ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257155415 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1257155415
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3454856449
Short name T557
Test name
Test status
Simulation time 46339334 ps
CPU time 0.58 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:47 PM PDT 24
Peak memory 182576 kb
Host smart-a7723026-f50a-4752-94d0-6a1a5607b997
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454856449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3454856449
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1230555126
Short name T453
Test name
Test status
Simulation time 15284305 ps
CPU time 0.58 seconds
Started Apr 21 12:48:49 PM PDT 24
Finished Apr 21 12:48:51 PM PDT 24
Peak memory 182164 kb
Host smart-e25e4fa9-914a-41ca-9a03-e98d28e15589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230555126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1230555126
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3931184219
Short name T93
Test name
Test status
Simulation time 37179342 ps
CPU time 0.78 seconds
Started Apr 21 12:48:46 PM PDT 24
Finished Apr 21 12:48:48 PM PDT 24
Peak memory 193344 kb
Host smart-2c1ec364-9fba-48fd-a88e-885c59324cd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931184219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3931184219
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3673464057
Short name T506
Test name
Test status
Simulation time 140394459 ps
CPU time 1.94 seconds
Started Apr 21 12:48:49 PM PDT 24
Finished Apr 21 12:48:51 PM PDT 24
Peak memory 197460 kb
Host smart-ba0d46cb-4d1b-4435-ae9c-2a43240450a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673464057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3673464057
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2376979572
Short name T101
Test name
Test status
Simulation time 82678932 ps
CPU time 0.85 seconds
Started Apr 21 12:48:52 PM PDT 24
Finished Apr 21 12:48:53 PM PDT 24
Peak memory 183208 kb
Host smart-8346e878-abf1-4805-8754-28f9812e18ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376979572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2376979572
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1185526388
Short name T68
Test name
Test status
Simulation time 170607853981 ps
CPU time 205.35 seconds
Started Apr 21 02:28:09 PM PDT 24
Finished Apr 21 02:31:35 PM PDT 24
Peak memory 182620 kb
Host smart-3c31adc2-745b-443b-bce4-78155148a68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185526388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1185526388
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1147977655
Short name T47
Test name
Test status
Simulation time 132287219706 ps
CPU time 74.74 seconds
Started Apr 21 02:28:13 PM PDT 24
Finished Apr 21 02:29:28 PM PDT 24
Peak memory 194312 kb
Host smart-0c1364fc-299b-4dcd-8436-cb9633d89e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147977655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1147977655
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.171919249
Short name T70
Test name
Test status
Simulation time 61799262337 ps
CPU time 367.84 seconds
Started Apr 21 02:28:08 PM PDT 24
Finished Apr 21 02:34:16 PM PDT 24
Peak memory 205408 kb
Host smart-a3ef9679-d405-4b04-a4a9-8be8034718fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171919249 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.171919249
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2679435356
Short name T24
Test name
Test status
Simulation time 44151430931 ps
CPU time 70.65 seconds
Started Apr 21 02:28:14 PM PDT 24
Finished Apr 21 02:29:25 PM PDT 24
Peak memory 182632 kb
Host smart-edadfde3-0b2a-4085-9f00-c79c88712d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679435356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2679435356
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1375910679
Short name T338
Test name
Test status
Simulation time 57656145569 ps
CPU time 108.99 seconds
Started Apr 21 02:28:12 PM PDT 24
Finished Apr 21 02:30:01 PM PDT 24
Peak memory 190868 kb
Host smart-72f15a4d-f54e-4ab4-b078-c8a59fd2f463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375910679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1375910679
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2185134690
Short name T18
Test name
Test status
Simulation time 55107492 ps
CPU time 0.79 seconds
Started Apr 21 02:28:13 PM PDT 24
Finished Apr 21 02:28:14 PM PDT 24
Peak memory 213100 kb
Host smart-d04dda84-6cb0-40f5-bb32-36cf32624b4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185134690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2185134690
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2097818002
Short name T395
Test name
Test status
Simulation time 8622524601 ps
CPU time 104.79 seconds
Started Apr 21 02:28:14 PM PDT 24
Finished Apr 21 02:30:00 PM PDT 24
Peak memory 197276 kb
Host smart-95658737-38ac-4000-836f-ef184e3ca331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097818002 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2097818002
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1854317317
Short name T429
Test name
Test status
Simulation time 196876413163 ps
CPU time 85.65 seconds
Started Apr 21 02:28:56 PM PDT 24
Finished Apr 21 02:30:22 PM PDT 24
Peak memory 182656 kb
Host smart-b3defa51-03a9-43ee-8d8f-3ee5373cad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854317317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1854317317
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3927189537
Short name T171
Test name
Test status
Simulation time 221782392522 ps
CPU time 144.02 seconds
Started Apr 21 02:28:56 PM PDT 24
Finished Apr 21 02:31:20 PM PDT 24
Peak memory 182640 kb
Host smart-cec77118-33da-4681-aa19-c55d93a3881f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927189537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3927189537
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3144132553
Short name T330
Test name
Test status
Simulation time 484066153314 ps
CPU time 227.19 seconds
Started Apr 21 02:34:10 PM PDT 24
Finished Apr 21 02:37:58 PM PDT 24
Peak memory 190880 kb
Host smart-cba37002-8481-4ad1-988e-fcdb19eef395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144132553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3144132553
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3401665895
Short name T252
Test name
Test status
Simulation time 347479167844 ps
CPU time 211.03 seconds
Started Apr 21 02:34:12 PM PDT 24
Finished Apr 21 02:37:43 PM PDT 24
Peak memory 190804 kb
Host smart-aeecfb63-c748-472e-8d3c-9a5108df1db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401665895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3401665895
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3810529572
Short name T342
Test name
Test status
Simulation time 135180517114 ps
CPU time 190.61 seconds
Started Apr 21 02:34:14 PM PDT 24
Finished Apr 21 02:37:25 PM PDT 24
Peak memory 182652 kb
Host smart-83877099-d57d-4084-9160-d1c3ba702797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810529572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3810529572
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1210764507
Short name T264
Test name
Test status
Simulation time 114379450526 ps
CPU time 206.71 seconds
Started Apr 21 02:34:16 PM PDT 24
Finished Apr 21 02:37:43 PM PDT 24
Peak memory 190888 kb
Host smart-b59e3527-d21a-48e2-a06a-9148568616d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210764507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1210764507
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.4104862571
Short name T216
Test name
Test status
Simulation time 167833400814 ps
CPU time 162.37 seconds
Started Apr 21 02:34:17 PM PDT 24
Finished Apr 21 02:37:00 PM PDT 24
Peak memory 190844 kb
Host smart-681833c3-7da8-47fb-ada2-5b01fbc45188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104862571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.4104862571
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.553120430
Short name T186
Test name
Test status
Simulation time 383954182266 ps
CPU time 376.17 seconds
Started Apr 21 02:34:17 PM PDT 24
Finished Apr 21 02:40:33 PM PDT 24
Peak memory 191864 kb
Host smart-e9d5baa4-6f1c-45f1-8905-4a055667270c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553120430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.553120430
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.131037595
Short name T365
Test name
Test status
Simulation time 180434564542 ps
CPU time 122.31 seconds
Started Apr 21 02:28:58 PM PDT 24
Finished Apr 21 02:31:01 PM PDT 24
Peak memory 182588 kb
Host smart-d0533e06-bd91-486d-b154-643770a83f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131037595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.131037595
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2402513261
Short name T412
Test name
Test status
Simulation time 89033887145 ps
CPU time 1374.56 seconds
Started Apr 21 02:29:00 PM PDT 24
Finished Apr 21 02:51:55 PM PDT 24
Peak memory 182612 kb
Host smart-7c1bec19-f3fa-4275-941b-0e2df8c9ecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402513261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2402513261
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3678766880
Short name T61
Test name
Test status
Simulation time 1257986798421 ps
CPU time 473.56 seconds
Started Apr 21 02:29:02 PM PDT 24
Finished Apr 21 02:36:56 PM PDT 24
Peak memory 195324 kb
Host smart-ebd63bca-baab-4523-b2d8-6a0f56dd6c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678766880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3678766880
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.3501963580
Short name T25
Test name
Test status
Simulation time 78231297167 ps
CPU time 132.69 seconds
Started Apr 21 02:34:23 PM PDT 24
Finished Apr 21 02:36:36 PM PDT 24
Peak memory 190876 kb
Host smart-feff1919-44b4-491f-be69-8cbc722901c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501963580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3501963580
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1379597102
Short name T236
Test name
Test status
Simulation time 33680837571 ps
CPU time 63.15 seconds
Started Apr 21 02:34:23 PM PDT 24
Finished Apr 21 02:35:27 PM PDT 24
Peak memory 182688 kb
Host smart-e0054fe7-cd63-4451-898c-31bc070e7955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379597102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1379597102
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2683130970
Short name T430
Test name
Test status
Simulation time 96637152777 ps
CPU time 524.15 seconds
Started Apr 21 02:34:23 PM PDT 24
Finished Apr 21 02:43:08 PM PDT 24
Peak memory 190880 kb
Host smart-987c9434-64b9-417c-b147-118f23130a33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683130970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2683130970
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3671924743
Short name T196
Test name
Test status
Simulation time 99845644461 ps
CPU time 375.95 seconds
Started Apr 21 02:34:27 PM PDT 24
Finished Apr 21 02:40:43 PM PDT 24
Peak memory 190864 kb
Host smart-f5ff6268-77de-41ad-a7e8-dcd7a93e4b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671924743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3671924743
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.218247797
Short name T340
Test name
Test status
Simulation time 359015165400 ps
CPU time 184.06 seconds
Started Apr 21 02:34:30 PM PDT 24
Finished Apr 21 02:37:35 PM PDT 24
Peak memory 190888 kb
Host smart-b03f3319-5a9a-4ef7-9e48-18da86e4b62c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218247797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.218247797
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.735763415
Short name T127
Test name
Test status
Simulation time 1257659743682 ps
CPU time 1562.35 seconds
Started Apr 21 02:34:29 PM PDT 24
Finished Apr 21 03:00:31 PM PDT 24
Peak memory 190864 kb
Host smart-2ca8c29f-cf4e-448a-98a6-579f10645ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735763415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.735763415
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3131085161
Short name T44
Test name
Test status
Simulation time 343779100655 ps
CPU time 220.25 seconds
Started Apr 21 02:29:00 PM PDT 24
Finished Apr 21 02:32:41 PM PDT 24
Peak memory 182652 kb
Host smart-5feca381-3f45-4229-9cf9-1a3f8e09b610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131085161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3131085161
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3670357111
Short name T417
Test name
Test status
Simulation time 1249122358 ps
CPU time 1.55 seconds
Started Apr 21 02:29:02 PM PDT 24
Finished Apr 21 02:29:03 PM PDT 24
Peak memory 192244 kb
Host smart-463b0271-1a8b-488e-b685-cd7f1f5ecbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670357111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3670357111
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3623830014
Short name T40
Test name
Test status
Simulation time 28817363072 ps
CPU time 215.42 seconds
Started Apr 21 02:29:05 PM PDT 24
Finished Apr 21 02:32:41 PM PDT 24
Peak memory 205520 kb
Host smart-690ee411-5aca-41a6-8411-81271ecc2d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623830014 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3623830014
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.3977841107
Short name T133
Test name
Test status
Simulation time 92973673437 ps
CPU time 176.69 seconds
Started Apr 21 02:34:32 PM PDT 24
Finished Apr 21 02:37:29 PM PDT 24
Peak memory 190880 kb
Host smart-49b1e7db-92c2-4146-94bf-f5b1176a2a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977841107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3977841107
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1892768209
Short name T266
Test name
Test status
Simulation time 59985832883 ps
CPU time 423.27 seconds
Started Apr 21 02:34:34 PM PDT 24
Finished Apr 21 02:41:38 PM PDT 24
Peak memory 190876 kb
Host smart-c2980cbd-2dfc-4836-aec3-03441fa351e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892768209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1892768209
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1162653494
Short name T335
Test name
Test status
Simulation time 234522975497 ps
CPU time 706.44 seconds
Started Apr 21 02:34:38 PM PDT 24
Finished Apr 21 02:46:25 PM PDT 24
Peak memory 190928 kb
Host smart-2091edf5-883b-4648-8199-63ee02d555c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162653494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1162653494
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3795676695
Short name T273
Test name
Test status
Simulation time 95636745873 ps
CPU time 57.56 seconds
Started Apr 21 02:34:35 PM PDT 24
Finished Apr 21 02:35:33 PM PDT 24
Peak memory 192892 kb
Host smart-de842bf4-8d1f-425a-b83a-81d86cf033ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795676695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3795676695
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1208882058
Short name T322
Test name
Test status
Simulation time 22034579030 ps
CPU time 37.4 seconds
Started Apr 21 02:34:35 PM PDT 24
Finished Apr 21 02:35:13 PM PDT 24
Peak memory 190872 kb
Host smart-266a11c5-fbdb-4e5a-ab69-c74bb0ee78dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208882058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1208882058
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3735892356
Short name T139
Test name
Test status
Simulation time 40039127488 ps
CPU time 184.66 seconds
Started Apr 21 02:34:43 PM PDT 24
Finished Apr 21 02:37:48 PM PDT 24
Peak memory 190876 kb
Host smart-ff30e7b0-632d-4d8e-92d5-94549ab13b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735892356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3735892356
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.357349982
Short name T56
Test name
Test status
Simulation time 1239329526604 ps
CPU time 1081.87 seconds
Started Apr 21 02:34:38 PM PDT 24
Finished Apr 21 02:52:40 PM PDT 24
Peak memory 190852 kb
Host smart-747a9959-b26a-43c8-b96e-7f82e09eef11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357349982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.357349982
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3374718507
Short name T110
Test name
Test status
Simulation time 193442478282 ps
CPU time 96.87 seconds
Started Apr 21 02:34:42 PM PDT 24
Finished Apr 21 02:36:20 PM PDT 24
Peak memory 182680 kb
Host smart-2d77497c-9a77-49b4-b8dd-a9e2c4fb79ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374718507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3374718507
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2167231238
Short name T303
Test name
Test status
Simulation time 32007235155 ps
CPU time 20.07 seconds
Started Apr 21 02:29:06 PM PDT 24
Finished Apr 21 02:29:26 PM PDT 24
Peak memory 182644 kb
Host smart-cc7ace04-0119-4495-9f37-85042b7a1450
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167231238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2167231238
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1333446998
Short name T424
Test name
Test status
Simulation time 241689916180 ps
CPU time 258.16 seconds
Started Apr 21 02:29:03 PM PDT 24
Finished Apr 21 02:33:22 PM PDT 24
Peak memory 182664 kb
Host smart-1edcbaaf-00bb-4889-a3a7-463c15ec6742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333446998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1333446998
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.3766967861
Short name T279
Test name
Test status
Simulation time 339412782817 ps
CPU time 1950.9 seconds
Started Apr 21 02:29:06 PM PDT 24
Finished Apr 21 03:01:37 PM PDT 24
Peak memory 190852 kb
Host smart-5289b81d-cf9e-43c3-a161-0fb562cb4f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766967861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3766967861
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1756722155
Short name T313
Test name
Test status
Simulation time 196981390925 ps
CPU time 95 seconds
Started Apr 21 02:29:06 PM PDT 24
Finished Apr 21 02:30:42 PM PDT 24
Peak memory 182644 kb
Host smart-864b8ba8-7c4d-4dbc-b9cf-b206077f3f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756722155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1756722155
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.507108432
Short name T351
Test name
Test status
Simulation time 27886805424 ps
CPU time 47.34 seconds
Started Apr 21 02:34:41 PM PDT 24
Finished Apr 21 02:35:29 PM PDT 24
Peak memory 190884 kb
Host smart-841f8d1b-388b-422d-ae79-3738b0a0bd2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507108432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.507108432
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2183406468
Short name T48
Test name
Test status
Simulation time 28434675904 ps
CPU time 46.09 seconds
Started Apr 21 02:34:44 PM PDT 24
Finished Apr 21 02:35:30 PM PDT 24
Peak memory 182672 kb
Host smart-25d8d066-6353-41f8-b728-a425c4705b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183406468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2183406468
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2768571414
Short name T201
Test name
Test status
Simulation time 354563724584 ps
CPU time 1913.52 seconds
Started Apr 21 02:34:49 PM PDT 24
Finished Apr 21 03:06:43 PM PDT 24
Peak memory 190844 kb
Host smart-017a22fc-3ea7-4028-9699-22b18daa376b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768571414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2768571414
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.4069144978
Short name T224
Test name
Test status
Simulation time 213895362251 ps
CPU time 595.97 seconds
Started Apr 21 02:34:50 PM PDT 24
Finished Apr 21 02:44:47 PM PDT 24
Peak memory 190808 kb
Host smart-87b41a5c-8afe-41e3-a8e9-c17739f92e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069144978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.4069144978
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3209852793
Short name T293
Test name
Test status
Simulation time 230713053555 ps
CPU time 3077.18 seconds
Started Apr 21 02:34:51 PM PDT 24
Finished Apr 21 03:26:09 PM PDT 24
Peak memory 190812 kb
Host smart-ace7e332-8203-4ef4-b99c-8590a042571c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209852793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3209852793
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3146915581
Short name T400
Test name
Test status
Simulation time 129651660550 ps
CPU time 161.3 seconds
Started Apr 21 02:29:12 PM PDT 24
Finished Apr 21 02:31:54 PM PDT 24
Peak memory 182644 kb
Host smart-e0054e28-0fcc-43cc-8048-1cfe738e0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146915581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3146915581
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1341180988
Short name T280
Test name
Test status
Simulation time 96043012748 ps
CPU time 133.06 seconds
Started Apr 21 02:29:09 PM PDT 24
Finished Apr 21 02:31:22 PM PDT 24
Peak memory 182620 kb
Host smart-2a543efa-8058-44d0-bc35-2adc2fe51918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341180988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1341180988
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.992493506
Short name T446
Test name
Test status
Simulation time 56970100045 ps
CPU time 109.03 seconds
Started Apr 21 02:29:11 PM PDT 24
Finished Apr 21 02:31:00 PM PDT 24
Peak memory 190856 kb
Host smart-38da11c0-1d3e-4700-9c5a-7a740d39dde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992493506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.992493506
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1992619089
Short name T311
Test name
Test status
Simulation time 45852542237 ps
CPU time 45.37 seconds
Started Apr 21 02:34:55 PM PDT 24
Finished Apr 21 02:35:40 PM PDT 24
Peak memory 182680 kb
Host smart-d5902470-988f-4cd6-8d99-6875fd5737a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992619089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1992619089
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1239709946
Short name T260
Test name
Test status
Simulation time 2498555415714 ps
CPU time 811.42 seconds
Started Apr 21 02:35:00 PM PDT 24
Finished Apr 21 02:48:32 PM PDT 24
Peak memory 190888 kb
Host smart-f3022241-d640-4650-88b0-697a5aa8a9e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239709946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1239709946
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.275505037
Short name T116
Test name
Test status
Simulation time 51130717555 ps
CPU time 89.59 seconds
Started Apr 21 02:35:01 PM PDT 24
Finished Apr 21 02:36:31 PM PDT 24
Peak memory 190880 kb
Host smart-9b8f0436-d4c2-4b2c-b9e0-cc95049c1e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275505037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.275505037
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1800743095
Short name T54
Test name
Test status
Simulation time 44957834652 ps
CPU time 67.37 seconds
Started Apr 21 02:35:08 PM PDT 24
Finished Apr 21 02:36:15 PM PDT 24
Peak memory 190880 kb
Host smart-97fa4371-cf2a-4eec-ad77-0c7e1210d743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800743095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1800743095
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3766886880
Short name T26
Test name
Test status
Simulation time 63718083168 ps
CPU time 31.86 seconds
Started Apr 21 02:35:12 PM PDT 24
Finished Apr 21 02:35:44 PM PDT 24
Peak memory 182684 kb
Host smart-0cb370a4-898f-422b-bfb7-df9268a9da71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766886880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3766886880
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.903788207
Short name T315
Test name
Test status
Simulation time 225768030792 ps
CPU time 148.85 seconds
Started Apr 21 02:35:09 PM PDT 24
Finished Apr 21 02:37:39 PM PDT 24
Peak memory 190804 kb
Host smart-a9b466ab-c3c8-4c91-aeaf-d86040f88156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903788207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.903788207
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3414838067
Short name T159
Test name
Test status
Simulation time 81928767636 ps
CPU time 54.48 seconds
Started Apr 21 02:29:14 PM PDT 24
Finished Apr 21 02:30:09 PM PDT 24
Peak memory 182680 kb
Host smart-7903e07a-dafc-4095-96d2-a3591ff76d2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414838067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3414838067
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.4186195420
Short name T448
Test name
Test status
Simulation time 79533987758 ps
CPU time 64.25 seconds
Started Apr 21 02:29:16 PM PDT 24
Finished Apr 21 02:30:20 PM PDT 24
Peak memory 182672 kb
Host smart-32c7a02d-7b9e-421f-b6e0-8168e8038114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186195420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.4186195420
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3899017995
Short name T234
Test name
Test status
Simulation time 330561777129 ps
CPU time 1224.83 seconds
Started Apr 21 02:29:15 PM PDT 24
Finished Apr 21 02:49:40 PM PDT 24
Peak memory 190848 kb
Host smart-f3131528-fc86-4cdf-b90a-78d9f5fefa0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899017995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3899017995
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1253798014
Short name T341
Test name
Test status
Simulation time 44410192030 ps
CPU time 83.11 seconds
Started Apr 21 02:29:15 PM PDT 24
Finished Apr 21 02:30:39 PM PDT 24
Peak memory 182680 kb
Host smart-fc286bbd-8ac1-4feb-8943-8c2d72a94a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253798014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1253798014
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3864274284
Short name T202
Test name
Test status
Simulation time 76855131417 ps
CPU time 359.48 seconds
Started Apr 21 02:35:14 PM PDT 24
Finished Apr 21 02:41:14 PM PDT 24
Peak memory 190872 kb
Host smart-668c4286-8ea1-4850-a407-7018e88afc35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864274284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3864274284
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1778515159
Short name T42
Test name
Test status
Simulation time 111516051280 ps
CPU time 24.35 seconds
Started Apr 21 02:35:11 PM PDT 24
Finished Apr 21 02:35:36 PM PDT 24
Peak memory 190852 kb
Host smart-70d3f140-f9d9-4240-b4b8-238b94f5ac46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778515159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1778515159
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.96253231
Short name T19
Test name
Test status
Simulation time 95649810242 ps
CPU time 45.61 seconds
Started Apr 21 02:35:16 PM PDT 24
Finished Apr 21 02:36:03 PM PDT 24
Peak memory 182676 kb
Host smart-09cd7c6b-4ba5-4747-b275-abfdf2106000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96253231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.96253231
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3782302343
Short name T333
Test name
Test status
Simulation time 3421691430 ps
CPU time 6.25 seconds
Started Apr 21 02:35:24 PM PDT 24
Finished Apr 21 02:35:34 PM PDT 24
Peak memory 182688 kb
Host smart-695c7279-284a-4110-a1d7-cb78b8c96b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782302343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3782302343
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3622439111
Short name T81
Test name
Test status
Simulation time 307783588327 ps
CPU time 485.53 seconds
Started Apr 21 02:35:25 PM PDT 24
Finished Apr 21 02:43:34 PM PDT 24
Peak memory 192568 kb
Host smart-45ba9d38-86b4-401d-9bc9-61b5660f9a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622439111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3622439111
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3085378587
Short name T200
Test name
Test status
Simulation time 128758807368 ps
CPU time 257.95 seconds
Started Apr 21 02:35:23 PM PDT 24
Finished Apr 21 02:39:45 PM PDT 24
Peak memory 182692 kb
Host smart-03c5e2ca-4df1-43e8-8a73-7afdd6379fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085378587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3085378587
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2302975115
Short name T213
Test name
Test status
Simulation time 58789314931 ps
CPU time 397.83 seconds
Started Apr 21 02:35:30 PM PDT 24
Finished Apr 21 02:42:09 PM PDT 24
Peak memory 190880 kb
Host smart-ff38885e-1b64-4331-8173-f27476fd5e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302975115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2302975115
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3243753256
Short name T148
Test name
Test status
Simulation time 170100268509 ps
CPU time 324 seconds
Started Apr 21 02:35:30 PM PDT 24
Finished Apr 21 02:40:55 PM PDT 24
Peak memory 190844 kb
Host smart-c1407c19-3db0-456e-9080-3aa34cce33bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243753256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3243753256
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.4289588028
Short name T3
Test name
Test status
Simulation time 37136100182 ps
CPU time 71.97 seconds
Started Apr 21 02:35:30 PM PDT 24
Finished Apr 21 02:36:43 PM PDT 24
Peak memory 182612 kb
Host smart-2d38e10c-dd2b-40ec-8166-e16de641d29c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289588028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4289588028
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.48393356
Short name T408
Test name
Test status
Simulation time 313438510101 ps
CPU time 206.31 seconds
Started Apr 21 02:29:21 PM PDT 24
Finished Apr 21 02:32:48 PM PDT 24
Peak memory 182668 kb
Host smart-15fb0587-3655-4e7c-aedb-6bced1f9a2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48393356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.48393356
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3021622798
Short name T379
Test name
Test status
Simulation time 3518276732 ps
CPU time 12.21 seconds
Started Apr 21 02:29:24 PM PDT 24
Finished Apr 21 02:29:37 PM PDT 24
Peak memory 194368 kb
Host smart-f636d635-f884-4220-8cd2-8a2132b55d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021622798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3021622798
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3504322199
Short name T166
Test name
Test status
Simulation time 726683101417 ps
CPU time 929.05 seconds
Started Apr 21 02:29:24 PM PDT 24
Finished Apr 21 02:44:53 PM PDT 24
Peak memory 190828 kb
Host smart-0b95fbbd-4c07-4fe9-b958-d5f6bebed1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504322199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3504322199
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.796734152
Short name T149
Test name
Test status
Simulation time 885298997249 ps
CPU time 1001.61 seconds
Started Apr 21 02:35:30 PM PDT 24
Finished Apr 21 02:52:13 PM PDT 24
Peak memory 193312 kb
Host smart-eba4919a-4bee-4f50-8cb6-df19c984f006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796734152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.796734152
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1744914227
Short name T345
Test name
Test status
Simulation time 254297783226 ps
CPU time 266.24 seconds
Started Apr 21 02:35:30 PM PDT 24
Finished Apr 21 02:39:58 PM PDT 24
Peak memory 190876 kb
Host smart-260cc9ca-d1de-4c30-a111-405e727fe502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744914227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1744914227
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1779198723
Short name T238
Test name
Test status
Simulation time 126905327710 ps
CPU time 70.33 seconds
Started Apr 21 02:35:32 PM PDT 24
Finished Apr 21 02:36:43 PM PDT 24
Peak memory 190840 kb
Host smart-7259f16d-3f0a-46bc-a9d4-f5fbd27b835f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779198723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1779198723
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2739084564
Short name T231
Test name
Test status
Simulation time 191391762678 ps
CPU time 603.33 seconds
Started Apr 21 02:35:36 PM PDT 24
Finished Apr 21 02:45:40 PM PDT 24
Peak memory 190856 kb
Host smart-a36c921f-493b-421a-b63a-79bfa4797018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739084564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2739084564
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.4226329400
Short name T354
Test name
Test status
Simulation time 34339124071 ps
CPU time 52.58 seconds
Started Apr 21 02:35:36 PM PDT 24
Finished Apr 21 02:36:29 PM PDT 24
Peak memory 191216 kb
Host smart-212259b5-b28b-4251-9054-9a286daa9c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226329400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4226329400
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3192539057
Short name T272
Test name
Test status
Simulation time 207156350725 ps
CPU time 279.39 seconds
Started Apr 21 02:35:45 PM PDT 24
Finished Apr 21 02:40:25 PM PDT 24
Peak memory 182688 kb
Host smart-4e3526c2-66d9-4ee4-aa32-24e429e410e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192539057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3192539057
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3395809806
Short name T82
Test name
Test status
Simulation time 63780224636 ps
CPU time 49.59 seconds
Started Apr 21 02:35:48 PM PDT 24
Finished Apr 21 02:36:37 PM PDT 24
Peak memory 182640 kb
Host smart-a9d15bc9-c357-450e-aed1-606dce2c0547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395809806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3395809806
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.48833313
Short name T413
Test name
Test status
Simulation time 263918020206 ps
CPU time 475 seconds
Started Apr 21 02:29:27 PM PDT 24
Finished Apr 21 02:37:22 PM PDT 24
Peak memory 182684 kb
Host smart-9af2a525-6f54-4b43-a37f-f24b4e658bd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48833313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.rv_timer_cfg_update_on_fly.48833313
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1558252797
Short name T380
Test name
Test status
Simulation time 620949179052 ps
CPU time 255.91 seconds
Started Apr 21 02:29:26 PM PDT 24
Finished Apr 21 02:33:42 PM PDT 24
Peak memory 182636 kb
Host smart-31aa3bf5-b642-4dca-9a34-aad24f03e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558252797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1558252797
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.313354558
Short name T292
Test name
Test status
Simulation time 88918473309 ps
CPU time 160.58 seconds
Started Apr 21 02:29:24 PM PDT 24
Finished Apr 21 02:32:05 PM PDT 24
Peak memory 190840 kb
Host smart-0e7816e7-0595-4ad5-88dc-4627d7162da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313354558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.313354558
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.517392717
Short name T392
Test name
Test status
Simulation time 40811874389 ps
CPU time 65.31 seconds
Started Apr 21 02:29:27 PM PDT 24
Finished Apr 21 02:30:33 PM PDT 24
Peak memory 182684 kb
Host smart-25639f9c-f75a-4ef3-810c-c3af59a2993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517392717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.517392717
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4159997954
Short name T191
Test name
Test status
Simulation time 523519299435 ps
CPU time 364.82 seconds
Started Apr 21 02:35:46 PM PDT 24
Finished Apr 21 02:41:51 PM PDT 24
Peak memory 190864 kb
Host smart-2c1f1e32-71b0-40c9-aeb7-6266c22dd282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159997954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4159997954
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1374175336
Short name T343
Test name
Test status
Simulation time 205317038504 ps
CPU time 154.44 seconds
Started Apr 21 02:35:46 PM PDT 24
Finished Apr 21 02:38:21 PM PDT 24
Peak memory 182660 kb
Host smart-421ba9b1-f2b2-4dd8-8e3f-ad27987b9b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374175336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1374175336
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.4268804782
Short name T157
Test name
Test status
Simulation time 623540501231 ps
CPU time 365.26 seconds
Started Apr 21 02:35:50 PM PDT 24
Finished Apr 21 02:41:55 PM PDT 24
Peak memory 190860 kb
Host smart-14f817ce-ee49-4415-91ea-1e73bd888615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268804782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4268804782
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1657096034
Short name T325
Test name
Test status
Simulation time 203145781434 ps
CPU time 1748.72 seconds
Started Apr 21 02:35:49 PM PDT 24
Finished Apr 21 03:04:58 PM PDT 24
Peak memory 190876 kb
Host smart-2df34700-9917-4b0a-81ee-87a1c2bf2ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657096034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1657096034
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3538862809
Short name T389
Test name
Test status
Simulation time 23754848666 ps
CPU time 37.01 seconds
Started Apr 21 02:35:55 PM PDT 24
Finished Apr 21 02:36:33 PM PDT 24
Peak memory 182644 kb
Host smart-10f48f6b-4c28-452e-a9cc-8ea1f119a826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538862809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3538862809
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1173952952
Short name T195
Test name
Test status
Simulation time 18001496638 ps
CPU time 53.34 seconds
Started Apr 21 02:35:56 PM PDT 24
Finished Apr 21 02:36:49 PM PDT 24
Peak memory 182664 kb
Host smart-2c2a5884-f80d-49e7-9018-266375e9940d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173952952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1173952952
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1786051912
Short name T451
Test name
Test status
Simulation time 454236381388 ps
CPU time 1096.01 seconds
Started Apr 21 02:35:59 PM PDT 24
Finished Apr 21 02:54:16 PM PDT 24
Peak memory 190832 kb
Host smart-34295034-a951-4d77-9edc-9a7f65aa7d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786051912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1786051912
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.991620803
Short name T407
Test name
Test status
Simulation time 46973098268 ps
CPU time 82.3 seconds
Started Apr 21 02:29:31 PM PDT 24
Finished Apr 21 02:30:54 PM PDT 24
Peak memory 182688 kb
Host smart-b41f4df4-2e81-49d9-b0fd-16faa26e2998
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991620803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.991620803
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_random.1676653096
Short name T55
Test name
Test status
Simulation time 234294524590 ps
CPU time 95.54 seconds
Started Apr 21 02:29:31 PM PDT 24
Finished Apr 21 02:31:07 PM PDT 24
Peak memory 182684 kb
Host smart-852145e3-af55-4984-b7cd-43e7d2fb37a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676653096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1676653096
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.589465464
Short name T397
Test name
Test status
Simulation time 1249257464384 ps
CPU time 286.04 seconds
Started Apr 21 02:29:38 PM PDT 24
Finished Apr 21 02:34:24 PM PDT 24
Peak memory 194320 kb
Host smart-ff97fce6-3a29-4c26-b2a3-315c744e40f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589465464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
589465464
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.1657424305
Short name T415
Test name
Test status
Simulation time 143184763172 ps
CPU time 193.38 seconds
Started Apr 21 02:36:02 PM PDT 24
Finished Apr 21 02:39:16 PM PDT 24
Peak memory 190872 kb
Host smart-98fcea76-32a3-43a3-8836-54c4d68aa303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657424305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1657424305
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3864436021
Short name T120
Test name
Test status
Simulation time 360677347024 ps
CPU time 567.09 seconds
Started Apr 21 02:36:06 PM PDT 24
Finished Apr 21 02:45:33 PM PDT 24
Peak memory 190864 kb
Host smart-3eddbfc6-72c7-4f66-a78b-8fbdd20f8755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864436021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3864436021
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.209672524
Short name T444
Test name
Test status
Simulation time 39971167694 ps
CPU time 224.18 seconds
Started Apr 21 02:36:06 PM PDT 24
Finished Apr 21 02:39:50 PM PDT 24
Peak memory 182668 kb
Host smart-821b5450-4c57-415a-8415-d40db490a6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209672524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.209672524
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2986308485
Short name T218
Test name
Test status
Simulation time 18636608529 ps
CPU time 29.33 seconds
Started Apr 21 02:36:05 PM PDT 24
Finished Apr 21 02:36:35 PM PDT 24
Peak memory 182664 kb
Host smart-d1f15319-3287-4d1b-9968-067dd0cbeb03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986308485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2986308485
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1084127925
Short name T131
Test name
Test status
Simulation time 160210228394 ps
CPU time 75.45 seconds
Started Apr 21 02:36:05 PM PDT 24
Finished Apr 21 02:37:21 PM PDT 24
Peak memory 190860 kb
Host smart-51f63ce8-eac8-48ed-b40e-7dced11ae680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084127925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1084127925
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1429005571
Short name T282
Test name
Test status
Simulation time 158616270962 ps
CPU time 251.19 seconds
Started Apr 21 02:36:05 PM PDT 24
Finished Apr 21 02:40:16 PM PDT 24
Peak memory 190848 kb
Host smart-182b7819-a6c8-4921-ad5b-25fbd27063f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429005571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1429005571
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2330069396
Short name T269
Test name
Test status
Simulation time 133126691729 ps
CPU time 926.84 seconds
Started Apr 21 02:36:04 PM PDT 24
Finished Apr 21 02:51:31 PM PDT 24
Peak memory 190876 kb
Host smart-8e92acb0-abdd-4b7d-896b-b29e3f4b94f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330069396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2330069396
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3657833952
Short name T388
Test name
Test status
Simulation time 503099155352 ps
CPU time 178.57 seconds
Started Apr 21 02:29:37 PM PDT 24
Finished Apr 21 02:32:36 PM PDT 24
Peak memory 182628 kb
Host smart-6772b864-e7ca-4d05-95c7-255e4a3129c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657833952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3657833952
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.79454247
Short name T361
Test name
Test status
Simulation time 153951622 ps
CPU time 0.76 seconds
Started Apr 21 02:29:40 PM PDT 24
Finished Apr 21 02:29:41 PM PDT 24
Peak memory 182412 kb
Host smart-0df8cc06-23f4-402f-bd62-e1bfa71b08d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79454247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.79454247
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.3718691941
Short name T406
Test name
Test status
Simulation time 19301557251 ps
CPU time 28.39 seconds
Started Apr 21 02:36:05 PM PDT 24
Finished Apr 21 02:36:33 PM PDT 24
Peak memory 182480 kb
Host smart-e5f2f56c-0250-40d3-89f0-6eced29f0879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718691941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3718691941
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.4242360783
Short name T275
Test name
Test status
Simulation time 610818601559 ps
CPU time 555.53 seconds
Started Apr 21 02:36:08 PM PDT 24
Finished Apr 21 02:45:24 PM PDT 24
Peak memory 190856 kb
Host smart-de6b6cef-5d3a-4992-a45f-375bcfa659f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242360783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.4242360783
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2697810124
Short name T230
Test name
Test status
Simulation time 551514553837 ps
CPU time 247.45 seconds
Started Apr 21 02:36:13 PM PDT 24
Finished Apr 21 02:40:20 PM PDT 24
Peak memory 190888 kb
Host smart-d3692822-d87f-4499-ad71-c04f56ef181d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697810124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2697810124
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1578219186
Short name T300
Test name
Test status
Simulation time 641080637847 ps
CPU time 435.13 seconds
Started Apr 21 02:36:11 PM PDT 24
Finished Apr 21 02:43:26 PM PDT 24
Peak memory 194176 kb
Host smart-910587a7-e726-4b1e-b039-a1acf0e29c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578219186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1578219186
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1095181784
Short name T156
Test name
Test status
Simulation time 3142855469 ps
CPU time 5.47 seconds
Started Apr 21 02:36:15 PM PDT 24
Finished Apr 21 02:36:21 PM PDT 24
Peak memory 182672 kb
Host smart-952e6e58-c1b0-473c-a399-cf3a411f64ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095181784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1095181784
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3611535701
Short name T409
Test name
Test status
Simulation time 14199847037 ps
CPU time 10.99 seconds
Started Apr 21 02:36:11 PM PDT 24
Finished Apr 21 02:36:23 PM PDT 24
Peak memory 182652 kb
Host smart-d08e76cd-fcdd-47fc-830b-e1393ff8b3b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611535701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3611535701
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1392259455
Short name T129
Test name
Test status
Simulation time 967751967461 ps
CPU time 671.97 seconds
Started Apr 21 02:36:15 PM PDT 24
Finished Apr 21 02:47:27 PM PDT 24
Peak memory 190876 kb
Host smart-2285e8f4-fbd2-45eb-a5a4-3091fb53bc68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392259455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1392259455
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1965548879
Short name T64
Test name
Test status
Simulation time 41750867475 ps
CPU time 68.25 seconds
Started Apr 21 02:36:30 PM PDT 24
Finished Apr 21 02:37:38 PM PDT 24
Peak memory 190872 kb
Host smart-dc1e2f1d-adf3-4966-8259-a0d08925229d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965548879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1965548879
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.931104321
Short name T76
Test name
Test status
Simulation time 198324133527 ps
CPU time 110.62 seconds
Started Apr 21 02:28:17 PM PDT 24
Finished Apr 21 02:30:08 PM PDT 24
Peak memory 182676 kb
Host smart-f3247ed4-6ed3-4091-9162-3a2e1db60d4a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931104321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.931104321
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.798821077
Short name T402
Test name
Test status
Simulation time 118274138792 ps
CPU time 174.29 seconds
Started Apr 21 02:28:16 PM PDT 24
Finished Apr 21 02:31:11 PM PDT 24
Peak memory 182676 kb
Host smart-372f511a-27aa-4cc9-8739-7f195ef55caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798821077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.798821077
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.4294453282
Short name T359
Test name
Test status
Simulation time 117217622649 ps
CPU time 45.13 seconds
Started Apr 21 02:28:15 PM PDT 24
Finished Apr 21 02:29:01 PM PDT 24
Peak memory 182452 kb
Host smart-ea47d6d4-9f04-4d79-a8c9-26a261300efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294453282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4294453282
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.644331448
Short name T283
Test name
Test status
Simulation time 31019738006 ps
CPU time 280.69 seconds
Started Apr 21 02:28:16 PM PDT 24
Finished Apr 21 02:32:57 PM PDT 24
Peak memory 182688 kb
Host smart-4921114c-382b-4354-a197-9d6ace41ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644331448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.644331448
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1274278048
Short name T16
Test name
Test status
Simulation time 58053111 ps
CPU time 0.82 seconds
Started Apr 21 02:28:24 PM PDT 24
Finished Apr 21 02:28:25 PM PDT 24
Peak memory 213256 kb
Host smart-933afff6-d352-46bc-8a51-6336857d348c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274278048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1274278048
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.504528595
Short name T317
Test name
Test status
Simulation time 111039428344 ps
CPU time 132.39 seconds
Started Apr 21 02:28:23 PM PDT 24
Finished Apr 21 02:30:35 PM PDT 24
Peak memory 192956 kb
Host smart-19322a42-8581-40f3-8e7a-9cbfc4adf0ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504528595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.504528595
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1207685631
Short name T298
Test name
Test status
Simulation time 1353837990474 ps
CPU time 852.5 seconds
Started Apr 21 02:29:44 PM PDT 24
Finished Apr 21 02:43:57 PM PDT 24
Peak memory 182676 kb
Host smart-40400617-450e-4b91-b817-7406c92dc860
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207685631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1207685631
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1656188340
Short name T375
Test name
Test status
Simulation time 903990328274 ps
CPU time 210.88 seconds
Started Apr 21 02:29:43 PM PDT 24
Finished Apr 21 02:33:14 PM PDT 24
Peak memory 182680 kb
Host smart-00ecc448-1615-4419-a2e4-1f336c4f9cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656188340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1656188340
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2728220810
Short name T301
Test name
Test status
Simulation time 175502630274 ps
CPU time 478.55 seconds
Started Apr 21 02:29:44 PM PDT 24
Finished Apr 21 02:37:43 PM PDT 24
Peak memory 190824 kb
Host smart-15e6226b-1cb2-4d4d-b9fe-55b37b0cf959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728220810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2728220810
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2450864013
Short name T441
Test name
Test status
Simulation time 41891735423 ps
CPU time 65.07 seconds
Started Apr 21 02:29:44 PM PDT 24
Finished Apr 21 02:30:50 PM PDT 24
Peak memory 182460 kb
Host smart-18d322fd-cd0d-4dfc-82cc-07d542add7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450864013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2450864013
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2048166331
Short name T38
Test name
Test status
Simulation time 68381034771 ps
CPU time 605.77 seconds
Started Apr 21 02:29:45 PM PDT 24
Finished Apr 21 02:39:51 PM PDT 24
Peak memory 212820 kb
Host smart-54894cd0-7158-4449-acbb-e0ba4b536015
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048166331 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2048166331
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3142900293
Short name T185
Test name
Test status
Simulation time 133340641932 ps
CPU time 246.43 seconds
Started Apr 21 02:29:58 PM PDT 24
Finished Apr 21 02:34:04 PM PDT 24
Peak memory 182624 kb
Host smart-a6c42852-9c67-4362-b10b-f353114086e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142900293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3142900293
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1443631936
Short name T6
Test name
Test status
Simulation time 22294804032 ps
CPU time 9.96 seconds
Started Apr 21 02:29:52 PM PDT 24
Finished Apr 21 02:30:02 PM PDT 24
Peak memory 182596 kb
Host smart-51612635-d623-4886-bdc5-7fb2e4741b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443631936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1443631936
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3569708363
Short name T144
Test name
Test status
Simulation time 519777171107 ps
CPU time 250.06 seconds
Started Apr 21 02:29:49 PM PDT 24
Finished Apr 21 02:33:59 PM PDT 24
Peak memory 190872 kb
Host smart-bcf84d8f-f74f-4282-8f55-d2eebae6a213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569708363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3569708363
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2606718423
Short name T232
Test name
Test status
Simulation time 35324052212 ps
CPU time 237.31 seconds
Started Apr 21 02:29:53 PM PDT 24
Finished Apr 21 02:33:50 PM PDT 24
Peak memory 182656 kb
Host smart-5568e6ad-bc79-4001-8682-0fca78747bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606718423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2606718423
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3207282971
Short name T320
Test name
Test status
Simulation time 302147599603 ps
CPU time 495.26 seconds
Started Apr 21 02:29:53 PM PDT 24
Finished Apr 21 02:38:09 PM PDT 24
Peak memory 182676 kb
Host smart-35c03d64-a8ba-47f0-a5d2-99d6eef5b8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207282971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3207282971
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1586142585
Short name T174
Test name
Test status
Simulation time 1461309525907 ps
CPU time 792.93 seconds
Started Apr 21 02:29:56 PM PDT 24
Finished Apr 21 02:43:10 PM PDT 24
Peak memory 182640 kb
Host smart-f490dd1e-c9fc-4dd1-841a-adc066767ce9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586142585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1586142585
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.2971678053
Short name T262
Test name
Test status
Simulation time 474360112956 ps
CPU time 1035.86 seconds
Started Apr 21 02:29:59 PM PDT 24
Finished Apr 21 02:47:15 PM PDT 24
Peak memory 190808 kb
Host smart-44202dc7-bb62-4d84-89e2-de2c52621334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971678053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2971678053
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2308081882
Short name T348
Test name
Test status
Simulation time 164503538901 ps
CPU time 1544.9 seconds
Started Apr 21 02:29:57 PM PDT 24
Finished Apr 21 02:55:42 PM PDT 24
Peak memory 190864 kb
Host smart-b3dae875-ccfc-46a6-ae25-072611443b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308081882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2308081882
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.155015658
Short name T58
Test name
Test status
Simulation time 380732999674 ps
CPU time 340.73 seconds
Started Apr 21 02:29:58 PM PDT 24
Finished Apr 21 02:35:39 PM PDT 24
Peak memory 190884 kb
Host smart-9257541c-57cc-4e54-95a8-835aca6a860b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155015658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
155015658
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2445326627
Short name T394
Test name
Test status
Simulation time 206094085487 ps
CPU time 82.16 seconds
Started Apr 21 02:29:57 PM PDT 24
Finished Apr 21 02:31:20 PM PDT 24
Peak memory 182676 kb
Host smart-ce609510-5def-49c1-be7b-304b13edac10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445326627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2445326627
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.720254914
Short name T256
Test name
Test status
Simulation time 640032738604 ps
CPU time 867.22 seconds
Started Apr 21 02:29:58 PM PDT 24
Finished Apr 21 02:44:26 PM PDT 24
Peak memory 190796 kb
Host smart-807a09e4-ce6b-4d64-9a50-059c34fcd6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720254914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.720254914
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.41337379
Short name T366
Test name
Test status
Simulation time 616251290 ps
CPU time 1.39 seconds
Started Apr 21 02:30:00 PM PDT 24
Finished Apr 21 02:30:02 PM PDT 24
Peak memory 190784 kb
Host smart-cdc12219-0c0d-4e90-8319-090453aaf6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41337379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.41337379
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3214158302
Short name T13
Test name
Test status
Simulation time 286413653433 ps
CPU time 1051.89 seconds
Started Apr 21 02:30:00 PM PDT 24
Finished Apr 21 02:47:32 PM PDT 24
Peak memory 213588 kb
Host smart-b04a3b9e-5186-4ec7-97d9-37e71200f390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214158302 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3214158302
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2455755582
Short name T263
Test name
Test status
Simulation time 560985325113 ps
CPU time 255.38 seconds
Started Apr 21 02:30:03 PM PDT 24
Finished Apr 21 02:34:19 PM PDT 24
Peak memory 182608 kb
Host smart-5a720235-e073-4ac9-9464-7f84c1e5704e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455755582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2455755582
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.554071461
Short name T371
Test name
Test status
Simulation time 47336665026 ps
CPU time 53.63 seconds
Started Apr 21 02:30:02 PM PDT 24
Finished Apr 21 02:30:56 PM PDT 24
Peak memory 182676 kb
Host smart-457fb406-7af1-4a5f-beba-c4e73f3939b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554071461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.554071461
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2142851127
Short name T43
Test name
Test status
Simulation time 156214318303 ps
CPU time 139.69 seconds
Started Apr 21 02:30:04 PM PDT 24
Finished Apr 21 02:32:24 PM PDT 24
Peak memory 194280 kb
Host smart-1535fddc-8b4f-4438-9711-2f243526aebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142851127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2142851127
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1617302270
Short name T372
Test name
Test status
Simulation time 115477547192 ps
CPU time 177.89 seconds
Started Apr 21 02:30:11 PM PDT 24
Finished Apr 21 02:33:09 PM PDT 24
Peak memory 193896 kb
Host smart-eeada21b-a60e-4a3a-8a1b-44de4acee9ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617302270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1617302270
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2220368952
Short name T203
Test name
Test status
Simulation time 248436159806 ps
CPU time 404.16 seconds
Started Apr 21 02:30:10 PM PDT 24
Finished Apr 21 02:36:55 PM PDT 24
Peak memory 182676 kb
Host smart-faf9c9b7-c904-4c83-a7ce-bf45243e7157
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220368952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2220368952
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.642862302
Short name T387
Test name
Test status
Simulation time 161254241569 ps
CPU time 269.56 seconds
Started Apr 21 02:30:10 PM PDT 24
Finished Apr 21 02:34:40 PM PDT 24
Peak memory 182628 kb
Host smart-432287d3-58ad-4c23-845f-313a21cd47a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642862302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.642862302
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2539008234
Short name T296
Test name
Test status
Simulation time 44960671158 ps
CPU time 25.62 seconds
Started Apr 21 02:30:10 PM PDT 24
Finished Apr 21 02:30:36 PM PDT 24
Peak memory 182664 kb
Host smart-d473ad09-0686-42b3-b9ab-7c0fa392ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539008234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2539008234
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3781865217
Short name T51
Test name
Test status
Simulation time 164034248643 ps
CPU time 180.75 seconds
Started Apr 21 02:30:14 PM PDT 24
Finished Apr 21 02:33:15 PM PDT 24
Peak memory 205504 kb
Host smart-de72e839-556c-4094-9562-2941f3e0693a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781865217 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3781865217
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2654381056
Short name T163
Test name
Test status
Simulation time 61926282928 ps
CPU time 32.44 seconds
Started Apr 21 02:30:15 PM PDT 24
Finished Apr 21 02:30:48 PM PDT 24
Peak memory 182608 kb
Host smart-75f3713d-0703-474e-9714-7ebed6a34d71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654381056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2654381056
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1215574670
Short name T447
Test name
Test status
Simulation time 90561870254 ps
CPU time 76.03 seconds
Started Apr 21 02:30:14 PM PDT 24
Finished Apr 21 02:31:30 PM PDT 24
Peak memory 182644 kb
Host smart-d023f3c9-7581-48fe-96ce-87c913d18fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215574670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1215574670
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2019801572
Short name T287
Test name
Test status
Simulation time 660437012349 ps
CPU time 136.37 seconds
Started Apr 21 02:30:17 PM PDT 24
Finished Apr 21 02:32:33 PM PDT 24
Peak memory 182660 kb
Host smart-40c9fd4a-8ac8-48f8-af10-8e83f08b9461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019801572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2019801572
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2560358243
Short name T225
Test name
Test status
Simulation time 31459689340 ps
CPU time 53.47 seconds
Started Apr 21 02:30:19 PM PDT 24
Finished Apr 21 02:31:12 PM PDT 24
Peak memory 182656 kb
Host smart-3f0886a6-320d-42e9-a2d6-b6c547fce16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560358243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2560358243
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.40399425
Short name T35
Test name
Test status
Simulation time 109465912979 ps
CPU time 288.58 seconds
Started Apr 21 02:30:17 PM PDT 24
Finished Apr 21 02:35:06 PM PDT 24
Peak memory 205548 kb
Host smart-4d7f7d66-f2d3-482e-a896-92dc0053b6b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40399425 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.40399425
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3959212817
Short name T2
Test name
Test status
Simulation time 558795220065 ps
CPU time 332.43 seconds
Started Apr 21 02:30:26 PM PDT 24
Finished Apr 21 02:35:58 PM PDT 24
Peak memory 182636 kb
Host smart-d3dd3eea-b46d-49cc-a242-fafad37c2d4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959212817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3959212817
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3855025759
Short name T1
Test name
Test status
Simulation time 126492956122 ps
CPU time 174.91 seconds
Started Apr 21 02:30:25 PM PDT 24
Finished Apr 21 02:33:20 PM PDT 24
Peak memory 182676 kb
Host smart-ecdaf37a-5691-4585-8849-9278a857bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855025759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3855025759
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3127964357
Short name T168
Test name
Test status
Simulation time 151359125207 ps
CPU time 155.15 seconds
Started Apr 21 02:30:21 PM PDT 24
Finished Apr 21 02:32:56 PM PDT 24
Peak memory 190884 kb
Host smart-12caa0e5-9d43-44eb-bdb2-b8ba6912e62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127964357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3127964357
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.4107444330
Short name T399
Test name
Test status
Simulation time 2170564740 ps
CPU time 2.11 seconds
Started Apr 21 02:30:26 PM PDT 24
Finished Apr 21 02:30:28 PM PDT 24
Peak memory 182648 kb
Host smart-f09cf4a9-b391-4d3d-927d-e02e3373a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107444330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4107444330
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.494770504
Short name T410
Test name
Test status
Simulation time 281412308499 ps
CPU time 411.78 seconds
Started Apr 21 02:30:30 PM PDT 24
Finished Apr 21 02:37:22 PM PDT 24
Peak memory 194100 kb
Host smart-80642606-6c0b-455f-a4ee-8c7d4ad86010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494770504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
494770504
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2242015528
Short name T41
Test name
Test status
Simulation time 97724603737 ps
CPU time 668.57 seconds
Started Apr 21 02:30:27 PM PDT 24
Finished Apr 21 02:41:36 PM PDT 24
Peak memory 205408 kb
Host smart-5c926dc6-76a2-4bcb-8b78-5a51839af954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242015528 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2242015528
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2335365328
Short name T259
Test name
Test status
Simulation time 7463943824971 ps
CPU time 1854.55 seconds
Started Apr 21 02:30:31 PM PDT 24
Finished Apr 21 03:01:26 PM PDT 24
Peak memory 182628 kb
Host smart-fa5b681c-30f1-4fda-86c5-bb0842081523
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335365328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2335365328
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1231579822
Short name T450
Test name
Test status
Simulation time 258342845914 ps
CPU time 170.07 seconds
Started Apr 21 02:30:35 PM PDT 24
Finished Apr 21 02:33:26 PM PDT 24
Peak memory 182544 kb
Host smart-e7223c8e-d588-4d89-b011-7672e7d584e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231579822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1231579822
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1901119793
Short name T309
Test name
Test status
Simulation time 63087828714 ps
CPU time 112.48 seconds
Started Apr 21 02:30:28 PM PDT 24
Finished Apr 21 02:32:21 PM PDT 24
Peak memory 190880 kb
Host smart-d030b963-c54c-4708-bb6c-bdc89a5be10e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901119793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1901119793
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.801820028
Short name T367
Test name
Test status
Simulation time 199029476 ps
CPU time 0.59 seconds
Started Apr 21 02:30:32 PM PDT 24
Finished Apr 21 02:30:32 PM PDT 24
Peak memory 182352 kb
Host smart-308f02d0-155a-4c7c-887d-7383b0e1077f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801820028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.801820028
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3900467195
Short name T438
Test name
Test status
Simulation time 16738490692 ps
CPU time 10.19 seconds
Started Apr 21 02:30:34 PM PDT 24
Finished Apr 21 02:30:45 PM PDT 24
Peak memory 182652 kb
Host smart-36075faf-ce42-442a-b60c-5e9c97a54adb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900467195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3900467195
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.127216555
Short name T434
Test name
Test status
Simulation time 225359470405 ps
CPU time 144.02 seconds
Started Apr 21 02:30:37 PM PDT 24
Finished Apr 21 02:33:02 PM PDT 24
Peak memory 182544 kb
Host smart-6d177ac0-e246-43fc-bfba-4e006e5684e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127216555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.127216555
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1603934278
Short name T284
Test name
Test status
Simulation time 39367633829 ps
CPU time 62.56 seconds
Started Apr 21 02:30:31 PM PDT 24
Finished Apr 21 02:31:34 PM PDT 24
Peak memory 182660 kb
Host smart-adcf7629-98e3-4af1-95d8-f31810fb248f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603934278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1603934278
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1916950614
Short name T302
Test name
Test status
Simulation time 192700010353 ps
CPU time 60.35 seconds
Started Apr 21 02:30:37 PM PDT 24
Finished Apr 21 02:31:38 PM PDT 24
Peak memory 182684 kb
Host smart-77b526df-7df7-4b64-bed6-03603939f40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916950614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1916950614
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3700491116
Short name T57
Test name
Test status
Simulation time 21561666283 ps
CPU time 51.71 seconds
Started Apr 21 02:30:41 PM PDT 24
Finished Apr 21 02:31:33 PM PDT 24
Peak memory 190876 kb
Host smart-6425a864-6344-42f0-9783-02abbe460e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700491116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3700491116
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.4003386991
Short name T449
Test name
Test status
Simulation time 571367389726 ps
CPU time 198.02 seconds
Started Apr 21 02:28:22 PM PDT 24
Finished Apr 21 02:31:41 PM PDT 24
Peak memory 182656 kb
Host smart-09a94d7e-6911-4252-9eb8-a053c1a97b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003386991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4003386991
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3977285945
Short name T226
Test name
Test status
Simulation time 82464091585 ps
CPU time 142.14 seconds
Started Apr 21 02:28:24 PM PDT 24
Finished Apr 21 02:30:46 PM PDT 24
Peak memory 190824 kb
Host smart-1dfc54e2-82cf-4101-9b69-70ba3a7a9aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977285945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3977285945
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3450047574
Short name T355
Test name
Test status
Simulation time 117079328114 ps
CPU time 1507.59 seconds
Started Apr 21 02:28:25 PM PDT 24
Finished Apr 21 02:53:33 PM PDT 24
Peak memory 190792 kb
Host smart-69461f97-ddeb-459a-ad7e-5dc970925f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450047574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3450047574
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1066290468
Short name T17
Test name
Test status
Simulation time 249945476 ps
CPU time 0.82 seconds
Started Apr 21 02:28:26 PM PDT 24
Finished Apr 21 02:28:27 PM PDT 24
Peak memory 213092 kb
Host smart-573acc1e-c73a-460b-969a-aea22af8ad82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066290468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1066290468
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1502997973
Short name T436
Test name
Test status
Simulation time 103350867120 ps
CPU time 191.35 seconds
Started Apr 21 02:28:23 PM PDT 24
Finished Apr 21 02:31:34 PM PDT 24
Peak memory 205516 kb
Host smart-4ae10426-a9b6-4ce2-bd04-a9e803da1ae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502997973 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1502997973
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2079823626
Short name T162
Test name
Test status
Simulation time 218535445146 ps
CPU time 241.61 seconds
Started Apr 21 02:30:50 PM PDT 24
Finished Apr 21 02:34:52 PM PDT 24
Peak memory 182656 kb
Host smart-f8a66965-2e84-4408-b200-e0c4099a271c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079823626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2079823626
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1115367988
Short name T385
Test name
Test status
Simulation time 45253426418 ps
CPU time 65.24 seconds
Started Apr 21 02:30:51 PM PDT 24
Finished Apr 21 02:31:56 PM PDT 24
Peak memory 182664 kb
Host smart-66a0116d-636e-4b59-b757-30d056a8c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115367988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1115367988
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3445140327
Short name T334
Test name
Test status
Simulation time 309235406133 ps
CPU time 136.57 seconds
Started Apr 21 02:30:55 PM PDT 24
Finished Apr 21 02:33:13 PM PDT 24
Peak memory 190864 kb
Host smart-fc888ef2-97b2-4269-b58e-71ab9990b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445140327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3445140327
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3690437114
Short name T356
Test name
Test status
Simulation time 333860492816 ps
CPU time 344.7 seconds
Started Apr 21 02:30:59 PM PDT 24
Finished Apr 21 02:36:44 PM PDT 24
Peak memory 193880 kb
Host smart-19f2918d-d6d3-4d45-a193-d694d531ed2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690437114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3690437114
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3001079425
Short name T270
Test name
Test status
Simulation time 395741236680 ps
CPU time 413.26 seconds
Started Apr 21 02:31:04 PM PDT 24
Finished Apr 21 02:37:58 PM PDT 24
Peak memory 182668 kb
Host smart-a0e1a575-556c-4aa3-bdb5-d61163168228
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001079425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3001079425
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1521969359
Short name T390
Test name
Test status
Simulation time 112185703467 ps
CPU time 56.12 seconds
Started Apr 21 02:31:04 PM PDT 24
Finished Apr 21 02:32:00 PM PDT 24
Peak memory 182664 kb
Host smart-40779e7e-72fe-42c7-9712-cac913887b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521969359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1521969359
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3946022265
Short name T79
Test name
Test status
Simulation time 356350428855 ps
CPU time 235.81 seconds
Started Apr 21 02:31:01 PM PDT 24
Finished Apr 21 02:34:57 PM PDT 24
Peak memory 194232 kb
Host smart-ca55fbf6-b81b-4c81-871e-b2bacfeb287d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946022265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3946022265
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3573421080
Short name T349
Test name
Test status
Simulation time 12903579067 ps
CPU time 22.2 seconds
Started Apr 21 02:31:03 PM PDT 24
Finished Apr 21 02:31:26 PM PDT 24
Peak memory 182660 kb
Host smart-ee276eb4-de91-4954-bb2d-a5686dabddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573421080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3573421080
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3200389668
Short name T179
Test name
Test status
Simulation time 371972353435 ps
CPU time 577.2 seconds
Started Apr 21 02:31:12 PM PDT 24
Finished Apr 21 02:40:50 PM PDT 24
Peak memory 190844 kb
Host smart-e9615151-b21f-4a19-a91b-af094ad73a3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200389668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3200389668
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3003892755
Short name T344
Test name
Test status
Simulation time 231566935330 ps
CPU time 349.61 seconds
Started Apr 21 02:31:13 PM PDT 24
Finished Apr 21 02:37:03 PM PDT 24
Peak memory 182644 kb
Host smart-cd8df554-f8f4-4f75-8188-b3398be18c3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003892755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3003892755
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2649709833
Short name T443
Test name
Test status
Simulation time 101667493252 ps
CPU time 158.17 seconds
Started Apr 21 02:31:13 PM PDT 24
Finished Apr 21 02:33:51 PM PDT 24
Peak memory 182632 kb
Host smart-7e2359c2-fbd6-4788-8982-3e85d5479261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649709833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2649709833
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.4288103685
Short name T321
Test name
Test status
Simulation time 103858517639 ps
CPU time 733.06 seconds
Started Apr 21 02:31:08 PM PDT 24
Finished Apr 21 02:43:21 PM PDT 24
Peak memory 190860 kb
Host smart-a7676719-34e1-4076-b340-dec843106798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288103685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4288103685
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1434780592
Short name T241
Test name
Test status
Simulation time 32851512997 ps
CPU time 31.42 seconds
Started Apr 21 02:31:12 PM PDT 24
Finished Apr 21 02:31:44 PM PDT 24
Peak memory 182664 kb
Host smart-afb644c7-24d5-4101-b9c3-9b3034ac5871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434780592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1434780592
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2310327435
Short name T150
Test name
Test status
Simulation time 117912221871 ps
CPU time 416.97 seconds
Started Apr 21 02:31:11 PM PDT 24
Finished Apr 21 02:38:09 PM PDT 24
Peak memory 195552 kb
Host smart-b0db6cef-808c-497b-b2f1-1b953d8063cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310327435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2310327435
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.424336781
Short name T364
Test name
Test status
Simulation time 13192789035 ps
CPU time 18.74 seconds
Started Apr 21 02:31:14 PM PDT 24
Finished Apr 21 02:31:33 PM PDT 24
Peak memory 182656 kb
Host smart-9d06f8de-4d41-4789-a38a-f4e020dcf204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424336781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.424336781
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3370751715
Short name T78
Test name
Test status
Simulation time 155346805993 ps
CPU time 406.31 seconds
Started Apr 21 02:31:14 PM PDT 24
Finished Apr 21 02:38:00 PM PDT 24
Peak memory 190888 kb
Host smart-40507fe0-eae1-48f2-8844-525e8180b3de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370751715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3370751715
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3766079119
Short name T175
Test name
Test status
Simulation time 23926132740 ps
CPU time 85.69 seconds
Started Apr 21 02:31:15 PM PDT 24
Finished Apr 21 02:32:41 PM PDT 24
Peak memory 182676 kb
Host smart-c0789b07-241d-41a2-82d7-79726da24af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766079119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3766079119
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.208260124
Short name T117
Test name
Test status
Simulation time 1848880195665 ps
CPU time 1862.4 seconds
Started Apr 21 02:31:16 PM PDT 24
Finished Apr 21 03:02:19 PM PDT 24
Peak memory 190884 kb
Host smart-cf5c7a9e-12c2-4836-b809-feb16c63f13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208260124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
208260124
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2319138174
Short name T113
Test name
Test status
Simulation time 546903690910 ps
CPU time 283.58 seconds
Started Apr 21 02:31:17 PM PDT 24
Finished Apr 21 02:36:01 PM PDT 24
Peak memory 182676 kb
Host smart-ca5bc918-de73-4c93-84f7-bd75946ca298
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319138174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2319138174
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.1147430611
Short name T324
Test name
Test status
Simulation time 58578576480 ps
CPU time 89.11 seconds
Started Apr 21 02:31:18 PM PDT 24
Finished Apr 21 02:32:48 PM PDT 24
Peak memory 190812 kb
Host smart-8ae3dff6-6958-4f24-a95e-a16f9bbe3927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147430611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1147430611
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4092888603
Short name T124
Test name
Test status
Simulation time 161132618269 ps
CPU time 497.26 seconds
Started Apr 21 02:31:22 PM PDT 24
Finished Apr 21 02:39:39 PM PDT 24
Peak memory 190820 kb
Host smart-e811bcf1-b68b-4c8e-b446-4a17b545ae24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092888603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4092888603
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1930527575
Short name T247
Test name
Test status
Simulation time 6176785790 ps
CPU time 10.31 seconds
Started Apr 21 02:31:26 PM PDT 24
Finished Apr 21 02:31:36 PM PDT 24
Peak memory 182652 kb
Host smart-17c99e83-337c-42a0-ae62-ad6dfb492f40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930527575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1930527575
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1147498042
Short name T369
Test name
Test status
Simulation time 298591914276 ps
CPU time 228.05 seconds
Started Apr 21 02:31:26 PM PDT 24
Finished Apr 21 02:35:14 PM PDT 24
Peak memory 182672 kb
Host smart-da6dca20-1c4f-4e05-b7c0-102a9a0dcf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147498042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1147498042
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2080556877
Short name T145
Test name
Test status
Simulation time 119439865630 ps
CPU time 255.62 seconds
Started Apr 21 02:31:22 PM PDT 24
Finished Apr 21 02:35:38 PM PDT 24
Peak memory 190876 kb
Host smart-a8a73d5b-3b2c-4436-a03e-a87ef8f64398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080556877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2080556877
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1771883239
Short name T384
Test name
Test status
Simulation time 119830575 ps
CPU time 0.62 seconds
Started Apr 21 02:31:24 PM PDT 24
Finished Apr 21 02:31:25 PM PDT 24
Peak memory 182400 kb
Host smart-26cfa1c6-8fb5-4de0-8b5a-0c9db49b57a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771883239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1771883239
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.472627934
Short name T426
Test name
Test status
Simulation time 211796747126 ps
CPU time 180.32 seconds
Started Apr 21 02:31:29 PM PDT 24
Finished Apr 21 02:34:30 PM PDT 24
Peak memory 182664 kb
Host smart-7bf0dbe9-6f96-4f70-b0fd-bbc6b6887510
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472627934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.472627934
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2553541575
Short name T362
Test name
Test status
Simulation time 444341261678 ps
CPU time 181.7 seconds
Started Apr 21 02:31:28 PM PDT 24
Finished Apr 21 02:34:29 PM PDT 24
Peak memory 182588 kb
Host smart-a58778a4-959d-4971-a863-1e4d72caaf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553541575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2553541575
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1074942983
Short name T427
Test name
Test status
Simulation time 47397116191 ps
CPU time 78.32 seconds
Started Apr 21 02:31:28 PM PDT 24
Finished Apr 21 02:32:47 PM PDT 24
Peak memory 182632 kb
Host smart-7e6b8f63-eb72-408e-aa52-67fc1a2d0e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074942983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1074942983
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.114382916
Short name T422
Test name
Test status
Simulation time 228336487329 ps
CPU time 491.06 seconds
Started Apr 21 02:31:31 PM PDT 24
Finished Apr 21 02:39:42 PM PDT 24
Peak memory 190792 kb
Host smart-2da2cc9c-001b-4e5b-9c9e-d9d9ec6fe93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114382916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.114382916
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3936832968
Short name T96
Test name
Test status
Simulation time 99690636484 ps
CPU time 800.47 seconds
Started Apr 21 02:31:31 PM PDT 24
Finished Apr 21 02:44:52 PM PDT 24
Peak memory 205496 kb
Host smart-ae83d63c-f1e5-43a4-aa5c-5e0a9c94d9fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936832968 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3936832968
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1816299374
Short name T421
Test name
Test status
Simulation time 470226595368 ps
CPU time 421.03 seconds
Started Apr 21 02:31:43 PM PDT 24
Finished Apr 21 02:38:45 PM PDT 24
Peak memory 182652 kb
Host smart-f17512b4-603e-4934-8cb7-e7a854c1aa8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816299374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1816299374
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3121830556
Short name T370
Test name
Test status
Simulation time 96693972961 ps
CPU time 156.75 seconds
Started Apr 21 02:31:43 PM PDT 24
Finished Apr 21 02:34:20 PM PDT 24
Peak memory 182676 kb
Host smart-ae03de77-41ea-4a29-8c6a-e3030da4cc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121830556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3121830556
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2918539219
Short name T265
Test name
Test status
Simulation time 104757423827 ps
CPU time 934.27 seconds
Started Apr 21 02:31:37 PM PDT 24
Finished Apr 21 02:47:13 PM PDT 24
Peak memory 190860 kb
Host smart-a451b35d-0995-46e2-b613-ce6d83ef0f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918539219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2918539219
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3462200175
Short name T308
Test name
Test status
Simulation time 193706821649 ps
CPU time 64.89 seconds
Started Apr 21 02:31:44 PM PDT 24
Finished Apr 21 02:32:49 PM PDT 24
Peak memory 190868 kb
Host smart-f5b71a17-38d9-460c-b62d-170ba4f863d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462200175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3462200175
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.866187645
Short name T271
Test name
Test status
Simulation time 10167053908 ps
CPU time 16.37 seconds
Started Apr 21 02:31:50 PM PDT 24
Finished Apr 21 02:32:07 PM PDT 24
Peak memory 182680 kb
Host smart-3f0c0990-f263-4392-b43c-37192b350803
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866187645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.866187645
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.491157341
Short name T383
Test name
Test status
Simulation time 592948098813 ps
CPU time 218.2 seconds
Started Apr 21 02:31:48 PM PDT 24
Finished Apr 21 02:35:27 PM PDT 24
Peak memory 182664 kb
Host smart-1b2498d4-2714-4be2-820c-676552034db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491157341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.491157341
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2147502023
Short name T439
Test name
Test status
Simulation time 594514454510 ps
CPU time 110.77 seconds
Started Apr 21 02:31:46 PM PDT 24
Finished Apr 21 02:33:37 PM PDT 24
Peak memory 190812 kb
Host smart-9a621f4d-abb4-4971-a313-ff59c82a4001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147502023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2147502023
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1325297155
Short name T21
Test name
Test status
Simulation time 60296736401 ps
CPU time 196.79 seconds
Started Apr 21 02:31:49 PM PDT 24
Finished Apr 21 02:35:06 PM PDT 24
Peak memory 190880 kb
Host smart-3302ee4e-09bb-4a3c-9636-5fddc0548964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325297155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1325297155
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2691109013
Short name T9
Test name
Test status
Simulation time 165827327039 ps
CPU time 342.53 seconds
Started Apr 21 02:31:51 PM PDT 24
Finished Apr 21 02:37:34 PM PDT 24
Peak memory 190860 kb
Host smart-97ba9b30-be89-41e0-bc9c-90b0754b4d64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691109013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2691109013
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.996688112
Short name T304
Test name
Test status
Simulation time 12309882580 ps
CPU time 21.35 seconds
Started Apr 21 02:31:55 PM PDT 24
Finished Apr 21 02:32:17 PM PDT 24
Peak memory 182676 kb
Host smart-a82676f9-5749-4318-ac39-1c328d30c02e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996688112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.996688112
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random.2631807755
Short name T135
Test name
Test status
Simulation time 21417455765 ps
CPU time 18.95 seconds
Started Apr 21 02:31:51 PM PDT 24
Finished Apr 21 02:32:11 PM PDT 24
Peak memory 182684 kb
Host smart-c8cf0bb8-cff0-48fd-b42b-35fb325753fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631807755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2631807755
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1017520512
Short name T435
Test name
Test status
Simulation time 71168434 ps
CPU time 0.62 seconds
Started Apr 21 02:31:55 PM PDT 24
Finished Apr 21 02:31:56 PM PDT 24
Peak memory 182404 kb
Host smart-9b367e25-be5a-4ff7-8dc8-a2341a27fe9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017520512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1017520512
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.1612905703
Short name T36
Test name
Test status
Simulation time 66667739778 ps
CPU time 494.92 seconds
Started Apr 21 02:32:24 PM PDT 24
Finished Apr 21 02:40:39 PM PDT 24
Peak memory 205500 kb
Host smart-2a4b09d0-a052-4721-b231-6e6c73381558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612905703 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.1612905703
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1711600523
Short name T75
Test name
Test status
Simulation time 377682750906 ps
CPU time 367.16 seconds
Started Apr 21 02:28:30 PM PDT 24
Finished Apr 21 02:34:38 PM PDT 24
Peak memory 182672 kb
Host smart-227540b5-fee2-4503-906d-541425db1e4a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711600523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1711600523
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2246614234
Short name T377
Test name
Test status
Simulation time 452928449685 ps
CPU time 219.35 seconds
Started Apr 21 02:28:31 PM PDT 24
Finished Apr 21 02:32:11 PM PDT 24
Peak memory 182648 kb
Host smart-c6eb5e97-a589-4a84-996f-fa532e47b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246614234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2246614234
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.497601163
Short name T363
Test name
Test status
Simulation time 259517737 ps
CPU time 0.66 seconds
Started Apr 21 02:28:31 PM PDT 24
Finished Apr 21 02:28:32 PM PDT 24
Peak memory 182356 kb
Host smart-10d33066-0835-4448-a5c2-77d7c8b6a7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497601163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.497601163
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3528601200
Short name T15
Test name
Test status
Simulation time 37403848 ps
CPU time 0.75 seconds
Started Apr 21 02:28:30 PM PDT 24
Finished Apr 21 02:28:31 PM PDT 24
Peak memory 213088 kb
Host smart-427c0044-8827-40e3-a36b-c644e7bd0520
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528601200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3528601200
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3332707099
Short name T242
Test name
Test status
Simulation time 1091402501336 ps
CPU time 1545.84 seconds
Started Apr 21 02:28:30 PM PDT 24
Finished Apr 21 02:54:17 PM PDT 24
Peak memory 195316 kb
Host smart-1efad9d7-5dbb-4a1a-b538-80c2507b31a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332707099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3332707099
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1409151270
Short name T125
Test name
Test status
Simulation time 249712784236 ps
CPU time 443.47 seconds
Started Apr 21 02:32:03 PM PDT 24
Finished Apr 21 02:39:27 PM PDT 24
Peak memory 182656 kb
Host smart-b7c39a63-bb8e-4e27-b974-bad53b5af610
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409151270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1409151270
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_random.1338459300
Short name T306
Test name
Test status
Simulation time 456669486668 ps
CPU time 266.87 seconds
Started Apr 21 02:31:58 PM PDT 24
Finished Apr 21 02:36:25 PM PDT 24
Peak memory 190880 kb
Host smart-537bb0ec-d48f-4373-a043-cf303fc0440f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338459300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1338459300
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1840052304
Short name T428
Test name
Test status
Simulation time 13084044585 ps
CPU time 14.86 seconds
Started Apr 21 02:32:03 PM PDT 24
Finished Apr 21 02:32:18 PM PDT 24
Peak memory 182676 kb
Host smart-bd93a4f4-39ce-4e88-8ce5-13495351f347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840052304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1840052304
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3230995144
Short name T50
Test name
Test status
Simulation time 256769413817 ps
CPU time 551.81 seconds
Started Apr 21 02:32:04 PM PDT 24
Finished Apr 21 02:41:16 PM PDT 24
Peak memory 206160 kb
Host smart-e10e61bb-0748-4419-b6e2-1e2327cce124
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230995144 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3230995144
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4187266970
Short name T138
Test name
Test status
Simulation time 299677143147 ps
CPU time 540.82 seconds
Started Apr 21 02:32:05 PM PDT 24
Finished Apr 21 02:41:06 PM PDT 24
Peak memory 182684 kb
Host smart-d8d0ae34-1804-4f37-84ef-4eeee0d94f13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187266970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4187266970
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2155882644
Short name T398
Test name
Test status
Simulation time 70918197938 ps
CPU time 102.29 seconds
Started Apr 21 02:32:06 PM PDT 24
Finished Apr 21 02:33:49 PM PDT 24
Peak memory 182668 kb
Host smart-5a979289-3286-40f9-a768-e2e23ec9c96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155882644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2155882644
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1872060731
Short name T243
Test name
Test status
Simulation time 182038620276 ps
CPU time 455.17 seconds
Started Apr 21 02:32:05 PM PDT 24
Finished Apr 21 02:39:41 PM PDT 24
Peak memory 190828 kb
Host smart-85102d38-a686-454a-babe-3a0ac2522d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872060731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1872060731
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.389279555
Short name T10
Test name
Test status
Simulation time 106710692864 ps
CPU time 343.54 seconds
Started Apr 21 02:32:04 PM PDT 24
Finished Apr 21 02:37:48 PM PDT 24
Peak memory 190832 kb
Host smart-3fc76acd-f4f2-4589-9d43-42a617a8e57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389279555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.389279555
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3966646869
Short name T223
Test name
Test status
Simulation time 2020746239541 ps
CPU time 1049.1 seconds
Started Apr 21 02:32:08 PM PDT 24
Finished Apr 21 02:49:38 PM PDT 24
Peak memory 182664 kb
Host smart-1438b5fa-426a-4343-b83c-a45a423c464d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966646869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3966646869
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3042037614
Short name T382
Test name
Test status
Simulation time 199491737660 ps
CPU time 303.5 seconds
Started Apr 21 02:32:09 PM PDT 24
Finished Apr 21 02:37:12 PM PDT 24
Peak memory 182680 kb
Host smart-331d664d-a09a-4782-8ff0-a6d2cea072cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042037614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3042037614
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.596571176
Short name T352
Test name
Test status
Simulation time 66137240415 ps
CPU time 286.72 seconds
Started Apr 21 02:32:14 PM PDT 24
Finished Apr 21 02:37:01 PM PDT 24
Peak memory 190852 kb
Host smart-c6aa3ad4-722f-43f4-956e-dee2af46d7d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596571176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.596571176
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.20483401
Short name T122
Test name
Test status
Simulation time 132531039493 ps
CPU time 938.06 seconds
Started Apr 21 02:32:13 PM PDT 24
Finished Apr 21 02:47:51 PM PDT 24
Peak memory 190880 kb
Host smart-8a13c252-b968-4b0b-93b8-4d1105abd7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20483401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.20483401
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3182796375
Short name T423
Test name
Test status
Simulation time 101371062466 ps
CPU time 163.93 seconds
Started Apr 21 02:32:13 PM PDT 24
Finished Apr 21 02:34:57 PM PDT 24
Peak memory 194216 kb
Host smart-b9cc9337-817a-4e38-bb55-c26ea3812bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182796375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3182796375
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.332581107
Short name T420
Test name
Test status
Simulation time 55877159657 ps
CPU time 88.01 seconds
Started Apr 21 02:32:16 PM PDT 24
Finished Apr 21 02:33:44 PM PDT 24
Peak memory 182672 kb
Host smart-c202c567-3070-47a0-8e85-326ff6d5d533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332581107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.332581107
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.620521928
Short name T134
Test name
Test status
Simulation time 323178811130 ps
CPU time 283.69 seconds
Started Apr 21 02:32:14 PM PDT 24
Finished Apr 21 02:36:58 PM PDT 24
Peak memory 194140 kb
Host smart-7425a94f-feea-4da2-9019-d9e1785cc4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620521928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.620521928
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.742751414
Short name T294
Test name
Test status
Simulation time 291996915693 ps
CPU time 565.76 seconds
Started Apr 21 02:32:23 PM PDT 24
Finished Apr 21 02:41:49 PM PDT 24
Peak memory 190868 kb
Host smart-dab7dfba-1954-4694-b714-39e2a4f5fd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742751414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.742751414
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2177895157
Short name T154
Test name
Test status
Simulation time 2069597472241 ps
CPU time 849.85 seconds
Started Apr 21 02:32:28 PM PDT 24
Finished Apr 21 02:46:39 PM PDT 24
Peak memory 190880 kb
Host smart-c7bd069f-47e0-4d6d-bbea-2b8567db37ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177895157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2177895157
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1501282822
Short name T414
Test name
Test status
Simulation time 14213750214 ps
CPU time 64.49 seconds
Started Apr 21 02:32:24 PM PDT 24
Finished Apr 21 02:33:29 PM PDT 24
Peak memory 194616 kb
Host smart-16f5bf2a-c7fe-491a-9153-25b0680ea0cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501282822 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1501282822
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3060237506
Short name T178
Test name
Test status
Simulation time 1009134044550 ps
CPU time 471.1 seconds
Started Apr 21 02:32:32 PM PDT 24
Finished Apr 21 02:40:23 PM PDT 24
Peak memory 182684 kb
Host smart-d63fb931-0099-4c47-bb4d-22018d27318a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060237506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3060237506
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2737221383
Short name T374
Test name
Test status
Simulation time 154234705358 ps
CPU time 113.46 seconds
Started Apr 21 02:32:29 PM PDT 24
Finished Apr 21 02:34:23 PM PDT 24
Peak memory 182600 kb
Host smart-0a6badfb-552d-4405-8d55-9c5904006f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737221383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2737221383
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.4243899063
Short name T276
Test name
Test status
Simulation time 73320663461 ps
CPU time 182.51 seconds
Started Apr 21 02:32:30 PM PDT 24
Finished Apr 21 02:35:32 PM PDT 24
Peak memory 190844 kb
Host smart-0160ba39-b8b3-401c-a017-be1f844207a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243899063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4243899063
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2520260981
Short name T11
Test name
Test status
Simulation time 62867886621 ps
CPU time 361.93 seconds
Started Apr 21 02:32:38 PM PDT 24
Finished Apr 21 02:38:40 PM PDT 24
Peak memory 205460 kb
Host smart-4e5b413b-17c9-4f28-937b-b98264f596bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520260981 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2520260981
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.776879778
Short name T405
Test name
Test status
Simulation time 181310774916 ps
CPU time 305.26 seconds
Started Apr 21 02:32:39 PM PDT 24
Finished Apr 21 02:37:44 PM PDT 24
Peak memory 182612 kb
Host smart-33f24e8f-2fb7-4a15-aa9c-d1ca423b012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776879778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.776879778
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1782067268
Short name T165
Test name
Test status
Simulation time 173396088311 ps
CPU time 175.87 seconds
Started Apr 21 02:32:37 PM PDT 24
Finished Apr 21 02:35:34 PM PDT 24
Peak memory 190856 kb
Host smart-57800173-d87c-4166-9ab7-03e8dd211a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782067268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1782067268
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3219597247
Short name T23
Test name
Test status
Simulation time 36231869657 ps
CPU time 54.16 seconds
Started Apr 21 02:32:38 PM PDT 24
Finished Apr 21 02:33:32 PM PDT 24
Peak memory 190836 kb
Host smart-c5981020-9567-4b84-9c54-a2f74347a949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219597247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3219597247
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.615758045
Short name T12
Test name
Test status
Simulation time 24008787551 ps
CPU time 179.91 seconds
Started Apr 21 02:32:39 PM PDT 24
Finished Apr 21 02:35:39 PM PDT 24
Peak memory 197272 kb
Host smart-c75b5287-4d8d-4b3f-b442-60af0896674d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615758045 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.615758045
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2505685484
Short name T373
Test name
Test status
Simulation time 339066037004 ps
CPU time 205.39 seconds
Started Apr 21 02:32:45 PM PDT 24
Finished Apr 21 02:36:11 PM PDT 24
Peak memory 182656 kb
Host smart-e2f0f1e9-43d9-4962-8c91-4bdba2730702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505685484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2505685484
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1430165681
Short name T233
Test name
Test status
Simulation time 888719529433 ps
CPU time 2655.14 seconds
Started Apr 21 02:32:39 PM PDT 24
Finished Apr 21 03:16:55 PM PDT 24
Peak memory 190872 kb
Host smart-06dcd208-bddc-4889-a357-26957a1ff948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430165681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1430165681
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3377356010
Short name T268
Test name
Test status
Simulation time 166711442371 ps
CPU time 73.81 seconds
Started Apr 21 02:32:47 PM PDT 24
Finished Apr 21 02:34:02 PM PDT 24
Peak memory 182644 kb
Host smart-c15d1e1b-acd8-41a6-a27f-5d15f342b6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377356010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3377356010
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.806086484
Short name T211
Test name
Test status
Simulation time 153042655203 ps
CPU time 1522.55 seconds
Started Apr 21 02:32:50 PM PDT 24
Finished Apr 21 02:58:13 PM PDT 24
Peak memory 190872 kb
Host smart-fe385716-c306-4829-8d4f-8f8b7e7550ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806086484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
806086484
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3068949277
Short name T176
Test name
Test status
Simulation time 238648765815 ps
CPU time 428.98 seconds
Started Apr 21 02:32:50 PM PDT 24
Finished Apr 21 02:40:00 PM PDT 24
Peak memory 182664 kb
Host smart-726ec37a-80c3-4438-98b7-6a2f43270d11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068949277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3068949277
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2609104117
Short name T440
Test name
Test status
Simulation time 143910884775 ps
CPU time 204.68 seconds
Started Apr 21 02:32:50 PM PDT 24
Finished Apr 21 02:36:15 PM PDT 24
Peak memory 182636 kb
Host smart-6b2eff8b-6eb1-4342-bc5c-54d8b9d2bf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609104117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2609104117
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1353894505
Short name T289
Test name
Test status
Simulation time 188824552247 ps
CPU time 169.66 seconds
Started Apr 21 02:32:50 PM PDT 24
Finished Apr 21 02:35:40 PM PDT 24
Peak memory 190856 kb
Host smart-7b51708c-588d-4002-b728-f4c2ca8d10ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353894505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1353894505
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3445808871
Short name T396
Test name
Test status
Simulation time 15256606358 ps
CPU time 5.65 seconds
Started Apr 21 02:32:54 PM PDT 24
Finished Apr 21 02:33:00 PM PDT 24
Peak memory 191572 kb
Host smart-e0f3bcea-8bc2-4350-9104-337987717c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445808871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3445808871
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2589111294
Short name T376
Test name
Test status
Simulation time 21596956 ps
CPU time 0.55 seconds
Started Apr 21 02:32:58 PM PDT 24
Finished Apr 21 02:32:59 PM PDT 24
Peak memory 181964 kb
Host smart-136d5f89-6042-41dd-83e5-11c4668838e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589111294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2589111294
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1285245813
Short name T46
Test name
Test status
Simulation time 178906626335 ps
CPU time 270.24 seconds
Started Apr 21 02:32:59 PM PDT 24
Finished Apr 21 02:37:29 PM PDT 24
Peak memory 182632 kb
Host smart-8792f178-3b43-4c74-8d20-2ba0f2335b00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285245813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1285245813
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3475001475
Short name T419
Test name
Test status
Simulation time 112518629403 ps
CPU time 184.52 seconds
Started Apr 21 02:32:57 PM PDT 24
Finished Apr 21 02:36:02 PM PDT 24
Peak memory 182612 kb
Host smart-42847f42-d96b-4587-a9cb-b740dfad30c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475001475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3475001475
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.247516918
Short name T173
Test name
Test status
Simulation time 316221717010 ps
CPU time 137.73 seconds
Started Apr 21 02:32:57 PM PDT 24
Finished Apr 21 02:35:15 PM PDT 24
Peak memory 190872 kb
Host smart-2cf0badd-083e-468c-893d-62284dbf5042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247516918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.247516918
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3335620493
Short name T437
Test name
Test status
Simulation time 135779398066 ps
CPU time 216.82 seconds
Started Apr 21 02:33:14 PM PDT 24
Finished Apr 21 02:36:52 PM PDT 24
Peak memory 182652 kb
Host smart-83e2596d-7604-4daa-ab30-ac37f82ba59b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335620493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3335620493
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1710934026
Short name T368
Test name
Test status
Simulation time 623121651653 ps
CPU time 252.38 seconds
Started Apr 21 02:33:09 PM PDT 24
Finished Apr 21 02:37:21 PM PDT 24
Peak memory 182648 kb
Host smart-177af6e6-34fa-4c96-8dd9-e2afaaa79cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710934026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1710934026
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1017753206
Short name T142
Test name
Test status
Simulation time 263859512422 ps
CPU time 543.35 seconds
Started Apr 21 02:33:06 PM PDT 24
Finished Apr 21 02:42:10 PM PDT 24
Peak memory 190840 kb
Host smart-24071811-e283-4da2-8662-f51bb273989d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017753206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1017753206
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3753540134
Short name T433
Test name
Test status
Simulation time 146109983294 ps
CPU time 236.28 seconds
Started Apr 21 02:33:13 PM PDT 24
Finished Apr 21 02:37:10 PM PDT 24
Peak memory 194424 kb
Host smart-ba91cb6d-85fc-44a8-8487-0446d332f172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753540134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3753540134
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3774143293
Short name T360
Test name
Test status
Simulation time 20001064026 ps
CPU time 19.91 seconds
Started Apr 21 02:28:38 PM PDT 24
Finished Apr 21 02:28:58 PM PDT 24
Peak memory 182684 kb
Host smart-9f0e5fba-32f1-44d3-84b1-201dd4fb76c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774143293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3774143293
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1649952507
Short name T403
Test name
Test status
Simulation time 825757321342 ps
CPU time 248.7 seconds
Started Apr 21 02:28:37 PM PDT 24
Finished Apr 21 02:32:46 PM PDT 24
Peak memory 182664 kb
Host smart-ec153314-ed5c-4304-9005-2f2cc3b0f0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649952507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1649952507
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1202417542
Short name T278
Test name
Test status
Simulation time 129858286526 ps
CPU time 125.99 seconds
Started Apr 21 02:28:37 PM PDT 24
Finished Apr 21 02:30:44 PM PDT 24
Peak memory 190804 kb
Host smart-456d00ec-fd72-45eb-a71c-0339dd9d24a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202417542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1202417542
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.269949414
Short name T401
Test name
Test status
Simulation time 44218564964 ps
CPU time 71.85 seconds
Started Apr 21 02:28:37 PM PDT 24
Finished Apr 21 02:29:50 PM PDT 24
Peak memory 182636 kb
Host smart-ccced5cb-64ae-431a-af3d-e3ca5fb490e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269949414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.269949414
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1927908003
Short name T305
Test name
Test status
Simulation time 416715927427 ps
CPU time 936.02 seconds
Started Apr 21 02:28:42 PM PDT 24
Finished Apr 21 02:44:19 PM PDT 24
Peak memory 190860 kb
Host smart-bac16ee2-6d2e-4549-b82c-f47cb3ae1ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927908003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1927908003
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.4249345152
Short name T97
Test name
Test status
Simulation time 293807952552 ps
CPU time 429.08 seconds
Started Apr 21 02:28:38 PM PDT 24
Finished Apr 21 02:35:48 PM PDT 24
Peak memory 205568 kb
Host smart-c215ac19-3c16-4df9-95e8-6616c074effb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249345152 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.4249345152
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2018153279
Short name T267
Test name
Test status
Simulation time 553183209147 ps
CPU time 2595.28 seconds
Started Apr 21 02:33:13 PM PDT 24
Finished Apr 21 03:16:29 PM PDT 24
Peak memory 190884 kb
Host smart-d1ead889-e57e-47f1-9284-3415afef3a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018153279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2018153279
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1124824414
Short name T404
Test name
Test status
Simulation time 303973914332 ps
CPU time 171.1 seconds
Started Apr 21 02:33:18 PM PDT 24
Finished Apr 21 02:36:10 PM PDT 24
Peak memory 190852 kb
Host smart-24c10a4b-b15c-4a58-904a-869847f61172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124824414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1124824414
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1907503646
Short name T316
Test name
Test status
Simulation time 185049898971 ps
CPU time 102.15 seconds
Started Apr 21 02:33:19 PM PDT 24
Finished Apr 21 02:35:01 PM PDT 24
Peak memory 182680 kb
Host smart-874cb900-87eb-44e0-af7d-619997fc2394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907503646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1907503646
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.119341608
Short name T258
Test name
Test status
Simulation time 92473054307 ps
CPU time 186.78 seconds
Started Apr 21 02:33:20 PM PDT 24
Finished Apr 21 02:36:28 PM PDT 24
Peak memory 190812 kb
Host smart-082637fb-9bc7-472a-ab7f-0d16b29e5919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119341608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.119341608
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3355412686
Short name T314
Test name
Test status
Simulation time 201630988701 ps
CPU time 161.31 seconds
Started Apr 21 02:33:18 PM PDT 24
Finished Apr 21 02:36:00 PM PDT 24
Peak memory 190888 kb
Host smart-c7ff7624-29de-4d96-a488-8b8a5a95d433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355412686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3355412686
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.865263927
Short name T62
Test name
Test status
Simulation time 62182206212 ps
CPU time 63.92 seconds
Started Apr 21 02:33:19 PM PDT 24
Finished Apr 21 02:34:23 PM PDT 24
Peak memory 182664 kb
Host smart-705ac89f-3379-4db8-ad7a-969f78ff0cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865263927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.865263927
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1480630696
Short name T214
Test name
Test status
Simulation time 22364123934 ps
CPU time 27.06 seconds
Started Apr 21 02:33:18 PM PDT 24
Finished Apr 21 02:33:46 PM PDT 24
Peak memory 182684 kb
Host smart-bdfd2465-b7d5-4cf3-8b7f-3ceb2255ae05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480630696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1480630696
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2016076871
Short name T190
Test name
Test status
Simulation time 156492860618 ps
CPU time 86.88 seconds
Started Apr 21 02:28:44 PM PDT 24
Finished Apr 21 02:30:11 PM PDT 24
Peak memory 182656 kb
Host smart-d53bae32-cd47-4d35-8e77-fa5fd570ddef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016076871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2016076871
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1686242862
Short name T432
Test name
Test status
Simulation time 97904108860 ps
CPU time 70.37 seconds
Started Apr 21 02:28:42 PM PDT 24
Finished Apr 21 02:29:53 PM PDT 24
Peak memory 182636 kb
Host smart-6331bc1c-0f96-44d7-a903-977a4bc7b41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686242862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1686242862
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1544676782
Short name T425
Test name
Test status
Simulation time 191655114773 ps
CPU time 82.4 seconds
Started Apr 21 02:28:42 PM PDT 24
Finished Apr 21 02:30:05 PM PDT 24
Peak memory 182476 kb
Host smart-1230d589-29c1-4124-b5c1-fb06dbd2454a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544676782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1544676782
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2577370066
Short name T378
Test name
Test status
Simulation time 438045729 ps
CPU time 1.42 seconds
Started Apr 21 02:28:42 PM PDT 24
Finished Apr 21 02:28:44 PM PDT 24
Peak memory 182616 kb
Host smart-c7aad579-5e3f-4ff9-987f-b5feaf30b75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577370066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2577370066
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2758618243
Short name T123
Test name
Test status
Simulation time 9753759229817 ps
CPU time 1310.07 seconds
Started Apr 21 02:28:44 PM PDT 24
Finished Apr 21 02:50:34 PM PDT 24
Peak memory 190864 kb
Host smart-447eee4a-a373-4903-b7f1-4bbad543bd10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758618243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2758618243
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.323874884
Short name T209
Test name
Test status
Simulation time 59263750456 ps
CPU time 278.29 seconds
Started Apr 21 02:33:19 PM PDT 24
Finished Apr 21 02:37:58 PM PDT 24
Peak memory 182660 kb
Host smart-8f3933d8-74d0-448c-8f14-3faaec612547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323874884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.323874884
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1605067748
Short name T119
Test name
Test status
Simulation time 129205523105 ps
CPU time 1814.53 seconds
Started Apr 21 02:33:19 PM PDT 24
Finished Apr 21 03:03:34 PM PDT 24
Peak memory 190864 kb
Host smart-1beb4553-a635-43b1-bdf6-6ae9b62925be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605067748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1605067748
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2316828654
Short name T418
Test name
Test status
Simulation time 87268075890 ps
CPU time 3304.48 seconds
Started Apr 21 02:33:21 PM PDT 24
Finished Apr 21 03:28:26 PM PDT 24
Peak memory 190880 kb
Host smart-16ebf9c1-7221-4acf-84d6-1fbe559348bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316828654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2316828654
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1093439991
Short name T108
Test name
Test status
Simulation time 421402562207 ps
CPU time 175.18 seconds
Started Apr 21 02:33:24 PM PDT 24
Finished Apr 21 02:36:19 PM PDT 24
Peak memory 190812 kb
Host smart-c66005e3-e4e3-430a-8cc9-c0869562bb75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093439991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1093439991
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.968277236
Short name T431
Test name
Test status
Simulation time 13244133447 ps
CPU time 31.36 seconds
Started Apr 21 02:33:22 PM PDT 24
Finished Apr 21 02:33:54 PM PDT 24
Peak memory 182688 kb
Host smart-0812960b-89a9-4223-888a-98ecee27225d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968277236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.968277236
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.735473201
Short name T114
Test name
Test status
Simulation time 165641491591 ps
CPU time 656.42 seconds
Started Apr 21 02:33:26 PM PDT 24
Finished Apr 21 02:44:23 PM PDT 24
Peak memory 190808 kb
Host smart-345f5771-771a-44b2-a352-b0ef4c73fe2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735473201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.735473201
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2480588670
Short name T253
Test name
Test status
Simulation time 194589837944 ps
CPU time 173.09 seconds
Started Apr 21 02:33:28 PM PDT 24
Finished Apr 21 02:36:22 PM PDT 24
Peak memory 190876 kb
Host smart-dcdac174-24b6-4e25-a269-b0c0b7a6c9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480588670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2480588670
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3130162127
Short name T155
Test name
Test status
Simulation time 148117065032 ps
CPU time 401.55 seconds
Started Apr 21 02:33:30 PM PDT 24
Finished Apr 21 02:40:12 PM PDT 24
Peak memory 190872 kb
Host smart-e2201965-3164-4fc4-9eec-e675efd61c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130162127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3130162127
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1593938543
Short name T346
Test name
Test status
Simulation time 861899545154 ps
CPU time 459.54 seconds
Started Apr 21 02:28:43 PM PDT 24
Finished Apr 21 02:36:23 PM PDT 24
Peak memory 182676 kb
Host smart-c4757f0a-ad5e-43d8-bf8d-46caf466ab7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593938543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1593938543
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.492621828
Short name T386
Test name
Test status
Simulation time 50342168809 ps
CPU time 70.05 seconds
Started Apr 21 02:28:43 PM PDT 24
Finished Apr 21 02:29:53 PM PDT 24
Peak memory 182672 kb
Host smart-4ceebf61-4b09-4186-9cf4-c5e7ab017b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492621828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.492621828
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2014588642
Short name T337
Test name
Test status
Simulation time 28929367453 ps
CPU time 44.62 seconds
Started Apr 21 02:28:42 PM PDT 24
Finished Apr 21 02:29:27 PM PDT 24
Peak memory 182660 kb
Host smart-7b0fc274-a203-4895-a64d-fd591f1864f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014588642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2014588642
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.513630630
Short name T7
Test name
Test status
Simulation time 87932331488 ps
CPU time 373.58 seconds
Started Apr 21 02:33:32 PM PDT 24
Finished Apr 21 02:39:46 PM PDT 24
Peak memory 190848 kb
Host smart-b33b0d70-263f-4865-a949-55e501317380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513630630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.513630630
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.910359065
Short name T328
Test name
Test status
Simulation time 102558496935 ps
CPU time 175.55 seconds
Started Apr 21 02:33:31 PM PDT 24
Finished Apr 21 02:36:27 PM PDT 24
Peak memory 190808 kb
Host smart-71d7872e-2003-4755-a3cc-c2130caa75cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910359065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.910359065
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3107502830
Short name T183
Test name
Test status
Simulation time 229447472727 ps
CPU time 288.63 seconds
Started Apr 21 02:33:36 PM PDT 24
Finished Apr 21 02:38:25 PM PDT 24
Peak memory 190840 kb
Host smart-13ff05a5-9e00-488a-ac52-caa9bb8c7a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107502830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3107502830
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2371410462
Short name T152
Test name
Test status
Simulation time 750233615518 ps
CPU time 650.59 seconds
Started Apr 21 02:33:36 PM PDT 24
Finished Apr 21 02:44:27 PM PDT 24
Peak memory 190840 kb
Host smart-cca6350c-27f2-4ff2-a10a-a65810fb9b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371410462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2371410462
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3231889676
Short name T250
Test name
Test status
Simulation time 151230931406 ps
CPU time 495.77 seconds
Started Apr 21 02:33:37 PM PDT 24
Finished Apr 21 02:41:53 PM PDT 24
Peak memory 190872 kb
Host smart-0988f8ba-5fa2-48e7-8b02-cd205d96d00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231889676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3231889676
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.562039473
Short name T336
Test name
Test status
Simulation time 192226618483 ps
CPU time 159 seconds
Started Apr 21 02:33:39 PM PDT 24
Finished Apr 21 02:36:19 PM PDT 24
Peak memory 190864 kb
Host smart-7fcf22bb-bfab-467b-b2b9-1cca38498f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562039473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.562039473
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3101311026
Short name T215
Test name
Test status
Simulation time 200986216258 ps
CPU time 326.69 seconds
Started Apr 21 02:33:43 PM PDT 24
Finished Apr 21 02:39:10 PM PDT 24
Peak memory 190828 kb
Host smart-c974f486-de9e-4f29-89e6-ca33724e1391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101311026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3101311026
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3421932901
Short name T112
Test name
Test status
Simulation time 421977698114 ps
CPU time 571.82 seconds
Started Apr 21 02:33:45 PM PDT 24
Finished Apr 21 02:43:17 PM PDT 24
Peak memory 191028 kb
Host smart-654c4a09-4d3b-4fae-a92d-5ee9ce498d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421932901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3421932901
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2892495512
Short name T181
Test name
Test status
Simulation time 250505658852 ps
CPU time 224.29 seconds
Started Apr 21 02:28:47 PM PDT 24
Finished Apr 21 02:32:31 PM PDT 24
Peak memory 182652 kb
Host smart-4daa4628-439f-431c-aceb-ad9677174202
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892495512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2892495512
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3680567362
Short name T381
Test name
Test status
Simulation time 661450937553 ps
CPU time 205.5 seconds
Started Apr 21 02:28:47 PM PDT 24
Finished Apr 21 02:32:13 PM PDT 24
Peak memory 182668 kb
Host smart-93d3e940-e95b-410a-b004-9cafc543ae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680567362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3680567362
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.4282788622
Short name T65
Test name
Test status
Simulation time 276282879100 ps
CPU time 353.66 seconds
Started Apr 21 02:28:45 PM PDT 24
Finished Apr 21 02:34:39 PM PDT 24
Peak memory 190880 kb
Host smart-6402d98d-ec58-4856-8086-90dc0054d126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282788622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.4282788622
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.17138090
Short name T49
Test name
Test status
Simulation time 172237901501 ps
CPU time 151.2 seconds
Started Apr 21 02:28:46 PM PDT 24
Finished Apr 21 02:31:17 PM PDT 24
Peak memory 190864 kb
Host smart-55637e20-906b-46ed-94c4-e12b84234c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17138090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.17138090
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2199587261
Short name T297
Test name
Test status
Simulation time 186170819179 ps
CPU time 296.25 seconds
Started Apr 21 02:28:47 PM PDT 24
Finished Apr 21 02:33:44 PM PDT 24
Peak memory 190896 kb
Host smart-c1228703-ebb0-4b75-b105-ad83bc5c4a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199587261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2199587261
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1663043071
Short name T37
Test name
Test status
Simulation time 291997864268 ps
CPU time 803.27 seconds
Started Apr 21 02:28:45 PM PDT 24
Finished Apr 21 02:42:08 PM PDT 24
Peak memory 206920 kb
Host smart-26a689c2-07d2-4e4c-aca2-640e62901e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663043071 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1663043071
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.396871873
Short name T357
Test name
Test status
Simulation time 380197692089 ps
CPU time 792.86 seconds
Started Apr 21 02:33:43 PM PDT 24
Finished Apr 21 02:46:57 PM PDT 24
Peak memory 192560 kb
Host smart-11f4eb5d-b50f-4326-af8b-e9469d0ec3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396871873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.396871873
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1338090017
Short name T228
Test name
Test status
Simulation time 578411353341 ps
CPU time 559.27 seconds
Started Apr 21 02:33:46 PM PDT 24
Finished Apr 21 02:43:06 PM PDT 24
Peak memory 190836 kb
Host smart-4cd15cac-e29e-4fa8-9236-8aea2e935738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338090017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1338090017
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.542642333
Short name T208
Test name
Test status
Simulation time 20127810330 ps
CPU time 40.95 seconds
Started Apr 21 02:33:46 PM PDT 24
Finished Apr 21 02:34:27 PM PDT 24
Peak memory 190792 kb
Host smart-3e031252-fe37-43e0-b75d-6f7a5c8cd079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542642333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.542642333
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1220985800
Short name T206
Test name
Test status
Simulation time 53094057093 ps
CPU time 180.61 seconds
Started Apr 21 02:33:47 PM PDT 24
Finished Apr 21 02:36:48 PM PDT 24
Peak memory 190892 kb
Host smart-e866357d-ddba-4dc1-b59a-3b5bc1e2a0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220985800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1220985800
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3128165991
Short name T192
Test name
Test status
Simulation time 236854819371 ps
CPU time 415.17 seconds
Started Apr 21 02:33:48 PM PDT 24
Finished Apr 21 02:40:44 PM PDT 24
Peak memory 190760 kb
Host smart-cc494ab8-f015-4694-b1fb-3ddd1f904075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128165991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3128165991
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2100151063
Short name T136
Test name
Test status
Simulation time 892025087453 ps
CPU time 802.28 seconds
Started Apr 21 02:33:49 PM PDT 24
Finished Apr 21 02:47:11 PM PDT 24
Peak memory 190880 kb
Host smart-dc1d4a2d-f453-4eb4-b46b-0aa0bc1f9ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100151063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2100151063
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2023264355
Short name T151
Test name
Test status
Simulation time 756373003274 ps
CPU time 315.59 seconds
Started Apr 21 02:33:50 PM PDT 24
Finished Apr 21 02:39:06 PM PDT 24
Peak memory 190856 kb
Host smart-007a26cc-b4df-488f-a979-693b9bf6b3d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023264355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2023264355
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3793290020
Short name T80
Test name
Test status
Simulation time 117266299195 ps
CPU time 557.34 seconds
Started Apr 21 02:33:53 PM PDT 24
Finished Apr 21 02:43:11 PM PDT 24
Peak memory 190876 kb
Host smart-7a98e32b-837e-4f2c-b297-b1f8e07694d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793290020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3793290020
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1799464942
Short name T416
Test name
Test status
Simulation time 80404808440 ps
CPU time 126.05 seconds
Started Apr 21 02:33:53 PM PDT 24
Finished Apr 21 02:35:59 PM PDT 24
Peak memory 190888 kb
Host smart-65fddad6-493b-4514-8f43-78048f7c083a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799464942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1799464942
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.777405132
Short name T274
Test name
Test status
Simulation time 144976310489 ps
CPU time 133.37 seconds
Started Apr 21 02:33:57 PM PDT 24
Finished Apr 21 02:36:11 PM PDT 24
Peak memory 190896 kb
Host smart-e7ee4f4a-a21d-45b8-970e-01529ccb6127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777405132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.777405132
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2627809955
Short name T411
Test name
Test status
Simulation time 719184508703 ps
CPU time 239.14 seconds
Started Apr 21 02:28:48 PM PDT 24
Finished Apr 21 02:32:47 PM PDT 24
Peak memory 182648 kb
Host smart-320660c8-dfa9-408d-b4cc-5f47726357ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627809955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2627809955
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2921060603
Short name T63
Test name
Test status
Simulation time 387420779377 ps
CPU time 198.79 seconds
Started Apr 21 02:28:45 PM PDT 24
Finished Apr 21 02:32:04 PM PDT 24
Peak memory 193052 kb
Host smart-f0dbce98-e15c-49f4-a503-c31f79d3adba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921060603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2921060603
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1522750558
Short name T391
Test name
Test status
Simulation time 203124524 ps
CPU time 0.87 seconds
Started Apr 21 02:28:52 PM PDT 24
Finished Apr 21 02:28:53 PM PDT 24
Peak memory 191088 kb
Host smart-ca70d5ca-08a9-45e8-bb3c-e03f89fa1374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522750558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1522750558
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.559117587
Short name T445
Test name
Test status
Simulation time 91069046533 ps
CPU time 12.31 seconds
Started Apr 21 02:28:55 PM PDT 24
Finished Apr 21 02:29:07 PM PDT 24
Peak memory 194300 kb
Host smart-5944250a-16e6-45eb-88ac-7506c27dbfc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559117587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.559117587
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.820205384
Short name T239
Test name
Test status
Simulation time 191189695388 ps
CPU time 164 seconds
Started Apr 21 02:33:52 PM PDT 24
Finished Apr 21 02:36:37 PM PDT 24
Peak memory 194320 kb
Host smart-b0ec6611-f973-4470-9109-434cf445157b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820205384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.820205384
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1522810893
Short name T106
Test name
Test status
Simulation time 110416815365 ps
CPU time 168.91 seconds
Started Apr 21 02:33:56 PM PDT 24
Finished Apr 21 02:36:45 PM PDT 24
Peak memory 190808 kb
Host smart-e56c3755-dbc1-47d0-bc30-b9a6ae62e53a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522810893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1522810893
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.915210129
Short name T442
Test name
Test status
Simulation time 50254164813 ps
CPU time 91.94 seconds
Started Apr 21 02:33:59 PM PDT 24
Finished Apr 21 02:35:31 PM PDT 24
Peak memory 182652 kb
Host smart-18b94f13-97da-426c-bf52-c5f402585f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915210129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.915210129
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.693531459
Short name T66
Test name
Test status
Simulation time 182092986498 ps
CPU time 309.37 seconds
Started Apr 21 02:34:07 PM PDT 24
Finished Apr 21 02:39:17 PM PDT 24
Peak memory 190924 kb
Host smart-34180e32-5f40-4955-92d0-3d6e5fd78963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693531459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.693531459
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.562644961
Short name T22
Test name
Test status
Simulation time 387379792654 ps
CPU time 568.41 seconds
Started Apr 21 02:34:05 PM PDT 24
Finished Apr 21 02:43:33 PM PDT 24
Peak memory 190800 kb
Host smart-1884bc68-2473-4014-8448-b4d1784a15bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562644961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.562644961
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3811082097
Short name T393
Test name
Test status
Simulation time 35159909978 ps
CPU time 49.26 seconds
Started Apr 21 02:34:10 PM PDT 24
Finished Apr 21 02:35:00 PM PDT 24
Peak memory 182544 kb
Host smart-622e34ed-cd7a-4cd8-b12f-cde6b3fbf058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811082097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3811082097
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2907679058
Short name T285
Test name
Test status
Simulation time 76140708502 ps
CPU time 1562.4 seconds
Started Apr 21 02:34:09 PM PDT 24
Finished Apr 21 03:00:12 PM PDT 24
Peak memory 190844 kb
Host smart-9d52bce7-bf4c-4fed-82ce-e6bb6a3781d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907679058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2907679058
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.4085231343
Short name T227
Test name
Test status
Simulation time 288074306214 ps
CPU time 124.1 seconds
Started Apr 21 02:34:06 PM PDT 24
Finished Apr 21 02:36:11 PM PDT 24
Peak memory 190872 kb
Host smart-1e8c86ac-0fb5-4326-bee9-584426f4bb68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085231343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4085231343
Directory /workspace/98.rv_timer_random/latest
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