Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 583
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.261750188 Apr 23 01:09:48 PM PDT 24 Apr 23 01:09:49 PM PDT 24 81541280 ps
T508 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3434253650 Apr 23 01:10:17 PM PDT 24 Apr 23 01:10:19 PM PDT 24 16628929 ps
T509 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2861553231 Apr 23 01:09:47 PM PDT 24 Apr 23 01:09:49 PM PDT 24 108660360 ps
T510 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3925356291 Apr 23 01:10:13 PM PDT 24 Apr 23 01:10:15 PM PDT 24 54054691 ps
T110 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3643299576 Apr 23 01:09:49 PM PDT 24 Apr 23 01:09:50 PM PDT 24 132130792 ps
T511 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.394634426 Apr 23 01:09:38 PM PDT 24 Apr 23 01:09:41 PM PDT 24 93289033 ps
T512 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4063656151 Apr 23 01:10:13 PM PDT 24 Apr 23 01:10:15 PM PDT 24 14004016 ps
T513 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1435152562 Apr 23 01:09:59 PM PDT 24 Apr 23 01:10:01 PM PDT 24 107783529 ps
T514 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.730274479 Apr 23 01:09:44 PM PDT 24 Apr 23 01:09:46 PM PDT 24 70359521 ps
T515 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1935569199 Apr 23 01:10:02 PM PDT 24 Apr 23 01:10:03 PM PDT 24 19665293 ps
T91 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3730381314 Apr 23 01:09:38 PM PDT 24 Apr 23 01:09:40 PM PDT 24 52708776 ps
T516 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2224039157 Apr 23 01:09:48 PM PDT 24 Apr 23 01:09:51 PM PDT 24 127032947 ps
T517 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2249770614 Apr 23 01:10:23 PM PDT 24 Apr 23 01:10:25 PM PDT 24 70136850 ps
T518 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3758264511 Apr 23 01:10:02 PM PDT 24 Apr 23 01:10:03 PM PDT 24 14041039 ps
T519 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1002030970 Apr 23 01:09:57 PM PDT 24 Apr 23 01:09:58 PM PDT 24 92181445 ps
T520 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1813849876 Apr 23 01:09:59 PM PDT 24 Apr 23 01:10:01 PM PDT 24 852945571 ps
T125 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4101554175 Apr 23 01:10:13 PM PDT 24 Apr 23 01:10:15 PM PDT 24 443677998 ps
T521 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.559592608 Apr 23 01:10:04 PM PDT 24 Apr 23 01:10:05 PM PDT 24 28726250 ps
T522 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4000060607 Apr 23 01:10:16 PM PDT 24 Apr 23 01:10:17 PM PDT 24 57146683 ps
T523 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1330561835 Apr 23 01:10:14 PM PDT 24 Apr 23 01:10:15 PM PDT 24 13641638 ps
T524 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.403639222 Apr 23 01:10:10 PM PDT 24 Apr 23 01:10:11 PM PDT 24 64578681 ps
T525 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.535126929 Apr 23 01:09:31 PM PDT 24 Apr 23 01:09:32 PM PDT 24 25533340 ps
T102 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2522207690 Apr 23 01:09:42 PM PDT 24 Apr 23 01:09:44 PM PDT 24 119269065 ps
T526 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.949412405 Apr 23 01:09:46 PM PDT 24 Apr 23 01:09:47 PM PDT 24 26606026 ps
T527 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2816524854 Apr 23 01:10:06 PM PDT 24 Apr 23 01:10:07 PM PDT 24 89059030 ps
T528 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1557713018 Apr 23 01:09:53 PM PDT 24 Apr 23 01:09:54 PM PDT 24 133324046 ps
T529 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3611500464 Apr 23 01:09:36 PM PDT 24 Apr 23 01:09:37 PM PDT 24 15258152 ps
T530 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3283249012 Apr 23 01:10:09 PM PDT 24 Apr 23 01:10:11 PM PDT 24 45962363 ps
T531 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2034503083 Apr 23 01:10:13 PM PDT 24 Apr 23 01:10:15 PM PDT 24 53488875 ps
T532 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3225387621 Apr 23 01:09:31 PM PDT 24 Apr 23 01:09:32 PM PDT 24 102823210 ps
T533 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2285302178 Apr 23 01:09:35 PM PDT 24 Apr 23 01:09:37 PM PDT 24 188865471 ps
T534 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.657385163 Apr 23 01:10:15 PM PDT 24 Apr 23 01:10:17 PM PDT 24 74989803 ps
T535 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.862327006 Apr 23 01:10:18 PM PDT 24 Apr 23 01:10:20 PM PDT 24 18975299 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.624072199 Apr 23 01:09:44 PM PDT 24 Apr 23 01:09:45 PM PDT 24 29148756 ps
T92 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4201549621 Apr 23 01:09:40 PM PDT 24 Apr 23 01:09:43 PM PDT 24 238159264 ps
T537 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3925384891 Apr 23 01:09:38 PM PDT 24 Apr 23 01:09:41 PM PDT 24 112096776 ps
T538 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2249549427 Apr 23 01:10:06 PM PDT 24 Apr 23 01:10:09 PM PDT 24 234428230 ps
T539 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2679697185 Apr 23 01:10:01 PM PDT 24 Apr 23 01:10:02 PM PDT 24 36350336 ps
T540 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.876492142 Apr 23 01:10:11 PM PDT 24 Apr 23 01:10:13 PM PDT 24 230007540 ps
T541 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2711969061 Apr 23 01:10:16 PM PDT 24 Apr 23 01:10:17 PM PDT 24 92785163 ps
T542 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2610390731 Apr 23 01:09:45 PM PDT 24 Apr 23 01:09:47 PM PDT 24 102039767 ps
T543 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1166827240 Apr 23 01:10:23 PM PDT 24 Apr 23 01:10:25 PM PDT 24 25707369 ps
T544 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1038488810 Apr 23 01:10:18 PM PDT 24 Apr 23 01:10:19 PM PDT 24 46001205 ps
T545 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2076493807 Apr 23 01:10:19 PM PDT 24 Apr 23 01:10:20 PM PDT 24 14571756 ps
T546 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3958080503 Apr 23 01:10:13 PM PDT 24 Apr 23 01:10:14 PM PDT 24 146707488 ps
T547 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3089205705 Apr 23 01:09:48 PM PDT 24 Apr 23 01:09:49 PM PDT 24 18090102 ps
T548 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3434366286 Apr 23 01:09:44 PM PDT 24 Apr 23 01:09:47 PM PDT 24 645331996 ps
T549 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1712602638 Apr 23 01:09:54 PM PDT 24 Apr 23 01:09:55 PM PDT 24 82921608 ps
T550 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2873395881 Apr 23 01:10:13 PM PDT 24 Apr 23 01:10:15 PM PDT 24 69921515 ps
T551 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1987539621 Apr 23 01:09:35 PM PDT 24 Apr 23 01:09:36 PM PDT 24 23958612 ps
T552 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1745774649 Apr 23 01:10:03 PM PDT 24 Apr 23 01:10:04 PM PDT 24 44523551 ps
T553 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2714445450 Apr 23 01:09:50 PM PDT 24 Apr 23 01:09:51 PM PDT 24 27973480 ps
T554 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.42457120 Apr 23 01:09:36 PM PDT 24 Apr 23 01:09:38 PM PDT 24 103429245 ps
T555 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1611691411 Apr 23 01:09:39 PM PDT 24 Apr 23 01:09:40 PM PDT 24 11614272 ps
T556 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.64385659 Apr 23 01:09:47 PM PDT 24 Apr 23 01:09:49 PM PDT 24 130450294 ps
T557 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.688538060 Apr 23 01:09:47 PM PDT 24 Apr 23 01:09:49 PM PDT 24 123407170 ps
T558 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.826477494 Apr 23 01:10:16 PM PDT 24 Apr 23 01:10:17 PM PDT 24 102684355 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1068511032 Apr 23 01:09:44 PM PDT 24 Apr 23 01:09:45 PM PDT 24 69448099 ps
T560 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.590740817 Apr 23 01:09:50 PM PDT 24 Apr 23 01:09:52 PM PDT 24 138217243 ps
T561 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3634516551 Apr 23 01:10:00 PM PDT 24 Apr 23 01:10:02 PM PDT 24 40850753 ps
T562 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3239050018 Apr 23 01:10:24 PM PDT 24 Apr 23 01:10:25 PM PDT 24 16867180 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3465308944 Apr 23 01:10:03 PM PDT 24 Apr 23 01:10:04 PM PDT 24 167628227 ps
T564 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1550909867 Apr 23 01:10:16 PM PDT 24 Apr 23 01:10:17 PM PDT 24 31454364 ps
T565 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1494700612 Apr 23 01:10:03 PM PDT 24 Apr 23 01:10:05 PM PDT 24 219244536 ps
T566 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1452473964 Apr 23 01:10:17 PM PDT 24 Apr 23 01:10:18 PM PDT 24 18535377 ps
T126 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3582450046 Apr 23 01:09:54 PM PDT 24 Apr 23 01:09:56 PM PDT 24 190265985 ps
T567 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3940587915 Apr 23 01:09:48 PM PDT 24 Apr 23 01:09:49 PM PDT 24 25789634 ps
T568 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1198173024 Apr 23 01:10:15 PM PDT 24 Apr 23 01:10:17 PM PDT 24 43507797 ps
T569 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1618978528 Apr 23 01:09:58 PM PDT 24 Apr 23 01:10:00 PM PDT 24 184086003 ps
T570 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3868349170 Apr 23 01:10:12 PM PDT 24 Apr 23 01:10:14 PM PDT 24 23570001 ps
T571 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2806300720 Apr 23 01:09:44 PM PDT 24 Apr 23 01:09:45 PM PDT 24 20017410 ps
T572 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.405073141 Apr 23 01:10:11 PM PDT 24 Apr 23 01:10:12 PM PDT 24 14349546 ps
T573 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2457106229 Apr 23 01:09:45 PM PDT 24 Apr 23 01:09:47 PM PDT 24 16295687 ps
T574 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3378314754 Apr 23 01:10:14 PM PDT 24 Apr 23 01:10:15 PM PDT 24 26880931 ps
T575 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1351913677 Apr 23 01:10:16 PM PDT 24 Apr 23 01:10:17 PM PDT 24 30265339 ps
T576 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3348783000 Apr 23 01:09:34 PM PDT 24 Apr 23 01:09:35 PM PDT 24 14547969 ps
T577 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3973093832 Apr 23 01:09:52 PM PDT 24 Apr 23 01:09:53 PM PDT 24 52099239 ps
T578 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1042925895 Apr 23 01:09:49 PM PDT 24 Apr 23 01:09:50 PM PDT 24 41552180 ps
T579 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2958153612 Apr 23 01:10:12 PM PDT 24 Apr 23 01:10:14 PM PDT 24 48347901 ps
T580 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4270881625 Apr 23 01:10:13 PM PDT 24 Apr 23 01:10:15 PM PDT 24 213015386 ps
T581 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2754792458 Apr 23 01:09:54 PM PDT 24 Apr 23 01:09:55 PM PDT 24 25496407 ps
T582 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4046446432 Apr 23 01:09:38 PM PDT 24 Apr 23 01:09:40 PM PDT 24 38581103 ps
T583 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.622391767 Apr 23 01:09:35 PM PDT 24 Apr 23 01:09:40 PM PDT 24 1719803725 ps

Test location /workspace/coverage/default/12.rv_timer_stress_all.2939685574
Short name T8
Test name
Test status
Simulation time 390881715015 ps
CPU time 1860.59 seconds
Started Apr 23 01:14:20 PM PDT 24
Finished Apr 23 01:45:22 PM PDT 24
Peak memory 190812 kb
Host smart-b9299011-3290-41e8-88b5-38ed8e18d4e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939685574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2939685574
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1230124096
Short name T14
Test name
Test status
Simulation time 101480380432 ps
CPU time 916.28 seconds
Started Apr 23 01:16:05 PM PDT 24
Finished Apr 23 01:31:22 PM PDT 24
Peak memory 210576 kb
Host smart-31b58ef2-9e63-4c0f-a73d-b0b55a6248f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230124096 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1230124096
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2477633054
Short name T205
Test name
Test status
Simulation time 522600902204 ps
CPU time 2779.46 seconds
Started Apr 23 01:14:33 PM PDT 24
Finished Apr 23 02:00:53 PM PDT 24
Peak memory 194444 kb
Host smart-71e94130-cc63-4597-beb2-860e1040f1ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477633054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2477633054
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2729947281
Short name T30
Test name
Test status
Simulation time 38437151 ps
CPU time 0.84 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:39 PM PDT 24
Peak memory 182972 kb
Host smart-bdd777a9-d59e-466b-90a8-ed796479dbfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729947281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2729947281
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/177.rv_timer_random.2218905434
Short name T9
Test name
Test status
Simulation time 1804556229138 ps
CPU time 608.39 seconds
Started Apr 23 01:18:20 PM PDT 24
Finished Apr 23 01:28:29 PM PDT 24
Peak memory 190656 kb
Host smart-f51459cd-e126-48b6-82e2-f38bb1099f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218905434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2218905434
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3366308267
Short name T59
Test name
Test status
Simulation time 3001712860113 ps
CPU time 2057.29 seconds
Started Apr 23 01:14:12 PM PDT 24
Finished Apr 23 01:48:30 PM PDT 24
Peak memory 190688 kb
Host smart-313009ba-9211-44c3-a2cf-ea78e8c5feff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366308267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3366308267
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2629171420
Short name T131
Test name
Test status
Simulation time 9563660340422 ps
CPU time 3381.23 seconds
Started Apr 23 01:14:35 PM PDT 24
Finished Apr 23 02:10:57 PM PDT 24
Peak memory 190728 kb
Host smart-024b0e23-6340-4cdd-af4c-bc65b78c6954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629171420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2629171420
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4034093324
Short name T35
Test name
Test status
Simulation time 16463119 ps
CPU time 0.58 seconds
Started Apr 23 01:10:09 PM PDT 24
Finished Apr 23 01:10:10 PM PDT 24
Peak memory 182524 kb
Host smart-09385cd5-a50b-4fdb-bd2c-51a7c1c9484b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034093324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4034093324
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.142945883
Short name T246
Test name
Test status
Simulation time 507318961964 ps
CPU time 1016.12 seconds
Started Apr 23 01:14:19 PM PDT 24
Finished Apr 23 01:31:16 PM PDT 24
Peak memory 190704 kb
Host smart-9a52aeca-c108-4f46-ab6e-f82c5b6b5ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142945883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
142945883
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3975286802
Short name T117
Test name
Test status
Simulation time 489280522438 ps
CPU time 2295.93 seconds
Started Apr 23 01:15:14 PM PDT 24
Finished Apr 23 01:53:31 PM PDT 24
Peak memory 190768 kb
Host smart-957c64bf-46d2-4958-b911-3e207ce4278a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975286802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3975286802
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1188965460
Short name T190
Test name
Test status
Simulation time 1604394205608 ps
CPU time 2035.16 seconds
Started Apr 23 01:14:49 PM PDT 24
Finished Apr 23 01:48:45 PM PDT 24
Peak memory 194828 kb
Host smart-56099099-ea0f-4a08-a732-3bdaaf656143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188965460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1188965460
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.388213833
Short name T261
Test name
Test status
Simulation time 1157100476185 ps
CPU time 1177.54 seconds
Started Apr 23 01:15:47 PM PDT 24
Finished Apr 23 01:35:25 PM PDT 24
Peak memory 190732 kb
Host smart-eeba1cd9-383b-4320-a8e9-1c963a28a7ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388213833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
388213833
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.693264154
Short name T164
Test name
Test status
Simulation time 859994611141 ps
CPU time 704.6 seconds
Started Apr 23 01:14:29 PM PDT 24
Finished Apr 23 01:26:15 PM PDT 24
Peak memory 190740 kb
Host smart-62f98e33-5d0a-4eee-bd09-7ea4458b9758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693264154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
693264154
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2851658215
Short name T16
Test name
Test status
Simulation time 247596874 ps
CPU time 0.76 seconds
Started Apr 23 01:13:59 PM PDT 24
Finished Apr 23 01:14:00 PM PDT 24
Peak memory 213136 kb
Host smart-de72b17b-9ee1-43cf-93ef-c169d3f9eaf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851658215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2851658215
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3843666576
Short name T178
Test name
Test status
Simulation time 566000925087 ps
CPU time 773.97 seconds
Started Apr 23 01:13:55 PM PDT 24
Finished Apr 23 01:26:50 PM PDT 24
Peak memory 190668 kb
Host smart-c26930ff-ba8a-44a5-8802-f2c7797cb8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843666576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3843666576
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3323929083
Short name T67
Test name
Test status
Simulation time 4191263557529 ps
CPU time 1954.25 seconds
Started Apr 23 01:15:52 PM PDT 24
Finished Apr 23 01:48:26 PM PDT 24
Peak memory 190708 kb
Host smart-e9493ec7-4ce0-42fe-b5a7-73b1c7bb9d4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323929083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3323929083
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.930232169
Short name T155
Test name
Test status
Simulation time 147224376225 ps
CPU time 545.5 seconds
Started Apr 23 01:17:26 PM PDT 24
Finished Apr 23 01:26:32 PM PDT 24
Peak memory 190812 kb
Host smart-0424e990-fa30-4971-8073-b0d7b476fe5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930232169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.930232169
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3985145866
Short name T305
Test name
Test status
Simulation time 1038623073424 ps
CPU time 2184.31 seconds
Started Apr 23 01:15:28 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 190728 kb
Host smart-0df2b710-ed56-4561-983a-e4392395101c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985145866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3985145866
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3133446691
Short name T276
Test name
Test status
Simulation time 1596691804506 ps
CPU time 1911.03 seconds
Started Apr 23 01:14:04 PM PDT 24
Finished Apr 23 01:45:56 PM PDT 24
Peak memory 195708 kb
Host smart-34040ecb-9d64-4722-b84e-7f8b9fd915e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133446691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3133446691
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3291546022
Short name T72
Test name
Test status
Simulation time 246171441751 ps
CPU time 490.12 seconds
Started Apr 23 01:14:39 PM PDT 24
Finished Apr 23 01:22:49 PM PDT 24
Peak memory 190732 kb
Host smart-bb4602d9-0167-474e-89c7-23874729f257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291546022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3291546022
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.3243928787
Short name T137
Test name
Test status
Simulation time 845413217015 ps
CPU time 978.48 seconds
Started Apr 23 01:14:01 PM PDT 24
Finished Apr 23 01:30:20 PM PDT 24
Peak memory 190768 kb
Host smart-0ea84f09-e767-4c60-b534-0d76601ba383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243928787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3243928787
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random.521295789
Short name T195
Test name
Test status
Simulation time 953449127208 ps
CPU time 643.7 seconds
Started Apr 23 01:15:17 PM PDT 24
Finished Apr 23 01:26:01 PM PDT 24
Peak memory 190672 kb
Host smart-7da343a7-9739-4a97-b181-c810148ba2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521295789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.521295789
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3669703875
Short name T65
Test name
Test status
Simulation time 890408625523 ps
CPU time 1321.86 seconds
Started Apr 23 01:14:06 PM PDT 24
Finished Apr 23 01:36:09 PM PDT 24
Peak memory 190792 kb
Host smart-4259126b-1238-4ccc-b35b-dedb3515ecc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669703875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3669703875
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.992710075
Short name T26
Test name
Test status
Simulation time 512691591864 ps
CPU time 748.17 seconds
Started Apr 23 01:14:17 PM PDT 24
Finished Apr 23 01:26:46 PM PDT 24
Peak memory 190792 kb
Host smart-0ba18588-bf54-4d60-8176-7d62f12ba9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992710075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
992710075
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.865448747
Short name T209
Test name
Test status
Simulation time 1197292560587 ps
CPU time 1175.52 seconds
Started Apr 23 01:14:23 PM PDT 24
Finished Apr 23 01:33:59 PM PDT 24
Peak memory 182484 kb
Host smart-09f919e9-d876-4170-8816-d886793104e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865448747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.865448747
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.4006898552
Short name T100
Test name
Test status
Simulation time 267803704754 ps
CPU time 808.96 seconds
Started Apr 23 01:15:00 PM PDT 24
Finished Apr 23 01:28:29 PM PDT 24
Peak memory 194580 kb
Host smart-cf92fa5b-fd33-40b3-9fda-4ea1087ea0ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006898552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.4006898552
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2659477515
Short name T235
Test name
Test status
Simulation time 428017799257 ps
CPU time 790.44 seconds
Started Apr 23 01:14:21 PM PDT 24
Finished Apr 23 01:27:32 PM PDT 24
Peak memory 182508 kb
Host smart-e341dade-df3a-42f8-897b-c4053f7b1824
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659477515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2659477515
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/90.rv_timer_random.3971290087
Short name T150
Test name
Test status
Simulation time 263538485316 ps
CPU time 301.9 seconds
Started Apr 23 01:17:07 PM PDT 24
Finished Apr 23 01:22:09 PM PDT 24
Peak memory 194664 kb
Host smart-981765c4-3d2f-4752-b20f-df9a85121880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971290087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3971290087
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2513983684
Short name T134
Test name
Test status
Simulation time 143364420395 ps
CPU time 212.1 seconds
Started Apr 23 01:17:26 PM PDT 24
Finished Apr 23 01:20:58 PM PDT 24
Peak memory 190732 kb
Host smart-bd9ae2bc-c5d3-401b-af57-6495549254d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513983684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2513983684
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.1560383168
Short name T216
Test name
Test status
Simulation time 107977342644 ps
CPU time 659.04 seconds
Started Apr 23 01:18:24 PM PDT 24
Finished Apr 23 01:29:23 PM PDT 24
Peak memory 190780 kb
Host smart-5b7b7897-16a3-4249-895a-90d86f0e24b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560383168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1560383168
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2650711378
Short name T63
Test name
Test status
Simulation time 5392459546297 ps
CPU time 1198.08 seconds
Started Apr 23 01:15:39 PM PDT 24
Finished Apr 23 01:35:37 PM PDT 24
Peak memory 190756 kb
Host smart-acccd297-ddbc-4278-bc6f-16cb16e34d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650711378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2650711378
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/59.rv_timer_random.2856338936
Short name T193
Test name
Test status
Simulation time 2263984819484 ps
CPU time 583.46 seconds
Started Apr 23 01:16:56 PM PDT 24
Finished Apr 23 01:26:40 PM PDT 24
Peak memory 190800 kb
Host smart-c6f990e0-a985-4b42-9a44-8491ca12a079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856338936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2856338936
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3983025838
Short name T172
Test name
Test status
Simulation time 522490283510 ps
CPU time 437.54 seconds
Started Apr 23 01:13:54 PM PDT 24
Finished Apr 23 01:21:12 PM PDT 24
Peak memory 190684 kb
Host smart-40ee653a-4cb0-46c3-b33f-9ef133e4b5de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983025838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3983025838
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.354661438
Short name T226
Test name
Test status
Simulation time 127865115945 ps
CPU time 839.41 seconds
Started Apr 23 01:14:03 PM PDT 24
Finished Apr 23 01:28:03 PM PDT 24
Peak memory 195100 kb
Host smart-2a89b626-ce78-4a89-8680-3b6bd850dcb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354661438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.354661438
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_random.1868028966
Short name T334
Test name
Test status
Simulation time 58592333135 ps
CPU time 273.13 seconds
Started Apr 23 01:14:23 PM PDT 24
Finished Apr 23 01:18:56 PM PDT 24
Peak memory 190716 kb
Host smart-0a5e5ae9-89a8-496f-91e6-42252b9914eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868028966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1868028966
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3633134841
Short name T201
Test name
Test status
Simulation time 491655565194 ps
CPU time 409.85 seconds
Started Apr 23 01:17:59 PM PDT 24
Finished Apr 23 01:24:49 PM PDT 24
Peak memory 190804 kb
Host smart-d7c6e36d-4ec4-480c-b5a5-9267b7436a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633134841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3633134841
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2729661435
Short name T211
Test name
Test status
Simulation time 246861665742 ps
CPU time 237.57 seconds
Started Apr 23 01:18:08 PM PDT 24
Finished Apr 23 01:22:07 PM PDT 24
Peak memory 190668 kb
Host smart-f880c64e-c132-4bee-a524-f025d2532bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729661435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2729661435
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1664765186
Short name T127
Test name
Test status
Simulation time 126907948688 ps
CPU time 335.78 seconds
Started Apr 23 01:18:42 PM PDT 24
Finished Apr 23 01:24:18 PM PDT 24
Peak memory 190732 kb
Host smart-a78e793e-488b-4c3f-8313-8b8ca2f96731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664765186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1664765186
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.4197077550
Short name T79
Test name
Test status
Simulation time 886395120824 ps
CPU time 898.8 seconds
Started Apr 23 01:14:19 PM PDT 24
Finished Apr 23 01:29:18 PM PDT 24
Peak memory 182596 kb
Host smart-e28e24e6-eff0-4194-9dde-62e6c4e11a2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197077550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.4197077550
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/161.rv_timer_random.1624009262
Short name T277
Test name
Test status
Simulation time 203978737086 ps
CPU time 505.23 seconds
Started Apr 23 01:18:09 PM PDT 24
Finished Apr 23 01:26:34 PM PDT 24
Peak memory 190712 kb
Host smart-a0ad1dd8-47e8-46f8-b4b8-002e1d2cfe05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624009262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1624009262
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3867641406
Short name T141
Test name
Test status
Simulation time 238210484989 ps
CPU time 232.08 seconds
Started Apr 23 01:18:14 PM PDT 24
Finished Apr 23 01:22:07 PM PDT 24
Peak memory 190800 kb
Host smart-275c3774-cff9-40b8-a685-ec61b69e7c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867641406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3867641406
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1888687079
Short name T268
Test name
Test status
Simulation time 312106767279 ps
CPU time 457.86 seconds
Started Apr 23 01:18:31 PM PDT 24
Finished Apr 23 01:26:09 PM PDT 24
Peak memory 190680 kb
Host smart-a2cc7a97-4c92-4e92-ab47-37356b0f4ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888687079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1888687079
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.1263241071
Short name T48
Test name
Test status
Simulation time 235924621132 ps
CPU time 219.18 seconds
Started Apr 23 01:14:39 PM PDT 24
Finished Apr 23 01:18:19 PM PDT 24
Peak memory 190716 kb
Host smart-65f34899-47a8-4693-840a-3707eca92c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263241071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1263241071
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.2879869622
Short name T314
Test name
Test status
Simulation time 708482768004 ps
CPU time 188.09 seconds
Started Apr 23 01:14:42 PM PDT 24
Finished Apr 23 01:17:50 PM PDT 24
Peak memory 190812 kb
Host smart-6d8f872d-3575-422c-8905-b50389397eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879869622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2879869622
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.574202174
Short name T177
Test name
Test status
Simulation time 338772797631 ps
CPU time 363.31 seconds
Started Apr 23 01:14:58 PM PDT 24
Finished Apr 23 01:21:02 PM PDT 24
Peak memory 190700 kb
Host smart-9c3f4b66-4525-4f69-b558-8b6799e7a570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574202174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.574202174
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3231223492
Short name T29
Test name
Test status
Simulation time 1375504899401 ps
CPU time 984.53 seconds
Started Apr 23 01:15:34 PM PDT 24
Finished Apr 23 01:31:59 PM PDT 24
Peak memory 190720 kb
Host smart-afa8bce6-827d-4eec-834b-09a0848f1436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231223492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3231223492
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.355887428
Short name T219
Test name
Test status
Simulation time 366772057703 ps
CPU time 667.51 seconds
Started Apr 23 01:15:47 PM PDT 24
Finished Apr 23 01:26:54 PM PDT 24
Peak memory 182520 kb
Host smart-0dbb8062-a7d3-49d6-b707-4190d2a19ff0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355887428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.355887428
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1566054098
Short name T248
Test name
Test status
Simulation time 227991098109 ps
CPU time 809.74 seconds
Started Apr 23 01:16:05 PM PDT 24
Finished Apr 23 01:29:36 PM PDT 24
Peak memory 190824 kb
Host smart-6587deba-0901-4a5c-9343-d86efa9140b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566054098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1566054098
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/85.rv_timer_random.3181201529
Short name T317
Test name
Test status
Simulation time 273076161076 ps
CPU time 100.76 seconds
Started Apr 23 01:17:10 PM PDT 24
Finished Apr 23 01:18:51 PM PDT 24
Peak memory 190576 kb
Host smart-d42cd6cc-650f-4ce4-b7f8-193848d5ec0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181201529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3181201529
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.827045343
Short name T311
Test name
Test status
Simulation time 1745294636390 ps
CPU time 490.36 seconds
Started Apr 23 01:14:13 PM PDT 24
Finished Apr 23 01:22:23 PM PDT 24
Peak memory 182484 kb
Host smart-1863c65f-3e2b-4b9f-a88e-6a002832cbd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827045343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.827045343
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/106.rv_timer_random.2799599357
Short name T184
Test name
Test status
Simulation time 557815822495 ps
CPU time 268.71 seconds
Started Apr 23 01:17:21 PM PDT 24
Finished Apr 23 01:21:50 PM PDT 24
Peak memory 190776 kb
Host smart-0559cf45-f8c3-4ef4-8445-b793f8d50864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799599357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2799599357
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1096753545
Short name T240
Test name
Test status
Simulation time 574759865941 ps
CPU time 437.65 seconds
Started Apr 23 01:17:26 PM PDT 24
Finished Apr 23 01:24:45 PM PDT 24
Peak memory 190792 kb
Host smart-df6285b9-4dec-46ca-8ea6-e44e0800e406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096753545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1096753545
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2859589397
Short name T84
Test name
Test status
Simulation time 849064594355 ps
CPU time 1090.67 seconds
Started Apr 23 01:17:47 PM PDT 24
Finished Apr 23 01:35:58 PM PDT 24
Peak memory 192840 kb
Host smart-e7c2d4bb-46e6-40ff-bf16-d4f742015f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859589397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2859589397
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.382703291
Short name T130
Test name
Test status
Simulation time 159120243866 ps
CPU time 606.43 seconds
Started Apr 23 01:18:01 PM PDT 24
Finished Apr 23 01:28:08 PM PDT 24
Peak memory 190720 kb
Host smart-88eea70b-33ff-4cf0-adff-1ea69b1d46d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382703291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.382703291
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3649768032
Short name T296
Test name
Test status
Simulation time 120688376238 ps
CPU time 197.11 seconds
Started Apr 23 01:18:38 PM PDT 24
Finished Apr 23 01:21:56 PM PDT 24
Peak memory 190728 kb
Host smart-9ccdab26-305d-40d6-81f9-35922d5279df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649768032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3649768032
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2776422997
Short name T306
Test name
Test status
Simulation time 797809752781 ps
CPU time 1539.51 seconds
Started Apr 23 01:14:38 PM PDT 24
Finished Apr 23 01:40:18 PM PDT 24
Peak memory 190868 kb
Host smart-ff76326f-0712-40ad-a4b0-8772a4f242e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776422997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2776422997
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.3648692063
Short name T273
Test name
Test status
Simulation time 598151273281 ps
CPU time 511.56 seconds
Started Apr 23 01:16:31 PM PDT 24
Finished Apr 23 01:25:03 PM PDT 24
Peak memory 194112 kb
Host smart-57094256-82c4-44c2-a29b-37bf3c04b780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648692063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3648692063
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.316815238
Short name T292
Test name
Test status
Simulation time 120807796418 ps
CPU time 187.59 seconds
Started Apr 23 01:16:43 PM PDT 24
Finished Apr 23 01:19:51 PM PDT 24
Peak memory 190712 kb
Host smart-6da23552-dbcb-4dae-aea6-09580008e2fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316815238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.316815238
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.38590171
Short name T43
Test name
Test status
Simulation time 522091346870 ps
CPU time 769.26 seconds
Started Apr 23 01:16:41 PM PDT 24
Finished Apr 23 01:29:31 PM PDT 24
Peak memory 190756 kb
Host smart-fe9d2cac-82c2-4ec0-8251-eba2212f9815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38590171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.38590171
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3042323999
Short name T160
Test name
Test status
Simulation time 219562916794 ps
CPU time 624.66 seconds
Started Apr 23 01:14:11 PM PDT 24
Finished Apr 23 01:24:36 PM PDT 24
Peak memory 195008 kb
Host smart-3166d216-76bc-4ba7-9eaf-abaa95f4fcf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042323999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3042323999
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1473833895
Short name T103
Test name
Test status
Simulation time 27111820 ps
CPU time 0.75 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 193288 kb
Host smart-6ebcbe23-c9d9-4a57-887b-2728e78985e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473833895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1473833895
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4101554175
Short name T125
Test name
Test status
Simulation time 443677998 ps
CPU time 1.38 seconds
Started Apr 23 01:10:13 PM PDT 24
Finished Apr 23 01:10:15 PM PDT 24
Peak memory 195132 kb
Host smart-8523a8a8-714a-4cd5-9d27-10899e8f48ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101554175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4101554175
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/102.rv_timer_random.921623557
Short name T252
Test name
Test status
Simulation time 29526024120 ps
CPU time 46.61 seconds
Started Apr 23 01:17:23 PM PDT 24
Finished Apr 23 01:18:10 PM PDT 24
Peak memory 190708 kb
Host smart-89be4a52-93ed-48c4-a42c-eb4743d53e19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921623557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.921623557
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3801565583
Short name T264
Test name
Test status
Simulation time 184990245377 ps
CPU time 2708.23 seconds
Started Apr 23 01:17:23 PM PDT 24
Finished Apr 23 02:02:32 PM PDT 24
Peak memory 190788 kb
Host smart-1524ce2f-a4a0-4ff0-8f62-d68035e8f504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801565583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3801565583
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2109607756
Short name T165
Test name
Test status
Simulation time 156095758494 ps
CPU time 696.39 seconds
Started Apr 23 01:17:26 PM PDT 24
Finished Apr 23 01:29:03 PM PDT 24
Peak memory 190804 kb
Host smart-f957e83e-862b-4c3e-a618-1a2483d55b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109607756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2109607756
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2100280959
Short name T10
Test name
Test status
Simulation time 111827191767 ps
CPU time 541.56 seconds
Started Apr 23 01:17:55 PM PDT 24
Finished Apr 23 01:26:57 PM PDT 24
Peak memory 194240 kb
Host smart-a4f90529-c734-4adb-b284-7f7709d3a5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100280959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2100280959
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2730888275
Short name T243
Test name
Test status
Simulation time 10433236838 ps
CPU time 17.8 seconds
Started Apr 23 01:14:26 PM PDT 24
Finished Apr 23 01:14:45 PM PDT 24
Peak memory 182588 kb
Host smart-0de5817b-9a78-48f3-b84c-c9b295765f56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730888275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2730888275
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/186.rv_timer_random.434565203
Short name T158
Test name
Test status
Simulation time 147830875643 ps
CPU time 249.24 seconds
Started Apr 23 01:18:28 PM PDT 24
Finished Apr 23 01:22:38 PM PDT 24
Peak memory 190812 kb
Host smart-ea53128d-666c-4dca-be18-14a65b487ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434565203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.434565203
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.439615225
Short name T266
Test name
Test status
Simulation time 49130343262 ps
CPU time 241.44 seconds
Started Apr 23 01:18:37 PM PDT 24
Finished Apr 23 01:22:39 PM PDT 24
Peak memory 190800 kb
Host smart-bff2d661-d814-470d-8966-cc3bde55e28c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439615225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.439615225
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1643298227
Short name T132
Test name
Test status
Simulation time 701674266869 ps
CPU time 1086.81 seconds
Started Apr 23 01:14:47 PM PDT 24
Finished Apr 23 01:32:54 PM PDT 24
Peak memory 182564 kb
Host smart-d58aa871-9cb7-4602-8561-044d4e354456
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643298227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1643298227
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3647542104
Short name T254
Test name
Test status
Simulation time 352639860224 ps
CPU time 1869.5 seconds
Started Apr 23 01:14:55 PM PDT 24
Finished Apr 23 01:46:05 PM PDT 24
Peak memory 190688 kb
Host smart-294a0c27-461a-42ca-86c2-4a09b39b05c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647542104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3647542104
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1618514397
Short name T336
Test name
Test status
Simulation time 40487599461 ps
CPU time 40.77 seconds
Started Apr 23 01:15:51 PM PDT 24
Finished Apr 23 01:16:32 PM PDT 24
Peak memory 182584 kb
Host smart-533eba16-049c-452d-bd3d-bd917a316a5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618514397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1618514397
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2177701173
Short name T93
Test name
Test status
Simulation time 460833290971 ps
CPU time 866.69 seconds
Started Apr 23 01:15:51 PM PDT 24
Finished Apr 23 01:30:18 PM PDT 24
Peak memory 190708 kb
Host smart-4ea4cf72-d069-4a10-bed7-2f3c68782e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177701173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2177701173
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_random.1929490118
Short name T310
Test name
Test status
Simulation time 214613753253 ps
CPU time 736.16 seconds
Started Apr 23 01:16:12 PM PDT 24
Finished Apr 23 01:28:29 PM PDT 24
Peak memory 193100 kb
Host smart-0aa41443-77c0-404a-a12c-64f6d78fff79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929490118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1929490118
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2977785736
Short name T327
Test name
Test status
Simulation time 1982072529151 ps
CPU time 882.6 seconds
Started Apr 23 01:14:10 PM PDT 24
Finished Apr 23 01:28:53 PM PDT 24
Peak memory 190728 kb
Host smart-8d678635-5a5b-49cb-aae0-d7eddcd60ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977785736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2977785736
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1384669690
Short name T169
Test name
Test status
Simulation time 33425566938 ps
CPU time 40.06 seconds
Started Apr 23 01:13:58 PM PDT 24
Finished Apr 23 01:14:39 PM PDT 24
Peak memory 190704 kb
Host smart-196424e2-47d3-4316-8f41-0630226eae5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384669690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1384669690
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.966759590
Short name T60
Test name
Test status
Simulation time 192097977154 ps
CPU time 341.25 seconds
Started Apr 23 01:14:19 PM PDT 24
Finished Apr 23 01:20:00 PM PDT 24
Peak memory 190716 kb
Host smart-938f64f6-f0a7-49fd-9662-173a01c08d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966759590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
966759590
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.2386165749
Short name T163
Test name
Test status
Simulation time 89607610787 ps
CPU time 86.09 seconds
Started Apr 23 01:17:22 PM PDT 24
Finished Apr 23 01:18:49 PM PDT 24
Peak memory 182568 kb
Host smart-3c473da3-74d1-41b2-99de-56ee20789092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386165749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2386165749
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1241731813
Short name T232
Test name
Test status
Simulation time 43865794102 ps
CPU time 82.45 seconds
Started Apr 23 01:17:22 PM PDT 24
Finished Apr 23 01:18:45 PM PDT 24
Peak memory 190640 kb
Host smart-0e26a41e-d337-409e-9b35-2b3ed85f3b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241731813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1241731813
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3121217950
Short name T27
Test name
Test status
Simulation time 71510765704 ps
CPU time 58.84 seconds
Started Apr 23 01:14:17 PM PDT 24
Finished Apr 23 01:15:17 PM PDT 24
Peak memory 182344 kb
Host smart-a3cab0a5-5a3a-4c53-803f-5919b2c689b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121217950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3121217950
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/123.rv_timer_random.468801008
Short name T202
Test name
Test status
Simulation time 80591794894 ps
CPU time 314.28 seconds
Started Apr 23 01:17:33 PM PDT 24
Finished Apr 23 01:22:48 PM PDT 24
Peak memory 193492 kb
Host smart-30fd86a4-2323-425f-b98b-10240257c3ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468801008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.468801008
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.984024006
Short name T258
Test name
Test status
Simulation time 216544057746 ps
CPU time 658.39 seconds
Started Apr 23 01:17:38 PM PDT 24
Finished Apr 23 01:28:37 PM PDT 24
Peak memory 190764 kb
Host smart-4262de10-6960-4e20-b813-3b6a252189a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984024006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.984024006
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2644683852
Short name T170
Test name
Test status
Simulation time 2144853597971 ps
CPU time 1110.17 seconds
Started Apr 23 01:14:19 PM PDT 24
Finished Apr 23 01:32:50 PM PDT 24
Peak memory 182596 kb
Host smart-6c98e8a8-844b-432a-81cc-8b2951b3b546
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644683852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2644683852
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2922350511
Short name T38
Test name
Test status
Simulation time 31693930039 ps
CPU time 255.89 seconds
Started Apr 23 01:14:20 PM PDT 24
Finished Apr 23 01:18:37 PM PDT 24
Peak memory 197248 kb
Host smart-15a01035-e551-470c-9021-09b0329be3dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922350511 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2922350511
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.rv_timer_random.2573830359
Short name T148
Test name
Test status
Simulation time 134749494021 ps
CPU time 193.32 seconds
Started Apr 23 01:17:45 PM PDT 24
Finished Apr 23 01:20:59 PM PDT 24
Peak memory 190708 kb
Host smart-4f363dc9-dcbd-4c38-95f7-e7a409e55324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573830359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2573830359
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1809300577
Short name T70
Test name
Test status
Simulation time 300059219203 ps
CPU time 1514.64 seconds
Started Apr 23 01:17:51 PM PDT 24
Finished Apr 23 01:43:06 PM PDT 24
Peak memory 190720 kb
Host smart-7e8fbea4-d2f5-497b-9e10-a8a9fab05bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809300577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1809300577
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2381158029
Short name T159
Test name
Test status
Simulation time 199939030536 ps
CPU time 1308.58 seconds
Started Apr 23 01:17:55 PM PDT 24
Finished Apr 23 01:39:44 PM PDT 24
Peak memory 190796 kb
Host smart-d429343c-faec-4e5e-91e8-e16607f9a416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381158029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2381158029
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2071385539
Short name T260
Test name
Test status
Simulation time 39818113484 ps
CPU time 185.78 seconds
Started Apr 23 01:17:53 PM PDT 24
Finished Apr 23 01:20:59 PM PDT 24
Peak memory 190720 kb
Host smart-8c9da2ed-9908-4194-8053-b1d573671a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071385539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2071385539
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1845847890
Short name T174
Test name
Test status
Simulation time 335451502579 ps
CPU time 889.19 seconds
Started Apr 23 01:14:25 PM PDT 24
Finished Apr 23 01:29:15 PM PDT 24
Peak memory 190652 kb
Host smart-c151aab9-d8ea-453b-8fca-8f82b189aa58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845847890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1845847890
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/178.rv_timer_random.3893424145
Short name T231
Test name
Test status
Simulation time 2611177159182 ps
CPU time 1968.17 seconds
Started Apr 23 01:18:17 PM PDT 24
Finished Apr 23 01:51:06 PM PDT 24
Peak memory 190716 kb
Host smart-e4f6774e-9b4d-4c38-8164-8bf80903c170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893424145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3893424145
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1730757701
Short name T76
Test name
Test status
Simulation time 346552220530 ps
CPU time 356.66 seconds
Started Apr 23 01:14:26 PM PDT 24
Finished Apr 23 01:20:23 PM PDT 24
Peak memory 193836 kb
Host smart-5919913d-3e27-45ef-aa5d-4e1869764e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730757701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1730757701
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/198.rv_timer_random.669131431
Short name T251
Test name
Test status
Simulation time 427881346490 ps
CPU time 185.01 seconds
Started Apr 23 01:18:40 PM PDT 24
Finished Apr 23 01:21:46 PM PDT 24
Peak memory 193156 kb
Host smart-9e5cce63-1219-4f43-839e-35998fa50ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669131431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.669131431
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.4123816790
Short name T133
Test name
Test status
Simulation time 147987682545 ps
CPU time 417.32 seconds
Started Apr 23 01:13:59 PM PDT 24
Finished Apr 23 01:20:57 PM PDT 24
Peak memory 190672 kb
Host smart-900a6287-8f3e-46ee-ab45-fd55c4621b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123816790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4123816790
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1796147978
Short name T192
Test name
Test status
Simulation time 1105667911544 ps
CPU time 567.82 seconds
Started Apr 23 01:14:32 PM PDT 24
Finished Apr 23 01:24:00 PM PDT 24
Peak memory 182588 kb
Host smart-044725bc-2db5-476f-a61f-8705d7abb4b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796147978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1796147978
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_random.3760892401
Short name T145
Test name
Test status
Simulation time 177544423435 ps
CPU time 285.61 seconds
Started Apr 23 01:14:30 PM PDT 24
Finished Apr 23 01:19:16 PM PDT 24
Peak memory 190684 kb
Host smart-f97d883b-a278-4e02-b88a-b62613095249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760892401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3760892401
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.1247723442
Short name T116
Test name
Test status
Simulation time 115948688365 ps
CPU time 214.27 seconds
Started Apr 23 01:14:38 PM PDT 24
Finished Apr 23 01:18:13 PM PDT 24
Peak memory 190724 kb
Host smart-032d8771-46a6-42f7-a2a1-c324c764953f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247723442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1247723442
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1621375067
Short name T212
Test name
Test status
Simulation time 124083934683 ps
CPU time 221.37 seconds
Started Apr 23 01:14:57 PM PDT 24
Finished Apr 23 01:18:39 PM PDT 24
Peak memory 190744 kb
Host smart-162ba063-e090-4e99-8d83-20c4c284ac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621375067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1621375067
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1028142001
Short name T333
Test name
Test status
Simulation time 1414040698960 ps
CPU time 503.25 seconds
Started Apr 23 01:15:16 PM PDT 24
Finished Apr 23 01:23:40 PM PDT 24
Peak memory 194612 kb
Host smart-dfa2dad1-dfa4-457e-9403-97788b135f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028142001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1028142001
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2028002665
Short name T309
Test name
Test status
Simulation time 306880411198 ps
CPU time 399.23 seconds
Started Apr 23 01:16:05 PM PDT 24
Finished Apr 23 01:22:45 PM PDT 24
Peak memory 190716 kb
Host smart-799bb7b5-498f-4c52-a1e4-d6982099e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028002665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2028002665
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_random.1994581036
Short name T239
Test name
Test status
Simulation time 19213246775 ps
CPU time 28.31 seconds
Started Apr 23 01:14:06 PM PDT 24
Finished Apr 23 01:14:35 PM PDT 24
Peak memory 190708 kb
Host smart-16471cd8-f741-4bee-91e5-61e2302102f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994581036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1994581036
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2098742917
Short name T494
Test name
Test status
Simulation time 124072394 ps
CPU time 0.6 seconds
Started Apr 23 01:09:39 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 182548 kb
Host smart-9f59096c-5a8f-47dd-9650-82fcf999b1d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098742917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2098742917
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4201549621
Short name T92
Test name
Test status
Simulation time 238159264 ps
CPU time 2.28 seconds
Started Apr 23 01:09:40 PM PDT 24
Finished Apr 23 01:09:43 PM PDT 24
Peak memory 191044 kb
Host smart-f96fae7e-81ab-44f9-92f8-db5b7e3e464a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201549621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.4201549621
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2929699831
Short name T463
Test name
Test status
Simulation time 14515249 ps
CPU time 0.59 seconds
Started Apr 23 01:09:34 PM PDT 24
Finished Apr 23 01:09:35 PM PDT 24
Peak memory 182560 kb
Host smart-d12a2e2a-4029-4d52-a41b-b91cdc8ea5e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929699831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2929699831
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2075728230
Short name T475
Test name
Test status
Simulation time 30385208 ps
CPU time 0.75 seconds
Started Apr 23 01:09:35 PM PDT 24
Finished Apr 23 01:09:36 PM PDT 24
Peak memory 194828 kb
Host smart-7b4e7bfe-005f-4c23-a88f-43a533e7d94d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075728230 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2075728230
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.198488941
Short name T34
Test name
Test status
Simulation time 14938082 ps
CPU time 0.58 seconds
Started Apr 23 01:09:35 PM PDT 24
Finished Apr 23 01:09:36 PM PDT 24
Peak memory 182556 kb
Host smart-0a03dc93-f719-45e4-9d27-2a3c590b0f71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198488941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.198488941
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.535126929
Short name T525
Test name
Test status
Simulation time 25533340 ps
CPU time 0.58 seconds
Started Apr 23 01:09:31 PM PDT 24
Finished Apr 23 01:09:32 PM PDT 24
Peak memory 182436 kb
Host smart-234db2b5-64e3-4907-a264-028b835730d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535126929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.535126929
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2285302178
Short name T533
Test name
Test status
Simulation time 188865471 ps
CPU time 0.59 seconds
Started Apr 23 01:09:35 PM PDT 24
Finished Apr 23 01:09:37 PM PDT 24
Peak memory 191244 kb
Host smart-0d350a8e-3e8b-4257-906b-6f01784a2937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285302178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2285302178
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3225387621
Short name T532
Test name
Test status
Simulation time 102823210 ps
CPU time 1.02 seconds
Started Apr 23 01:09:31 PM PDT 24
Finished Apr 23 01:09:32 PM PDT 24
Peak memory 197264 kb
Host smart-d72b8550-e438-4946-91f1-5456c1a0baff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225387621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3225387621
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3726329942
Short name T480
Test name
Test status
Simulation time 97296244 ps
CPU time 1.32 seconds
Started Apr 23 01:09:30 PM PDT 24
Finished Apr 23 01:09:32 PM PDT 24
Peak memory 195012 kb
Host smart-ebc5207d-c97a-456b-9d5f-9df7c161596d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726329942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3726329942
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.93326887
Short name T88
Test name
Test status
Simulation time 37265160 ps
CPU time 0.6 seconds
Started Apr 23 01:09:35 PM PDT 24
Finished Apr 23 01:09:36 PM PDT 24
Peak memory 182596 kb
Host smart-cb3a7b9f-f932-4583-893f-b216aca47d18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93326887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasi
ng.93326887
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.622391767
Short name T583
Test name
Test status
Simulation time 1719803725 ps
CPU time 3.71 seconds
Started Apr 23 01:09:35 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 193484 kb
Host smart-cf5853fd-c491-4241-8aba-dbe9a7bdb788
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622391767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.622391767
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3348783000
Short name T576
Test name
Test status
Simulation time 14547969 ps
CPU time 0.55 seconds
Started Apr 23 01:09:34 PM PDT 24
Finished Apr 23 01:09:35 PM PDT 24
Peak memory 182088 kb
Host smart-9f65c799-c722-4246-bd30-953c767e1a4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348783000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3348783000
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4062602192
Short name T33
Test name
Test status
Simulation time 130080477 ps
CPU time 0.92 seconds
Started Apr 23 01:09:37 PM PDT 24
Finished Apr 23 01:09:39 PM PDT 24
Peak memory 197216 kb
Host smart-4d109757-aa4c-4735-968d-0dc26eeb329f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062602192 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4062602192
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4020936286
Short name T470
Test name
Test status
Simulation time 15164232 ps
CPU time 0.56 seconds
Started Apr 23 01:09:36 PM PDT 24
Finished Apr 23 01:09:37 PM PDT 24
Peak memory 182588 kb
Host smart-a103350b-7e59-41d1-81d1-9b49b6c4a70e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020936286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.4020936286
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1987539621
Short name T551
Test name
Test status
Simulation time 23958612 ps
CPU time 0.54 seconds
Started Apr 23 01:09:35 PM PDT 24
Finished Apr 23 01:09:36 PM PDT 24
Peak memory 182452 kb
Host smart-801dd016-6c03-4042-92fd-14f96dfaaa3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987539621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1987539621
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.289883068
Short name T487
Test name
Test status
Simulation time 208304102 ps
CPU time 1.16 seconds
Started Apr 23 01:09:35 PM PDT 24
Finished Apr 23 01:09:37 PM PDT 24
Peak memory 197484 kb
Host smart-84ab9364-7de9-452f-a5dd-e1cb3ae5e922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289883068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.289883068
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1103989452
Short name T124
Test name
Test status
Simulation time 875516268 ps
CPU time 1.35 seconds
Started Apr 23 01:09:35 PM PDT 24
Finished Apr 23 01:09:37 PM PDT 24
Peak memory 195344 kb
Host smart-424c8f6f-20ef-46bf-9958-8f77859ec405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103989452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1103989452
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2971606780
Short name T54
Test name
Test status
Simulation time 19930600 ps
CPU time 0.68 seconds
Started Apr 23 01:10:06 PM PDT 24
Finished Apr 23 01:10:07 PM PDT 24
Peak memory 194256 kb
Host smart-79d3310f-ed75-4c35-bc98-fb06e15ce56f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971606780 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2971606780
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1932956587
Short name T504
Test name
Test status
Simulation time 15605617 ps
CPU time 0.62 seconds
Started Apr 23 01:10:01 PM PDT 24
Finished Apr 23 01:10:02 PM PDT 24
Peak memory 182088 kb
Host smart-e2ef659c-0bf6-46bf-bd77-6e8b3ec4fc31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932956587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1932956587
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.4132592924
Short name T500
Test name
Test status
Simulation time 41964677 ps
CPU time 0.57 seconds
Started Apr 23 01:10:00 PM PDT 24
Finished Apr 23 01:10:01 PM PDT 24
Peak memory 182520 kb
Host smart-0ddda3b9-a26c-48cd-9c24-df9bec01c044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132592924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.4132592924
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2679697185
Short name T539
Test name
Test status
Simulation time 36350336 ps
CPU time 0.82 seconds
Started Apr 23 01:10:01 PM PDT 24
Finished Apr 23 01:10:02 PM PDT 24
Peak memory 192636 kb
Host smart-c65d18cc-9cf9-4702-ab88-4fd73790ffc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679697185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2679697185
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1813849876
Short name T520
Test name
Test status
Simulation time 852945571 ps
CPU time 1.57 seconds
Started Apr 23 01:09:59 PM PDT 24
Finished Apr 23 01:10:01 PM PDT 24
Peak memory 197412 kb
Host smart-c1668b66-c7a9-4826-9fd1-e0441c6067e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813849876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1813849876
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1435152562
Short name T513
Test name
Test status
Simulation time 107783529 ps
CPU time 1.13 seconds
Started Apr 23 01:09:59 PM PDT 24
Finished Apr 23 01:10:01 PM PDT 24
Peak memory 195156 kb
Host smart-56e69f29-332b-4fb9-9e6d-c75e3f6d823e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435152562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1435152562
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.990183597
Short name T468
Test name
Test status
Simulation time 39822387 ps
CPU time 0.94 seconds
Started Apr 23 01:10:06 PM PDT 24
Finished Apr 23 01:10:08 PM PDT 24
Peak memory 196416 kb
Host smart-439c94fc-38ba-4238-8c61-7ca3de539b4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990183597 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.990183597
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3758264511
Short name T518
Test name
Test status
Simulation time 14041039 ps
CPU time 0.6 seconds
Started Apr 23 01:10:02 PM PDT 24
Finished Apr 23 01:10:03 PM PDT 24
Peak memory 182084 kb
Host smart-cf94f86f-66b2-4af1-929f-2f823f29992b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758264511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3758264511
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2084245784
Short name T498
Test name
Test status
Simulation time 44860298 ps
CPU time 0.54 seconds
Started Apr 23 01:09:58 PM PDT 24
Finished Apr 23 01:09:59 PM PDT 24
Peak memory 182140 kb
Host smart-c4909fe4-67e8-4530-b44f-0d4154dfea95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084245784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2084245784
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3276316244
Short name T56
Test name
Test status
Simulation time 141783728 ps
CPU time 0.77 seconds
Started Apr 23 01:09:58 PM PDT 24
Finished Apr 23 01:10:00 PM PDT 24
Peak memory 193336 kb
Host smart-274b0232-6691-481a-9a44-6cdad75375e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276316244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3276316244
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3900092194
Short name T58
Test name
Test status
Simulation time 1477145115 ps
CPU time 2.9 seconds
Started Apr 23 01:10:06 PM PDT 24
Finished Apr 23 01:10:10 PM PDT 24
Peak memory 197472 kb
Host smart-27eb74b4-7c7f-4340-90dc-6458db24454c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900092194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3900092194
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1618978528
Short name T569
Test name
Test status
Simulation time 184086003 ps
CPU time 1.3 seconds
Started Apr 23 01:09:58 PM PDT 24
Finished Apr 23 01:10:00 PM PDT 24
Peak memory 195372 kb
Host smart-e336c015-564b-40c1-b2c0-fb12eea78d55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618978528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1618978528
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1002030970
Short name T519
Test name
Test status
Simulation time 92181445 ps
CPU time 0.86 seconds
Started Apr 23 01:09:57 PM PDT 24
Finished Apr 23 01:09:58 PM PDT 24
Peak memory 196864 kb
Host smart-e2a4b377-8c89-4aa1-ab41-5ef71e3f0716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002030970 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1002030970
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2095033027
Short name T501
Test name
Test status
Simulation time 15789294 ps
CPU time 0.56 seconds
Started Apr 23 01:10:00 PM PDT 24
Finished Apr 23 01:10:01 PM PDT 24
Peak memory 182584 kb
Host smart-59f0d5ea-7bc0-4417-9b8a-fb3c405f9bdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095033027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2095033027
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3816654682
Short name T461
Test name
Test status
Simulation time 56326771 ps
CPU time 0.59 seconds
Started Apr 23 01:10:01 PM PDT 24
Finished Apr 23 01:10:02 PM PDT 24
Peak memory 182032 kb
Host smart-7c10ab97-a413-47ce-b5b3-5279963fbc99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816654682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3816654682
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3970375161
Short name T109
Test name
Test status
Simulation time 89382676 ps
CPU time 0.77 seconds
Started Apr 23 01:09:59 PM PDT 24
Finished Apr 23 01:10:00 PM PDT 24
Peak memory 191612 kb
Host smart-16f475a5-ca6e-45b6-b497-276a9a6d5166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970375161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3970375161
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1657770802
Short name T472
Test name
Test status
Simulation time 55686437 ps
CPU time 2.8 seconds
Started Apr 23 01:09:59 PM PDT 24
Finished Apr 23 01:10:02 PM PDT 24
Peak memory 197440 kb
Host smart-c46e4353-8425-404d-9f51-be3143ff9c75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657770802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1657770802
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3634516551
Short name T561
Test name
Test status
Simulation time 40850753 ps
CPU time 0.9 seconds
Started Apr 23 01:10:00 PM PDT 24
Finished Apr 23 01:10:02 PM PDT 24
Peak memory 182924 kb
Host smart-967b374f-b348-4b8d-a97c-1ca91b3aa557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634516551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3634516551
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1745774649
Short name T552
Test name
Test status
Simulation time 44523551 ps
CPU time 0.63 seconds
Started Apr 23 01:10:03 PM PDT 24
Finished Apr 23 01:10:04 PM PDT 24
Peak memory 193032 kb
Host smart-4371eb91-cdbd-4a4b-a8ac-dc3d64c76b99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745774649 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1745774649
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.959671688
Short name T497
Test name
Test status
Simulation time 13172714 ps
CPU time 0.58 seconds
Started Apr 23 01:10:03 PM PDT 24
Finished Apr 23 01:10:04 PM PDT 24
Peak memory 182520 kb
Host smart-0dd5c8b0-44b5-4a4c-b456-f61b223c587c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959671688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.959671688
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3465308944
Short name T563
Test name
Test status
Simulation time 167628227 ps
CPU time 0.63 seconds
Started Apr 23 01:10:03 PM PDT 24
Finished Apr 23 01:10:04 PM PDT 24
Peak memory 182500 kb
Host smart-1ff59497-b132-4396-8cb1-7b6eb1326848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465308944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3465308944
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2816524854
Short name T527
Test name
Test status
Simulation time 89059030 ps
CPU time 0.64 seconds
Started Apr 23 01:10:06 PM PDT 24
Finished Apr 23 01:10:07 PM PDT 24
Peak memory 191596 kb
Host smart-417de87a-9c32-4cdb-ab14-3682457b9940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816524854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2816524854
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2249549427
Short name T538
Test name
Test status
Simulation time 234428230 ps
CPU time 2.35 seconds
Started Apr 23 01:10:06 PM PDT 24
Finished Apr 23 01:10:09 PM PDT 24
Peak memory 197452 kb
Host smart-1bfbb4d2-f8f6-4766-8c48-23b4ec7a83c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249549427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2249549427
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4284775456
Short name T484
Test name
Test status
Simulation time 193102194 ps
CPU time 0.83 seconds
Started Apr 23 01:10:04 PM PDT 24
Finished Apr 23 01:10:06 PM PDT 24
Peak memory 192692 kb
Host smart-3dadb0bb-2ad8-4cb7-be4a-03b6e58f09f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284775456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.4284775456
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1935569199
Short name T515
Test name
Test status
Simulation time 19665293 ps
CPU time 0.96 seconds
Started Apr 23 01:10:02 PM PDT 24
Finished Apr 23 01:10:03 PM PDT 24
Peak memory 197132 kb
Host smart-b6d0cec1-277e-4b91-ba9a-b54791f1e37b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935569199 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1935569199
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2337117948
Short name T52
Test name
Test status
Simulation time 17109008 ps
CPU time 0.59 seconds
Started Apr 23 01:10:02 PM PDT 24
Finished Apr 23 01:10:03 PM PDT 24
Peak memory 182576 kb
Host smart-cf255109-8b4b-458a-8ecb-f3253216c66b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337117948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2337117948
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.398371400
Short name T462
Test name
Test status
Simulation time 20295317 ps
CPU time 0.56 seconds
Started Apr 23 01:10:03 PM PDT 24
Finished Apr 23 01:10:03 PM PDT 24
Peak memory 181988 kb
Host smart-4dbc4b6c-214c-4799-9d14-be68dae63b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398371400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.398371400
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.559592608
Short name T521
Test name
Test status
Simulation time 28726250 ps
CPU time 0.73 seconds
Started Apr 23 01:10:04 PM PDT 24
Finished Apr 23 01:10:05 PM PDT 24
Peak memory 191648 kb
Host smart-27799884-e877-4b37-9263-0f70adbe00ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559592608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.559592608
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2944769715
Short name T505
Test name
Test status
Simulation time 130858537 ps
CPU time 1.07 seconds
Started Apr 23 01:10:04 PM PDT 24
Finished Apr 23 01:10:06 PM PDT 24
Peak memory 195588 kb
Host smart-e16eb544-ae67-4981-8a13-1e77aca32b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944769715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2944769715
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2946804175
Short name T31
Test name
Test status
Simulation time 295962765 ps
CPU time 1.06 seconds
Started Apr 23 01:10:04 PM PDT 24
Finished Apr 23 01:10:06 PM PDT 24
Peak memory 195100 kb
Host smart-bdf1cc63-4498-4aa5-a0e5-d13d06df6bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946804175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2946804175
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2739942825
Short name T464
Test name
Test status
Simulation time 163333204 ps
CPU time 0.9 seconds
Started Apr 23 01:10:10 PM PDT 24
Finished Apr 23 01:10:12 PM PDT 24
Peak memory 196608 kb
Host smart-d382f90c-f97e-41fd-bb35-05556d00435d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739942825 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2739942825
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1661865197
Short name T478
Test name
Test status
Simulation time 11747669 ps
CPU time 0.57 seconds
Started Apr 23 01:10:10 PM PDT 24
Finished Apr 23 01:10:11 PM PDT 24
Peak memory 182536 kb
Host smart-188514da-9a3c-4b56-ab72-e1c19586595e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661865197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1661865197
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.575629444
Short name T492
Test name
Test status
Simulation time 78375732 ps
CPU time 0.58 seconds
Started Apr 23 01:10:09 PM PDT 24
Finished Apr 23 01:10:10 PM PDT 24
Peak memory 182004 kb
Host smart-906a18f9-691d-45b2-bd51-7bbb0f6b8fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575629444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.575629444
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.558952507
Short name T104
Test name
Test status
Simulation time 26488660 ps
CPU time 0.69 seconds
Started Apr 23 01:10:09 PM PDT 24
Finished Apr 23 01:10:11 PM PDT 24
Peak memory 191908 kb
Host smart-a0d05a19-3db0-4b72-b209-808b52529433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558952507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.558952507
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1494700612
Short name T565
Test name
Test status
Simulation time 219244536 ps
CPU time 1.16 seconds
Started Apr 23 01:10:03 PM PDT 24
Finished Apr 23 01:10:05 PM PDT 24
Peak memory 194676 kb
Host smart-96b75dca-e1e1-4520-867d-78c49b9e8913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494700612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1494700612
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2926842330
Short name T32
Test name
Test status
Simulation time 125299809 ps
CPU time 1.49 seconds
Started Apr 23 01:10:03 PM PDT 24
Finished Apr 23 01:10:05 PM PDT 24
Peak memory 194332 kb
Host smart-e36db7e4-1131-42ef-a887-525bd88efc10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926842330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2926842330
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.403639222
Short name T524
Test name
Test status
Simulation time 64578681 ps
CPU time 0.93 seconds
Started Apr 23 01:10:10 PM PDT 24
Finished Apr 23 01:10:11 PM PDT 24
Peak memory 197292 kb
Host smart-4ec9ebd3-2e64-4978-8a20-95ac4516511d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403639222 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.403639222
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1173021919
Short name T474
Test name
Test status
Simulation time 47251438 ps
CPU time 0.55 seconds
Started Apr 23 01:10:11 PM PDT 24
Finished Apr 23 01:10:12 PM PDT 24
Peak memory 182528 kb
Host smart-075ecf4e-74ae-4afb-982d-1741affc3762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173021919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1173021919
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.939563743
Short name T485
Test name
Test status
Simulation time 45039434 ps
CPU time 0.54 seconds
Started Apr 23 01:10:09 PM PDT 24
Finished Apr 23 01:10:10 PM PDT 24
Peak memory 182160 kb
Host smart-675f37e4-1c1a-4abb-ada0-8fe8b88d9964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939563743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.939563743
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1073391150
Short name T108
Test name
Test status
Simulation time 22923364 ps
CPU time 0.81 seconds
Started Apr 23 01:10:10 PM PDT 24
Finished Apr 23 01:10:11 PM PDT 24
Peak memory 193152 kb
Host smart-f05b766f-49a2-4017-b88e-57c522b2c61e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073391150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1073391150
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.609558557
Short name T489
Test name
Test status
Simulation time 35733429 ps
CPU time 1.67 seconds
Started Apr 23 01:10:10 PM PDT 24
Finished Apr 23 01:10:12 PM PDT 24
Peak memory 197440 kb
Host smart-bbdf45ac-9eae-4557-bf02-710024fb2eb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609558557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.609558557
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3915282242
Short name T493
Test name
Test status
Simulation time 71583559 ps
CPU time 1.12 seconds
Started Apr 23 01:10:12 PM PDT 24
Finished Apr 23 01:10:13 PM PDT 24
Peak memory 183280 kb
Host smart-d5e2a12e-f01e-4986-825c-f17ba8add860
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915282242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3915282242
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3868349170
Short name T570
Test name
Test status
Simulation time 23570001 ps
CPU time 1.02 seconds
Started Apr 23 01:10:12 PM PDT 24
Finished Apr 23 01:10:14 PM PDT 24
Peak memory 197256 kb
Host smart-b12c0e38-8bbb-4090-b75a-a28a0b59284a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868349170 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3868349170
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1622701815
Short name T476
Test name
Test status
Simulation time 16058313 ps
CPU time 0.57 seconds
Started Apr 23 01:10:09 PM PDT 24
Finished Apr 23 01:10:10 PM PDT 24
Peak memory 182568 kb
Host smart-9e898cc0-a9ba-4dff-9cb2-38902cc54cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622701815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1622701815
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2142813091
Short name T107
Test name
Test status
Simulation time 90467430 ps
CPU time 0.79 seconds
Started Apr 23 01:10:09 PM PDT 24
Finished Apr 23 01:10:11 PM PDT 24
Peak memory 191580 kb
Host smart-6e039ddd-38f8-45e1-a831-d5c7c0d452c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142813091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2142813091
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.876492142
Short name T540
Test name
Test status
Simulation time 230007540 ps
CPU time 2.01 seconds
Started Apr 23 01:10:11 PM PDT 24
Finished Apr 23 01:10:13 PM PDT 24
Peak memory 197444 kb
Host smart-4cc9204d-310a-4742-b4e0-bf4c9e8817c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876492142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.876492142
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3283249012
Short name T530
Test name
Test status
Simulation time 45962363 ps
CPU time 0.9 seconds
Started Apr 23 01:10:09 PM PDT 24
Finished Apr 23 01:10:11 PM PDT 24
Peak memory 182836 kb
Host smart-f1afd3c7-5f5b-4280-85bf-129f7f34554d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283249012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3283249012
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2249770614
Short name T517
Test name
Test status
Simulation time 70136850 ps
CPU time 0.72 seconds
Started Apr 23 01:10:23 PM PDT 24
Finished Apr 23 01:10:25 PM PDT 24
Peak memory 195256 kb
Host smart-e9667590-b9c9-469b-a4cf-c8a822fb01d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249770614 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2249770614
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1550909867
Short name T564
Test name
Test status
Simulation time 31454364 ps
CPU time 0.63 seconds
Started Apr 23 01:10:16 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 182492 kb
Host smart-a2f7ae29-7e00-4d05-bfcd-653177d8e944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550909867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1550909867
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.569353959
Short name T456
Test name
Test status
Simulation time 56289761 ps
CPU time 0.55 seconds
Started Apr 23 01:10:23 PM PDT 24
Finished Apr 23 01:10:24 PM PDT 24
Peak memory 182512 kb
Host smart-3b1e10c2-3a25-4bd7-95a1-2f6c40d6c3ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569353959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.569353959
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3378314754
Short name T574
Test name
Test status
Simulation time 26880931 ps
CPU time 0.63 seconds
Started Apr 23 01:10:14 PM PDT 24
Finished Apr 23 01:10:15 PM PDT 24
Peak memory 191920 kb
Host smart-fc51a9a6-0996-46d4-bbef-1e267f96c7e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378314754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3378314754
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4270881625
Short name T580
Test name
Test status
Simulation time 213015386 ps
CPU time 1.41 seconds
Started Apr 23 01:10:13 PM PDT 24
Finished Apr 23 01:10:15 PM PDT 24
Peak memory 197456 kb
Host smart-b8042e66-9d72-4f1d-bcc8-67979465656e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270881625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4270881625
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2958153612
Short name T579
Test name
Test status
Simulation time 48347901 ps
CPU time 0.85 seconds
Started Apr 23 01:10:12 PM PDT 24
Finished Apr 23 01:10:14 PM PDT 24
Peak memory 195756 kb
Host smart-80741ef0-a7e7-4ef6-a0f9-88e561f7331f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958153612 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2958153612
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4073407575
Short name T57
Test name
Test status
Simulation time 11832488 ps
CPU time 0.59 seconds
Started Apr 23 01:10:11 PM PDT 24
Finished Apr 23 01:10:12 PM PDT 24
Peak memory 182344 kb
Host smart-9efbad08-87ed-4dd8-a097-ee8735e6aad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073407575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.4073407575
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4063656151
Short name T512
Test name
Test status
Simulation time 14004016 ps
CPU time 0.55 seconds
Started Apr 23 01:10:13 PM PDT 24
Finished Apr 23 01:10:15 PM PDT 24
Peak memory 181932 kb
Host smart-928ed170-92cd-4f6d-ad41-f63aae182513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063656151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4063656151
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1166827240
Short name T543
Test name
Test status
Simulation time 25707369 ps
CPU time 0.62 seconds
Started Apr 23 01:10:23 PM PDT 24
Finished Apr 23 01:10:25 PM PDT 24
Peak memory 191472 kb
Host smart-1dc52d70-9037-439e-bb61-a62af77b80a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166827240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1166827240
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2705799291
Short name T466
Test name
Test status
Simulation time 92640045 ps
CPU time 1.24 seconds
Started Apr 23 01:10:14 PM PDT 24
Finished Apr 23 01:10:16 PM PDT 24
Peak memory 197424 kb
Host smart-c1e583bf-c0f5-475d-b507-d33ce458c145
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705799291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2705799291
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2711969061
Short name T541
Test name
Test status
Simulation time 92785163 ps
CPU time 1.15 seconds
Started Apr 23 01:10:16 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 194800 kb
Host smart-8dc1e021-71d1-47b7-a082-74eb5c54798e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711969061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2711969061
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1618276381
Short name T50
Test name
Test status
Simulation time 236039467 ps
CPU time 0.81 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 182564 kb
Host smart-054b0b90-7f18-41b4-ba34-e3d0a857dacc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618276381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1618276381
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.507472350
Short name T459
Test name
Test status
Simulation time 750266275 ps
CPU time 2.56 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:42 PM PDT 24
Peak memory 190936 kb
Host smart-9bba3202-db96-42b0-bcb9-ff5a5ec3cc52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507472350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.507472350
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3723688594
Short name T55
Test name
Test status
Simulation time 19568181 ps
CPU time 0.58 seconds
Started Apr 23 01:09:39 PM PDT 24
Finished Apr 23 01:09:41 PM PDT 24
Peak memory 182628 kb
Host smart-13be4a31-4709-4526-91e6-7d38a597e1ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723688594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3723688594
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.42457120
Short name T554
Test name
Test status
Simulation time 103429245 ps
CPU time 1.12 seconds
Started Apr 23 01:09:36 PM PDT 24
Finished Apr 23 01:09:38 PM PDT 24
Peak memory 197528 kb
Host smart-b7dd2d9b-65fc-4b46-9f06-23a7fa130929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42457120 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.42457120
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3730381314
Short name T91
Test name
Test status
Simulation time 52708776 ps
CPU time 0.57 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 182656 kb
Host smart-3b4d49f5-d318-4917-8472-67ac7954c703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730381314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3730381314
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1611691411
Short name T555
Test name
Test status
Simulation time 11614272 ps
CPU time 0.56 seconds
Started Apr 23 01:09:39 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 182416 kb
Host smart-c8886960-71f6-4106-b4d8-9b34fdbff6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611691411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1611691411
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4046446432
Short name T582
Test name
Test status
Simulation time 38581103 ps
CPU time 0.84 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 193328 kb
Host smart-0205117f-ab1c-43a3-a4a7-655fc7d897bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046446432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4046446432
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.394634426
Short name T511
Test name
Test status
Simulation time 93289033 ps
CPU time 2.57 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:41 PM PDT 24
Peak memory 197532 kb
Host smart-77c27c9c-63b3-45b0-af01-da13d722782d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394634426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.394634426
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.657385163
Short name T534
Test name
Test status
Simulation time 74989803 ps
CPU time 0.54 seconds
Started Apr 23 01:10:15 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 181924 kb
Host smart-0a593160-7a3e-410b-87a8-70fc6060d33b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657385163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.657385163
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3802534416
Short name T495
Test name
Test status
Simulation time 14768985 ps
CPU time 0.54 seconds
Started Apr 23 01:10:12 PM PDT 24
Finished Apr 23 01:10:14 PM PDT 24
Peak memory 182444 kb
Host smart-0bbf6847-df17-47c5-9e68-143e8dca6997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802534416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3802534416
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3239050018
Short name T562
Test name
Test status
Simulation time 16867180 ps
CPU time 0.58 seconds
Started Apr 23 01:10:24 PM PDT 24
Finished Apr 23 01:10:25 PM PDT 24
Peak memory 182436 kb
Host smart-535d93a3-0fa2-433e-a3d7-e954c258bcdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239050018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3239050018
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1198173024
Short name T568
Test name
Test status
Simulation time 43507797 ps
CPU time 0.57 seconds
Started Apr 23 01:10:15 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 182496 kb
Host smart-df01469b-19a0-4865-b7cd-cbed6aa68c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198173024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1198173024
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2066115525
Short name T471
Test name
Test status
Simulation time 17213374 ps
CPU time 0.57 seconds
Started Apr 23 01:10:12 PM PDT 24
Finished Apr 23 01:10:14 PM PDT 24
Peak memory 182476 kb
Host smart-a93d7377-ba81-420a-b2e0-5223d85572df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066115525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2066115525
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3958080503
Short name T546
Test name
Test status
Simulation time 146707488 ps
CPU time 0.54 seconds
Started Apr 23 01:10:13 PM PDT 24
Finished Apr 23 01:10:14 PM PDT 24
Peak memory 181940 kb
Host smart-36434845-a76f-4e7b-9f14-42e7bfc91ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958080503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3958080503
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1038488810
Short name T544
Test name
Test status
Simulation time 46001205 ps
CPU time 0.58 seconds
Started Apr 23 01:10:18 PM PDT 24
Finished Apr 23 01:10:19 PM PDT 24
Peak memory 182588 kb
Host smart-27021da3-8a03-4762-80f5-33da46fa04d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038488810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1038488810
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.405073141
Short name T572
Test name
Test status
Simulation time 14349546 ps
CPU time 0.57 seconds
Started Apr 23 01:10:11 PM PDT 24
Finished Apr 23 01:10:12 PM PDT 24
Peak memory 182536 kb
Host smart-f483897b-5b4e-4608-a7dd-7b2c1ea27d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405073141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.405073141
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.689739547
Short name T483
Test name
Test status
Simulation time 24018832 ps
CPU time 0.55 seconds
Started Apr 23 01:10:12 PM PDT 24
Finished Apr 23 01:10:14 PM PDT 24
Peak memory 182512 kb
Host smart-d613c46b-71b8-445f-a583-599ee2ec029e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689739547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.689739547
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.862327006
Short name T535
Test name
Test status
Simulation time 18975299 ps
CPU time 0.55 seconds
Started Apr 23 01:10:18 PM PDT 24
Finished Apr 23 01:10:20 PM PDT 24
Peak memory 182540 kb
Host smart-d8703074-dd36-488e-be21-ad6d9607d998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862327006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.862327006
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.624072199
Short name T536
Test name
Test status
Simulation time 29148756 ps
CPU time 0.74 seconds
Started Apr 23 01:09:44 PM PDT 24
Finished Apr 23 01:09:45 PM PDT 24
Peak memory 182536 kb
Host smart-97a7da70-dbce-4cf5-b7ea-2eb4edd76a1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624072199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.624072199
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.889360622
Short name T89
Test name
Test status
Simulation time 86505875 ps
CPU time 3.12 seconds
Started Apr 23 01:09:45 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 182752 kb
Host smart-53344d21-7713-4b3c-9263-b14eb2f5075c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889360622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.889360622
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2457106229
Short name T573
Test name
Test status
Simulation time 16295687 ps
CPU time 0.57 seconds
Started Apr 23 01:09:45 PM PDT 24
Finished Apr 23 01:09:47 PM PDT 24
Peak memory 182564 kb
Host smart-fb2aecf6-cc4c-430f-a5b1-f2093e2dee07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457106229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2457106229
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2443120778
Short name T499
Test name
Test status
Simulation time 22871539 ps
CPU time 0.99 seconds
Started Apr 23 01:09:42 PM PDT 24
Finished Apr 23 01:09:43 PM PDT 24
Peak memory 197288 kb
Host smart-249bfc9d-39b7-47f9-934c-9d521c65ae0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443120778 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2443120778
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1068511032
Short name T559
Test name
Test status
Simulation time 69448099 ps
CPU time 0.59 seconds
Started Apr 23 01:09:44 PM PDT 24
Finished Apr 23 01:09:45 PM PDT 24
Peak memory 182536 kb
Host smart-68dc35c8-2be9-44da-b741-c527c6328732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068511032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1068511032
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3611500464
Short name T529
Test name
Test status
Simulation time 15258152 ps
CPU time 0.54 seconds
Started Apr 23 01:09:36 PM PDT 24
Finished Apr 23 01:09:37 PM PDT 24
Peak memory 182444 kb
Host smart-11104925-e919-459d-9067-4c0d12fb98e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611500464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3611500464
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.683557100
Short name T105
Test name
Test status
Simulation time 16478943 ps
CPU time 0.69 seconds
Started Apr 23 01:09:44 PM PDT 24
Finished Apr 23 01:09:45 PM PDT 24
Peak memory 192700 kb
Host smart-0d6b2bee-032c-4a2b-bbf6-58408691af7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683557100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.683557100
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3925384891
Short name T537
Test name
Test status
Simulation time 112096776 ps
CPU time 2.19 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:41 PM PDT 24
Peak memory 197468 kb
Host smart-c6e9a990-8b30-4974-aab0-4295f87d9dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925384891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3925384891
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1252614349
Short name T123
Test name
Test status
Simulation time 79835047 ps
CPU time 1.11 seconds
Started Apr 23 01:09:38 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 195052 kb
Host smart-60950442-c88f-4300-b7b9-87a19a89e1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252614349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1252614349
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1033266419
Short name T465
Test name
Test status
Simulation time 12213436 ps
CPU time 0.53 seconds
Started Apr 23 01:10:24 PM PDT 24
Finished Apr 23 01:10:25 PM PDT 24
Peak memory 182128 kb
Host smart-f9febf74-8170-4130-9467-ed01c82e4815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033266419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1033266419
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1801626508
Short name T496
Test name
Test status
Simulation time 58598439 ps
CPU time 0.55 seconds
Started Apr 23 01:10:23 PM PDT 24
Finished Apr 23 01:10:24 PM PDT 24
Peak memory 182516 kb
Host smart-7db4afad-0ae7-4716-94a7-6ceda52c53d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801626508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1801626508
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.399290890
Short name T469
Test name
Test status
Simulation time 21792446 ps
CPU time 0.55 seconds
Started Apr 23 01:10:18 PM PDT 24
Finished Apr 23 01:10:19 PM PDT 24
Peak memory 182432 kb
Host smart-efee7083-adf6-42f6-b4c0-e3312cae5031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399290890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.399290890
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1330561835
Short name T523
Test name
Test status
Simulation time 13641638 ps
CPU time 0.58 seconds
Started Apr 23 01:10:14 PM PDT 24
Finished Apr 23 01:10:15 PM PDT 24
Peak memory 182412 kb
Host smart-aee14fdb-82f2-4c0e-a5c6-96687632a213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330561835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1330561835
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.538800508
Short name T503
Test name
Test status
Simulation time 29238051 ps
CPU time 0.57 seconds
Started Apr 23 01:10:13 PM PDT 24
Finished Apr 23 01:10:14 PM PDT 24
Peak memory 182520 kb
Host smart-5003d532-625b-48fb-8579-3a2006b1d171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538800508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.538800508
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2034503083
Short name T531
Test name
Test status
Simulation time 53488875 ps
CPU time 0.52 seconds
Started Apr 23 01:10:13 PM PDT 24
Finished Apr 23 01:10:15 PM PDT 24
Peak memory 182460 kb
Host smart-cdc6a977-5aab-4fde-abf0-fdeb748393d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034503083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2034503083
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3925356291
Short name T510
Test name
Test status
Simulation time 54054691 ps
CPU time 0.53 seconds
Started Apr 23 01:10:13 PM PDT 24
Finished Apr 23 01:10:15 PM PDT 24
Peak memory 182524 kb
Host smart-b0e32dbc-d213-4cc6-a03e-4c03870338ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925356291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3925356291
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2873395881
Short name T550
Test name
Test status
Simulation time 69921515 ps
CPU time 0.51 seconds
Started Apr 23 01:10:13 PM PDT 24
Finished Apr 23 01:10:15 PM PDT 24
Peak memory 181956 kb
Host smart-b93acc2a-58ae-49ab-b751-aa15169d0a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873395881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2873395881
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1524327398
Short name T481
Test name
Test status
Simulation time 55842263 ps
CPU time 0.55 seconds
Started Apr 23 01:10:20 PM PDT 24
Finished Apr 23 01:10:21 PM PDT 24
Peak memory 182480 kb
Host smart-70a77b0d-80c6-4d33-b8c5-662d9247191f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524327398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1524327398
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.935412766
Short name T491
Test name
Test status
Simulation time 15640669 ps
CPU time 0.56 seconds
Started Apr 23 01:10:16 PM PDT 24
Finished Apr 23 01:10:18 PM PDT 24
Peak memory 182448 kb
Host smart-ee1aff87-3e8d-4152-b9fb-27b168df3cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935412766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.935412766
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2522207690
Short name T102
Test name
Test status
Simulation time 119269065 ps
CPU time 0.74 seconds
Started Apr 23 01:09:42 PM PDT 24
Finished Apr 23 01:09:44 PM PDT 24
Peak memory 192408 kb
Host smart-63d037b2-d639-4415-a976-32b8c6e5ebc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522207690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2522207690
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.435073507
Short name T90
Test name
Test status
Simulation time 301884165 ps
CPU time 2.44 seconds
Started Apr 23 01:09:45 PM PDT 24
Finished Apr 23 01:09:48 PM PDT 24
Peak memory 191008 kb
Host smart-68e5b778-e0ee-4b4d-b3f4-e7d164ad6571
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435073507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.435073507
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3920615919
Short name T458
Test name
Test status
Simulation time 16378467 ps
CPU time 0.62 seconds
Started Apr 23 01:09:43 PM PDT 24
Finished Apr 23 01:09:44 PM PDT 24
Peak memory 182096 kb
Host smart-b0495067-9893-4f05-ba86-5c93f353b14f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920615919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3920615919
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2806300720
Short name T571
Test name
Test status
Simulation time 20017410 ps
CPU time 0.66 seconds
Started Apr 23 01:09:44 PM PDT 24
Finished Apr 23 01:09:45 PM PDT 24
Peak memory 194372 kb
Host smart-a3468bc1-a256-4473-97bc-7d7c6ecbdb22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806300720 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2806300720
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3689583825
Short name T479
Test name
Test status
Simulation time 20703790 ps
CPU time 0.52 seconds
Started Apr 23 01:09:41 PM PDT 24
Finished Apr 23 01:09:42 PM PDT 24
Peak memory 182468 kb
Host smart-ece26e7e-8b63-4191-9d4a-e74951955aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689583825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3689583825
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3637766278
Short name T488
Test name
Test status
Simulation time 13324464 ps
CPU time 0.57 seconds
Started Apr 23 01:09:42 PM PDT 24
Finished Apr 23 01:09:43 PM PDT 24
Peak memory 182492 kb
Host smart-bf1ad7d3-ba03-4923-aca1-07234c3c307e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637766278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3637766278
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1181085705
Short name T106
Test name
Test status
Simulation time 54199084 ps
CPU time 0.69 seconds
Started Apr 23 01:09:44 PM PDT 24
Finished Apr 23 01:09:45 PM PDT 24
Peak memory 191560 kb
Host smart-3c09023f-2f3e-4031-9b6f-184ac7b9d926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181085705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1181085705
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3434366286
Short name T548
Test name
Test status
Simulation time 645331996 ps
CPU time 2.97 seconds
Started Apr 23 01:09:44 PM PDT 24
Finished Apr 23 01:09:47 PM PDT 24
Peak memory 197460 kb
Host smart-0b0d867f-13e9-4ac9-9e69-a61efa0b60d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434366286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3434366286
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.730274479
Short name T514
Test name
Test status
Simulation time 70359521 ps
CPU time 1.1 seconds
Started Apr 23 01:09:44 PM PDT 24
Finished Apr 23 01:09:46 PM PDT 24
Peak memory 194868 kb
Host smart-1c9fe5e5-1901-4012-a303-89d96cd8da9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730274479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.730274479
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1351913677
Short name T575
Test name
Test status
Simulation time 30265339 ps
CPU time 0.54 seconds
Started Apr 23 01:10:16 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 182180 kb
Host smart-2d682370-388a-4acb-88ea-14bdd5d15eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351913677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1351913677
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1440728279
Short name T490
Test name
Test status
Simulation time 11458279 ps
CPU time 0.55 seconds
Started Apr 23 01:10:15 PM PDT 24
Finished Apr 23 01:10:16 PM PDT 24
Peak memory 181932 kb
Host smart-187053ae-6844-4529-a22a-f127c9f9c50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440728279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1440728279
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3029815639
Short name T457
Test name
Test status
Simulation time 94881165 ps
CPU time 0.57 seconds
Started Apr 23 01:10:17 PM PDT 24
Finished Apr 23 01:10:19 PM PDT 24
Peak memory 182396 kb
Host smart-e44f7d61-c775-4e18-8357-7fdb19123129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029815639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3029815639
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3434253650
Short name T508
Test name
Test status
Simulation time 16628929 ps
CPU time 0.56 seconds
Started Apr 23 01:10:17 PM PDT 24
Finished Apr 23 01:10:19 PM PDT 24
Peak memory 182544 kb
Host smart-ca71083d-61f1-4132-95c6-83cc56bc1503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434253650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3434253650
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2496392147
Short name T482
Test name
Test status
Simulation time 13460631 ps
CPU time 0.6 seconds
Started Apr 23 01:10:18 PM PDT 24
Finished Apr 23 01:10:20 PM PDT 24
Peak memory 182528 kb
Host smart-3c2777c0-04cb-48fe-989a-6e24327dff86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496392147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2496392147
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1452473964
Short name T566
Test name
Test status
Simulation time 18535377 ps
CPU time 0.59 seconds
Started Apr 23 01:10:17 PM PDT 24
Finished Apr 23 01:10:18 PM PDT 24
Peak memory 182500 kb
Host smart-fb45b2b7-81aa-481c-b30f-1b72acb5ef84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452473964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1452473964
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.826477494
Short name T558
Test name
Test status
Simulation time 102684355 ps
CPU time 0.55 seconds
Started Apr 23 01:10:16 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 182524 kb
Host smart-c247ed4d-82cb-4d6a-a036-5a940f33749d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826477494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.826477494
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2076493807
Short name T545
Test name
Test status
Simulation time 14571756 ps
CPU time 0.53 seconds
Started Apr 23 01:10:19 PM PDT 24
Finished Apr 23 01:10:20 PM PDT 24
Peak memory 181960 kb
Host smart-e46878e3-98f2-4a51-adb0-0f41c34e196f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076493807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2076493807
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4000060607
Short name T522
Test name
Test status
Simulation time 57146683 ps
CPU time 0.59 seconds
Started Apr 23 01:10:16 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 182480 kb
Host smart-14bc14f2-1d3b-4385-ac75-9d627d7d1c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000060607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4000060607
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1167201499
Short name T455
Test name
Test status
Simulation time 17666483 ps
CPU time 0.55 seconds
Started Apr 23 01:10:16 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 182380 kb
Host smart-37e822ec-caff-4f02-8592-5131ee6b6608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167201499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1167201499
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.590740817
Short name T560
Test name
Test status
Simulation time 138217243 ps
CPU time 1.01 seconds
Started Apr 23 01:09:50 PM PDT 24
Finished Apr 23 01:09:52 PM PDT 24
Peak memory 196880 kb
Host smart-8f8ef86e-fee4-42cf-b389-bd78b2e46d06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590740817 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.590740817
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.522949896
Short name T87
Test name
Test status
Simulation time 13217794 ps
CPU time 0.58 seconds
Started Apr 23 01:09:49 PM PDT 24
Finished Apr 23 01:09:50 PM PDT 24
Peak memory 182508 kb
Host smart-e418c466-fee7-4b24-91bc-b525542264bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522949896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.522949896
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3348092443
Short name T460
Test name
Test status
Simulation time 44701382 ps
CPU time 0.53 seconds
Started Apr 23 01:09:42 PM PDT 24
Finished Apr 23 01:09:43 PM PDT 24
Peak memory 181936 kb
Host smart-8a03b8e6-0db0-4a42-8be3-b684ca5a19e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348092443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3348092443
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3643299576
Short name T110
Test name
Test status
Simulation time 132130792 ps
CPU time 0.77 seconds
Started Apr 23 01:09:49 PM PDT 24
Finished Apr 23 01:09:50 PM PDT 24
Peak memory 193168 kb
Host smart-cdb06787-af23-4a25-bed9-66646bb850f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643299576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3643299576
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2610390731
Short name T542
Test name
Test status
Simulation time 102039767 ps
CPU time 1.1 seconds
Started Apr 23 01:09:45 PM PDT 24
Finished Apr 23 01:09:47 PM PDT 24
Peak memory 197020 kb
Host smart-e02c3385-08c9-4642-9412-d8a4dc3a7088
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610390731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2610390731
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1362188592
Short name T53
Test name
Test status
Simulation time 304043612 ps
CPU time 1.1 seconds
Started Apr 23 01:09:45 PM PDT 24
Finished Apr 23 01:09:46 PM PDT 24
Peak memory 183140 kb
Host smart-eb4d7c45-7b87-48a0-a780-03bd18f12685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362188592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1362188592
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.688538060
Short name T557
Test name
Test status
Simulation time 123407170 ps
CPU time 0.84 seconds
Started Apr 23 01:09:47 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 196500 kb
Host smart-023852a2-e555-4e80-a21b-219d0ac89822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688538060 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.688538060
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1042925895
Short name T578
Test name
Test status
Simulation time 41552180 ps
CPU time 0.56 seconds
Started Apr 23 01:09:49 PM PDT 24
Finished Apr 23 01:09:50 PM PDT 24
Peak memory 182580 kb
Host smart-62fbd583-02db-4d7b-b81a-e0ce6c31ac50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042925895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1042925895
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.64385659
Short name T556
Test name
Test status
Simulation time 130450294 ps
CPU time 0.53 seconds
Started Apr 23 01:09:47 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 181964 kb
Host smart-b7e9187e-5155-4470-a8c6-fc4221eb6f94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64385659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.64385659
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3089205705
Short name T547
Test name
Test status
Simulation time 18090102 ps
CPU time 0.79 seconds
Started Apr 23 01:09:48 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 193288 kb
Host smart-b9a31e91-0c81-49b5-9356-d37d67a6583e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089205705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3089205705
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2707578822
Short name T506
Test name
Test status
Simulation time 856312747 ps
CPU time 3.18 seconds
Started Apr 23 01:09:48 PM PDT 24
Finished Apr 23 01:09:52 PM PDT 24
Peak memory 197456 kb
Host smart-ba469e21-c452-4656-b007-97a86327d94b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707578822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2707578822
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1675703767
Short name T122
Test name
Test status
Simulation time 311813567 ps
CPU time 1.17 seconds
Started Apr 23 01:09:48 PM PDT 24
Finished Apr 23 01:09:50 PM PDT 24
Peak memory 194980 kb
Host smart-c806b9fc-f1aa-4dbc-b7f5-007d9ee76df4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675703767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1675703767
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2714445450
Short name T553
Test name
Test status
Simulation time 27973480 ps
CPU time 0.79 seconds
Started Apr 23 01:09:50 PM PDT 24
Finished Apr 23 01:09:51 PM PDT 24
Peak memory 195660 kb
Host smart-23a27a2e-cf8b-4ab9-bbe6-b98a36339819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714445450 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2714445450
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.949412405
Short name T526
Test name
Test status
Simulation time 26606026 ps
CPU time 0.54 seconds
Started Apr 23 01:09:46 PM PDT 24
Finished Apr 23 01:09:47 PM PDT 24
Peak memory 182396 kb
Host smart-3666f6b0-cbcf-4f2e-b268-4b838d6cd0c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949412405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.949412405
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3169485694
Short name T477
Test name
Test status
Simulation time 15653135 ps
CPU time 0.52 seconds
Started Apr 23 01:09:47 PM PDT 24
Finished Apr 23 01:09:48 PM PDT 24
Peak memory 181976 kb
Host smart-8ec5df7f-e34d-4c23-890a-67aba7acb0a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169485694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3169485694
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3940587915
Short name T567
Test name
Test status
Simulation time 25789634 ps
CPU time 0.72 seconds
Started Apr 23 01:09:48 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 193148 kb
Host smart-e097b407-71c4-4efb-a93d-48f884a393e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940587915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3940587915
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2224039157
Short name T516
Test name
Test status
Simulation time 127032947 ps
CPU time 2.33 seconds
Started Apr 23 01:09:48 PM PDT 24
Finished Apr 23 01:09:51 PM PDT 24
Peak memory 197396 kb
Host smart-1ebf4842-f732-4098-8f81-f91d2fb277e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224039157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2224039157
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.261750188
Short name T507
Test name
Test status
Simulation time 81541280 ps
CPU time 1.15 seconds
Started Apr 23 01:09:48 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 194756 kb
Host smart-cd6b68ce-5390-4b00-8caf-d5a000db69a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261750188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.261750188
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1535255357
Short name T486
Test name
Test status
Simulation time 35397398 ps
CPU time 1.52 seconds
Started Apr 23 01:09:53 PM PDT 24
Finished Apr 23 01:09:55 PM PDT 24
Peak memory 197452 kb
Host smart-9a4738b5-a3c3-44dd-9359-3b3e90b2fb17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535255357 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1535255357
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3973093832
Short name T577
Test name
Test status
Simulation time 52099239 ps
CPU time 0.6 seconds
Started Apr 23 01:09:52 PM PDT 24
Finished Apr 23 01:09:53 PM PDT 24
Peak memory 182580 kb
Host smart-018ae5f7-ead6-4949-b190-f5800c4e8feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973093832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3973093832
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2979517167
Short name T467
Test name
Test status
Simulation time 43709478 ps
CPU time 0.52 seconds
Started Apr 23 01:09:52 PM PDT 24
Finished Apr 23 01:09:53 PM PDT 24
Peak memory 182508 kb
Host smart-9a3c86de-3fe2-4fbd-b804-0d85e516cbc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979517167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2979517167
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1557713018
Short name T528
Test name
Test status
Simulation time 133324046 ps
CPU time 0.84 seconds
Started Apr 23 01:09:53 PM PDT 24
Finished Apr 23 01:09:54 PM PDT 24
Peak memory 191596 kb
Host smart-328b15ef-4816-4ca2-b7c2-9261257f5a2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557713018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1557713018
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2861553231
Short name T509
Test name
Test status
Simulation time 108660360 ps
CPU time 1.94 seconds
Started Apr 23 01:09:47 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 197424 kb
Host smart-13304980-cb06-45af-854c-f2d9bc6ce17b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861553231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2861553231
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3080882378
Short name T51
Test name
Test status
Simulation time 289939058 ps
CPU time 0.83 seconds
Started Apr 23 01:09:55 PM PDT 24
Finished Apr 23 01:09:57 PM PDT 24
Peak memory 193472 kb
Host smart-2f14e668-62b9-43b0-b63c-291493f71b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080882378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3080882378
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1712602638
Short name T549
Test name
Test status
Simulation time 82921608 ps
CPU time 1.09 seconds
Started Apr 23 01:09:54 PM PDT 24
Finished Apr 23 01:09:55 PM PDT 24
Peak memory 197372 kb
Host smart-c3f7a1ac-53c7-4328-affc-d0216b0b533a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712602638 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1712602638
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1578085930
Short name T502
Test name
Test status
Simulation time 33625939 ps
CPU time 0.55 seconds
Started Apr 23 01:09:52 PM PDT 24
Finished Apr 23 01:09:53 PM PDT 24
Peak memory 182104 kb
Host smart-3a62af7a-2723-455a-a556-663008575e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578085930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1578085930
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.273738252
Short name T473
Test name
Test status
Simulation time 43193395 ps
CPU time 0.54 seconds
Started Apr 23 01:09:53 PM PDT 24
Finished Apr 23 01:09:54 PM PDT 24
Peak memory 182396 kb
Host smart-85c438ec-9a47-4c6d-9550-7a02e6131c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273738252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.273738252
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2754792458
Short name T581
Test name
Test status
Simulation time 25496407 ps
CPU time 0.66 seconds
Started Apr 23 01:09:54 PM PDT 24
Finished Apr 23 01:09:55 PM PDT 24
Peak memory 191448 kb
Host smart-6052a2a2-ddef-41ab-b204-6af9c5301a18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754792458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2754792458
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.256616872
Short name T49
Test name
Test status
Simulation time 97704697 ps
CPU time 1.28 seconds
Started Apr 23 01:09:54 PM PDT 24
Finished Apr 23 01:09:55 PM PDT 24
Peak memory 197120 kb
Host smart-d5fdaaa9-d6aa-4d14-b372-74abef3a53e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256616872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.256616872
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3582450046
Short name T126
Test name
Test status
Simulation time 190265985 ps
CPU time 1.4 seconds
Started Apr 23 01:09:54 PM PDT 24
Finished Apr 23 01:09:56 PM PDT 24
Peak memory 183116 kb
Host smart-d0f2a642-bc34-48ee-93ea-cc09588c096a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582450046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3582450046
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3605621065
Short name T237
Test name
Test status
Simulation time 25164341926 ps
CPU time 47.25 seconds
Started Apr 23 01:13:57 PM PDT 24
Finished Apr 23 01:14:44 PM PDT 24
Peak memory 182528 kb
Host smart-a7bddd2a-47dc-4fa4-84c0-3f91a981d0ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605621065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3605621065
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.662698930
Short name T415
Test name
Test status
Simulation time 10748076642 ps
CPU time 19.94 seconds
Started Apr 23 01:13:56 PM PDT 24
Finished Apr 23 01:14:17 PM PDT 24
Peak memory 182468 kb
Host smart-45685700-419d-4673-84cc-6afcd500d26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662698930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.662698930
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2001896023
Short name T253
Test name
Test status
Simulation time 1390605963859 ps
CPU time 745.25 seconds
Started Apr 23 01:13:58 PM PDT 24
Finished Apr 23 01:26:24 PM PDT 24
Peak memory 182576 kb
Host smart-6f0e1433-2a5e-416a-8dd6-7151c0f6aac0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001896023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2001896023
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.908486581
Short name T389
Test name
Test status
Simulation time 53451980422 ps
CPU time 74.64 seconds
Started Apr 23 01:13:56 PM PDT 24
Finished Apr 23 01:15:11 PM PDT 24
Peak memory 182560 kb
Host smart-7a50fa66-a1da-4dfb-8570-98d74f9fa264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908486581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.908486581
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1703776175
Short name T312
Test name
Test status
Simulation time 12571565670 ps
CPU time 17.35 seconds
Started Apr 23 01:13:58 PM PDT 24
Finished Apr 23 01:14:15 PM PDT 24
Peak memory 182528 kb
Host smart-d65db249-78b8-481e-8e47-5d858c81af72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703776175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1703776175
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.4246037930
Short name T18
Test name
Test status
Simulation time 254650240 ps
CPU time 0.85 seconds
Started Apr 23 01:14:01 PM PDT 24
Finished Apr 23 01:14:02 PM PDT 24
Peak memory 213120 kb
Host smart-8c5e8c2c-173a-4ecd-acda-51d3bbb0acf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246037930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4246037930
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3779615364
Short name T40
Test name
Test status
Simulation time 54476056236 ps
CPU time 375.53 seconds
Started Apr 23 01:13:57 PM PDT 24
Finished Apr 23 01:20:13 PM PDT 24
Peak memory 205332 kb
Host smart-1bbd82bd-7d8b-4c68-8c71-2d440fd43a41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779615364 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3779615364
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1164376889
Short name T393
Test name
Test status
Simulation time 55974793345 ps
CPU time 82.86 seconds
Started Apr 23 01:14:13 PM PDT 24
Finished Apr 23 01:15:36 PM PDT 24
Peak memory 182496 kb
Host smart-543b17eb-315e-439a-ac90-a895ed381f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164376889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1164376889
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1207049771
Short name T199
Test name
Test status
Simulation time 248064455921 ps
CPU time 405.26 seconds
Started Apr 23 01:14:14 PM PDT 24
Finished Apr 23 01:21:00 PM PDT 24
Peak memory 192816 kb
Host smart-90c86324-2ddb-4e07-8436-9d743385d7fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207049771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1207049771
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3194243941
Short name T119
Test name
Test status
Simulation time 65439806 ps
CPU time 0.79 seconds
Started Apr 23 01:14:13 PM PDT 24
Finished Apr 23 01:14:14 PM PDT 24
Peak memory 182236 kb
Host smart-00b5d194-a0b5-4d4b-953b-da490ac58d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194243941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3194243941
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2582690761
Short name T11
Test name
Test status
Simulation time 31930328663 ps
CPU time 273.06 seconds
Started Apr 23 01:14:13 PM PDT 24
Finished Apr 23 01:18:47 PM PDT 24
Peak memory 197128 kb
Host smart-b3c0d6e0-5107-4d15-9b6c-c4ddcb58a50d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582690761 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2582690761
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.1584274537
Short name T230
Test name
Test status
Simulation time 69744217578 ps
CPU time 122.67 seconds
Started Apr 23 01:17:18 PM PDT 24
Finished Apr 23 01:19:21 PM PDT 24
Peak memory 190532 kb
Host smart-33ef97a5-40b3-45a8-a8c5-bb39a4eadddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584274537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1584274537
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3640410145
Short name T183
Test name
Test status
Simulation time 178066787627 ps
CPU time 473.18 seconds
Started Apr 23 01:17:21 PM PDT 24
Finished Apr 23 01:25:15 PM PDT 24
Peak memory 190720 kb
Host smart-5ce45af3-8579-4067-883e-ac7ba66e292c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640410145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3640410145
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2971042939
Short name T262
Test name
Test status
Simulation time 193746734941 ps
CPU time 283.92 seconds
Started Apr 23 01:17:21 PM PDT 24
Finished Apr 23 01:22:05 PM PDT 24
Peak memory 190716 kb
Host smart-c38c23f2-4ef9-45da-8ec2-8716b03b2f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971042939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2971042939
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1303616617
Short name T188
Test name
Test status
Simulation time 611075276695 ps
CPU time 390.99 seconds
Started Apr 23 01:17:19 PM PDT 24
Finished Apr 23 01:23:50 PM PDT 24
Peak memory 190704 kb
Host smart-cdf66803-d91c-407c-a7fa-dbf1b1744a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303616617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1303616617
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1992354927
Short name T244
Test name
Test status
Simulation time 96004942106 ps
CPU time 82.88 seconds
Started Apr 23 01:17:22 PM PDT 24
Finished Apr 23 01:18:46 PM PDT 24
Peak memory 190748 kb
Host smart-523faaa0-8875-4b90-9a2b-2192393710d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992354927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1992354927
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2164956702
Short name T359
Test name
Test status
Simulation time 85504480407 ps
CPU time 168.84 seconds
Started Apr 23 01:17:24 PM PDT 24
Finished Apr 23 01:20:13 PM PDT 24
Peak memory 190804 kb
Host smart-049beef0-97dd-46bb-8228-d5f9a6efa5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164956702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2164956702
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.15082720
Short name T297
Test name
Test status
Simulation time 44124616526 ps
CPU time 45.13 seconds
Started Apr 23 01:14:17 PM PDT 24
Finished Apr 23 01:15:03 PM PDT 24
Peak memory 182600 kb
Host smart-1a5244b7-7c28-4687-b693-4d00c57ba1fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15082720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.rv_timer_cfg_update_on_fly.15082720
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1119255223
Short name T429
Test name
Test status
Simulation time 748135759110 ps
CPU time 176.26 seconds
Started Apr 23 01:14:16 PM PDT 24
Finished Apr 23 01:17:13 PM PDT 24
Peak memory 182512 kb
Host smart-fb27ba7c-a43f-41cd-b4eb-a145f443dc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119255223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1119255223
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2037880852
Short name T287
Test name
Test status
Simulation time 1118650344161 ps
CPU time 794.27 seconds
Started Apr 23 01:14:20 PM PDT 24
Finished Apr 23 01:27:34 PM PDT 24
Peak memory 190708 kb
Host smart-394a4927-fedd-4e9b-91ec-5d251ed9926c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037880852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2037880852
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.2493231364
Short name T320
Test name
Test status
Simulation time 499773428814 ps
CPU time 103 seconds
Started Apr 23 01:17:23 PM PDT 24
Finished Apr 23 01:19:07 PM PDT 24
Peak memory 182556 kb
Host smart-1266371a-1fa4-4ad2-95de-df67eb6af2ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493231364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2493231364
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2119629166
Short name T71
Test name
Test status
Simulation time 34941280718 ps
CPU time 52.75 seconds
Started Apr 23 01:17:24 PM PDT 24
Finished Apr 23 01:18:17 PM PDT 24
Peak memory 182524 kb
Host smart-17ede1cb-a05e-449d-9d0c-9e84ab896814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119629166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2119629166
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2754890648
Short name T325
Test name
Test status
Simulation time 175888922339 ps
CPU time 199.98 seconds
Started Apr 23 01:17:22 PM PDT 24
Finished Apr 23 01:20:42 PM PDT 24
Peak memory 190776 kb
Host smart-ad760539-8871-4a46-ae25-917da5b01e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754890648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2754890648
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2638260292
Short name T179
Test name
Test status
Simulation time 96926356326 ps
CPU time 211.25 seconds
Started Apr 23 01:17:26 PM PDT 24
Finished Apr 23 01:20:58 PM PDT 24
Peak memory 190776 kb
Host smart-a39ae269-5411-45b0-8931-8a199734e532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638260292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2638260292
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4068161765
Short name T291
Test name
Test status
Simulation time 622685522525 ps
CPU time 528.73 seconds
Started Apr 23 01:17:31 PM PDT 24
Finished Apr 23 01:26:20 PM PDT 24
Peak memory 193576 kb
Host smart-d4d13fab-d4b8-4518-9d28-5b34fbc32bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068161765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4068161765
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3258146307
Short name T449
Test name
Test status
Simulation time 118107095609 ps
CPU time 178.42 seconds
Started Apr 23 01:14:21 PM PDT 24
Finished Apr 23 01:17:20 PM PDT 24
Peak memory 182476 kb
Host smart-0a061c65-fadf-4085-ba98-16a14c9d8ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258146307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3258146307
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1315570015
Short name T416
Test name
Test status
Simulation time 135025204824 ps
CPU time 126.16 seconds
Started Apr 23 01:14:19 PM PDT 24
Finished Apr 23 01:16:26 PM PDT 24
Peak memory 182552 kb
Host smart-f1b796eb-abdb-4423-ac3b-360aca3748de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315570015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1315570015
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3309319558
Short name T13
Test name
Test status
Simulation time 11367146083 ps
CPU time 3.76 seconds
Started Apr 23 01:14:19 PM PDT 24
Finished Apr 23 01:14:23 PM PDT 24
Peak memory 194120 kb
Host smart-432a6f05-e685-4da2-954c-aa3f9ea2b459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309319558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3309319558
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.639852165
Short name T427
Test name
Test status
Simulation time 411790771582 ps
CPU time 867.53 seconds
Started Apr 23 01:14:21 PM PDT 24
Finished Apr 23 01:28:49 PM PDT 24
Peak memory 209416 kb
Host smart-d293ac87-1c9f-418b-9ef4-a444f94b4685
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639852165 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.639852165
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1712060518
Short name T242
Test name
Test status
Simulation time 820329545680 ps
CPU time 666.51 seconds
Started Apr 23 01:17:30 PM PDT 24
Finished Apr 23 01:28:37 PM PDT 24
Peak memory 190724 kb
Host smart-e8de4b40-0222-45c7-b3be-bfeba0fa8d69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712060518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1712060518
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3718418457
Short name T338
Test name
Test status
Simulation time 93558422111 ps
CPU time 107.99 seconds
Started Apr 23 01:17:35 PM PDT 24
Finished Apr 23 01:19:24 PM PDT 24
Peak memory 190704 kb
Host smart-d4b2fc9a-8dfc-4e01-bfb7-6e9223765033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718418457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3718418457
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3092835419
Short name T445
Test name
Test status
Simulation time 117031107447 ps
CPU time 93 seconds
Started Apr 23 01:17:35 PM PDT 24
Finished Apr 23 01:19:09 PM PDT 24
Peak memory 190748 kb
Host smart-6947d04d-0693-48e2-90e5-19992f5b7fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092835419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3092835419
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1884201444
Short name T115
Test name
Test status
Simulation time 141614834579 ps
CPU time 127.19 seconds
Started Apr 23 01:17:39 PM PDT 24
Finished Apr 23 01:19:46 PM PDT 24
Peak memory 190716 kb
Host smart-c15ec33a-56ab-47ab-8dca-6104b1b9e4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884201444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1884201444
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.403368789
Short name T413
Test name
Test status
Simulation time 54982286699 ps
CPU time 106.39 seconds
Started Apr 23 01:17:37 PM PDT 24
Finished Apr 23 01:19:24 PM PDT 24
Peak memory 182524 kb
Host smart-058d030e-e909-4401-872e-60d595bcd3cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403368789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.403368789
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3387411425
Short name T140
Test name
Test status
Simulation time 615197809577 ps
CPU time 320.12 seconds
Started Apr 23 01:17:39 PM PDT 24
Finished Apr 23 01:22:59 PM PDT 24
Peak memory 190716 kb
Host smart-dc486650-cc55-4bd3-8d01-5ed1fd7444d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387411425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3387411425
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4076682310
Short name T221
Test name
Test status
Simulation time 91580399933 ps
CPU time 30.1 seconds
Started Apr 23 01:17:38 PM PDT 24
Finished Apr 23 01:18:09 PM PDT 24
Peak memory 190680 kb
Host smart-d196a368-1f54-4388-9e01-d641a321c897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076682310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4076682310
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1810530603
Short name T227
Test name
Test status
Simulation time 463377659317 ps
CPU time 257.72 seconds
Started Apr 23 01:17:42 PM PDT 24
Finished Apr 23 01:22:00 PM PDT 24
Peak memory 190704 kb
Host smart-66c13ca8-daae-425e-a679-20f8480388eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810530603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1810530603
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1473536170
Short name T419
Test name
Test status
Simulation time 407319665462 ps
CPU time 173.92 seconds
Started Apr 23 01:14:17 PM PDT 24
Finished Apr 23 01:17:12 PM PDT 24
Peak memory 182576 kb
Host smart-fbefc1e6-b8ab-47ec-8da1-9c39cb649671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473536170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1473536170
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2022627659
Short name T73
Test name
Test status
Simulation time 1413401442 ps
CPU time 2.78 seconds
Started Apr 23 01:14:21 PM PDT 24
Finished Apr 23 01:14:24 PM PDT 24
Peak memory 182228 kb
Host smart-df743a61-f76a-41b1-b326-a9c114a9ed27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022627659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2022627659
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.4076967630
Short name T74
Test name
Test status
Simulation time 313196391076 ps
CPU time 715.88 seconds
Started Apr 23 01:14:17 PM PDT 24
Finished Apr 23 01:26:14 PM PDT 24
Peak memory 190704 kb
Host smart-974e64a1-c4ff-4bbc-939d-d4e675333c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076967630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.4076967630
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3492129749
Short name T318
Test name
Test status
Simulation time 302085422373 ps
CPU time 588.88 seconds
Started Apr 23 01:17:42 PM PDT 24
Finished Apr 23 01:27:32 PM PDT 24
Peak memory 182592 kb
Host smart-efd0464e-20b9-4f3c-81d3-100770969b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492129749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3492129749
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3909761655
Short name T280
Test name
Test status
Simulation time 82066661035 ps
CPU time 157.43 seconds
Started Apr 23 01:17:41 PM PDT 24
Finished Apr 23 01:20:19 PM PDT 24
Peak memory 190732 kb
Host smart-82f3aa2a-33db-4e84-a393-277ba09cb0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909761655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3909761655
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2834905593
Short name T245
Test name
Test status
Simulation time 221419928453 ps
CPU time 97.2 seconds
Started Apr 23 01:17:42 PM PDT 24
Finished Apr 23 01:19:19 PM PDT 24
Peak memory 190720 kb
Host smart-d4d263df-1c22-4972-8149-70a8cd055fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834905593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2834905593
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2284670378
Short name T412
Test name
Test status
Simulation time 258389823584 ps
CPU time 153.68 seconds
Started Apr 23 01:17:45 PM PDT 24
Finished Apr 23 01:20:19 PM PDT 24
Peak memory 190724 kb
Host smart-36ac60b6-60d3-4917-aac3-9932ab9a4b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284670378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2284670378
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1372075582
Short name T341
Test name
Test status
Simulation time 31523889352 ps
CPU time 9.03 seconds
Started Apr 23 01:17:54 PM PDT 24
Finished Apr 23 01:18:03 PM PDT 24
Peak memory 182600 kb
Host smart-0153c699-dab5-4602-bc1c-ae17f94e0f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372075582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1372075582
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3252262602
Short name T439
Test name
Test status
Simulation time 175097359955 ps
CPU time 39.29 seconds
Started Apr 23 01:17:47 PM PDT 24
Finished Apr 23 01:18:27 PM PDT 24
Peak memory 182596 kb
Host smart-62698ea1-6fb8-4b13-98f4-bac40e17fe1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252262602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3252262602
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1544561721
Short name T367
Test name
Test status
Simulation time 172365003460 ps
CPU time 89.55 seconds
Started Apr 23 01:17:49 PM PDT 24
Finished Apr 23 01:19:19 PM PDT 24
Peak memory 182520 kb
Host smart-54f45ef8-6ca0-4443-9c80-dd76dfb68273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544561721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1544561721
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1007351939
Short name T3
Test name
Test status
Simulation time 169977460991 ps
CPU time 74.29 seconds
Started Apr 23 01:14:22 PM PDT 24
Finished Apr 23 01:15:36 PM PDT 24
Peak memory 182568 kb
Host smart-6755ccb9-a2e2-4660-9b28-3071429dc499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007351939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1007351939
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.233345902
Short name T428
Test name
Test status
Simulation time 50502503 ps
CPU time 0.6 seconds
Started Apr 23 01:14:21 PM PDT 24
Finished Apr 23 01:14:22 PM PDT 24
Peak memory 182252 kb
Host smart-0e3b364b-231b-4a2b-8091-c29ac6ec95b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233345902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.233345902
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.740591555
Short name T418
Test name
Test status
Simulation time 267913552638 ps
CPU time 427.93 seconds
Started Apr 23 01:14:20 PM PDT 24
Finished Apr 23 01:21:29 PM PDT 24
Peak memory 190688 kb
Host smart-dab974be-7986-4471-9d30-1c09f9a41f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740591555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
740591555
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.4609362
Short name T331
Test name
Test status
Simulation time 130484830022 ps
CPU time 1290 seconds
Started Apr 23 01:17:55 PM PDT 24
Finished Apr 23 01:39:26 PM PDT 24
Peak memory 190772 kb
Host smart-f42cf2e5-0cb4-4edf-85a9-f26b3e7a5c48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4609362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4609362
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1388230252
Short name T6
Test name
Test status
Simulation time 124492242855 ps
CPU time 353.05 seconds
Started Apr 23 01:17:52 PM PDT 24
Finished Apr 23 01:23:45 PM PDT 24
Peak memory 190688 kb
Host smart-cb56d197-57e9-4f6d-ae8d-ef5f70af99ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388230252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1388230252
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2564573775
Short name T323
Test name
Test status
Simulation time 344930306870 ps
CPU time 378.31 seconds
Started Apr 23 01:17:54 PM PDT 24
Finished Apr 23 01:24:12 PM PDT 24
Peak memory 190708 kb
Host smart-ab540bad-e20d-4598-92d6-cd8d801a48ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564573775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2564573775
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3368585253
Short name T225
Test name
Test status
Simulation time 69416638907 ps
CPU time 163.35 seconds
Started Apr 23 01:18:00 PM PDT 24
Finished Apr 23 01:20:44 PM PDT 24
Peak memory 190688 kb
Host smart-ed08838e-dfd6-4910-ab8b-ad097b9d0137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368585253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3368585253
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2192479541
Short name T185
Test name
Test status
Simulation time 96364452264 ps
CPU time 62.04 seconds
Started Apr 23 01:18:00 PM PDT 24
Finished Apr 23 01:19:02 PM PDT 24
Peak memory 182520 kb
Host smart-60bfd980-b84b-46fc-9b03-38ca41f7be0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192479541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2192479541
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2926629369
Short name T383
Test name
Test status
Simulation time 96111942447 ps
CPU time 154.02 seconds
Started Apr 23 01:14:21 PM PDT 24
Finished Apr 23 01:16:55 PM PDT 24
Peak memory 182536 kb
Host smart-0804558f-01ca-4d50-b1fd-e2e7ed45af3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926629369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2926629369
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2709385252
Short name T144
Test name
Test status
Simulation time 199588621448 ps
CPU time 92.2 seconds
Started Apr 23 01:14:24 PM PDT 24
Finished Apr 23 01:15:57 PM PDT 24
Peak memory 190672 kb
Host smart-fdecd4e6-5946-477c-915e-da6a8df1dc8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709385252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2709385252
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3083805334
Short name T111
Test name
Test status
Simulation time 18961068121 ps
CPU time 39.67 seconds
Started Apr 23 01:14:22 PM PDT 24
Finished Apr 23 01:15:03 PM PDT 24
Peak memory 182500 kb
Host smart-86b5dca7-672c-411b-9a2a-8859b3e74c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083805334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3083805334
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2135819442
Short name T61
Test name
Test status
Simulation time 688065732952 ps
CPU time 310.98 seconds
Started Apr 23 01:14:28 PM PDT 24
Finished Apr 23 01:19:39 PM PDT 24
Peak memory 190736 kb
Host smart-2e1d437b-2a0d-4833-b109-14265e247e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135819442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2135819442
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.577498433
Short name T46
Test name
Test status
Simulation time 590535492191 ps
CPU time 529.12 seconds
Started Apr 23 01:18:01 PM PDT 24
Finished Apr 23 01:26:50 PM PDT 24
Peak memory 194080 kb
Host smart-5a8ccd23-c33f-4472-8226-ffa52cdfa391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577498433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.577498433
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.191633427
Short name T171
Test name
Test status
Simulation time 91784652822 ps
CPU time 85.74 seconds
Started Apr 23 01:17:59 PM PDT 24
Finished Apr 23 01:19:25 PM PDT 24
Peak memory 191844 kb
Host smart-dabe4d6a-1ce5-4c99-92e8-a86b63470720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191633427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.191633427
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1099306454
Short name T114
Test name
Test status
Simulation time 65419267272 ps
CPU time 93.03 seconds
Started Apr 23 01:17:59 PM PDT 24
Finished Apr 23 01:19:32 PM PDT 24
Peak memory 190788 kb
Host smart-b0a2e846-016c-426e-8cab-8bab930c1fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099306454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1099306454
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1337863228
Short name T189
Test name
Test status
Simulation time 308201325128 ps
CPU time 1924.79 seconds
Started Apr 23 01:18:06 PM PDT 24
Finished Apr 23 01:50:12 PM PDT 24
Peak memory 190668 kb
Host smart-308cd369-d7ae-483f-b49a-a210a77eb66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337863228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1337863228
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1506894650
Short name T329
Test name
Test status
Simulation time 150794945373 ps
CPU time 608.45 seconds
Started Apr 23 01:18:02 PM PDT 24
Finished Apr 23 01:28:11 PM PDT 24
Peak memory 190680 kb
Host smart-7c2985a8-6fb4-443f-8ac0-bc4e3f5be069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506894650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1506894650
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2422469129
Short name T337
Test name
Test status
Simulation time 212041171628 ps
CPU time 252.25 seconds
Started Apr 23 01:18:03 PM PDT 24
Finished Apr 23 01:22:15 PM PDT 24
Peak memory 190656 kb
Host smart-8bbbdbb6-54bb-4fa8-a08a-773b3279e916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422469129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2422469129
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3980811663
Short name T228
Test name
Test status
Simulation time 26286039564 ps
CPU time 38.36 seconds
Started Apr 23 01:18:03 PM PDT 24
Finished Apr 23 01:18:42 PM PDT 24
Peak memory 182304 kb
Host smart-e8b6c92f-38e9-4557-8908-2e59bbc4dd0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980811663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3980811663
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.793261562
Short name T286
Test name
Test status
Simulation time 95717428579 ps
CPU time 162.15 seconds
Started Apr 23 01:18:07 PM PDT 24
Finished Apr 23 01:20:50 PM PDT 24
Peak memory 182472 kb
Host smart-39bcde7e-3851-495d-bcbd-288eddc1bb4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793261562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.793261562
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.981734406
Short name T233
Test name
Test status
Simulation time 189325641413 ps
CPU time 232.75 seconds
Started Apr 23 01:18:07 PM PDT 24
Finished Apr 23 01:22:00 PM PDT 24
Peak memory 190672 kb
Host smart-c1738309-b240-49c9-9760-5cef170c99a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981734406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.981734406
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.933634125
Short name T360
Test name
Test status
Simulation time 30261652931 ps
CPU time 50.7 seconds
Started Apr 23 01:14:25 PM PDT 24
Finished Apr 23 01:15:17 PM PDT 24
Peak memory 182524 kb
Host smart-59773836-7125-4443-8fa7-85da1545cf68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933634125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.933634125
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1351858463
Short name T385
Test name
Test status
Simulation time 12682565916 ps
CPU time 18.61 seconds
Started Apr 23 01:14:29 PM PDT 24
Finished Apr 23 01:14:48 PM PDT 24
Peak memory 182492 kb
Host smart-ee89fa3b-4245-4e94-95ab-c93c6f3ec271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351858463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1351858463
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3539302480
Short name T153
Test name
Test status
Simulation time 37567528855 ps
CPU time 64.31 seconds
Started Apr 23 01:14:26 PM PDT 24
Finished Apr 23 01:15:31 PM PDT 24
Peak memory 182524 kb
Host smart-00ad90ae-b7a7-4982-8884-d995dedd0f89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539302480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3539302480
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2872453325
Short name T271
Test name
Test status
Simulation time 9448097174 ps
CPU time 20.38 seconds
Started Apr 23 01:14:26 PM PDT 24
Finished Apr 23 01:14:47 PM PDT 24
Peak memory 190676 kb
Host smart-f6e10e96-68e0-4e50-8253-7aca8e08672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872453325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2872453325
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1757205571
Short name T417
Test name
Test status
Simulation time 65718506077 ps
CPU time 36.7 seconds
Started Apr 23 01:18:06 PM PDT 24
Finished Apr 23 01:18:43 PM PDT 24
Peak memory 182512 kb
Host smart-5b9e4d8b-d73e-45b6-9a54-60420c142285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757205571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1757205571
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3802378484
Short name T438
Test name
Test status
Simulation time 109401188997 ps
CPU time 106.17 seconds
Started Apr 23 01:18:11 PM PDT 24
Finished Apr 23 01:19:58 PM PDT 24
Peak memory 190656 kb
Host smart-3a175b13-ab07-48cd-82fb-38b10ee46aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802378484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3802378484
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2774997899
Short name T357
Test name
Test status
Simulation time 579318417587 ps
CPU time 511.39 seconds
Started Apr 23 01:18:10 PM PDT 24
Finished Apr 23 01:26:42 PM PDT 24
Peak memory 190772 kb
Host smart-3e6be5df-e365-4162-995f-291a24bfee7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774997899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2774997899
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3488513431
Short name T128
Test name
Test status
Simulation time 83096905211 ps
CPU time 88.64 seconds
Started Apr 23 01:18:12 PM PDT 24
Finished Apr 23 01:19:41 PM PDT 24
Peak memory 190760 kb
Host smart-a32d2574-df8c-415f-835f-d3821f60895b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488513431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3488513431
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3614562724
Short name T257
Test name
Test status
Simulation time 196321449306 ps
CPU time 77.79 seconds
Started Apr 23 01:18:13 PM PDT 24
Finished Apr 23 01:19:31 PM PDT 24
Peak memory 194176 kb
Host smart-ab5750f6-e338-4389-93d0-f72febd0d74b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614562724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3614562724
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3385327536
Short name T166
Test name
Test status
Simulation time 207871139444 ps
CPU time 1316.29 seconds
Started Apr 23 01:18:10 PM PDT 24
Finished Apr 23 01:40:07 PM PDT 24
Peak memory 190668 kb
Host smart-04fdc29a-0ee8-406a-acb4-46da40cfef2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385327536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3385327536
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1299120430
Short name T326
Test name
Test status
Simulation time 38132355078 ps
CPU time 398.74 seconds
Started Apr 23 01:18:11 PM PDT 24
Finished Apr 23 01:24:50 PM PDT 24
Peak memory 182484 kb
Host smart-468cf4ca-734f-446c-90b4-495ae071b315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299120430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1299120430
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2107630328
Short name T270
Test name
Test status
Simulation time 170783858333 ps
CPU time 255.73 seconds
Started Apr 23 01:18:11 PM PDT 24
Finished Apr 23 01:22:27 PM PDT 24
Peak memory 194164 kb
Host smart-7d13d201-7eb3-4580-8970-a501467ce2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107630328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2107630328
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3407287662
Short name T44
Test name
Test status
Simulation time 107621176813 ps
CPU time 151.82 seconds
Started Apr 23 01:18:11 PM PDT 24
Finished Apr 23 01:20:43 PM PDT 24
Peak memory 190712 kb
Host smart-4a8cb96c-6108-4279-8eea-2925540abaa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407287662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3407287662
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3897992998
Short name T352
Test name
Test status
Simulation time 227757451677 ps
CPU time 203.01 seconds
Started Apr 23 01:14:28 PM PDT 24
Finished Apr 23 01:17:52 PM PDT 24
Peak memory 182528 kb
Host smart-ff81773a-8073-4159-aeb5-9c2704b3884d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897992998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3897992998
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.628636155
Short name T430
Test name
Test status
Simulation time 143373366470 ps
CPU time 199.72 seconds
Started Apr 23 01:14:28 PM PDT 24
Finished Apr 23 01:17:48 PM PDT 24
Peak memory 182476 kb
Host smart-10942640-54b2-4954-ac1d-99c4495f9732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628636155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.628636155
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3557657406
Short name T1
Test name
Test status
Simulation time 86579350546 ps
CPU time 169.11 seconds
Started Apr 23 01:14:30 PM PDT 24
Finished Apr 23 01:17:19 PM PDT 24
Peak memory 190708 kb
Host smart-66267063-14b1-4c30-9469-65162ff86854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557657406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3557657406
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3971534090
Short name T282
Test name
Test status
Simulation time 71565773681 ps
CPU time 356.28 seconds
Started Apr 23 01:14:27 PM PDT 24
Finished Apr 23 01:20:23 PM PDT 24
Peak memory 182580 kb
Host smart-5f144027-d2a1-4353-b83a-126d06e795e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971534090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3971534090
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3237881332
Short name T358
Test name
Test status
Simulation time 967198342724 ps
CPU time 492.56 seconds
Started Apr 23 01:14:27 PM PDT 24
Finished Apr 23 01:22:40 PM PDT 24
Peak memory 195252 kb
Host smart-a27332ba-f700-4240-8bd1-0dca03efe8f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237881332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3237881332
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.3355496969
Short name T272
Test name
Test status
Simulation time 197309850855 ps
CPU time 345.78 seconds
Started Apr 23 01:18:10 PM PDT 24
Finished Apr 23 01:23:56 PM PDT 24
Peak memory 190660 kb
Host smart-560aac1c-78f3-4e8f-a0b9-b3a1139650e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355496969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3355496969
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3685808574
Short name T432
Test name
Test status
Simulation time 42282808096 ps
CPU time 449.98 seconds
Started Apr 23 01:18:17 PM PDT 24
Finished Apr 23 01:25:48 PM PDT 24
Peak memory 190800 kb
Host smart-3d95da81-ea7e-44a7-b6da-725407da5c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685808574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3685808574
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1152083788
Short name T197
Test name
Test status
Simulation time 491148170147 ps
CPU time 592.99 seconds
Started Apr 23 01:18:14 PM PDT 24
Finished Apr 23 01:28:08 PM PDT 24
Peak memory 190716 kb
Host smart-2f080780-a472-4cb7-a329-3a76bd4a25da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152083788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1152083788
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.159588553
Short name T345
Test name
Test status
Simulation time 195355333188 ps
CPU time 392.39 seconds
Started Apr 23 01:18:13 PM PDT 24
Finished Apr 23 01:24:46 PM PDT 24
Peak memory 190684 kb
Host smart-804e716e-a07c-4e24-95cd-52d313d11044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159588553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.159588553
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2450374589
Short name T198
Test name
Test status
Simulation time 238753473491 ps
CPU time 195.86 seconds
Started Apr 23 01:18:17 PM PDT 24
Finished Apr 23 01:21:34 PM PDT 24
Peak memory 190712 kb
Host smart-d0be3f4c-e2fd-41f2-85d3-08abb1aafdb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450374589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2450374589
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3457394830
Short name T81
Test name
Test status
Simulation time 545101012250 ps
CPU time 479.31 seconds
Started Apr 23 01:18:21 PM PDT 24
Finished Apr 23 01:26:20 PM PDT 24
Peak memory 190752 kb
Host smart-e529f322-73a8-481a-958b-3243b89ebabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457394830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3457394830
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3981832310
Short name T175
Test name
Test status
Simulation time 82727548467 ps
CPU time 1592.08 seconds
Started Apr 23 01:18:27 PM PDT 24
Finished Apr 23 01:45:00 PM PDT 24
Peak memory 190720 kb
Host smart-d24811a3-c0d9-4259-9301-0b6b1db15df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981832310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3981832310
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3692736418
Short name T387
Test name
Test status
Simulation time 401475707100 ps
CPU time 173.87 seconds
Started Apr 23 01:14:26 PM PDT 24
Finished Apr 23 01:17:21 PM PDT 24
Peak memory 182584 kb
Host smart-6e5b2257-daa3-412a-a9d7-ac28f4dbc8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692736418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3692736418
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2916089435
Short name T223
Test name
Test status
Simulation time 7272186472 ps
CPU time 18.61 seconds
Started Apr 23 01:14:25 PM PDT 24
Finished Apr 23 01:14:44 PM PDT 24
Peak memory 190712 kb
Host smart-064a636e-33dc-48e2-9d36-d1f28137f946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916089435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2916089435
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1978376253
Short name T64
Test name
Test status
Simulation time 101310114275 ps
CPU time 62.66 seconds
Started Apr 23 01:14:25 PM PDT 24
Finished Apr 23 01:15:28 PM PDT 24
Peak memory 182488 kb
Host smart-11d924f3-bdc3-49b7-949d-41824131b9f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978376253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1978376253
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.4013276159
Short name T156
Test name
Test status
Simulation time 484197881903 ps
CPU time 368.05 seconds
Started Apr 23 01:18:25 PM PDT 24
Finished Apr 23 01:24:33 PM PDT 24
Peak memory 190776 kb
Host smart-e34567d7-a1fa-4554-8636-b977d0d4a0ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013276159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.4013276159
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1244538103
Short name T154
Test name
Test status
Simulation time 67910878699 ps
CPU time 102.32 seconds
Started Apr 23 01:18:23 PM PDT 24
Finished Apr 23 01:20:06 PM PDT 24
Peak memory 190720 kb
Host smart-367b8542-9445-41f7-8f1d-c5c898dff3e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244538103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1244538103
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.877414770
Short name T278
Test name
Test status
Simulation time 198682178719 ps
CPU time 572.69 seconds
Started Apr 23 01:18:27 PM PDT 24
Finished Apr 23 01:28:00 PM PDT 24
Peak memory 190708 kb
Host smart-b0a04da9-8446-4e4d-a12b-e13c67367a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877414770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.877414770
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2737536560
Short name T256
Test name
Test status
Simulation time 143389848952 ps
CPU time 465.64 seconds
Started Apr 23 01:18:26 PM PDT 24
Finished Apr 23 01:26:12 PM PDT 24
Peak memory 190700 kb
Host smart-a76a10c9-f73f-4134-aa70-f83d0ef89ef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737536560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2737536560
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3368572266
Short name T322
Test name
Test status
Simulation time 103943246676 ps
CPU time 21.43 seconds
Started Apr 23 01:18:26 PM PDT 24
Finished Apr 23 01:18:48 PM PDT 24
Peak memory 190776 kb
Host smart-b0b58819-9413-4dc4-9931-d6432ca9dab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368572266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3368572266
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2897135918
Short name T238
Test name
Test status
Simulation time 404151681900 ps
CPU time 552.04 seconds
Started Apr 23 01:18:26 PM PDT 24
Finished Apr 23 01:27:39 PM PDT 24
Peak memory 190688 kb
Host smart-ff569090-a08f-4b9a-a3b5-fcb16b372296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897135918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2897135918
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3815855482
Short name T279
Test name
Test status
Simulation time 153324586159 ps
CPU time 255.55 seconds
Started Apr 23 01:18:30 PM PDT 24
Finished Apr 23 01:22:46 PM PDT 24
Peak memory 190788 kb
Host smart-9ad43574-59b2-49ca-b887-2446eb09ce41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815855482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3815855482
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2409421234
Short name T308
Test name
Test status
Simulation time 1762417582858 ps
CPU time 519.41 seconds
Started Apr 23 01:18:31 PM PDT 24
Finished Apr 23 01:27:11 PM PDT 24
Peak memory 190640 kb
Host smart-aaa3b745-1d9d-48de-aed5-8c8b104b5912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409421234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2409421234
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3617959402
Short name T431
Test name
Test status
Simulation time 104903897472 ps
CPU time 176.79 seconds
Started Apr 23 01:14:30 PM PDT 24
Finished Apr 23 01:17:27 PM PDT 24
Peak memory 182480 kb
Host smart-ed72a374-af71-454a-bad2-4233d177bf23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617959402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3617959402
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2015430642
Short name T382
Test name
Test status
Simulation time 388162363310 ps
CPU time 146.73 seconds
Started Apr 23 01:14:29 PM PDT 24
Finished Apr 23 01:16:56 PM PDT 24
Peak memory 182484 kb
Host smart-8c84bbde-2527-470b-9b14-1a31c3d2f4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015430642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2015430642
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2785335570
Short name T354
Test name
Test status
Simulation time 181244394368 ps
CPU time 98 seconds
Started Apr 23 01:14:28 PM PDT 24
Finished Apr 23 01:16:07 PM PDT 24
Peak memory 182612 kb
Host smart-72445446-215e-425e-bc85-bdf87cdb1b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785335570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2785335570
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1915005834
Short name T25
Test name
Test status
Simulation time 255230870 ps
CPU time 0.91 seconds
Started Apr 23 01:14:30 PM PDT 24
Finished Apr 23 01:14:32 PM PDT 24
Peak memory 182232 kb
Host smart-1a6a17c7-eac8-4930-b6f8-d184ea7660f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915005834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1915005834
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1882968320
Short name T288
Test name
Test status
Simulation time 74918000777 ps
CPU time 295.13 seconds
Started Apr 23 01:14:30 PM PDT 24
Finished Apr 23 01:19:25 PM PDT 24
Peak memory 194180 kb
Host smart-5a901d78-7721-43c1-9117-5afa58e77eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882968320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1882968320
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.40172185
Short name T129
Test name
Test status
Simulation time 76222754921 ps
CPU time 135.08 seconds
Started Apr 23 01:18:38 PM PDT 24
Finished Apr 23 01:20:53 PM PDT 24
Peak memory 193128 kb
Host smart-8c49287e-3bb8-4dc3-9c62-fe26af6b80c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40172185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.40172185
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1292396057
Short name T7
Test name
Test status
Simulation time 6968991604 ps
CPU time 10.74 seconds
Started Apr 23 01:18:34 PM PDT 24
Finished Apr 23 01:18:45 PM PDT 24
Peak memory 182516 kb
Host smart-060710a9-4654-4e10-af8f-31439784cad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292396057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1292396057
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.770802552
Short name T433
Test name
Test status
Simulation time 53521798246 ps
CPU time 670.25 seconds
Started Apr 23 01:18:37 PM PDT 24
Finished Apr 23 01:29:48 PM PDT 24
Peak memory 190712 kb
Host smart-f14f8c5d-c0ea-4465-bd51-3ea0a64118bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770802552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.770802552
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4288036707
Short name T206
Test name
Test status
Simulation time 64048687177 ps
CPU time 42.81 seconds
Started Apr 23 01:18:38 PM PDT 24
Finished Apr 23 01:19:22 PM PDT 24
Peak memory 190724 kb
Host smart-6c34c600-1165-4707-b734-831b43e286eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288036707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4288036707
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2942045519
Short name T24
Test name
Test status
Simulation time 141651060989 ps
CPU time 1967.65 seconds
Started Apr 23 01:18:40 PM PDT 24
Finished Apr 23 01:51:29 PM PDT 24
Peak memory 193032 kb
Host smart-2339cb80-e2e2-4d79-9d2a-59ede5313ab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942045519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2942045519
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3122509253
Short name T247
Test name
Test status
Simulation time 26026818905 ps
CPU time 42.65 seconds
Started Apr 23 01:14:01 PM PDT 24
Finished Apr 23 01:14:45 PM PDT 24
Peak memory 182524 kb
Host smart-560c1b46-ab02-4a31-86ad-c4f88b9246f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122509253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3122509253
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.68072353
Short name T379
Test name
Test status
Simulation time 122900072611 ps
CPU time 50.02 seconds
Started Apr 23 01:13:59 PM PDT 24
Finished Apr 23 01:14:50 PM PDT 24
Peak memory 182516 kb
Host smart-291a6106-73a3-403e-b9a9-62de1d2a7bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68072353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.68072353
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3786053694
Short name T362
Test name
Test status
Simulation time 45786420104 ps
CPU time 40.51 seconds
Started Apr 23 01:14:02 PM PDT 24
Finished Apr 23 01:14:43 PM PDT 24
Peak memory 182504 kb
Host smart-0aff664a-5935-4aad-b4d3-46cdcee3a26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786053694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3786053694
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1980099427
Short name T19
Test name
Test status
Simulation time 109414304 ps
CPU time 0.87 seconds
Started Apr 23 01:14:00 PM PDT 24
Finished Apr 23 01:14:01 PM PDT 24
Peak memory 214212 kb
Host smart-765d0dda-8bb0-4037-ad85-11af213789cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980099427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1980099427
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.987854044
Short name T374
Test name
Test status
Simulation time 385318029967 ps
CPU time 160.84 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:16:51 PM PDT 24
Peak memory 182520 kb
Host smart-22d70fff-fd87-4ac4-81cb-902a995997d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987854044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.987854044
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1943711484
Short name T390
Test name
Test status
Simulation time 427882773120 ps
CPU time 159.89 seconds
Started Apr 23 01:14:30 PM PDT 24
Finished Apr 23 01:17:10 PM PDT 24
Peak memory 182516 kb
Host smart-87eb32b0-6138-42ce-b7b5-1153f4bc9a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943711484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1943711484
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2244969858
Short name T441
Test name
Test status
Simulation time 92736023178 ps
CPU time 93.91 seconds
Started Apr 23 01:14:31 PM PDT 24
Finished Apr 23 01:16:06 PM PDT 24
Peak memory 182504 kb
Host smart-f42e4ab4-a4c2-4ffa-b144-e3c58f0c4def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244969858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2244969858
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2166825460
Short name T299
Test name
Test status
Simulation time 1620453392548 ps
CPU time 718.57 seconds
Started Apr 23 01:14:35 PM PDT 24
Finished Apr 23 01:26:34 PM PDT 24
Peak memory 182520 kb
Host smart-52d98497-2638-4c4c-b6a4-bc15730f854e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166825460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2166825460
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.777046321
Short name T78
Test name
Test status
Simulation time 106399610734 ps
CPU time 155.86 seconds
Started Apr 23 01:14:34 PM PDT 24
Finished Apr 23 01:17:11 PM PDT 24
Peak memory 182476 kb
Host smart-410b2ca6-4b2d-4b6f-9d44-87d6389c7c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777046321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.777046321
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1645761025
Short name T21
Test name
Test status
Simulation time 467894737866 ps
CPU time 685.66 seconds
Started Apr 23 01:14:29 PM PDT 24
Finished Apr 23 01:25:55 PM PDT 24
Peak memory 190724 kb
Host smart-472935af-d203-46c8-9081-1ee2f911bd05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645761025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1645761025
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3501892631
Short name T368
Test name
Test status
Simulation time 48005979047 ps
CPU time 71.06 seconds
Started Apr 23 01:14:33 PM PDT 24
Finished Apr 23 01:15:45 PM PDT 24
Peak memory 190672 kb
Host smart-bd199a55-dc28-4731-9382-c268d9756a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501892631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3501892631
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.659855768
Short name T370
Test name
Test status
Simulation time 890290044928 ps
CPU time 568.86 seconds
Started Apr 23 01:14:35 PM PDT 24
Finished Apr 23 01:24:05 PM PDT 24
Peak memory 182512 kb
Host smart-31db854f-4c37-4a63-9b71-c4309ff1a882
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659855768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.659855768
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1579585369
Short name T395
Test name
Test status
Simulation time 98803740183 ps
CPU time 81.04 seconds
Started Apr 23 01:14:35 PM PDT 24
Finished Apr 23 01:15:56 PM PDT 24
Peak memory 182488 kb
Host smart-655528be-6085-42e8-85a4-4d6de0e62d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579585369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1579585369
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3642514909
Short name T250
Test name
Test status
Simulation time 667638089633 ps
CPU time 1080.75 seconds
Started Apr 23 01:14:33 PM PDT 24
Finished Apr 23 01:32:34 PM PDT 24
Peak memory 190712 kb
Host smart-c4ddf1e3-67d0-4aa6-a53e-078606da9a12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642514909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3642514909
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1903265389
Short name T161
Test name
Test status
Simulation time 191812369151 ps
CPU time 44.1 seconds
Started Apr 23 01:14:34 PM PDT 24
Finished Apr 23 01:15:18 PM PDT 24
Peak memory 193160 kb
Host smart-ba3f6944-0c8f-47ef-99f7-1ff75fdeed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903265389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1903265389
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.758750107
Short name T410
Test name
Test status
Simulation time 786261055597 ps
CPU time 240.4 seconds
Started Apr 23 01:14:35 PM PDT 24
Finished Apr 23 01:18:36 PM PDT 24
Peak memory 182524 kb
Host smart-50bde798-1bc8-43ab-a459-d3f35b35aad4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758750107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.758750107
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3689046259
Short name T398
Test name
Test status
Simulation time 185231057039 ps
CPU time 140.91 seconds
Started Apr 23 01:14:35 PM PDT 24
Finished Apr 23 01:16:56 PM PDT 24
Peak memory 182680 kb
Host smart-1d29ffdd-fc85-4eef-94cd-e15da08616e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689046259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3689046259
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1330411176
Short name T446
Test name
Test status
Simulation time 222098925242 ps
CPU time 129.05 seconds
Started Apr 23 01:14:34 PM PDT 24
Finished Apr 23 01:16:44 PM PDT 24
Peak memory 190808 kb
Host smart-cbed4302-110a-4787-9b20-2f43d50ff8ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330411176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1330411176
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2699628675
Short name T143
Test name
Test status
Simulation time 128965107985 ps
CPU time 305.37 seconds
Started Apr 23 01:14:36 PM PDT 24
Finished Apr 23 01:19:42 PM PDT 24
Peak memory 193096 kb
Host smart-d920949b-8640-47b2-b9bd-2bf39d731db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699628675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2699628675
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2562481010
Short name T443
Test name
Test status
Simulation time 1782193807508 ps
CPU time 751.03 seconds
Started Apr 23 01:14:38 PM PDT 24
Finished Apr 23 01:27:10 PM PDT 24
Peak memory 182440 kb
Host smart-6979944f-deeb-4cad-9e63-41c36911cf5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562481010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2562481010
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.884324980
Short name T4
Test name
Test status
Simulation time 125914422643 ps
CPU time 177.94 seconds
Started Apr 23 01:14:41 PM PDT 24
Finished Apr 23 01:17:39 PM PDT 24
Peak memory 182520 kb
Host smart-41ccde22-221d-45c1-b4d1-4c43e250512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884324980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.884324980
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1478200555
Short name T146
Test name
Test status
Simulation time 556971936478 ps
CPU time 1443.36 seconds
Started Apr 23 01:14:38 PM PDT 24
Finished Apr 23 01:38:42 PM PDT 24
Peak memory 190760 kb
Host smart-e1d2a4fa-b2d6-453c-aee7-c94a55fd1281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478200555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1478200555
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.30708921
Short name T80
Test name
Test status
Simulation time 159172371681 ps
CPU time 126.61 seconds
Started Apr 23 01:14:37 PM PDT 24
Finished Apr 23 01:16:44 PM PDT 24
Peak memory 194240 kb
Host smart-295c4951-5769-44ae-b481-d65f6f9b3602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30708921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.30708921
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3274174637
Short name T95
Test name
Test status
Simulation time 686563776075 ps
CPU time 1188.33 seconds
Started Apr 23 01:14:36 PM PDT 24
Finished Apr 23 01:34:25 PM PDT 24
Peak memory 182556 kb
Host smart-959654be-c10d-4e07-b9b1-5ddabc359a2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274174637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3274174637
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1572425623
Short name T386
Test name
Test status
Simulation time 83304765580 ps
CPU time 131.8 seconds
Started Apr 23 01:14:38 PM PDT 24
Finished Apr 23 01:16:51 PM PDT 24
Peak memory 182576 kb
Host smart-1594d8a8-55f9-4c0e-9515-43827adcd186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572425623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1572425623
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1728067322
Short name T366
Test name
Test status
Simulation time 337641336561 ps
CPU time 123.93 seconds
Started Apr 23 01:14:40 PM PDT 24
Finished Apr 23 01:16:45 PM PDT 24
Peak memory 190712 kb
Host smart-f8b82f41-4870-44b6-9d90-1daf5fc29a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728067322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1728067322
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3855226888
Short name T136
Test name
Test status
Simulation time 92960456631 ps
CPU time 91.08 seconds
Started Apr 23 01:14:38 PM PDT 24
Finished Apr 23 01:16:09 PM PDT 24
Peak memory 182560 kb
Host smart-cbd6845c-12c3-43ba-8b7a-53d30c2bb5f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855226888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3855226888
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.4268237791
Short name T453
Test name
Test status
Simulation time 393193434477 ps
CPU time 176.38 seconds
Started Apr 23 01:14:36 PM PDT 24
Finished Apr 23 01:17:33 PM PDT 24
Peak memory 182448 kb
Host smart-67bf7264-da3b-47c3-9a53-872e5ec429e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268237791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.4268237791
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1935484769
Short name T85
Test name
Test status
Simulation time 15550747817 ps
CPU time 15.39 seconds
Started Apr 23 01:14:42 PM PDT 24
Finished Apr 23 01:14:57 PM PDT 24
Peak memory 190752 kb
Host smart-d9130319-002c-4950-ba6b-1fbca34a1366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935484769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1935484769
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3958145989
Short name T112
Test name
Test status
Simulation time 406576766675 ps
CPU time 165.6 seconds
Started Apr 23 01:14:40 PM PDT 24
Finished Apr 23 01:17:26 PM PDT 24
Peak memory 182480 kb
Host smart-9cbb739d-07ce-4bcf-9e39-b3f1c23f4732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958145989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3958145989
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3911960533
Short name T434
Test name
Test status
Simulation time 64953719550 ps
CPU time 47.59 seconds
Started Apr 23 01:14:42 PM PDT 24
Finished Apr 23 01:15:30 PM PDT 24
Peak memory 182476 kb
Host smart-42351066-9cf0-4726-8429-ddf6f01e376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911960533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3911960533
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1877823107
Short name T437
Test name
Test status
Simulation time 351286777738 ps
CPU time 464.99 seconds
Started Apr 23 01:14:44 PM PDT 24
Finished Apr 23 01:22:29 PM PDT 24
Peak memory 194332 kb
Host smart-16d8d9b6-d2de-4818-831b-4bc0066114af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877823107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1877823107
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3392413696
Short name T450
Test name
Test status
Simulation time 1382647459312 ps
CPU time 927.39 seconds
Started Apr 23 01:14:46 PM PDT 24
Finished Apr 23 01:30:14 PM PDT 24
Peak memory 190716 kb
Host smart-73656621-435f-4bce-b2d1-f62d77b77205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392413696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3392413696
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2324318489
Short name T200
Test name
Test status
Simulation time 722595446850 ps
CPU time 403.52 seconds
Started Apr 23 01:14:50 PM PDT 24
Finished Apr 23 01:21:34 PM PDT 24
Peak memory 182580 kb
Host smart-600e19a4-5bc4-4c74-8074-d84ce1437591
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324318489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2324318489
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.821115906
Short name T388
Test name
Test status
Simulation time 16216471302 ps
CPU time 23.66 seconds
Started Apr 23 01:14:50 PM PDT 24
Finished Apr 23 01:15:14 PM PDT 24
Peak memory 182512 kb
Host smart-da3abece-4ef1-4f33-8278-b26fb33085e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821115906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.821115906
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2207316708
Short name T321
Test name
Test status
Simulation time 101600908456 ps
CPU time 58.15 seconds
Started Apr 23 01:14:46 PM PDT 24
Finished Apr 23 01:15:44 PM PDT 24
Peak memory 182552 kb
Host smart-0c09eea5-402c-4ee0-bbb3-e84c499c1157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207316708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2207316708
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.421813986
Short name T176
Test name
Test status
Simulation time 124482654846 ps
CPU time 134.36 seconds
Started Apr 23 01:14:49 PM PDT 24
Finished Apr 23 01:17:04 PM PDT 24
Peak memory 182516 kb
Host smart-5ecb2ef7-4048-4314-bb4c-9357c442335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421813986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.421813986
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3485795860
Short name T86
Test name
Test status
Simulation time 69309702397 ps
CPU time 650.73 seconds
Started Apr 23 01:14:52 PM PDT 24
Finished Apr 23 01:25:43 PM PDT 24
Peak memory 197144 kb
Host smart-58665fe0-8b98-460a-b9f1-4ca7cf6d8332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485795860 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3485795860
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3619902935
Short name T98
Test name
Test status
Simulation time 44381469117 ps
CPU time 23.58 seconds
Started Apr 23 01:14:51 PM PDT 24
Finished Apr 23 01:15:15 PM PDT 24
Peak memory 182520 kb
Host smart-d39af30b-e82c-47ab-85ad-3a3b5533839e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619902935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3619902935
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2849851515
Short name T444
Test name
Test status
Simulation time 138067448785 ps
CPU time 58.68 seconds
Started Apr 23 01:14:49 PM PDT 24
Finished Apr 23 01:15:48 PM PDT 24
Peak memory 182512 kb
Host smart-c011d74c-dd82-4a28-948d-b95950f637fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849851515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2849851515
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3760890124
Short name T186
Test name
Test status
Simulation time 251493874773 ps
CPU time 115.05 seconds
Started Apr 23 01:14:50 PM PDT 24
Finished Apr 23 01:16:46 PM PDT 24
Peak memory 194364 kb
Host smart-59775288-1da1-462a-bb74-9a815d5d0cb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760890124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3760890124
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2914685468
Short name T283
Test name
Test status
Simulation time 85022506704 ps
CPU time 138.83 seconds
Started Apr 23 01:14:52 PM PDT 24
Finished Apr 23 01:17:11 PM PDT 24
Peak memory 190712 kb
Host smart-8a6f2993-af63-4cfc-807e-072e99e872bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914685468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2914685468
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4069830652
Short name T138
Test name
Test status
Simulation time 372075306834 ps
CPU time 589.7 seconds
Started Apr 23 01:14:03 PM PDT 24
Finished Apr 23 01:23:53 PM PDT 24
Peak memory 182540 kb
Host smart-cae2b98b-6513-41c2-98e8-4714e998214b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069830652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4069830652
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1623530715
Short name T409
Test name
Test status
Simulation time 486045625227 ps
CPU time 199.83 seconds
Started Apr 23 01:14:01 PM PDT 24
Finished Apr 23 01:17:21 PM PDT 24
Peak memory 182600 kb
Host smart-5487bdf6-1628-4e84-851f-4d850a097a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623530715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1623530715
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2996702579
Short name T425
Test name
Test status
Simulation time 21435080 ps
CPU time 0.57 seconds
Started Apr 23 01:14:02 PM PDT 24
Finished Apr 23 01:14:03 PM PDT 24
Peak memory 182300 kb
Host smart-cb28255f-70f1-4816-8b9d-fd7bf715c593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996702579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2996702579
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3558519115
Short name T20
Test name
Test status
Simulation time 131625820 ps
CPU time 0.88 seconds
Started Apr 23 01:14:05 PM PDT 24
Finished Apr 23 01:14:06 PM PDT 24
Peak memory 213668 kb
Host smart-6cbdc90d-ee4e-4be1-ae19-84393c2587f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558519115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3558519115
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.880519321
Short name T66
Test name
Test status
Simulation time 4681047764007 ps
CPU time 1506.87 seconds
Started Apr 23 01:14:03 PM PDT 24
Finished Apr 23 01:39:10 PM PDT 24
Peak memory 190700 kb
Host smart-f348944f-af3d-4dcd-b2c4-33d6d4e82705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880519321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.880519321
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2447225883
Short name T15
Test name
Test status
Simulation time 62918296223 ps
CPU time 258.9 seconds
Started Apr 23 01:14:01 PM PDT 24
Finished Apr 23 01:18:21 PM PDT 24
Peak memory 197192 kb
Host smart-0aef10fe-93b4-4482-bba3-7904c3a4c7cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447225883 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2447225883
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3427656986
Short name T452
Test name
Test status
Simulation time 45572999356 ps
CPU time 23.69 seconds
Started Apr 23 01:14:51 PM PDT 24
Finished Apr 23 01:15:15 PM PDT 24
Peak memory 182468 kb
Host smart-d262ac49-8245-4b67-92e6-ca9f6f00d359
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427656986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3427656986
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3993487832
Short name T397
Test name
Test status
Simulation time 74836028881 ps
CPU time 101.58 seconds
Started Apr 23 01:14:56 PM PDT 24
Finished Apr 23 01:16:38 PM PDT 24
Peak memory 182588 kb
Host smart-4fb32b5c-7c96-419d-b62d-bef5084cf25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993487832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3993487832
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.920429727
Short name T442
Test name
Test status
Simulation time 20929972063 ps
CPU time 702.04 seconds
Started Apr 23 01:14:54 PM PDT 24
Finished Apr 23 01:26:36 PM PDT 24
Peak memory 193244 kb
Host smart-5fc2f0ff-d625-460e-a6e4-33ea92dcbfad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920429727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.920429727
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.33509088
Short name T392
Test name
Test status
Simulation time 169502898 ps
CPU time 0.75 seconds
Started Apr 23 01:14:53 PM PDT 24
Finished Apr 23 01:14:54 PM PDT 24
Peak memory 182308 kb
Host smart-9f7a7c5d-6b17-4860-845a-d0d5a9085ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33509088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.33509088
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3547270527
Short name T204
Test name
Test status
Simulation time 531091527589 ps
CPU time 434.25 seconds
Started Apr 23 01:14:57 PM PDT 24
Finished Apr 23 01:22:11 PM PDT 24
Peak memory 182524 kb
Host smart-d7a3fd38-ed00-4f9e-a49b-ef70fb288ec4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547270527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3547270527
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.4192407437
Short name T404
Test name
Test status
Simulation time 81435589886 ps
CPU time 122.69 seconds
Started Apr 23 01:14:57 PM PDT 24
Finished Apr 23 01:17:01 PM PDT 24
Peak memory 182548 kb
Host smart-2b2f0d22-a8d0-4f26-924b-98a6c2d3f5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192407437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.4192407437
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2651481935
Short name T62
Test name
Test status
Simulation time 419835518853 ps
CPU time 1009.34 seconds
Started Apr 23 01:15:03 PM PDT 24
Finished Apr 23 01:31:52 PM PDT 24
Peak memory 190740 kb
Host smart-ae3eccd3-101e-42b0-9c84-7f2ffccee839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651481935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2651481935
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.868178441
Short name T36
Test name
Test status
Simulation time 82211532730 ps
CPU time 566.88 seconds
Started Apr 23 01:15:02 PM PDT 24
Finished Apr 23 01:24:29 PM PDT 24
Peak memory 197136 kb
Host smart-23032f6d-34c1-4682-86bc-74a1ca1af34a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868178441 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.868178441
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1237564475
Short name T315
Test name
Test status
Simulation time 95056757763 ps
CPU time 49.92 seconds
Started Apr 23 01:15:04 PM PDT 24
Finished Apr 23 01:15:55 PM PDT 24
Peak memory 182492 kb
Host smart-95a8e677-f1e0-413e-83f1-a932910a859b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237564475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1237564475
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3634195715
Short name T447
Test name
Test status
Simulation time 226923163445 ps
CPU time 100.91 seconds
Started Apr 23 01:15:02 PM PDT 24
Finished Apr 23 01:16:43 PM PDT 24
Peak memory 182600 kb
Host smart-698a20f6-1b41-4f62-af52-09227023f6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634195715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3634195715
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.910068395
Short name T300
Test name
Test status
Simulation time 176125890747 ps
CPU time 744.94 seconds
Started Apr 23 01:15:00 PM PDT 24
Finished Apr 23 01:27:26 PM PDT 24
Peak memory 190692 kb
Host smart-1e8bc738-b613-484a-965f-c56e0802322d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910068395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.910068395
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.454035708
Short name T281
Test name
Test status
Simulation time 111633185969 ps
CPU time 61.1 seconds
Started Apr 23 01:15:04 PM PDT 24
Finished Apr 23 01:16:06 PM PDT 24
Peak memory 190708 kb
Host smart-07e0d4ce-5d6c-4f6f-a738-df40a47501f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454035708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.454035708
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.94843020
Short name T12
Test name
Test status
Simulation time 2824286075045 ps
CPU time 2642.97 seconds
Started Apr 23 01:15:08 PM PDT 24
Finished Apr 23 01:59:11 PM PDT 24
Peak memory 195204 kb
Host smart-42c660c7-86e0-4d99-b0e3-816e8b2c11aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94843020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.94843020
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2161510602
Short name T224
Test name
Test status
Simulation time 26621043084 ps
CPU time 27.11 seconds
Started Apr 23 01:15:10 PM PDT 24
Finished Apr 23 01:15:37 PM PDT 24
Peak memory 182608 kb
Host smart-5086f64c-6b99-469e-b2e7-b4e0147d78f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161510602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2161510602
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1267372125
Short name T378
Test name
Test status
Simulation time 318628627126 ps
CPU time 127.2 seconds
Started Apr 23 01:15:14 PM PDT 24
Finished Apr 23 01:17:22 PM PDT 24
Peak memory 182552 kb
Host smart-4297e99a-8374-475c-a28f-0f2e3c576367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267372125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1267372125
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.256149786
Short name T28
Test name
Test status
Simulation time 51032923668 ps
CPU time 212.52 seconds
Started Apr 23 01:15:09 PM PDT 24
Finished Apr 23 01:18:42 PM PDT 24
Peak memory 182504 kb
Host smart-51ef7ed2-fa1a-4cca-8fd4-622aa196010a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256149786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.256149786
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2815975304
Short name T405
Test name
Test status
Simulation time 250606908 ps
CPU time 0.64 seconds
Started Apr 23 01:15:13 PM PDT 24
Finished Apr 23 01:15:14 PM PDT 24
Peak memory 182308 kb
Host smart-eaf5f9fa-fb5f-4c82-af81-8f550f4ff09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815975304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2815975304
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.369836404
Short name T363
Test name
Test status
Simulation time 942885509622 ps
CPU time 493.6 seconds
Started Apr 23 01:15:16 PM PDT 24
Finished Apr 23 01:23:30 PM PDT 24
Peak memory 182504 kb
Host smart-a4508b08-0055-40f7-a135-28e4ca6597a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369836404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.369836404
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1780321394
Short name T96
Test name
Test status
Simulation time 736625831245 ps
CPU time 172.1 seconds
Started Apr 23 01:15:12 PM PDT 24
Finished Apr 23 01:18:04 PM PDT 24
Peak memory 182556 kb
Host smart-e9edf244-3283-43a9-b0cf-be0fbfdfffef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780321394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1780321394
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2918240328
Short name T274
Test name
Test status
Simulation time 102861137960 ps
CPU time 98.65 seconds
Started Apr 23 01:15:11 PM PDT 24
Finished Apr 23 01:16:50 PM PDT 24
Peak memory 190800 kb
Host smart-f79f58f1-a487-4576-ac7d-da74042fd465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918240328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2918240328
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2632311474
Short name T319
Test name
Test status
Simulation time 133422845255 ps
CPU time 75.17 seconds
Started Apr 23 01:15:17 PM PDT 24
Finished Apr 23 01:16:33 PM PDT 24
Peak memory 182496 kb
Host smart-a62493c7-29d6-4a59-bce2-5a45009156d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632311474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2632311474
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3080225550
Short name T217
Test name
Test status
Simulation time 210719184047 ps
CPU time 355.06 seconds
Started Apr 23 01:15:15 PM PDT 24
Finished Apr 23 01:21:10 PM PDT 24
Peak memory 182592 kb
Host smart-12e78c66-51f2-4e5a-abb3-63d8a6e02e97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080225550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3080225550
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4085935209
Short name T147
Test name
Test status
Simulation time 200328915906 ps
CPU time 103.07 seconds
Started Apr 23 01:15:19 PM PDT 24
Finished Apr 23 01:17:03 PM PDT 24
Peak memory 182492 kb
Host smart-4a87824e-c242-43b6-8126-98306d8ce387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085935209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4085935209
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.588950907
Short name T361
Test name
Test status
Simulation time 740523490965 ps
CPU time 1044.64 seconds
Started Apr 23 01:15:20 PM PDT 24
Finished Apr 23 01:32:45 PM PDT 24
Peak memory 195508 kb
Host smart-339e3e4d-719e-4049-af75-6068e3f78e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588950907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
588950907
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.26791112
Short name T406
Test name
Test status
Simulation time 16354218088 ps
CPU time 17.13 seconds
Started Apr 23 01:15:27 PM PDT 24
Finished Apr 23 01:15:44 PM PDT 24
Peak memory 182484 kb
Host smart-ec46ce50-df28-4600-9b62-26c00b4b6ca8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26791112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.rv_timer_cfg_update_on_fly.26791112
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2421027154
Short name T45
Test name
Test status
Simulation time 278612275743 ps
CPU time 102.17 seconds
Started Apr 23 01:15:22 PM PDT 24
Finished Apr 23 01:17:05 PM PDT 24
Peak memory 182520 kb
Host smart-bfc9919e-7612-4e63-a248-8c408111edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421027154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2421027154
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2361161840
Short name T324
Test name
Test status
Simulation time 149152832724 ps
CPU time 146.38 seconds
Started Apr 23 01:15:23 PM PDT 24
Finished Apr 23 01:17:50 PM PDT 24
Peak memory 190700 kb
Host smart-e946ee66-f4e7-49ab-a2ea-275de10d8002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361161840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2361161840
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1138893714
Short name T168
Test name
Test status
Simulation time 66598669620 ps
CPU time 947.52 seconds
Started Apr 23 01:15:26 PM PDT 24
Finished Apr 23 01:31:14 PM PDT 24
Peak memory 182592 kb
Host smart-677a8a95-eb20-4597-b363-38d7724e650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138893714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1138893714
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1492375782
Short name T194
Test name
Test status
Simulation time 73918827095 ps
CPU time 128.41 seconds
Started Apr 23 01:15:30 PM PDT 24
Finished Apr 23 01:17:39 PM PDT 24
Peak memory 182528 kb
Host smart-afa5ab2d-1ce8-4613-958f-35235c41cb0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492375782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1492375782
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3563988839
Short name T448
Test name
Test status
Simulation time 157041618970 ps
CPU time 205.46 seconds
Started Apr 23 01:15:25 PM PDT 24
Finished Apr 23 01:18:51 PM PDT 24
Peak memory 182596 kb
Host smart-d8d92cf6-e081-4e1c-a066-55a25c10e86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563988839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3563988839
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3595286701
Short name T5
Test name
Test status
Simulation time 26302558416 ps
CPU time 72.46 seconds
Started Apr 23 01:15:27 PM PDT 24
Finished Apr 23 01:16:39 PM PDT 24
Peak memory 190724 kb
Host smart-4c13db0e-89e7-4164-89b3-4400e32ad92e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595286701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3595286701
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.957924667
Short name T365
Test name
Test status
Simulation time 141420349080 ps
CPU time 1056.07 seconds
Started Apr 23 01:15:30 PM PDT 24
Finished Apr 23 01:33:07 PM PDT 24
Peak memory 182552 kb
Host smart-731b3e26-5b29-4f34-b478-58de0ea21d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957924667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.957924667
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2808819114
Short name T420
Test name
Test status
Simulation time 42513884903 ps
CPU time 78.65 seconds
Started Apr 23 01:15:35 PM PDT 24
Finished Apr 23 01:16:54 PM PDT 24
Peak memory 182564 kb
Host smart-fbfdd1bd-3e19-4dbe-9088-2ec45b3b59dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808819114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2808819114
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.430287906
Short name T377
Test name
Test status
Simulation time 547000476377 ps
CPU time 70.56 seconds
Started Apr 23 01:15:33 PM PDT 24
Finished Apr 23 01:16:44 PM PDT 24
Peak memory 182492 kb
Host smart-40de2d5a-45fe-439b-8c92-7b17fc678cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430287906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.430287906
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3985664237
Short name T241
Test name
Test status
Simulation time 55788663158 ps
CPU time 176.04 seconds
Started Apr 23 01:15:38 PM PDT 24
Finished Apr 23 01:18:34 PM PDT 24
Peak memory 191732 kb
Host smart-07ca64bc-5861-41da-b217-f281c67bf46b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985664237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3985664237
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3224355903
Short name T423
Test name
Test status
Simulation time 136559637 ps
CPU time 0.74 seconds
Started Apr 23 01:15:37 PM PDT 24
Finished Apr 23 01:15:38 PM PDT 24
Peak memory 182236 kb
Host smart-f2de25ee-313f-468f-b7d3-8c48d204b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224355903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3224355903
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2338929409
Short name T304
Test name
Test status
Simulation time 332821781110 ps
CPU time 567.51 seconds
Started Apr 23 01:15:43 PM PDT 24
Finished Apr 23 01:25:11 PM PDT 24
Peak memory 182560 kb
Host smart-33d6b025-2ab8-4f86-bdb7-3a6518ca3ff0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338929409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2338929409
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2612542339
Short name T421
Test name
Test status
Simulation time 425575483279 ps
CPU time 255.93 seconds
Started Apr 23 01:15:38 PM PDT 24
Finished Apr 23 01:19:54 PM PDT 24
Peak memory 182508 kb
Host smart-dcb60bc0-0140-4bee-89f0-0ec247c67684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612542339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2612542339
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1695407391
Short name T75
Test name
Test status
Simulation time 115899800017 ps
CPU time 64.79 seconds
Started Apr 23 01:15:38 PM PDT 24
Finished Apr 23 01:16:43 PM PDT 24
Peak memory 190768 kb
Host smart-39270b31-8c88-43c6-9eae-8b36dbe8b487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695407391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1695407391
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.456926095
Short name T399
Test name
Test status
Simulation time 685073704 ps
CPU time 1.03 seconds
Started Apr 23 01:15:40 PM PDT 24
Finished Apr 23 01:15:42 PM PDT 24
Peak memory 193108 kb
Host smart-7f32424b-4069-48d8-91a1-d406169bfd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456926095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.456926095
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3953958060
Short name T332
Test name
Test status
Simulation time 718706825545 ps
CPU time 2325.13 seconds
Started Apr 23 01:15:43 PM PDT 24
Finished Apr 23 01:54:29 PM PDT 24
Peak memory 194164 kb
Host smart-c77f1f29-7db6-4d76-839f-e89b670a50cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953958060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3953958060
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.687334213
Short name T290
Test name
Test status
Simulation time 961588080361 ps
CPU time 703.15 seconds
Started Apr 23 01:14:06 PM PDT 24
Finished Apr 23 01:25:50 PM PDT 24
Peak memory 182544 kb
Host smart-4d12c416-a8a9-44be-9117-2df99f9f241b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687334213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.687334213
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3793276096
Short name T411
Test name
Test status
Simulation time 42839869406 ps
CPU time 42.13 seconds
Started Apr 23 01:14:07 PM PDT 24
Finished Apr 23 01:14:49 PM PDT 24
Peak memory 182584 kb
Host smart-85d9c1c8-14df-42b8-ba62-246c573596d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793276096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3793276096
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3117714983
Short name T335
Test name
Test status
Simulation time 48676434548 ps
CPU time 82.69 seconds
Started Apr 23 01:14:03 PM PDT 24
Finished Apr 23 01:15:27 PM PDT 24
Peak memory 190716 kb
Host smart-bf3eeabc-1efc-495e-8f92-cb0948bcde97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117714983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3117714983
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.4162839725
Short name T426
Test name
Test status
Simulation time 46056878568 ps
CPU time 87.03 seconds
Started Apr 23 01:14:06 PM PDT 24
Finished Apr 23 01:15:34 PM PDT 24
Peak memory 190796 kb
Host smart-71225b68-6bcf-4f33-b335-f50e75c8cc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162839725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4162839725
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2702188086
Short name T17
Test name
Test status
Simulation time 112585069 ps
CPU time 0.87 seconds
Started Apr 23 01:14:06 PM PDT 24
Finished Apr 23 01:14:08 PM PDT 24
Peak memory 213604 kb
Host smart-8e875aac-65fb-48a9-9f16-5c8e671e3bd5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702188086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2702188086
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3757516195
Short name T37
Test name
Test status
Simulation time 33833232689 ps
CPU time 284.11 seconds
Started Apr 23 01:14:06 PM PDT 24
Finished Apr 23 01:18:51 PM PDT 24
Peak memory 205328 kb
Host smart-4bc7b0c8-1fa2-4fa3-93bd-feb9756b10c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757516195 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3757516195
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2925504004
Short name T422
Test name
Test status
Simulation time 549097592816 ps
CPU time 186.16 seconds
Started Apr 23 01:15:41 PM PDT 24
Finished Apr 23 01:18:48 PM PDT 24
Peak memory 182504 kb
Host smart-ce7db3bc-1bd3-4b8e-9344-d77da930fed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925504004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2925504004
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2680367495
Short name T213
Test name
Test status
Simulation time 420969431285 ps
CPU time 356.1 seconds
Started Apr 23 01:15:44 PM PDT 24
Finished Apr 23 01:21:41 PM PDT 24
Peak memory 190712 kb
Host smart-82c96702-c5fe-4da5-9235-45cb520f5513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680367495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2680367495
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.171039665
Short name T294
Test name
Test status
Simulation time 53446029279 ps
CPU time 50.42 seconds
Started Apr 23 01:15:47 PM PDT 24
Finished Apr 23 01:16:38 PM PDT 24
Peak memory 182560 kb
Host smart-704bbc53-0c9e-4bd1-9337-030c8e6cb7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171039665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.171039665
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.13857080
Short name T39
Test name
Test status
Simulation time 68688710642 ps
CPU time 488.56 seconds
Started Apr 23 01:15:45 PM PDT 24
Finished Apr 23 01:23:54 PM PDT 24
Peak memory 197168 kb
Host smart-2d91acce-5183-447b-bef2-977d53f18625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13857080 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.13857080
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2120913974
Short name T187
Test name
Test status
Simulation time 1055182413536 ps
CPU time 634.33 seconds
Started Apr 23 01:15:49 PM PDT 24
Finished Apr 23 01:26:24 PM PDT 24
Peak memory 182524 kb
Host smart-db0f8d56-67de-4363-aa1e-498d8e1a2f76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120913974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2120913974
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.566972397
Short name T376
Test name
Test status
Simulation time 196079524897 ps
CPU time 82.58 seconds
Started Apr 23 01:15:50 PM PDT 24
Finished Apr 23 01:17:13 PM PDT 24
Peak memory 182504 kb
Host smart-f9be2ce2-9a4b-4d41-8af6-c535a1f3facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566972397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.566972397
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3381315691
Short name T236
Test name
Test status
Simulation time 267157238795 ps
CPU time 541.13 seconds
Started Apr 23 01:15:46 PM PDT 24
Finished Apr 23 01:24:47 PM PDT 24
Peak memory 190692 kb
Host smart-bc52a81c-a3e3-4420-88c1-dfa79432a440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381315691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3381315691
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2344668365
Short name T364
Test name
Test status
Simulation time 65784725055 ps
CPU time 35.46 seconds
Started Apr 23 01:15:49 PM PDT 24
Finished Apr 23 01:16:25 PM PDT 24
Peak memory 182580 kb
Host smart-cc993be6-962b-4bfd-8a0e-2149f1bd2017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344668365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2344668365
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.848503842
Short name T42
Test name
Test status
Simulation time 73445203615 ps
CPU time 821.86 seconds
Started Apr 23 01:15:47 PM PDT 24
Finished Apr 23 01:29:30 PM PDT 24
Peak memory 205272 kb
Host smart-e595826c-1738-4a5d-a724-f32e35d7e4d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848503842 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.848503842
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1999076065
Short name T435
Test name
Test status
Simulation time 221306558593 ps
CPU time 295.21 seconds
Started Apr 23 01:15:50 PM PDT 24
Finished Apr 23 01:20:46 PM PDT 24
Peak memory 182572 kb
Host smart-83648b9d-cd87-40f4-b262-758b11f3e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999076065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1999076065
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3381649286
Short name T118
Test name
Test status
Simulation time 150722984844 ps
CPU time 445.08 seconds
Started Apr 23 01:15:51 PM PDT 24
Finished Apr 23 01:23:16 PM PDT 24
Peak memory 190736 kb
Host smart-4e2dbc70-422f-4053-be51-7424624e4b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381649286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3381649286
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3614821186
Short name T371
Test name
Test status
Simulation time 22350618102 ps
CPU time 39.78 seconds
Started Apr 23 01:15:50 PM PDT 24
Finished Apr 23 01:16:31 PM PDT 24
Peak memory 182584 kb
Host smart-1c2cedba-a983-4aa7-b61a-43aaf730aa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614821186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3614821186
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.521552928
Short name T451
Test name
Test status
Simulation time 79799573265 ps
CPU time 157.14 seconds
Started Apr 23 01:15:50 PM PDT 24
Finished Apr 23 01:18:28 PM PDT 24
Peak memory 205424 kb
Host smart-971fe693-2a3b-4ea6-b138-7390f0149e5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521552928 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.521552928
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3938913181
Short name T220
Test name
Test status
Simulation time 223539705465 ps
CPU time 135.18 seconds
Started Apr 23 01:16:00 PM PDT 24
Finished Apr 23 01:18:16 PM PDT 24
Peak memory 182456 kb
Host smart-d5f8f8b5-e28e-4415-85d3-29c006ce7e3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938913181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3938913181
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.967984795
Short name T381
Test name
Test status
Simulation time 57503810514 ps
CPU time 88.96 seconds
Started Apr 23 01:15:57 PM PDT 24
Finished Apr 23 01:17:26 PM PDT 24
Peak memory 182552 kb
Host smart-e1ccb947-1e46-4d4a-97f1-196359ba94a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967984795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.967984795
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2978289947
Short name T263
Test name
Test status
Simulation time 336898418828 ps
CPU time 582.29 seconds
Started Apr 23 01:15:54 PM PDT 24
Finished Apr 23 01:25:37 PM PDT 24
Peak memory 190756 kb
Host smart-b2e9b72e-dfa2-4e1d-a546-02aaf4221378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978289947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2978289947
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2598871169
Short name T293
Test name
Test status
Simulation time 132381705828 ps
CPU time 64.78 seconds
Started Apr 23 01:16:01 PM PDT 24
Finished Apr 23 01:17:07 PM PDT 24
Peak memory 194300 kb
Host smart-3aeceb96-884b-48b1-8336-528619749fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598871169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2598871169
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.589347279
Short name T23
Test name
Test status
Simulation time 1267346085412 ps
CPU time 454.82 seconds
Started Apr 23 01:16:00 PM PDT 24
Finished Apr 23 01:23:36 PM PDT 24
Peak memory 195176 kb
Host smart-ae628844-0c31-4a3b-917c-066ff6fb3951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589347279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
589347279
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2287172706
Short name T120
Test name
Test status
Simulation time 171022162708 ps
CPU time 973 seconds
Started Apr 23 01:16:02 PM PDT 24
Finished Apr 23 01:32:16 PM PDT 24
Peak memory 211500 kb
Host smart-2edae379-b43a-4d84-bfa2-ff612bdc9de2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287172706 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2287172706
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2128405694
Short name T346
Test name
Test status
Simulation time 17792585869 ps
CPU time 10.85 seconds
Started Apr 23 01:16:02 PM PDT 24
Finished Apr 23 01:16:14 PM PDT 24
Peak memory 182524 kb
Host smart-87197507-a445-4dd5-a67f-6707e1c98a02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128405694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2128405694
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2257729857
Short name T68
Test name
Test status
Simulation time 217919460765 ps
CPU time 181.48 seconds
Started Apr 23 01:16:02 PM PDT 24
Finished Apr 23 01:19:04 PM PDT 24
Peak memory 182508 kb
Host smart-d061d6b1-c13a-4f62-ac35-58f3a9551989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257729857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2257729857
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1964136240
Short name T342
Test name
Test status
Simulation time 388969150272 ps
CPU time 218.71 seconds
Started Apr 23 01:16:00 PM PDT 24
Finished Apr 23 01:19:39 PM PDT 24
Peak memory 190736 kb
Host smart-0a6caa63-0162-4e3b-a02f-f3586aaa39a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964136240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1964136240
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1820946512
Short name T218
Test name
Test status
Simulation time 732007231785 ps
CPU time 664.78 seconds
Started Apr 23 01:16:09 PM PDT 24
Finished Apr 23 01:27:14 PM PDT 24
Peak memory 182484 kb
Host smart-cf1029a9-09d2-4435-afd2-6a945f798f19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820946512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1820946512
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2459745985
Short name T391
Test name
Test status
Simulation time 307507505356 ps
CPU time 99.8 seconds
Started Apr 23 01:16:05 PM PDT 24
Finished Apr 23 01:17:46 PM PDT 24
Peak memory 182476 kb
Host smart-a52cef94-8a67-4548-b9a6-81f8bcd72bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459745985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2459745985
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.400549298
Short name T229
Test name
Test status
Simulation time 164783534195 ps
CPU time 223.3 seconds
Started Apr 23 01:16:05 PM PDT 24
Finished Apr 23 01:19:48 PM PDT 24
Peak memory 182464 kb
Host smart-18c073fe-a5a7-4cb0-9430-b1080c001979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400549298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.400549298
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2263730519
Short name T349
Test name
Test status
Simulation time 56066493111 ps
CPU time 80.76 seconds
Started Apr 23 01:16:09 PM PDT 24
Finished Apr 23 01:17:30 PM PDT 24
Peak memory 190712 kb
Host smart-da81c2e1-75c7-4ddd-8194-56e4adffdd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263730519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2263730519
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2942168447
Short name T347
Test name
Test status
Simulation time 124242977904 ps
CPU time 186.22 seconds
Started Apr 23 01:16:09 PM PDT 24
Finished Apr 23 01:19:16 PM PDT 24
Peak memory 190716 kb
Host smart-831d2635-ff52-48f2-a1fc-3bfaca61b5fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942168447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2942168447
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.4055735828
Short name T259
Test name
Test status
Simulation time 15284786280 ps
CPU time 22.6 seconds
Started Apr 23 01:16:10 PM PDT 24
Finished Apr 23 01:16:33 PM PDT 24
Peak memory 182444 kb
Host smart-b1341171-4420-4928-948c-50816f6eb927
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055735828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.4055735828
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3627318490
Short name T440
Test name
Test status
Simulation time 152560313864 ps
CPU time 60.4 seconds
Started Apr 23 01:16:10 PM PDT 24
Finished Apr 23 01:17:11 PM PDT 24
Peak memory 182512 kb
Host smart-6e3bc3f8-99ec-4ef7-8aee-af75ae755033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627318490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3627318490
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3108815672
Short name T307
Test name
Test status
Simulation time 333270355088 ps
CPU time 436.18 seconds
Started Apr 23 01:16:10 PM PDT 24
Finished Apr 23 01:23:26 PM PDT 24
Peak memory 190724 kb
Host smart-c3805b32-380f-4314-9e6d-0cb148bba688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108815672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3108815672
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3986124140
Short name T181
Test name
Test status
Simulation time 173372330675 ps
CPU time 316.98 seconds
Started Apr 23 01:16:12 PM PDT 24
Finished Apr 23 01:21:29 PM PDT 24
Peak memory 190768 kb
Host smart-8ae912f7-fc5f-4eb5-b2bc-3c933e39af9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986124140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3986124140
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.709104646
Short name T402
Test name
Test status
Simulation time 49034359454 ps
CPU time 79.72 seconds
Started Apr 23 01:16:12 PM PDT 24
Finished Apr 23 01:17:32 PM PDT 24
Peak memory 194280 kb
Host smart-d65be73d-52f4-4f01-b5a6-c7202067eead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709104646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
709104646
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.3795497985
Short name T41
Test name
Test status
Simulation time 40258380175 ps
CPU time 226.93 seconds
Started Apr 23 01:16:12 PM PDT 24
Finished Apr 23 01:19:59 PM PDT 24
Peak memory 197204 kb
Host smart-ea85e7b9-63db-417d-b5dc-d6c3eb94aa5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795497985 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.3795497985
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3243342420
Short name T255
Test name
Test status
Simulation time 29435193397 ps
CPU time 14.61 seconds
Started Apr 23 01:16:16 PM PDT 24
Finished Apr 23 01:16:31 PM PDT 24
Peak memory 182608 kb
Host smart-a379f543-9d87-4680-9b3c-8198c7b9c7e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243342420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3243342420
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2548790468
Short name T400
Test name
Test status
Simulation time 604496803108 ps
CPU time 254.24 seconds
Started Apr 23 01:16:11 PM PDT 24
Finished Apr 23 01:20:25 PM PDT 24
Peak memory 182520 kb
Host smart-eaead94c-f633-450b-82c0-47136a9a9aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548790468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2548790468
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3710837352
Short name T401
Test name
Test status
Simulation time 16847043976 ps
CPU time 14.39 seconds
Started Apr 23 01:16:16 PM PDT 24
Finished Apr 23 01:16:31 PM PDT 24
Peak memory 190700 kb
Host smart-b7bfcc86-6b6b-4706-be45-3cb0005d36b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710837352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3710837352
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3943379284
Short name T101
Test name
Test status
Simulation time 35422410321 ps
CPU time 32.28 seconds
Started Apr 23 01:16:14 PM PDT 24
Finished Apr 23 01:16:47 PM PDT 24
Peak memory 182404 kb
Host smart-6cb4c3ab-d873-4a3c-9d44-720c3d99fda5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943379284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3943379284
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1049596357
Short name T436
Test name
Test status
Simulation time 20847697092 ps
CPU time 6.55 seconds
Started Apr 23 01:16:17 PM PDT 24
Finished Apr 23 01:16:24 PM PDT 24
Peak memory 182592 kb
Host smart-987ae01f-13aa-4812-8d9c-34f416bbd2b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049596357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1049596357
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.257016045
Short name T394
Test name
Test status
Simulation time 141901474760 ps
CPU time 115.02 seconds
Started Apr 23 01:16:16 PM PDT 24
Finished Apr 23 01:18:11 PM PDT 24
Peak memory 182512 kb
Host smart-ccc778ea-4328-485d-acb3-38cb37deb7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257016045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.257016045
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.391604265
Short name T82
Test name
Test status
Simulation time 46196092306 ps
CPU time 82.12 seconds
Started Apr 23 01:16:16 PM PDT 24
Finished Apr 23 01:17:38 PM PDT 24
Peak memory 182508 kb
Host smart-2e894898-612e-4f68-b18f-a9831aaa21f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391604265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.391604265
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3631352510
Short name T384
Test name
Test status
Simulation time 546530002 ps
CPU time 0.86 seconds
Started Apr 23 01:16:20 PM PDT 24
Finished Apr 23 01:16:21 PM PDT 24
Peak memory 190940 kb
Host smart-352591c4-3a70-4ce3-85cf-72edfdddec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631352510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3631352510
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2387188809
Short name T316
Test name
Test status
Simulation time 140457042710 ps
CPU time 418.78 seconds
Started Apr 23 01:16:24 PM PDT 24
Finished Apr 23 01:23:23 PM PDT 24
Peak memory 194288 kb
Host smart-a8d727ee-f765-48ca-a2d4-36a3169a5ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387188809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2387188809
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2492771652
Short name T157
Test name
Test status
Simulation time 114234259790 ps
CPU time 197.05 seconds
Started Apr 23 01:16:30 PM PDT 24
Finished Apr 23 01:19:47 PM PDT 24
Peak memory 182524 kb
Host smart-56dc9810-4827-4014-a9ca-83d8f4c1d746
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492771652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2492771652
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3060339983
Short name T396
Test name
Test status
Simulation time 233891208738 ps
CPU time 169.49 seconds
Started Apr 23 01:16:29 PM PDT 24
Finished Apr 23 01:19:19 PM PDT 24
Peak memory 182172 kb
Host smart-3768b57b-197c-44bc-8662-e48e69110ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060339983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3060339983
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.618631854
Short name T222
Test name
Test status
Simulation time 97218463042 ps
CPU time 172.8 seconds
Started Apr 23 01:16:29 PM PDT 24
Finished Apr 23 01:19:23 PM PDT 24
Peak memory 190388 kb
Host smart-3b023e97-2b87-47fd-bb75-59e2da690891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618631854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.618631854
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.606474125
Short name T269
Test name
Test status
Simulation time 27377906792 ps
CPU time 9.84 seconds
Started Apr 23 01:16:27 PM PDT 24
Finished Apr 23 01:16:38 PM PDT 24
Peak memory 194124 kb
Host smart-21de1be0-de0e-41b8-b912-d8148a211440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606474125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.606474125
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1350757208
Short name T340
Test name
Test status
Simulation time 103368201299 ps
CPU time 694.72 seconds
Started Apr 23 01:16:31 PM PDT 24
Finished Apr 23 01:28:06 PM PDT 24
Peak memory 190712 kb
Host smart-bdb347d6-bb6c-4e23-8bb4-203d9127557b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350757208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1350757208
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3720526415
Short name T313
Test name
Test status
Simulation time 256690652848 ps
CPU time 252.44 seconds
Started Apr 23 01:14:06 PM PDT 24
Finished Apr 23 01:18:19 PM PDT 24
Peak memory 182520 kb
Host smart-777eada4-2947-4948-a0ee-d3ef27a73fd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720526415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3720526415
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1713148946
Short name T403
Test name
Test status
Simulation time 61021287985 ps
CPU time 80.96 seconds
Started Apr 23 01:14:06 PM PDT 24
Finished Apr 23 01:15:27 PM PDT 24
Peak memory 182600 kb
Host smart-ad8878ae-2e36-46e9-9a2a-0c8c85328c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713148946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1713148946
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.440490677
Short name T285
Test name
Test status
Simulation time 5596538900 ps
CPU time 6.32 seconds
Started Apr 23 01:14:05 PM PDT 24
Finished Apr 23 01:14:12 PM PDT 24
Peak memory 182516 kb
Host smart-88ea9d9c-08f4-42ae-a039-bbe50546ca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440490677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.440490677
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.871119301
Short name T330
Test name
Test status
Simulation time 353670888091 ps
CPU time 189.68 seconds
Started Apr 23 01:16:32 PM PDT 24
Finished Apr 23 01:19:42 PM PDT 24
Peak memory 190768 kb
Host smart-852a0f13-7e7b-4efd-a548-cb40cc7f82e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871119301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.871119301
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1224749783
Short name T267
Test name
Test status
Simulation time 394791778672 ps
CPU time 99.49 seconds
Started Apr 23 01:16:39 PM PDT 24
Finished Apr 23 01:18:19 PM PDT 24
Peak memory 190676 kb
Host smart-d20732c1-8a97-4790-8a09-158765d02400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224749783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1224749783
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3770448244
Short name T351
Test name
Test status
Simulation time 85064159079 ps
CPU time 149.08 seconds
Started Apr 23 01:16:31 PM PDT 24
Finished Apr 23 01:19:00 PM PDT 24
Peak memory 190724 kb
Host smart-183d84e9-2fe5-468a-a51b-6f103d36a14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770448244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3770448244
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2562860305
Short name T355
Test name
Test status
Simulation time 495867527217 ps
CPU time 137.45 seconds
Started Apr 23 01:16:32 PM PDT 24
Finished Apr 23 01:18:49 PM PDT 24
Peak memory 182512 kb
Host smart-59365764-f550-4473-87db-e8f35c5bda1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562860305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2562860305
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4193296962
Short name T215
Test name
Test status
Simulation time 191386531729 ps
CPU time 217.84 seconds
Started Apr 23 01:16:35 PM PDT 24
Finished Apr 23 01:20:13 PM PDT 24
Peak memory 190744 kb
Host smart-e86007d3-b33e-4bd7-b747-a099bc1a6ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193296962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4193296962
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1441360377
Short name T249
Test name
Test status
Simulation time 41725632609 ps
CPU time 72.8 seconds
Started Apr 23 01:16:33 PM PDT 24
Finished Apr 23 01:17:46 PM PDT 24
Peak memory 182576 kb
Host smart-74550d15-7002-47bb-93d9-4fd205f97892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441360377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1441360377
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1791476750
Short name T372
Test name
Test status
Simulation time 118948193774 ps
CPU time 473.18 seconds
Started Apr 23 01:16:37 PM PDT 24
Finished Apr 23 01:24:31 PM PDT 24
Peak memory 190792 kb
Host smart-04054f37-b7ab-495a-a900-65e526e3a6a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791476750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1791476750
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1946526286
Short name T139
Test name
Test status
Simulation time 712669156956 ps
CPU time 100.89 seconds
Started Apr 23 01:16:38 PM PDT 24
Finished Apr 23 01:18:20 PM PDT 24
Peak memory 190720 kb
Host smart-12aeea88-5c6a-4419-bca1-8dbe46c81f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946526286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1946526286
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3242778454
Short name T208
Test name
Test status
Simulation time 1660109752776 ps
CPU time 866.53 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:28:36 PM PDT 24
Peak memory 182452 kb
Host smart-3924ef08-977d-4f50-a34d-f22afab990a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242778454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3242778454
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3683604671
Short name T375
Test name
Test status
Simulation time 88836091224 ps
CPU time 72.81 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:15:22 PM PDT 24
Peak memory 182448 kb
Host smart-168e8e27-458a-4645-a9ac-ada24fd2ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683604671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3683604671
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2113899642
Short name T275
Test name
Test status
Simulation time 167221211491 ps
CPU time 264.22 seconds
Started Apr 23 01:14:10 PM PDT 24
Finished Apr 23 01:18:35 PM PDT 24
Peak memory 190704 kb
Host smart-35e594c0-c03e-485a-a825-31aebd42402d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113899642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2113899642
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.594546797
Short name T407
Test name
Test status
Simulation time 10517169151 ps
CPU time 9.66 seconds
Started Apr 23 01:14:10 PM PDT 24
Finished Apr 23 01:14:20 PM PDT 24
Peak memory 182512 kb
Host smart-b691e00c-0837-4b26-9049-19234f99a818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594546797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.594546797
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.4131017932
Short name T203
Test name
Test status
Simulation time 257861992369 ps
CPU time 275.98 seconds
Started Apr 23 01:16:40 PM PDT 24
Finished Apr 23 01:21:17 PM PDT 24
Peak memory 190724 kb
Host smart-23c9947c-f270-4e0c-a0ee-0faeb290db88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131017932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.4131017932
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3113194573
Short name T135
Test name
Test status
Simulation time 174819207024 ps
CPU time 75.36 seconds
Started Apr 23 01:16:43 PM PDT 24
Finished Apr 23 01:17:58 PM PDT 24
Peak memory 190724 kb
Host smart-80f8401a-f7bd-4c2a-8357-31671cf2ccd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113194573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3113194573
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.592936776
Short name T149
Test name
Test status
Simulation time 88908545066 ps
CPU time 77.84 seconds
Started Apr 23 01:16:42 PM PDT 24
Finished Apr 23 01:18:00 PM PDT 24
Peak memory 190812 kb
Host smart-1ef8dd43-ba4e-4b6c-9e72-a02412a2a38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592936776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.592936776
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.517321173
Short name T180
Test name
Test status
Simulation time 144933696059 ps
CPU time 290.88 seconds
Started Apr 23 01:16:45 PM PDT 24
Finished Apr 23 01:21:37 PM PDT 24
Peak memory 190768 kb
Host smart-110760b3-d77d-45e8-a071-570c7e2b89b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517321173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.517321173
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3815608662
Short name T151
Test name
Test status
Simulation time 459818709777 ps
CPU time 1873.21 seconds
Started Apr 23 01:16:46 PM PDT 24
Finished Apr 23 01:48:00 PM PDT 24
Peak memory 190680 kb
Host smart-fa23db18-05e7-4342-9b19-500b440292d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815608662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3815608662
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.852793420
Short name T284
Test name
Test status
Simulation time 166535584131 ps
CPU time 314.78 seconds
Started Apr 23 01:16:45 PM PDT 24
Finished Apr 23 01:22:00 PM PDT 24
Peak memory 190724 kb
Host smart-f754d01e-3bd3-4c4b-aef9-c7cb57b694a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852793420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.852793420
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.4010074438
Short name T152
Test name
Test status
Simulation time 19752379014 ps
CPU time 38.4 seconds
Started Apr 23 01:16:50 PM PDT 24
Finished Apr 23 01:17:29 PM PDT 24
Peak memory 190712 kb
Host smart-c4bbce24-4f37-4e93-bbfd-59f6d9059665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010074438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4010074438
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3205528367
Short name T210
Test name
Test status
Simulation time 665029211436 ps
CPU time 426.32 seconds
Started Apr 23 01:16:50 PM PDT 24
Finished Apr 23 01:23:57 PM PDT 24
Peak memory 190752 kb
Host smart-a1f20d51-294f-438c-824b-64165c4277ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205528367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3205528367
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.8008052
Short name T173
Test name
Test status
Simulation time 65118089258 ps
CPU time 34.39 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:14:44 PM PDT 24
Peak memory 182604 kb
Host smart-a7aca0cd-efdd-4a07-beb2-1441777af9ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8008052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.r
v_timer_cfg_update_on_fly.8008052
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1974354517
Short name T380
Test name
Test status
Simulation time 250556145952 ps
CPU time 247.07 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:18:16 PM PDT 24
Peak memory 182568 kb
Host smart-46db7e7d-cbf7-4ad0-a74d-6b0a2128525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974354517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1974354517
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2435152186
Short name T77
Test name
Test status
Simulation time 20131749313 ps
CPU time 17.8 seconds
Started Apr 23 01:14:10 PM PDT 24
Finished Apr 23 01:14:28 PM PDT 24
Peak memory 182324 kb
Host smart-7288dd49-1f7b-47e0-a317-5a074a305619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435152186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2435152186
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1376322563
Short name T298
Test name
Test status
Simulation time 87831888703 ps
CPU time 106.88 seconds
Started Apr 23 01:14:11 PM PDT 24
Finished Apr 23 01:15:58 PM PDT 24
Peak memory 190700 kb
Host smart-3738fef0-1942-40bc-a97c-388fc9498b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376322563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1376322563
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1617714327
Short name T182
Test name
Test status
Simulation time 75045909775 ps
CPU time 156.09 seconds
Started Apr 23 01:14:11 PM PDT 24
Finished Apr 23 01:16:47 PM PDT 24
Peak memory 182600 kb
Host smart-e3876223-8449-40cb-835d-57724f4f6ac1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617714327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1617714327
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.4027114619
Short name T121
Test name
Test status
Simulation time 202931559304 ps
CPU time 1715.56 seconds
Started Apr 23 01:14:11 PM PDT 24
Finished Apr 23 01:42:48 PM PDT 24
Peak memory 213560 kb
Host smart-fea03ff8-e496-4f2c-bd0a-91da98e2316c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027114619 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.4027114619
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.959867193
Short name T234
Test name
Test status
Simulation time 240110007609 ps
CPU time 182.47 seconds
Started Apr 23 01:16:50 PM PDT 24
Finished Apr 23 01:19:53 PM PDT 24
Peak memory 190764 kb
Host smart-0e327b7d-a1a0-4eab-90a9-3c7460e7d35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959867193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.959867193
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1672773081
Short name T214
Test name
Test status
Simulation time 555241718867 ps
CPU time 1687.27 seconds
Started Apr 23 01:16:52 PM PDT 24
Finished Apr 23 01:45:00 PM PDT 24
Peak memory 190676 kb
Host smart-5bba009f-bad9-45ea-a69c-909a346ded4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672773081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1672773081
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3354298687
Short name T83
Test name
Test status
Simulation time 572123117736 ps
CPU time 307.32 seconds
Started Apr 23 01:16:53 PM PDT 24
Finished Apr 23 01:22:00 PM PDT 24
Peak memory 190748 kb
Host smart-9505f8eb-3ec6-47af-9b4e-6850fafa7c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354298687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3354298687
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1428350067
Short name T265
Test name
Test status
Simulation time 249547661709 ps
CPU time 938.46 seconds
Started Apr 23 01:16:56 PM PDT 24
Finished Apr 23 01:32:35 PM PDT 24
Peak memory 190796 kb
Host smart-b28f8d43-5698-44eb-b833-477b8ed86e41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428350067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1428350067
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2768877081
Short name T328
Test name
Test status
Simulation time 344961195984 ps
CPU time 731.58 seconds
Started Apr 23 01:16:57 PM PDT 24
Finished Apr 23 01:29:09 PM PDT 24
Peak memory 190716 kb
Host smart-474c9723-0b89-447a-8379-ce92f3e68626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768877081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2768877081
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3427382508
Short name T408
Test name
Test status
Simulation time 33357360277 ps
CPU time 56.89 seconds
Started Apr 23 01:16:57 PM PDT 24
Finished Apr 23 01:17:54 PM PDT 24
Peak memory 190724 kb
Host smart-e2f59897-2036-4031-a003-4822349eb698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427382508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3427382508
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.695478447
Short name T424
Test name
Test status
Simulation time 70528834353 ps
CPU time 113.48 seconds
Started Apr 23 01:16:59 PM PDT 24
Finished Apr 23 01:18:53 PM PDT 24
Peak memory 190704 kb
Host smart-2c81b040-3205-4222-b32c-3a83185e19ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695478447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.695478447
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1296455686
Short name T356
Test name
Test status
Simulation time 42611069681 ps
CPU time 80.72 seconds
Started Apr 23 01:16:58 PM PDT 24
Finished Apr 23 01:18:19 PM PDT 24
Peak memory 190712 kb
Host smart-b0dd162d-be71-44b0-8f0d-25bec6b4d72b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296455686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1296455686
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.757224269
Short name T344
Test name
Test status
Simulation time 93657020543 ps
CPU time 89.2 seconds
Started Apr 23 01:17:10 PM PDT 24
Finished Apr 23 01:18:39 PM PDT 24
Peak memory 182328 kb
Host smart-1f2541b0-eef6-4960-8a67-0ba98dd2cfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757224269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.757224269
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1553979956
Short name T207
Test name
Test status
Simulation time 1215452191001 ps
CPU time 397.33 seconds
Started Apr 23 01:17:10 PM PDT 24
Finished Apr 23 01:23:47 PM PDT 24
Peak memory 192768 kb
Host smart-692732ca-488b-41bc-8433-be867e064ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553979956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1553979956
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1086854164
Short name T301
Test name
Test status
Simulation time 1629408786665 ps
CPU time 471.8 seconds
Started Apr 23 01:14:12 PM PDT 24
Finished Apr 23 01:22:05 PM PDT 24
Peak memory 182512 kb
Host smart-1191f865-3bed-4356-86ec-f969d1a49403
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086854164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1086854164
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.327164672
Short name T414
Test name
Test status
Simulation time 115343119462 ps
CPU time 63.89 seconds
Started Apr 23 01:14:08 PM PDT 24
Finished Apr 23 01:15:12 PM PDT 24
Peak memory 182516 kb
Host smart-9b77705b-2149-425b-9217-ed0bbb08140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327164672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.327164672
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.326970857
Short name T2
Test name
Test status
Simulation time 444919208591 ps
CPU time 276.95 seconds
Started Apr 23 01:14:12 PM PDT 24
Finished Apr 23 01:18:49 PM PDT 24
Peak memory 190708 kb
Host smart-c5afcd6a-266d-4cb7-a379-733d4f059c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326970857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.326970857
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2816346260
Short name T302
Test name
Test status
Simulation time 335579210189 ps
CPU time 152.68 seconds
Started Apr 23 01:14:18 PM PDT 24
Finished Apr 23 01:16:51 PM PDT 24
Peak memory 190780 kb
Host smart-7bf9d446-c0b7-480d-8d9b-094e9e37e1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816346260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2816346260
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.361203577
Short name T339
Test name
Test status
Simulation time 648538163749 ps
CPU time 1980.63 seconds
Started Apr 23 01:17:05 PM PDT 24
Finished Apr 23 01:50:07 PM PDT 24
Peak memory 190792 kb
Host smart-20b9189d-26dc-42d7-876f-08b194e91aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361203577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.361203577
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2155315364
Short name T369
Test name
Test status
Simulation time 33247020942 ps
CPU time 39.9 seconds
Started Apr 23 01:17:06 PM PDT 24
Finished Apr 23 01:17:47 PM PDT 24
Peak memory 182512 kb
Host smart-fe8ce5c9-340f-44cd-95bf-3931fa28506f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155315364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2155315364
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1730028883
Short name T97
Test name
Test status
Simulation time 145483099666 ps
CPU time 144.01 seconds
Started Apr 23 01:17:04 PM PDT 24
Finished Apr 23 01:19:29 PM PDT 24
Peak memory 190752 kb
Host smart-2c4338c0-d72e-4216-89a0-352ad8c625cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730028883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1730028883
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2049205033
Short name T113
Test name
Test status
Simulation time 89722239661 ps
CPU time 63 seconds
Started Apr 23 01:17:10 PM PDT 24
Finished Apr 23 01:18:13 PM PDT 24
Peak memory 182516 kb
Host smart-58b97333-fa07-49c4-af8c-5fa2449a9a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049205033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2049205033
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2708821181
Short name T343
Test name
Test status
Simulation time 195721431940 ps
CPU time 193.49 seconds
Started Apr 23 01:17:04 PM PDT 24
Finished Apr 23 01:20:18 PM PDT 24
Peak memory 190764 kb
Host smart-c14737bb-2599-4175-95e5-5110c20d8f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708821181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2708821181
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4096309156
Short name T167
Test name
Test status
Simulation time 59605898336 ps
CPU time 108.16 seconds
Started Apr 23 01:17:03 PM PDT 24
Finished Apr 23 01:18:52 PM PDT 24
Peak memory 190800 kb
Host smart-4f33539b-f5e9-4d82-b59a-b89ea791ce7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096309156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4096309156
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.290788475
Short name T196
Test name
Test status
Simulation time 498542210912 ps
CPU time 255.92 seconds
Started Apr 23 01:17:07 PM PDT 24
Finished Apr 23 01:21:24 PM PDT 24
Peak memory 190708 kb
Host smart-1386dd0b-7e25-4902-b2cc-b7982518f71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290788475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.290788475
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2052792113
Short name T348
Test name
Test status
Simulation time 459626785841 ps
CPU time 337.8 seconds
Started Apr 23 01:17:06 PM PDT 24
Finished Apr 23 01:22:45 PM PDT 24
Peak memory 190812 kb
Host smart-ebf38363-c9d9-4b1a-b373-e460262fd30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052792113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2052792113
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1340472614
Short name T142
Test name
Test status
Simulation time 311614268796 ps
CPU time 118.74 seconds
Started Apr 23 01:17:06 PM PDT 24
Finished Apr 23 01:19:05 PM PDT 24
Peak memory 190728 kb
Host smart-b89a1075-d5ab-4c54-b99c-0070ab59eefc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340472614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1340472614
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2155031289
Short name T289
Test name
Test status
Simulation time 611673325869 ps
CPU time 1003.02 seconds
Started Apr 23 01:14:13 PM PDT 24
Finished Apr 23 01:30:56 PM PDT 24
Peak memory 182592 kb
Host smart-b111a1cb-af5c-43e1-a281-b42ba520f6cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155031289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2155031289
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1150980556
Short name T22
Test name
Test status
Simulation time 353611068392 ps
CPU time 143.35 seconds
Started Apr 23 01:14:13 PM PDT 24
Finished Apr 23 01:16:37 PM PDT 24
Peak memory 182468 kb
Host smart-930a6baf-2b88-4e27-b38e-f05379de8be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150980556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1150980556
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3668336368
Short name T47
Test name
Test status
Simulation time 307776955702 ps
CPU time 158.78 seconds
Started Apr 23 01:14:15 PM PDT 24
Finished Apr 23 01:16:54 PM PDT 24
Peak memory 190712 kb
Host smart-61a0f83c-8f56-47e7-9f79-f6880edf9e52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668336368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3668336368
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.893038226
Short name T350
Test name
Test status
Simulation time 247242607197 ps
CPU time 529.18 seconds
Started Apr 23 01:14:15 PM PDT 24
Finished Apr 23 01:23:05 PM PDT 24
Peak memory 190764 kb
Host smart-9a0f5d94-c48b-4eee-b52e-ef4104159742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893038226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.893038226
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3287391761
Short name T94
Test name
Test status
Simulation time 23827473774 ps
CPU time 208.29 seconds
Started Apr 23 01:14:14 PM PDT 24
Finished Apr 23 01:17:43 PM PDT 24
Peak memory 197084 kb
Host smart-d3ba6d4e-a6bc-4164-82dd-90a898c0b5fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287391761 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.3287391761
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.3656952008
Short name T353
Test name
Test status
Simulation time 199535615360 ps
CPU time 168.86 seconds
Started Apr 23 01:17:16 PM PDT 24
Finished Apr 23 01:20:05 PM PDT 24
Peak memory 192288 kb
Host smart-2b21acaf-3b55-47b1-8f0f-444cca60a9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656952008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3656952008
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2863296103
Short name T69
Test name
Test status
Simulation time 104461342107 ps
CPU time 323.71 seconds
Started Apr 23 01:17:16 PM PDT 24
Finished Apr 23 01:22:40 PM PDT 24
Peak memory 190804 kb
Host smart-8c4a2959-709c-4b24-8870-a93721b34924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863296103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2863296103
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1883692746
Short name T295
Test name
Test status
Simulation time 26229884350 ps
CPU time 13.56 seconds
Started Apr 23 01:17:16 PM PDT 24
Finished Apr 23 01:17:30 PM PDT 24
Peak memory 182508 kb
Host smart-869a8311-27ba-4a45-a748-fa5910256a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883692746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1883692746
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2735042810
Short name T303
Test name
Test status
Simulation time 186629089127 ps
CPU time 202.87 seconds
Started Apr 23 01:17:16 PM PDT 24
Finished Apr 23 01:20:39 PM PDT 24
Peak memory 190716 kb
Host smart-869a4f23-7acd-4e0b-b4bd-2cf86e56eb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735042810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2735042810
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2026159254
Short name T454
Test name
Test status
Simulation time 96088613789 ps
CPU time 160.58 seconds
Started Apr 23 01:17:15 PM PDT 24
Finished Apr 23 01:19:56 PM PDT 24
Peak memory 190728 kb
Host smart-8f498c26-df12-41d9-ace5-3dc6a3e9610f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026159254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2026159254
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2533881465
Short name T99
Test name
Test status
Simulation time 13069498151 ps
CPU time 13.67 seconds
Started Apr 23 01:17:17 PM PDT 24
Finished Apr 23 01:17:31 PM PDT 24
Peak memory 182520 kb
Host smart-5cfc0bf0-787d-469e-9d0b-0790ca3392af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533881465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2533881465
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1008698852
Short name T373
Test name
Test status
Simulation time 64235946721 ps
CPU time 536.2 seconds
Started Apr 23 01:17:15 PM PDT 24
Finished Apr 23 01:26:12 PM PDT 24
Peak memory 182520 kb
Host smart-2f0ddaad-38b2-4601-bcbf-72c3868a8b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008698852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1008698852
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.671788491
Short name T191
Test name
Test status
Simulation time 313677972909 ps
CPU time 144.9 seconds
Started Apr 23 01:17:18 PM PDT 24
Finished Apr 23 01:19:43 PM PDT 24
Peak memory 190568 kb
Host smart-0146c87a-c3b9-4f26-aad6-948e0c8cbbf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671788491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.671788491
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1281969452
Short name T162
Test name
Test status
Simulation time 43719693977 ps
CPU time 76.15 seconds
Started Apr 23 01:17:17 PM PDT 24
Finished Apr 23 01:18:34 PM PDT 24
Peak memory 190728 kb
Host smart-3039d66c-0c31-4ba0-b5dc-f47763dcf08c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281969452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1281969452
Directory /workspace/99.rv_timer_random/latest
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