Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.36 98.73 100.00 100.00 100.00 99.89


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.723279849 Apr 25 12:21:28 PM PDT 24 Apr 25 12:21:31 PM PDT 24 29310390 ps
T508 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3543663827 Apr 25 12:21:35 PM PDT 24 Apr 25 12:21:37 PM PDT 24 58681186 ps
T509 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.461632116 Apr 25 12:21:28 PM PDT 24 Apr 25 12:21:31 PM PDT 24 357246204 ps
T510 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.997919917 Apr 25 12:21:06 PM PDT 24 Apr 25 12:21:07 PM PDT 24 13872249 ps
T511 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3601916746 Apr 25 12:21:01 PM PDT 24 Apr 25 12:21:03 PM PDT 24 10991412 ps
T512 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.945985339 Apr 25 12:21:49 PM PDT 24 Apr 25 12:21:51 PM PDT 24 49090657 ps
T513 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1926920477 Apr 25 12:21:40 PM PDT 24 Apr 25 12:21:44 PM PDT 24 187777564 ps
T514 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3919104340 Apr 25 12:21:41 PM PDT 24 Apr 25 12:21:43 PM PDT 24 21930658 ps
T515 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2324065382 Apr 25 12:21:04 PM PDT 24 Apr 25 12:21:06 PM PDT 24 13583172 ps
T516 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2147257732 Apr 25 12:19:18 PM PDT 24 Apr 25 12:19:19 PM PDT 24 72496337 ps
T517 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1832813003 Apr 25 12:21:22 PM PDT 24 Apr 25 12:21:24 PM PDT 24 28253085 ps
T518 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.599269478 Apr 25 12:21:11 PM PDT 24 Apr 25 12:21:15 PM PDT 24 123093908 ps
T519 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3900132320 Apr 25 12:21:03 PM PDT 24 Apr 25 12:21:05 PM PDT 24 11178860 ps
T520 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1046191619 Apr 25 12:21:05 PM PDT 24 Apr 25 12:21:07 PM PDT 24 59959590 ps
T521 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3363943798 Apr 25 12:22:03 PM PDT 24 Apr 25 12:22:05 PM PDT 24 39519617 ps
T522 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2760165967 Apr 25 12:22:01 PM PDT 24 Apr 25 12:22:03 PM PDT 24 665956221 ps
T89 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3888400349 Apr 25 12:21:00 PM PDT 24 Apr 25 12:21:02 PM PDT 24 39933944 ps
T523 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.863264492 Apr 25 12:17:40 PM PDT 24 Apr 25 12:17:42 PM PDT 24 195374452 ps
T524 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1411186725 Apr 25 12:19:38 PM PDT 24 Apr 25 12:19:39 PM PDT 24 11371340 ps
T525 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1892583216 Apr 25 12:21:56 PM PDT 24 Apr 25 12:22:00 PM PDT 24 55691664 ps
T526 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2846713028 Apr 25 12:21:39 PM PDT 24 Apr 25 12:21:41 PM PDT 24 81945618 ps
T90 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.239147511 Apr 25 12:21:27 PM PDT 24 Apr 25 12:21:29 PM PDT 24 24039330 ps
T527 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3729775974 Apr 25 12:21:55 PM PDT 24 Apr 25 12:21:59 PM PDT 24 400545130 ps
T528 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3685557717 Apr 25 12:21:27 PM PDT 24 Apr 25 12:21:29 PM PDT 24 15837636 ps
T529 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3250731213 Apr 25 12:21:06 PM PDT 24 Apr 25 12:21:08 PM PDT 24 41541077 ps
T530 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1209464031 Apr 25 12:21:02 PM PDT 24 Apr 25 12:21:04 PM PDT 24 40982009 ps
T531 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3807065797 Apr 25 12:21:59 PM PDT 24 Apr 25 12:22:01 PM PDT 24 125131473 ps
T532 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.978954308 Apr 25 12:21:49 PM PDT 24 Apr 25 12:21:51 PM PDT 24 46069919 ps
T533 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2601697727 Apr 25 12:17:10 PM PDT 24 Apr 25 12:17:12 PM PDT 24 75752955 ps
T534 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2306371665 Apr 25 12:21:53 PM PDT 24 Apr 25 12:21:55 PM PDT 24 351523069 ps
T535 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.708253860 Apr 25 12:21:28 PM PDT 24 Apr 25 12:21:30 PM PDT 24 325786658 ps
T536 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.573998689 Apr 25 12:22:02 PM PDT 24 Apr 25 12:22:04 PM PDT 24 285350513 ps
T537 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.659301060 Apr 25 12:21:05 PM PDT 24 Apr 25 12:21:07 PM PDT 24 21447294 ps
T538 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1694647567 Apr 25 12:21:04 PM PDT 24 Apr 25 12:21:05 PM PDT 24 18479371 ps
T539 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4131659436 Apr 25 12:21:49 PM PDT 24 Apr 25 12:21:51 PM PDT 24 65390261 ps
T540 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3960979415 Apr 25 12:21:03 PM PDT 24 Apr 25 12:21:06 PM PDT 24 191231776 ps
T541 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3493927917 Apr 25 12:21:34 PM PDT 24 Apr 25 12:21:37 PM PDT 24 26030030 ps
T542 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3233968899 Apr 25 12:21:41 PM PDT 24 Apr 25 12:21:43 PM PDT 24 70119064 ps
T543 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3455425120 Apr 25 12:17:00 PM PDT 24 Apr 25 12:17:02 PM PDT 24 35674418 ps
T544 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1209685372 Apr 25 12:21:40 PM PDT 24 Apr 25 12:21:43 PM PDT 24 97326236 ps
T545 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.557634731 Apr 25 12:21:49 PM PDT 24 Apr 25 12:21:51 PM PDT 24 37531447 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1458464483 Apr 25 12:21:41 PM PDT 24 Apr 25 12:21:43 PM PDT 24 96746096 ps
T102 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4251824545 Apr 25 12:21:04 PM PDT 24 Apr 25 12:21:06 PM PDT 24 354572278 ps
T547 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1040329094 Apr 25 12:21:12 PM PDT 24 Apr 25 12:21:15 PM PDT 24 127386850 ps
T548 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.411207130 Apr 25 12:21:03 PM PDT 24 Apr 25 12:21:06 PM PDT 24 70005754 ps
T549 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3924028048 Apr 25 12:21:09 PM PDT 24 Apr 25 12:21:11 PM PDT 24 89202858 ps
T550 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3628796052 Apr 25 12:21:05 PM PDT 24 Apr 25 12:21:08 PM PDT 24 24364170 ps
T551 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3963571085 Apr 25 12:21:39 PM PDT 24 Apr 25 12:21:41 PM PDT 24 104714072 ps
T552 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1093846787 Apr 25 12:17:13 PM PDT 24 Apr 25 12:17:14 PM PDT 24 74702113 ps
T91 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2554763513 Apr 25 12:21:25 PM PDT 24 Apr 25 12:21:26 PM PDT 24 46327811 ps
T553 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3236528268 Apr 25 12:21:27 PM PDT 24 Apr 25 12:21:29 PM PDT 24 64775866 ps
T554 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2361484360 Apr 25 12:18:00 PM PDT 24 Apr 25 12:18:02 PM PDT 24 17108025 ps
T555 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1125521801 Apr 25 12:17:17 PM PDT 24 Apr 25 12:17:19 PM PDT 24 14890576 ps
T556 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4120954035 Apr 25 12:20:41 PM PDT 24 Apr 25 12:20:43 PM PDT 24 289996529 ps
T557 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.355758053 Apr 25 12:21:16 PM PDT 24 Apr 25 12:21:18 PM PDT 24 33078598 ps
T558 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2179841340 Apr 25 12:16:50 PM PDT 24 Apr 25 12:16:52 PM PDT 24 14155688 ps
T559 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1875654320 Apr 25 12:21:08 PM PDT 24 Apr 25 12:21:10 PM PDT 24 21668734 ps
T560 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4274415701 Apr 25 12:22:10 PM PDT 24 Apr 25 12:22:12 PM PDT 24 35188778 ps
T92 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.660259300 Apr 25 12:21:03 PM PDT 24 Apr 25 12:21:05 PM PDT 24 13778991 ps
T561 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.427679020 Apr 25 12:21:27 PM PDT 24 Apr 25 12:21:29 PM PDT 24 17229131 ps
T562 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2341809211 Apr 25 12:21:12 PM PDT 24 Apr 25 12:21:16 PM PDT 24 29195660 ps
T563 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.109928494 Apr 25 12:21:25 PM PDT 24 Apr 25 12:21:27 PM PDT 24 67489797 ps
T564 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3672709509 Apr 25 12:21:29 PM PDT 24 Apr 25 12:21:31 PM PDT 24 42024344 ps
T565 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.400897457 Apr 25 12:21:55 PM PDT 24 Apr 25 12:21:57 PM PDT 24 44584003 ps
T566 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2338708026 Apr 25 12:18:36 PM PDT 24 Apr 25 12:18:37 PM PDT 24 98639342 ps
T567 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.445684555 Apr 25 12:18:44 PM PDT 24 Apr 25 12:18:46 PM PDT 24 69591484 ps
T568 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1229234666 Apr 25 12:21:08 PM PDT 24 Apr 25 12:21:11 PM PDT 24 324954611 ps
T569 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4191017953 Apr 25 12:21:48 PM PDT 24 Apr 25 12:21:50 PM PDT 24 137204989 ps
T570 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.818870484 Apr 25 12:22:12 PM PDT 24 Apr 25 12:22:14 PM PDT 24 27584341 ps
T571 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.956917255 Apr 25 12:21:56 PM PDT 24 Apr 25 12:21:58 PM PDT 24 17242812 ps
T572 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1545111766 Apr 25 12:19:06 PM PDT 24 Apr 25 12:19:08 PM PDT 24 14727310 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2263300472 Apr 25 12:21:54 PM PDT 24 Apr 25 12:21:56 PM PDT 24 20917814 ps
T574 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2516223944 Apr 25 12:21:25 PM PDT 24 Apr 25 12:21:26 PM PDT 24 104580143 ps
T575 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4033741862 Apr 25 12:21:00 PM PDT 24 Apr 25 12:21:01 PM PDT 24 14098033 ps
T576 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4010906233 Apr 25 12:21:35 PM PDT 24 Apr 25 12:21:37 PM PDT 24 163217155 ps
T577 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4267003082 Apr 25 12:21:50 PM PDT 24 Apr 25 12:21:53 PM PDT 24 36717827 ps
T93 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1889389947 Apr 25 12:21:29 PM PDT 24 Apr 25 12:21:31 PM PDT 24 21113456 ps
T578 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3606376754 Apr 25 12:23:04 PM PDT 24 Apr 25 12:23:05 PM PDT 24 56493715 ps
T579 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.173335526 Apr 25 12:17:52 PM PDT 24 Apr 25 12:17:53 PM PDT 24 16368860 ps
T580 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3056573290 Apr 25 12:20:35 PM PDT 24 Apr 25 12:20:36 PM PDT 24 106939979 ps

Test location /workspace/coverage/default/28.rv_timer_random.3029632717
Short name T9
Test name
Test status
Simulation time 138422670253 ps
CPU time 235.89 seconds
Started Apr 25 12:24:21 PM PDT 24
Finished Apr 25 12:28:18 PM PDT 24
Peak memory 194460 kb
Host smart-f0249b09-ae79-4c97-a4b2-e99d1b3928d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029632717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3029632717
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1299727003
Short name T12
Test name
Test status
Simulation time 36450737175 ps
CPU time 121.07 seconds
Started Apr 25 12:24:02 PM PDT 24
Finished Apr 25 12:26:04 PM PDT 24
Peak memory 197456 kb
Host smart-a4081ce2-812e-4a6f-8c0a-19d43652c246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299727003 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1299727003
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1691688394
Short name T48
Test name
Test status
Simulation time 665936301018 ps
CPU time 1747.85 seconds
Started Apr 25 12:24:45 PM PDT 24
Finished Apr 25 12:53:55 PM PDT 24
Peak memory 191008 kb
Host smart-cf56c83b-5756-404b-a89d-eaa53ffc7b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691688394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1691688394
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3854273971
Short name T234
Test name
Test status
Simulation time 1822781702467 ps
CPU time 2276.34 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 01:02:26 PM PDT 24
Peak memory 191004 kb
Host smart-9ea74a34-fa40-46d6-9a2a-a980e585ff86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854273971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3854273971
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1950426387
Short name T54
Test name
Test status
Simulation time 28762347 ps
CPU time 0.57 seconds
Started Apr 25 12:21:08 PM PDT 24
Finished Apr 25 12:21:10 PM PDT 24
Peak memory 181044 kb
Host smart-5b110a20-5057-4a08-b26d-94fc34690434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950426387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1950426387
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1446731619
Short name T47
Test name
Test status
Simulation time 4336024051048 ps
CPU time 2252.67 seconds
Started Apr 25 12:24:41 PM PDT 24
Finished Apr 25 01:02:15 PM PDT 24
Peak memory 191032 kb
Host smart-cbacf9e8-df36-4724-85a0-7be7799adce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446731619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1446731619
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2934709219
Short name T58
Test name
Test status
Simulation time 486041021 ps
CPU time 1.44 seconds
Started Apr 25 12:21:27 PM PDT 24
Finished Apr 25 12:21:30 PM PDT 24
Peak memory 193928 kb
Host smart-7cfea149-cd88-48e7-9381-ce852798340b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934709219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2934709219
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2376688524
Short name T76
Test name
Test status
Simulation time 1924862208745 ps
CPU time 3882.63 seconds
Started Apr 25 12:24:02 PM PDT 24
Finished Apr 25 01:28:45 PM PDT 24
Peak memory 190976 kb
Host smart-2c3fb2a4-1f19-4b75-9478-1df9166a81a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376688524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2376688524
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2895685400
Short name T237
Test name
Test status
Simulation time 398287323951 ps
CPU time 1123.72 seconds
Started Apr 25 12:24:54 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 191032 kb
Host smart-be61d98f-194b-40f7-990f-ff260ae3a037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895685400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2895685400
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3961507107
Short name T195
Test name
Test status
Simulation time 2580615495159 ps
CPU time 1056.2 seconds
Started Apr 25 12:24:30 PM PDT 24
Finished Apr 25 12:42:07 PM PDT 24
Peak memory 190988 kb
Host smart-3e0300b5-0ccb-49c8-9dd5-39b2485ecff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961507107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3961507107
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.2454776130
Short name T112
Test name
Test status
Simulation time 254353015944 ps
CPU time 328.54 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:30:25 PM PDT 24
Peak memory 190980 kb
Host smart-5b48f5c7-e6b1-46b0-be27-a6291ae181c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454776130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2454776130
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1432963137
Short name T18
Test name
Test status
Simulation time 88064741 ps
CPU time 0.9 seconds
Started Apr 25 12:24:14 PM PDT 24
Finished Apr 25 12:24:16 PM PDT 24
Peak memory 214332 kb
Host smart-262ae565-d0d6-42ab-ab14-706750ab49e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432963137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1432963137
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1635769609
Short name T69
Test name
Test status
Simulation time 1262903514898 ps
CPU time 577.63 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:34:07 PM PDT 24
Peak memory 195944 kb
Host smart-6ce5643a-56be-426b-ac13-18ba7bfe84a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635769609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1635769609
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1851773840
Short name T190
Test name
Test status
Simulation time 528434686200 ps
CPU time 1818 seconds
Started Apr 25 12:24:15 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 190936 kb
Host smart-29c96350-8304-478c-a7f6-d86de9e24b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851773840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1851773840
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/72.rv_timer_random.1798346760
Short name T8
Test name
Test status
Simulation time 118912680804 ps
CPU time 361.7 seconds
Started Apr 25 12:25:08 PM PDT 24
Finished Apr 25 12:31:11 PM PDT 24
Peak memory 191132 kb
Host smart-58df7690-4aa4-4c96-9a62-8c3dd057065d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798346760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1798346760
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2398761813
Short name T270
Test name
Test status
Simulation time 590910711459 ps
CPU time 1122.27 seconds
Started Apr 25 12:23:51 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 190936 kb
Host smart-52647eb3-a044-4fc0-927d-d173d938d88b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398761813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2398761813
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/135.rv_timer_random.2866944074
Short name T169
Test name
Test status
Simulation time 302326975514 ps
CPU time 422.63 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:31:56 PM PDT 24
Peak memory 191004 kb
Host smart-65ca5551-39f7-4ce1-89b2-dbbda95f114b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866944074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2866944074
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.742109313
Short name T147
Test name
Test status
Simulation time 1546156439312 ps
CPU time 509.73 seconds
Started Apr 25 12:24:23 PM PDT 24
Finished Apr 25 12:32:54 PM PDT 24
Peak memory 191000 kb
Host smart-8672e55a-3a31-433d-acff-65f2643f3e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742109313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
742109313
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2602487871
Short name T74
Test name
Test status
Simulation time 1762364862885 ps
CPU time 999.82 seconds
Started Apr 25 12:24:03 PM PDT 24
Finished Apr 25 12:40:44 PM PDT 24
Peak memory 191028 kb
Host smart-872500ec-9ed3-4162-a95e-f30831defd27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602487871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2602487871
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.3722456423
Short name T248
Test name
Test status
Simulation time 423871031604 ps
CPU time 1268.94 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:45:34 PM PDT 24
Peak memory 190988 kb
Host smart-0f5dbc27-4df8-4cd1-ab71-b97b5f6d2a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722456423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3722456423
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3443733251
Short name T49
Test name
Test status
Simulation time 525677037222 ps
CPU time 934.14 seconds
Started Apr 25 12:24:32 PM PDT 24
Finished Apr 25 12:40:06 PM PDT 24
Peak memory 182808 kb
Host smart-de5ef404-b886-4397-8e75-ab52f6046954
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443733251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3443733251
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/148.rv_timer_random.3800667695
Short name T220
Test name
Test status
Simulation time 787603118606 ps
CPU time 2901.72 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 01:13:17 PM PDT 24
Peak memory 190992 kb
Host smart-27668446-39d3-4b02-9f2f-87f21c0287b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800667695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3800667695
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1595068146
Short name T149
Test name
Test status
Simulation time 2460390555443 ps
CPU time 2164.93 seconds
Started Apr 25 12:23:58 PM PDT 24
Finished Apr 25 01:00:04 PM PDT 24
Peak memory 191004 kb
Host smart-0a516470-935d-444b-bece-9911be44cab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595068146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1595068146
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/56.rv_timer_random.2450758117
Short name T3
Test name
Test status
Simulation time 103321493539 ps
CPU time 178.6 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:27:36 PM PDT 24
Peak memory 190988 kb
Host smart-01771bc8-9b83-424c-9257-01fbdfe64ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450758117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2450758117
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3290417764
Short name T62
Test name
Test status
Simulation time 86191080677 ps
CPU time 285.57 seconds
Started Apr 25 12:25:03 PM PDT 24
Finished Apr 25 12:29:50 PM PDT 24
Peak memory 190972 kb
Host smart-0f2c1dbd-737e-42ee-b4d8-a10a3fea30ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290417764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3290417764
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3865231307
Short name T339
Test name
Test status
Simulation time 321148353177 ps
CPU time 1491.28 seconds
Started Apr 25 12:24:42 PM PDT 24
Finished Apr 25 12:49:34 PM PDT 24
Peak memory 195432 kb
Host smart-794a39fb-5c40-409f-a31e-c20415869324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865231307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3865231307
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.3307638019
Short name T260
Test name
Test status
Simulation time 57688773538 ps
CPU time 98.21 seconds
Started Apr 25 12:24:02 PM PDT 24
Finished Apr 25 12:25:41 PM PDT 24
Peak memory 190924 kb
Host smart-5106712f-1397-4d59-9cdc-07b494d0c421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307638019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3307638019
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.473352249
Short name T268
Test name
Test status
Simulation time 284199775304 ps
CPU time 721.99 seconds
Started Apr 25 12:25:01 PM PDT 24
Finished Apr 25 12:37:04 PM PDT 24
Peak memory 193348 kb
Host smart-ae39d5f6-94b2-421f-9aa2-30ea92bdf158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473352249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.473352249
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.3652508506
Short name T180
Test name
Test status
Simulation time 755147272195 ps
CPU time 380.27 seconds
Started Apr 25 12:24:05 PM PDT 24
Finished Apr 25 12:30:26 PM PDT 24
Peak memory 191000 kb
Host smart-9f4588d3-0d93-414e-85e8-9450ae77d086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652508506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3652508506
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3456702627
Short name T350
Test name
Test status
Simulation time 1596993909589 ps
CPU time 296.4 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:29:49 PM PDT 24
Peak memory 191028 kb
Host smart-2a383872-055a-474c-acda-4db9e120abaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456702627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3456702627
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3955606810
Short name T295
Test name
Test status
Simulation time 174939245062 ps
CPU time 288.85 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:29:41 PM PDT 24
Peak memory 194932 kb
Host smart-43744dcd-ac49-4897-af03-a6e734e0c6c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955606810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3955606810
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.194014760
Short name T318
Test name
Test status
Simulation time 444216122026 ps
CPU time 605.63 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:34:51 PM PDT 24
Peak memory 191100 kb
Host smart-640f8239-a07f-4220-aee9-793f3e4b9367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194014760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
194014760
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.1405355091
Short name T283
Test name
Test status
Simulation time 1938426829763 ps
CPU time 815.57 seconds
Started Apr 25 12:24:41 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 191004 kb
Host smart-ce341574-7375-4946-9437-004be776437b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405355091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1405355091
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random.429369816
Short name T233
Test name
Test status
Simulation time 286386210145 ps
CPU time 488.57 seconds
Started Apr 25 12:24:39 PM PDT 24
Finished Apr 25 12:32:49 PM PDT 24
Peak memory 190992 kb
Host smart-6aa692d5-1886-4943-85ec-b6d8b66355e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429369816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.429369816
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2219696856
Short name T297
Test name
Test status
Simulation time 6426769393476 ps
CPU time 1526.92 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 182816 kb
Host smart-608a0f3e-9239-4dea-b702-1d05dcf2712b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219696856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2219696856
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/156.rv_timer_random.4185599217
Short name T151
Test name
Test status
Simulation time 342347156603 ps
CPU time 808.61 seconds
Started Apr 25 12:24:54 PM PDT 24
Finished Apr 25 12:38:25 PM PDT 24
Peak memory 190928 kb
Host smart-4b2ab37b-3ef3-41eb-93ad-176000d5c61d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185599217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.4185599217
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2919288811
Short name T211
Test name
Test status
Simulation time 1697081115721 ps
CPU time 1473.42 seconds
Started Apr 25 12:24:26 PM PDT 24
Finished Apr 25 12:49:01 PM PDT 24
Peak memory 190976 kb
Host smart-ecceca75-03ef-4b7a-9c57-b8eb22d0bd14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919288811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2919288811
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_random.2976392018
Short name T108
Test name
Test status
Simulation time 139156692403 ps
CPU time 728.86 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:36:54 PM PDT 24
Peak memory 190984 kb
Host smart-defa23da-ee14-4d01-bec4-5cd2028867e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976392018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2976392018
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1776877071
Short name T327
Test name
Test status
Simulation time 234804188207 ps
CPU time 642.86 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:35:33 PM PDT 24
Peak memory 190968 kb
Host smart-28fe3b6b-af45-4ec6-8ea5-6296b39fa85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776877071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1776877071
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2865652292
Short name T170
Test name
Test status
Simulation time 4856026834320 ps
CPU time 2657.02 seconds
Started Apr 25 12:24:14 PM PDT 24
Finished Apr 25 01:08:32 PM PDT 24
Peak memory 190932 kb
Host smart-b0f04d28-d0d9-4395-b82e-2ace2abc13f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865652292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2865652292
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/119.rv_timer_random.1736089073
Short name T111
Test name
Test status
Simulation time 146457192950 ps
CPU time 402.32 seconds
Started Apr 25 12:25:02 PM PDT 24
Finished Apr 25 12:31:45 PM PDT 24
Peak memory 191000 kb
Host smart-10530ef8-cbb9-4fc6-b82d-83a261985ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736089073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1736089073
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1243605172
Short name T287
Test name
Test status
Simulation time 491988198874 ps
CPU time 843.26 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:38:53 PM PDT 24
Peak memory 191004 kb
Host smart-9b5875f6-7b02-436c-93ed-bd814d929456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243605172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1243605172
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3618183747
Short name T224
Test name
Test status
Simulation time 2291225395440 ps
CPU time 674.01 seconds
Started Apr 25 12:24:16 PM PDT 24
Finished Apr 25 12:35:31 PM PDT 24
Peak memory 182736 kb
Host smart-adb5c842-5acc-4e72-bf29-e4ee9418751e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618183747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3618183747
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random.383592873
Short name T176
Test name
Test status
Simulation time 173064328846 ps
CPU time 533.7 seconds
Started Apr 25 12:24:30 PM PDT 24
Finished Apr 25 12:33:25 PM PDT 24
Peak memory 190992 kb
Host smart-3a0d3774-491c-4c60-9b72-41fd8fe66125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383592873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.383592873
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.674983231
Short name T179
Test name
Test status
Simulation time 1203201927105 ps
CPU time 959.43 seconds
Started Apr 25 12:24:29 PM PDT 24
Finished Apr 25 12:40:30 PM PDT 24
Peak memory 190968 kb
Host smart-1390099b-d2e0-49f8-bbae-c50b409a0bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674983231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
674983231
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.2340310511
Short name T109
Test name
Test status
Simulation time 84642701906 ps
CPU time 388.07 seconds
Started Apr 25 12:25:07 PM PDT 24
Finished Apr 25 12:31:36 PM PDT 24
Peak memory 190964 kb
Host smart-6194fc93-5d9e-43b5-9bb7-f2efa89a087e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340310511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2340310511
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.474528803
Short name T184
Test name
Test status
Simulation time 231637898259 ps
CPU time 225.14 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:28:15 PM PDT 24
Peak memory 182800 kb
Host smart-84a09d3a-63fb-4d6d-8029-c86beb506f88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474528803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.474528803
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/118.rv_timer_random.887697366
Short name T174
Test name
Test status
Simulation time 1068659118593 ps
CPU time 883.23 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:39:32 PM PDT 24
Peak memory 190996 kb
Host smart-007c7ca0-ce0e-4f52-8e72-db06d5549e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887697366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.887697366
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.339314602
Short name T154
Test name
Test status
Simulation time 2228141264765 ps
CPU time 2517.51 seconds
Started Apr 25 12:23:56 PM PDT 24
Finished Apr 25 01:05:54 PM PDT 24
Peak memory 195648 kb
Host smart-7da72c99-d6c5-4f1d-be7e-bcc6e52b36df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339314602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
339314602
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2822743944
Short name T11
Test name
Test status
Simulation time 246449474069 ps
CPU time 733.18 seconds
Started Apr 25 12:24:12 PM PDT 24
Finished Apr 25 12:36:27 PM PDT 24
Peak memory 191004 kb
Host smart-7f171bcf-c206-480c-a76b-8894d8697784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822743944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2822743944
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_random.151374454
Short name T164
Test name
Test status
Simulation time 200779645788 ps
CPU time 160.64 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:27:06 PM PDT 24
Peak memory 190988 kb
Host smart-0cfe0f3d-1d04-43c7-b92b-f4bfa15ccfe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151374454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.151374454
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2930092848
Short name T73
Test name
Test status
Simulation time 1587674082905 ps
CPU time 1159.47 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 195460 kb
Host smart-29fb18f9-cad2-414c-ba16-0438ce3634e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930092848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2930092848
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.2950358906
Short name T243
Test name
Test status
Simulation time 255337470815 ps
CPU time 181.08 seconds
Started Apr 25 12:23:55 PM PDT 24
Finished Apr 25 12:26:59 PM PDT 24
Peak memory 194324 kb
Host smart-8d29ac38-469b-4a11-be6c-8e9d8e614ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950358906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2950358906
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1158486706
Short name T217
Test name
Test status
Simulation time 806342354615 ps
CPU time 460.72 seconds
Started Apr 25 12:24:58 PM PDT 24
Finished Apr 25 12:32:41 PM PDT 24
Peak memory 192056 kb
Host smart-dbb7cd20-4d27-47fc-b19d-ff00223e2901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158486706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1158486706
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2554763513
Short name T91
Test name
Test status
Simulation time 46327811 ps
CPU time 0.78 seconds
Started Apr 25 12:21:25 PM PDT 24
Finished Apr 25 12:21:26 PM PDT 24
Peak memory 192412 kb
Host smart-02f77b53-ec46-413a-9ffd-cd35a94a1bf0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554763513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2554763513
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1095350926
Short name T52
Test name
Test status
Simulation time 39216743 ps
CPU time 0.62 seconds
Started Apr 25 12:22:35 PM PDT 24
Finished Apr 25 12:22:36 PM PDT 24
Peak memory 191572 kb
Host smart-7304ead2-5c09-4c32-923f-8876259f4378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095350926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1095350926
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_random.2443375366
Short name T242
Test name
Test status
Simulation time 82480232387 ps
CPU time 223.98 seconds
Started Apr 25 12:24:16 PM PDT 24
Finished Apr 25 12:28:01 PM PDT 24
Peak memory 191004 kb
Host smart-6d7fd674-334e-474b-88a7-ebde25d79b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443375366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2443375366
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.767532999
Short name T173
Test name
Test status
Simulation time 175514533504 ps
CPU time 397.23 seconds
Started Apr 25 12:24:45 PM PDT 24
Finished Apr 25 12:31:24 PM PDT 24
Peak memory 191008 kb
Host smart-fd2cebee-2338-49fe-be83-add63339d0b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767532999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.767532999
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.1572165904
Short name T196
Test name
Test status
Simulation time 722470737818 ps
CPU time 1527.55 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:50:16 PM PDT 24
Peak memory 191000 kb
Host smart-38ec368d-7133-404b-b473-65a25ae617e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572165904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1572165904
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.401434956
Short name T311
Test name
Test status
Simulation time 1100615694260 ps
CPU time 555.8 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:33:41 PM PDT 24
Peak memory 182816 kb
Host smart-a5469b47-92ab-4ec6-9c04-851ca9a49578
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401434956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.401434956
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.76821083
Short name T313
Test name
Test status
Simulation time 119564369712 ps
CPU time 107.47 seconds
Started Apr 25 12:23:52 PM PDT 24
Finished Apr 25 12:25:41 PM PDT 24
Peak memory 193732 kb
Host smart-fb5b6d69-dd31-45e1-bc84-fd77f2bf34a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76821083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.76821083
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/152.rv_timer_random.3203025255
Short name T231
Test name
Test status
Simulation time 84016779410 ps
CPU time 73.62 seconds
Started Apr 25 12:25:02 PM PDT 24
Finished Apr 25 12:26:16 PM PDT 24
Peak memory 191000 kb
Host smart-e5cffaf9-21c9-4c64-964b-bbd5077a7a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203025255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3203025255
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3943417245
Short name T175
Test name
Test status
Simulation time 130942087289 ps
CPU time 2713.29 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 01:09:58 PM PDT 24
Peak memory 190952 kb
Host smart-4e3a44b3-db8a-43c0-9c85-2883099f5add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943417245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3943417245
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.518238316
Short name T114
Test name
Test status
Simulation time 416703367494 ps
CPU time 1249.94 seconds
Started Apr 25 12:25:12 PM PDT 24
Finished Apr 25 12:46:03 PM PDT 24
Peak memory 191012 kb
Host smart-15289eca-27aa-47e5-a276-eb5e9065b4ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518238316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.518238316
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3535800817
Short name T182
Test name
Test status
Simulation time 134758807908 ps
CPU time 122.68 seconds
Started Apr 25 12:25:05 PM PDT 24
Finished Apr 25 12:27:08 PM PDT 24
Peak memory 191020 kb
Host smart-bf1469a2-2632-4898-9e3a-a80327b6da75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535800817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3535800817
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.4150587939
Short name T119
Test name
Test status
Simulation time 75168624757 ps
CPU time 289.94 seconds
Started Apr 25 12:24:42 PM PDT 24
Finished Apr 25 12:29:34 PM PDT 24
Peak memory 182808 kb
Host smart-b568c229-8b58-4661-a5e0-e972cdf7563d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150587939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4150587939
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.701816700
Short name T338
Test name
Test status
Simulation time 351456238335 ps
CPU time 694.97 seconds
Started Apr 25 12:25:10 PM PDT 24
Finished Apr 25 12:36:46 PM PDT 24
Peak memory 194332 kb
Host smart-75322f80-1eb5-464a-a8e7-edb787c65074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701816700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.701816700
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2347931133
Short name T255
Test name
Test status
Simulation time 173165137403 ps
CPU time 438.82 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:32:14 PM PDT 24
Peak memory 193732 kb
Host smart-7cf4e133-141a-4966-80ae-197ed07595e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347931133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2347931133
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1090398782
Short name T70
Test name
Test status
Simulation time 1430543374815 ps
CPU time 1359.92 seconds
Started Apr 25 12:24:04 PM PDT 24
Finished Apr 25 12:46:44 PM PDT 24
Peak memory 190980 kb
Host smart-c192b879-81c6-4344-85c5-9d47e3a91c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090398782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1090398782
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2148035699
Short name T71
Test name
Test status
Simulation time 250622712113 ps
CPU time 111.56 seconds
Started Apr 25 12:24:58 PM PDT 24
Finished Apr 25 12:26:51 PM PDT 24
Peak memory 190772 kb
Host smart-d467c633-8363-435a-97e2-d46b5cffbc67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148035699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2148035699
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.821136969
Short name T116
Test name
Test status
Simulation time 114000713583 ps
CPU time 1238.83 seconds
Started Apr 25 12:24:52 PM PDT 24
Finished Apr 25 12:45:33 PM PDT 24
Peak memory 190976 kb
Host smart-7c38fd0b-1764-4112-a103-4d139a4e7f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821136969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.821136969
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2971275231
Short name T263
Test name
Test status
Simulation time 141275390391 ps
CPU time 116.51 seconds
Started Apr 25 12:25:04 PM PDT 24
Finished Apr 25 12:27:01 PM PDT 24
Peak memory 191008 kb
Host smart-0bb261d0-328a-4fc6-b548-867c80a135c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971275231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2971275231
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.713724079
Short name T101
Test name
Test status
Simulation time 93051531 ps
CPU time 1.07 seconds
Started Apr 25 12:21:01 PM PDT 24
Finished Apr 25 12:21:03 PM PDT 24
Peak memory 194068 kb
Host smart-4595987d-6cfe-40bf-909d-88951498f9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713724079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.713724079
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3210882914
Short name T343
Test name
Test status
Simulation time 1492850790298 ps
CPU time 510.12 seconds
Started Apr 25 12:24:07 PM PDT 24
Finished Apr 25 12:32:38 PM PDT 24
Peak memory 194832 kb
Host smart-4b219dd2-8f15-4366-be4e-b328d68a64a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210882914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3210882914
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3987413094
Short name T134
Test name
Test status
Simulation time 1686573594947 ps
CPU time 991.84 seconds
Started Apr 25 12:24:38 PM PDT 24
Finished Apr 25 12:41:12 PM PDT 24
Peak memory 182796 kb
Host smart-9efdc9f8-8d95-443e-9008-cbde95d0cbc5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987413094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3987413094
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.625277868
Short name T239
Test name
Test status
Simulation time 61101266516 ps
CPU time 281.09 seconds
Started Apr 25 12:24:12 PM PDT 24
Finished Apr 25 12:28:54 PM PDT 24
Peak memory 190980 kb
Host smart-d2f5ccb9-fdca-4d83-a542-a1883d777630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625277868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.625277868
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1251172467
Short name T178
Test name
Test status
Simulation time 70822903687 ps
CPU time 60.6 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:25:56 PM PDT 24
Peak memory 190996 kb
Host smart-d772d0ec-da59-4bda-ba84-ca932f234c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251172467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1251172467
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.154012330
Short name T254
Test name
Test status
Simulation time 70768588229 ps
CPU time 47.35 seconds
Started Apr 25 12:24:03 PM PDT 24
Finished Apr 25 12:24:51 PM PDT 24
Peak memory 190964 kb
Host smart-ec879e78-9b30-44a7-8f35-a33721ca52cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154012330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.154012330
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1914555829
Short name T336
Test name
Test status
Simulation time 395477550638 ps
CPU time 402.38 seconds
Started Apr 25 12:24:58 PM PDT 24
Finished Apr 25 12:31:42 PM PDT 24
Peak memory 190932 kb
Host smart-c698249f-19f2-41a8-b5ac-fc0526e94976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914555829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1914555829
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1270502761
Short name T160
Test name
Test status
Simulation time 159105993216 ps
CPU time 251.37 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:29:04 PM PDT 24
Peak memory 190940 kb
Host smart-d3891f9f-623d-4e2c-85f8-fbbfb5bcb426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270502761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1270502761
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3959721281
Short name T445
Test name
Test status
Simulation time 326460993790 ps
CPU time 142.58 seconds
Started Apr 25 12:25:00 PM PDT 24
Finished Apr 25 12:27:24 PM PDT 24
Peak memory 191024 kb
Host smart-8baefb36-0b1d-478f-b510-ffdd7b854570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959721281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3959721281
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1926178850
Short name T207
Test name
Test status
Simulation time 2973304938239 ps
CPU time 1101.34 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:43:09 PM PDT 24
Peak memory 191000 kb
Host smart-6ea01c1f-bbb3-4ca8-b885-34510800de03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926178850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1926178850
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2506530851
Short name T183
Test name
Test status
Simulation time 127243805458 ps
CPU time 119.46 seconds
Started Apr 25 12:24:59 PM PDT 24
Finished Apr 25 12:27:00 PM PDT 24
Peak memory 194204 kb
Host smart-ec74757b-68dc-4e37-a6f2-cbf492af8619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506530851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2506530851
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3257300650
Short name T203
Test name
Test status
Simulation time 61433879226 ps
CPU time 111.35 seconds
Started Apr 25 12:24:27 PM PDT 24
Finished Apr 25 12:26:20 PM PDT 24
Peak memory 182804 kb
Host smart-65406751-b831-48aa-bdc2-cdb07d35f3db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257300650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3257300650
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/144.rv_timer_random.2852414429
Short name T238
Test name
Test status
Simulation time 72458227762 ps
CPU time 164.09 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:27:40 PM PDT 24
Peak memory 190924 kb
Host smart-d81d2e7b-791c-48dd-a8f1-9bd1f34f6725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852414429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2852414429
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2161146370
Short name T205
Test name
Test status
Simulation time 679164490640 ps
CPU time 217.76 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:28:22 PM PDT 24
Peak memory 190996 kb
Host smart-da7d10d7-e781-4cb0-925f-f0cea03acfb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161146370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2161146370
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.667237423
Short name T208
Test name
Test status
Simulation time 88331967782 ps
CPU time 142.89 seconds
Started Apr 25 12:25:04 PM PDT 24
Finished Apr 25 12:27:27 PM PDT 24
Peak memory 190996 kb
Host smart-684de499-85a3-44be-b17c-fec4aebd3529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667237423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.667237423
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1122324195
Short name T252
Test name
Test status
Simulation time 611874617411 ps
CPU time 541.52 seconds
Started Apr 25 12:24:32 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 182792 kb
Host smart-0d45d216-9646-4849-8eec-ca4319420eed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122324195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1122324195
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/150.rv_timer_random.2211987577
Short name T125
Test name
Test status
Simulation time 361069138151 ps
CPU time 606.5 seconds
Started Apr 25 12:25:07 PM PDT 24
Finished Apr 25 12:35:14 PM PDT 24
Peak memory 191008 kb
Host smart-667a4cbc-a53e-43f4-bedc-8d657a410002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211987577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2211987577
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3307936901
Short name T201
Test name
Test status
Simulation time 510010401176 ps
CPU time 425.25 seconds
Started Apr 25 12:25:17 PM PDT 24
Finished Apr 25 12:32:23 PM PDT 24
Peak memory 191028 kb
Host smart-20afaf38-d533-4d01-8891-d860e2d9d118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307936901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3307936901
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.3580346936
Short name T223
Test name
Test status
Simulation time 130269125911 ps
CPU time 619.51 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:35:16 PM PDT 24
Peak memory 194856 kb
Host smart-c30bd166-ee79-423e-a735-a85d33ae2573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580346936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3580346936
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.4136957447
Short name T341
Test name
Test status
Simulation time 109652100148 ps
CPU time 2460.26 seconds
Started Apr 25 12:24:58 PM PDT 24
Finished Apr 25 01:06:00 PM PDT 24
Peak memory 191004 kb
Host smart-4e51ecd2-ba70-452d-b553-eab25498d2c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136957447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4136957447
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.2927049074
Short name T228
Test name
Test status
Simulation time 138637582773 ps
CPU time 676.41 seconds
Started Apr 25 12:24:12 PM PDT 24
Finished Apr 25 12:35:30 PM PDT 24
Peak memory 190988 kb
Host smart-c09aa99a-6b16-41d0-8fb8-39ccca866efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927049074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2927049074
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2176209494
Short name T129
Test name
Test status
Simulation time 369152896306 ps
CPU time 168.79 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:27:41 PM PDT 24
Peak memory 190972 kb
Host smart-5eaebba3-d161-4a66-9dce-288f31359d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176209494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2176209494
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.514908488
Short name T166
Test name
Test status
Simulation time 341346019473 ps
CPU time 612.32 seconds
Started Apr 25 12:25:09 PM PDT 24
Finished Apr 25 12:35:22 PM PDT 24
Peak memory 190992 kb
Host smart-4cfb4398-9b96-49f1-b151-5902bd0388ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514908488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.514908488
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2729826784
Short name T79
Test name
Test status
Simulation time 38203700388 ps
CPU time 57.4 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:25:53 PM PDT 24
Peak memory 182800 kb
Host smart-55d5e718-4f4e-417c-abd2-c738e54b2802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729826784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2729826784
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2015925674
Short name T61
Test name
Test status
Simulation time 382161743906 ps
CPU time 314.74 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:29:44 PM PDT 24
Peak memory 191028 kb
Host smart-c4e57b92-aeef-4d13-af1c-4faf09b3e1f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015925674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2015925674
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1436542584
Short name T232
Test name
Test status
Simulation time 66785663490 ps
CPU time 106.56 seconds
Started Apr 25 12:24:33 PM PDT 24
Finished Apr 25 12:26:20 PM PDT 24
Peak memory 191020 kb
Host smart-f8faa1be-e25b-4378-afa7-d295203e8d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436542584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1436542584
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_random.2667984115
Short name T316
Test name
Test status
Simulation time 55379729208 ps
CPU time 77.83 seconds
Started Apr 25 12:24:34 PM PDT 24
Finished Apr 25 12:25:53 PM PDT 24
Peak memory 190996 kb
Host smart-2a14b64a-6367-4203-a382-67f427a47997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667984115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2667984115
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random.3493463711
Short name T245
Test name
Test status
Simulation time 1412841710635 ps
CPU time 468.46 seconds
Started Apr 25 12:24:44 PM PDT 24
Finished Apr 25 12:32:34 PM PDT 24
Peak memory 191136 kb
Host smart-ddce417d-7667-4436-9ef9-ef960815c848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493463711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3493463711
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3931867146
Short name T262
Test name
Test status
Simulation time 69476858350 ps
CPU time 95.34 seconds
Started Apr 25 12:24:29 PM PDT 24
Finished Apr 25 12:26:06 PM PDT 24
Peak memory 194848 kb
Host smart-96b893db-33b1-47ae-b6d1-1d32ea71b331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931867146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3931867146
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.512483769
Short name T187
Test name
Test status
Simulation time 119192849448 ps
CPU time 189.83 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:27:47 PM PDT 24
Peak memory 182796 kb
Host smart-55cbb4a6-5bf5-4394-84a3-1b0027e01a2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512483769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.512483769
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.3558612033
Short name T171
Test name
Test status
Simulation time 163374002657 ps
CPU time 568.79 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:34:14 PM PDT 24
Peak memory 190740 kb
Host smart-87958857-6401-4fd1-9830-1a63d482d3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558612033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3558612033
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3107284760
Short name T323
Test name
Test status
Simulation time 53576854819 ps
CPU time 804.84 seconds
Started Apr 25 12:24:45 PM PDT 24
Finished Apr 25 12:38:11 PM PDT 24
Peak memory 190980 kb
Host smart-6f34c2d5-65d5-468a-9e6e-a5997dc3010d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107284760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3107284760
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2012785182
Short name T247
Test name
Test status
Simulation time 85225769725 ps
CPU time 83.3 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:26:11 PM PDT 24
Peak memory 190980 kb
Host smart-3003647a-81e3-4734-aad9-aac85e8228d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012785182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2012785182
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2824339208
Short name T221
Test name
Test status
Simulation time 168573820521 ps
CPU time 554.28 seconds
Started Apr 25 12:24:42 PM PDT 24
Finished Apr 25 12:33:57 PM PDT 24
Peak memory 191004 kb
Host smart-b536d082-c084-4993-bf57-318a3a2e99bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824339208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2824339208
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2833451035
Short name T466
Test name
Test status
Simulation time 171203038 ps
CPU time 3.12 seconds
Started Apr 25 12:21:28 PM PDT 24
Finished Apr 25 12:21:33 PM PDT 24
Peak memory 189152 kb
Host smart-57860a73-cc9c-4d53-811c-a107c33d0a0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833451035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2833451035
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2361484360
Short name T554
Test name
Test status
Simulation time 17108025 ps
CPU time 0.63 seconds
Started Apr 25 12:18:00 PM PDT 24
Finished Apr 25 12:18:02 PM PDT 24
Peak memory 182696 kb
Host smart-0f34b749-44db-4bcc-8772-ad14c6d0c321
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361484360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2361484360
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4023253573
Short name T503
Test name
Test status
Simulation time 20171726 ps
CPU time 0.69 seconds
Started Apr 25 12:21:39 PM PDT 24
Finished Apr 25 12:21:41 PM PDT 24
Peak memory 192312 kb
Host smart-5ff4487e-ca11-43c2-b38d-ccaf9c2bc45d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023253573 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.4023253573
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1889389947
Short name T93
Test name
Test status
Simulation time 21113456 ps
CPU time 0.56 seconds
Started Apr 25 12:21:29 PM PDT 24
Finished Apr 25 12:21:31 PM PDT 24
Peak memory 182516 kb
Host smart-97ad64cc-ab7f-4fac-8c97-1ce084f00bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889389947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1889389947
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4163887063
Short name T457
Test name
Test status
Simulation time 12540053 ps
CPU time 0.58 seconds
Started Apr 25 12:21:40 PM PDT 24
Finished Apr 25 12:21:43 PM PDT 24
Peak memory 180396 kb
Host smart-7ad3a5ef-e14f-4145-ac0b-855587360ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163887063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.4163887063
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.461632116
Short name T509
Test name
Test status
Simulation time 357246204 ps
CPU time 0.84 seconds
Started Apr 25 12:21:28 PM PDT 24
Finished Apr 25 12:21:31 PM PDT 24
Peak memory 189864 kb
Host smart-ed8c84ae-38b0-4043-848b-a0acf5125d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461632116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.461632116
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1450540451
Short name T475
Test name
Test status
Simulation time 166041576 ps
CPU time 2.37 seconds
Started Apr 25 12:21:11 PM PDT 24
Finished Apr 25 12:21:16 PM PDT 24
Peak memory 196392 kb
Host smart-7f0c51e4-98cc-4494-a8ad-992f59f3c86f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450540451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1450540451
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3963571085
Short name T551
Test name
Test status
Simulation time 104714072 ps
CPU time 1.36 seconds
Started Apr 25 12:21:39 PM PDT 24
Finished Apr 25 12:21:41 PM PDT 24
Peak memory 193800 kb
Host smart-214a5e7c-af97-4778-84b8-220b30e5e59a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963571085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3963571085
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2263300472
Short name T573
Test name
Test status
Simulation time 20917814 ps
CPU time 0.6 seconds
Started Apr 25 12:21:54 PM PDT 24
Finished Apr 25 12:21:56 PM PDT 24
Peak memory 182092 kb
Host smart-6780b11e-de8f-4a84-b38c-da83b05ffc2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263300472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2263300472
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4114490119
Short name T471
Test name
Test status
Simulation time 1929485950 ps
CPU time 3.28 seconds
Started Apr 25 12:21:39 PM PDT 24
Finished Apr 25 12:21:43 PM PDT 24
Peak memory 193440 kb
Host smart-539d25a8-d45a-42ad-9013-9a36354af9c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114490119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4114490119
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4231567204
Short name T476
Test name
Test status
Simulation time 16553600 ps
CPU time 0.54 seconds
Started Apr 25 12:22:10 PM PDT 24
Finished Apr 25 12:22:12 PM PDT 24
Peak memory 181604 kb
Host smart-e81e732d-f579-410a-852a-184ea7e0415e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231567204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4231567204
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3363943798
Short name T521
Test name
Test status
Simulation time 39519617 ps
CPU time 1.62 seconds
Started Apr 25 12:22:03 PM PDT 24
Finished Apr 25 12:22:05 PM PDT 24
Peak memory 197456 kb
Host smart-d99dc3c8-0e8b-4fe6-987b-dd2b411283ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363943798 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3363943798
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3180514869
Short name T488
Test name
Test status
Simulation time 22996091 ps
CPU time 0.6 seconds
Started Apr 25 12:17:09 PM PDT 24
Finished Apr 25 12:17:11 PM PDT 24
Peak memory 182668 kb
Host smart-1e5aea4b-b8de-42cf-831b-c8d9c1c22dcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180514869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3180514869
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2846713028
Short name T526
Test name
Test status
Simulation time 81945618 ps
CPU time 0.61 seconds
Started Apr 25 12:21:39 PM PDT 24
Finished Apr 25 12:21:41 PM PDT 24
Peak memory 180780 kb
Host smart-c8a7ff02-2c46-478e-9abe-d20b90030b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846713028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2846713028
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1926920477
Short name T513
Test name
Test status
Simulation time 187777564 ps
CPU time 2.41 seconds
Started Apr 25 12:21:40 PM PDT 24
Finished Apr 25 12:21:44 PM PDT 24
Peak memory 197280 kb
Host smart-32312a92-d735-4279-b705-b5caca1ccca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926920477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1926920477
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3233968899
Short name T542
Test name
Test status
Simulation time 70119064 ps
CPU time 1.04 seconds
Started Apr 25 12:21:41 PM PDT 24
Finished Apr 25 12:21:43 PM PDT 24
Peak memory 194036 kb
Host smart-b68c5721-a01c-49fa-8e92-93628fd4b4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233968899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3233968899
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1525580743
Short name T51
Test name
Test status
Simulation time 147847732 ps
CPU time 0.93 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:06 PM PDT 24
Peak memory 196680 kb
Host smart-15a5527d-a7b3-48d6-b3b4-4b760f57aaca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525580743 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1525580743
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2106791705
Short name T35
Test name
Test status
Simulation time 11988312 ps
CPU time 0.6 seconds
Started Apr 25 12:21:16 PM PDT 24
Finished Apr 25 12:21:18 PM PDT 24
Peak memory 181304 kb
Host smart-a3307ad0-493d-4ca3-8cb3-103c015f3363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106791705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2106791705
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1694647567
Short name T538
Test name
Test status
Simulation time 18479371 ps
CPU time 0.57 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:05 PM PDT 24
Peak memory 182468 kb
Host smart-2074e67d-690b-4dca-a037-c7085c83bb99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694647567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1694647567
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3531658884
Short name T94
Test name
Test status
Simulation time 22156153 ps
CPU time 0.59 seconds
Started Apr 25 12:21:09 PM PDT 24
Finished Apr 25 12:21:11 PM PDT 24
Peak memory 191504 kb
Host smart-c2e3de86-0085-4b22-a994-818e99d7f8fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531658884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3531658884
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1209464031
Short name T530
Test name
Test status
Simulation time 40982009 ps
CPU time 1.78 seconds
Started Apr 25 12:21:02 PM PDT 24
Finished Apr 25 12:21:04 PM PDT 24
Peak memory 197168 kb
Host smart-204c95f1-e2e9-4e42-9115-1c17b47118dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209464031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1209464031
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.708253860
Short name T535
Test name
Test status
Simulation time 325786658 ps
CPU time 0.8 seconds
Started Apr 25 12:21:28 PM PDT 24
Finished Apr 25 12:21:30 PM PDT 24
Peak memory 192280 kb
Host smart-7566fc46-f089-4d28-88ff-877a0f43d333
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708253860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.708253860
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2601697727
Short name T533
Test name
Test status
Simulation time 75752955 ps
CPU time 1.06 seconds
Started Apr 25 12:17:10 PM PDT 24
Finished Apr 25 12:17:12 PM PDT 24
Peak memory 197320 kb
Host smart-467cad60-f221-4ac6-ad60-8ebb25d4e133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601697727 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2601697727
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.933277091
Short name T87
Test name
Test status
Simulation time 36526115 ps
CPU time 0.59 seconds
Started Apr 25 12:20:11 PM PDT 24
Finished Apr 25 12:20:14 PM PDT 24
Peak memory 182548 kb
Host smart-f6270c26-963c-4e0b-ab67-58e72ee9a698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933277091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.933277091
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.400172278
Short name T491
Test name
Test status
Simulation time 22567910 ps
CPU time 0.51 seconds
Started Apr 25 12:21:16 PM PDT 24
Finished Apr 25 12:21:18 PM PDT 24
Peak memory 182384 kb
Host smart-ccd5d377-12e2-4c9a-b71b-05fb9b57b52c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400172278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.400172278
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1612269726
Short name T97
Test name
Test status
Simulation time 117866191 ps
CPU time 0.67 seconds
Started Apr 25 12:21:06 PM PDT 24
Finished Apr 25 12:21:08 PM PDT 24
Peak memory 191328 kb
Host smart-08b88a87-894e-4a7e-8def-7c85330e1351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612269726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1612269726
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2392258109
Short name T500
Test name
Test status
Simulation time 237326018 ps
CPU time 1.35 seconds
Started Apr 25 12:21:17 PM PDT 24
Finished Apr 25 12:21:19 PM PDT 24
Peak memory 197124 kb
Host smart-e4b15f87-1b37-4830-9b79-95189dc70c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392258109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2392258109
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.954259865
Short name T489
Test name
Test status
Simulation time 47839307 ps
CPU time 0.76 seconds
Started Apr 25 12:21:50 PM PDT 24
Finished Apr 25 12:21:53 PM PDT 24
Peak memory 193112 kb
Host smart-84128f3d-0faa-492d-8daa-1cda808c0fa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954259865 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.954259865
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4033741862
Short name T575
Test name
Test status
Simulation time 14098033 ps
CPU time 0.54 seconds
Started Apr 25 12:21:00 PM PDT 24
Finished Apr 25 12:21:01 PM PDT 24
Peak memory 181976 kb
Host smart-75dd52b8-fe4c-4726-b117-39b21dae6a04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033741862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4033741862
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3560873685
Short name T505
Test name
Test status
Simulation time 75560529 ps
CPU time 0.52 seconds
Started Apr 25 12:21:00 PM PDT 24
Finished Apr 25 12:21:01 PM PDT 24
Peak memory 181684 kb
Host smart-130a334b-3457-442e-9404-d40f3db46ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560873685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3560873685
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.362616695
Short name T96
Test name
Test status
Simulation time 15804861 ps
CPU time 0.7 seconds
Started Apr 25 12:21:34 PM PDT 24
Finished Apr 25 12:21:37 PM PDT 24
Peak memory 189872 kb
Host smart-8bc713a8-f6cc-4d62-982e-58dbd6b715ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362616695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.362616695
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3634398317
Short name T450
Test name
Test status
Simulation time 225662522 ps
CPU time 2.75 seconds
Started Apr 25 12:21:01 PM PDT 24
Finished Apr 25 12:21:05 PM PDT 24
Peak memory 197436 kb
Host smart-7e2db56a-8414-429d-92d9-15691a83ce0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634398317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3634398317
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2306371665
Short name T534
Test name
Test status
Simulation time 351523069 ps
CPU time 1.11 seconds
Started Apr 25 12:21:53 PM PDT 24
Finished Apr 25 12:21:55 PM PDT 24
Peak memory 194660 kb
Host smart-34a6fe2d-1b70-46c6-b788-c0c485b31a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306371665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2306371665
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.599269478
Short name T518
Test name
Test status
Simulation time 123093908 ps
CPU time 1.55 seconds
Started Apr 25 12:21:11 PM PDT 24
Finished Apr 25 12:21:15 PM PDT 24
Peak memory 196292 kb
Host smart-f80e90d0-4ad8-4b7c-bb45-3647a4cb39f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599269478 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.599269478
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3425515324
Short name T484
Test name
Test status
Simulation time 42103415 ps
CPU time 0.6 seconds
Started Apr 25 12:21:34 PM PDT 24
Finished Apr 25 12:21:37 PM PDT 24
Peak memory 180128 kb
Host smart-dd2f8268-880d-494c-8827-11bf0be9a615
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425515324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3425515324
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2274507825
Short name T461
Test name
Test status
Simulation time 29581426 ps
CPU time 0.6 seconds
Started Apr 25 12:21:37 PM PDT 24
Finished Apr 25 12:21:39 PM PDT 24
Peak memory 182448 kb
Host smart-415495a7-fd58-45d5-a737-8c7d23dafdc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274507825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2274507825
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2226418717
Short name T34
Test name
Test status
Simulation time 20830982 ps
CPU time 0.63 seconds
Started Apr 25 12:21:48 PM PDT 24
Finished Apr 25 12:21:50 PM PDT 24
Peak memory 190860 kb
Host smart-a691a4e2-4430-4a25-a0c9-20a257cb36c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226418717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2226418717
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4267003082
Short name T577
Test name
Test status
Simulation time 36717827 ps
CPU time 0.98 seconds
Started Apr 25 12:21:50 PM PDT 24
Finished Apr 25 12:21:53 PM PDT 24
Peak memory 196268 kb
Host smart-98482674-5345-4267-8243-dce1ccc618d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267003082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.4267003082
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4010906233
Short name T576
Test name
Test status
Simulation time 163217155 ps
CPU time 0.81 seconds
Started Apr 25 12:21:35 PM PDT 24
Finished Apr 25 12:21:37 PM PDT 24
Peak memory 192220 kb
Host smart-fea481bc-3823-4bca-98a5-7bd55401723b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010906233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.4010906233
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1209685372
Short name T544
Test name
Test status
Simulation time 97326236 ps
CPU time 1.23 seconds
Started Apr 25 12:21:40 PM PDT 24
Finished Apr 25 12:21:43 PM PDT 24
Peak memory 197160 kb
Host smart-6c4cf81c-73b8-4a7e-8b67-bc26cb56c518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209685372 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1209685372
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3543663827
Short name T508
Test name
Test status
Simulation time 58681186 ps
CPU time 0.56 seconds
Started Apr 25 12:21:35 PM PDT 24
Finished Apr 25 12:21:37 PM PDT 24
Peak memory 181476 kb
Host smart-87183186-448d-41c7-9549-9e92f874df1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543663827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3543663827
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1267167811
Short name T453
Test name
Test status
Simulation time 53899796 ps
CPU time 0.52 seconds
Started Apr 25 12:21:53 PM PDT 24
Finished Apr 25 12:21:55 PM PDT 24
Peak memory 181728 kb
Host smart-e6d204fc-9ef3-4d00-a916-1db7cbfd6541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267167811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1267167811
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.723279849
Short name T507
Test name
Test status
Simulation time 29310390 ps
CPU time 0.78 seconds
Started Apr 25 12:21:28 PM PDT 24
Finished Apr 25 12:21:31 PM PDT 24
Peak memory 190016 kb
Host smart-13c15e74-99e5-4d45-bb61-c306ff3794fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723279849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.723279849
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1040329094
Short name T547
Test name
Test status
Simulation time 127386850 ps
CPU time 1.14 seconds
Started Apr 25 12:21:12 PM PDT 24
Finished Apr 25 12:21:15 PM PDT 24
Peak memory 196984 kb
Host smart-aaa6e869-4f46-40e3-94e4-ead79c81c118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040329094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1040329094
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3672709509
Short name T564
Test name
Test status
Simulation time 42024344 ps
CPU time 0.76 seconds
Started Apr 25 12:21:29 PM PDT 24
Finished Apr 25 12:21:31 PM PDT 24
Peak memory 192652 kb
Host smart-23332fa9-4437-443c-8d0c-9b582f9e90fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672709509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3672709509
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2516223944
Short name T574
Test name
Test status
Simulation time 104580143 ps
CPU time 0.76 seconds
Started Apr 25 12:21:25 PM PDT 24
Finished Apr 25 12:21:26 PM PDT 24
Peak memory 195664 kb
Host smart-ecdfff84-1f7b-4862-b0ce-0b067a3b633d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516223944 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2516223944
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.509515695
Short name T492
Test name
Test status
Simulation time 15784882 ps
CPU time 0.54 seconds
Started Apr 25 12:21:41 PM PDT 24
Finished Apr 25 12:21:42 PM PDT 24
Peak memory 182284 kb
Host smart-95b1e586-1e82-440d-b2ad-a8e60d1c85d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509515695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.509515695
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3919104340
Short name T514
Test name
Test status
Simulation time 21930658 ps
CPU time 0.57 seconds
Started Apr 25 12:21:41 PM PDT 24
Finished Apr 25 12:21:43 PM PDT 24
Peak memory 181556 kb
Host smart-d9ea5395-132b-4cfd-9ecd-51d99b5dbaae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919104340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3919104340
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4274415701
Short name T560
Test name
Test status
Simulation time 35188778 ps
CPU time 0.78 seconds
Started Apr 25 12:22:10 PM PDT 24
Finished Apr 25 12:22:12 PM PDT 24
Peak memory 192896 kb
Host smart-3fe05e3e-431f-4fff-b50c-262d20b25e3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274415701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4274415701
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2911707152
Short name T455
Test name
Test status
Simulation time 76804264 ps
CPU time 2.62 seconds
Started Apr 25 12:21:25 PM PDT 24
Finished Apr 25 12:21:29 PM PDT 24
Peak memory 197468 kb
Host smart-b4a10bcb-94c5-4a41-b9ec-37b193d3de2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911707152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2911707152
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2152466109
Short name T100
Test name
Test status
Simulation time 120238650 ps
CPU time 1.42 seconds
Started Apr 25 12:21:08 PM PDT 24
Finished Apr 25 12:21:11 PM PDT 24
Peak memory 194316 kb
Host smart-428e6d06-0607-4618-86e0-8565a4c659f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152466109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2152466109
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3944605244
Short name T478
Test name
Test status
Simulation time 21191914 ps
CPU time 0.73 seconds
Started Apr 25 12:21:53 PM PDT 24
Finished Apr 25 12:21:56 PM PDT 24
Peak memory 193992 kb
Host smart-063ddbb8-2ead-4d4a-b5eb-bd0d7ee8fa0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944605244 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3944605244
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3306589047
Short name T55
Test name
Test status
Simulation time 11960041 ps
CPU time 0.55 seconds
Started Apr 25 12:20:33 PM PDT 24
Finished Apr 25 12:20:34 PM PDT 24
Peak memory 182364 kb
Host smart-ae778754-e025-4567-9c55-3690440cab0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306589047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3306589047
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.956917255
Short name T571
Test name
Test status
Simulation time 17242812 ps
CPU time 0.6 seconds
Started Apr 25 12:21:56 PM PDT 24
Finished Apr 25 12:21:58 PM PDT 24
Peak memory 181768 kb
Host smart-61d8d8a9-886b-4ed9-9902-a5531d30f2e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956917255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.956917255
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3056573290
Short name T580
Test name
Test status
Simulation time 106939979 ps
CPU time 0.73 seconds
Started Apr 25 12:20:35 PM PDT 24
Finished Apr 25 12:20:36 PM PDT 24
Peak memory 193192 kb
Host smart-2414f7ce-b312-47ea-9dcf-c8e618b57d0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056573290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3056573290
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3557729552
Short name T472
Test name
Test status
Simulation time 157575101 ps
CPU time 2.18 seconds
Started Apr 25 12:22:10 PM PDT 24
Finished Apr 25 12:22:13 PM PDT 24
Peak memory 195896 kb
Host smart-f63047ce-b186-4ac5-a78d-cd3ac2330b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557729552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3557729552
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2147257732
Short name T516
Test name
Test status
Simulation time 72496337 ps
CPU time 1.05 seconds
Started Apr 25 12:19:18 PM PDT 24
Finished Apr 25 12:19:19 PM PDT 24
Peak memory 194920 kb
Host smart-3bf88560-3f76-4550-8107-5517b05c6f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147257732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2147257732
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1832813003
Short name T517
Test name
Test status
Simulation time 28253085 ps
CPU time 0.83 seconds
Started Apr 25 12:21:22 PM PDT 24
Finished Apr 25 12:21:24 PM PDT 24
Peak memory 195512 kb
Host smart-744a9147-3f9e-4b55-ac4b-60b67afd4bfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832813003 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1832813003
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4284886114
Short name T497
Test name
Test status
Simulation time 24788292 ps
CPU time 0.65 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:05 PM PDT 24
Peak memory 180556 kb
Host smart-89411ed4-787d-4674-ab99-1a73f002b07a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284886114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4284886114
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3012255362
Short name T85
Test name
Test status
Simulation time 16445908 ps
CPU time 0.72 seconds
Started Apr 25 12:21:53 PM PDT 24
Finished Apr 25 12:21:56 PM PDT 24
Peak memory 189936 kb
Host smart-9a8659dd-cdcc-455f-8ec5-6607f8351746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012255362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3012255362
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.431865441
Short name T53
Test name
Test status
Simulation time 113477140 ps
CPU time 1.89 seconds
Started Apr 25 12:21:49 PM PDT 24
Finished Apr 25 12:21:52 PM PDT 24
Peak memory 196176 kb
Host smart-e411a61b-eee3-4d92-97f5-8934c40c6955
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431865441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.431865441
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.573998689
Short name T536
Test name
Test status
Simulation time 285350513 ps
CPU time 1.1 seconds
Started Apr 25 12:22:02 PM PDT 24
Finished Apr 25 12:22:04 PM PDT 24
Peak memory 182356 kb
Host smart-0d9f0510-0fc4-4bd8-bdc5-f7cb5b25f120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573998689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.573998689
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3628796052
Short name T550
Test name
Test status
Simulation time 24364170 ps
CPU time 1.07 seconds
Started Apr 25 12:21:05 PM PDT 24
Finished Apr 25 12:21:08 PM PDT 24
Peak memory 196700 kb
Host smart-a930e0a1-8ebf-4c68-8c6a-130e18f54deb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628796052 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3628796052
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.239147511
Short name T90
Test name
Test status
Simulation time 24039330 ps
CPU time 0.55 seconds
Started Apr 25 12:21:27 PM PDT 24
Finished Apr 25 12:21:29 PM PDT 24
Peak memory 182256 kb
Host smart-82d6d8eb-4484-4283-932a-4e53bdcc0807
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239147511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.239147511
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.416004053
Short name T462
Test name
Test status
Simulation time 38364794 ps
CPU time 0.54 seconds
Started Apr 25 12:19:15 PM PDT 24
Finished Apr 25 12:19:16 PM PDT 24
Peak memory 181868 kb
Host smart-442705fc-4f25-4d05-9aac-a9a9c922ed1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416004053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.416004053
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1545111766
Short name T572
Test name
Test status
Simulation time 14727310 ps
CPU time 0.62 seconds
Started Apr 25 12:19:06 PM PDT 24
Finished Apr 25 12:19:08 PM PDT 24
Peak memory 191436 kb
Host smart-0133c985-a7d9-4922-8b39-7e85632cd06d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545111766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1545111766
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.713821717
Short name T490
Test name
Test status
Simulation time 752048619 ps
CPU time 3.32 seconds
Started Apr 25 12:21:03 PM PDT 24
Finished Apr 25 12:21:07 PM PDT 24
Peak memory 197428 kb
Host smart-697ed5cd-9b92-406c-9c10-2fbf719ea284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713821717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.713821717
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3924028048
Short name T549
Test name
Test status
Simulation time 89202858 ps
CPU time 1.06 seconds
Started Apr 25 12:21:09 PM PDT 24
Finished Apr 25 12:21:11 PM PDT 24
Peak memory 194480 kb
Host smart-66282524-dafd-4ac6-8612-3d2b1cd14e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924028048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3924028048
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3250731213
Short name T529
Test name
Test status
Simulation time 41541077 ps
CPU time 0.76 seconds
Started Apr 25 12:21:06 PM PDT 24
Finished Apr 25 12:21:08 PM PDT 24
Peak memory 195368 kb
Host smart-e6fc14c2-bee3-4f87-91f9-cea69feda93b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250731213 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3250731213
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1130091733
Short name T482
Test name
Test status
Simulation time 33388382 ps
CPU time 0.53 seconds
Started Apr 25 12:21:17 PM PDT 24
Finished Apr 25 12:21:19 PM PDT 24
Peak memory 181960 kb
Host smart-c587b5fa-817d-4935-bab4-5f51f2e2ea42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130091733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1130091733
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.997919917
Short name T510
Test name
Test status
Simulation time 13872249 ps
CPU time 0.54 seconds
Started Apr 25 12:21:06 PM PDT 24
Finished Apr 25 12:21:07 PM PDT 24
Peak memory 182260 kb
Host smart-3c102fe1-24a7-42d6-b9c9-dd456af6a097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997919917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.997919917
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.427679020
Short name T561
Test name
Test status
Simulation time 17229131 ps
CPU time 0.65 seconds
Started Apr 25 12:21:27 PM PDT 24
Finished Apr 25 12:21:29 PM PDT 24
Peak memory 190264 kb
Host smart-c50e29a7-016b-4570-a8ca-1317c49212d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427679020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.427679020
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3729775974
Short name T527
Test name
Test status
Simulation time 400545130 ps
CPU time 2.78 seconds
Started Apr 25 12:21:55 PM PDT 24
Finished Apr 25 12:21:59 PM PDT 24
Peak memory 197132 kb
Host smart-b8a411e1-3e23-44bc-b255-113a766761bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729775974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3729775974
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3236528268
Short name T553
Test name
Test status
Simulation time 64775866 ps
CPU time 0.79 seconds
Started Apr 25 12:21:27 PM PDT 24
Finished Apr 25 12:21:29 PM PDT 24
Peak memory 191956 kb
Host smart-33b6c9fb-353f-48b0-ba13-838ee3f0b88c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236528268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3236528268
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4099399903
Short name T496
Test name
Test status
Simulation time 280128806 ps
CPU time 2.53 seconds
Started Apr 25 12:21:08 PM PDT 24
Finished Apr 25 12:21:12 PM PDT 24
Peak memory 190140 kb
Host smart-712cbfc5-e6ff-4938-873c-c51dea7c1400
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099399903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4099399903
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.223701260
Short name T502
Test name
Test status
Simulation time 15127659 ps
CPU time 0.56 seconds
Started Apr 25 12:21:49 PM PDT 24
Finished Apr 25 12:21:52 PM PDT 24
Peak memory 182288 kb
Host smart-fc474c11-3d52-4ed0-bff9-6d48bb0c6367
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223701260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.223701260
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.262565749
Short name T493
Test name
Test status
Simulation time 326844295 ps
CPU time 0.73 seconds
Started Apr 25 12:21:01 PM PDT 24
Finished Apr 25 12:21:03 PM PDT 24
Peak memory 193604 kb
Host smart-daa739dd-8973-4755-986c-a918636677a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262565749 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.262565749
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3807065797
Short name T531
Test name
Test status
Simulation time 125131473 ps
CPU time 0.55 seconds
Started Apr 25 12:21:59 PM PDT 24
Finished Apr 25 12:22:01 PM PDT 24
Peak memory 182524 kb
Host smart-22b2b6d7-6f7e-4fe9-8639-dcbf52fbd35f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807065797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3807065797
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.659301060
Short name T537
Test name
Test status
Simulation time 21447294 ps
CPU time 0.57 seconds
Started Apr 25 12:21:05 PM PDT 24
Finished Apr 25 12:21:07 PM PDT 24
Peak memory 182368 kb
Host smart-4b7e5edb-d1ec-40f8-956d-52a28fc9779e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659301060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.659301060
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.329075168
Short name T56
Test name
Test status
Simulation time 43456006 ps
CPU time 0.63 seconds
Started Apr 25 12:21:01 PM PDT 24
Finished Apr 25 12:21:03 PM PDT 24
Peak memory 189352 kb
Host smart-097b7fe4-f93c-487c-b355-45427b254b93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329075168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.329075168
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.712111097
Short name T463
Test name
Test status
Simulation time 31488736 ps
CPU time 1.55 seconds
Started Apr 25 12:19:59 PM PDT 24
Finished Apr 25 12:20:02 PM PDT 24
Peak memory 197564 kb
Host smart-628dec9c-6edd-491d-bd27-a307071d3681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712111097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.712111097
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2896141224
Short name T33
Test name
Test status
Simulation time 145624114 ps
CPU time 1.08 seconds
Started Apr 25 12:21:51 PM PDT 24
Finished Apr 25 12:21:53 PM PDT 24
Peak memory 194688 kb
Host smart-e1c30a8e-d657-4c8f-8e3d-88c415294d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896141224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2896141224
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3900132320
Short name T519
Test name
Test status
Simulation time 11178860 ps
CPU time 0.58 seconds
Started Apr 25 12:21:03 PM PDT 24
Finished Apr 25 12:21:05 PM PDT 24
Peak memory 180360 kb
Host smart-78a430d0-c5dc-4b2d-b907-e944ef60d197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900132320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3900132320
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.355758053
Short name T557
Test name
Test status
Simulation time 33078598 ps
CPU time 0.56 seconds
Started Apr 25 12:21:16 PM PDT 24
Finished Apr 25 12:21:18 PM PDT 24
Peak memory 180672 kb
Host smart-1b52ee17-177d-4704-848c-1175fd989b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355758053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.355758053
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3040212705
Short name T460
Test name
Test status
Simulation time 54011386 ps
CPU time 0.56 seconds
Started Apr 25 12:21:07 PM PDT 24
Finished Apr 25 12:21:08 PM PDT 24
Peak memory 181580 kb
Host smart-5426d2e1-7304-4c75-aad2-bb1550a60d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040212705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3040212705
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.890006928
Short name T485
Test name
Test status
Simulation time 12947866 ps
CPU time 0.57 seconds
Started Apr 25 12:17:30 PM PDT 24
Finished Apr 25 12:17:31 PM PDT 24
Peak memory 182412 kb
Host smart-771b361e-5cca-4091-a9f7-5365c4be509c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890006928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.890006928
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2324065382
Short name T515
Test name
Test status
Simulation time 13583172 ps
CPU time 0.56 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:06 PM PDT 24
Peak memory 181504 kb
Host smart-2d99fa0b-7e39-4c00-a211-4f5ea30e8a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324065382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2324065382
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1718013761
Short name T499
Test name
Test status
Simulation time 58822292 ps
CPU time 0.55 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:06 PM PDT 24
Peak memory 182152 kb
Host smart-a4d95c64-ff6f-4deb-9acf-7295e81b844e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718013761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1718013761
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.978954308
Short name T532
Test name
Test status
Simulation time 46069919 ps
CPU time 0.51 seconds
Started Apr 25 12:21:49 PM PDT 24
Finished Apr 25 12:21:51 PM PDT 24
Peak memory 182084 kb
Host smart-c2b6258c-d140-45a3-ad83-78e4d527c92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978954308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.978954308
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.671932529
Short name T465
Test name
Test status
Simulation time 25257291 ps
CPU time 0.55 seconds
Started Apr 25 12:21:51 PM PDT 24
Finished Apr 25 12:21:52 PM PDT 24
Peak memory 182252 kb
Host smart-6311f2f5-1932-46f6-801f-0a50f9a1f594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671932529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.671932529
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2179841340
Short name T558
Test name
Test status
Simulation time 14155688 ps
CPU time 0.55 seconds
Started Apr 25 12:16:50 PM PDT 24
Finished Apr 25 12:16:52 PM PDT 24
Peak memory 182408 kb
Host smart-56760f82-803c-48de-8bdf-72351e92d038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179841340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2179841340
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.377505614
Short name T452
Test name
Test status
Simulation time 16639947 ps
CPU time 0.56 seconds
Started Apr 25 12:16:43 PM PDT 24
Finished Apr 25 12:16:44 PM PDT 24
Peak memory 182420 kb
Host smart-fe475eed-9654-4820-a440-f7addf44d947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377505614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.377505614
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4134757773
Short name T88
Test name
Test status
Simulation time 14058894 ps
CPU time 0.62 seconds
Started Apr 25 12:17:39 PM PDT 24
Finished Apr 25 12:17:40 PM PDT 24
Peak memory 182688 kb
Host smart-995a4325-703d-4899-b38c-40d1234d6c44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134757773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.4134757773
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3888400349
Short name T89
Test name
Test status
Simulation time 39933944 ps
CPU time 1.4 seconds
Started Apr 25 12:21:00 PM PDT 24
Finished Apr 25 12:21:02 PM PDT 24
Peak memory 192928 kb
Host smart-5bedeb39-20b8-4efb-bf80-42a456efd570
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888400349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3888400349
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2114579991
Short name T86
Test name
Test status
Simulation time 14837975 ps
CPU time 0.55 seconds
Started Apr 25 12:21:08 PM PDT 24
Finished Apr 25 12:21:10 PM PDT 24
Peak memory 181992 kb
Host smart-c086f3c6-4b29-4d61-95f4-9c14ab266df2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114579991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2114579991
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2338708026
Short name T566
Test name
Test status
Simulation time 98639342 ps
CPU time 1.23 seconds
Started Apr 25 12:18:36 PM PDT 24
Finished Apr 25 12:18:37 PM PDT 24
Peak memory 197416 kb
Host smart-4665db85-9f1a-4031-82b9-449babcb69ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338708026 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2338708026
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.660259300
Short name T92
Test name
Test status
Simulation time 13778991 ps
CPU time 0.57 seconds
Started Apr 25 12:21:03 PM PDT 24
Finished Apr 25 12:21:05 PM PDT 24
Peak memory 181120 kb
Host smart-c00f23e5-d0df-44f3-9860-e18e228e2145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660259300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.660259300
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1520129914
Short name T464
Test name
Test status
Simulation time 15107996 ps
CPU time 0.54 seconds
Started Apr 25 12:21:08 PM PDT 24
Finished Apr 25 12:21:10 PM PDT 24
Peak memory 181676 kb
Host smart-7ed07e56-8ec5-4247-ba36-f5d3baeb6292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520129914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1520129914
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1046191619
Short name T520
Test name
Test status
Simulation time 59959590 ps
CPU time 0.67 seconds
Started Apr 25 12:21:05 PM PDT 24
Finished Apr 25 12:21:07 PM PDT 24
Peak memory 191400 kb
Host smart-9b567e93-3aa1-40f7-967f-ef9c6f4e29d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046191619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1046191619
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3499437847
Short name T449
Test name
Test status
Simulation time 92817902 ps
CPU time 2.41 seconds
Started Apr 25 12:21:53 PM PDT 24
Finished Apr 25 12:21:58 PM PDT 24
Peak memory 195816 kb
Host smart-4b66a7bd-0c70-4555-962b-dd93eba30cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499437847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3499437847
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2280920707
Short name T32
Test name
Test status
Simulation time 696096496 ps
CPU time 1.29 seconds
Started Apr 25 12:21:29 PM PDT 24
Finished Apr 25 12:21:32 PM PDT 24
Peak memory 195056 kb
Host smart-b0ed7dfe-6d0b-4270-bcad-41abffd14660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280920707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2280920707
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2970644172
Short name T483
Test name
Test status
Simulation time 17277650 ps
CPU time 0.54 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:06 PM PDT 24
Peak memory 181792 kb
Host smart-a8619ff3-a9f1-4d8c-a5b9-a427e9df1a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970644172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2970644172
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.689964571
Short name T454
Test name
Test status
Simulation time 52738236 ps
CPU time 0.58 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:05 PM PDT 24
Peak memory 180160 kb
Host smart-55f88caa-794b-4ee5-b3e2-f829e3ab00a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689964571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.689964571
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.382487779
Short name T467
Test name
Test status
Simulation time 24028222 ps
CPU time 0.56 seconds
Started Apr 25 12:16:56 PM PDT 24
Finished Apr 25 12:16:57 PM PDT 24
Peak memory 182496 kb
Host smart-073bcaa4-e51c-4d38-ae32-38ca81463e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382487779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.382487779
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3280976758
Short name T473
Test name
Test status
Simulation time 16500498 ps
CPU time 0.58 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:05 PM PDT 24
Peak memory 180780 kb
Host smart-040fba4a-4356-4683-98c6-31a7e9994007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280976758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3280976758
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3455425120
Short name T543
Test name
Test status
Simulation time 35674418 ps
CPU time 0.61 seconds
Started Apr 25 12:17:00 PM PDT 24
Finished Apr 25 12:17:02 PM PDT 24
Peak memory 182360 kb
Host smart-2991f9bc-9e6d-4b3e-bd66-2d3b6bf6b7f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455425120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3455425120
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.173335526
Short name T579
Test name
Test status
Simulation time 16368860 ps
CPU time 0.55 seconds
Started Apr 25 12:17:52 PM PDT 24
Finished Apr 25 12:17:53 PM PDT 24
Peak memory 182416 kb
Host smart-e4a1f8f5-72cd-4958-977f-75e9b6563450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173335526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.173335526
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.818870484
Short name T570
Test name
Test status
Simulation time 27584341 ps
CPU time 0.54 seconds
Started Apr 25 12:22:12 PM PDT 24
Finished Apr 25 12:22:14 PM PDT 24
Peak memory 182456 kb
Host smart-bcb3e7ce-91d0-4d5f-828b-f9b8e4f97ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818870484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.818870484
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1141650832
Short name T480
Test name
Test status
Simulation time 24880167 ps
CPU time 0.56 seconds
Started Apr 25 12:19:29 PM PDT 24
Finished Apr 25 12:19:30 PM PDT 24
Peak memory 182392 kb
Host smart-61966821-d25f-4625-abd2-071a2e2f48d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141650832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1141650832
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2354727032
Short name T474
Test name
Test status
Simulation time 26611692 ps
CPU time 0.54 seconds
Started Apr 25 12:22:10 PM PDT 24
Finished Apr 25 12:22:12 PM PDT 24
Peak memory 182480 kb
Host smart-c91e9e79-41ce-49da-b298-b60f993088c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354727032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2354727032
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2027078143
Short name T477
Test name
Test status
Simulation time 12895032 ps
CPU time 0.53 seconds
Started Apr 25 12:21:29 PM PDT 24
Finished Apr 25 12:21:31 PM PDT 24
Peak memory 182068 kb
Host smart-01716caf-6812-4897-8224-9aa89a176b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027078143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2027078143
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3493927917
Short name T541
Test name
Test status
Simulation time 26030030 ps
CPU time 0.69 seconds
Started Apr 25 12:21:34 PM PDT 24
Finished Apr 25 12:21:37 PM PDT 24
Peak memory 189412 kb
Host smart-05c6db61-295d-43dd-87d0-44f26fe6bdef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493927917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3493927917
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.655702219
Short name T57
Test name
Test status
Simulation time 751070737 ps
CPU time 1.6 seconds
Started Apr 25 12:21:53 PM PDT 24
Finished Apr 25 12:21:55 PM PDT 24
Peak memory 190756 kb
Host smart-8bd513f0-2615-4a47-bc6f-ec45ab2ee89a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655702219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.655702219
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3685557717
Short name T528
Test name
Test status
Simulation time 15837636 ps
CPU time 0.62 seconds
Started Apr 25 12:21:27 PM PDT 24
Finished Apr 25 12:21:29 PM PDT 24
Peak memory 181096 kb
Host smart-236262ee-9161-42d4-9b8b-0650de79755f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685557717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3685557717
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4260084669
Short name T504
Test name
Test status
Simulation time 125036645 ps
CPU time 0.86 seconds
Started Apr 25 12:21:40 PM PDT 24
Finished Apr 25 12:21:43 PM PDT 24
Peak memory 194036 kb
Host smart-4e830b58-0a7a-49db-b352-996f45fdff93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260084669 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4260084669
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.863264492
Short name T523
Test name
Test status
Simulation time 195374452 ps
CPU time 0.61 seconds
Started Apr 25 12:17:40 PM PDT 24
Finished Apr 25 12:17:42 PM PDT 24
Peak memory 182552 kb
Host smart-fff10d3f-f713-4f45-a46c-33c6fc8581a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863264492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.863264492
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.4009596018
Short name T501
Test name
Test status
Simulation time 56062587 ps
CPU time 0.52 seconds
Started Apr 25 12:21:01 PM PDT 24
Finished Apr 25 12:21:02 PM PDT 24
Peak memory 182108 kb
Host smart-fbeb980a-8aaa-4128-b866-9960e02526ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009596018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.4009596018
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4191017953
Short name T569
Test name
Test status
Simulation time 137204989 ps
CPU time 0.76 seconds
Started Apr 25 12:21:48 PM PDT 24
Finished Apr 25 12:21:50 PM PDT 24
Peak memory 192264 kb
Host smart-eb49d6bf-0782-4cac-a769-970db550a16c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191017953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.4191017953
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3960979415
Short name T540
Test name
Test status
Simulation time 191231776 ps
CPU time 1.29 seconds
Started Apr 25 12:21:03 PM PDT 24
Finished Apr 25 12:21:06 PM PDT 24
Peak memory 195576 kb
Host smart-86c05df3-0a14-40d9-8449-817a4a795bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960979415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3960979415
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.411207130
Short name T548
Test name
Test status
Simulation time 70005754 ps
CPU time 1.09 seconds
Started Apr 25 12:21:03 PM PDT 24
Finished Apr 25 12:21:06 PM PDT 24
Peak memory 193368 kb
Host smart-819996a5-3b42-4690-bf8b-4f013046e521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411207130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.411207130
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.611874729
Short name T468
Test name
Test status
Simulation time 61963672 ps
CPU time 0.56 seconds
Started Apr 25 12:22:10 PM PDT 24
Finished Apr 25 12:22:12 PM PDT 24
Peak memory 182480 kb
Host smart-e83a1ced-069a-44e3-acca-178e55de11d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611874729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.611874729
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.400897457
Short name T565
Test name
Test status
Simulation time 44584003 ps
CPU time 0.58 seconds
Started Apr 25 12:21:55 PM PDT 24
Finished Apr 25 12:21:57 PM PDT 24
Peak memory 181088 kb
Host smart-ebbd70fa-5aa1-48fe-9157-56a9f4e7d5c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400897457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.400897457
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3170198610
Short name T494
Test name
Test status
Simulation time 14343176 ps
CPU time 0.55 seconds
Started Apr 25 12:18:44 PM PDT 24
Finished Apr 25 12:18:45 PM PDT 24
Peak memory 182372 kb
Host smart-ff8331f9-e3ad-40e4-9e12-801afe427e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170198610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3170198610
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.68410127
Short name T487
Test name
Test status
Simulation time 20922422 ps
CPU time 0.55 seconds
Started Apr 25 12:17:12 PM PDT 24
Finished Apr 25 12:17:13 PM PDT 24
Peak memory 182020 kb
Host smart-5a23c494-ea18-4eb1-acd6-9d4c3c41d5cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68410127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.68410127
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1411186725
Short name T524
Test name
Test status
Simulation time 11371340 ps
CPU time 0.56 seconds
Started Apr 25 12:19:38 PM PDT 24
Finished Apr 25 12:19:39 PM PDT 24
Peak memory 182576 kb
Host smart-dae10a70-4392-46cc-b3d9-cfb9ff432b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411186725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1411186725
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1298919324
Short name T459
Test name
Test status
Simulation time 33452600 ps
CPU time 0.56 seconds
Started Apr 25 12:21:56 PM PDT 24
Finished Apr 25 12:21:58 PM PDT 24
Peak memory 180696 kb
Host smart-e209374f-5c1a-4526-9642-0b5cb01efb79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298919324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1298919324
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1861922313
Short name T481
Test name
Test status
Simulation time 12729458 ps
CPU time 0.55 seconds
Started Apr 25 12:18:45 PM PDT 24
Finished Apr 25 12:18:46 PM PDT 24
Peak memory 182408 kb
Host smart-54d8cac2-49a4-477d-a3ff-77d4893e442c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861922313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1861922313
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2061625526
Short name T470
Test name
Test status
Simulation time 14888226 ps
CPU time 0.56 seconds
Started Apr 25 12:21:12 PM PDT 24
Finished Apr 25 12:21:15 PM PDT 24
Peak memory 180960 kb
Host smart-2f4dad15-f8b9-447c-9bed-ff0edb5ac43c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061625526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2061625526
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.788140287
Short name T458
Test name
Test status
Simulation time 21775986 ps
CPU time 0.51 seconds
Started Apr 25 12:21:53 PM PDT 24
Finished Apr 25 12:21:55 PM PDT 24
Peak memory 181676 kb
Host smart-614fd893-8a89-4d29-b43d-ddc5ad8006fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788140287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.788140287
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1093846787
Short name T552
Test name
Test status
Simulation time 74702113 ps
CPU time 0.55 seconds
Started Apr 25 12:17:13 PM PDT 24
Finished Apr 25 12:17:14 PM PDT 24
Peak memory 182220 kb
Host smart-492cb832-3cb2-4c76-8a7b-0b09e929e285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093846787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1093846787
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.945985339
Short name T512
Test name
Test status
Simulation time 49090657 ps
CPU time 0.72 seconds
Started Apr 25 12:21:49 PM PDT 24
Finished Apr 25 12:21:51 PM PDT 24
Peak memory 193140 kb
Host smart-c0cad86a-d41e-4d59-b25f-cc50b4b1b477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945985339 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.945985339
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3215275450
Short name T506
Test name
Test status
Simulation time 12898442 ps
CPU time 0.53 seconds
Started Apr 25 12:21:12 PM PDT 24
Finished Apr 25 12:21:15 PM PDT 24
Peak memory 182076 kb
Host smart-355b9134-56de-45c5-bc67-cd0c9fadd53f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215275450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3215275450
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3272837810
Short name T498
Test name
Test status
Simulation time 18404924 ps
CPU time 0.59 seconds
Started Apr 25 12:17:57 PM PDT 24
Finished Apr 25 12:17:58 PM PDT 24
Peak memory 182380 kb
Host smart-2f987859-0c47-4148-bc56-69267bc6a7e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272837810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3272837810
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.224909335
Short name T99
Test name
Test status
Simulation time 43831249 ps
CPU time 0.84 seconds
Started Apr 25 12:21:29 PM PDT 24
Finished Apr 25 12:21:31 PM PDT 24
Peak memory 193112 kb
Host smart-ff98f123-a6ac-4655-a81d-1b48431cf1a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224909335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.224909335
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1229199489
Short name T451
Test name
Test status
Simulation time 357269574 ps
CPU time 1.81 seconds
Started Apr 25 12:21:40 PM PDT 24
Finished Apr 25 12:21:44 PM PDT 24
Peak memory 196116 kb
Host smart-cf40ab94-8eba-4e84-9676-ed488a60cdc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229199489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1229199489
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2760165967
Short name T522
Test name
Test status
Simulation time 665956221 ps
CPU time 1.04 seconds
Started Apr 25 12:22:01 PM PDT 24
Finished Apr 25 12:22:03 PM PDT 24
Peak memory 194588 kb
Host smart-d7cfc945-ff2c-40be-a23c-bbb96f17cd20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760165967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2760165967
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3606376754
Short name T578
Test name
Test status
Simulation time 56493715 ps
CPU time 0.79 seconds
Started Apr 25 12:23:04 PM PDT 24
Finished Apr 25 12:23:05 PM PDT 24
Peak memory 196292 kb
Host smart-86f496d0-56cf-4987-8b0c-b9d3fd27bc7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606376754 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3606376754
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1125521801
Short name T555
Test name
Test status
Simulation time 14890576 ps
CPU time 0.58 seconds
Started Apr 25 12:17:17 PM PDT 24
Finished Apr 25 12:17:19 PM PDT 24
Peak memory 182476 kb
Host smart-07c7236d-1824-4aba-be36-5dc7a1200ad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125521801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1125521801
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2903095288
Short name T456
Test name
Test status
Simulation time 43377194 ps
CPU time 0.53 seconds
Started Apr 25 12:21:41 PM PDT 24
Finished Apr 25 12:21:43 PM PDT 24
Peak memory 182120 kb
Host smart-db2edce6-c386-46ee-a227-9064df8b9c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903095288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2903095288
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.109928494
Short name T563
Test name
Test status
Simulation time 67489797 ps
CPU time 0.71 seconds
Started Apr 25 12:21:25 PM PDT 24
Finished Apr 25 12:21:27 PM PDT 24
Peak memory 192588 kb
Host smart-b0548bb7-711f-4ece-ad6e-7d46d480d4cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109928494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.109928494
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2341809211
Short name T562
Test name
Test status
Simulation time 29195660 ps
CPU time 1.34 seconds
Started Apr 25 12:21:12 PM PDT 24
Finished Apr 25 12:21:16 PM PDT 24
Peak memory 197000 kb
Host smart-e6333264-3185-4fe2-ab32-e33352b35443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341809211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2341809211
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.460741224
Short name T31
Test name
Test status
Simulation time 292780030 ps
CPU time 0.77 seconds
Started Apr 25 12:21:25 PM PDT 24
Finished Apr 25 12:21:27 PM PDT 24
Peak memory 193188 kb
Host smart-b088af7c-face-4ae0-a6b2-3bbaf3e4255e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460741224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.460741224
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4131659436
Short name T539
Test name
Test status
Simulation time 65390261 ps
CPU time 0.96 seconds
Started Apr 25 12:21:49 PM PDT 24
Finished Apr 25 12:21:51 PM PDT 24
Peak memory 195572 kb
Host smart-6a4f6482-60a7-40cc-b831-ddfed7d19bf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131659436 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.4131659436
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2368827664
Short name T486
Test name
Test status
Simulation time 20392144 ps
CPU time 0.51 seconds
Started Apr 25 12:21:41 PM PDT 24
Finished Apr 25 12:21:42 PM PDT 24
Peak memory 182268 kb
Host smart-11c87acf-d676-469d-a595-ef6d900f8008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368827664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2368827664
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.744267829
Short name T469
Test name
Test status
Simulation time 34791866 ps
CPU time 0.54 seconds
Started Apr 25 12:22:03 PM PDT 24
Finished Apr 25 12:22:05 PM PDT 24
Peak memory 182416 kb
Host smart-f0aa5264-a452-4863-a17d-4674b39c66a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744267829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.744267829
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3391164003
Short name T95
Test name
Test status
Simulation time 13791332 ps
CPU time 0.77 seconds
Started Apr 25 12:22:10 PM PDT 24
Finished Apr 25 12:22:12 PM PDT 24
Peak memory 190084 kb
Host smart-37d348d6-22c1-4712-aff2-58069874ece3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391164003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3391164003
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2504762163
Short name T479
Test name
Test status
Simulation time 594396582 ps
CPU time 2.63 seconds
Started Apr 25 12:21:41 PM PDT 24
Finished Apr 25 12:21:45 PM PDT 24
Peak memory 197212 kb
Host smart-3f82adaf-2f3e-4989-921b-a209eda06cae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504762163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2504762163
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4120954035
Short name T556
Test name
Test status
Simulation time 289996529 ps
CPU time 1.37 seconds
Started Apr 25 12:20:41 PM PDT 24
Finished Apr 25 12:20:43 PM PDT 24
Peak memory 195204 kb
Host smart-78ba3520-56a6-449d-be12-66a03afdfeba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120954035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.4120954035
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3496670383
Short name T36
Test name
Test status
Simulation time 84917171 ps
CPU time 1.14 seconds
Started Apr 25 12:21:08 PM PDT 24
Finished Apr 25 12:21:11 PM PDT 24
Peak memory 195712 kb
Host smart-cbdf8676-4bab-470e-a8b6-4d6dc4eee726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496670383 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3496670383
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4150006912
Short name T68
Test name
Test status
Simulation time 13649135 ps
CPU time 0.59 seconds
Started Apr 25 12:21:49 PM PDT 24
Finished Apr 25 12:21:51 PM PDT 24
Peak memory 180676 kb
Host smart-fe316f80-f6af-406f-bb6c-7463b4ec28f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150006912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4150006912
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1458464483
Short name T546
Test name
Test status
Simulation time 96746096 ps
CPU time 0.6 seconds
Started Apr 25 12:21:41 PM PDT 24
Finished Apr 25 12:21:43 PM PDT 24
Peak memory 181468 kb
Host smart-58230105-aa89-4a27-873b-f26db62d21cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458464483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1458464483
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.557634731
Short name T545
Test name
Test status
Simulation time 37531447 ps
CPU time 0.61 seconds
Started Apr 25 12:21:49 PM PDT 24
Finished Apr 25 12:21:51 PM PDT 24
Peak memory 190380 kb
Host smart-3566051a-28d9-44b1-b02e-eb5c0352c9d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557634731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.557634731
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1892583216
Short name T525
Test name
Test status
Simulation time 55691664 ps
CPU time 2.52 seconds
Started Apr 25 12:21:56 PM PDT 24
Finished Apr 25 12:22:00 PM PDT 24
Peak memory 196708 kb
Host smart-abc10f85-2591-487e-ab1a-f4bdaa1c50b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892583216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1892583216
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4251824545
Short name T102
Test name
Test status
Simulation time 354572278 ps
CPU time 1.07 seconds
Started Apr 25 12:21:04 PM PDT 24
Finished Apr 25 12:21:06 PM PDT 24
Peak memory 193524 kb
Host smart-52e11c25-c077-4263-9e36-bfeef46f453d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251824545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4251824545
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2454530668
Short name T495
Test name
Test status
Simulation time 37894277 ps
CPU time 0.93 seconds
Started Apr 25 12:17:50 PM PDT 24
Finished Apr 25 12:17:51 PM PDT 24
Peak memory 197368 kb
Host smart-45cf3e42-8f75-4864-8615-2ef70afa2c44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454530668 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2454530668
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3601916746
Short name T511
Test name
Test status
Simulation time 10991412 ps
CPU time 0.6 seconds
Started Apr 25 12:21:01 PM PDT 24
Finished Apr 25 12:21:03 PM PDT 24
Peak memory 180792 kb
Host smart-19961477-d2be-4038-92a2-de70eb38a088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601916746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3601916746
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1875654320
Short name T559
Test name
Test status
Simulation time 21668734 ps
CPU time 0.61 seconds
Started Apr 25 12:21:08 PM PDT 24
Finished Apr 25 12:21:10 PM PDT 24
Peak memory 179732 kb
Host smart-702b704b-744b-4924-840e-4f7327f0df68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875654320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1875654320
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1472547955
Short name T98
Test name
Test status
Simulation time 33519353 ps
CPU time 0.74 seconds
Started Apr 25 12:18:21 PM PDT 24
Finished Apr 25 12:18:23 PM PDT 24
Peak memory 191544 kb
Host smart-f7bf5018-5b14-47a5-b532-ec82a73a1e86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472547955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1472547955
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1229234666
Short name T568
Test name
Test status
Simulation time 324954611 ps
CPU time 1.71 seconds
Started Apr 25 12:21:08 PM PDT 24
Finished Apr 25 12:21:11 PM PDT 24
Peak memory 195872 kb
Host smart-97f32e3f-7b0a-4b1e-9bd5-10bcde15a8f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229234666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1229234666
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.445684555
Short name T567
Test name
Test status
Simulation time 69591484 ps
CPU time 0.8 seconds
Started Apr 25 12:18:44 PM PDT 24
Finished Apr 25 12:18:46 PM PDT 24
Peak memory 193080 kb
Host smart-45deefe2-730e-41c8-bc83-bb9ae8e0171c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445684555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.445684555
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2838275013
Short name T168
Test name
Test status
Simulation time 244090345237 ps
CPU time 456.4 seconds
Started Apr 25 12:23:53 PM PDT 24
Finished Apr 25 12:31:30 PM PDT 24
Peak memory 182796 kb
Host smart-80aedcd3-6080-45d7-9a83-50cbe101583a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838275013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2838275013
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2595522516
Short name T419
Test name
Test status
Simulation time 168586427969 ps
CPU time 222.99 seconds
Started Apr 25 12:24:03 PM PDT 24
Finished Apr 25 12:27:52 PM PDT 24
Peak memory 182824 kb
Host smart-2cc7f013-b273-4b9c-be01-5f70efdc3ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595522516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2595522516
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.291125442
Short name T302
Test name
Test status
Simulation time 154742200031 ps
CPU time 1453.35 seconds
Started Apr 25 12:24:05 PM PDT 24
Finished Apr 25 12:48:20 PM PDT 24
Peak memory 190980 kb
Host smart-24509d01-9d58-4757-acb7-afbae7321534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291125442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.291125442
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4235785557
Short name T198
Test name
Test status
Simulation time 1209051308088 ps
CPU time 892.59 seconds
Started Apr 25 12:24:03 PM PDT 24
Finished Apr 25 12:38:56 PM PDT 24
Peak memory 191004 kb
Host smart-9c3fac4a-41d3-449c-b332-4d875902e1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235785557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4235785557
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1685106527
Short name T429
Test name
Test status
Simulation time 478807052635 ps
CPU time 223.76 seconds
Started Apr 25 12:23:56 PM PDT 24
Finished Apr 25 12:27:40 PM PDT 24
Peak memory 182724 kb
Host smart-4f9293dc-149c-490e-9a67-88cc75ad167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685106527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1685106527
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3024788784
Short name T45
Test name
Test status
Simulation time 206053451490 ps
CPU time 86.97 seconds
Started Apr 25 12:23:59 PM PDT 24
Finished Apr 25 12:25:27 PM PDT 24
Peak memory 182792 kb
Host smart-9b1d5c3e-acd7-4a87-a570-d799fde0b635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024788784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3024788784
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.380924586
Short name T110
Test name
Test status
Simulation time 34893540421 ps
CPU time 33.86 seconds
Started Apr 25 12:24:05 PM PDT 24
Finished Apr 25 12:24:40 PM PDT 24
Peak memory 191012 kb
Host smart-9cc1a64f-0bab-4c2c-9bfa-27a0c9d4048c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380924586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.380924586
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1375273671
Short name T19
Test name
Test status
Simulation time 85731576 ps
CPU time 0.91 seconds
Started Apr 25 12:24:11 PM PDT 24
Finished Apr 25 12:24:14 PM PDT 24
Peak memory 214260 kb
Host smart-1dfaac30-a1b8-45ad-90c2-bfd376ab4a89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375273671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1375273671
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1753398011
Short name T39
Test name
Test status
Simulation time 56817040460 ps
CPU time 307.79 seconds
Started Apr 25 12:24:11 PM PDT 24
Finished Apr 25 12:29:21 PM PDT 24
Peak memory 197444 kb
Host smart-3301c5f4-ff86-4dc3-bb86-bcfd185adb35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753398011 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1753398011
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.899315649
Short name T393
Test name
Test status
Simulation time 304885103638 ps
CPU time 129.86 seconds
Started Apr 25 12:24:15 PM PDT 24
Finished Apr 25 12:26:26 PM PDT 24
Peak memory 182468 kb
Host smart-408d4aa8-0b93-4c8d-b71d-747bc320be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899315649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.899315649
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.784005198
Short name T332
Test name
Test status
Simulation time 158765815339 ps
CPU time 95.72 seconds
Started Apr 25 12:24:15 PM PDT 24
Finished Apr 25 12:25:52 PM PDT 24
Peak memory 182776 kb
Host smart-d8d8b97e-3429-42b0-be70-ab4eb1a67011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784005198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.784005198
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2299608011
Short name T259
Test name
Test status
Simulation time 1140571723599 ps
CPU time 1028.18 seconds
Started Apr 25 12:24:18 PM PDT 24
Finished Apr 25 12:41:27 PM PDT 24
Peak memory 191020 kb
Host smart-ddfd23be-a55c-415a-969e-b4621cf86799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299608011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2299608011
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.1037443526
Short name T146
Test name
Test status
Simulation time 193797869746 ps
CPU time 168.65 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:27:33 PM PDT 24
Peak memory 190988 kb
Host smart-57ca66e5-cbdb-4c42-aebc-6cd13ce4021c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037443526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1037443526
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3044407059
Short name T65
Test name
Test status
Simulation time 432740524164 ps
CPU time 248.68 seconds
Started Apr 25 12:24:58 PM PDT 24
Finished Apr 25 12:29:09 PM PDT 24
Peak memory 190972 kb
Host smart-a6fb7c2b-f877-4b35-b24b-972fda13f19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044407059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3044407059
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.4093756551
Short name T447
Test name
Test status
Simulation time 39615134670 ps
CPU time 69.62 seconds
Started Apr 25 12:24:45 PM PDT 24
Finished Apr 25 12:25:57 PM PDT 24
Peak memory 182732 kb
Host smart-8a2b8381-90bc-4f6a-8ca2-6668c35295c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093756551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4093756551
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3086957780
Short name T218
Test name
Test status
Simulation time 193691734473 ps
CPU time 120.82 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:26:50 PM PDT 24
Peak memory 190996 kb
Host smart-4cb6bf80-8cd0-43d7-8512-5423b3d6da48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086957780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3086957780
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.911247377
Short name T353
Test name
Test status
Simulation time 151199376948 ps
CPU time 85.89 seconds
Started Apr 25 12:24:56 PM PDT 24
Finished Apr 25 12:26:24 PM PDT 24
Peak memory 182796 kb
Host smart-0cd2e1fd-d05c-4982-b1b4-9cf81ae3ce39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911247377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.911247377
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3292586660
Short name T298
Test name
Test status
Simulation time 123074066404 ps
CPU time 258.95 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:29:08 PM PDT 24
Peak memory 191004 kb
Host smart-bfa24d78-fb69-41a1-9c2a-bfd3869f563d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292586660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3292586660
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.336476119
Short name T307
Test name
Test status
Simulation time 36312568355 ps
CPU time 12.51 seconds
Started Apr 25 12:24:27 PM PDT 24
Finished Apr 25 12:24:40 PM PDT 24
Peak memory 182744 kb
Host smart-f26f39cd-05fc-4c56-b5c2-ed71b5ad80f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336476119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.336476119
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.243477097
Short name T402
Test name
Test status
Simulation time 202466462079 ps
CPU time 182.02 seconds
Started Apr 25 12:24:15 PM PDT 24
Finished Apr 25 12:27:19 PM PDT 24
Peak memory 182808 kb
Host smart-69a1fe4c-d6fc-4470-8cf3-01a827ba9757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243477097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.243477097
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1491295427
Short name T386
Test name
Test status
Simulation time 144234504 ps
CPU time 0.79 seconds
Started Apr 25 12:24:10 PM PDT 24
Finished Apr 25 12:24:12 PM PDT 24
Peak memory 182592 kb
Host smart-0f80c625-45bd-4eae-b6de-bcb8cfb11453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491295427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1491295427
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.260092509
Short name T40
Test name
Test status
Simulation time 76933247600 ps
CPU time 762.99 seconds
Started Apr 25 12:23:52 PM PDT 24
Finished Apr 25 12:36:36 PM PDT 24
Peak memory 205644 kb
Host smart-805b3cb5-940f-4128-b5a0-e2db17aae16c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260092509 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.260092509
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.467305721
Short name T106
Test name
Test status
Simulation time 199668642717 ps
CPU time 125.27 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:26:55 PM PDT 24
Peak memory 182932 kb
Host smart-d44adb17-d2a9-4703-97c7-19ef312ef8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467305721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.467305721
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3104116391
Short name T142
Test name
Test status
Simulation time 333062126121 ps
CPU time 163.94 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:27:32 PM PDT 24
Peak memory 191000 kb
Host smart-a0b8ca50-17d1-465f-be94-30c98772688e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104116391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3104116391
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.821472153
Short name T277
Test name
Test status
Simulation time 194345447878 ps
CPU time 91.11 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:26:19 PM PDT 24
Peak memory 182788 kb
Host smart-567e6977-6c74-4b1b-ac08-f0bc79169716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821472153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.821472153
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.198475230
Short name T117
Test name
Test status
Simulation time 112560671125 ps
CPU time 548.4 seconds
Started Apr 25 12:25:02 PM PDT 24
Finished Apr 25 12:34:11 PM PDT 24
Peak memory 193172 kb
Host smart-51cdbf73-ba64-410a-8ecc-bc0643fce0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198475230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.198475230
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1222679783
Short name T156
Test name
Test status
Simulation time 243336337887 ps
CPU time 182.18 seconds
Started Apr 25 12:25:14 PM PDT 24
Finished Apr 25 12:28:17 PM PDT 24
Peak memory 190908 kb
Host smart-d088483b-60c3-408b-9c07-863c76af3174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222679783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1222679783
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1605005992
Short name T78
Test name
Test status
Simulation time 63297315806 ps
CPU time 553.92 seconds
Started Apr 25 12:24:42 PM PDT 24
Finished Apr 25 12:33:57 PM PDT 24
Peak memory 182764 kb
Host smart-00ece970-ce8a-4a87-8800-de14af04cac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605005992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1605005992
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1456762228
Short name T432
Test name
Test status
Simulation time 151692194852 ps
CPU time 61.47 seconds
Started Apr 25 12:24:04 PM PDT 24
Finished Apr 25 12:25:06 PM PDT 24
Peak memory 182736 kb
Host smart-153862d0-ec52-4738-a61f-44c0029c3266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456762228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1456762228
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1601445335
Short name T434
Test name
Test status
Simulation time 192400402358 ps
CPU time 150.81 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:26:56 PM PDT 24
Peak memory 193516 kb
Host smart-af652d83-9717-4146-8a0d-69828985f9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601445335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1601445335
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.820635864
Short name T42
Test name
Test status
Simulation time 28246020093 ps
CPU time 121.67 seconds
Started Apr 25 12:24:06 PM PDT 24
Finished Apr 25 12:26:09 PM PDT 24
Peak memory 195376 kb
Host smart-457526b3-843b-4130-8238-9d36619d567b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820635864 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.820635864
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.4160632384
Short name T185
Test name
Test status
Simulation time 83273205167 ps
CPU time 141.89 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:27:15 PM PDT 24
Peak memory 191016 kb
Host smart-17f4bdcf-2bdc-44cb-a346-ec18af33c7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160632384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.4160632384
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2848710530
Short name T128
Test name
Test status
Simulation time 154750599305 ps
CPU time 350.8 seconds
Started Apr 25 12:24:57 PM PDT 24
Finished Apr 25 12:30:49 PM PDT 24
Peak memory 182940 kb
Host smart-27315aff-484d-40a5-862e-bfca2c75b577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848710530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2848710530
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3069532695
Short name T81
Test name
Test status
Simulation time 1628043240542 ps
CPU time 580.54 seconds
Started Apr 25 12:24:41 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 191000 kb
Host smart-bcf98fdb-2834-44a5-bfc8-3e13dc6f8926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069532695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3069532695
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2042065749
Short name T293
Test name
Test status
Simulation time 733295547474 ps
CPU time 1751.15 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:54:04 PM PDT 24
Peak memory 191004 kb
Host smart-fa764b72-5290-42e4-aa9a-292bb0b34527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042065749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2042065749
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2168118219
Short name T59
Test name
Test status
Simulation time 77798596370 ps
CPU time 48.38 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:25:41 PM PDT 24
Peak memory 182864 kb
Host smart-a77797b5-ab5b-4b79-9fe8-f45d3d1cfc36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168118219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2168118219
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.995801422
Short name T145
Test name
Test status
Simulation time 542807544958 ps
CPU time 209.87 seconds
Started Apr 25 12:24:54 PM PDT 24
Finished Apr 25 12:28:26 PM PDT 24
Peak memory 182804 kb
Host smart-a364729e-0264-462b-80d3-5ca1e179c8be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995801422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.995801422
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.362969677
Short name T235
Test name
Test status
Simulation time 208945263605 ps
CPU time 435.45 seconds
Started Apr 25 12:24:49 PM PDT 24
Finished Apr 25 12:32:07 PM PDT 24
Peak memory 191132 kb
Host smart-30c7507b-4aa7-4628-9007-4aa6412fb911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362969677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.362969677
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2512458923
Short name T165
Test name
Test status
Simulation time 329423297337 ps
CPU time 274.25 seconds
Started Apr 25 12:24:54 PM PDT 24
Finished Apr 25 12:29:30 PM PDT 24
Peak memory 193380 kb
Host smart-8fb32f16-f785-4fb8-9f43-7b45996a156c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512458923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2512458923
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2943527313
Short name T241
Test name
Test status
Simulation time 25815575493 ps
CPU time 36.18 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:25:26 PM PDT 24
Peak memory 182792 kb
Host smart-2325c1c8-d19a-4519-9967-1a2a77eee5bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943527313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2943527313
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4009376296
Short name T144
Test name
Test status
Simulation time 290952976348 ps
CPU time 143.9 seconds
Started Apr 25 12:24:27 PM PDT 24
Finished Apr 25 12:26:53 PM PDT 24
Peak memory 182808 kb
Host smart-93fa6961-9dad-4cb3-8420-ec4a65b6c9aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009376296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4009376296
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2403630191
Short name T387
Test name
Test status
Simulation time 365914042463 ps
CPU time 257.17 seconds
Started Apr 25 12:24:07 PM PDT 24
Finished Apr 25 12:28:25 PM PDT 24
Peak memory 182808 kb
Host smart-2f69ad61-84f6-4380-beaa-6c4dc4d0bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403630191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2403630191
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3335704725
Short name T380
Test name
Test status
Simulation time 202481472 ps
CPU time 1.48 seconds
Started Apr 25 12:24:17 PM PDT 24
Finished Apr 25 12:24:19 PM PDT 24
Peak memory 182788 kb
Host smart-3f542acc-aa78-4cb9-ac73-39e91b6e3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335704725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3335704725
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1332969115
Short name T16
Test name
Test status
Simulation time 20400301867 ps
CPU time 163.95 seconds
Started Apr 25 12:24:13 PM PDT 24
Finished Apr 25 12:26:58 PM PDT 24
Peak memory 197456 kb
Host smart-129b69b4-0364-4db8-891f-6879fe0be3c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332969115 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1332969115
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.666295895
Short name T331
Test name
Test status
Simulation time 147881559781 ps
CPU time 658.14 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:35:55 PM PDT 24
Peak memory 194508 kb
Host smart-a187af97-c9b4-4e2c-9fbb-1636b3934b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666295895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.666295895
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1481311151
Short name T225
Test name
Test status
Simulation time 473743039530 ps
CPU time 348.1 seconds
Started Apr 25 12:25:17 PM PDT 24
Finished Apr 25 12:31:05 PM PDT 24
Peak memory 191028 kb
Host smart-a21256e3-36f0-4e6f-8168-a66f0fb31801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481311151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1481311151
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2551975580
Short name T273
Test name
Test status
Simulation time 2328308377 ps
CPU time 5.09 seconds
Started Apr 25 12:25:18 PM PDT 24
Finished Apr 25 12:25:23 PM PDT 24
Peak memory 182916 kb
Host smart-a3ce2db1-edce-410e-8759-cd92fef41a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551975580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2551975580
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1508351041
Short name T188
Test name
Test status
Simulation time 186364089566 ps
CPU time 339.86 seconds
Started Apr 25 12:25:14 PM PDT 24
Finished Apr 25 12:30:54 PM PDT 24
Peak memory 191020 kb
Host smart-e00c209c-7876-4830-af55-43ed3668e519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508351041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1508351041
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3544582110
Short name T306
Test name
Test status
Simulation time 53086735874 ps
CPU time 93.38 seconds
Started Apr 25 12:25:03 PM PDT 24
Finished Apr 25 12:26:37 PM PDT 24
Peak memory 190992 kb
Host smart-538df75e-b8f9-47aa-be9b-dc2cdcc89b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544582110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3544582110
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2900858692
Short name T249
Test name
Test status
Simulation time 313819114416 ps
CPU time 204.97 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:28:22 PM PDT 24
Peak memory 191016 kb
Host smart-958f60de-17bf-4eb3-8cf7-fcfddf8aeb8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900858692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2900858692
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3152104052
Short name T80
Test name
Test status
Simulation time 188401277361 ps
CPU time 73.51 seconds
Started Apr 25 12:23:51 PM PDT 24
Finished Apr 25 12:25:16 PM PDT 24
Peak memory 182796 kb
Host smart-8218626d-22da-482e-97ff-ab6663940ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152104052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3152104052
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2637517393
Short name T150
Test name
Test status
Simulation time 364342649933 ps
CPU time 342.57 seconds
Started Apr 25 12:24:19 PM PDT 24
Finished Apr 25 12:30:03 PM PDT 24
Peak memory 190892 kb
Host smart-01f4da87-360d-44a1-84e4-15b3767a1653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637517393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2637517393
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4156385115
Short name T4
Test name
Test status
Simulation time 165143796672 ps
CPU time 99.66 seconds
Started Apr 25 12:24:13 PM PDT 24
Finished Apr 25 12:25:54 PM PDT 24
Peak memory 182716 kb
Host smart-2c937a30-bd93-4d94-876e-36df4baa39ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156385115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4156385115
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3154721853
Short name T192
Test name
Test status
Simulation time 179964081262 ps
CPU time 84.36 seconds
Started Apr 25 12:25:01 PM PDT 24
Finished Apr 25 12:26:26 PM PDT 24
Peak memory 182820 kb
Host smart-bd24a3f8-e746-4b80-a0b5-7fc8336ca772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154721853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3154721853
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.689231763
Short name T131
Test name
Test status
Simulation time 67564381162 ps
CPU time 91.31 seconds
Started Apr 25 12:25:05 PM PDT 24
Finished Apr 25 12:26:37 PM PDT 24
Peak memory 191000 kb
Host smart-05767c18-7fb2-4b91-b9aa-0244e40ab6c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689231763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.689231763
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3844896318
Short name T25
Test name
Test status
Simulation time 35700576635 ps
CPU time 50.35 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:25:43 PM PDT 24
Peak memory 182804 kb
Host smart-36e36b3a-1d6d-490d-8749-c109b0b52ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844896318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3844896318
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.950681571
Short name T219
Test name
Test status
Simulation time 44510214790 ps
CPU time 64.66 seconds
Started Apr 25 12:24:45 PM PDT 24
Finished Apr 25 12:25:52 PM PDT 24
Peak memory 182808 kb
Host smart-b4b8d464-155b-4293-9702-2af5592ea8b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950681571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.950681571
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3354678647
Short name T443
Test name
Test status
Simulation time 70455422143 ps
CPU time 102.82 seconds
Started Apr 25 12:24:12 PM PDT 24
Finished Apr 25 12:25:56 PM PDT 24
Peak memory 182736 kb
Host smart-26d95390-14b9-421c-aded-830957d3c8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354678647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3354678647
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1050190018
Short name T280
Test name
Test status
Simulation time 19368600443 ps
CPU time 8.56 seconds
Started Apr 25 12:24:11 PM PDT 24
Finished Apr 25 12:24:22 PM PDT 24
Peak memory 190968 kb
Host smart-5931bfeb-275f-4f4f-b509-fb54d2dd9cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050190018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1050190018
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1048734147
Short name T374
Test name
Test status
Simulation time 28986493206 ps
CPU time 13.88 seconds
Started Apr 25 12:24:25 PM PDT 24
Finished Apr 25 12:24:40 PM PDT 24
Peak memory 182816 kb
Host smart-3e7f5d9c-ca54-460d-a8e7-ca663b04178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048734147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1048734147
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.1984679324
Short name T30
Test name
Test status
Simulation time 98202677218 ps
CPU time 60.11 seconds
Started Apr 25 12:25:18 PM PDT 24
Finished Apr 25 12:26:20 PM PDT 24
Peak memory 182636 kb
Host smart-11641639-3f97-4f5a-88ed-7a034a83e7ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984679324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1984679324
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1097432898
Short name T157
Test name
Test status
Simulation time 436495666923 ps
CPU time 467.71 seconds
Started Apr 25 12:25:11 PM PDT 24
Finished Apr 25 12:32:59 PM PDT 24
Peak memory 191020 kb
Host smart-17461a4a-7fde-4383-83c6-430e93aae7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097432898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1097432898
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1544936969
Short name T423
Test name
Test status
Simulation time 1158715048491 ps
CPU time 595.61 seconds
Started Apr 25 12:24:29 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 182820 kb
Host smart-a11e54a5-182b-4a74-be41-e8862392d105
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544936969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1544936969
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.4041687470
Short name T368
Test name
Test status
Simulation time 270990077539 ps
CPU time 111.74 seconds
Started Apr 25 12:24:18 PM PDT 24
Finished Apr 25 12:26:10 PM PDT 24
Peak memory 182756 kb
Host smart-b4c9752b-ec43-451f-a1f6-56599bff0ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041687470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.4041687470
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2714449218
Short name T433
Test name
Test status
Simulation time 59372502061 ps
CPU time 272.96 seconds
Started Apr 25 12:23:53 PM PDT 24
Finished Apr 25 12:28:27 PM PDT 24
Peak memory 190852 kb
Host smart-0c280600-499b-41fb-8144-ccf24edbd31e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714449218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2714449218
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2241347292
Short name T365
Test name
Test status
Simulation time 4387696213 ps
CPU time 7.6 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:25:01 PM PDT 24
Peak memory 190980 kb
Host smart-20842b3b-5f3e-4368-a6d5-ce6fe575e2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241347292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2241347292
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.3078133604
Short name T244
Test name
Test status
Simulation time 434846998437 ps
CPU time 213.57 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:28:25 PM PDT 24
Peak memory 190996 kb
Host smart-00811c94-fbb5-4061-a143-0bd241c7ad9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078133604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3078133604
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.831248808
Short name T152
Test name
Test status
Simulation time 1092877734231 ps
CPU time 406.09 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:31:38 PM PDT 24
Peak memory 190980 kb
Host smart-a4dd5975-d2ab-4152-86ad-ebeb0e6a45a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831248808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.831248808
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4168297836
Short name T204
Test name
Test status
Simulation time 383892179547 ps
CPU time 321.09 seconds
Started Apr 25 12:25:13 PM PDT 24
Finished Apr 25 12:30:35 PM PDT 24
Peak memory 191020 kb
Host smart-c7ea75df-8d55-4345-9658-a1dca34040ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168297836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4168297836
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3821660016
Short name T299
Test name
Test status
Simulation time 105353189276 ps
CPU time 307.33 seconds
Started Apr 25 12:25:17 PM PDT 24
Finished Apr 25 12:30:25 PM PDT 24
Peak memory 194300 kb
Host smart-042ce2da-eec4-4a19-a298-a949fdd5e7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821660016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3821660016
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2082353795
Short name T285
Test name
Test status
Simulation time 80924611313 ps
CPU time 444.28 seconds
Started Apr 25 12:24:52 PM PDT 24
Finished Apr 25 12:32:18 PM PDT 24
Peak memory 191012 kb
Host smart-4539a9d3-533e-4a1a-8b8f-63284dd9f1f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082353795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2082353795
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2736536391
Short name T103
Test name
Test status
Simulation time 63257273880 ps
CPU time 537.5 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:33:51 PM PDT 24
Peak memory 190980 kb
Host smart-832258b6-6a76-4e5f-9a96-5463af36bc30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736536391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2736536391
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.693971622
Short name T26
Test name
Test status
Simulation time 54043588606 ps
CPU time 141.85 seconds
Started Apr 25 12:24:45 PM PDT 24
Finished Apr 25 12:27:08 PM PDT 24
Peak memory 190996 kb
Host smart-d015c71d-a353-41f2-b246-2818245ca53b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693971622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.693971622
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3915355732
Short name T122
Test name
Test status
Simulation time 1460996673696 ps
CPU time 475.72 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:32:45 PM PDT 24
Peak memory 191004 kb
Host smart-48228e77-f17e-4ef5-8355-04e225ea80a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915355732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3915355732
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.209071819
Short name T342
Test name
Test status
Simulation time 103663824104 ps
CPU time 54.74 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:25:44 PM PDT 24
Peak memory 182780 kb
Host smart-b157e7bd-97e7-4281-b11a-affad0bbb8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209071819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.209071819
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1937336808
Short name T202
Test name
Test status
Simulation time 36067102357 ps
CPU time 61.71 seconds
Started Apr 25 12:24:10 PM PDT 24
Finished Apr 25 12:25:13 PM PDT 24
Peak memory 182740 kb
Host smart-a7271ce5-44c8-422a-bf4f-ebd1dcace2ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937336808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1937336808
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1485691147
Short name T369
Test name
Test status
Simulation time 369704433956 ps
CPU time 236.89 seconds
Started Apr 25 12:24:29 PM PDT 24
Finished Apr 25 12:28:28 PM PDT 24
Peak memory 182816 kb
Host smart-fb75f238-19dc-49a6-8964-8a00bb469d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485691147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1485691147
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.4196715278
Short name T143
Test name
Test status
Simulation time 289103862157 ps
CPU time 492.43 seconds
Started Apr 25 12:24:06 PM PDT 24
Finished Apr 25 12:32:19 PM PDT 24
Peak memory 190996 kb
Host smart-58b9099f-0c43-4321-a2fb-ef0669aef228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196715278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4196715278
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2184779224
Short name T326
Test name
Test status
Simulation time 46493771149 ps
CPU time 88.37 seconds
Started Apr 25 12:24:19 PM PDT 24
Finished Apr 25 12:25:48 PM PDT 24
Peak memory 190980 kb
Host smart-4152a44a-6181-4521-b1bb-0112c5a68a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184779224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2184779224
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.2232043903
Short name T250
Test name
Test status
Simulation time 58329579063 ps
CPU time 126.31 seconds
Started Apr 25 12:25:04 PM PDT 24
Finished Apr 25 12:27:11 PM PDT 24
Peak memory 193024 kb
Host smart-84304ef2-5fb8-4b7d-a5b4-7ee7040fbbe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232043903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2232043903
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2448922939
Short name T315
Test name
Test status
Simulation time 452517015403 ps
CPU time 290.68 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:29:46 PM PDT 24
Peak memory 191016 kb
Host smart-d26cbdd4-b522-4abc-af77-886b70480409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448922939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2448922939
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.605309733
Short name T312
Test name
Test status
Simulation time 185597870789 ps
CPU time 1081.41 seconds
Started Apr 25 12:25:21 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 182768 kb
Host smart-cfd08e59-eb1a-4330-b8a0-7c0fd7ed52aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605309733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.605309733
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.4170892884
Short name T304
Test name
Test status
Simulation time 130307249888 ps
CPU time 896.87 seconds
Started Apr 25 12:25:10 PM PDT 24
Finished Apr 25 12:40:08 PM PDT 24
Peak memory 191000 kb
Host smart-7ad59704-7df6-4f69-84b4-cc1ab622b084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170892884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.4170892884
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2706675426
Short name T359
Test name
Test status
Simulation time 299746708781 ps
CPU time 306.28 seconds
Started Apr 25 12:25:11 PM PDT 24
Finished Apr 25 12:30:18 PM PDT 24
Peak memory 182824 kb
Host smart-fa64e766-8ed1-4612-9de9-30e5398ca164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706675426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2706675426
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.815087870
Short name T266
Test name
Test status
Simulation time 505612627205 ps
CPU time 496.36 seconds
Started Apr 25 12:25:03 PM PDT 24
Finished Apr 25 12:33:20 PM PDT 24
Peak memory 191004 kb
Host smart-6cab699e-b248-4935-8553-318b5d4fd2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815087870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.815087870
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3443897284
Short name T139
Test name
Test status
Simulation time 370183937218 ps
CPU time 554.68 seconds
Started Apr 25 12:24:49 PM PDT 24
Finished Apr 25 12:34:06 PM PDT 24
Peak memory 190956 kb
Host smart-1412d668-c7a6-4bea-8d84-6b85bb2ab662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443897284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3443897284
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3172807638
Short name T210
Test name
Test status
Simulation time 222379858050 ps
CPU time 109.35 seconds
Started Apr 25 12:25:10 PM PDT 24
Finished Apr 25 12:27:00 PM PDT 24
Peak memory 191020 kb
Host smart-db26e25d-1fd7-4849-8b8e-f68938754186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172807638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3172807638
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.130225230
Short name T209
Test name
Test status
Simulation time 430815831636 ps
CPU time 749.65 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:36:55 PM PDT 24
Peak memory 182816 kb
Host smart-7caaeadc-9721-4e06-a682-f3e11478ead0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130225230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.130225230
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.897342534
Short name T370
Test name
Test status
Simulation time 340297883357 ps
CPU time 134.52 seconds
Started Apr 25 12:24:13 PM PDT 24
Finished Apr 25 12:26:29 PM PDT 24
Peak memory 182756 kb
Host smart-2b136a4f-d910-4fcc-9846-c5e167d5e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897342534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.897342534
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3468648515
Short name T381
Test name
Test status
Simulation time 337960002 ps
CPU time 2.84 seconds
Started Apr 25 12:24:13 PM PDT 24
Finished Apr 25 12:24:18 PM PDT 24
Peak memory 190928 kb
Host smart-2b6c63ca-9761-410d-a210-0275432f0e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468648515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3468648515
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3485408169
Short name T328
Test name
Test status
Simulation time 1471630667913 ps
CPU time 607.29 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:34:59 PM PDT 24
Peak memory 190988 kb
Host smart-007b8573-978c-4dfe-87d5-08675b3ec5f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485408169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3485408169
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3648012826
Short name T163
Test name
Test status
Simulation time 139397133979 ps
CPU time 127.27 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:27:03 PM PDT 24
Peak memory 190980 kb
Host smart-ab96d327-b1f6-4d01-acb5-f3f6e378c47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648012826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3648012826
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1771181177
Short name T27
Test name
Test status
Simulation time 392885032991 ps
CPU time 1908.71 seconds
Started Apr 25 12:25:12 PM PDT 24
Finished Apr 25 12:57:02 PM PDT 24
Peak memory 191016 kb
Host smart-bcaef0e1-e10f-4312-a3b8-084182a86a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771181177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1771181177
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2697945168
Short name T137
Test name
Test status
Simulation time 303326111300 ps
CPU time 475.68 seconds
Started Apr 25 12:25:01 PM PDT 24
Finished Apr 25 12:32:58 PM PDT 24
Peak memory 191016 kb
Host smart-f4254c62-c332-4e71-9ea5-2e86f24ba827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697945168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2697945168
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3783845388
Short name T215
Test name
Test status
Simulation time 132623818063 ps
CPU time 1675.52 seconds
Started Apr 25 12:25:10 PM PDT 24
Finished Apr 25 12:53:06 PM PDT 24
Peak memory 191016 kb
Host smart-4001bb1c-c2d7-4bdf-9c8c-ab8ad2df6032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783845388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3783845388
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1196074459
Short name T240
Test name
Test status
Simulation time 54289387982 ps
CPU time 89.11 seconds
Started Apr 25 12:25:14 PM PDT 24
Finished Apr 25 12:26:44 PM PDT 24
Peak memory 194976 kb
Host smart-27c153ea-d37b-4fe8-82c0-cae3f62a958f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196074459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1196074459
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4034769134
Short name T274
Test name
Test status
Simulation time 1749557289704 ps
CPU time 699.44 seconds
Started Apr 25 12:24:29 PM PDT 24
Finished Apr 25 12:36:10 PM PDT 24
Peak memory 182800 kb
Host smart-3ac0d8c8-4ae3-4b6a-82c4-2bff4388d745
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034769134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4034769134
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1604019779
Short name T384
Test name
Test status
Simulation time 286958057455 ps
CPU time 220.53 seconds
Started Apr 25 12:24:23 PM PDT 24
Finished Apr 25 12:28:05 PM PDT 24
Peak memory 182784 kb
Host smart-cf9b9429-a560-4240-a8c2-b0b105896181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604019779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1604019779
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1254245722
Short name T123
Test name
Test status
Simulation time 428403707239 ps
CPU time 1056.65 seconds
Started Apr 25 12:24:16 PM PDT 24
Finished Apr 25 12:41:54 PM PDT 24
Peak memory 191008 kb
Host smart-d635247c-56d1-4ec8-b680-bfde9ac1351c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254245722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1254245722
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3175195233
Short name T1
Test name
Test status
Simulation time 18222107058 ps
CPU time 38.17 seconds
Started Apr 25 12:23:51 PM PDT 24
Finished Apr 25 12:24:30 PM PDT 24
Peak memory 191004 kb
Host smart-e667e2e4-87a4-425f-9437-42f59df1a4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175195233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3175195233
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1466932656
Short name T135
Test name
Test status
Simulation time 145980841163 ps
CPU time 250.83 seconds
Started Apr 25 12:24:19 PM PDT 24
Finished Apr 25 12:28:31 PM PDT 24
Peak memory 190968 kb
Host smart-af9917c7-2301-4c4d-aab4-0fcb7530e1f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466932656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1466932656
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2511382363
Short name T38
Test name
Test status
Simulation time 35322548402 ps
CPU time 337.13 seconds
Started Apr 25 12:24:35 PM PDT 24
Finished Apr 25 12:30:14 PM PDT 24
Peak memory 197428 kb
Host smart-3eb9e857-d173-43fc-9ded-45384078a33a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511382363 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.2511382363
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.4191479249
Short name T329
Test name
Test status
Simulation time 154977043520 ps
CPU time 1117.36 seconds
Started Apr 25 12:24:57 PM PDT 24
Finished Apr 25 12:43:36 PM PDT 24
Peak memory 191000 kb
Host smart-a1399422-3cf0-45bf-9b7b-5480600fa28c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191479249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4191479249
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3873097152
Short name T333
Test name
Test status
Simulation time 21738212338 ps
CPU time 16.85 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:25:12 PM PDT 24
Peak memory 182780 kb
Host smart-74eaed5b-ac23-453e-9495-d8d10b9590f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873097152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3873097152
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2115145629
Short name T197
Test name
Test status
Simulation time 104879690807 ps
CPU time 152.06 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:27:22 PM PDT 24
Peak memory 190988 kb
Host smart-b625cc69-5628-4e85-9509-1c3fb436c982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115145629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2115145629
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2762483392
Short name T284
Test name
Test status
Simulation time 506984240586 ps
CPU time 201.98 seconds
Started Apr 25 12:24:59 PM PDT 24
Finished Apr 25 12:28:22 PM PDT 24
Peak memory 191032 kb
Host smart-db21b1af-84eb-4b92-8d88-b5f6108de487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762483392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2762483392
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3422985422
Short name T133
Test name
Test status
Simulation time 455687788607 ps
CPU time 277.27 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:29:28 PM PDT 24
Peak memory 190988 kb
Host smart-ef8c4fdf-11c7-4782-a212-966b96ff3263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422985422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3422985422
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1244116573
Short name T186
Test name
Test status
Simulation time 192037578051 ps
CPU time 1158.19 seconds
Started Apr 25 12:25:12 PM PDT 24
Finished Apr 25 12:44:32 PM PDT 24
Peak memory 194644 kb
Host smart-c6e96dcb-90a4-41c2-9dca-9e9598ea0230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244116573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1244116573
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1635632411
Short name T325
Test name
Test status
Simulation time 187297680040 ps
CPU time 85.81 seconds
Started Apr 25 12:25:09 PM PDT 24
Finished Apr 25 12:26:35 PM PDT 24
Peak memory 182856 kb
Host smart-1b90f88a-ef9c-4c8e-8d6e-c1e30b9e5bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635632411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1635632411
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3904894277
Short name T296
Test name
Test status
Simulation time 85360008605 ps
CPU time 388.45 seconds
Started Apr 25 12:25:13 PM PDT 24
Finished Apr 25 12:31:43 PM PDT 24
Peak memory 191116 kb
Host smart-aee6aafa-484a-4b34-98af-32ed40e7a188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904894277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3904894277
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3847851342
Short name T200
Test name
Test status
Simulation time 218160333778 ps
CPU time 111.6 seconds
Started Apr 25 12:24:30 PM PDT 24
Finished Apr 25 12:26:23 PM PDT 24
Peak memory 182804 kb
Host smart-6bf9551d-00ed-4d8f-9ca1-39818e169845
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847851342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3847851342
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.821450390
Short name T421
Test name
Test status
Simulation time 71249505996 ps
CPU time 59.88 seconds
Started Apr 25 12:24:37 PM PDT 24
Finished Apr 25 12:25:39 PM PDT 24
Peak memory 182808 kb
Host smart-4d25bea4-7445-470d-a3c2-eb272a1d5cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821450390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.821450390
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.4035586523
Short name T104
Test name
Test status
Simulation time 118270864664 ps
CPU time 198.29 seconds
Started Apr 25 12:24:03 PM PDT 24
Finished Apr 25 12:27:22 PM PDT 24
Peak memory 182796 kb
Host smart-a1a25b95-6a0b-4b07-9e45-554511f4e4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035586523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.4035586523
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1744025895
Short name T20
Test name
Test status
Simulation time 59176367 ps
CPU time 0.79 seconds
Started Apr 25 12:24:04 PM PDT 24
Finished Apr 25 12:24:06 PM PDT 24
Peak memory 213188 kb
Host smart-1c512e43-5837-4aae-8867-1d90e63c6148
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744025895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1744025895
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4086506114
Short name T383
Test name
Test status
Simulation time 176713192 ps
CPU time 0.69 seconds
Started Apr 25 12:23:53 PM PDT 24
Finished Apr 25 12:23:55 PM PDT 24
Peak memory 182296 kb
Host smart-6c810890-2ab4-4d6f-9f47-a18cd0f231d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086506114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4086506114
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2447278389
Short name T413
Test name
Test status
Simulation time 80216482263 ps
CPU time 143.44 seconds
Started Apr 25 12:24:25 PM PDT 24
Finished Apr 25 12:26:50 PM PDT 24
Peak memory 182804 kb
Host smart-9f6c21ee-20a8-4a78-a51b-34f008aa41eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447278389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2447278389
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3273876189
Short name T362
Test name
Test status
Simulation time 341630397646 ps
CPU time 278.73 seconds
Started Apr 25 12:24:34 PM PDT 24
Finished Apr 25 12:29:14 PM PDT 24
Peak memory 182808 kb
Host smart-586fc042-2cfa-466a-b10a-fe960299d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273876189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3273876189
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3781253849
Short name T162
Test name
Test status
Simulation time 2413154927643 ps
CPU time 361.77 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:30:51 PM PDT 24
Peak memory 190992 kb
Host smart-edc049ed-3760-415c-9148-3134baa3eade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781253849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3781253849
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1369792452
Short name T364
Test name
Test status
Simulation time 640417939 ps
CPU time 1.01 seconds
Started Apr 25 12:24:11 PM PDT 24
Finished Apr 25 12:24:13 PM PDT 24
Peak memory 192888 kb
Host smart-8d68626b-e425-43b6-86ce-d6b05174e9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369792452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1369792452
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1467738551
Short name T159
Test name
Test status
Simulation time 749434361029 ps
CPU time 220.28 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:28:18 PM PDT 24
Peak memory 182804 kb
Host smart-6f02ddd7-f348-4137-9a83-b2401a9d3a0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467738551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1467738551
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2648721756
Short name T391
Test name
Test status
Simulation time 278199982867 ps
CPU time 156.19 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:27:06 PM PDT 24
Peak memory 182936 kb
Host smart-7015fc61-0d85-4d92-b7be-54c3b0ff5c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648721756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2648721756
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2703591059
Short name T404
Test name
Test status
Simulation time 30550265334 ps
CPU time 51.66 seconds
Started Apr 25 12:24:35 PM PDT 24
Finished Apr 25 12:25:27 PM PDT 24
Peak memory 182776 kb
Host smart-17dafba9-5bc1-44a2-99d0-7b749915b3ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703591059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2703591059
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1399568652
Short name T140
Test name
Test status
Simulation time 77258506339 ps
CPU time 327.58 seconds
Started Apr 25 12:23:57 PM PDT 24
Finished Apr 25 12:29:35 PM PDT 24
Peak memory 190988 kb
Host smart-6b4a4340-d497-4aa7-986c-d2e7ddc6e2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399568652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1399568652
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1297308007
Short name T405
Test name
Test status
Simulation time 35394664091 ps
CPU time 19.77 seconds
Started Apr 25 12:24:37 PM PDT 24
Finished Apr 25 12:24:58 PM PDT 24
Peak memory 182812 kb
Host smart-9e08afe9-2d88-4d38-88d1-72daa6af527d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297308007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1297308007
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.627072310
Short name T397
Test name
Test status
Simulation time 206059367016 ps
CPU time 309.22 seconds
Started Apr 25 12:24:07 PM PDT 24
Finished Apr 25 12:29:17 PM PDT 24
Peak memory 182812 kb
Host smart-04771dc3-8715-488e-a5de-76f388618105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627072310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.627072310
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3313762250
Short name T278
Test name
Test status
Simulation time 333088829535 ps
CPU time 286.74 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:29:12 PM PDT 24
Peak memory 190976 kb
Host smart-ae5792c2-e484-4643-ba67-f2d716d33165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313762250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3313762250
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.652987120
Short name T417
Test name
Test status
Simulation time 8313202381 ps
CPU time 13.22 seconds
Started Apr 25 12:24:45 PM PDT 24
Finished Apr 25 12:25:00 PM PDT 24
Peak memory 182896 kb
Host smart-5018ad40-737e-4b52-9909-cd5c4ac7146d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652987120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.652987120
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3661843653
Short name T256
Test name
Test status
Simulation time 22499183602 ps
CPU time 24.63 seconds
Started Apr 25 12:24:49 PM PDT 24
Finished Apr 25 12:25:16 PM PDT 24
Peak memory 182792 kb
Host smart-4685bf89-fd6b-4624-b220-08e516051d41
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661843653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3661843653
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3581222132
Short name T392
Test name
Test status
Simulation time 103380525476 ps
CPU time 173.23 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:27:19 PM PDT 24
Peak memory 182772 kb
Host smart-746ac71a-2924-4ec9-af34-593a16a513f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581222132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3581222132
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1721081132
Short name T337
Test name
Test status
Simulation time 63665285540 ps
CPU time 100.99 seconds
Started Apr 25 12:24:25 PM PDT 24
Finished Apr 25 12:26:08 PM PDT 24
Peak memory 190988 kb
Host smart-cac4c2af-69d3-4e45-a93a-a3905df4f9c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721081132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1721081132
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3587904949
Short name T14
Test name
Test status
Simulation time 54775048197 ps
CPU time 420.69 seconds
Started Apr 25 12:24:03 PM PDT 24
Finished Apr 25 12:31:04 PM PDT 24
Peak memory 194780 kb
Host smart-808876d9-bfd1-465c-85b1-bb72f4689727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587904949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3587904949
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2278088630
Short name T15
Test name
Test status
Simulation time 148726696051 ps
CPU time 1292.49 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:46:21 PM PDT 24
Peak memory 213472 kb
Host smart-0cde05e7-69e4-451b-a781-72880e7f99b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278088630 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2278088630
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1944239143
Short name T214
Test name
Test status
Simulation time 731244053161 ps
CPU time 439.61 seconds
Started Apr 25 12:24:20 PM PDT 24
Finished Apr 25 12:31:41 PM PDT 24
Peak memory 182548 kb
Host smart-afe69cf2-0d72-49a7-bfab-433afff0bce7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944239143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1944239143
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.138748027
Short name T388
Test name
Test status
Simulation time 215559118279 ps
CPU time 78.36 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:25:43 PM PDT 24
Peak memory 182808 kb
Host smart-5d5a12e5-75eb-415a-b6ed-427226d58617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138748027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.138748027
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2250577916
Short name T308
Test name
Test status
Simulation time 95234293547 ps
CPU time 235.17 seconds
Started Apr 25 12:24:11 PM PDT 24
Finished Apr 25 12:28:08 PM PDT 24
Peak memory 190980 kb
Host smart-ae0e8a74-720f-48a9-8d1e-914b88fc57e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250577916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2250577916
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1751822690
Short name T378
Test name
Test status
Simulation time 18664289 ps
CPU time 0.53 seconds
Started Apr 25 12:24:15 PM PDT 24
Finished Apr 25 12:24:17 PM PDT 24
Peak memory 182608 kb
Host smart-467bbd70-afb1-4193-a221-2125ecafd5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751822690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1751822690
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.53074808
Short name T371
Test name
Test status
Simulation time 500161831757 ps
CPU time 418.85 seconds
Started Apr 25 12:24:34 PM PDT 24
Finished Apr 25 12:31:33 PM PDT 24
Peak memory 191000 kb
Host smart-96cfc35c-36d0-4904-83a7-71e7a228a606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53074808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.53074808
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3787935123
Short name T344
Test name
Test status
Simulation time 4458056504 ps
CPU time 2.4 seconds
Started Apr 25 12:24:10 PM PDT 24
Finished Apr 25 12:24:14 PM PDT 24
Peak memory 182816 kb
Host smart-c2c3e109-55f2-4d6a-8ce3-8914355484bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787935123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3787935123
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2538674362
Short name T430
Test name
Test status
Simulation time 39810110172 ps
CPU time 63.64 seconds
Started Apr 25 12:24:32 PM PDT 24
Finished Apr 25 12:25:36 PM PDT 24
Peak memory 182832 kb
Host smart-98655f33-f746-49ef-8dc0-476b3f4bbd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538674362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2538674362
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3116897903
Short name T292
Test name
Test status
Simulation time 567252355269 ps
CPU time 398.65 seconds
Started Apr 25 12:24:09 PM PDT 24
Finished Apr 25 12:30:48 PM PDT 24
Peak memory 191004 kb
Host smart-c6bbe518-ca73-464d-b00a-081e036c9ba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116897903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3116897903
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.486185553
Short name T324
Test name
Test status
Simulation time 13868095765 ps
CPU time 23.45 seconds
Started Apr 25 12:24:00 PM PDT 24
Finished Apr 25 12:24:24 PM PDT 24
Peak memory 181984 kb
Host smart-cc9cd571-ab8d-488a-96e6-54401cb45b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486185553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.486185553
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1741204854
Short name T230
Test name
Test status
Simulation time 91451832550 ps
CPU time 153.73 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:27:24 PM PDT 24
Peak memory 182796 kb
Host smart-20c8171a-6851-4213-bd1f-a8e1343ae009
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741204854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1741204854
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3955945994
Short name T444
Test name
Test status
Simulation time 99056774314 ps
CPU time 131.95 seconds
Started Apr 25 12:24:30 PM PDT 24
Finished Apr 25 12:26:43 PM PDT 24
Peak memory 182800 kb
Host smart-9560efb5-82ac-4ee2-89cf-5fc22425870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955945994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3955945994
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3950596524
Short name T138
Test name
Test status
Simulation time 309177006681 ps
CPU time 460.33 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:32:05 PM PDT 24
Peak memory 190992 kb
Host smart-b34a71f9-8ee0-4b99-a3ee-da9dcd32abae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950596524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3950596524
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3591559128
Short name T267
Test name
Test status
Simulation time 150492478345 ps
CPU time 60.61 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:25:30 PM PDT 24
Peak memory 194044 kb
Host smart-764e07f5-f2ed-464f-a6af-7ede06f978a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591559128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3591559128
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.157976936
Short name T305
Test name
Test status
Simulation time 9238356107 ps
CPU time 9.48 seconds
Started Apr 25 12:24:09 PM PDT 24
Finished Apr 25 12:24:20 PM PDT 24
Peak memory 182804 kb
Host smart-8db6ece9-3307-4262-b33d-7a717a6d7a05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157976936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.157976936
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1468007826
Short name T422
Test name
Test status
Simulation time 139744358233 ps
CPU time 56.05 seconds
Started Apr 25 12:24:27 PM PDT 24
Finished Apr 25 12:25:25 PM PDT 24
Peak memory 182804 kb
Host smart-919bf448-615f-4ee7-8c8e-4319d76febbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468007826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1468007826
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.4184035946
Short name T44
Test name
Test status
Simulation time 160773079093 ps
CPU time 79.9 seconds
Started Apr 25 12:24:37 PM PDT 24
Finished Apr 25 12:25:58 PM PDT 24
Peak memory 190980 kb
Host smart-01b383f9-fd00-4e61-b924-d20af884358c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184035946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.4184035946
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3628625482
Short name T439
Test name
Test status
Simulation time 5455337953 ps
CPU time 4.85 seconds
Started Apr 25 12:24:08 PM PDT 24
Finished Apr 25 12:24:14 PM PDT 24
Peak memory 191596 kb
Host smart-ba3e5beb-470a-4054-a3be-b7c622530646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628625482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3628625482
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1575678123
Short name T276
Test name
Test status
Simulation time 169825873423 ps
CPU time 152.41 seconds
Started Apr 25 12:24:25 PM PDT 24
Finished Apr 25 12:26:58 PM PDT 24
Peak memory 182800 kb
Host smart-fc4d2c49-9e5a-4800-abaa-a02bc3359107
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575678123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1575678123
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.944918667
Short name T390
Test name
Test status
Simulation time 120579140160 ps
CPU time 112.36 seconds
Started Apr 25 12:24:44 PM PDT 24
Finished Apr 25 12:26:38 PM PDT 24
Peak memory 182916 kb
Host smart-1f81a5d6-de58-49f1-ba21-5f0ce4758e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944918667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.944918667
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.472195139
Short name T153
Test name
Test status
Simulation time 30973327029 ps
CPU time 29.2 seconds
Started Apr 25 12:24:16 PM PDT 24
Finished Apr 25 12:24:47 PM PDT 24
Peak memory 191608 kb
Host smart-1d8b9105-6bb8-4b20-ade3-9ce8e7284ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472195139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.472195139
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.79447524
Short name T132
Test name
Test status
Simulation time 1886235465040 ps
CPU time 2185.24 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 01:01:14 PM PDT 24
Peak memory 190992 kb
Host smart-96d9c2f3-6469-469e-884b-03c34f1d0b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79447524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.79447524
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3611733318
Short name T253
Test name
Test status
Simulation time 690718001092 ps
CPU time 319.06 seconds
Started Apr 25 12:24:17 PM PDT 24
Finished Apr 25 12:29:37 PM PDT 24
Peak memory 182808 kb
Host smart-11d0bfa7-a876-47de-8d6f-49d97ddbb636
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611733318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3611733318
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.443173966
Short name T385
Test name
Test status
Simulation time 248237764592 ps
CPU time 168.1 seconds
Started Apr 25 12:24:23 PM PDT 24
Finished Apr 25 12:27:12 PM PDT 24
Peak memory 182812 kb
Host smart-d052e6bf-9ee5-49f0-bae7-dd2efa9fe6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443173966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.443173966
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.502263813
Short name T398
Test name
Test status
Simulation time 402654367306 ps
CPU time 306.04 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:29:35 PM PDT 24
Peak memory 190940 kb
Host smart-7171318f-acc3-4fc2-809e-4c1e79cc6987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502263813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
502263813
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1019748243
Short name T395
Test name
Test status
Simulation time 67437074215 ps
CPU time 61.45 seconds
Started Apr 25 12:23:52 PM PDT 24
Finished Apr 25 12:24:54 PM PDT 24
Peak memory 182808 kb
Host smart-7babc8d4-d40b-459b-b157-8f0ded4f118d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019748243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1019748243
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.908973915
Short name T121
Test name
Test status
Simulation time 154182511352 ps
CPU time 149.54 seconds
Started Apr 25 12:24:09 PM PDT 24
Finished Apr 25 12:26:40 PM PDT 24
Peak memory 191004 kb
Host smart-cf886350-81e4-4acb-9d0e-f9e0f6841d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908973915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.908973915
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.393400607
Short name T410
Test name
Test status
Simulation time 245445745 ps
CPU time 0.88 seconds
Started Apr 25 12:24:02 PM PDT 24
Finished Apr 25 12:24:03 PM PDT 24
Peak memory 182520 kb
Host smart-e014fc2f-e469-4d4f-900f-9d786363e25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393400607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.393400607
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1262127663
Short name T21
Test name
Test status
Simulation time 118235531 ps
CPU time 0.69 seconds
Started Apr 25 12:24:26 PM PDT 24
Finished Apr 25 12:24:28 PM PDT 24
Peak memory 213112 kb
Host smart-a59b095c-54a6-4aa5-9b6d-2c0b9fe14864
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262127663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1262127663
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.547570752
Short name T6
Test name
Test status
Simulation time 201051405 ps
CPU time 0.57 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:24:25 PM PDT 24
Peak memory 182644 kb
Host smart-89da8601-472c-4639-ae71-f500c18acd24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547570752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.547570752
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2474433130
Short name T310
Test name
Test status
Simulation time 2080897049146 ps
CPU time 1027.87 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:41:38 PM PDT 24
Peak memory 182736 kb
Host smart-78a3890f-b013-4079-aa60-7bb6c2250483
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474433130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2474433130
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2838444463
Short name T396
Test name
Test status
Simulation time 145149923740 ps
CPU time 233.26 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:28:19 PM PDT 24
Peak memory 182796 kb
Host smart-216f757f-c6a0-40fc-946a-765e80a30ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838444463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2838444463
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3789472469
Short name T394
Test name
Test status
Simulation time 477820101190 ps
CPU time 191.56 seconds
Started Apr 25 12:24:25 PM PDT 24
Finished Apr 25 12:27:38 PM PDT 24
Peak memory 190988 kb
Host smart-165f9ed6-f1eb-4e51-8783-895620e4aa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789472469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3789472469
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2765280825
Short name T415
Test name
Test status
Simulation time 48461812007 ps
CPU time 88 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:26:05 PM PDT 24
Peak memory 182896 kb
Host smart-25bfa007-eda6-4ceb-a1f6-ecb8159a7951
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765280825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2765280825
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1732124635
Short name T63
Test name
Test status
Simulation time 567417438834 ps
CPU time 241.25 seconds
Started Apr 25 12:24:37 PM PDT 24
Finished Apr 25 12:28:40 PM PDT 24
Peak memory 182832 kb
Host smart-a31c3bed-9eaf-4ceb-9d2c-b5989a9802d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732124635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1732124635
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2465355995
Short name T379
Test name
Test status
Simulation time 1619033363 ps
CPU time 0.95 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:24:38 PM PDT 24
Peak memory 192440 kb
Host smart-0fabf7b7-e239-453e-8879-ff8207115722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465355995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2465355995
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2666053456
Short name T113
Test name
Test status
Simulation time 1867696863925 ps
CPU time 575.15 seconds
Started Apr 25 12:24:29 PM PDT 24
Finished Apr 25 12:34:05 PM PDT 24
Peak memory 190768 kb
Host smart-4b9c2a26-046c-43e7-a1d6-432c15265bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666053456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2666053456
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3499023353
Short name T124
Test name
Test status
Simulation time 504716742557 ps
CPU time 190.91 seconds
Started Apr 25 12:24:37 PM PDT 24
Finished Apr 25 12:27:49 PM PDT 24
Peak memory 182808 kb
Host smart-173e3680-06da-40e8-9b83-822a48d1130d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499023353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3499023353
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3221889358
Short name T376
Test name
Test status
Simulation time 247974821469 ps
CPU time 195.62 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:27:41 PM PDT 24
Peak memory 182848 kb
Host smart-ec6f9dec-42c3-48f6-9958-bf2003b41bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221889358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3221889358
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1033242090
Short name T289
Test name
Test status
Simulation time 1039964255024 ps
CPU time 884.65 seconds
Started Apr 25 12:24:10 PM PDT 24
Finished Apr 25 12:38:56 PM PDT 24
Peak memory 191000 kb
Host smart-2c05271f-9162-4d68-82d6-095bbab84c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033242090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1033242090
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3815506212
Short name T77
Test name
Test status
Simulation time 116969100128 ps
CPU time 339.74 seconds
Started Apr 25 12:24:21 PM PDT 24
Finished Apr 25 12:30:02 PM PDT 24
Peak memory 190924 kb
Host smart-10ca9cee-b0a7-4cee-9c28-a9b4e4e3d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815506212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3815506212
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.252591759
Short name T161
Test name
Test status
Simulation time 106217693057 ps
CPU time 623.82 seconds
Started Apr 25 12:24:37 PM PDT 24
Finished Apr 25 12:35:02 PM PDT 24
Peak memory 194804 kb
Host smart-10694ff0-bfb4-4b75-a52c-283988695360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252591759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
252591759
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2588118560
Short name T46
Test name
Test status
Simulation time 3628922449147 ps
CPU time 831.71 seconds
Started Apr 25 12:24:54 PM PDT 24
Finished Apr 25 12:38:48 PM PDT 24
Peak memory 182812 kb
Host smart-f9563f02-af10-469b-a7d9-c2737488e8c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588118560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2588118560
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3398385564
Short name T382
Test name
Test status
Simulation time 194379326380 ps
CPU time 156.08 seconds
Started Apr 25 12:24:34 PM PDT 24
Finished Apr 25 12:27:11 PM PDT 24
Peak memory 182692 kb
Host smart-e94a21f3-1a62-491a-8089-d954a14c8511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398385564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3398385564
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1479011507
Short name T321
Test name
Test status
Simulation time 233951117267 ps
CPU time 211.39 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:28:01 PM PDT 24
Peak memory 182776 kb
Host smart-d1ec149c-e242-4222-933c-bd9336fcc172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479011507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1479011507
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.303202003
Short name T10
Test name
Test status
Simulation time 172813624686 ps
CPU time 87.49 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:26:12 PM PDT 24
Peak memory 182712 kb
Host smart-1a61f936-372a-49a8-9806-e21242ae123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303202003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.303202003
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1524205184
Short name T213
Test name
Test status
Simulation time 777437789744 ps
CPU time 297.89 seconds
Started Apr 25 12:24:34 PM PDT 24
Finished Apr 25 12:29:33 PM PDT 24
Peak memory 191028 kb
Host smart-8efc39ea-6021-46cf-9d55-894af9a6c375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524205184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1524205184
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.634682233
Short name T206
Test name
Test status
Simulation time 4101944071 ps
CPU time 2.65 seconds
Started Apr 25 12:24:37 PM PDT 24
Finished Apr 25 12:24:41 PM PDT 24
Peak memory 182824 kb
Host smart-f553b9c0-e451-437e-ab89-5eae44045442
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634682233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.634682233
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3438070863
Short name T424
Test name
Test status
Simulation time 307137867768 ps
CPU time 113.26 seconds
Started Apr 25 12:24:56 PM PDT 24
Finished Apr 25 12:26:51 PM PDT 24
Peak memory 182792 kb
Host smart-e5e72ce6-cb33-45d5-b005-7042b11c06ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438070863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3438070863
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3187424286
Short name T448
Test name
Test status
Simulation time 687357863984 ps
CPU time 77.99 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:25:55 PM PDT 24
Peak memory 193336 kb
Host smart-59bf5d09-ba4a-406b-b3d1-5a1882aeb23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187424286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3187424286
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2880360494
Short name T269
Test name
Test status
Simulation time 331826494878 ps
CPU time 68.98 seconds
Started Apr 25 12:24:19 PM PDT 24
Finished Apr 25 12:25:29 PM PDT 24
Peak memory 191000 kb
Host smart-4b0e8ae1-c680-4e45-a211-781f66c77638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880360494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2880360494
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3039532908
Short name T366
Test name
Test status
Simulation time 657212716819 ps
CPU time 248.44 seconds
Started Apr 25 12:24:39 PM PDT 24
Finished Apr 25 12:28:49 PM PDT 24
Peak memory 190916 kb
Host smart-5bf8217b-fb93-497e-8fc7-12aac16989ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039532908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3039532908
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.19188026
Short name T216
Test name
Test status
Simulation time 61950031241 ps
CPU time 62.52 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:25:28 PM PDT 24
Peak memory 182812 kb
Host smart-e9104dc1-6513-4e7e-8fb2-77eac8495798
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19188026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.rv_timer_cfg_update_on_fly.19188026
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.616828814
Short name T407
Test name
Test status
Simulation time 291089413073 ps
CPU time 123.26 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:26:40 PM PDT 24
Peak memory 182792 kb
Host smart-1c73a8d9-1e72-4161-b28a-882d20f11d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616828814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.616828814
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1378625728
Short name T360
Test name
Test status
Simulation time 5211391967 ps
CPU time 32.84 seconds
Started Apr 25 12:24:26 PM PDT 24
Finished Apr 25 12:25:00 PM PDT 24
Peak memory 182788 kb
Host smart-8432bd4a-8a00-4150-a571-726608ca5e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378625728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1378625728
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2345617035
Short name T258
Test name
Test status
Simulation time 169317425865 ps
CPU time 951.38 seconds
Started Apr 25 12:24:23 PM PDT 24
Finished Apr 25 12:40:15 PM PDT 24
Peak memory 191008 kb
Host smart-5090efc1-d514-43bc-ba1b-d75f8f2fb1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345617035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2345617035
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.962081742
Short name T416
Test name
Test status
Simulation time 730076385827 ps
CPU time 388.67 seconds
Started Apr 25 12:24:16 PM PDT 24
Finished Apr 25 12:30:46 PM PDT 24
Peak memory 182796 kb
Host smart-7180092f-6495-4ea1-a294-51fc86516c57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962081742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.962081742
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3217386428
Short name T389
Test name
Test status
Simulation time 547654034900 ps
CPU time 123.42 seconds
Started Apr 25 12:24:21 PM PDT 24
Finished Apr 25 12:26:25 PM PDT 24
Peak memory 182788 kb
Host smart-62e779fa-f990-4b3a-80a8-393956c08243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217386428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3217386428
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.58147693
Short name T290
Test name
Test status
Simulation time 845157197156 ps
CPU time 387.26 seconds
Started Apr 25 12:24:27 PM PDT 24
Finished Apr 25 12:31:00 PM PDT 24
Peak memory 191128 kb
Host smart-b978b659-6380-4062-bc73-d11b03ae7cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58147693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.58147693
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.129550685
Short name T425
Test name
Test status
Simulation time 52597943290 ps
CPU time 39.6 seconds
Started Apr 25 12:24:38 PM PDT 24
Finished Apr 25 12:25:19 PM PDT 24
Peak memory 182804 kb
Host smart-568eec53-9120-4c4b-9856-c9b6c482153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129550685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.129550685
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.1395913774
Short name T84
Test name
Test status
Simulation time 210193684094 ps
CPU time 382.57 seconds
Started Apr 25 12:24:37 PM PDT 24
Finished Apr 25 12:31:01 PM PDT 24
Peak memory 205608 kb
Host smart-14b64de5-2f59-482c-9f19-5236e50573fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395913774 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.1395913774
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2140831586
Short name T23
Test name
Test status
Simulation time 266673737884 ps
CPU time 219.49 seconds
Started Apr 25 12:24:27 PM PDT 24
Finished Apr 25 12:28:08 PM PDT 24
Peak memory 182936 kb
Host smart-70a90ae1-9e9b-4f1b-8b73-05a8d23b547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140831586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2140831586
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3257807647
Short name T275
Test name
Test status
Simulation time 48235040228 ps
CPU time 88.44 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:26:16 PM PDT 24
Peak memory 191008 kb
Host smart-58f91418-7cb7-474e-b684-0ce0bfcf54dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257807647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3257807647
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3598817559
Short name T348
Test name
Test status
Simulation time 106810817984 ps
CPU time 117.83 seconds
Started Apr 25 12:24:14 PM PDT 24
Finished Apr 25 12:26:13 PM PDT 24
Peak memory 194352 kb
Host smart-95bda79e-15c8-4e79-a442-557538a5b4af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598817559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3598817559
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.665049193
Short name T41
Test name
Test status
Simulation time 13082844139 ps
CPU time 131.74 seconds
Started Apr 25 12:24:23 PM PDT 24
Finished Apr 25 12:26:36 PM PDT 24
Peak memory 197320 kb
Host smart-7765fdb7-30fc-43f0-ad3e-dceff301272d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665049193 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.665049193
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2125905635
Short name T115
Test name
Test status
Simulation time 656813373199 ps
CPU time 386.49 seconds
Started Apr 25 12:24:28 PM PDT 24
Finished Apr 25 12:30:56 PM PDT 24
Peak memory 182820 kb
Host smart-21820565-5617-4c28-b3c3-15f669d82189
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125905635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2125905635
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.22671277
Short name T361
Test name
Test status
Simulation time 237008983474 ps
CPU time 86.07 seconds
Started Apr 25 12:24:33 PM PDT 24
Finished Apr 25 12:25:59 PM PDT 24
Peak memory 182732 kb
Host smart-6f0451af-3190-4f1b-9f26-e5178ba095ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22671277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.22671277
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.392090740
Short name T320
Test name
Test status
Simulation time 38734063724 ps
CPU time 285.64 seconds
Started Apr 25 12:24:19 PM PDT 24
Finished Apr 25 12:29:06 PM PDT 24
Peak memory 182792 kb
Host smart-e311e52c-82f6-4f36-8bab-8b0bd66192b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392090740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.392090740
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2802090624
Short name T358
Test name
Test status
Simulation time 45138895303 ps
CPU time 42.9 seconds
Started Apr 25 12:24:35 PM PDT 24
Finished Apr 25 12:25:19 PM PDT 24
Peak memory 182524 kb
Host smart-408120bb-fef8-475e-916c-6fe81375b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802090624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2802090624
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4163168693
Short name T414
Test name
Test status
Simulation time 164941705112 ps
CPU time 99.3 seconds
Started Apr 25 12:24:40 PM PDT 24
Finished Apr 25 12:26:20 PM PDT 24
Peak memory 195136 kb
Host smart-9885981b-1a9c-4a06-bd2d-fd6c71e146e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163168693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4163168693
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2524677818
Short name T294
Test name
Test status
Simulation time 400264433939 ps
CPU time 637.84 seconds
Started Apr 25 12:24:33 PM PDT 24
Finished Apr 25 12:35:12 PM PDT 24
Peak memory 182776 kb
Host smart-d8fb18d3-6b63-4cf5-9a10-fa623f67432a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524677818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2524677818
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3445778849
Short name T60
Test name
Test status
Simulation time 634711926791 ps
CPU time 271.61 seconds
Started Apr 25 12:24:33 PM PDT 24
Finished Apr 25 12:29:05 PM PDT 24
Peak memory 182800 kb
Host smart-7d3f8d19-5ab9-41d1-9159-13ad50fd214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445778849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3445778849
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3356377618
Short name T438
Test name
Test status
Simulation time 69877640 ps
CPU time 0.56 seconds
Started Apr 25 12:24:30 PM PDT 24
Finished Apr 25 12:24:32 PM PDT 24
Peak memory 182556 kb
Host smart-dd6a193d-705c-4ee8-a2aa-69bf684ad3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356377618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3356377618
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1253733801
Short name T107
Test name
Test status
Simulation time 3107301398862 ps
CPU time 791.95 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:37:49 PM PDT 24
Peak memory 191128 kb
Host smart-a211a30c-3011-407e-8a3d-313ad6a1dfb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253733801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1253733801
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3915675036
Short name T340
Test name
Test status
Simulation time 93365172587 ps
CPU time 50.11 seconds
Started Apr 25 12:24:15 PM PDT 24
Finished Apr 25 12:25:06 PM PDT 24
Peak memory 182824 kb
Host smart-89a6d20a-004a-4cba-b1d0-ed6931ec71d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915675036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3915675036
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2688816846
Short name T5
Test name
Test status
Simulation time 231658119993 ps
CPU time 175.27 seconds
Started Apr 25 12:24:07 PM PDT 24
Finished Apr 25 12:27:03 PM PDT 24
Peak memory 182752 kb
Host smart-842c02b9-eb04-43c7-b135-13ce8e907e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688816846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2688816846
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.202988835
Short name T303
Test name
Test status
Simulation time 221074404163 ps
CPU time 130.83 seconds
Started Apr 25 12:24:20 PM PDT 24
Finished Apr 25 12:26:37 PM PDT 24
Peak memory 191004 kb
Host smart-c4f29e1a-2d36-4486-8861-8a08b2348d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202988835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.202988835
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.399230883
Short name T345
Test name
Test status
Simulation time 32769838337 ps
CPU time 317.27 seconds
Started Apr 25 12:24:18 PM PDT 24
Finished Apr 25 12:29:36 PM PDT 24
Peak memory 190972 kb
Host smart-22262a08-37b7-4603-9988-9696619db87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399230883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.399230883
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1226366721
Short name T17
Test name
Test status
Simulation time 83084619 ps
CPU time 0.92 seconds
Started Apr 25 12:24:33 PM PDT 24
Finished Apr 25 12:24:35 PM PDT 24
Peak memory 214268 kb
Host smart-9db5e318-4897-4a03-826d-83a6e5d97ac4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226366721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1226366721
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1098144760
Short name T412
Test name
Test status
Simulation time 368356562619 ps
CPU time 107.77 seconds
Started Apr 25 12:23:57 PM PDT 24
Finished Apr 25 12:25:46 PM PDT 24
Peak memory 182724 kb
Host smart-eb217dd2-1914-4f00-aa0a-8c37cdb5e879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098144760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1098144760
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.331778075
Short name T37
Test name
Test status
Simulation time 31071308355 ps
CPU time 250.15 seconds
Started Apr 25 12:24:22 PM PDT 24
Finished Apr 25 12:28:33 PM PDT 24
Peak memory 197360 kb
Host smart-2fd6d0f2-01b5-472d-a619-b3ad5c8f49c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331778075 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.331778075
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1855843366
Short name T375
Test name
Test status
Simulation time 106631572691 ps
CPU time 162.58 seconds
Started Apr 25 12:24:24 PM PDT 24
Finished Apr 25 12:27:07 PM PDT 24
Peak memory 182780 kb
Host smart-64579b18-9753-4776-b66f-3a1029de0600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855843366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1855843366
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3896180992
Short name T440
Test name
Test status
Simulation time 101093247414 ps
CPU time 112.74 seconds
Started Apr 25 12:24:38 PM PDT 24
Finished Apr 25 12:26:32 PM PDT 24
Peak memory 191080 kb
Host smart-01cc0c70-b3bf-4263-81fe-b16a55e33842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896180992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3896180992
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2843650062
Short name T319
Test name
Test status
Simulation time 76974398480 ps
CPU time 1312.78 seconds
Started Apr 25 12:24:26 PM PDT 24
Finished Apr 25 12:46:20 PM PDT 24
Peak memory 190924 kb
Host smart-4efe13c9-0711-4215-8f2d-4b75ad6b0869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843650062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2843650062
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2651769991
Short name T347
Test name
Test status
Simulation time 259945647786 ps
CPU time 127.89 seconds
Started Apr 25 12:24:45 PM PDT 24
Finished Apr 25 12:26:54 PM PDT 24
Peak memory 182808 kb
Host smart-55037c7b-f838-49ae-993d-cea6599555cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651769991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2651769991
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.484485182
Short name T426
Test name
Test status
Simulation time 113434800452 ps
CPU time 173 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:27:38 PM PDT 24
Peak memory 182812 kb
Host smart-d607e58b-5f5c-47c6-abb3-61ad2fb4bb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484485182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.484485182
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4262886024
Short name T356
Test name
Test status
Simulation time 211000537061 ps
CPU time 186.49 seconds
Started Apr 25 12:24:30 PM PDT 24
Finished Apr 25 12:27:37 PM PDT 24
Peak memory 193772 kb
Host smart-390b4766-54d4-48f9-88df-ae2c154ceb40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262886024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4262886024
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3718987942
Short name T349
Test name
Test status
Simulation time 15990324493 ps
CPU time 27.15 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:25:05 PM PDT 24
Peak memory 191992 kb
Host smart-b71e8e8b-2826-4ee4-8a5b-0775cb61a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718987942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3718987942
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.918086064
Short name T291
Test name
Test status
Simulation time 986938210244 ps
CPU time 911.9 seconds
Started Apr 25 12:24:33 PM PDT 24
Finished Apr 25 12:39:46 PM PDT 24
Peak memory 182796 kb
Host smart-9b30f2e6-d303-4fdc-aaf0-f45985e0f756
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918086064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.918086064
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.694023488
Short name T377
Test name
Test status
Simulation time 177204263042 ps
CPU time 133.8 seconds
Started Apr 25 12:24:49 PM PDT 24
Finished Apr 25 12:27:05 PM PDT 24
Peak memory 182800 kb
Host smart-4ed755bd-cebc-4f2e-8bc6-f7af5506b36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694023488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.694023488
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3213631847
Short name T136
Test name
Test status
Simulation time 180666650899 ps
CPU time 159.63 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:27:25 PM PDT 24
Peak memory 190980 kb
Host smart-79f223c2-81bb-4212-8526-03993b3fab17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213631847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3213631847
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.191979378
Short name T172
Test name
Test status
Simulation time 176340203066 ps
CPU time 213.84 seconds
Started Apr 25 12:24:38 PM PDT 24
Finished Apr 25 12:28:13 PM PDT 24
Peak memory 190976 kb
Host smart-f8022a31-5a74-41fa-bc84-85f1a662abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191979378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.191979378
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.788012231
Short name T373
Test name
Test status
Simulation time 23354603 ps
CPU time 0.62 seconds
Started Apr 25 12:24:35 PM PDT 24
Finished Apr 25 12:24:36 PM PDT 24
Peak memory 182552 kb
Host smart-da067829-c742-45e3-aa27-971e40207259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788012231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
788012231
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1674268672
Short name T246
Test name
Test status
Simulation time 869477861937 ps
CPU time 430.29 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:31:59 PM PDT 24
Peak memory 182820 kb
Host smart-b139d593-54cc-4001-9891-bcec584d4c2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674268672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1674268672
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2581010612
Short name T420
Test name
Test status
Simulation time 469974499728 ps
CPU time 186.45 seconds
Started Apr 25 12:24:27 PM PDT 24
Finished Apr 25 12:27:35 PM PDT 24
Peak memory 182728 kb
Host smart-c8e0c46b-f084-46cf-8f19-6a2ded7e337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581010612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2581010612
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2176491437
Short name T229
Test name
Test status
Simulation time 200980451773 ps
CPU time 171.06 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:27:36 PM PDT 24
Peak memory 191008 kb
Host smart-b9a36bdd-86e2-459e-a16d-5ace4f0332e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176491437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2176491437
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3781203889
Short name T29
Test name
Test status
Simulation time 189451286 ps
CPU time 0.75 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:25:02 PM PDT 24
Peak memory 182708 kb
Host smart-07f88e82-e9ce-4f93-879a-3bed6df9ce54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781203889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3781203889
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2485495455
Short name T43
Test name
Test status
Simulation time 29427262369 ps
CPU time 310.42 seconds
Started Apr 25 12:24:26 PM PDT 24
Finished Apr 25 12:29:37 PM PDT 24
Peak memory 197468 kb
Host smart-99707c7f-2a77-4c92-9c94-7b4ec6ed7396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485495455 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2485495455
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2701795704
Short name T67
Test name
Test status
Simulation time 346020046423 ps
CPU time 452.4 seconds
Started Apr 25 12:24:49 PM PDT 24
Finished Apr 25 12:32:24 PM PDT 24
Peak memory 182548 kb
Host smart-6073d75e-f24d-4658-91d9-4017ff835aa4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701795704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2701795704
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3466865334
Short name T403
Test name
Test status
Simulation time 44460725551 ps
CPU time 66.13 seconds
Started Apr 25 12:24:42 PM PDT 24
Finished Apr 25 12:25:49 PM PDT 24
Peak memory 182804 kb
Host smart-46ad4baf-1c29-4e81-9e31-d29116f9c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466865334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3466865334
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2314503191
Short name T50
Test name
Test status
Simulation time 245296193294 ps
CPU time 422.63 seconds
Started Apr 25 12:24:34 PM PDT 24
Finished Apr 25 12:31:37 PM PDT 24
Peak memory 190988 kb
Host smart-06b2fb5a-3505-4eee-b5d6-163962a602aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314503191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2314503191
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1448023492
Short name T227
Test name
Test status
Simulation time 127683982045 ps
CPU time 41.67 seconds
Started Apr 25 12:24:41 PM PDT 24
Finished Apr 25 12:25:23 PM PDT 24
Peak memory 195216 kb
Host smart-8f3573a3-6a8e-4ab7-9906-b88cdc6fab41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448023492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1448023492
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1763941121
Short name T251
Test name
Test status
Simulation time 5665682819 ps
CPU time 2.26 seconds
Started Apr 25 12:24:27 PM PDT 24
Finished Apr 25 12:24:30 PM PDT 24
Peak memory 182808 kb
Host smart-b58f7921-7e33-4fbb-9369-0ba15abf3d8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763941121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1763941121
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.334915199
Short name T367
Test name
Test status
Simulation time 370442091254 ps
CPU time 199.74 seconds
Started Apr 25 12:24:33 PM PDT 24
Finished Apr 25 12:27:54 PM PDT 24
Peak memory 182748 kb
Host smart-0b917d51-3f8a-49dc-aec9-1535ab6c286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334915199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.334915199
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1494378420
Short name T127
Test name
Test status
Simulation time 1714426034410 ps
CPU time 355.11 seconds
Started Apr 25 12:24:47 PM PDT 24
Finished Apr 25 12:30:44 PM PDT 24
Peak memory 190980 kb
Host smart-f1d5368f-aa22-4549-9833-e8d5714d24a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494378420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1494378420
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1745005703
Short name T141
Test name
Test status
Simulation time 47544298010 ps
CPU time 83.28 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:26:16 PM PDT 24
Peak memory 190980 kb
Host smart-d6456580-c582-4166-897c-28f90536463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745005703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1745005703
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.67855807
Short name T427
Test name
Test status
Simulation time 49747225373 ps
CPU time 151.65 seconds
Started Apr 25 12:24:30 PM PDT 24
Finished Apr 25 12:27:02 PM PDT 24
Peak memory 197480 kb
Host smart-b310583e-940d-4fa7-90eb-8b503967a078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67855807 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.67855807
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_random.495858024
Short name T401
Test name
Test status
Simulation time 29533167936 ps
CPU time 49.43 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:25:42 PM PDT 24
Peak memory 182796 kb
Host smart-f0913843-c529-409b-9548-b1171c9a7919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495858024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.495858024
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3537625130
Short name T354
Test name
Test status
Simulation time 173632865313 ps
CPU time 630.42 seconds
Started Apr 25 12:25:01 PM PDT 24
Finished Apr 25 12:35:32 PM PDT 24
Peak memory 191028 kb
Host smart-64fa2edc-ff86-4caa-bc90-d212e4b54ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537625130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3537625130
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.811296871
Short name T431
Test name
Test status
Simulation time 656153413817 ps
CPU time 135.19 seconds
Started Apr 25 12:24:54 PM PDT 24
Finished Apr 25 12:27:11 PM PDT 24
Peak memory 182812 kb
Host smart-1443824e-26b0-45c0-a86c-abd159813637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811296871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.811296871
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2772780722
Short name T118
Test name
Test status
Simulation time 362836689590 ps
CPU time 483.71 seconds
Started Apr 25 12:24:44 PM PDT 24
Finished Apr 25 12:32:49 PM PDT 24
Peak memory 190976 kb
Host smart-c44afeea-33a6-4e8c-baca-a55e6da0c0e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772780722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2772780722
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1781923031
Short name T261
Test name
Test status
Simulation time 198964895500 ps
CPU time 428.64 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:32:06 PM PDT 24
Peak memory 182908 kb
Host smart-0de25269-8c02-42db-929e-cf5d021a199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781923031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1781923031
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3255235401
Short name T226
Test name
Test status
Simulation time 234914299042 ps
CPU time 371.98 seconds
Started Apr 25 12:24:36 PM PDT 24
Finished Apr 25 12:30:49 PM PDT 24
Peak memory 182812 kb
Host smart-fd0ff974-0a37-488e-a73e-9842c8a78b01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255235401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3255235401
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1817191248
Short name T435
Test name
Test status
Simulation time 85989448281 ps
CPU time 106.55 seconds
Started Apr 25 12:24:40 PM PDT 24
Finished Apr 25 12:26:27 PM PDT 24
Peak memory 182796 kb
Host smart-6b124f49-f590-403b-aad7-e836f23b23b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817191248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1817191248
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2394697656
Short name T13
Test name
Test status
Simulation time 179307699166 ps
CPU time 1966.98 seconds
Started Apr 25 12:24:35 PM PDT 24
Finished Apr 25 12:57:23 PM PDT 24
Peak memory 195208 kb
Host smart-a45af6d8-0fbe-458e-908d-7b99776c1a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394697656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2394697656
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.791886252
Short name T82
Test name
Test status
Simulation time 122244434313 ps
CPU time 189.75 seconds
Started Apr 25 12:25:05 PM PDT 24
Finished Apr 25 12:28:16 PM PDT 24
Peak memory 182820 kb
Host smart-90fa9563-be2e-49d3-9f40-59ada67fe710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791886252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
791886252
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4021619213
Short name T428
Test name
Test status
Simulation time 90937479131 ps
CPU time 154.42 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:27:19 PM PDT 24
Peak memory 182564 kb
Host smart-eb6bd3b3-f929-44bf-8f62-84d6dd6d343a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021619213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4021619213
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1184887080
Short name T411
Test name
Test status
Simulation time 172860902206 ps
CPU time 139.72 seconds
Started Apr 25 12:25:03 PM PDT 24
Finished Apr 25 12:27:24 PM PDT 24
Peak memory 182784 kb
Host smart-26362f03-bb5e-4aec-9045-284bbfaf60b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184887080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1184887080
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3300468842
Short name T24
Test name
Test status
Simulation time 278935977440 ps
CPU time 532.07 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:33:43 PM PDT 24
Peak memory 191000 kb
Host smart-04847c74-f229-4b00-a076-c9550d6b3d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300468842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3300468842
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3097066531
Short name T322
Test name
Test status
Simulation time 195313950224 ps
CPU time 346.45 seconds
Started Apr 25 12:24:10 PM PDT 24
Finished Apr 25 12:29:58 PM PDT 24
Peak memory 182828 kb
Host smart-cfe78622-a09b-4a73-a2fc-32c06dff2be4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097066531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3097066531
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1026111019
Short name T372
Test name
Test status
Simulation time 215229127597 ps
CPU time 322.45 seconds
Started Apr 25 12:23:57 PM PDT 24
Finished Apr 25 12:29:20 PM PDT 24
Peak memory 182740 kb
Host smart-3cdb251b-e3f5-4031-bb9b-6e3085787f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026111019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1026111019
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1053610782
Short name T22
Test name
Test status
Simulation time 45737834193 ps
CPU time 84.76 seconds
Started Apr 25 12:24:09 PM PDT 24
Finished Apr 25 12:25:35 PM PDT 24
Peak memory 191020 kb
Host smart-b75830e8-c555-4b6f-be79-cedaa1b3c18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053610782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1053610782
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1870545005
Short name T72
Test name
Test status
Simulation time 1321388807768 ps
CPU time 613.15 seconds
Started Apr 25 12:24:08 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 190936 kb
Host smart-6f4317cb-bdd9-4ba1-8d8f-cb4778883375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870545005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1870545005
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.686145809
Short name T282
Test name
Test status
Simulation time 503926239017 ps
CPU time 522.75 seconds
Started Apr 25 12:24:59 PM PDT 24
Finished Apr 25 12:33:43 PM PDT 24
Peak memory 194320 kb
Host smart-855d374e-87d4-4ae6-aebf-9b88471b5b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686145809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.686145809
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.438499997
Short name T199
Test name
Test status
Simulation time 105325452152 ps
CPU time 79.63 seconds
Started Apr 25 12:24:57 PM PDT 24
Finished Apr 25 12:26:18 PM PDT 24
Peak memory 182796 kb
Host smart-abf92f72-b5dc-4db0-a42f-97b4660cab69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438499997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.438499997
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.139211608
Short name T236
Test name
Test status
Simulation time 146288736528 ps
CPU time 456.65 seconds
Started Apr 25 12:24:54 PM PDT 24
Finished Apr 25 12:32:33 PM PDT 24
Peak memory 190924 kb
Host smart-6845cfe4-ef22-4c01-9e77-bab386720aa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139211608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.139211608
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3220182848
Short name T2
Test name
Test status
Simulation time 320721265868 ps
CPU time 284.17 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:29:41 PM PDT 24
Peak memory 191004 kb
Host smart-c0be6833-9895-416e-8da0-8b8d2be5c285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220182848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3220182848
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.286926883
Short name T300
Test name
Test status
Simulation time 205597115976 ps
CPU time 183.52 seconds
Started Apr 25 12:25:00 PM PDT 24
Finished Apr 25 12:28:05 PM PDT 24
Peak memory 190964 kb
Host smart-47ba1029-c54e-4172-81cc-ed9a05e30ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286926883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.286926883
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3380043026
Short name T64
Test name
Test status
Simulation time 312473956592 ps
CPU time 1503.58 seconds
Started Apr 25 12:25:02 PM PDT 24
Finished Apr 25 12:50:07 PM PDT 24
Peak memory 191024 kb
Host smart-1fe8ad16-b6a4-4290-9ac5-9556fb3a1d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380043026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3380043026
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2491067094
Short name T357
Test name
Test status
Simulation time 2416581495 ps
CPU time 4.26 seconds
Started Apr 25 12:24:05 PM PDT 24
Finished Apr 25 12:24:10 PM PDT 24
Peak memory 182780 kb
Host smart-fd91c26f-328d-45bf-b4d1-4926c6f2bc22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491067094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2491067094
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random.342312664
Short name T155
Test name
Test status
Simulation time 55722323988 ps
CPU time 89.44 seconds
Started Apr 25 12:24:16 PM PDT 24
Finished Apr 25 12:25:46 PM PDT 24
Peak memory 190968 kb
Host smart-d0a1cf0b-446a-4216-a09e-d99e3c67f117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342312664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.342312664
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.854720153
Short name T189
Test name
Test status
Simulation time 506578756125 ps
CPU time 227.28 seconds
Started Apr 25 12:23:54 PM PDT 24
Finished Apr 25 12:27:42 PM PDT 24
Peak memory 182788 kb
Host smart-828ae94d-eb8a-476e-8946-0e7dfcb8723a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854720153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.854720153
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3350431748
Short name T83
Test name
Test status
Simulation time 209652267803 ps
CPU time 87.9 seconds
Started Apr 25 12:23:56 PM PDT 24
Finished Apr 25 12:25:25 PM PDT 24
Peak memory 182808 kb
Host smart-8313655b-dea6-4220-9ded-b0a1be4ca183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350431748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3350431748
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.4207172702
Short name T446
Test name
Test status
Simulation time 70999011744 ps
CPU time 590.12 seconds
Started Apr 25 12:23:58 PM PDT 24
Finished Apr 25 12:33:49 PM PDT 24
Peak memory 208028 kb
Host smart-be636b89-7678-4179-89b6-0e56fdbe51d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207172702 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.4207172702
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1303143262
Short name T222
Test name
Test status
Simulation time 233745824448 ps
CPU time 991.47 seconds
Started Apr 25 12:24:56 PM PDT 24
Finished Apr 25 12:41:29 PM PDT 24
Peak memory 190748 kb
Host smart-3507d5c0-8b38-49fb-b87b-a0108589c69c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303143262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1303143262
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.318567514
Short name T177
Test name
Test status
Simulation time 188900271337 ps
CPU time 506.42 seconds
Started Apr 25 12:24:57 PM PDT 24
Finished Apr 25 12:33:25 PM PDT 24
Peak memory 191024 kb
Host smart-15aede16-d0dd-43cf-919f-095a3593527f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318567514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.318567514
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.167270362
Short name T193
Test name
Test status
Simulation time 6530336299 ps
CPU time 82.81 seconds
Started Apr 25 12:24:57 PM PDT 24
Finished Apr 25 12:26:21 PM PDT 24
Peak memory 182872 kb
Host smart-59f1ccfe-d38f-4664-97f7-283f4ee78d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167270362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.167270362
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2837571946
Short name T264
Test name
Test status
Simulation time 83244288845 ps
CPU time 184.83 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:27:58 PM PDT 24
Peak memory 191012 kb
Host smart-da24e03f-8ea4-4e03-8c2d-cf2652ebe9dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837571946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2837571946
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3944344785
Short name T194
Test name
Test status
Simulation time 392179912639 ps
CPU time 576.59 seconds
Started Apr 25 12:24:34 PM PDT 24
Finished Apr 25 12:34:12 PM PDT 24
Peak memory 190924 kb
Host smart-8de75935-1ad9-469c-a458-0b659a1bfb22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944344785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3944344785
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2957632195
Short name T158
Test name
Test status
Simulation time 298487702586 ps
CPU time 127.52 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:26:57 PM PDT 24
Peak memory 191016 kb
Host smart-b30042c1-c3c4-4089-b900-2b986e88e48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957632195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2957632195
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.163127101
Short name T148
Test name
Test status
Simulation time 26426684860 ps
CPU time 40.72 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:25:25 PM PDT 24
Peak memory 182780 kb
Host smart-de2233f7-247a-445a-b641-31a60aeb6bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163127101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.163127101
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1677860141
Short name T406
Test name
Test status
Simulation time 355574675 ps
CPU time 0.99 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:24:57 PM PDT 24
Peak memory 182596 kb
Host smart-140895a6-402f-4c27-9f7b-30420f46c8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677860141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1677860141
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3994148016
Short name T399
Test name
Test status
Simulation time 121278826811 ps
CPU time 60.3 seconds
Started Apr 25 12:24:49 PM PDT 24
Finished Apr 25 12:25:52 PM PDT 24
Peak memory 182804 kb
Host smart-fe1ae0ee-57e9-42b6-adfe-c9ffd9b2fe3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994148016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3994148016
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1502086635
Short name T330
Test name
Test status
Simulation time 70150164215 ps
CPU time 464.24 seconds
Started Apr 25 12:24:48 PM PDT 24
Finished Apr 25 12:32:34 PM PDT 24
Peak memory 182776 kb
Host smart-11f8d61a-d5a4-4567-ac52-2c31a41683da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502086635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1502086635
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.961034379
Short name T120
Test name
Test status
Simulation time 495162844679 ps
CPU time 809.51 seconds
Started Apr 25 12:23:59 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 182736 kb
Host smart-e2ec334b-c86e-4aba-9d50-805c62dceeb6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961034379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.961034379
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3818259468
Short name T436
Test name
Test status
Simulation time 503339289285 ps
CPU time 135.39 seconds
Started Apr 25 12:24:14 PM PDT 24
Finished Apr 25 12:26:31 PM PDT 24
Peak memory 182808 kb
Host smart-9393ff63-41b2-438c-b982-e4ff237acc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818259468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3818259468
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3546142449
Short name T257
Test name
Test status
Simulation time 71768147179 ps
CPU time 141.91 seconds
Started Apr 25 12:24:17 PM PDT 24
Finished Apr 25 12:26:40 PM PDT 24
Peak memory 191004 kb
Host smart-fa87a090-9b9e-4353-aae6-bd133f7bdd49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546142449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3546142449
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.500512883
Short name T279
Test name
Test status
Simulation time 120987746947 ps
CPU time 93.27 seconds
Started Apr 25 12:24:05 PM PDT 24
Finished Apr 25 12:25:40 PM PDT 24
Peak memory 182728 kb
Host smart-01cefea9-b6d5-45ad-baa3-d74f94a66e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500512883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.500512883
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1784183164
Short name T400
Test name
Test status
Simulation time 168826588706 ps
CPU time 260.33 seconds
Started Apr 25 12:23:57 PM PDT 24
Finished Apr 25 12:28:18 PM PDT 24
Peak memory 190936 kb
Host smart-1cb074ed-b64c-4fae-9ca1-166f573abf69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784183164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1784183164
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.4027661760
Short name T314
Test name
Test status
Simulation time 280961727361 ps
CPU time 522.01 seconds
Started Apr 25 12:24:41 PM PDT 24
Finished Apr 25 12:33:25 PM PDT 24
Peak memory 191004 kb
Host smart-69f03b77-33e9-4361-9b8d-84b16e1f9f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027661760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4027661760
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.964630584
Short name T351
Test name
Test status
Simulation time 111010890670 ps
CPU time 1169.08 seconds
Started Apr 25 12:25:12 PM PDT 24
Finished Apr 25 12:44:43 PM PDT 24
Peak memory 182796 kb
Host smart-d86ee9a4-729f-426d-b5e5-eb4551c7950e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964630584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.964630584
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1065570496
Short name T130
Test name
Test status
Simulation time 1136376043659 ps
CPU time 219.61 seconds
Started Apr 25 12:24:41 PM PDT 24
Finished Apr 25 12:28:21 PM PDT 24
Peak memory 190996 kb
Host smart-1c4ce904-1898-47e0-aecd-72c3d5fb9629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065570496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1065570496
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4029120817
Short name T281
Test name
Test status
Simulation time 340486573623 ps
CPU time 251.42 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:29:12 PM PDT 24
Peak memory 190976 kb
Host smart-528aa667-c2a4-4276-862f-de1d4e8eabdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029120817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4029120817
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3706550796
Short name T288
Test name
Test status
Simulation time 69382259334 ps
CPU time 37.18 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:25:25 PM PDT 24
Peak memory 182776 kb
Host smart-2f748d6e-3bd5-44e2-b25a-cf79436cabb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706550796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3706550796
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.721366955
Short name T181
Test name
Test status
Simulation time 240163369385 ps
CPU time 158.01 seconds
Started Apr 25 12:25:10 PM PDT 24
Finished Apr 25 12:27:48 PM PDT 24
Peak memory 190988 kb
Host smart-51a246a5-4648-4aa8-964c-d758af2f22e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721366955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.721366955
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3344809402
Short name T346
Test name
Test status
Simulation time 131049019184 ps
CPU time 810.24 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:38:25 PM PDT 24
Peak memory 182776 kb
Host smart-6b68b2c7-ca1b-46ab-8c3f-a6a2aae8e98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344809402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3344809402
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2582594851
Short name T272
Test name
Test status
Simulation time 20985528011 ps
CPU time 37 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:25:22 PM PDT 24
Peak memory 182804 kb
Host smart-07a1a6ba-3780-4f56-9c1a-f9f70a017333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582594851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2582594851
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1227026129
Short name T437
Test name
Test status
Simulation time 117780333521 ps
CPU time 106.08 seconds
Started Apr 25 12:24:14 PM PDT 24
Finished Apr 25 12:26:01 PM PDT 24
Peak memory 182804 kb
Host smart-e657b5d5-957f-4a22-943d-b90207516ce4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227026129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1227026129
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3787484501
Short name T408
Test name
Test status
Simulation time 144796258299 ps
CPU time 55.2 seconds
Started Apr 25 12:24:19 PM PDT 24
Finished Apr 25 12:25:15 PM PDT 24
Peak memory 182804 kb
Host smart-3df87fa7-ae24-4bbc-901b-62ff8004ba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787484501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3787484501
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3492330579
Short name T334
Test name
Test status
Simulation time 131581897557 ps
CPU time 65.77 seconds
Started Apr 25 12:23:52 PM PDT 24
Finished Apr 25 12:24:59 PM PDT 24
Peak memory 182764 kb
Host smart-1ccd3a90-b8eb-4797-aa62-c8b773eef115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492330579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3492330579
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3635835674
Short name T409
Test name
Test status
Simulation time 9365551728 ps
CPU time 15.08 seconds
Started Apr 25 12:23:54 PM PDT 24
Finished Apr 25 12:24:09 PM PDT 24
Peak memory 182612 kb
Host smart-5e4bd50e-0532-4998-b489-6b430d99e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635835674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3635835674
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1722278490
Short name T191
Test name
Test status
Simulation time 1646822017044 ps
CPU time 771.47 seconds
Started Apr 25 12:24:18 PM PDT 24
Finished Apr 25 12:37:10 PM PDT 24
Peak memory 195732 kb
Host smart-560503e8-30a4-4ae6-a238-721c97019386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722278490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1722278490
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.664541601
Short name T28
Test name
Test status
Simulation time 103487461309 ps
CPU time 168.59 seconds
Started Apr 25 12:24:49 PM PDT 24
Finished Apr 25 12:27:40 PM PDT 24
Peak memory 190976 kb
Host smart-70156734-d063-407c-8667-e4b261861f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664541601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.664541601
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3980506735
Short name T286
Test name
Test status
Simulation time 443628948839 ps
CPU time 148.89 seconds
Started Apr 25 12:24:55 PM PDT 24
Finished Apr 25 12:27:26 PM PDT 24
Peak memory 190976 kb
Host smart-eb7dcd32-fb93-4de8-85b5-b84eaf689011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980506735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3980506735
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1191185266
Short name T271
Test name
Test status
Simulation time 147010378287 ps
CPU time 286.06 seconds
Started Apr 25 12:25:03 PM PDT 24
Finished Apr 25 12:29:50 PM PDT 24
Peak memory 190952 kb
Host smart-bc6e17cf-875b-431d-87a2-40383fa6e140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191185266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1191185266
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3164887977
Short name T442
Test name
Test status
Simulation time 357511809708 ps
CPU time 386.6 seconds
Started Apr 25 12:24:42 PM PDT 24
Finished Apr 25 12:31:10 PM PDT 24
Peak memory 191008 kb
Host smart-054f1042-6eb8-4269-bc6d-77b835202b6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164887977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3164887977
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3548953036
Short name T355
Test name
Test status
Simulation time 954837241492 ps
CPU time 445.9 seconds
Started Apr 25 12:24:49 PM PDT 24
Finished Apr 25 12:32:17 PM PDT 24
Peak memory 190732 kb
Host smart-505c9118-d9d2-4341-b8ae-648ac2ef7c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548953036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3548953036
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.626159144
Short name T301
Test name
Test status
Simulation time 70230285282 ps
CPU time 150.44 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:27:24 PM PDT 24
Peak memory 182796 kb
Host smart-f109f7ea-1c97-4553-85d4-8e2b7a0d17d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626159144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.626159144
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3542037780
Short name T66
Test name
Test status
Simulation time 91621195650 ps
CPU time 148.6 seconds
Started Apr 25 12:23:50 PM PDT 24
Finished Apr 25 12:26:19 PM PDT 24
Peak memory 182752 kb
Host smart-fe179ffa-d7ca-4267-8efc-6131372b16f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542037780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3542037780
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.546181681
Short name T418
Test name
Test status
Simulation time 78366842409 ps
CPU time 61.17 seconds
Started Apr 25 12:24:09 PM PDT 24
Finished Apr 25 12:25:11 PM PDT 24
Peak memory 182816 kb
Host smart-60181801-0cf3-440b-ac3b-35e863af1d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546181681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.546181681
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1979645257
Short name T167
Test name
Test status
Simulation time 60895665214 ps
CPU time 62.69 seconds
Started Apr 25 12:24:14 PM PDT 24
Finished Apr 25 12:25:18 PM PDT 24
Peak memory 193472 kb
Host smart-807756e3-5f10-4420-a925-849f02de6147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979645257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1979645257
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1210227022
Short name T363
Test name
Test status
Simulation time 400633871 ps
CPU time 3.79 seconds
Started Apr 25 12:24:38 PM PDT 24
Finished Apr 25 12:24:43 PM PDT 24
Peak memory 182808 kb
Host smart-029e564c-7edf-4659-a467-579a84e31ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210227022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1210227022
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3844991520
Short name T126
Test name
Test status
Simulation time 262077333450 ps
CPU time 3404.82 seconds
Started Apr 25 12:24:26 PM PDT 24
Finished Apr 25 01:21:12 PM PDT 24
Peak memory 191016 kb
Host smart-6615ca88-8ce2-4c2f-aacf-4519b507d638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844991520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3844991520
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.3868180889
Short name T75
Test name
Test status
Simulation time 112784690119 ps
CPU time 180.27 seconds
Started Apr 25 12:24:40 PM PDT 24
Finished Apr 25 12:27:41 PM PDT 24
Peak memory 194600 kb
Host smart-b33245eb-7bb3-4968-ac32-dcad56ae42e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868180889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3868180889
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3094559448
Short name T317
Test name
Test status
Simulation time 301039483258 ps
CPU time 154.28 seconds
Started Apr 25 12:24:46 PM PDT 24
Finished Apr 25 12:27:22 PM PDT 24
Peak memory 190924 kb
Host smart-e6aeb25f-8595-4e35-9c47-2328371fd31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094559448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3094559448
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2569894275
Short name T105
Test name
Test status
Simulation time 742486909898 ps
CPU time 791.08 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:38:03 PM PDT 24
Peak memory 191000 kb
Host smart-1c457cdf-6596-4a97-82ca-accb1b4d4ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569894275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2569894275
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.844303038
Short name T265
Test name
Test status
Simulation time 95236679304 ps
CPU time 76.46 seconds
Started Apr 25 12:25:02 PM PDT 24
Finished Apr 25 12:26:20 PM PDT 24
Peak memory 182936 kb
Host smart-1cf549ae-3d55-4695-b95f-0007f761740a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844303038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.844303038
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3733633480
Short name T309
Test name
Test status
Simulation time 95964599912 ps
CPU time 159.19 seconds
Started Apr 25 12:24:52 PM PDT 24
Finished Apr 25 12:27:33 PM PDT 24
Peak memory 190988 kb
Host smart-20e3d589-ac51-439b-a7bb-d07094a32043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733633480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3733633480
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.98403126
Short name T7
Test name
Test status
Simulation time 39917556971 ps
CPU time 57.59 seconds
Started Apr 25 12:24:51 PM PDT 24
Finished Apr 25 12:25:51 PM PDT 24
Peak memory 182600 kb
Host smart-84fdd7a3-9a35-4fe7-8eae-12addb7d7122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98403126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.98403126
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.534844068
Short name T212
Test name
Test status
Simulation time 479040295732 ps
CPU time 1036.12 seconds
Started Apr 25 12:24:50 PM PDT 24
Finished Apr 25 12:42:08 PM PDT 24
Peak memory 190976 kb
Host smart-92f72af1-9d76-445e-8895-9f5a4d79132f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534844068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.534844068
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.36841769
Short name T335
Test name
Test status
Simulation time 89340657734 ps
CPU time 49.23 seconds
Started Apr 25 12:24:43 PM PDT 24
Finished Apr 25 12:25:34 PM PDT 24
Peak memory 182808 kb
Host smart-b0d6c87f-20e6-4de6-9111-38083b530ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36841769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.36841769
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3100264850
Short name T441
Test name
Test status
Simulation time 37766246627 ps
CPU time 725.64 seconds
Started Apr 25 12:24:53 PM PDT 24
Finished Apr 25 12:37:01 PM PDT 24
Peak memory 182780 kb
Host smart-639c9756-fc87-472f-9a34-9520b3ec0352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100264850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3100264850
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3611190541
Short name T352
Test name
Test status
Simulation time 48792564736 ps
CPU time 17.24 seconds
Started Apr 25 12:25:07 PM PDT 24
Finished Apr 25 12:25:25 PM PDT 24
Peak memory 182412 kb
Host smart-8e295741-eb56-470f-88ee-7a1decde42cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611190541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3611190541
Directory /workspace/99.rv_timer_random/latest
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