Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
112779813 |
1 |
|
T1 |
134569 |
|
T2 |
16935 |
|
T3 |
117 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59510498 |
1 |
|
T1 |
52569 |
|
T2 |
16935 |
|
T3 |
50 |
auto[1] |
53269315 |
1 |
|
T1 |
129312 |
|
T3 |
67 |
|
T4 |
709216 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
112773758 |
1 |
|
T1 |
134568 |
|
T2 |
16931 |
|
T3 |
49 |
auto[1] |
6055 |
1 |
|
T1 |
9 |
|
T2 |
4 |
|
T3 |
68 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
59507478 |
1 |
|
T1 |
52565 |
|
T2 |
16931 |
|
T3 |
20 |
all_values[0] |
auto[0] |
auto[1] |
3020 |
1 |
|
T1 |
4 |
|
T2 |
4 |
|
T3 |
30 |
all_values[0] |
auto[1] |
auto[0] |
53266280 |
1 |
|
T1 |
129311 |
|
T3 |
29 |
|
T4 |
709210 |
all_values[0] |
auto[1] |
auto[1] |
3035 |
1 |
|
T1 |
5 |
|
T3 |
38 |
|
T4 |
6 |