Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 577
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2637153898 Apr 28 12:58:05 PM PDT 24 Apr 28 12:58:07 PM PDT 24 116820995 ps
T508 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.229458402 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:17 PM PDT 24 391087976 ps
T509 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.711777307 Apr 28 12:58:13 PM PDT 24 Apr 28 12:58:15 PM PDT 24 17812147 ps
T510 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.313818156 Apr 28 12:58:00 PM PDT 24 Apr 28 12:58:02 PM PDT 24 34678033 ps
T511 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3848030785 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:16 PM PDT 24 31363686 ps
T512 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3709381521 Apr 28 12:57:58 PM PDT 24 Apr 28 12:57:59 PM PDT 24 67916757 ps
T513 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1990993925 Apr 28 12:58:01 PM PDT 24 Apr 28 12:58:03 PM PDT 24 38972059 ps
T514 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.37940813 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:16 PM PDT 24 1164472723 ps
T515 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.525606406 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:20 PM PDT 24 15365725 ps
T516 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.53151293 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:13 PM PDT 24 15602863 ps
T517 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2419240066 Apr 28 12:58:11 PM PDT 24 Apr 28 12:58:13 PM PDT 24 82591145 ps
T518 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2894288071 Apr 28 12:58:01 PM PDT 24 Apr 28 12:58:03 PM PDT 24 28648893 ps
T519 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.800811548 Apr 28 12:58:08 PM PDT 24 Apr 28 12:58:10 PM PDT 24 20062018 ps
T520 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4202863166 Apr 28 12:58:15 PM PDT 24 Apr 28 12:58:18 PM PDT 24 61914378 ps
T521 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.686224888 Apr 28 12:58:07 PM PDT 24 Apr 28 12:58:09 PM PDT 24 74226210 ps
T522 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2976814106 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:15 PM PDT 24 89868685 ps
T523 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.584681344 Apr 28 12:57:50 PM PDT 24 Apr 28 12:57:53 PM PDT 24 19737796 ps
T524 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.38906715 Apr 28 12:57:55 PM PDT 24 Apr 28 12:57:58 PM PDT 24 1573804811 ps
T525 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2649963204 Apr 28 12:58:13 PM PDT 24 Apr 28 12:58:15 PM PDT 24 23097356 ps
T526 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3419278295 Apr 28 12:58:07 PM PDT 24 Apr 28 12:58:09 PM PDT 24 26994579 ps
T527 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.496066218 Apr 28 12:58:00 PM PDT 24 Apr 28 12:58:01 PM PDT 24 19317112 ps
T528 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2456900361 Apr 28 12:58:07 PM PDT 24 Apr 28 12:58:08 PM PDT 24 36569780 ps
T529 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3324331318 Apr 28 12:58:08 PM PDT 24 Apr 28 12:58:09 PM PDT 24 45216146 ps
T530 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.258744578 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:17 PM PDT 24 45455910 ps
T531 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3606762540 Apr 28 12:58:11 PM PDT 24 Apr 28 12:58:13 PM PDT 24 26033352 ps
T92 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3539124074 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:20 PM PDT 24 37104811 ps
T93 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1871518020 Apr 28 12:57:54 PM PDT 24 Apr 28 12:57:55 PM PDT 24 51361280 ps
T94 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3343508886 Apr 28 12:57:45 PM PDT 24 Apr 28 12:57:47 PM PDT 24 13996265 ps
T532 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1692180143 Apr 28 12:57:58 PM PDT 24 Apr 28 12:57:59 PM PDT 24 20201518 ps
T95 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3115454752 Apr 28 12:58:05 PM PDT 24 Apr 28 12:58:06 PM PDT 24 12454752 ps
T533 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.242087777 Apr 28 12:58:11 PM PDT 24 Apr 28 12:58:13 PM PDT 24 15286362 ps
T534 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2958532591 Apr 28 12:58:13 PM PDT 24 Apr 28 12:58:16 PM PDT 24 94063195 ps
T96 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1082209670 Apr 28 12:57:49 PM PDT 24 Apr 28 12:57:51 PM PDT 24 23758037 ps
T535 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3947020047 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:15 PM PDT 24 429248488 ps
T536 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4224751078 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:20 PM PDT 24 31249562 ps
T537 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.244648641 Apr 28 12:58:08 PM PDT 24 Apr 28 12:58:10 PM PDT 24 131654424 ps
T538 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2113672630 Apr 28 12:58:07 PM PDT 24 Apr 28 12:58:08 PM PDT 24 17299086 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3072191505 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:16 PM PDT 24 32990875 ps
T540 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2439649520 Apr 28 12:58:11 PM PDT 24 Apr 28 12:58:13 PM PDT 24 16128326 ps
T541 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1731185784 Apr 28 12:57:59 PM PDT 24 Apr 28 12:58:00 PM PDT 24 30585020 ps
T542 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1385926673 Apr 28 12:57:49 PM PDT 24 Apr 28 12:57:51 PM PDT 24 21598623 ps
T543 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.581685034 Apr 28 12:57:55 PM PDT 24 Apr 28 12:57:56 PM PDT 24 15685963 ps
T544 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3477740233 Apr 28 12:58:03 PM PDT 24 Apr 28 12:58:05 PM PDT 24 315445255 ps
T545 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1251048898 Apr 28 12:58:06 PM PDT 24 Apr 28 12:58:07 PM PDT 24 118654438 ps
T546 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4070147682 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:16 PM PDT 24 83435276 ps
T547 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3616765090 Apr 28 12:57:59 PM PDT 24 Apr 28 12:58:00 PM PDT 24 83299191 ps
T548 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1070257203 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:16 PM PDT 24 35168844 ps
T549 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3972467637 Apr 28 12:57:50 PM PDT 24 Apr 28 12:57:54 PM PDT 24 115772277 ps
T550 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.33693134 Apr 28 12:58:09 PM PDT 24 Apr 28 12:58:12 PM PDT 24 1634866858 ps
T551 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4087989661 Apr 28 12:58:06 PM PDT 24 Apr 28 12:58:08 PM PDT 24 39593992 ps
T552 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1496909563 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:20 PM PDT 24 32541185 ps
T553 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4182216190 Apr 28 12:57:55 PM PDT 24 Apr 28 12:57:57 PM PDT 24 96403930 ps
T554 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4000208019 Apr 28 12:57:59 PM PDT 24 Apr 28 12:58:01 PM PDT 24 54744853 ps
T555 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3905269343 Apr 28 12:57:54 PM PDT 24 Apr 28 12:57:56 PM PDT 24 24377852 ps
T556 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.803200328 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:13 PM PDT 24 33926232 ps
T557 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1089539643 Apr 28 12:58:03 PM PDT 24 Apr 28 12:58:05 PM PDT 24 18734798 ps
T558 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3592340941 Apr 28 12:58:11 PM PDT 24 Apr 28 12:58:13 PM PDT 24 15546163 ps
T559 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1354661446 Apr 28 12:57:59 PM PDT 24 Apr 28 12:58:01 PM PDT 24 93156416 ps
T560 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3182154936 Apr 28 12:58:08 PM PDT 24 Apr 28 12:58:10 PM PDT 24 44972202 ps
T561 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4086984944 Apr 28 12:58:10 PM PDT 24 Apr 28 12:58:11 PM PDT 24 21694669 ps
T562 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3033009327 Apr 28 12:57:57 PM PDT 24 Apr 28 12:57:58 PM PDT 24 13654616 ps
T563 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1450465305 Apr 28 12:57:49 PM PDT 24 Apr 28 12:57:52 PM PDT 24 22332478 ps
T564 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2370167655 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:20 PM PDT 24 239006967 ps
T565 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4277760298 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:22 PM PDT 24 103665114 ps
T566 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3232965261 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:23 PM PDT 24 103597233 ps
T567 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2458917575 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:21 PM PDT 24 258387202 ps
T568 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3643355175 Apr 28 12:57:58 PM PDT 24 Apr 28 12:57:59 PM PDT 24 17589717 ps
T569 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3090274606 Apr 28 12:58:07 PM PDT 24 Apr 28 12:58:08 PM PDT 24 18679692 ps
T570 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2661817226 Apr 28 12:57:55 PM PDT 24 Apr 28 12:57:57 PM PDT 24 211032838 ps
T571 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2545541269 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:17 PM PDT 24 31172043 ps
T97 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3417031952 Apr 28 12:58:13 PM PDT 24 Apr 28 12:58:16 PM PDT 24 45610617 ps
T572 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2375843669 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:21 PM PDT 24 203334013 ps
T573 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3039137424 Apr 28 12:57:57 PM PDT 24 Apr 28 12:57:59 PM PDT 24 34012365 ps
T574 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3912390336 Apr 28 12:58:11 PM PDT 24 Apr 28 12:58:13 PM PDT 24 161771657 ps
T575 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1360458941 Apr 28 12:58:04 PM PDT 24 Apr 28 12:58:05 PM PDT 24 22129982 ps
T576 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1657552006 Apr 28 12:58:10 PM PDT 24 Apr 28 12:58:12 PM PDT 24 79394917 ps
T577 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1965613815 Apr 28 12:57:49 PM PDT 24 Apr 28 12:57:52 PM PDT 24 67503217 ps

Test location /workspace/coverage/default/18.rv_timer_random.3336728280
Short name T1
Test name
Test status
Simulation time 230413080648 ps
CPU time 1138.34 seconds
Started Apr 28 02:16:54 PM PDT 24
Finished Apr 28 02:35:52 PM PDT 24
Peak memory 191256 kb
Host smart-a24a7eec-7b59-4dcc-aa11-99021a6c4351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336728280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3336728280
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2037183575
Short name T12
Test name
Test status
Simulation time 356961398403 ps
CPU time 609.12 seconds
Started Apr 28 02:17:09 PM PDT 24
Finished Apr 28 02:27:20 PM PDT 24
Peak memory 210172 kb
Host smart-c765bbf0-1b34-4ca8-8754-323b66f51dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037183575 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2037183575
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1710589903
Short name T126
Test name
Test status
Simulation time 1684710973070 ps
CPU time 4727.27 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 03:36:11 PM PDT 24
Peak memory 191144 kb
Host smart-c940e98e-af16-4ab0-815e-719da19cf9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710589903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1710589903
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3232065143
Short name T44
Test name
Test status
Simulation time 995830320395 ps
CPU time 2220.24 seconds
Started Apr 28 02:17:27 PM PDT 24
Finished Apr 28 02:54:28 PM PDT 24
Peak memory 191288 kb
Host smart-935a0bcd-8c92-4d09-9307-08cc67f427e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232065143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3232065143
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2893500228
Short name T28
Test name
Test status
Simulation time 255787792 ps
CPU time 1.1 seconds
Started Apr 28 12:58:02 PM PDT 24
Finished Apr 28 12:58:03 PM PDT 24
Peak memory 183172 kb
Host smart-a3dc13c9-fab6-4f36-97a9-6cd7b3539c38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893500228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2893500228
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4019977540
Short name T10
Test name
Test status
Simulation time 704287641210 ps
CPU time 1833.41 seconds
Started Apr 28 02:17:14 PM PDT 24
Finished Apr 28 02:47:48 PM PDT 24
Peak memory 191080 kb
Host smart-6ba01c9e-f19d-43b8-8c17-a583b7c7a87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019977540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4019977540
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1223998281
Short name T33
Test name
Test status
Simulation time 494447700436 ps
CPU time 821 seconds
Started Apr 28 02:16:53 PM PDT 24
Finished Apr 28 02:30:34 PM PDT 24
Peak memory 195996 kb
Host smart-a4050a36-3901-45d7-ba9c-7a751ae0d821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223998281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1223998281
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1955287958
Short name T227
Test name
Test status
Simulation time 432132513558 ps
CPU time 943.22 seconds
Started Apr 28 02:16:46 PM PDT 24
Finished Apr 28 02:32:30 PM PDT 24
Peak memory 195968 kb
Host smart-35f9c3a9-632a-476b-b47c-39eb1d343812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955287958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1955287958
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3268786957
Short name T64
Test name
Test status
Simulation time 786379255089 ps
CPU time 1001.42 seconds
Started Apr 28 02:17:26 PM PDT 24
Finished Apr 28 02:34:08 PM PDT 24
Peak memory 191236 kb
Host smart-af2b6acb-141f-4dfc-928b-e453e7920ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268786957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3268786957
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2721672829
Short name T199
Test name
Test status
Simulation time 1330284152599 ps
CPU time 3116.35 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 03:08:33 PM PDT 24
Peak memory 191276 kb
Host smart-a300dee9-c17b-4bcc-8da3-ded43d912f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721672829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2721672829
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.185254962
Short name T119
Test name
Test status
Simulation time 1068842785494 ps
CPU time 986.31 seconds
Started Apr 28 02:17:06 PM PDT 24
Finished Apr 28 02:33:33 PM PDT 24
Peak memory 191240 kb
Host smart-032b32c1-c9dd-421f-bdf8-4bc522c0413e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185254962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
185254962
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2540004655
Short name T16
Test name
Test status
Simulation time 93345362 ps
CPU time 0.89 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 214504 kb
Host smart-357f8b02-4482-4d1d-8672-5dfcb27993cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540004655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2540004655
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.352501896
Short name T53
Test name
Test status
Simulation time 44339228 ps
CPU time 0.87 seconds
Started Apr 28 12:57:59 PM PDT 24
Finished Apr 28 12:58:00 PM PDT 24
Peak memory 192612 kb
Host smart-1624e23e-9149-4b90-ad35-6f0954c546a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352501896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.352501896
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.238154309
Short name T156
Test name
Test status
Simulation time 632090463414 ps
CPU time 1181.18 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:36:40 PM PDT 24
Peak memory 191268 kb
Host smart-611e2c1f-2f6f-4ae0-9bb8-db74e7e7e949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238154309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
238154309
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.519229532
Short name T67
Test name
Test status
Simulation time 327499977263 ps
CPU time 496.86 seconds
Started Apr 28 02:16:51 PM PDT 24
Finished Apr 28 02:25:09 PM PDT 24
Peak memory 191256 kb
Host smart-6e2d630f-92ef-4434-9459-e4f1335590b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519229532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
519229532
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2298275999
Short name T247
Test name
Test status
Simulation time 828001034688 ps
CPU time 951.06 seconds
Started Apr 28 02:16:40 PM PDT 24
Finished Apr 28 02:32:32 PM PDT 24
Peak memory 191112 kb
Host smart-fb5a8222-bc32-4ef0-9dbc-1f1c359b7169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298275999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2298275999
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2700830348
Short name T158
Test name
Test status
Simulation time 526020470769 ps
CPU time 2242.93 seconds
Started Apr 28 02:17:27 PM PDT 24
Finished Apr 28 02:54:51 PM PDT 24
Peak memory 196004 kb
Host smart-d22b11c7-22e9-4084-a408-f2426fcc3d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700830348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2700830348
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.516429997
Short name T262
Test name
Test status
Simulation time 412006344216 ps
CPU time 1061.59 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:34:29 PM PDT 24
Peak memory 196660 kb
Host smart-430f090e-dbbd-4b3a-be09-5c1676b34eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516429997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
516429997
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/189.rv_timer_random.10076536
Short name T258
Test name
Test status
Simulation time 163952680339 ps
CPU time 518.26 seconds
Started Apr 28 02:18:58 PM PDT 24
Finished Apr 28 02:27:37 PM PDT 24
Peak memory 191296 kb
Host smart-1f077ed4-6ba4-4422-8b40-43c68413f2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10076536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.10076536
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3288663967
Short name T169
Test name
Test status
Simulation time 253181448133 ps
CPU time 993.96 seconds
Started Apr 28 02:17:04 PM PDT 24
Finished Apr 28 02:33:40 PM PDT 24
Peak memory 195428 kb
Host smart-c85555f5-f0c5-4fe9-9eab-7098e9d3a045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288663967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3288663967
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.946067434
Short name T56
Test name
Test status
Simulation time 730692569363 ps
CPU time 434.48 seconds
Started Apr 28 02:17:38 PM PDT 24
Finished Apr 28 02:24:53 PM PDT 24
Peak memory 191272 kb
Host smart-893ee0a9-95f7-4f5a-8b9d-ebe294f3855b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946067434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.946067434
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1614787093
Short name T214
Test name
Test status
Simulation time 187932520795 ps
CPU time 530.54 seconds
Started Apr 28 02:16:41 PM PDT 24
Finished Apr 28 02:25:32 PM PDT 24
Peak memory 191280 kb
Host smart-d0f09dc4-9328-42b7-9688-cc54541cb94c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614787093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1614787093
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.3943081252
Short name T181
Test name
Test status
Simulation time 126165820763 ps
CPU time 217.66 seconds
Started Apr 28 02:18:11 PM PDT 24
Finished Apr 28 02:21:49 PM PDT 24
Peak memory 191268 kb
Host smart-9beff341-8d2d-4786-835e-79f4948b54eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943081252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3943081252
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3818069767
Short name T42
Test name
Test status
Simulation time 559837243009 ps
CPU time 1407.88 seconds
Started Apr 28 02:16:52 PM PDT 24
Finished Apr 28 02:40:21 PM PDT 24
Peak memory 194836 kb
Host smart-df0c00e1-9d80-4cd2-8060-3adb78fa77df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818069767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3818069767
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/193.rv_timer_random.3515153014
Short name T152
Test name
Test status
Simulation time 379558991812 ps
CPU time 352.42 seconds
Started Apr 28 02:18:57 PM PDT 24
Finished Apr 28 02:24:50 PM PDT 24
Peak memory 195068 kb
Host smart-b950d59f-d0dd-4f24-baaf-97840b6711c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515153014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3515153014
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2467369358
Short name T145
Test name
Test status
Simulation time 1876820124081 ps
CPU time 814.73 seconds
Started Apr 28 02:16:49 PM PDT 24
Finished Apr 28 02:30:24 PM PDT 24
Peak memory 195324 kb
Host smart-f8b7ba97-3b1b-4211-8a7b-e329b289125d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467369358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2467369358
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.1864903200
Short name T251
Test name
Test status
Simulation time 139244957519 ps
CPU time 236.89 seconds
Started Apr 28 02:18:46 PM PDT 24
Finished Apr 28 02:22:43 PM PDT 24
Peak memory 191100 kb
Host smart-61a0e0d0-b5da-44f6-a79a-f814366052e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864903200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1864903200
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.110115373
Short name T201
Test name
Test status
Simulation time 580497080066 ps
CPU time 2354.42 seconds
Started Apr 28 02:18:58 PM PDT 24
Finished Apr 28 02:58:13 PM PDT 24
Peak memory 191268 kb
Host smart-8ea85707-2f07-4004-a5f9-9e0224dde96d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110115373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.110115373
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2523210056
Short name T84
Test name
Test status
Simulation time 12039567 ps
CPU time 0.57 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 182748 kb
Host smart-8530ad3c-ac72-4c15-928c-9530df9b4f3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523210056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2523210056
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.29984810
Short name T212
Test name
Test status
Simulation time 699792762351 ps
CPU time 720 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:28:40 PM PDT 24
Peak memory 183008 kb
Host smart-d25e38cb-f566-46a4-955b-02149d8d4a1d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29984810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
rv_timer_cfg_update_on_fly.29984810
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.4108612030
Short name T232
Test name
Test status
Simulation time 157368768727 ps
CPU time 238.62 seconds
Started Apr 28 02:17:50 PM PDT 24
Finished Apr 28 02:21:49 PM PDT 24
Peak memory 191220 kb
Host smart-347ba1e2-25e2-474e-9f07-19bc528656f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108612030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4108612030
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3558802986
Short name T133
Test name
Test status
Simulation time 441949071663 ps
CPU time 209.45 seconds
Started Apr 28 02:17:57 PM PDT 24
Finished Apr 28 02:21:27 PM PDT 24
Peak memory 191220 kb
Host smart-96df8072-49a4-4882-8152-6de5c66031f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558802986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3558802986
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.785599585
Short name T270
Test name
Test status
Simulation time 293537406735 ps
CPU time 382.81 seconds
Started Apr 28 02:17:58 PM PDT 24
Finished Apr 28 02:24:21 PM PDT 24
Peak memory 191252 kb
Host smart-1144a178-f0a2-44e8-9fdf-5ad1751f7663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785599585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.785599585
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.941423201
Short name T338
Test name
Test status
Simulation time 220736575526 ps
CPU time 1078.02 seconds
Started Apr 28 02:18:43 PM PDT 24
Finished Apr 28 02:36:41 PM PDT 24
Peak memory 191212 kb
Host smart-83bfc521-8b83-4857-9e2c-4e580f309dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941423201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.941423201
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2452538464
Short name T151
Test name
Test status
Simulation time 192813368241 ps
CPU time 426.16 seconds
Started Apr 28 02:18:52 PM PDT 24
Finished Apr 28 02:25:59 PM PDT 24
Peak memory 191216 kb
Host smart-9c16dad9-f3cc-4c91-95c2-61977965ddf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452538464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2452538464
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3290859661
Short name T150
Test name
Test status
Simulation time 294466475036 ps
CPU time 263.47 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:21:32 PM PDT 24
Peak memory 195964 kb
Host smart-cebd35f7-06e0-4e34-9aa4-09269b27c217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290859661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3290859661
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1598102712
Short name T313
Test name
Test status
Simulation time 464321854906 ps
CPU time 450.25 seconds
Started Apr 28 02:17:14 PM PDT 24
Finished Apr 28 02:24:46 PM PDT 24
Peak memory 194216 kb
Host smart-ac214c4d-7c55-4ef4-9e9c-d43801e795e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598102712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1598102712
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1781128872
Short name T185
Test name
Test status
Simulation time 581833522874 ps
CPU time 497.44 seconds
Started Apr 28 02:17:19 PM PDT 24
Finished Apr 28 02:25:36 PM PDT 24
Peak memory 191252 kb
Host smart-d42c10e1-243b-495c-b546-378780646f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781128872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1781128872
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.2472870686
Short name T202
Test name
Test status
Simulation time 233882206223 ps
CPU time 683.45 seconds
Started Apr 28 02:17:53 PM PDT 24
Finished Apr 28 02:29:17 PM PDT 24
Peak memory 191260 kb
Host smart-de9ae0f1-6541-4720-b0b1-3b86a27248cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472870686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2472870686
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2425921202
Short name T280
Test name
Test status
Simulation time 199253886174 ps
CPU time 503.78 seconds
Started Apr 28 02:18:19 PM PDT 24
Finished Apr 28 02:26:43 PM PDT 24
Peak memory 191284 kb
Host smart-29985962-3550-4b27-8514-5d4528b0b0d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425921202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2425921202
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.512074962
Short name T220
Test name
Test status
Simulation time 159631126353 ps
CPU time 293.18 seconds
Started Apr 28 02:18:29 PM PDT 24
Finished Apr 28 02:23:22 PM PDT 24
Peak memory 183008 kb
Host smart-ab01654f-4a7f-466f-8eef-258d520a8461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512074962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.512074962
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.3210819345
Short name T289
Test name
Test status
Simulation time 427674774034 ps
CPU time 398.95 seconds
Started Apr 28 02:18:35 PM PDT 24
Finished Apr 28 02:25:14 PM PDT 24
Peak memory 191136 kb
Host smart-dc528d4d-b4d5-49e7-b9e0-f1039bc7f12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210819345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3210819345
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.215630383
Short name T146
Test name
Test status
Simulation time 72977290332 ps
CPU time 111.78 seconds
Started Apr 28 02:17:04 PM PDT 24
Finished Apr 28 02:18:57 PM PDT 24
Peak memory 183076 kb
Host smart-ade65859-b46a-4dac-be91-cd28bd251b20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215630383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.215630383
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.219828024
Short name T66
Test name
Test status
Simulation time 3327248638773 ps
CPU time 762.49 seconds
Started Apr 28 02:17:06 PM PDT 24
Finished Apr 28 02:29:49 PM PDT 24
Peak memory 191192 kb
Host smart-55738c7a-e091-4f08-940d-63af7aa70cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219828024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
219828024
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3695257229
Short name T123
Test name
Test status
Simulation time 1426415886707 ps
CPU time 753.73 seconds
Started Apr 28 02:17:11 PM PDT 24
Finished Apr 28 02:29:46 PM PDT 24
Peak memory 191272 kb
Host smart-87d8828d-6384-48c7-b7a0-3b77547f55c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695257229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3695257229
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/55.rv_timer_random.2366640707
Short name T200
Test name
Test status
Simulation time 1160891521053 ps
CPU time 485.31 seconds
Started Apr 28 02:17:22 PM PDT 24
Finished Apr 28 02:25:28 PM PDT 24
Peak memory 191212 kb
Host smart-aaf2530c-e3ce-4d13-a94a-de6247e86328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366640707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2366640707
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1638402789
Short name T187
Test name
Test status
Simulation time 508121534480 ps
CPU time 317.28 seconds
Started Apr 28 02:17:35 PM PDT 24
Finished Apr 28 02:22:52 PM PDT 24
Peak memory 191212 kb
Host smart-a6d1692c-9a46-4351-8fb0-c6570fa09006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638402789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1638402789
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.677437413
Short name T328
Test name
Test status
Simulation time 308884424322 ps
CPU time 730.56 seconds
Started Apr 28 02:17:34 PM PDT 24
Finished Apr 28 02:29:45 PM PDT 24
Peak memory 191084 kb
Host smart-b6fafbd1-80da-476d-9812-ac6a864c56a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677437413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.677437413
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1445193955
Short name T216
Test name
Test status
Simulation time 152126367817 ps
CPU time 672.81 seconds
Started Apr 28 02:17:50 PM PDT 24
Finished Apr 28 02:29:03 PM PDT 24
Peak memory 191264 kb
Host smart-4ddb6818-2e5e-4ed7-b56d-92ca1144ab54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445193955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1445193955
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2496266828
Short name T141
Test name
Test status
Simulation time 90432804274 ps
CPU time 471.95 seconds
Started Apr 28 02:18:14 PM PDT 24
Finished Apr 28 02:26:06 PM PDT 24
Peak memory 191260 kb
Host smart-ade3e954-14b8-466b-be82-8e1f8115d4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496266828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2496266828
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.201636215
Short name T140
Test name
Test status
Simulation time 157243782683 ps
CPU time 696.04 seconds
Started Apr 28 02:18:15 PM PDT 24
Finished Apr 28 02:29:52 PM PDT 24
Peak memory 191188 kb
Host smart-2bea09e2-6227-4d21-a777-bd7ef4275911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201636215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.201636215
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1373802621
Short name T252
Test name
Test status
Simulation time 88314031857 ps
CPU time 543.32 seconds
Started Apr 28 02:18:23 PM PDT 24
Finished Apr 28 02:27:27 PM PDT 24
Peak memory 191244 kb
Host smart-4be5b717-b813-411c-9d72-463766d50c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373802621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1373802621
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3105391011
Short name T346
Test name
Test status
Simulation time 1853520659807 ps
CPU time 1680.22 seconds
Started Apr 28 02:18:48 PM PDT 24
Finished Apr 28 02:46:48 PM PDT 24
Peak memory 191208 kb
Host smart-90552ea9-1b0e-41b6-9489-d7c3a058c635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105391011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3105391011
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.1714989780
Short name T127
Test name
Test status
Simulation time 489403841586 ps
CPU time 231.36 seconds
Started Apr 28 02:17:02 PM PDT 24
Finished Apr 28 02:20:53 PM PDT 24
Peak memory 191092 kb
Host smart-8ffd424d-2e22-4e0e-ae8d-da848e0b6b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714989780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1714989780
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3642457429
Short name T260
Test name
Test status
Simulation time 994526703017 ps
CPU time 903.1 seconds
Started Apr 28 02:17:14 PM PDT 24
Finished Apr 28 02:32:17 PM PDT 24
Peak memory 183072 kb
Host smart-7029b337-bca4-458d-894e-b9d1aa87fec4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642457429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3642457429
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/58.rv_timer_random.2158330915
Short name T5
Test name
Test status
Simulation time 397314735095 ps
CPU time 409.51 seconds
Started Apr 28 02:17:27 PM PDT 24
Finished Apr 28 02:24:17 PM PDT 24
Peak memory 191236 kb
Host smart-0ba4a12e-a306-49b1-9be3-aea18acfffa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158330915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2158330915
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2562719534
Short name T163
Test name
Test status
Simulation time 61195106389 ps
CPU time 1049.65 seconds
Started Apr 28 02:17:40 PM PDT 24
Finished Apr 28 02:35:10 PM PDT 24
Peak memory 191152 kb
Host smart-a73e7979-8e48-4615-ae1f-3b9eb2d9723c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562719534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2562719534
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1088014460
Short name T115
Test name
Test status
Simulation time 434847079 ps
CPU time 1.41 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:11 PM PDT 24
Peak memory 195324 kb
Host smart-06cdb959-1aa0-46ec-9651-332ba579397d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088014460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1088014460
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_timer_random.1786651222
Short name T153
Test name
Test status
Simulation time 135072649305 ps
CPU time 457.06 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:24:26 PM PDT 24
Peak memory 191220 kb
Host smart-0e54d714-1449-4086-ab8d-c1f04beb8778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786651222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1786651222
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2417408616
Short name T24
Test name
Test status
Simulation time 414358091967 ps
CPU time 752.5 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:29:21 PM PDT 24
Peak memory 182960 kb
Host smart-92e81cdb-4c2a-49ec-a207-90992f02502d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417408616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2417408616
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/126.rv_timer_random.1982201050
Short name T250
Test name
Test status
Simulation time 161309130144 ps
CPU time 116.67 seconds
Started Apr 28 02:18:02 PM PDT 24
Finished Apr 28 02:19:59 PM PDT 24
Peak memory 191268 kb
Host smart-481c35e5-19a6-4bb4-a761-4891014de370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982201050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1982201050
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2529594147
Short name T162
Test name
Test status
Simulation time 85175479602 ps
CPU time 153.13 seconds
Started Apr 28 02:18:07 PM PDT 24
Finished Apr 28 02:20:41 PM PDT 24
Peak memory 191244 kb
Host smart-d4b915b6-e60c-4bce-9107-4d59e8bf295a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529594147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2529594147
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3347986192
Short name T321
Test name
Test status
Simulation time 83777494836 ps
CPU time 67.1 seconds
Started Apr 28 02:18:25 PM PDT 24
Finished Apr 28 02:19:33 PM PDT 24
Peak memory 191236 kb
Host smart-23264c0c-8680-40b6-b759-9b1139ec85e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347986192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3347986192
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2570376670
Short name T300
Test name
Test status
Simulation time 85910722332 ps
CPU time 2647.86 seconds
Started Apr 28 02:18:31 PM PDT 24
Finished Apr 28 03:02:40 PM PDT 24
Peak memory 191268 kb
Host smart-2c463cc9-d3b7-4144-a118-dc7d15749c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570376670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2570376670
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1339682958
Short name T43
Test name
Test status
Simulation time 130450894303 ps
CPU time 254.88 seconds
Started Apr 28 02:18:35 PM PDT 24
Finished Apr 28 02:22:50 PM PDT 24
Peak memory 191136 kb
Host smart-6a7a89f1-6974-478c-9d9f-1a1e7c06b99d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339682958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1339682958
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2233824787
Short name T246
Test name
Test status
Simulation time 92688058055 ps
CPU time 245.31 seconds
Started Apr 28 02:18:33 PM PDT 24
Finished Apr 28 02:22:39 PM PDT 24
Peak memory 191172 kb
Host smart-b70511d3-3aff-46bc-a48c-6c202116f982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233824787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2233824787
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.2121408131
Short name T128
Test name
Test status
Simulation time 692577254638 ps
CPU time 885.65 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:31:43 PM PDT 24
Peak memory 191260 kb
Host smart-4288de07-fc9f-46e1-be8f-6d4bedb8f9de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121408131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2121408131
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2674053908
Short name T326
Test name
Test status
Simulation time 1123286784789 ps
CPU time 592.38 seconds
Started Apr 28 02:17:06 PM PDT 24
Finished Apr 28 02:26:59 PM PDT 24
Peak memory 191144 kb
Host smart-f8a3b27d-f728-4f31-9073-ca111b937f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674053908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2674053908
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.4153116557
Short name T298
Test name
Test status
Simulation time 586362417539 ps
CPU time 322.36 seconds
Started Apr 28 02:17:03 PM PDT 24
Finished Apr 28 02:22:26 PM PDT 24
Peak memory 183020 kb
Host smart-b9193805-75f1-4533-8eed-5e0834c3fe73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153116557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.4153116557
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2364996288
Short name T178
Test name
Test status
Simulation time 757165139166 ps
CPU time 442 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:24:01 PM PDT 24
Peak memory 183092 kb
Host smart-112ca01c-41f1-4304-a9fa-6ef6f4d86f76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364996288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2364996288
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random.358155905
Short name T309
Test name
Test status
Simulation time 204008251776 ps
CPU time 244.45 seconds
Started Apr 28 02:17:17 PM PDT 24
Finished Apr 28 02:21:22 PM PDT 24
Peak memory 191244 kb
Host smart-f4784d9e-8004-4346-867d-89212947fb23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358155905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.358155905
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1466086416
Short name T120
Test name
Test status
Simulation time 1164269259017 ps
CPU time 836.63 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:31:20 PM PDT 24
Peak memory 191176 kb
Host smart-836f7d7b-8e9e-4e3f-b18e-0a84d3210dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466086416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1466086416
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1928098149
Short name T195
Test name
Test status
Simulation time 235825710851 ps
CPU time 1028.47 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:33:42 PM PDT 24
Peak memory 191248 kb
Host smart-78a4d719-418c-42e4-a35d-32f486fbd355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928098149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1928098149
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2545398088
Short name T361
Test name
Test status
Simulation time 39646326238 ps
CPU time 23.34 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:17:11 PM PDT 24
Peak memory 183064 kb
Host smart-8cb1fbc7-df56-4abd-85cb-7e8090f8b457
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545398088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2545398088
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.1025921877
Short name T405
Test name
Test status
Simulation time 18941425823 ps
CPU time 35.38 seconds
Started Apr 28 02:16:42 PM PDT 24
Finished Apr 28 02:17:18 PM PDT 24
Peak memory 191248 kb
Host smart-1fb7f400-7af7-4c8f-9a72-29b586a458ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025921877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1025921877
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.808564655
Short name T302
Test name
Test status
Simulation time 140222993081 ps
CPU time 348 seconds
Started Apr 28 02:17:48 PM PDT 24
Finished Apr 28 02:23:36 PM PDT 24
Peak memory 192228 kb
Host smart-59c59fb8-9d59-4864-b9c5-1aec24b09105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808564655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.808564655
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.1649443265
Short name T25
Test name
Test status
Simulation time 38728451160 ps
CPU time 35.07 seconds
Started Apr 28 02:17:53 PM PDT 24
Finished Apr 28 02:18:28 PM PDT 24
Peak memory 183048 kb
Host smart-3f2e61c6-2344-4c60-85d5-e43cf5663acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649443265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1649443265
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.188779901
Short name T342
Test name
Test status
Simulation time 2550970464 ps
CPU time 4.54 seconds
Started Apr 28 02:17:52 PM PDT 24
Finished Apr 28 02:17:57 PM PDT 24
Peak memory 182764 kb
Host smart-0d36577c-5cb7-4a2b-9c4d-7ac8ad107ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188779901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.188779901
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2936928782
Short name T345
Test name
Test status
Simulation time 434491405260 ps
CPU time 252.42 seconds
Started Apr 28 02:17:58 PM PDT 24
Finished Apr 28 02:22:11 PM PDT 24
Peak memory 191252 kb
Host smart-90947487-bf13-48e5-80e2-f4c117d37d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936928782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2936928782
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2819053123
Short name T231
Test name
Test status
Simulation time 306551723492 ps
CPU time 1411.33 seconds
Started Apr 28 02:18:02 PM PDT 24
Finished Apr 28 02:41:34 PM PDT 24
Peak memory 194816 kb
Host smart-bd998f89-fe7a-427f-9944-2c484273005b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819053123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2819053123
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.219502480
Short name T20
Test name
Test status
Simulation time 467026700516 ps
CPU time 275.85 seconds
Started Apr 28 02:18:14 PM PDT 24
Finished Apr 28 02:22:50 PM PDT 24
Peak memory 191212 kb
Host smart-8bd12b6a-5274-45b2-bfb2-00f6a192b724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219502480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.219502480
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.450850013
Short name T269
Test name
Test status
Simulation time 367839601687 ps
CPU time 631.49 seconds
Started Apr 28 02:18:19 PM PDT 24
Finished Apr 28 02:28:51 PM PDT 24
Peak memory 191176 kb
Host smart-51c8f3f6-f0dc-4345-affc-e41e743484d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450850013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.450850013
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.786320902
Short name T242
Test name
Test status
Simulation time 205151545252 ps
CPU time 520.53 seconds
Started Apr 28 02:18:24 PM PDT 24
Finished Apr 28 02:27:04 PM PDT 24
Peak memory 191236 kb
Host smart-77c77889-87e6-4fc3-9dc9-8b76d22e6661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786320902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.786320902
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3286910611
Short name T186
Test name
Test status
Simulation time 144068466979 ps
CPU time 193.02 seconds
Started Apr 28 02:18:26 PM PDT 24
Finished Apr 28 02:21:39 PM PDT 24
Peak memory 194608 kb
Host smart-e79c9736-3610-41ce-b265-b039c336f27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286910611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3286910611
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3888496183
Short name T347
Test name
Test status
Simulation time 391733274651 ps
CPU time 164.27 seconds
Started Apr 28 02:16:48 PM PDT 24
Finished Apr 28 02:19:33 PM PDT 24
Peak memory 191260 kb
Host smart-3e96b427-b350-42f5-81d9-b0d1ff75dfef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888496183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3888496183
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2195702966
Short name T331
Test name
Test status
Simulation time 612204253086 ps
CPU time 464.1 seconds
Started Apr 28 02:18:28 PM PDT 24
Finished Apr 28 02:26:13 PM PDT 24
Peak memory 191236 kb
Host smart-5fa04a60-e4e1-4215-98be-d031fa880d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195702966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2195702966
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.858011686
Short name T406
Test name
Test status
Simulation time 230039842043 ps
CPU time 94.24 seconds
Started Apr 28 02:18:28 PM PDT 24
Finished Apr 28 02:20:03 PM PDT 24
Peak memory 191244 kb
Host smart-71d3c442-5645-4dbe-b03a-2f7ab9762bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858011686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.858011686
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2828836317
Short name T80
Test name
Test status
Simulation time 27470751811 ps
CPU time 102.99 seconds
Started Apr 28 02:16:52 PM PDT 24
Finished Apr 28 02:18:36 PM PDT 24
Peak memory 191212 kb
Host smart-fba85ed1-9691-4c5a-aef5-a1226b4cf969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828836317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2828836317
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/165.rv_timer_random.2895436354
Short name T22
Test name
Test status
Simulation time 127934108379 ps
CPU time 104.75 seconds
Started Apr 28 02:18:35 PM PDT 24
Finished Apr 28 02:20:21 PM PDT 24
Peak memory 191128 kb
Host smart-d01a8547-f130-43b3-a583-f90d90a88610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895436354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2895436354
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3231247549
Short name T99
Test name
Test status
Simulation time 86729401022 ps
CPU time 550.58 seconds
Started Apr 28 02:18:36 PM PDT 24
Finished Apr 28 02:27:47 PM PDT 24
Peak memory 191284 kb
Host smart-ca2b9027-590b-45ee-9faa-31b805a4c8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231247549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3231247549
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3601577604
Short name T105
Test name
Test status
Simulation time 45800236479 ps
CPU time 295.69 seconds
Started Apr 28 02:18:38 PM PDT 24
Finished Apr 28 02:23:34 PM PDT 24
Peak memory 191252 kb
Host smart-e3d5bf25-ac7a-41a1-a410-5d67c09a4a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601577604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3601577604
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4063956868
Short name T57
Test name
Test status
Simulation time 587878644013 ps
CPU time 655.04 seconds
Started Apr 28 02:18:44 PM PDT 24
Finished Apr 28 02:29:40 PM PDT 24
Peak memory 191280 kb
Host smart-ad70e0a3-fa50-4a51-8c56-b499cabb5ac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063956868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4063956868
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3573520835
Short name T248
Test name
Test status
Simulation time 98296475157 ps
CPU time 1004.76 seconds
Started Apr 28 02:18:52 PM PDT 24
Finished Apr 28 02:35:38 PM PDT 24
Peak memory 191244 kb
Host smart-929be918-9496-4565-aae2-9278d659b81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573520835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3573520835
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.309164991
Short name T238
Test name
Test status
Simulation time 167622251911 ps
CPU time 78.06 seconds
Started Apr 28 02:17:00 PM PDT 24
Finished Apr 28 02:18:18 PM PDT 24
Peak memory 191152 kb
Host smart-0acd89d0-0f3e-45f8-b309-c8b9dd0990e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309164991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.309164991
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1892226039
Short name T180
Test name
Test status
Simulation time 1007494317673 ps
CPU time 203.43 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:20:22 PM PDT 24
Peak memory 191236 kb
Host smart-950e1fed-a368-4f78-8d63-8e871262ac1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892226039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1892226039
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2917680701
Short name T356
Test name
Test status
Simulation time 213097117710 ps
CPU time 337.17 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:22:35 PM PDT 24
Peak memory 191208 kb
Host smart-9fac19c0-cfce-4575-b69b-f47725f70853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917680701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2917680701
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1119701502
Short name T330
Test name
Test status
Simulation time 839292534523 ps
CPU time 264.11 seconds
Started Apr 28 02:16:56 PM PDT 24
Finished Apr 28 02:21:21 PM PDT 24
Peak memory 183052 kb
Host smart-07963579-59c8-4e78-ab89-6f282e7cb8a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119701502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1119701502
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.2864188592
Short name T129
Test name
Test status
Simulation time 332105338072 ps
CPU time 95.4 seconds
Started Apr 28 02:17:19 PM PDT 24
Finished Apr 28 02:18:55 PM PDT 24
Peak memory 191236 kb
Host smart-e20b7457-15f7-44fa-b981-2fb824ff0170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864188592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2864188592
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2082820776
Short name T275
Test name
Test status
Simulation time 309618257867 ps
CPU time 442.68 seconds
Started Apr 28 02:17:10 PM PDT 24
Finished Apr 28 02:24:33 PM PDT 24
Peak memory 191260 kb
Host smart-1f7c561e-3552-444c-9c2d-29f2c20e0f7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082820776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2082820776
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1528828592
Short name T197
Test name
Test status
Simulation time 1009344292872 ps
CPU time 540.81 seconds
Started Apr 28 02:17:12 PM PDT 24
Finished Apr 28 02:26:14 PM PDT 24
Peak memory 183020 kb
Host smart-83fa5fa7-8af7-475f-a35e-3368c1130f2a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528828592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1528828592
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2849119353
Short name T73
Test name
Test status
Simulation time 15636361494 ps
CPU time 22.29 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:17:46 PM PDT 24
Peak memory 182980 kb
Host smart-f3b8c14f-39b9-4b86-95a9-cebe424ecf91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849119353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2849119353
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random.2148342727
Short name T285
Test name
Test status
Simulation time 322085699403 ps
CPU time 159.28 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:19:19 PM PDT 24
Peak memory 191240 kb
Host smart-2461f484-3ee5-457a-8c84-18b51add8ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148342727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2148342727
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.4235403495
Short name T131
Test name
Test status
Simulation time 45205400008 ps
CPU time 79.38 seconds
Started Apr 28 02:17:22 PM PDT 24
Finished Apr 28 02:18:43 PM PDT 24
Peak memory 193720 kb
Host smart-cb24e342-98ca-4d89-9b0b-ef4dc5a5e2fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235403495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.4235403495
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.641049756
Short name T228
Test name
Test status
Simulation time 609977957491 ps
CPU time 256.8 seconds
Started Apr 28 02:17:30 PM PDT 24
Finished Apr 28 02:21:47 PM PDT 24
Peak memory 191212 kb
Host smart-e0c9d6b0-984c-4dbd-b57a-7f14d3a05e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641049756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.641049756
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.4164060899
Short name T355
Test name
Test status
Simulation time 633979094019 ps
CPU time 418.71 seconds
Started Apr 28 02:17:34 PM PDT 24
Finished Apr 28 02:24:33 PM PDT 24
Peak memory 191240 kb
Host smart-54667cd2-dbed-4f4b-b210-7bfae9626d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164060899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4164060899
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2043008231
Short name T90
Test name
Test status
Simulation time 141034682 ps
CPU time 0.84 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:52 PM PDT 24
Peak memory 192612 kb
Host smart-075bdc48-f0e8-44a7-884b-9d9c11c20f60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043008231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2043008231
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1965613815
Short name T577
Test name
Test status
Simulation time 67503217 ps
CPU time 1.38 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:52 PM PDT 24
Peak memory 191024 kb
Host smart-55a4dcba-fb3c-46ae-a7a1-82288a395675
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965613815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1965613815
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1385926673
Short name T542
Test name
Test status
Simulation time 21598623 ps
CPU time 0.54 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:51 PM PDT 24
Peak memory 182184 kb
Host smart-52484bfe-57d8-4d33-84f0-d712206591ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385926673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1385926673
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1794004928
Short name T502
Test name
Test status
Simulation time 115826450 ps
CPU time 1.45 seconds
Started Apr 28 12:57:51 PM PDT 24
Finished Apr 28 12:57:54 PM PDT 24
Peak memory 197624 kb
Host smart-e10394bd-aa8e-4251-bb66-55628b92409f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794004928 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1794004928
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3343508886
Short name T94
Test name
Test status
Simulation time 13996265 ps
CPU time 0.54 seconds
Started Apr 28 12:57:45 PM PDT 24
Finished Apr 28 12:57:47 PM PDT 24
Peak memory 182600 kb
Host smart-0e7123a0-c3b9-4583-b6a8-57775d7d9670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343508886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3343508886
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.191603130
Short name T499
Test name
Test status
Simulation time 16392152 ps
CPU time 0.56 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:51 PM PDT 24
Peak memory 182576 kb
Host smart-8177a2b0-8f15-4d74-9250-38c8f2ff5d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191603130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.191603130
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1995863364
Short name T112
Test name
Test status
Simulation time 27011694 ps
CPU time 0.7 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:51 PM PDT 24
Peak memory 192808 kb
Host smart-5a1907f6-db67-484f-ac78-4c6785d131ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995863364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1995863364
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3972467637
Short name T549
Test name
Test status
Simulation time 115772277 ps
CPU time 1.84 seconds
Started Apr 28 12:57:50 PM PDT 24
Finished Apr 28 12:57:54 PM PDT 24
Peak memory 197628 kb
Host smart-e883bbbf-d084-4dd0-9de7-26c805de0711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972467637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3972467637
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2790979255
Short name T116
Test name
Test status
Simulation time 72603926 ps
CPU time 1.06 seconds
Started Apr 28 12:57:51 PM PDT 24
Finished Apr 28 12:57:54 PM PDT 24
Peak memory 195136 kb
Host smart-d1aa7689-d160-42fd-bb7f-f2b0ab23d4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790979255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2790979255
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3736683555
Short name T494
Test name
Test status
Simulation time 40177076 ps
CPU time 0.61 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:52 PM PDT 24
Peak memory 182672 kb
Host smart-0c77bea1-ff71-41e3-84df-17ec723a1924
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736683555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3736683555
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2683772219
Short name T478
Test name
Test status
Simulation time 968988216 ps
CPU time 1.56 seconds
Started Apr 28 12:58:01 PM PDT 24
Finished Apr 28 12:58:04 PM PDT 24
Peak memory 193288 kb
Host smart-2fb95f31-aab6-46b8-a0ac-aad86d27070e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683772219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2683772219
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1990993925
Short name T513
Test name
Test status
Simulation time 38972059 ps
CPU time 0.55 seconds
Started Apr 28 12:58:01 PM PDT 24
Finished Apr 28 12:58:03 PM PDT 24
Peak memory 182300 kb
Host smart-a4652154-7824-402b-8418-317f6fc5c255
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990993925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1990993925
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.584681344
Short name T523
Test name
Test status
Simulation time 19737796 ps
CPU time 0.61 seconds
Started Apr 28 12:57:50 PM PDT 24
Finished Apr 28 12:57:53 PM PDT 24
Peak memory 193944 kb
Host smart-3cb8b84a-d07d-4a02-ae47-8aabedca25f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584681344 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.584681344
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3787228868
Short name T485
Test name
Test status
Simulation time 74886365 ps
CPU time 0.55 seconds
Started Apr 28 12:57:55 PM PDT 24
Finished Apr 28 12:57:56 PM PDT 24
Peak memory 182580 kb
Host smart-b323b282-70aa-4c19-a566-48ad38f649bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787228868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3787228868
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3905269343
Short name T555
Test name
Test status
Simulation time 24377852 ps
CPU time 0.57 seconds
Started Apr 28 12:57:54 PM PDT 24
Finished Apr 28 12:57:56 PM PDT 24
Peak memory 182560 kb
Host smart-55883410-4644-4de3-908e-508033a71581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905269343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3905269343
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.771368647
Short name T111
Test name
Test status
Simulation time 21033605 ps
CPU time 0.61 seconds
Started Apr 28 12:57:52 PM PDT 24
Finished Apr 28 12:57:54 PM PDT 24
Peak memory 191616 kb
Host smart-60622387-04d3-4a2d-8c32-bb8a744723ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771368647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.771368647
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1940679767
Short name T482
Test name
Test status
Simulation time 114232741 ps
CPU time 1.56 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:53 PM PDT 24
Peak memory 197496 kb
Host smart-94fbbe3f-442b-4310-a756-a1ddf47b18a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940679767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1940679767
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4182216190
Short name T553
Test name
Test status
Simulation time 96403930 ps
CPU time 1.27 seconds
Started Apr 28 12:57:55 PM PDT 24
Finished Apr 28 12:57:57 PM PDT 24
Peak memory 183220 kb
Host smart-9f35be9b-6955-4805-a752-0c50494fb64a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182216190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4182216190
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3845254832
Short name T462
Test name
Test status
Simulation time 23962066 ps
CPU time 1.09 seconds
Started Apr 28 12:58:04 PM PDT 24
Finished Apr 28 12:58:06 PM PDT 24
Peak memory 197440 kb
Host smart-d5eff1cd-f1ab-4a6c-8c1f-bfebf20ace63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845254832 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3845254832
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.338772687
Short name T31
Test name
Test status
Simulation time 16117786 ps
CPU time 0.54 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:09 PM PDT 24
Peak memory 182676 kb
Host smart-59cc0cb6-1c26-44d8-a91d-7b899ffe036c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338772687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.338772687
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3703925791
Short name T472
Test name
Test status
Simulation time 46815467 ps
CPU time 0.52 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 182516 kb
Host smart-1429263a-1f5e-4c2d-b4d3-0b73f1e44861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703925791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3703925791
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2159538598
Short name T107
Test name
Test status
Simulation time 56308355 ps
CPU time 0.59 seconds
Started Apr 28 12:58:05 PM PDT 24
Finished Apr 28 12:58:06 PM PDT 24
Peak memory 191348 kb
Host smart-8de4e768-b228-4bfd-880f-5b6cda42ca23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159538598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2159538598
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3039137424
Short name T573
Test name
Test status
Simulation time 34012365 ps
CPU time 1.61 seconds
Started Apr 28 12:57:57 PM PDT 24
Finished Apr 28 12:57:59 PM PDT 24
Peak memory 197648 kb
Host smart-e0a21631-3b23-4596-ab28-238a2448efd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039137424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3039137424
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3109376752
Short name T54
Test name
Test status
Simulation time 951384706 ps
CPU time 1.34 seconds
Started Apr 28 12:58:06 PM PDT 24
Finished Apr 28 12:58:08 PM PDT 24
Peak memory 195524 kb
Host smart-26d99fb5-00d9-4880-9a46-d5d6db656b37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109376752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3109376752
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1251048898
Short name T545
Test name
Test status
Simulation time 118654438 ps
CPU time 0.96 seconds
Started Apr 28 12:58:06 PM PDT 24
Finished Apr 28 12:58:07 PM PDT 24
Peak memory 197296 kb
Host smart-0d57d826-2504-412f-8068-0fb6134e68eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251048898 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1251048898
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1093297224
Short name T113
Test name
Test status
Simulation time 42600410 ps
CPU time 0.55 seconds
Started Apr 28 12:58:01 PM PDT 24
Finished Apr 28 12:58:03 PM PDT 24
Peak memory 182720 kb
Host smart-f49edb83-a727-4088-bc1a-819f64f38b79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093297224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1093297224
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.244648641
Short name T537
Test name
Test status
Simulation time 131654424 ps
CPU time 0.55 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:10 PM PDT 24
Peak memory 182504 kb
Host smart-ad766d81-b870-4ceb-9686-85388efbe7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244648641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.244648641
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2950755848
Short name T501
Test name
Test status
Simulation time 19690550 ps
CPU time 0.81 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:12 PM PDT 24
Peak memory 191624 kb
Host smart-1b763228-8407-4b94-93be-a5849272f3b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950755848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2950755848
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.33693134
Short name T550
Test name
Test status
Simulation time 1634866858 ps
CPU time 1.99 seconds
Started Apr 28 12:58:09 PM PDT 24
Finished Apr 28 12:58:12 PM PDT 24
Peak memory 197556 kb
Host smart-702938d7-0468-477f-b348-58bf949f1d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33693134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.33693134
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2270997517
Short name T479
Test name
Test status
Simulation time 19785807 ps
CPU time 0.71 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:14 PM PDT 24
Peak memory 194468 kb
Host smart-78f8226f-c6fd-4e35-a344-7b03c04545df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270997517 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2270997517
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2268443354
Short name T91
Test name
Test status
Simulation time 17636842 ps
CPU time 0.57 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 182644 kb
Host smart-e117affc-5a88-4d20-87d1-00182f0ebf47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268443354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2268443354
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4202863166
Short name T520
Test name
Test status
Simulation time 61914378 ps
CPU time 0.55 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:18 PM PDT 24
Peak memory 182632 kb
Host smart-523065a5-9ca4-4163-b1c0-02e0ce317507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202863166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.4202863166
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1496909563
Short name T552
Test name
Test status
Simulation time 32541185 ps
CPU time 0.74 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 193272 kb
Host smart-a63d7acb-7c98-494b-84d5-401c5848d118
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496909563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1496909563
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.686224888
Short name T521
Test name
Test status
Simulation time 74226210 ps
CPU time 1.15 seconds
Started Apr 28 12:58:07 PM PDT 24
Finished Apr 28 12:58:09 PM PDT 24
Peak memory 197624 kb
Host smart-8e464125-1ba3-40f7-a070-11b843f4e627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686224888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.686224888
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3616765090
Short name T547
Test name
Test status
Simulation time 83299191 ps
CPU time 0.97 seconds
Started Apr 28 12:57:59 PM PDT 24
Finished Apr 28 12:58:00 PM PDT 24
Peak memory 197392 kb
Host smart-651e84fd-5607-4c0d-8cd8-cc09c854257b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616765090 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3616765090
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3115454752
Short name T95
Test name
Test status
Simulation time 12454752 ps
CPU time 0.54 seconds
Started Apr 28 12:58:05 PM PDT 24
Finished Apr 28 12:58:06 PM PDT 24
Peak memory 182772 kb
Host smart-3f647988-c74b-428e-88a9-b6aacde59e72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115454752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3115454752
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4288461680
Short name T459
Test name
Test status
Simulation time 50805280 ps
CPU time 0.56 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:10 PM PDT 24
Peak memory 182136 kb
Host smart-8e2417c7-922e-477a-80b4-10ab35913ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288461680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.4288461680
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2677090316
Short name T109
Test name
Test status
Simulation time 61309566 ps
CPU time 0.77 seconds
Started Apr 28 12:58:09 PM PDT 24
Finished Apr 28 12:58:10 PM PDT 24
Peak memory 191784 kb
Host smart-d9dd7350-9ba3-4829-b90a-005ef9df1fc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677090316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2677090316
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.875470737
Short name T458
Test name
Test status
Simulation time 37257523 ps
CPU time 0.98 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 196732 kb
Host smart-2b8a1574-ddd7-4c47-abf0-81d4d56030d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875470737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.875470737
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3182154936
Short name T560
Test name
Test status
Simulation time 44972202 ps
CPU time 0.81 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:10 PM PDT 24
Peak memory 193884 kb
Host smart-6efc3c57-afe1-4e52-8ecd-5298e1de882a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182154936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3182154936
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2133186384
Short name T453
Test name
Test status
Simulation time 147096940 ps
CPU time 0.7 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:10 PM PDT 24
Peak memory 194880 kb
Host smart-fa0902a9-5d9f-4840-861d-fb7c84a80faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133186384 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2133186384
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1717589280
Short name T52
Test name
Test status
Simulation time 15562562 ps
CPU time 0.6 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:11 PM PDT 24
Peak memory 191864 kb
Host smart-eb379fc8-f370-4f9d-ad35-42b0e8756616
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717589280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1717589280
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4086984944
Short name T561
Test name
Test status
Simulation time 21694669 ps
CPU time 0.52 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:11 PM PDT 24
Peak memory 182040 kb
Host smart-b2f540cd-0ee4-4498-a9cd-edd5fa1299f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086984944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4086984944
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2545541269
Short name T571
Test name
Test status
Simulation time 31172043 ps
CPU time 0.8 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:17 PM PDT 24
Peak memory 191752 kb
Host smart-eae421a0-7d81-4c0d-a612-0a201cacff1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545541269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2545541269
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.401704950
Short name T477
Test name
Test status
Simulation time 1330401689 ps
CPU time 2.48 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:14 PM PDT 24
Peak memory 197704 kb
Host smart-65468852-8535-4d42-b12b-e1de4cfb488c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401704950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.401704950
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4277760298
Short name T565
Test name
Test status
Simulation time 103665114 ps
CPU time 1.34 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 195528 kb
Host smart-e242fe20-dc54-486f-8354-fa87060cb762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277760298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4277760298
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2958532591
Short name T534
Test name
Test status
Simulation time 94063195 ps
CPU time 0.8 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 195212 kb
Host smart-832c9345-19d4-4722-9b36-a420691f9e4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958532591 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2958532591
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1646622452
Short name T493
Test name
Test status
Simulation time 45134990 ps
CPU time 0.56 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 182512 kb
Host smart-adce0940-8932-4b51-a3ae-79fa72fdb7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646622452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1646622452
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3132672643
Short name T505
Test name
Test status
Simulation time 156323453 ps
CPU time 0.6 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 191956 kb
Host smart-1f90375c-653b-4164-ab02-1a4e9835e90e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132672643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3132672643
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1657552006
Short name T576
Test name
Test status
Simulation time 79394917 ps
CPU time 1.23 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:12 PM PDT 24
Peak memory 197576 kb
Host smart-b4e0cc3d-a0a4-4cbd-a5d3-8b96315287b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657552006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1657552006
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2071628861
Short name T114
Test name
Test status
Simulation time 247471371 ps
CPU time 1.09 seconds
Started Apr 28 12:58:06 PM PDT 24
Finished Apr 28 12:58:08 PM PDT 24
Peak memory 183404 kb
Host smart-0deb5fdb-2974-466b-b75a-48dad911f3c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071628861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2071628861
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3595556631
Short name T468
Test name
Test status
Simulation time 71468627 ps
CPU time 0.99 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:12 PM PDT 24
Peak memory 197416 kb
Host smart-b1b354aa-b58a-4d9e-85a9-82496ae6537d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595556631 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3595556631
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.258744578
Short name T530
Test name
Test status
Simulation time 45455910 ps
CPU time 0.57 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:17 PM PDT 24
Peak memory 182708 kb
Host smart-585f9575-ce9d-4e1f-a463-bf2aee6e1f26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258744578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.258744578
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.169539528
Short name T464
Test name
Test status
Simulation time 14363643 ps
CPU time 0.53 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:09 PM PDT 24
Peak memory 181980 kb
Host smart-9824c8f1-5286-4f02-af38-98d5207c5007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169539528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.169539528
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1044504976
Short name T32
Test name
Test status
Simulation time 38444958 ps
CPU time 0.67 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 192160 kb
Host smart-5cc3d74a-d593-4ec1-8709-e47cbf9aa5f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044504976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1044504976
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4268414741
Short name T455
Test name
Test status
Simulation time 91283259 ps
CPU time 1.77 seconds
Started Apr 28 12:58:09 PM PDT 24
Finished Apr 28 12:58:12 PM PDT 24
Peak memory 197636 kb
Host smart-3341db2c-e64b-418d-bbba-bd64572f9c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268414741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4268414741
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2370167655
Short name T564
Test name
Test status
Simulation time 239006967 ps
CPU time 1.31 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 183200 kb
Host smart-61944e3a-10d5-4841-a290-81db6472e371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370167655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2370167655
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3090274606
Short name T569
Test name
Test status
Simulation time 18679692 ps
CPU time 0.64 seconds
Started Apr 28 12:58:07 PM PDT 24
Finished Apr 28 12:58:08 PM PDT 24
Peak memory 193892 kb
Host smart-1aa9de7b-adc5-4efe-82ae-cdbb256489df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090274606 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3090274606
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3539124074
Short name T92
Test name
Test status
Simulation time 37104811 ps
CPU time 0.57 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 182732 kb
Host smart-0d2f880d-7c86-481e-99f8-69a4f805edb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539124074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3539124074
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.220987500
Short name T500
Test name
Test status
Simulation time 58990903 ps
CPU time 0.57 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:18 PM PDT 24
Peak memory 182688 kb
Host smart-58cf76c2-7441-4906-89bb-3bf7bc125b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220987500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.220987500
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2113672630
Short name T538
Test name
Test status
Simulation time 17299086 ps
CPU time 0.71 seconds
Started Apr 28 12:58:07 PM PDT 24
Finished Apr 28 12:58:08 PM PDT 24
Peak memory 191644 kb
Host smart-6c22e609-4b2e-4d6e-83a9-25691019fd10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113672630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2113672630
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2419240066
Short name T517
Test name
Test status
Simulation time 82591145 ps
CPU time 1.75 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 197512 kb
Host smart-29b5c089-4d37-46cd-874b-168cd6fb454b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419240066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2419240066
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2375843669
Short name T572
Test name
Test status
Simulation time 203334013 ps
CPU time 1.24 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 195140 kb
Host smart-1e559bb0-bfe8-441b-82c5-659c7f3293e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375843669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2375843669
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.229458402
Short name T508
Test name
Test status
Simulation time 391087976 ps
CPU time 1.16 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:17 PM PDT 24
Peak memory 197640 kb
Host smart-453c0cc5-9575-4d72-bc4c-c8d7636ee73f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229458402 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.229458402
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3417031952
Short name T97
Test name
Test status
Simulation time 45610617 ps
CPU time 0.52 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 182592 kb
Host smart-2b38315d-0bbd-472d-b783-753e30b361f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417031952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3417031952
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.242087777
Short name T533
Test name
Test status
Simulation time 15286362 ps
CPU time 0.56 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 182540 kb
Host smart-ab0f2967-cac0-4a20-a02b-424819544dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242087777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.242087777
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1070257203
Short name T548
Test name
Test status
Simulation time 35168844 ps
CPU time 0.73 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 193112 kb
Host smart-453f7216-6b9f-4315-82b1-e8426ce17a59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070257203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1070257203
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3947020047
Short name T535
Test name
Test status
Simulation time 429248488 ps
CPU time 1.97 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 197676 kb
Host smart-c3da2976-897f-4a07-9e85-aaf71dc9f360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947020047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3947020047
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2458917575
Short name T567
Test name
Test status
Simulation time 258387202 ps
CPU time 0.79 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 193564 kb
Host smart-06809ac1-3ba6-4f89-a0be-57fb24ecf3be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458917575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2458917575
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3592340941
Short name T558
Test name
Test status
Simulation time 15546163 ps
CPU time 0.61 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 193032 kb
Host smart-8aa72302-0d8a-4cc6-9bfc-0c49e7248e79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592340941 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3592340941
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2490848407
Short name T87
Test name
Test status
Simulation time 19038425 ps
CPU time 0.62 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 182748 kb
Host smart-2a5954ff-cd18-4f8d-8687-2b28c20c5634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490848407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2490848407
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3072191505
Short name T539
Test name
Test status
Simulation time 32990875 ps
CPU time 0.52 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 182196 kb
Host smart-11597fe9-b0c3-481d-bb48-244b7c7107ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072191505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3072191505
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.38931520
Short name T108
Test name
Test status
Simulation time 27548365 ps
CPU time 0.67 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:12 PM PDT 24
Peak memory 192224 kb
Host smart-d4a09d64-92cc-4532-8104-3016f6237c5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38931520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_tim
er_same_csr_outstanding.38931520
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.37940813
Short name T514
Test name
Test status
Simulation time 1164472723 ps
CPU time 3.01 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 197516 kb
Host smart-6cb48653-2782-4c12-97e8-3c47bb2b246c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.37940813
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.883347540
Short name T117
Test name
Test status
Simulation time 79862747 ps
CPU time 0.85 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:10 PM PDT 24
Peak memory 182952 kb
Host smart-0384f38f-e073-4b74-b202-679621004de1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883347540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.883347540
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.242297620
Short name T471
Test name
Test status
Simulation time 119657713 ps
CPU time 2.22 seconds
Started Apr 28 12:57:51 PM PDT 24
Finished Apr 28 12:57:54 PM PDT 24
Peak memory 193704 kb
Host smart-fd86dcbe-7bd3-4655-be89-d0befbab54fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242297620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.242297620
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2863635126
Short name T86
Test name
Test status
Simulation time 14875244 ps
CPU time 0.58 seconds
Started Apr 28 12:57:53 PM PDT 24
Finished Apr 28 12:57:54 PM PDT 24
Peak memory 182740 kb
Host smart-1fefb7db-559e-495a-9e1f-b58bdf30b06b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863635126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2863635126
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3538105941
Short name T484
Test name
Test status
Simulation time 138709553 ps
CPU time 0.85 seconds
Started Apr 28 12:57:51 PM PDT 24
Finished Apr 28 12:57:54 PM PDT 24
Peak memory 196656 kb
Host smart-ab95e06c-675e-4e00-a520-ce8233f622fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538105941 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3538105941
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1082209670
Short name T96
Test name
Test status
Simulation time 23758037 ps
CPU time 0.65 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:51 PM PDT 24
Peak memory 182772 kb
Host smart-d0dd60eb-5e29-435d-b735-fef736c9078d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082209670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1082209670
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2717098544
Short name T474
Test name
Test status
Simulation time 46560467 ps
CPU time 0.55 seconds
Started Apr 28 12:57:53 PM PDT 24
Finished Apr 28 12:57:54 PM PDT 24
Peak memory 182648 kb
Host smart-de51114b-4790-4427-b18f-b723822fd430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717098544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2717098544
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3643355175
Short name T568
Test name
Test status
Simulation time 17589717 ps
CPU time 0.59 seconds
Started Apr 28 12:57:58 PM PDT 24
Finished Apr 28 12:57:59 PM PDT 24
Peak memory 191968 kb
Host smart-ace0ccf0-b499-4954-8d04-caf077dc9a8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643355175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3643355175
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1094546045
Short name T489
Test name
Test status
Simulation time 150289388 ps
CPU time 2.54 seconds
Started Apr 28 12:57:52 PM PDT 24
Finished Apr 28 12:57:56 PM PDT 24
Peak memory 197620 kb
Host smart-41ed6a59-772f-4f03-afc8-ada14dbe3cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094546045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1094546045
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.442045628
Short name T65
Test name
Test status
Simulation time 82601312 ps
CPU time 1.1 seconds
Started Apr 28 12:57:50 PM PDT 24
Finished Apr 28 12:57:53 PM PDT 24
Peak memory 195232 kb
Host smart-56b0dc3b-166a-4e12-89af-2213b47347ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442045628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.442045628
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3015599097
Short name T496
Test name
Test status
Simulation time 16246852 ps
CPU time 0.54 seconds
Started Apr 28 12:58:07 PM PDT 24
Finished Apr 28 12:58:08 PM PDT 24
Peak memory 182700 kb
Host smart-364915d4-9440-446b-9632-c575d2cc3eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015599097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3015599097
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1245953017
Short name T483
Test name
Test status
Simulation time 21556102 ps
CPU time 0.52 seconds
Started Apr 28 12:58:07 PM PDT 24
Finished Apr 28 12:58:08 PM PDT 24
Peak memory 182120 kb
Host smart-6ae33fbe-bbe7-4841-939b-bc2506767171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245953017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1245953017
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1306492611
Short name T456
Test name
Test status
Simulation time 39080958 ps
CPU time 0.53 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 182088 kb
Host smart-6097cd5c-8a1e-4f9f-8f00-4328f2f239ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306492611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1306492611
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.711777307
Short name T509
Test name
Test status
Simulation time 17812147 ps
CPU time 0.53 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 182124 kb
Host smart-7e37a578-48bd-4233-a68c-d9e52950ace1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711777307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.711777307
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2309594657
Short name T454
Test name
Test status
Simulation time 18854149 ps
CPU time 0.51 seconds
Started Apr 28 12:58:04 PM PDT 24
Finished Apr 28 12:58:05 PM PDT 24
Peak memory 182124 kb
Host smart-b3378e31-6009-4dd4-a8f4-e0643ca2a023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309594657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2309594657
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1925640041
Short name T476
Test name
Test status
Simulation time 18191064 ps
CPU time 0.54 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:14 PM PDT 24
Peak memory 182596 kb
Host smart-0bb4226c-3e73-4ac0-837b-8e42e93047aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925640041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1925640041
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2445787863
Short name T491
Test name
Test status
Simulation time 15363790 ps
CPU time 0.55 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 182520 kb
Host smart-fcd0934e-0772-44d7-9ca9-8e9faca35908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445787863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2445787863
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.803200328
Short name T556
Test name
Test status
Simulation time 33926232 ps
CPU time 0.58 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 182612 kb
Host smart-5d9aabfe-c019-42f3-a3da-63cde2bc3c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803200328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.803200328
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1855388951
Short name T481
Test name
Test status
Simulation time 14500488 ps
CPU time 0.53 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:18 PM PDT 24
Peak memory 182108 kb
Host smart-f97ef900-8ac2-4137-998d-f949b4cfb06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855388951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1855388951
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4282283213
Short name T449
Test name
Test status
Simulation time 15331315 ps
CPU time 0.56 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:11 PM PDT 24
Peak memory 182524 kb
Host smart-fa253242-dcdf-44c4-9578-a5a6b7823304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282283213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4282283213
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1900417324
Short name T89
Test name
Test status
Simulation time 180788783 ps
CPU time 0.67 seconds
Started Apr 28 12:57:54 PM PDT 24
Finished Apr 28 12:57:56 PM PDT 24
Peak memory 182632 kb
Host smart-b49dd07c-7026-41a1-be48-d9856042d0ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900417324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1900417324
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.18724726
Short name T504
Test name
Test status
Simulation time 534156435 ps
CPU time 1.5 seconds
Started Apr 28 12:58:01 PM PDT 24
Finished Apr 28 12:58:03 PM PDT 24
Peak memory 191192 kb
Host smart-2a9e7e83-8b65-46bd-be3a-601894e4c1c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18724726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ba
sh.18724726
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2456900361
Short name T528
Test name
Test status
Simulation time 36569780 ps
CPU time 0.55 seconds
Started Apr 28 12:58:07 PM PDT 24
Finished Apr 28 12:58:08 PM PDT 24
Peak memory 182628 kb
Host smart-781231a8-10c9-4e5f-9943-7652d29c4140
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456900361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2456900361
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2884297053
Short name T506
Test name
Test status
Simulation time 48749972 ps
CPU time 0.76 seconds
Started Apr 28 12:57:53 PM PDT 24
Finished Apr 28 12:57:55 PM PDT 24
Peak memory 195664 kb
Host smart-528f8a4f-969c-4ff6-b6ed-793bdbaf2d25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884297053 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2884297053
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3033009327
Short name T562
Test name
Test status
Simulation time 13654616 ps
CPU time 0.56 seconds
Started Apr 28 12:57:57 PM PDT 24
Finished Apr 28 12:57:58 PM PDT 24
Peak memory 182732 kb
Host smart-d11e3611-3ade-4396-816d-fa33f74b6976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033009327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3033009327
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.702961594
Short name T495
Test name
Test status
Simulation time 23101802 ps
CPU time 0.52 seconds
Started Apr 28 12:57:54 PM PDT 24
Finished Apr 28 12:57:55 PM PDT 24
Peak memory 182544 kb
Host smart-0def154d-a868-4fe3-8230-542d53525104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702961594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.702961594
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3618778732
Short name T110
Test name
Test status
Simulation time 21281494 ps
CPU time 0.77 seconds
Started Apr 28 12:57:50 PM PDT 24
Finished Apr 28 12:57:57 PM PDT 24
Peak memory 191760 kb
Host smart-c02848dc-bbfd-4447-b992-3915609b35bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618778732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3618778732
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.38906715
Short name T524
Test name
Test status
Simulation time 1573804811 ps
CPU time 2.79 seconds
Started Apr 28 12:57:55 PM PDT 24
Finished Apr 28 12:57:58 PM PDT 24
Peak memory 197548 kb
Host smart-9a31cde4-75f6-4eb9-b0c9-48cda729ebea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38906715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.38906715
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3900073810
Short name T473
Test name
Test status
Simulation time 324097463 ps
CPU time 1.33 seconds
Started Apr 28 12:58:00 PM PDT 24
Finished Apr 28 12:58:02 PM PDT 24
Peak memory 183228 kb
Host smart-6d15a4cb-7e57-432f-a489-9e56ce73f444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900073810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3900073810
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.53151293
Short name T516
Test name
Test status
Simulation time 15602863 ps
CPU time 0.56 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 182652 kb
Host smart-ee6f86d9-d4fa-4169-b632-d5ff203bcba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53151293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.53151293
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1567365078
Short name T492
Test name
Test status
Simulation time 55350330 ps
CPU time 0.55 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 182392 kb
Host smart-56ced37f-80e2-4e7f-9a2f-166383257c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567365078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1567365078
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1184000992
Short name T466
Test name
Test status
Simulation time 30531560 ps
CPU time 0.54 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 182292 kb
Host smart-6d206fc4-d21f-4b28-8470-6c210aaf88b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184000992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1184000992
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3953171108
Short name T467
Test name
Test status
Simulation time 13080139 ps
CPU time 0.55 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 182532 kb
Host smart-b040199f-5ca7-4e6f-bbc7-1c92da48daf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953171108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3953171108
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4224751078
Short name T536
Test name
Test status
Simulation time 31249562 ps
CPU time 0.53 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 182624 kb
Host smart-8be23a28-2413-4448-afe9-3de8578b56a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224751078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4224751078
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.4115345677
Short name T450
Test name
Test status
Simulation time 24040274 ps
CPU time 0.59 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:11 PM PDT 24
Peak memory 182684 kb
Host smart-35ccd6b1-49df-423d-98e1-51826eef3b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115345677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.4115345677
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.800811548
Short name T519
Test name
Test status
Simulation time 20062018 ps
CPU time 0.57 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:10 PM PDT 24
Peak memory 182584 kb
Host smart-4a844f00-ab5d-45b3-ba40-22809783b6cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800811548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.800811548
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3249602484
Short name T497
Test name
Test status
Simulation time 23411763 ps
CPU time 0.57 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:12 PM PDT 24
Peak memory 182572 kb
Host smart-1f1aff27-c42b-435e-a68b-0ed34e6647d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249602484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3249602484
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3606762540
Short name T531
Test name
Test status
Simulation time 26033352 ps
CPU time 0.53 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 182564 kb
Host smart-55e363d4-91c2-4ac9-8c21-a41bc8f8945f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606762540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3606762540
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.713228222
Short name T475
Test name
Test status
Simulation time 15203481 ps
CPU time 0.57 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 182684 kb
Host smart-db204054-7311-4fb1-bab2-2fc761be5cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713228222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.713228222
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1360458941
Short name T575
Test name
Test status
Simulation time 22129982 ps
CPU time 0.63 seconds
Started Apr 28 12:58:04 PM PDT 24
Finished Apr 28 12:58:05 PM PDT 24
Peak memory 182736 kb
Host smart-2dfc7cd6-74ac-4acd-87dc-eabbe2009e55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360458941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1360458941
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.975532684
Short name T51
Test name
Test status
Simulation time 582274870 ps
CPU time 1.55 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:18 PM PDT 24
Peak memory 191088 kb
Host smart-0abd36ca-b514-4773-abd5-3ae78cabf688
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975532684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.975532684
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1731586857
Short name T486
Test name
Test status
Simulation time 28461719 ps
CPU time 0.55 seconds
Started Apr 28 12:58:01 PM PDT 24
Finished Apr 28 12:58:02 PM PDT 24
Peak memory 182740 kb
Host smart-88f5ffef-2d08-478f-802f-e8ac9f765c4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731586857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1731586857
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4070147682
Short name T546
Test name
Test status
Simulation time 83435276 ps
CPU time 0.68 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 195044 kb
Host smart-e423d4b2-7eec-45ba-896a-8c5a5fc1a027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070147682 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4070147682
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1871518020
Short name T93
Test name
Test status
Simulation time 51361280 ps
CPU time 0.61 seconds
Started Apr 28 12:57:54 PM PDT 24
Finished Apr 28 12:57:55 PM PDT 24
Peak memory 182764 kb
Host smart-781e323f-4cf3-4e90-8f92-97a3fa9100eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871518020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1871518020
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1450465305
Short name T563
Test name
Test status
Simulation time 22332478 ps
CPU time 0.56 seconds
Started Apr 28 12:57:49 PM PDT 24
Finished Apr 28 12:57:52 PM PDT 24
Peak memory 182460 kb
Host smart-2d02c4d3-3486-46ff-8276-8584a38dc91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450465305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1450465305
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3605670536
Short name T85
Test name
Test status
Simulation time 26672573 ps
CPU time 0.61 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:18 PM PDT 24
Peak memory 192056 kb
Host smart-b68bb59f-522a-49fb-8af0-79ac88797c8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605670536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3605670536
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3524734215
Short name T498
Test name
Test status
Simulation time 286564933 ps
CPU time 1.03 seconds
Started Apr 28 12:57:54 PM PDT 24
Finished Apr 28 12:57:56 PM PDT 24
Peak memory 197412 kb
Host smart-78f0612e-aaeb-4736-9a91-d7dc55444696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524734215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3524734215
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1521575268
Short name T30
Test name
Test status
Simulation time 78011268 ps
CPU time 1.11 seconds
Started Apr 28 12:58:00 PM PDT 24
Finished Apr 28 12:58:02 PM PDT 24
Peak memory 195172 kb
Host smart-3528b22a-c013-4408-8869-d350199d4437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521575268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1521575268
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2499824545
Short name T452
Test name
Test status
Simulation time 19291240 ps
CPU time 0.52 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 182328 kb
Host smart-f5f9129c-b2dc-4490-b3f8-4c349ca9029f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499824545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2499824545
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.266956439
Short name T465
Test name
Test status
Simulation time 134512719 ps
CPU time 0.52 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 182628 kb
Host smart-f7384a8e-d2f6-4e93-ad54-a56db33790df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266956439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.266956439
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1682662431
Short name T503
Test name
Test status
Simulation time 19988512 ps
CPU time 0.58 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 182704 kb
Host smart-96220a57-b70c-4aba-a2a7-1d714ef80e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682662431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1682662431
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3349401788
Short name T451
Test name
Test status
Simulation time 13803860 ps
CPU time 0.56 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 182624 kb
Host smart-c8fcfa52-ec87-4959-8dae-41535ff68bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349401788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3349401788
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4277579324
Short name T463
Test name
Test status
Simulation time 31717449 ps
CPU time 0.54 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:18 PM PDT 24
Peak memory 182544 kb
Host smart-17104078-e3ac-4abb-b051-12afb3a171de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277579324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4277579324
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3626352334
Short name T488
Test name
Test status
Simulation time 12214830 ps
CPU time 0.57 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 182668 kb
Host smart-81a38fd0-e1f5-4e59-acaa-baa74012d121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626352334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3626352334
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2439649520
Short name T540
Test name
Test status
Simulation time 16128326 ps
CPU time 0.6 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 182768 kb
Host smart-d91e8fe1-e6be-4907-aeab-66290120621f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439649520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2439649520
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3571112143
Short name T460
Test name
Test status
Simulation time 47324781 ps
CPU time 0.52 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 182064 kb
Host smart-e6b17b33-3a3e-49ac-8bb5-edc30ac0ede5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571112143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3571112143
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3848030785
Short name T511
Test name
Test status
Simulation time 31363686 ps
CPU time 0.56 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 182696 kb
Host smart-0237afd5-28b3-4629-a02d-2c7cf5001c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848030785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3848030785
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.525606406
Short name T515
Test name
Test status
Simulation time 15365725 ps
CPU time 0.54 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 182584 kb
Host smart-1c07ed9c-517e-462b-836b-9310847516d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525606406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.525606406
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3330191139
Short name T470
Test name
Test status
Simulation time 34490017 ps
CPU time 1.45 seconds
Started Apr 28 12:58:01 PM PDT 24
Finished Apr 28 12:58:04 PM PDT 24
Peak memory 197628 kb
Host smart-15ac2bc6-3a94-4e9e-837d-b8163a602c00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330191139 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3330191139
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1692180143
Short name T532
Test name
Test status
Simulation time 20201518 ps
CPU time 0.53 seconds
Started Apr 28 12:57:58 PM PDT 24
Finished Apr 28 12:57:59 PM PDT 24
Peak memory 182748 kb
Host smart-a64d1df4-7b81-4fec-bcd5-fca95b24d0b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692180143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1692180143
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.496066218
Short name T527
Test name
Test status
Simulation time 19317112 ps
CPU time 0.54 seconds
Started Apr 28 12:58:00 PM PDT 24
Finished Apr 28 12:58:01 PM PDT 24
Peak memory 182144 kb
Host smart-e0631697-d1b4-4649-b5f6-a1eb85635f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496066218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.496066218
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1731185784
Short name T541
Test name
Test status
Simulation time 30585020 ps
CPU time 0.74 seconds
Started Apr 28 12:57:59 PM PDT 24
Finished Apr 28 12:58:00 PM PDT 24
Peak memory 193152 kb
Host smart-171fbdb4-cf63-4634-8362-5fbf835c7d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731185784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1731185784
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2483238911
Short name T469
Test name
Test status
Simulation time 384576896 ps
CPU time 1.92 seconds
Started Apr 28 12:58:01 PM PDT 24
Finished Apr 28 12:58:03 PM PDT 24
Peak memory 197524 kb
Host smart-9630fd04-7e5f-46bc-b1e6-09b47fa507cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483238911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2483238911
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2637153898
Short name T507
Test name
Test status
Simulation time 116820995 ps
CPU time 1.39 seconds
Started Apr 28 12:58:05 PM PDT 24
Finished Apr 28 12:58:07 PM PDT 24
Peak memory 195360 kb
Host smart-f3ffbbff-02f6-4b54-a445-a2af6d0d9a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637153898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2637153898
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3419278295
Short name T526
Test name
Test status
Simulation time 26994579 ps
CPU time 0.82 seconds
Started Apr 28 12:58:07 PM PDT 24
Finished Apr 28 12:58:09 PM PDT 24
Peak memory 196216 kb
Host smart-04899a01-2543-468b-9afc-354b1b369f71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419278295 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3419278295
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.983842101
Short name T461
Test name
Test status
Simulation time 18128539 ps
CPU time 0.55 seconds
Started Apr 28 12:57:59 PM PDT 24
Finished Apr 28 12:58:00 PM PDT 24
Peak memory 182752 kb
Host smart-e2cdc9f1-f469-41b3-8818-9ca9d8a7c8ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983842101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.983842101
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3324331318
Short name T529
Test name
Test status
Simulation time 45216146 ps
CPU time 0.51 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:09 PM PDT 24
Peak memory 181976 kb
Host smart-02615380-1b1a-4fe1-a57c-17336e5116d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324331318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3324331318
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3912390336
Short name T574
Test name
Test status
Simulation time 161771657 ps
CPU time 0.88 seconds
Started Apr 28 12:58:11 PM PDT 24
Finished Apr 28 12:58:13 PM PDT 24
Peak memory 192784 kb
Host smart-f4985519-efee-47f0-9cd5-c453a88d891e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912390336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3912390336
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4087989661
Short name T551
Test name
Test status
Simulation time 39593992 ps
CPU time 1.8 seconds
Started Apr 28 12:58:06 PM PDT 24
Finished Apr 28 12:58:08 PM PDT 24
Peak memory 197620 kb
Host smart-52804ddc-3587-4696-9168-675e52eef7f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087989661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4087989661
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3477740233
Short name T544
Test name
Test status
Simulation time 315445255 ps
CPU time 1.11 seconds
Started Apr 28 12:58:03 PM PDT 24
Finished Apr 28 12:58:05 PM PDT 24
Peak memory 183492 kb
Host smart-28548ca9-9088-4dec-96d3-146df108e539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477740233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3477740233
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.505535480
Short name T480
Test name
Test status
Simulation time 77616870 ps
CPU time 0.69 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 195156 kb
Host smart-ad09022e-9f7c-4dec-8246-32f867e1eb51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505535480 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.505535480
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2482350381
Short name T88
Test name
Test status
Simulation time 13100831 ps
CPU time 0.59 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:17 PM PDT 24
Peak memory 182776 kb
Host smart-b6d5e1e8-b518-486d-a5b8-612ef43a356b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482350381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2482350381
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.581685034
Short name T543
Test name
Test status
Simulation time 15685963 ps
CPU time 0.53 seconds
Started Apr 28 12:57:55 PM PDT 24
Finished Apr 28 12:57:56 PM PDT 24
Peak memory 182676 kb
Host smart-17cc57d7-216c-4758-8dd0-bf8afcd09df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581685034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.581685034
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1354661446
Short name T559
Test name
Test status
Simulation time 93156416 ps
CPU time 0.8 seconds
Started Apr 28 12:57:59 PM PDT 24
Finished Apr 28 12:58:01 PM PDT 24
Peak memory 193548 kb
Host smart-6e51f9d2-0e53-4e55-a160-060b6b3dd1fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354661446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1354661446
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2216560739
Short name T457
Test name
Test status
Simulation time 48445700 ps
CPU time 2.27 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:17 PM PDT 24
Peak memory 197564 kb
Host smart-2eb9650a-4532-4733-97b7-7e489bbc4e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216560739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2216560739
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1301084265
Short name T29
Test name
Test status
Simulation time 90954965 ps
CPU time 1.08 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:17 PM PDT 24
Peak memory 183432 kb
Host smart-84fd6752-f4b5-4f11-8ba0-2b433f5749f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301084265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1301084265
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.214935656
Short name T490
Test name
Test status
Simulation time 24917258 ps
CPU time 1.01 seconds
Started Apr 28 12:57:59 PM PDT 24
Finished Apr 28 12:58:00 PM PDT 24
Peak memory 197424 kb
Host smart-827d1a8a-9751-4677-922f-3b4a5aed7b09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214935656 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.214935656
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2649963204
Short name T525
Test name
Test status
Simulation time 23097356 ps
CPU time 0.57 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 182656 kb
Host smart-b4e01b17-7ca6-4370-9564-f2164cea4128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649963204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2649963204
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.95427152
Short name T487
Test name
Test status
Simulation time 46709167 ps
CPU time 0.54 seconds
Started Apr 28 12:58:08 PM PDT 24
Finished Apr 28 12:58:10 PM PDT 24
Peak memory 181956 kb
Host smart-795670b2-c94b-45f8-80cf-c0ab66320c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95427152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.95427152
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1089539643
Short name T557
Test name
Test status
Simulation time 18734798 ps
CPU time 0.7 seconds
Started Apr 28 12:58:03 PM PDT 24
Finished Apr 28 12:58:05 PM PDT 24
Peak memory 192128 kb
Host smart-e1378a3c-cf6b-4c8a-a1b9-9e9b4768b00a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089539643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1089539643
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2661817226
Short name T570
Test name
Test status
Simulation time 211032838 ps
CPU time 1.3 seconds
Started Apr 28 12:57:55 PM PDT 24
Finished Apr 28 12:57:57 PM PDT 24
Peak memory 197616 kb
Host smart-80e6a4bd-e89a-4271-96a7-013390db8aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661817226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2661817226
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3709381521
Short name T512
Test name
Test status
Simulation time 67916757 ps
CPU time 1.05 seconds
Started Apr 28 12:57:58 PM PDT 24
Finished Apr 28 12:57:59 PM PDT 24
Peak memory 195068 kb
Host smart-c433d967-9a00-4d77-a1f4-a002bd8edd33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709381521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3709381521
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.313818156
Short name T510
Test name
Test status
Simulation time 34678033 ps
CPU time 1.45 seconds
Started Apr 28 12:58:00 PM PDT 24
Finished Apr 28 12:58:02 PM PDT 24
Peak memory 197628 kb
Host smart-125b10db-98ba-437a-ba7e-5b0c9c19be11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313818156 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.313818156
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1813945679
Short name T55
Test name
Test status
Simulation time 14015185 ps
CPU time 0.6 seconds
Started Apr 28 12:58:00 PM PDT 24
Finished Apr 28 12:58:02 PM PDT 24
Peak memory 182724 kb
Host smart-383f61b6-8bf4-4161-b26b-9c9277fa6910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813945679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1813945679
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2894288071
Short name T518
Test name
Test status
Simulation time 28648893 ps
CPU time 0.59 seconds
Started Apr 28 12:58:01 PM PDT 24
Finished Apr 28 12:58:03 PM PDT 24
Peak memory 182520 kb
Host smart-486bc5ee-08aa-44c8-bdb1-4d1b373b1567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894288071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2894288071
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2976814106
Short name T522
Test name
Test status
Simulation time 89868685 ps
CPU time 0.72 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 193336 kb
Host smart-5d6a4a0c-4ad6-471d-b464-c605bb0261e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976814106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2976814106
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3232965261
Short name T566
Test name
Test status
Simulation time 103597233 ps
CPU time 2.57 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:23 PM PDT 24
Peak memory 197656 kb
Host smart-447c283a-9612-4f3f-a73e-c4388464cfb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232965261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3232965261
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4000208019
Short name T554
Test name
Test status
Simulation time 54744853 ps
CPU time 0.81 seconds
Started Apr 28 12:57:59 PM PDT 24
Finished Apr 28 12:58:01 PM PDT 24
Peak memory 182908 kb
Host smart-55051404-699e-4c47-a2a9-4ec5a5c067d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000208019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4000208019
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.696599522
Short name T223
Test name
Test status
Simulation time 71065328935 ps
CPU time 42.1 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:17:19 PM PDT 24
Peak memory 183068 kb
Host smart-a8f893c8-b25a-490a-9ef5-fe54ecede06b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696599522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.696599522
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3433617535
Short name T408
Test name
Test status
Simulation time 18679160627 ps
CPU time 15.38 seconds
Started Apr 28 02:16:32 PM PDT 24
Finished Apr 28 02:16:48 PM PDT 24
Peak memory 182976 kb
Host smart-2ce8ca61-1af8-4d3e-9ecf-5bda14ef228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433617535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3433617535
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3297838163
Short name T74
Test name
Test status
Simulation time 48115405719 ps
CPU time 132.45 seconds
Started Apr 28 02:16:37 PM PDT 24
Finished Apr 28 02:18:51 PM PDT 24
Peak memory 191256 kb
Host smart-e852a3df-9e6e-4970-97d3-d544edfe53fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297838163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3297838163
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3621080394
Short name T121
Test name
Test status
Simulation time 82135304965 ps
CPU time 139.91 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:18:54 PM PDT 24
Peak memory 191176 kb
Host smart-07df9bd5-5ef9-43bf-a977-cbc9f67e13b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621080394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3621080394
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3242160910
Short name T396
Test name
Test status
Simulation time 108840795429 ps
CPU time 79.9 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:17:56 PM PDT 24
Peak memory 183088 kb
Host smart-3c60be31-6155-4a11-8277-2840f05c904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242160910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3242160910
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3292776662
Short name T198
Test name
Test status
Simulation time 90507548243 ps
CPU time 77.37 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:17:57 PM PDT 24
Peak memory 183056 kb
Host smart-27d2a814-7424-4983-a8e1-7081e0a1ef07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292776662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3292776662
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.521238248
Short name T427
Test name
Test status
Simulation time 44216629004 ps
CPU time 121.06 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:18:37 PM PDT 24
Peak memory 191208 kb
Host smart-94a470a2-cb43-464c-99cf-f551398eb4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521238248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.521238248
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.385180179
Short name T14
Test name
Test status
Simulation time 69508312 ps
CPU time 0.74 seconds
Started Apr 28 02:16:36 PM PDT 24
Finished Apr 28 02:16:38 PM PDT 24
Peak memory 213392 kb
Host smart-213556b0-2b0a-42fa-b69c-6001d6e6071c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385180179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.385180179
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2900874372
Short name T393
Test name
Test status
Simulation time 318878403458 ps
CPU time 269.84 seconds
Started Apr 28 02:16:45 PM PDT 24
Finished Apr 28 02:21:15 PM PDT 24
Peak memory 183064 kb
Host smart-f9471937-ac1a-43f4-8704-b1493097b2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900874372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2900874372
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1724576523
Short name T147
Test name
Test status
Simulation time 36301779734 ps
CPU time 69.6 seconds
Started Apr 28 02:16:48 PM PDT 24
Finished Apr 28 02:17:58 PM PDT 24
Peak memory 183072 kb
Host smart-87321c9c-d8b4-4d56-ad80-4abd3018ac1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724576523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1724576523
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.3049633349
Short name T433
Test name
Test status
Simulation time 111185625608 ps
CPU time 286.58 seconds
Started Apr 28 02:17:48 PM PDT 24
Finished Apr 28 02:22:35 PM PDT 24
Peak memory 191260 kb
Host smart-d5716a88-c6e2-4e7f-bd04-dbc641435b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049633349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3049633349
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.4146731064
Short name T297
Test name
Test status
Simulation time 13773971733 ps
CPU time 12.14 seconds
Started Apr 28 02:17:49 PM PDT 24
Finished Apr 28 02:18:02 PM PDT 24
Peak memory 183020 kb
Host smart-dbbc8b04-a8a2-439c-abf3-4ce853f3e644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146731064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.4146731064
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3360567464
Short name T350
Test name
Test status
Simulation time 118001805325 ps
CPU time 423.35 seconds
Started Apr 28 02:17:48 PM PDT 24
Finished Apr 28 02:24:52 PM PDT 24
Peak memory 191244 kb
Host smart-86267ce4-4bb9-4c51-88cf-f6923c527747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360567464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3360567464
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2015345545
Short name T294
Test name
Test status
Simulation time 378436453858 ps
CPU time 474.71 seconds
Started Apr 28 02:17:49 PM PDT 24
Finished Apr 28 02:25:45 PM PDT 24
Peak memory 191220 kb
Host smart-c27649d5-6dd2-4307-a196-e318f78fbeaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015345545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2015345545
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3275753868
Short name T71
Test name
Test status
Simulation time 169207696656 ps
CPU time 118.05 seconds
Started Apr 28 02:17:48 PM PDT 24
Finished Apr 28 02:19:46 PM PDT 24
Peak memory 194768 kb
Host smart-536c3003-7f43-4690-b22d-3886e4bcfbcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275753868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3275753868
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.225119097
Short name T211
Test name
Test status
Simulation time 639667944167 ps
CPU time 402.34 seconds
Started Apr 28 02:17:49 PM PDT 24
Finished Apr 28 02:24:32 PM PDT 24
Peak memory 191212 kb
Host smart-08807dde-a7cf-43f4-a9c2-2f479403fbf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225119097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.225119097
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.202682408
Short name T46
Test name
Test status
Simulation time 1078167267967 ps
CPU time 1070.68 seconds
Started Apr 28 02:17:52 PM PDT 24
Finished Apr 28 02:35:43 PM PDT 24
Peak memory 191220 kb
Host smart-f7c41ab4-9d4f-4a76-ac0b-de6f6b687fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202682408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.202682408
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.507445688
Short name T98
Test name
Test status
Simulation time 486794713403 ps
CPU time 469.55 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:24:37 PM PDT 24
Peak memory 183076 kb
Host smart-aef06ef7-214f-4053-bd8b-d6a63310f48a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507445688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.507445688
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3204800556
Short name T426
Test name
Test status
Simulation time 735022832661 ps
CPU time 79.66 seconds
Started Apr 28 02:16:48 PM PDT 24
Finished Apr 28 02:18:08 PM PDT 24
Peak memory 183064 kb
Host smart-daa5137e-5268-43fa-a5ae-ed02fccb7da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204800556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3204800556
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1397981619
Short name T373
Test name
Test status
Simulation time 1138246194 ps
CPU time 1.75 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:16:50 PM PDT 24
Peak memory 193548 kb
Host smart-14c19698-1166-4928-99ed-d5620d514845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397981619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1397981619
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2818642249
Short name T271
Test name
Test status
Simulation time 2192242394788 ps
CPU time 676.73 seconds
Started Apr 28 02:16:48 PM PDT 24
Finished Apr 28 02:28:06 PM PDT 24
Peak memory 191184 kb
Host smart-a2a7cb9a-3921-48dc-a634-b5d4691cae34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818642249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2818642249
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.3001475142
Short name T226
Test name
Test status
Simulation time 99138826514 ps
CPU time 101.24 seconds
Started Apr 28 02:17:53 PM PDT 24
Finished Apr 28 02:19:34 PM PDT 24
Peak memory 191168 kb
Host smart-4ed79de2-1b76-463e-b482-2f10f25d2d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001475142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3001475142
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3588783650
Short name T245
Test name
Test status
Simulation time 680727504103 ps
CPU time 869.64 seconds
Started Apr 28 02:17:57 PM PDT 24
Finished Apr 28 02:32:27 PM PDT 24
Peak memory 191092 kb
Host smart-6706bd13-7a90-4830-b4f4-597bf77f0b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588783650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3588783650
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2956779639
Short name T359
Test name
Test status
Simulation time 125230051546 ps
CPU time 452.49 seconds
Started Apr 28 02:17:57 PM PDT 24
Finished Apr 28 02:25:30 PM PDT 24
Peak memory 191240 kb
Host smart-53bf8d27-332d-4415-bb5e-8805b0a553b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956779639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2956779639
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4022440609
Short name T62
Test name
Test status
Simulation time 99234000077 ps
CPU time 632.55 seconds
Started Apr 28 02:17:59 PM PDT 24
Finished Apr 28 02:28:32 PM PDT 24
Peak memory 191244 kb
Host smart-83e5e5dc-565d-4e36-93a2-4a48333387c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022440609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4022440609
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2176925342
Short name T435
Test name
Test status
Simulation time 58593772826 ps
CPU time 85.02 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:18:12 PM PDT 24
Peak memory 182908 kb
Host smart-2caef78d-61e5-40d4-9d15-18aaa52af750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176925342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2176925342
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2499140801
Short name T254
Test name
Test status
Simulation time 1006092146754 ps
CPU time 272 seconds
Started Apr 28 02:16:49 PM PDT 24
Finished Apr 28 02:21:22 PM PDT 24
Peak memory 191084 kb
Host smart-733b0a4a-03ab-4a05-bb5b-e702ff07e96d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499140801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2499140801
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2065532677
Short name T439
Test name
Test status
Simulation time 38952583034 ps
CPU time 50.55 seconds
Started Apr 28 02:17:01 PM PDT 24
Finished Apr 28 02:17:52 PM PDT 24
Peak memory 183068 kb
Host smart-a1b6eda4-8a95-4b94-8b99-63553ae01ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065532677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2065532677
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3189679935
Short name T332
Test name
Test status
Simulation time 76187666223 ps
CPU time 75.27 seconds
Started Apr 28 02:17:57 PM PDT 24
Finished Apr 28 02:19:13 PM PDT 24
Peak memory 183004 kb
Host smart-e6287e07-cb41-42a4-9bf5-c7fd18e396ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189679935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3189679935
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1140139481
Short name T265
Test name
Test status
Simulation time 86065663236 ps
CPU time 145.27 seconds
Started Apr 28 02:17:57 PM PDT 24
Finished Apr 28 02:20:23 PM PDT 24
Peak memory 191100 kb
Host smart-a6d935e2-30be-4d9d-9bdc-608e486163de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140139481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1140139481
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.713510734
Short name T138
Test name
Test status
Simulation time 269601370992 ps
CPU time 476.78 seconds
Started Apr 28 02:17:58 PM PDT 24
Finished Apr 28 02:25:55 PM PDT 24
Peak memory 193552 kb
Host smart-4bd9a750-e350-4f26-8ee2-456672b3c261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713510734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.713510734
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2991786715
Short name T175
Test name
Test status
Simulation time 47301290420 ps
CPU time 69.77 seconds
Started Apr 28 02:18:04 PM PDT 24
Finished Apr 28 02:19:15 PM PDT 24
Peak memory 183040 kb
Host smart-5bed564f-75fd-4446-8418-f597cc6eecc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991786715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2991786715
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.865885478
Short name T235
Test name
Test status
Simulation time 497943067846 ps
CPU time 747.6 seconds
Started Apr 28 02:18:07 PM PDT 24
Finished Apr 28 02:30:35 PM PDT 24
Peak memory 191204 kb
Host smart-f6b1621e-e6ef-42b8-a770-1670565e2706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865885478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.865885478
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3499569724
Short name T264
Test name
Test status
Simulation time 273474575920 ps
CPU time 177.13 seconds
Started Apr 28 02:18:06 PM PDT 24
Finished Apr 28 02:21:04 PM PDT 24
Peak memory 191220 kb
Host smart-050391f4-f58c-43b6-9d67-6d418d757638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499569724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3499569724
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.502036463
Short name T284
Test name
Test status
Simulation time 921094701118 ps
CPU time 543.55 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:25:51 PM PDT 24
Peak memory 183036 kb
Host smart-1c77dfdc-f425-494d-8c88-b50e1077c5f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502036463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.502036463
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2675579779
Short name T21
Test name
Test status
Simulation time 100994071265 ps
CPU time 36.1 seconds
Started Apr 28 02:16:50 PM PDT 24
Finished Apr 28 02:17:26 PM PDT 24
Peak memory 183028 kb
Host smart-39311323-dfe2-4c19-9a52-e471d1e5b79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675579779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2675579779
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.3729528767
Short name T225
Test name
Test status
Simulation time 43192701140 ps
CPU time 821.76 seconds
Started Apr 28 02:16:50 PM PDT 24
Finished Apr 28 02:30:32 PM PDT 24
Peak memory 191272 kb
Host smart-e8c6be8e-597e-4c9f-9a38-36eb890adf72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729528767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3729528767
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2756272558
Short name T414
Test name
Test status
Simulation time 199465341047 ps
CPU time 160.88 seconds
Started Apr 28 02:16:48 PM PDT 24
Finished Apr 28 02:19:30 PM PDT 24
Peak memory 191236 kb
Host smart-8b6899dc-d3b1-49e6-b924-96be2b1bd23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756272558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2756272558
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3679836895
Short name T148
Test name
Test status
Simulation time 630085030475 ps
CPU time 1402.13 seconds
Started Apr 28 02:16:46 PM PDT 24
Finished Apr 28 02:40:09 PM PDT 24
Peak memory 191228 kb
Host smart-4c6325ae-776e-408d-bac3-072ae3a9dc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679836895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3679836895
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1398296569
Short name T49
Test name
Test status
Simulation time 14035792876 ps
CPU time 108.25 seconds
Started Apr 28 02:16:49 PM PDT 24
Finished Apr 28 02:18:38 PM PDT 24
Peak memory 195272 kb
Host smart-96452d06-630d-493d-a91c-504aeb317368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398296569 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1398296569
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3422785321
Short name T441
Test name
Test status
Simulation time 529211232111 ps
CPU time 439.23 seconds
Started Apr 28 02:18:06 PM PDT 24
Finished Apr 28 02:25:26 PM PDT 24
Peak memory 191228 kb
Host smart-a7f0888a-afac-4b92-b322-28751bbc3416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422785321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3422785321
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.208049277
Short name T440
Test name
Test status
Simulation time 546854790660 ps
CPU time 420.68 seconds
Started Apr 28 02:18:15 PM PDT 24
Finished Apr 28 02:25:16 PM PDT 24
Peak memory 183016 kb
Host smart-0faa0731-eaaf-4744-9608-cdff093aea96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208049277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.208049277
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.570573644
Short name T448
Test name
Test status
Simulation time 30442902482 ps
CPU time 51.79 seconds
Started Apr 28 02:18:21 PM PDT 24
Finished Apr 28 02:19:13 PM PDT 24
Peak memory 183036 kb
Host smart-3ffe8814-8819-4dd3-943e-d350e656854c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570573644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.570573644
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3456210108
Short name T125
Test name
Test status
Simulation time 54898860358 ps
CPU time 639.04 seconds
Started Apr 28 02:18:19 PM PDT 24
Finished Apr 28 02:28:59 PM PDT 24
Peak memory 191248 kb
Host smart-6daed976-a712-433a-92b0-3aa079a95d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456210108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3456210108
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.594187642
Short name T236
Test name
Test status
Simulation time 207239876082 ps
CPU time 118.93 seconds
Started Apr 28 02:18:23 PM PDT 24
Finished Apr 28 02:20:23 PM PDT 24
Peak memory 183044 kb
Host smart-7e23ed41-de59-4726-8193-f47065082c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594187642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.594187642
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3065054362
Short name T134
Test name
Test status
Simulation time 451740735618 ps
CPU time 408.61 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:23:37 PM PDT 24
Peak memory 183080 kb
Host smart-0bff4516-242a-4a00-9047-2af1e2aebb91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065054362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3065054362
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.655194627
Short name T409
Test name
Test status
Simulation time 857696958627 ps
CPU time 186.72 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:19:54 PM PDT 24
Peak memory 183060 kb
Host smart-63492526-d53c-4b8e-bd2d-c1121e13977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655194627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.655194627
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1455205797
Short name T193
Test name
Test status
Simulation time 88805237962 ps
CPU time 130.9 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:18:59 PM PDT 24
Peak memory 191212 kb
Host smart-df814538-64a0-4afa-98f9-173d6805a0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455205797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1455205797
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3796291590
Short name T8
Test name
Test status
Simulation time 25140468733 ps
CPU time 24.83 seconds
Started Apr 28 02:16:48 PM PDT 24
Finished Apr 28 02:17:14 PM PDT 24
Peak memory 183008 kb
Host smart-c77ad47f-4616-438d-9693-ea25a9a12d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796291590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3796291590
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3681104156
Short name T36
Test name
Test status
Simulation time 273884995607 ps
CPU time 478.11 seconds
Started Apr 28 02:16:49 PM PDT 24
Finished Apr 28 02:24:48 PM PDT 24
Peak memory 206640 kb
Host smart-d468e6a3-b3b8-4cc5-be5a-39049433d381
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681104156 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3681104156
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3036365205
Short name T159
Test name
Test status
Simulation time 29291299529 ps
CPU time 9.91 seconds
Started Apr 28 02:18:19 PM PDT 24
Finished Apr 28 02:18:29 PM PDT 24
Peak memory 183040 kb
Host smart-5a7e6e69-dbe4-418a-a16a-49523bc54a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036365205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3036365205
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2043802433
Short name T132
Test name
Test status
Simulation time 92483531261 ps
CPU time 325.63 seconds
Started Apr 28 02:18:19 PM PDT 24
Finished Apr 28 02:23:45 PM PDT 24
Peak memory 191276 kb
Host smart-4c288420-997d-4405-9841-a3698f94d725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043802433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2043802433
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1916591010
Short name T160
Test name
Test status
Simulation time 68944286005 ps
CPU time 48.22 seconds
Started Apr 28 02:18:19 PM PDT 24
Finished Apr 28 02:19:07 PM PDT 24
Peak memory 183040 kb
Host smart-55f0a338-7e85-4224-b2e7-b9d0051d0913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916591010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1916591010
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3668519075
Short name T190
Test name
Test status
Simulation time 68138892808 ps
CPU time 122.44 seconds
Started Apr 28 02:18:22 PM PDT 24
Finished Apr 28 02:20:25 PM PDT 24
Peak memory 191128 kb
Host smart-7cf06a66-0300-4d40-aed4-e9a201a5c00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668519075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3668519075
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3926792891
Short name T164
Test name
Test status
Simulation time 50348092950 ps
CPU time 80.19 seconds
Started Apr 28 02:18:23 PM PDT 24
Finished Apr 28 02:19:44 PM PDT 24
Peak memory 183044 kb
Host smart-b9655d18-dea4-4d7f-ab58-363f969c6dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926792891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3926792891
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.242305653
Short name T365
Test name
Test status
Simulation time 144682688043 ps
CPU time 1886.17 seconds
Started Apr 28 02:18:25 PM PDT 24
Finished Apr 28 02:49:52 PM PDT 24
Peak memory 191140 kb
Host smart-37444c9a-df65-4054-86b7-772bc7b0b289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242305653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.242305653
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4280120462
Short name T418
Test name
Test status
Simulation time 1671648024514 ps
CPU time 440.51 seconds
Started Apr 28 02:16:52 PM PDT 24
Finished Apr 28 02:24:13 PM PDT 24
Peak memory 183032 kb
Host smart-7a6d5385-cd7e-44a6-aae8-f1a73d7aed8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280120462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.4280120462
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3152910382
Short name T261
Test name
Test status
Simulation time 46669346154 ps
CPU time 84.15 seconds
Started Apr 28 02:17:00 PM PDT 24
Finished Apr 28 02:18:24 PM PDT 24
Peak memory 183080 kb
Host smart-458403c4-cf74-422f-b063-0b31f2f46e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152910382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3152910382
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2983080820
Short name T13
Test name
Test status
Simulation time 397952065733 ps
CPU time 1181.16 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:36:39 PM PDT 24
Peak memory 213196 kb
Host smart-9c9925be-1e24-4df1-8b40-ec719d54f9d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983080820 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.2983080820
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.rv_timer_random.78169810
Short name T6
Test name
Test status
Simulation time 737229565613 ps
CPU time 149.61 seconds
Started Apr 28 02:18:30 PM PDT 24
Finished Apr 28 02:21:00 PM PDT 24
Peak memory 191248 kb
Host smart-3a60fe71-83e6-42d7-b7e8-39ee9a20c6b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78169810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.78169810
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.363129055
Short name T315
Test name
Test status
Simulation time 324218193880 ps
CPU time 148.74 seconds
Started Apr 28 02:18:35 PM PDT 24
Finished Apr 28 02:21:05 PM PDT 24
Peak memory 191128 kb
Host smart-52e4f0ad-ea69-4e5a-b382-0f9cf162b1d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363129055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.363129055
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4279788042
Short name T2
Test name
Test status
Simulation time 163122114860 ps
CPU time 66.95 seconds
Started Apr 28 02:18:27 PM PDT 24
Finished Apr 28 02:19:35 PM PDT 24
Peak memory 191260 kb
Host smart-4fe5eea5-7029-4c32-897c-04e845c80345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279788042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4279788042
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1654864268
Short name T306
Test name
Test status
Simulation time 108541766538 ps
CPU time 302.87 seconds
Started Apr 28 02:18:29 PM PDT 24
Finished Apr 28 02:23:32 PM PDT 24
Peak memory 183020 kb
Host smart-13890219-1749-4881-90cc-079c09bafc4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654864268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1654864268
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1176097464
Short name T222
Test name
Test status
Simulation time 50091005130 ps
CPU time 49.82 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:17:48 PM PDT 24
Peak memory 183024 kb
Host smart-857598af-e13d-4457-a462-7f8efe21fd6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176097464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1176097464
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.320421350
Short name T385
Test name
Test status
Simulation time 934342713153 ps
CPU time 232.63 seconds
Started Apr 28 02:17:02 PM PDT 24
Finished Apr 28 02:20:55 PM PDT 24
Peak memory 183036 kb
Host smart-3d7328a1-0e6a-420a-a4fa-940ca49f37e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320421350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.320421350
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2670080757
Short name T58
Test name
Test status
Simulation time 183840487210 ps
CPU time 336.62 seconds
Started Apr 28 02:16:53 PM PDT 24
Finished Apr 28 02:22:30 PM PDT 24
Peak memory 191212 kb
Host smart-4aa601a0-1fd5-4c16-b72b-ccca523b881a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670080757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2670080757
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.879677862
Short name T38
Test name
Test status
Simulation time 16330061499 ps
CPU time 116.53 seconds
Started Apr 28 02:16:52 PM PDT 24
Finished Apr 28 02:18:49 PM PDT 24
Peak memory 197716 kb
Host smart-e49f5e12-746d-4ab5-91f9-24e24e2d443f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879677862 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.879677862
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.3351034530
Short name T286
Test name
Test status
Simulation time 1232054399341 ps
CPU time 419.18 seconds
Started Apr 28 02:18:28 PM PDT 24
Finished Apr 28 02:25:28 PM PDT 24
Peak memory 191100 kb
Host smart-15808e3b-5515-45b7-b573-16a1f3730a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351034530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3351034530
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3547653606
Short name T176
Test name
Test status
Simulation time 313262694493 ps
CPU time 208.52 seconds
Started Apr 28 02:18:35 PM PDT 24
Finished Apr 28 02:22:05 PM PDT 24
Peak memory 193872 kb
Host smart-b3cf9815-4480-42c7-b04d-3519afd70048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547653606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3547653606
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4198102587
Short name T295
Test name
Test status
Simulation time 499815308010 ps
CPU time 467.37 seconds
Started Apr 28 02:18:29 PM PDT 24
Finished Apr 28 02:26:16 PM PDT 24
Peak memory 191260 kb
Host smart-9f7cd0f6-2880-4e7a-bd20-a5d1bd0cbcbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198102587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4198102587
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.859302851
Short name T344
Test name
Test status
Simulation time 66562546205 ps
CPU time 1277.11 seconds
Started Apr 28 02:18:31 PM PDT 24
Finished Apr 28 02:39:49 PM PDT 24
Peak memory 191260 kb
Host smart-e981654d-2de8-4ea4-a2f5-e3ee527a68d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859302851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.859302851
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3772979045
Short name T437
Test name
Test status
Simulation time 901032948648 ps
CPU time 335.21 seconds
Started Apr 28 02:18:34 PM PDT 24
Finished Apr 28 02:24:09 PM PDT 24
Peak memory 191200 kb
Host smart-3958985b-a111-42e9-a3db-38c6ceb383f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772979045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3772979045
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2743931587
Short name T249
Test name
Test status
Simulation time 165793618199 ps
CPU time 480.36 seconds
Started Apr 28 02:18:33 PM PDT 24
Finished Apr 28 02:26:34 PM PDT 24
Peak memory 183020 kb
Host smart-0cf1ecfe-e446-4bc3-9e53-afb3edd5d726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743931587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2743931587
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3201922755
Short name T191
Test name
Test status
Simulation time 917102912365 ps
CPU time 658.23 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:27:57 PM PDT 24
Peak memory 183084 kb
Host smart-cc7b4b03-9f7f-44d5-85ab-fe42d483018f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201922755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3201922755
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3762267570
Short name T442
Test name
Test status
Simulation time 778299487708 ps
CPU time 293.05 seconds
Started Apr 28 02:17:04 PM PDT 24
Finished Apr 28 02:21:58 PM PDT 24
Peak memory 183072 kb
Host smart-bb0220ea-2ca1-4bfa-9fb3-4c367ed9ab1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762267570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3762267570
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3040525558
Short name T122
Test name
Test status
Simulation time 72876717664 ps
CPU time 545.75 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:26:03 PM PDT 24
Peak memory 191232 kb
Host smart-82220772-c530-430c-9022-e4756b35e6f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040525558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3040525558
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3016400571
Short name T370
Test name
Test status
Simulation time 94312985 ps
CPU time 0.65 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:16:59 PM PDT 24
Peak memory 182864 kb
Host smart-6ed64f24-cde8-4300-b4a9-df49459d2d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016400571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3016400571
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2839620176
Short name T172
Test name
Test status
Simulation time 823563705596 ps
CPU time 274.51 seconds
Started Apr 28 02:18:37 PM PDT 24
Finished Apr 28 02:23:12 PM PDT 24
Peak memory 191236 kb
Host smart-0888b716-62cd-4607-9284-4aec49a5bd48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839620176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2839620176
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3831201630
Short name T334
Test name
Test status
Simulation time 34586698149 ps
CPU time 50.27 seconds
Started Apr 28 02:18:37 PM PDT 24
Finished Apr 28 02:19:28 PM PDT 24
Peak memory 182920 kb
Host smart-4c8c8805-b822-4bf7-8359-b42cfa573537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831201630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3831201630
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.4031145717
Short name T170
Test name
Test status
Simulation time 412170553486 ps
CPU time 405.41 seconds
Started Apr 28 02:18:43 PM PDT 24
Finished Apr 28 02:25:29 PM PDT 24
Peak memory 191236 kb
Host smart-33cc59c1-f467-4429-93ac-b365ba58677c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031145717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4031145717
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1564401976
Short name T360
Test name
Test status
Simulation time 195711969426 ps
CPU time 99.74 seconds
Started Apr 28 02:18:42 PM PDT 24
Finished Apr 28 02:20:22 PM PDT 24
Peak memory 191276 kb
Host smart-247870a6-cc8f-4835-959c-9d7a7bb9e98a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564401976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1564401976
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1393846002
Short name T362
Test name
Test status
Simulation time 122045942189 ps
CPU time 39.66 seconds
Started Apr 28 02:18:42 PM PDT 24
Finished Apr 28 02:19:22 PM PDT 24
Peak memory 182908 kb
Host smart-35c17611-1b8c-4649-af07-248c6b268c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393846002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1393846002
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.243461886
Short name T161
Test name
Test status
Simulation time 2139575219155 ps
CPU time 1730.27 seconds
Started Apr 28 02:18:43 PM PDT 24
Finished Apr 28 02:47:33 PM PDT 24
Peak memory 191200 kb
Host smart-29e4305e-9906-442c-83d0-ff6c8fd5b3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243461886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.243461886
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.836885141
Short name T323
Test name
Test status
Simulation time 57743042428 ps
CPU time 1162.57 seconds
Started Apr 28 02:18:43 PM PDT 24
Finished Apr 28 02:38:06 PM PDT 24
Peak memory 183040 kb
Host smart-d2d960f0-343e-4814-a8cb-d19782492a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836885141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.836885141
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.696027136
Short name T429
Test name
Test status
Simulation time 554259444609 ps
CPU time 170.19 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:19:48 PM PDT 24
Peak memory 183048 kb
Host smart-e8bc49c8-3cd6-4765-bffe-1b92afedba09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696027136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.696027136
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3238976354
Short name T447
Test name
Test status
Simulation time 322128874525 ps
CPU time 148.26 seconds
Started Apr 28 02:17:00 PM PDT 24
Finished Apr 28 02:19:28 PM PDT 24
Peak memory 191156 kb
Host smart-9165a1d5-28d0-46e1-9a81-0deb7d3ba117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238976354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3238976354
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2131579107
Short name T239
Test name
Test status
Simulation time 542584289665 ps
CPU time 283.24 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:21:52 PM PDT 24
Peak memory 191280 kb
Host smart-4dd63cb7-b371-499a-ac25-a375e5f0190a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131579107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2131579107
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.787309683
Short name T308
Test name
Test status
Simulation time 132531319587 ps
CPU time 726.08 seconds
Started Apr 28 02:18:47 PM PDT 24
Finished Apr 28 02:30:54 PM PDT 24
Peak memory 191244 kb
Host smart-8a73437f-cd8b-4ba7-bd9d-7e55aab25964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787309683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.787309683
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.398689884
Short name T431
Test name
Test status
Simulation time 116302392591 ps
CPU time 267.21 seconds
Started Apr 28 02:18:52 PM PDT 24
Finished Apr 28 02:23:20 PM PDT 24
Peak memory 191228 kb
Host smart-31098b90-1f67-4577-8ee5-3b951b4f8508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398689884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.398689884
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2587132906
Short name T358
Test name
Test status
Simulation time 2770768202 ps
CPU time 4.46 seconds
Started Apr 28 02:18:52 PM PDT 24
Finished Apr 28 02:18:57 PM PDT 24
Peak memory 182940 kb
Host smart-ac1865b3-2700-4643-bac5-986ee3b39b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587132906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2587132906
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.8794338
Short name T311
Test name
Test status
Simulation time 172808678073 ps
CPU time 216.4 seconds
Started Apr 28 02:18:56 PM PDT 24
Finished Apr 28 02:22:33 PM PDT 24
Peak memory 191256 kb
Host smart-fd33e67f-df70-4f07-ad46-e0fbf525a1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8794338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.8794338
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3348920789
Short name T292
Test name
Test status
Simulation time 416557474690 ps
CPU time 192.78 seconds
Started Apr 28 02:18:51 PM PDT 24
Finished Apr 28 02:22:05 PM PDT 24
Peak memory 191276 kb
Host smart-2a9807ec-dad3-4fa5-a572-8ae2ce8c22a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348920789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3348920789
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.164706229
Short name T189
Test name
Test status
Simulation time 1398063009931 ps
CPU time 719.54 seconds
Started Apr 28 02:17:03 PM PDT 24
Finished Apr 28 02:29:03 PM PDT 24
Peak memory 183076 kb
Host smart-a01a8fe2-41e5-4f53-ae7a-f720141c0281
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164706229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.164706229
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3613028000
Short name T395
Test name
Test status
Simulation time 61357329413 ps
CPU time 86.33 seconds
Started Apr 28 02:16:53 PM PDT 24
Finished Apr 28 02:18:20 PM PDT 24
Peak memory 183072 kb
Host smart-98efc724-026d-46f0-8ce4-0d145159863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613028000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3613028000
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.826610197
Short name T174
Test name
Test status
Simulation time 123305590889 ps
CPU time 349.32 seconds
Started Apr 28 02:16:52 PM PDT 24
Finished Apr 28 02:22:42 PM PDT 24
Peak memory 191252 kb
Host smart-5df09cb4-cdce-4c0e-8fb3-755f7ab401d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826610197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.826610197
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3654598335
Short name T364
Test name
Test status
Simulation time 60537403135 ps
CPU time 91.63 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:18:31 PM PDT 24
Peak memory 191280 kb
Host smart-6733b910-8775-4278-a0fc-4c73d655c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654598335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3654598335
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1563797182
Short name T83
Test name
Test status
Simulation time 44702057054 ps
CPU time 322.92 seconds
Started Apr 28 02:16:53 PM PDT 24
Finished Apr 28 02:22:16 PM PDT 24
Peak memory 205896 kb
Host smart-f927a407-13d0-46db-a974-ee5c3e6b5145
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563797182 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1563797182
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.3377088666
Short name T234
Test name
Test status
Simulation time 32920340937 ps
CPU time 227.46 seconds
Started Apr 28 02:19:01 PM PDT 24
Finished Apr 28 02:22:49 PM PDT 24
Peak memory 191260 kb
Host smart-483bda5b-f04b-4f1b-8165-749c77a9481a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377088666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3377088666
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.4282041979
Short name T279
Test name
Test status
Simulation time 548516404808 ps
CPU time 298.31 seconds
Started Apr 28 02:18:57 PM PDT 24
Finished Apr 28 02:23:56 PM PDT 24
Peak memory 191260 kb
Host smart-d24b3514-7750-4305-b509-ed329f8dceef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282041979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.4282041979
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.19222961
Short name T130
Test name
Test status
Simulation time 135271136702 ps
CPU time 63.13 seconds
Started Apr 28 02:18:57 PM PDT 24
Finished Apr 28 02:20:00 PM PDT 24
Peak memory 194720 kb
Host smart-17e27df2-0392-4fe0-a789-29b8fb01ef73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19222961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.19222961
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2293915978
Short name T203
Test name
Test status
Simulation time 86272728469 ps
CPU time 148.27 seconds
Started Apr 28 02:19:08 PM PDT 24
Finished Apr 28 02:21:36 PM PDT 24
Peak memory 191248 kb
Host smart-595ffa38-157d-4a74-a9bf-fe9b47fff1a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293915978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2293915978
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.636685023
Short name T213
Test name
Test status
Simulation time 25731643930 ps
CPU time 241.59 seconds
Started Apr 28 02:19:07 PM PDT 24
Finished Apr 28 02:23:09 PM PDT 24
Peak memory 191248 kb
Host smart-2d1adc72-4857-4b05-9a3f-d985ba93c1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636685023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.636685023
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4011662419
Short name T253
Test name
Test status
Simulation time 582271786827 ps
CPU time 606.13 seconds
Started Apr 28 02:19:08 PM PDT 24
Finished Apr 28 02:29:15 PM PDT 24
Peak memory 191240 kb
Host smart-2e56276c-8472-4d06-af99-2e7f9137f932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011662419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4011662419
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1497585911
Short name T401
Test name
Test status
Simulation time 118185140857 ps
CPU time 20.19 seconds
Started Apr 28 02:19:01 PM PDT 24
Finished Apr 28 02:19:21 PM PDT 24
Peak memory 182900 kb
Host smart-402cf4b4-06a0-478e-beb0-90517ce6b681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497585911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1497585911
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.344072845
Short name T166
Test name
Test status
Simulation time 676532674577 ps
CPU time 606.85 seconds
Started Apr 28 02:19:02 PM PDT 24
Finished Apr 28 02:29:09 PM PDT 24
Peak memory 191244 kb
Host smart-f05ac20f-7a6c-4e9b-b150-4cfee1b26558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344072845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.344072845
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.643442295
Short name T263
Test name
Test status
Simulation time 1463006063940 ps
CPU time 382.12 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:22:58 PM PDT 24
Peak memory 183012 kb
Host smart-04e53671-4d98-4383-8dce-56f56008a4fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643442295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.643442295
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3883911004
Short name T19
Test name
Test status
Simulation time 111570913087 ps
CPU time 174.54 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:19:29 PM PDT 24
Peak memory 182900 kb
Host smart-cba58c1f-7ac8-48c5-90b1-bbe7cc8df113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883911004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3883911004
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.982195142
Short name T336
Test name
Test status
Simulation time 50195671997 ps
CPU time 891.78 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:31:29 PM PDT 24
Peak memory 191208 kb
Host smart-a8c4985c-d248-47f1-989b-022a5c4ff8d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982195142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.982195142
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1109335454
Short name T17
Test name
Test status
Simulation time 65679499 ps
CPU time 0.85 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:16:36 PM PDT 24
Peak memory 214092 kb
Host smart-2d6e404c-f6a8-451e-a3e6-343b9f85fb55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109335454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1109335454
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2831569147
Short name T415
Test name
Test status
Simulation time 43957399383 ps
CPU time 35.65 seconds
Started Apr 28 02:16:31 PM PDT 24
Finished Apr 28 02:17:07 PM PDT 24
Peak memory 183116 kb
Host smart-e0409074-af00-4abd-927a-1a92be5a4ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831569147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2831569147
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.1990954144
Short name T40
Test name
Test status
Simulation time 137401161513 ps
CPU time 989.84 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:33:10 PM PDT 24
Peak memory 210992 kb
Host smart-dda2d367-6818-4f25-b72a-f73525aa0ff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990954144 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.1990954144
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.289315268
Short name T100
Test name
Test status
Simulation time 424130451024 ps
CPU time 188.33 seconds
Started Apr 28 02:17:00 PM PDT 24
Finished Apr 28 02:20:09 PM PDT 24
Peak memory 183040 kb
Host smart-b123a998-ad26-42d7-be2c-5b006acae8ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289315268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.289315268
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1415975702
Short name T424
Test name
Test status
Simulation time 124863705063 ps
CPU time 174.98 seconds
Started Apr 28 02:16:52 PM PDT 24
Finished Apr 28 02:19:47 PM PDT 24
Peak memory 183044 kb
Host smart-17fa23e1-e091-4b03-bf67-778130ebe175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415975702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1415975702
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1445480671
Short name T353
Test name
Test status
Simulation time 107845799320 ps
CPU time 41.43 seconds
Started Apr 28 02:16:52 PM PDT 24
Finished Apr 28 02:17:34 PM PDT 24
Peak memory 183044 kb
Host smart-d6639616-5fc3-41bc-b944-e21fea61cce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445480671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1445480671
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2715576452
Short name T416
Test name
Test status
Simulation time 1321536055008 ps
CPU time 583.68 seconds
Started Apr 28 02:16:52 PM PDT 24
Finished Apr 28 02:26:36 PM PDT 24
Peak memory 191208 kb
Host smart-f1e288fc-3fad-4eaa-a6ac-2f6bbd4a9dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715576452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2715576452
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.4107148029
Short name T23
Test name
Test status
Simulation time 58212454845 ps
CPU time 98.45 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:18:36 PM PDT 24
Peak memory 183084 kb
Host smart-90dfa9f6-9c41-4a40-a1a8-0c5b7c345e0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107148029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.4107148029
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4117237941
Short name T404
Test name
Test status
Simulation time 570276104134 ps
CPU time 198.65 seconds
Started Apr 28 02:17:02 PM PDT 24
Finished Apr 28 02:20:21 PM PDT 24
Peak memory 183072 kb
Host smart-b8ef73bc-34af-4f14-afd3-02de42c8fbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117237941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4117237941
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1996733066
Short name T287
Test name
Test status
Simulation time 196549007882 ps
CPU time 86.94 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:18:36 PM PDT 24
Peak memory 191280 kb
Host smart-ecd53455-f198-4e77-a46f-c11a199aff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996733066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1996733066
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3263554491
Short name T219
Test name
Test status
Simulation time 630647668867 ps
CPU time 305.23 seconds
Started Apr 28 02:17:11 PM PDT 24
Finished Apr 28 02:22:17 PM PDT 24
Peak memory 183088 kb
Host smart-1130b2a1-1257-449d-b68e-9b676bb9bf83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263554491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3263554491
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3747799941
Short name T403
Test name
Test status
Simulation time 28153015976 ps
CPU time 36.72 seconds
Started Apr 28 02:17:09 PM PDT 24
Finished Apr 28 02:17:46 PM PDT 24
Peak memory 183028 kb
Host smart-59950721-5402-470f-a801-846cfa628a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747799941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3747799941
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3321042781
Short name T397
Test name
Test status
Simulation time 60218843758 ps
CPU time 145.95 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:19:34 PM PDT 24
Peak memory 191256 kb
Host smart-4ad3f393-a8c0-4bf1-b56e-42e030f504cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321042781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3321042781
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2436131176
Short name T387
Test name
Test status
Simulation time 572628754895 ps
CPU time 101.81 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:18:41 PM PDT 24
Peak memory 183028 kb
Host smart-e7416014-d082-4fcd-9240-fd41841578e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436131176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2436131176
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4126245881
Short name T277
Test name
Test status
Simulation time 641341818662 ps
CPU time 356 seconds
Started Apr 28 02:17:14 PM PDT 24
Finished Apr 28 02:23:11 PM PDT 24
Peak memory 182900 kb
Host smart-b3fdd0d8-2d65-45de-b7dd-ca76925510e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126245881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4126245881
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.368765962
Short name T392
Test name
Test status
Simulation time 463294031197 ps
CPU time 168.84 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:19:46 PM PDT 24
Peak memory 183048 kb
Host smart-f2939cc8-3e34-4016-b295-91fdabd8fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368765962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.368765962
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2348463735
Short name T430
Test name
Test status
Simulation time 63219124641 ps
CPU time 263.91 seconds
Started Apr 28 02:17:04 PM PDT 24
Finished Apr 28 02:21:29 PM PDT 24
Peak memory 191244 kb
Host smart-285fc449-3fe8-438c-a4d4-45948ea28d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348463735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2348463735
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.231131654
Short name T417
Test name
Test status
Simulation time 374907586 ps
CPU time 0.71 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:16:59 PM PDT 24
Peak memory 182836 kb
Host smart-0684fc7b-db79-46f5-ada4-4828b3fd5bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231131654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.231131654
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3671827033
Short name T259
Test name
Test status
Simulation time 73716470683 ps
CPU time 49.3 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:17:48 PM PDT 24
Peak memory 182948 kb
Host smart-c076b088-64ad-402d-bbef-07517efd9739
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671827033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3671827033
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1767715956
Short name T59
Test name
Test status
Simulation time 35881692969 ps
CPU time 56.86 seconds
Started Apr 28 02:17:11 PM PDT 24
Finished Apr 28 02:18:09 PM PDT 24
Peak memory 183048 kb
Host smart-bd705f5b-046b-49c9-a8ff-ac06a9a0a5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767715956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1767715956
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.18248788
Short name T316
Test name
Test status
Simulation time 217352541668 ps
CPU time 418.92 seconds
Started Apr 28 02:16:57 PM PDT 24
Finished Apr 28 02:23:56 PM PDT 24
Peak memory 191252 kb
Host smart-fd9923c0-31e5-441e-ae09-386ece91c2a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18248788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.18248788
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1395135496
Short name T104
Test name
Test status
Simulation time 33471933164 ps
CPU time 59.67 seconds
Started Apr 28 02:17:03 PM PDT 24
Finished Apr 28 02:18:03 PM PDT 24
Peak memory 191292 kb
Host smart-3238ba4d-f550-4df4-b274-c248673a1cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395135496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1395135496
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.3076088162
Short name T34
Test name
Test status
Simulation time 343934319720 ps
CPU time 549.59 seconds
Started Apr 28 02:17:00 PM PDT 24
Finished Apr 28 02:26:11 PM PDT 24
Peak memory 205940 kb
Host smart-c7e43bc6-04a8-4120-8626-0a29fdc7b03e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076088162 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.3076088162
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3320838758
Short name T255
Test name
Test status
Simulation time 372802171802 ps
CPU time 605.89 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:27:22 PM PDT 24
Peak memory 183052 kb
Host smart-0ef9fd26-cab2-4afc-b21d-4decf8cdca34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320838758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3320838758
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1205763417
Short name T372
Test name
Test status
Simulation time 243281004734 ps
CPU time 196.55 seconds
Started Apr 28 02:17:13 PM PDT 24
Finished Apr 28 02:20:30 PM PDT 24
Peak memory 183048 kb
Host smart-8e18e033-db52-4a7d-8f48-fe9332273bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205763417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1205763417
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3303761250
Short name T26
Test name
Test status
Simulation time 41382578189 ps
CPU time 72.56 seconds
Started Apr 28 02:16:58 PM PDT 24
Finished Apr 28 02:18:12 PM PDT 24
Peak memory 191208 kb
Host smart-2a753116-67b1-4b05-a457-2a293e699e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303761250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3303761250
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3082740954
Short name T389
Test name
Test status
Simulation time 113365538 ps
CPU time 0.74 seconds
Started Apr 28 02:16:59 PM PDT 24
Finished Apr 28 02:17:01 PM PDT 24
Peak memory 182892 kb
Host smart-47006e29-db1c-46f3-a9b8-b9e53bdcfc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082740954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3082740954
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.349812614
Short name T165
Test name
Test status
Simulation time 444595302244 ps
CPU time 559.58 seconds
Started Apr 28 02:17:03 PM PDT 24
Finished Apr 28 02:26:23 PM PDT 24
Peak memory 191236 kb
Host smart-62afde2a-d7ae-4776-ab97-085fd6ffb5d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349812614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
349812614
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2068228587
Short name T425
Test name
Test status
Simulation time 175294852067 ps
CPU time 232.35 seconds
Started Apr 28 02:17:04 PM PDT 24
Finished Apr 28 02:20:58 PM PDT 24
Peak memory 183028 kb
Host smart-c48539d3-3107-4e3a-908c-3c6064e3d727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068228587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2068228587
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.152527680
Short name T256
Test name
Test status
Simulation time 535815131304 ps
CPU time 273.58 seconds
Started Apr 28 02:17:01 PM PDT 24
Finished Apr 28 02:21:35 PM PDT 24
Peak memory 191196 kb
Host smart-a4ded99e-5f88-4552-b847-535f61111899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152527680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.152527680
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.4071994263
Short name T400
Test name
Test status
Simulation time 17197058231 ps
CPU time 19.06 seconds
Started Apr 28 02:16:59 PM PDT 24
Finished Apr 28 02:17:18 PM PDT 24
Peak memory 191268 kb
Host smart-95f2119f-08f8-4667-8101-63e32168a050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071994263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.4071994263
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2272793640
Short name T118
Test name
Test status
Simulation time 1785275912122 ps
CPU time 1811.64 seconds
Started Apr 28 02:17:05 PM PDT 24
Finished Apr 28 02:47:18 PM PDT 24
Peak memory 191252 kb
Host smart-4faa6660-1ec8-463e-a845-42180c03ca45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272793640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2272793640
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1870643174
Short name T192
Test name
Test status
Simulation time 133191363146 ps
CPU time 114.12 seconds
Started Apr 28 02:17:05 PM PDT 24
Finished Apr 28 02:19:00 PM PDT 24
Peak memory 183012 kb
Host smart-2123e167-6086-46fb-bfda-d639abc86c0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870643174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1870643174
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3089619472
Short name T77
Test name
Test status
Simulation time 111272007787 ps
CPU time 163.42 seconds
Started Apr 28 02:17:09 PM PDT 24
Finished Apr 28 02:19:54 PM PDT 24
Peak memory 182900 kb
Host smart-15e4f3c3-6deb-40c2-b2ab-b3b444a4fd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089619472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3089619472
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.183539960
Short name T293
Test name
Test status
Simulation time 1306210973719 ps
CPU time 494.85 seconds
Started Apr 28 02:16:59 PM PDT 24
Finished Apr 28 02:25:14 PM PDT 24
Peak memory 191288 kb
Host smart-861b9ea0-e23a-4aeb-beac-0b34dc090b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183539960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.183539960
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.151399393
Short name T391
Test name
Test status
Simulation time 171240872400 ps
CPU time 111.52 seconds
Started Apr 28 02:17:09 PM PDT 24
Finished Apr 28 02:19:02 PM PDT 24
Peak memory 183052 kb
Host smart-f938c84f-5bb8-4dce-b100-bdb0cc1649f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151399393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
151399393
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2341410918
Short name T341
Test name
Test status
Simulation time 2526758898323 ps
CPU time 1479.91 seconds
Started Apr 28 02:17:14 PM PDT 24
Finished Apr 28 02:41:55 PM PDT 24
Peak memory 183040 kb
Host smart-090954a2-d8fc-48e8-96c0-6760eed8e358
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341410918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2341410918
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3999471662
Short name T70
Test name
Test status
Simulation time 77689738294 ps
CPU time 124.87 seconds
Started Apr 28 02:17:06 PM PDT 24
Finished Apr 28 02:19:11 PM PDT 24
Peak memory 183064 kb
Host smart-e2874234-1385-4f9e-84df-5754e68d1e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999471662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3999471662
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2751927639
Short name T278
Test name
Test status
Simulation time 777890534086 ps
CPU time 434.49 seconds
Started Apr 28 02:17:04 PM PDT 24
Finished Apr 28 02:24:20 PM PDT 24
Peak memory 191240 kb
Host smart-399381dc-0c2f-462d-8e28-81449056a980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751927639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2751927639
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1210268861
Short name T382
Test name
Test status
Simulation time 4915049617 ps
CPU time 82.91 seconds
Started Apr 28 02:17:05 PM PDT 24
Finished Apr 28 02:18:29 PM PDT 24
Peak memory 191140 kb
Host smart-2e555fd6-19b1-4606-b726-0aaf5c780653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210268861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1210268861
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3632276928
Short name T3
Test name
Test status
Simulation time 102154569 ps
CPU time 0.66 seconds
Started Apr 28 02:17:02 PM PDT 24
Finished Apr 28 02:17:03 PM PDT 24
Peak memory 182872 kb
Host smart-8b28d5db-ee48-4705-a6cd-d09f53999c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632276928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3632276928
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3256211428
Short name T81
Test name
Test status
Simulation time 112248848061 ps
CPU time 890.86 seconds
Started Apr 28 02:17:02 PM PDT 24
Finished Apr 28 02:31:54 PM PDT 24
Peak memory 205852 kb
Host smart-45355db1-195b-4f35-91f5-bcb54208c84f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256211428 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3256211428
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3463210336
Short name T428
Test name
Test status
Simulation time 60035836662 ps
CPU time 86.02 seconds
Started Apr 28 02:17:13 PM PDT 24
Finished Apr 28 02:18:39 PM PDT 24
Peak memory 182956 kb
Host smart-110de60b-9875-4c60-8a69-d580b8923ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463210336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3463210336
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1958644494
Short name T304
Test name
Test status
Simulation time 62991203333 ps
CPU time 381.6 seconds
Started Apr 28 02:17:05 PM PDT 24
Finished Apr 28 02:23:28 PM PDT 24
Peak memory 191220 kb
Host smart-fb525025-d4d4-4067-b519-ec03b93e0a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958644494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1958644494
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3197514526
Short name T375
Test name
Test status
Simulation time 189188744 ps
CPU time 0.65 seconds
Started Apr 28 02:17:12 PM PDT 24
Finished Apr 28 02:17:14 PM PDT 24
Peak memory 182832 kb
Host smart-fd30bb50-c333-4b9b-a794-9e4d9bb31e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197514526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3197514526
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_random.4285412245
Short name T60
Test name
Test status
Simulation time 80726811233 ps
CPU time 242.38 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:20:38 PM PDT 24
Peak memory 191224 kb
Host smart-66f3d523-d580-4300-8bd4-2ead78c4030b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285412245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4285412245
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2071449627
Short name T290
Test name
Test status
Simulation time 225487741936 ps
CPU time 156.44 seconds
Started Apr 28 02:16:37 PM PDT 24
Finished Apr 28 02:19:14 PM PDT 24
Peak memory 191216 kb
Host smart-ee943274-5877-47ea-a569-d0c134b01061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071449627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2071449627
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3068124793
Short name T15
Test name
Test status
Simulation time 73216798 ps
CPU time 0.88 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 213428 kb
Host smart-f3f12d59-6cb1-42e8-be74-eff79da2143e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068124793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3068124793
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.812686259
Short name T281
Test name
Test status
Simulation time 47786178510 ps
CPU time 208.89 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:20:03 PM PDT 24
Peak memory 191264 kb
Host smart-1b3dc461-478b-47a9-9302-984efdd952e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812686259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.812686259
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.889687470
Short name T218
Test name
Test status
Simulation time 2325714609463 ps
CPU time 1383.31 seconds
Started Apr 28 02:17:04 PM PDT 24
Finished Apr 28 02:40:08 PM PDT 24
Peak memory 183068 kb
Host smart-81eda40d-66cb-44f4-9c20-be6aea4d52ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889687470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.889687470
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.985415371
Short name T394
Test name
Test status
Simulation time 6996180580 ps
CPU time 6.15 seconds
Started Apr 28 02:17:12 PM PDT 24
Finished Apr 28 02:17:19 PM PDT 24
Peak memory 183044 kb
Host smart-2a0a4567-ea2a-465f-a94c-2a2334ced274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985415371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.985415371
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1093311957
Short name T154
Test name
Test status
Simulation time 118141547375 ps
CPU time 197.21 seconds
Started Apr 28 02:17:13 PM PDT 24
Finished Apr 28 02:20:31 PM PDT 24
Peak memory 191252 kb
Host smart-2efd2630-98dd-4a45-a362-7c1ffc22ac66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093311957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1093311957
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.4214566390
Short name T63
Test name
Test status
Simulation time 96417806672 ps
CPU time 552.7 seconds
Started Apr 28 02:17:07 PM PDT 24
Finished Apr 28 02:26:20 PM PDT 24
Peak memory 195380 kb
Host smart-9eb1dc2c-9f2d-45f6-8208-95f4b8f28cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214566390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.4214566390
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1727806198
Short name T142
Test name
Test status
Simulation time 1214416336809 ps
CPU time 697.94 seconds
Started Apr 28 02:17:09 PM PDT 24
Finished Apr 28 02:28:47 PM PDT 24
Peak memory 183080 kb
Host smart-026b1e8f-6e0e-4370-80d4-ad0d6ea33e24
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727806198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1727806198
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.822790733
Short name T378
Test name
Test status
Simulation time 275211019956 ps
CPU time 215.09 seconds
Started Apr 28 02:17:03 PM PDT 24
Finished Apr 28 02:20:38 PM PDT 24
Peak memory 183076 kb
Host smart-673aa337-b552-4f91-9399-bbe63347ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822790733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.822790733
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2589698583
Short name T7
Test name
Test status
Simulation time 67992762136 ps
CPU time 99.32 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:18:55 PM PDT 24
Peak memory 191248 kb
Host smart-f46e9dd0-8246-4070-b69f-a94b12aa1a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589698583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2589698583
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2595068734
Short name T204
Test name
Test status
Simulation time 3776649060091 ps
CPU time 911.49 seconds
Started Apr 28 02:17:05 PM PDT 24
Finished Apr 28 02:32:18 PM PDT 24
Peak memory 194632 kb
Host smart-ad85641b-6a9a-4177-86f3-8a1ef328ef6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595068734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2595068734
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.67448705
Short name T446
Test name
Test status
Simulation time 249430248089 ps
CPU time 377.86 seconds
Started Apr 28 02:17:05 PM PDT 24
Finished Apr 28 02:23:24 PM PDT 24
Peak memory 182912 kb
Host smart-19cf32d5-8078-45a8-bc15-fa6ab1a6b2c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67448705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.rv_timer_cfg_update_on_fly.67448705
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_random.1297421906
Short name T296
Test name
Test status
Simulation time 170501185210 ps
CPU time 324.23 seconds
Started Apr 28 02:17:10 PM PDT 24
Finished Apr 28 02:22:35 PM PDT 24
Peak memory 191272 kb
Host smart-9d8823ee-4a7e-4ae5-b27b-62ed5a58b300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297421906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1297421906
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3312725654
Short name T27
Test name
Test status
Simulation time 201333430022 ps
CPU time 152.65 seconds
Started Apr 28 02:17:04 PM PDT 24
Finished Apr 28 02:19:38 PM PDT 24
Peak memory 183052 kb
Host smart-5ceb97b5-6c75-4a6d-88d3-535430db4ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312725654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3312725654
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.315921148
Short name T388
Test name
Test status
Simulation time 202916995561 ps
CPU time 266.46 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:21:44 PM PDT 24
Peak memory 183048 kb
Host smart-ec4efa2a-c568-40e1-9352-4eacbb33c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315921148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.315921148
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1923697294
Short name T301
Test name
Test status
Simulation time 435426187740 ps
CPU time 192.42 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:20:30 PM PDT 24
Peak memory 191212 kb
Host smart-6fd2a128-41a4-48c2-aed3-2ce65a0586b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923697294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1923697294
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1766694429
Short name T303
Test name
Test status
Simulation time 117123503874 ps
CPU time 322.32 seconds
Started Apr 28 02:17:05 PM PDT 24
Finished Apr 28 02:22:28 PM PDT 24
Peak memory 191188 kb
Host smart-52c71b3e-0584-4e73-ac17-ca33941ecfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766694429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1766694429
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2578625373
Short name T50
Test name
Test status
Simulation time 87950550370 ps
CPU time 194.07 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:20:30 PM PDT 24
Peak memory 197712 kb
Host smart-a33f4e92-5fa7-49ff-befb-5bde77966ba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578625373 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.2578625373
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2247566658
Short name T299
Test name
Test status
Simulation time 396032605118 ps
CPU time 647.53 seconds
Started Apr 28 02:17:07 PM PDT 24
Finished Apr 28 02:27:55 PM PDT 24
Peak memory 183100 kb
Host smart-be19557d-cf11-4816-8b51-05cf1f329351
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247566658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2247566658
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.871952052
Short name T444
Test name
Test status
Simulation time 37576732540 ps
CPU time 54.29 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:18:11 PM PDT 24
Peak memory 183048 kb
Host smart-27f19e46-1988-437b-91a5-f941105558e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871952052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.871952052
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2785954068
Short name T386
Test name
Test status
Simulation time 480690783 ps
CPU time 0.77 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:17:17 PM PDT 24
Peak memory 182892 kb
Host smart-94014d8f-680e-44ed-9cfe-bbd00f1742f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785954068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2785954068
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.44944127
Short name T434
Test name
Test status
Simulation time 229809824537 ps
CPU time 319.4 seconds
Started Apr 28 02:17:09 PM PDT 24
Finished Apr 28 02:22:30 PM PDT 24
Peak memory 191248 kb
Host smart-cb5ce0dc-17ef-4e8b-b49b-61410c5cca5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44944127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.44944127
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2724272456
Short name T182
Test name
Test status
Simulation time 53007277438 ps
CPU time 29.38 seconds
Started Apr 28 02:17:13 PM PDT 24
Finished Apr 28 02:17:43 PM PDT 24
Peak memory 183060 kb
Host smart-9e0b516c-a526-4ab7-be5c-eef4f8a68f7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724272456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2724272456
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.531906094
Short name T436
Test name
Test status
Simulation time 122065602751 ps
CPU time 56.68 seconds
Started Apr 28 02:17:21 PM PDT 24
Finished Apr 28 02:18:18 PM PDT 24
Peak memory 183032 kb
Host smart-759a661c-1d46-44c5-b48a-f39e67cd3c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531906094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.531906094
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3335206250
Short name T139
Test name
Test status
Simulation time 553485394953 ps
CPU time 494.59 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:25:31 PM PDT 24
Peak memory 191104 kb
Host smart-46b8ecc5-7b82-4660-8f71-332c15f01d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335206250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3335206250
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4234469274
Short name T291
Test name
Test status
Simulation time 92207688327 ps
CPU time 1892.17 seconds
Started Apr 28 02:17:09 PM PDT 24
Finished Apr 28 02:48:42 PM PDT 24
Peak memory 191204 kb
Host smart-71d226d8-5775-4a8e-88f1-69aee08ebd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234469274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4234469274
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2492008002
Short name T209
Test name
Test status
Simulation time 694095246222 ps
CPU time 741.37 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:29:30 PM PDT 24
Peak memory 191192 kb
Host smart-a5853f2e-a611-4a6d-b5a9-13922334454e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492008002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2492008002
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1160353588
Short name T422
Test name
Test status
Simulation time 114727457430 ps
CPU time 103.57 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:18:52 PM PDT 24
Peak memory 183056 kb
Host smart-3dc43435-8793-429a-8333-eb75093acd13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160353588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1160353588
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1152828581
Short name T367
Test name
Test status
Simulation time 544207192220 ps
CPU time 194.79 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:20:30 PM PDT 24
Peak memory 183072 kb
Host smart-bab115f6-9c18-4b59-833b-5e1773c98cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152828581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1152828581
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1029522542
Short name T206
Test name
Test status
Simulation time 110340226434 ps
CPU time 100.04 seconds
Started Apr 28 02:17:12 PM PDT 24
Finished Apr 28 02:18:53 PM PDT 24
Peak memory 191264 kb
Host smart-19f625ff-9072-4a33-9bcf-3414a7ec738b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029522542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1029522542
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.674315514
Short name T283
Test name
Test status
Simulation time 337799950484 ps
CPU time 471.34 seconds
Started Apr 28 02:17:11 PM PDT 24
Finished Apr 28 02:25:03 PM PDT 24
Peak memory 191200 kb
Host smart-e6d12b4a-0c5c-413c-979c-b3bde4ca55e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674315514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.674315514
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1914586855
Short name T272
Test name
Test status
Simulation time 663654269612 ps
CPU time 947.23 seconds
Started Apr 28 02:17:10 PM PDT 24
Finished Apr 28 02:32:58 PM PDT 24
Peak memory 194768 kb
Host smart-c9ba56dd-c91e-4594-a2b7-6b90f132b52c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914586855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1914586855
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1942036163
Short name T47
Test name
Test status
Simulation time 719762025791 ps
CPU time 429.2 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:24:18 PM PDT 24
Peak memory 183024 kb
Host smart-04a94f94-7363-46c1-9d14-f5eb1e21c333
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942036163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1942036163
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2605667523
Short name T78
Test name
Test status
Simulation time 25573139024 ps
CPU time 42.84 seconds
Started Apr 28 02:17:18 PM PDT 24
Finished Apr 28 02:18:01 PM PDT 24
Peak memory 183064 kb
Host smart-db0fa23e-e41c-4d94-8844-e845b0d86e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605667523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2605667523
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1189275443
Short name T419
Test name
Test status
Simulation time 225945772597 ps
CPU time 192.07 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:20:28 PM PDT 24
Peak memory 194608 kb
Host smart-46514032-d91f-4e83-8fe3-d448b359aefc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189275443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1189275443
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2331749075
Short name T443
Test name
Test status
Simulation time 51030521176 ps
CPU time 102.71 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:18:59 PM PDT 24
Peak memory 183072 kb
Host smart-6f45679f-4613-4847-982a-31154a68c322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331749075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2331749075
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3607055245
Short name T432
Test name
Test status
Simulation time 1873092426851 ps
CPU time 509.86 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:25:39 PM PDT 24
Peak memory 191216 kb
Host smart-0f0da6cb-4e08-49e1-90db-638e2f064837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607055245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3607055245
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1834793355
Short name T41
Test name
Test status
Simulation time 208065103281 ps
CPU time 372.32 seconds
Started Apr 28 02:17:14 PM PDT 24
Finished Apr 28 02:23:28 PM PDT 24
Peak memory 183084 kb
Host smart-7f8a4fdd-18b4-4a82-8197-2482185ad930
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834793355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1834793355
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1847029717
Short name T377
Test name
Test status
Simulation time 1932968051 ps
CPU time 3.66 seconds
Started Apr 28 02:17:12 PM PDT 24
Finished Apr 28 02:17:17 PM PDT 24
Peak memory 182804 kb
Host smart-bf01c4eb-4f2f-4e4d-bd83-d0026747202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847029717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1847029717
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.667926486
Short name T257
Test name
Test status
Simulation time 74599628552 ps
CPU time 276.33 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:21:53 PM PDT 24
Peak memory 191120 kb
Host smart-cc6f2046-0231-4cab-bde5-b8be135c0b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667926486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.667926486
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1184976095
Short name T39
Test name
Test status
Simulation time 72558539567 ps
CPU time 588.11 seconds
Started Apr 28 02:17:11 PM PDT 24
Finished Apr 28 02:27:00 PM PDT 24
Peak memory 205512 kb
Host smart-7831c1e9-4b5f-4d38-b763-47ec725c093b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184976095 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1184976095
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3546543059
Short name T282
Test name
Test status
Simulation time 124007872454 ps
CPU time 216.68 seconds
Started Apr 28 02:17:18 PM PDT 24
Finished Apr 28 02:20:56 PM PDT 24
Peak memory 182924 kb
Host smart-81750cca-ce60-48a8-b163-2b0e98a777d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546543059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3546543059
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.221945550
Short name T376
Test name
Test status
Simulation time 245932759142 ps
CPU time 205.62 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:20:41 PM PDT 24
Peak memory 183024 kb
Host smart-9033bdef-5bf6-455b-a4f3-3669698b4b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221945550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.221945550
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2397579154
Short name T75
Test name
Test status
Simulation time 223758772011 ps
CPU time 210.84 seconds
Started Apr 28 02:17:14 PM PDT 24
Finished Apr 28 02:20:46 PM PDT 24
Peak memory 191268 kb
Host smart-cd868043-fff8-432a-927d-4a3988384502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397579154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2397579154
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3552376906
Short name T407
Test name
Test status
Simulation time 328256667 ps
CPU time 0.63 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:17:09 PM PDT 24
Peak memory 182840 kb
Host smart-eef82e26-4c96-484f-8706-69032a26e626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552376906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3552376906
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.692963008
Short name T369
Test name
Test status
Simulation time 801389164793 ps
CPU time 372.88 seconds
Started Apr 28 02:17:11 PM PDT 24
Finished Apr 28 02:23:25 PM PDT 24
Peak memory 190876 kb
Host smart-0bec23b7-60c5-436b-b354-3668b4e92a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692963008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
692963008
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.345334755
Short name T357
Test name
Test status
Simulation time 167175852125 ps
CPU time 130.31 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:18:50 PM PDT 24
Peak memory 183052 kb
Host smart-babf32a7-94a3-4a10-8c45-8f247526795a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345334755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.345334755
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3702154986
Short name T371
Test name
Test status
Simulation time 19798757333 ps
CPU time 27.91 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:17:04 PM PDT 24
Peak memory 183076 kb
Host smart-f8e64151-03d2-49e3-9f11-f5a0ca9a70f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702154986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3702154986
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2630034716
Short name T320
Test name
Test status
Simulation time 26438955309 ps
CPU time 53.45 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:17:33 PM PDT 24
Peak memory 193748 kb
Host smart-f246549b-eb1e-41bf-a5f9-04273814f205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630034716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2630034716
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2159683131
Short name T333
Test name
Test status
Simulation time 129078701550 ps
CPU time 125.83 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:18:41 PM PDT 24
Peak memory 191260 kb
Host smart-778a80d5-7d04-4c5c-9932-92f3a8e86848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159683131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2159683131
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.228545287
Short name T18
Test name
Test status
Simulation time 288216384 ps
CPU time 0.74 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 214040 kb
Host smart-7c66cda4-06a1-4609-8db9-b557e4a72ba1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228545287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.228545287
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1357777858
Short name T318
Test name
Test status
Simulation time 1375072607205 ps
CPU time 1365.92 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:40:02 PM PDT 24
Peak memory 183088 kb
Host smart-e6709556-5137-4cf7-9847-93b644d43971
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357777858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1357777858
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.586458555
Short name T368
Test name
Test status
Simulation time 9171975927 ps
CPU time 4.71 seconds
Started Apr 28 02:17:10 PM PDT 24
Finished Apr 28 02:17:15 PM PDT 24
Peak memory 183060 kb
Host smart-2b670ecc-0b92-4c61-a75b-f71911a51d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586458555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.586458555
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2012262451
Short name T137
Test name
Test status
Simulation time 568503198720 ps
CPU time 839.35 seconds
Started Apr 28 02:17:08 PM PDT 24
Finished Apr 28 02:31:08 PM PDT 24
Peak memory 191092 kb
Host smart-1e338642-d864-416c-9539-5672ce83f730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012262451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2012262451
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.518168586
Short name T314
Test name
Test status
Simulation time 46717971124 ps
CPU time 49.92 seconds
Started Apr 28 02:17:07 PM PDT 24
Finished Apr 28 02:17:58 PM PDT 24
Peak memory 183040 kb
Host smart-5f34dfea-0826-4e14-a43a-2883ac039832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518168586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.518168586
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3905509492
Short name T324
Test name
Test status
Simulation time 1031189433685 ps
CPU time 570.82 seconds
Started Apr 28 02:17:28 PM PDT 24
Finished Apr 28 02:26:59 PM PDT 24
Peak memory 183020 kb
Host smart-c1d2a49b-15f2-454b-a655-35cd763bd60d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905509492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3905509492
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2900927855
Short name T402
Test name
Test status
Simulation time 102088159522 ps
CPU time 159.45 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:20:03 PM PDT 24
Peak memory 182968 kb
Host smart-e4a2d30f-2176-4c98-b24e-5916e5f4a11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900927855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2900927855
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2755353507
Short name T124
Test name
Test status
Simulation time 38609550859 ps
CPU time 60.78 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:18:16 PM PDT 24
Peak memory 182892 kb
Host smart-9522a611-7c6a-4844-b60d-f2228acebb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755353507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2755353507
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1693766354
Short name T102
Test name
Test status
Simulation time 6501597888 ps
CPU time 6.94 seconds
Started Apr 28 02:17:17 PM PDT 24
Finished Apr 28 02:17:24 PM PDT 24
Peak memory 183016 kb
Host smart-fca56a00-77e9-4a44-8b6d-1c5580ff9190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693766354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1693766354
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.4192550152
Short name T327
Test name
Test status
Simulation time 1164908370702 ps
CPU time 736.62 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:29:33 PM PDT 24
Peak memory 183008 kb
Host smart-187f91a7-4721-4c30-879c-a24823b696fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192550152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.4192550152
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2572732741
Short name T374
Test name
Test status
Simulation time 145273377084 ps
CPU time 233.46 seconds
Started Apr 28 02:17:13 PM PDT 24
Finished Apr 28 02:21:07 PM PDT 24
Peak memory 183000 kb
Host smart-ed767583-8424-456e-a149-0f7cf223ac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572732741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2572732741
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1216926595
Short name T329
Test name
Test status
Simulation time 732158660133 ps
CPU time 300.69 seconds
Started Apr 28 02:17:25 PM PDT 24
Finished Apr 28 02:22:26 PM PDT 24
Peak memory 191248 kb
Host smart-22667dc0-bec0-48b3-bd5b-3db6e52c8ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216926595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1216926595
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2274141551
Short name T310
Test name
Test status
Simulation time 22826293848 ps
CPU time 59.69 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:18:23 PM PDT 24
Peak memory 182944 kb
Host smart-117b7819-ea87-441d-bb9f-75eabb67bd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274141551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2274141551
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3003598811
Short name T288
Test name
Test status
Simulation time 294201981048 ps
CPU time 986.97 seconds
Started Apr 28 02:17:15 PM PDT 24
Finished Apr 28 02:33:43 PM PDT 24
Peak memory 183060 kb
Host smart-2710256c-89be-4d3a-8d87-4bba4f489d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003598811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3003598811
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2548129864
Short name T11
Test name
Test status
Simulation time 70330048657 ps
CPU time 588.31 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:27:12 PM PDT 24
Peak memory 205804 kb
Host smart-b43424ea-5cae-4149-b443-f5bda8db270b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548129864 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2548129864
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2810653672
Short name T241
Test name
Test status
Simulation time 233249930173 ps
CPU time 125.06 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:19:22 PM PDT 24
Peak memory 182904 kb
Host smart-88dc7dfb-bf66-47e7-ad5f-222773a3d120
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810653672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2810653672
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.2780805394
Short name T312
Test name
Test status
Simulation time 631924622934 ps
CPU time 431 seconds
Started Apr 28 02:17:12 PM PDT 24
Finished Apr 28 02:24:23 PM PDT 24
Peak memory 191100 kb
Host smart-1bf36148-282c-493a-8786-ae5ff9514203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780805394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2780805394
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.386346564
Short name T243
Test name
Test status
Simulation time 966391060373 ps
CPU time 613.62 seconds
Started Apr 28 02:17:19 PM PDT 24
Finished Apr 28 02:27:33 PM PDT 24
Peak memory 191256 kb
Host smart-e4ecbba3-c8e2-409e-b181-13a2f1c493db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386346564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
386346564
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.672802737
Short name T380
Test name
Test status
Simulation time 943327218530 ps
CPU time 276.14 seconds
Started Apr 28 02:17:28 PM PDT 24
Finished Apr 28 02:22:05 PM PDT 24
Peak memory 183016 kb
Host smart-f0779b4b-146c-460c-9bd4-a2ed8154d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672802737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.672802737
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.680005055
Short name T205
Test name
Test status
Simulation time 45061611545 ps
CPU time 188.62 seconds
Started Apr 28 02:17:22 PM PDT 24
Finished Apr 28 02:20:31 PM PDT 24
Peak memory 182936 kb
Host smart-3a9c935f-ea9c-413b-9b25-cff03b44d6f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680005055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.680005055
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1759993283
Short name T399
Test name
Test status
Simulation time 9766848845 ps
CPU time 18.8 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:17:43 PM PDT 24
Peak memory 183016 kb
Host smart-dfb48ba5-87fd-4fd5-a19b-cd46cb5a10f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759993283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1759993283
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3210228054
Short name T423
Test name
Test status
Simulation time 1710181965502 ps
CPU time 650.81 seconds
Started Apr 28 02:17:24 PM PDT 24
Finished Apr 28 02:28:16 PM PDT 24
Peak memory 183076 kb
Host smart-a45db2f6-8e41-47fe-b055-3efdd7902de1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210228054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3210228054
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1302727097
Short name T410
Test name
Test status
Simulation time 151305856609 ps
CPU time 195.4 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:20:39 PM PDT 24
Peak memory 183040 kb
Host smart-59e76c96-b1c4-4bd5-9257-ddf47bdd69bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302727097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1302727097
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.930585112
Short name T215
Test name
Test status
Simulation time 236006703273 ps
CPU time 218.48 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:21:02 PM PDT 24
Peak memory 191140 kb
Host smart-15d2f57b-be0c-46d5-98f4-5d952906025e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930585112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.930585112
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3384007705
Short name T4
Test name
Test status
Simulation time 356485002565 ps
CPU time 700.37 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:29:04 PM PDT 24
Peak memory 191164 kb
Host smart-afeaf232-9e65-43ce-83bc-752f4b312568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384007705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3384007705
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1812699989
Short name T349
Test name
Test status
Simulation time 201363895365 ps
CPU time 358.12 seconds
Started Apr 28 02:17:13 PM PDT 24
Finished Apr 28 02:23:11 PM PDT 24
Peak memory 183004 kb
Host smart-5fc13732-fbf5-481f-bfe7-aa2401948424
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812699989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1812699989
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1492685757
Short name T421
Test name
Test status
Simulation time 191929496419 ps
CPU time 267.77 seconds
Started Apr 28 02:17:24 PM PDT 24
Finished Apr 28 02:21:52 PM PDT 24
Peak memory 182936 kb
Host smart-4c317b4f-e8a9-49a4-914c-966f1dababbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492685757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1492685757
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1351702302
Short name T48
Test name
Test status
Simulation time 59433315345 ps
CPU time 133.64 seconds
Started Apr 28 02:17:12 PM PDT 24
Finished Apr 28 02:19:26 PM PDT 24
Peak memory 191196 kb
Host smart-f8e4b4c8-9a96-40b5-adab-b79f295dabd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351702302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1351702302
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3520476441
Short name T183
Test name
Test status
Simulation time 158785567949 ps
CPU time 76.3 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:18:33 PM PDT 24
Peak memory 182972 kb
Host smart-cf250fe0-7c0a-4f57-832f-14318e0de45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520476441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3520476441
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2121267146
Short name T168
Test name
Test status
Simulation time 392711191332 ps
CPU time 270.8 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:21:55 PM PDT 24
Peak memory 182952 kb
Host smart-4f4e9a10-b776-46c4-ab47-4bf0a791f4fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121267146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2121267146
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1487815847
Short name T411
Test name
Test status
Simulation time 164159130423 ps
CPU time 260.57 seconds
Started Apr 28 02:17:12 PM PDT 24
Finished Apr 28 02:21:33 PM PDT 24
Peak memory 183028 kb
Host smart-fe1d28e2-7d9f-416c-93f2-4e5137967f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487815847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1487815847
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2088044506
Short name T352
Test name
Test status
Simulation time 380951405993 ps
CPU time 802.37 seconds
Started Apr 28 02:17:22 PM PDT 24
Finished Apr 28 02:30:45 PM PDT 24
Peak memory 191248 kb
Host smart-e90f6466-9f90-4a5f-9b79-4892176ef0c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088044506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2088044506
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.798118271
Short name T322
Test name
Test status
Simulation time 78676494080 ps
CPU time 155.83 seconds
Started Apr 28 02:17:11 PM PDT 24
Finished Apr 28 02:19:47 PM PDT 24
Peak memory 193760 kb
Host smart-c96ff675-3e9a-4d3c-a42e-25dbcbd9b553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798118271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.798118271
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3598667573
Short name T229
Test name
Test status
Simulation time 429181022807 ps
CPU time 789.65 seconds
Started Apr 28 02:17:17 PM PDT 24
Finished Apr 28 02:30:27 PM PDT 24
Peak memory 183052 kb
Host smart-abef7ea3-cc06-4eb0-8e0a-0d62ec4a8311
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598667573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3598667573
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1324098613
Short name T412
Test name
Test status
Simulation time 623024948340 ps
CPU time 242.88 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:21:27 PM PDT 24
Peak memory 182980 kb
Host smart-e56b08f7-f5f7-4a6c-80a4-5e1d9be39b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324098613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1324098613
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2013376058
Short name T307
Test name
Test status
Simulation time 48132991357 ps
CPU time 123.48 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:19:27 PM PDT 24
Peak memory 191176 kb
Host smart-5784b14e-62ae-463a-9a48-51411e7ca661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013376058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2013376058
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2276609495
Short name T266
Test name
Test status
Simulation time 367412571467 ps
CPU time 145.27 seconds
Started Apr 28 02:17:27 PM PDT 24
Finished Apr 28 02:19:53 PM PDT 24
Peak memory 183016 kb
Host smart-74a53272-4df0-4740-995a-ecfd6709fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276609495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2276609495
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.4004241772
Short name T379
Test name
Test status
Simulation time 266411188182 ps
CPU time 198.62 seconds
Started Apr 28 02:17:16 PM PDT 24
Finished Apr 28 02:20:36 PM PDT 24
Peak memory 183048 kb
Host smart-5ebc65a8-1eab-4e1e-86c7-d0ac230f7321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004241772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4004241772
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4249397614
Short name T135
Test name
Test status
Simulation time 40360464743 ps
CPU time 20.28 seconds
Started Apr 28 02:17:27 PM PDT 24
Finished Apr 28 02:17:48 PM PDT 24
Peak memory 183012 kb
Host smart-028ebcf1-e448-4a39-ac53-6788836c0d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249397614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4249397614
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2583032889
Short name T217
Test name
Test status
Simulation time 125270960378 ps
CPU time 175.65 seconds
Started Apr 28 02:17:28 PM PDT 24
Finished Apr 28 02:20:24 PM PDT 24
Peak memory 191088 kb
Host smart-7c3b7b9b-40bf-4d13-b63f-bb8e19cc7136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583032889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2583032889
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2646686871
Short name T37
Test name
Test status
Simulation time 92121703440 ps
CPU time 181.93 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:20:25 PM PDT 24
Peak memory 205872 kb
Host smart-f37fbdcb-976a-4686-8136-5d5f9d3e7753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646686871 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2646686871
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3306965700
Short name T274
Test name
Test status
Simulation time 11264769004 ps
CPU time 18.39 seconds
Started Apr 28 02:16:40 PM PDT 24
Finished Apr 28 02:16:59 PM PDT 24
Peak memory 182972 kb
Host smart-aee9ff84-d1eb-494f-98ed-638481e5ab1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306965700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3306965700
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4187486604
Short name T383
Test name
Test status
Simulation time 33872700299 ps
CPU time 49.72 seconds
Started Apr 28 02:16:43 PM PDT 24
Finished Apr 28 02:17:33 PM PDT 24
Peak memory 183068 kb
Host smart-ab883122-0e6f-4081-ae66-cac60f455214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187486604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4187486604
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2578591146
Short name T413
Test name
Test status
Simulation time 373802971 ps
CPU time 0.75 seconds
Started Apr 28 02:16:40 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 182852 kb
Host smart-294be484-b92d-427c-8a20-ef80c2fc88cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578591146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2578591146
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1595527978
Short name T194
Test name
Test status
Simulation time 439972212897 ps
CPU time 1342.18 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:39:10 PM PDT 24
Peak memory 191260 kb
Host smart-3d17ede0-f53a-4e0a-aedb-9d95edd85306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595527978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1595527978
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1396395834
Short name T76
Test name
Test status
Simulation time 1844622102 ps
CPU time 1.09 seconds
Started Apr 28 02:17:23 PM PDT 24
Finished Apr 28 02:17:25 PM PDT 24
Peak memory 182852 kb
Host smart-92f0a2b6-f6ae-42d2-9307-18564852ccb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396395834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1396395834
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2219222461
Short name T106
Test name
Test status
Simulation time 166847885587 ps
CPU time 253.2 seconds
Started Apr 28 02:17:22 PM PDT 24
Finished Apr 28 02:21:36 PM PDT 24
Peak memory 191212 kb
Host smart-e7e20d06-2e0f-4f38-a8d9-626708288610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219222461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2219222461
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1504212854
Short name T207
Test name
Test status
Simulation time 304055710109 ps
CPU time 646.61 seconds
Started Apr 28 02:17:28 PM PDT 24
Finished Apr 28 02:28:15 PM PDT 24
Peak memory 191272 kb
Host smart-6021097b-46d1-4bf7-bf98-6683a9557d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504212854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1504212854
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.841791663
Short name T339
Test name
Test status
Simulation time 141542500386 ps
CPU time 129.4 seconds
Started Apr 28 02:17:25 PM PDT 24
Finished Apr 28 02:19:35 PM PDT 24
Peak memory 191260 kb
Host smart-f2ea5299-dfd4-4946-a588-3e50dfa913ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841791663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.841791663
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2483760860
Short name T445
Test name
Test status
Simulation time 36055100626 ps
CPU time 20.55 seconds
Started Apr 28 02:17:32 PM PDT 24
Finished Apr 28 02:17:53 PM PDT 24
Peak memory 182884 kb
Host smart-9868d0fd-6bcf-43bb-a448-d078f164c904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483760860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2483760860
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.598439718
Short name T337
Test name
Test status
Simulation time 165875311197 ps
CPU time 179 seconds
Started Apr 28 02:17:24 PM PDT 24
Finished Apr 28 02:20:24 PM PDT 24
Peak memory 193392 kb
Host smart-153a11a1-14d5-43a7-99ac-4f884de4ccae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598439718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.598439718
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2784363455
Short name T363
Test name
Test status
Simulation time 163231210225 ps
CPU time 183.53 seconds
Started Apr 28 02:17:21 PM PDT 24
Finished Apr 28 02:20:25 PM PDT 24
Peak memory 191268 kb
Host smart-cb692543-f91a-46e3-894d-ad272c251ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784363455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2784363455
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3021757831
Short name T438
Test name
Test status
Simulation time 1549353974386 ps
CPU time 936.33 seconds
Started Apr 28 02:16:45 PM PDT 24
Finished Apr 28 02:32:22 PM PDT 24
Peak memory 183088 kb
Host smart-de8aa43c-631d-4097-b9b6-0e46db1aec9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021757831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3021757831
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1784922690
Short name T384
Test name
Test status
Simulation time 49177794076 ps
CPU time 68.52 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:17:48 PM PDT 24
Peak memory 183052 kb
Host smart-ca150bc2-15ff-40e9-8212-f179c76971fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784922690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1784922690
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.901125075
Short name T343
Test name
Test status
Simulation time 287876065917 ps
CPU time 161.69 seconds
Started Apr 28 02:16:37 PM PDT 24
Finished Apr 28 02:19:20 PM PDT 24
Peak memory 191228 kb
Host smart-f39c370c-582a-4db9-804c-af2c25925317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901125075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.901125075
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1833983201
Short name T208
Test name
Test status
Simulation time 177506462167 ps
CPU time 102.46 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:18:22 PM PDT 24
Peak memory 182992 kb
Host smart-aa878054-82ee-458a-94d8-ebdb4277e3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833983201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1833983201
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2431526834
Short name T244
Test name
Test status
Simulation time 1974487998573 ps
CPU time 440.37 seconds
Started Apr 28 02:17:21 PM PDT 24
Finished Apr 28 02:24:42 PM PDT 24
Peak memory 191192 kb
Host smart-bf9868f7-fa5d-4401-8300-465c39ac41bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431526834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2431526834
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1368456688
Short name T276
Test name
Test status
Simulation time 20544154840 ps
CPU time 33.59 seconds
Started Apr 28 02:17:24 PM PDT 24
Finished Apr 28 02:17:58 PM PDT 24
Peak memory 183000 kb
Host smart-fd6bd0cc-c647-4596-b60b-824c97657016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368456688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1368456688
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2212581666
Short name T340
Test name
Test status
Simulation time 101281453978 ps
CPU time 1384.13 seconds
Started Apr 28 02:17:25 PM PDT 24
Finished Apr 28 02:40:29 PM PDT 24
Peak memory 191208 kb
Host smart-524736c7-add0-4e45-8c7e-d161f3cd7781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212581666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2212581666
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.828708712
Short name T79
Test name
Test status
Simulation time 496436146216 ps
CPU time 468.81 seconds
Started Apr 28 02:17:24 PM PDT 24
Finished Apr 28 02:25:14 PM PDT 24
Peak memory 191196 kb
Host smart-682fa956-d8f1-416b-92c0-ef0807c7eb1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828708712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.828708712
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.725475772
Short name T173
Test name
Test status
Simulation time 226114994378 ps
CPU time 180.45 seconds
Started Apr 28 02:17:31 PM PDT 24
Finished Apr 28 02:20:32 PM PDT 24
Peak memory 191212 kb
Host smart-f0d0ce68-9cc8-4909-bc43-228b9ee3d1f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725475772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.725475772
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2918843726
Short name T221
Test name
Test status
Simulation time 129186994962 ps
CPU time 103.77 seconds
Started Apr 28 02:17:27 PM PDT 24
Finished Apr 28 02:19:11 PM PDT 24
Peak memory 191248 kb
Host smart-5c76f306-b317-47e0-a0c8-1d9d75e14a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918843726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2918843726
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.391757153
Short name T177
Test name
Test status
Simulation time 130258415385 ps
CPU time 131.28 seconds
Started Apr 28 02:17:33 PM PDT 24
Finished Apr 28 02:19:45 PM PDT 24
Peak memory 191196 kb
Host smart-a3c429f7-3e89-4927-a3c9-693da507c30a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391757153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.391757153
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3347170070
Short name T273
Test name
Test status
Simulation time 309445373870 ps
CPU time 333.38 seconds
Started Apr 28 02:17:31 PM PDT 24
Finished Apr 28 02:23:05 PM PDT 24
Peak memory 191228 kb
Host smart-dfd8db7b-8727-41e1-867b-424582ba21aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347170070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3347170070
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3433022420
Short name T144
Test name
Test status
Simulation time 149979105477 ps
CPU time 149.51 seconds
Started Apr 28 02:17:34 PM PDT 24
Finished Apr 28 02:20:04 PM PDT 24
Peak memory 183080 kb
Host smart-c1326041-b23b-4a1d-bb7c-fc2434a4bd83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433022420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3433022420
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3945302427
Short name T335
Test name
Test status
Simulation time 241229573335 ps
CPU time 388.14 seconds
Started Apr 28 02:16:48 PM PDT 24
Finished Apr 28 02:23:17 PM PDT 24
Peak memory 183076 kb
Host smart-097d3882-7ce5-47fd-b28d-3fe56ccc1afd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945302427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3945302427
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2071956445
Short name T390
Test name
Test status
Simulation time 135244721389 ps
CPU time 225.64 seconds
Started Apr 28 02:16:45 PM PDT 24
Finished Apr 28 02:20:31 PM PDT 24
Peak memory 183008 kb
Host smart-58296118-3b27-44c9-9b44-fc0d6a517039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071956445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2071956445
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1984366691
Short name T319
Test name
Test status
Simulation time 56174742685 ps
CPU time 45.28 seconds
Started Apr 28 02:16:50 PM PDT 24
Finished Apr 28 02:17:36 PM PDT 24
Peak memory 191200 kb
Host smart-e2d0186a-a135-4b8d-9053-b4be95022af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984366691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1984366691
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1036980609
Short name T45
Test name
Test status
Simulation time 66598080 ps
CPU time 0.64 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:16:48 PM PDT 24
Peak memory 182860 kb
Host smart-87247813-e9b6-42af-8e22-5431d474b1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036980609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1036980609
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.980418442
Short name T69
Test name
Test status
Simulation time 2825570524829 ps
CPU time 1128.34 seconds
Started Apr 28 02:16:42 PM PDT 24
Finished Apr 28 02:35:31 PM PDT 24
Peak memory 196900 kb
Host smart-5ad4e8d0-b245-4542-951b-c5d123c4f7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980418442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.980418442
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.729290522
Short name T35
Test name
Test status
Simulation time 20078312906 ps
CPU time 166.49 seconds
Started Apr 28 02:16:44 PM PDT 24
Finished Apr 28 02:19:30 PM PDT 24
Peak memory 197664 kb
Host smart-ec1cd893-5f58-4ee8-8802-de0978293974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729290522 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.729290522
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3534954885
Short name T237
Test name
Test status
Simulation time 727187584371 ps
CPU time 215.01 seconds
Started Apr 28 02:17:31 PM PDT 24
Finished Apr 28 02:21:06 PM PDT 24
Peak memory 191244 kb
Host smart-d090286e-2372-4aba-8461-85688bba11e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534954885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3534954885
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3190747109
Short name T351
Test name
Test status
Simulation time 73383696848 ps
CPU time 152.33 seconds
Started Apr 28 02:17:29 PM PDT 24
Finished Apr 28 02:20:02 PM PDT 24
Peak memory 191252 kb
Host smart-1e6fefb1-d26d-49ed-9de0-643b008c2c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190747109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3190747109
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1782598987
Short name T103
Test name
Test status
Simulation time 89827791977 ps
CPU time 66.15 seconds
Started Apr 28 02:17:36 PM PDT 24
Finished Apr 28 02:18:42 PM PDT 24
Peak memory 182976 kb
Host smart-4c0a6a0b-55b0-45b3-9fb0-b5bd643a2e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782598987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1782598987
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3512929305
Short name T136
Test name
Test status
Simulation time 74364492594 ps
CPU time 390.1 seconds
Started Apr 28 02:17:31 PM PDT 24
Finished Apr 28 02:24:01 PM PDT 24
Peak memory 191252 kb
Host smart-86684767-b727-47e3-a492-383384e6605c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512929305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3512929305
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1488506405
Short name T61
Test name
Test status
Simulation time 287107822945 ps
CPU time 441.38 seconds
Started Apr 28 02:17:35 PM PDT 24
Finished Apr 28 02:24:57 PM PDT 24
Peak memory 194876 kb
Host smart-d3fff0d6-c002-4a17-96ba-c4b80fc5e263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488506405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1488506405
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2741139142
Short name T348
Test name
Test status
Simulation time 50593080550 ps
CPU time 84.06 seconds
Started Apr 28 02:17:35 PM PDT 24
Finished Apr 28 02:18:59 PM PDT 24
Peak memory 183060 kb
Host smart-79b8bff6-5d9a-4ec9-a357-764319c54acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741139142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2741139142
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3765662256
Short name T155
Test name
Test status
Simulation time 558088917031 ps
CPU time 358.38 seconds
Started Apr 28 02:17:35 PM PDT 24
Finished Apr 28 02:23:34 PM PDT 24
Peak memory 191224 kb
Host smart-33ee7dd9-9611-47e1-8fa4-623dd20fddae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765662256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3765662256
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2965846719
Short name T210
Test name
Test status
Simulation time 162693394627 ps
CPU time 271.43 seconds
Started Apr 28 02:17:34 PM PDT 24
Finished Apr 28 02:22:06 PM PDT 24
Peak memory 191244 kb
Host smart-d28b5dc2-8100-410b-a78b-1b9408a32165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965846719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2965846719
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.4167106396
Short name T167
Test name
Test status
Simulation time 246748102503 ps
CPU time 391.54 seconds
Started Apr 28 02:17:34 PM PDT 24
Finished Apr 28 02:24:06 PM PDT 24
Peak memory 191204 kb
Host smart-3004dff2-c830-4afb-a0a3-5874e62f3861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167106396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.4167106396
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3413798716
Short name T143
Test name
Test status
Simulation time 464723632400 ps
CPU time 750.9 seconds
Started Apr 28 02:16:44 PM PDT 24
Finished Apr 28 02:29:15 PM PDT 24
Peak memory 182960 kb
Host smart-eaed923c-9884-4574-8338-2619e52931b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413798716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3413798716
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1531505681
Short name T101
Test name
Test status
Simulation time 69276856155 ps
CPU time 59.9 seconds
Started Apr 28 02:16:46 PM PDT 24
Finished Apr 28 02:17:46 PM PDT 24
Peak memory 183056 kb
Host smart-be8ee344-be1d-401b-972b-e982c06978f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531505681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1531505681
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3493423830
Short name T305
Test name
Test status
Simulation time 249315152050 ps
CPU time 471.02 seconds
Started Apr 28 02:16:43 PM PDT 24
Finished Apr 28 02:24:34 PM PDT 24
Peak memory 191212 kb
Host smart-9c488109-b100-41ba-b6a9-00e5d2d95416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493423830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3493423830
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1435834781
Short name T72
Test name
Test status
Simulation time 70135747200 ps
CPU time 114.45 seconds
Started Apr 28 02:16:42 PM PDT 24
Finished Apr 28 02:18:36 PM PDT 24
Peak memory 191192 kb
Host smart-e83a096c-d504-4488-8576-c00fc1630395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435834781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1435834781
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.726376298
Short name T267
Test name
Test status
Simulation time 551128360907 ps
CPU time 510.89 seconds
Started Apr 28 02:16:44 PM PDT 24
Finished Apr 28 02:25:15 PM PDT 24
Peak memory 191268 kb
Host smart-40003e5e-52ec-496f-8f0e-df456c102148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726376298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.726376298
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.12056697
Short name T82
Test name
Test status
Simulation time 77643732116 ps
CPU time 718.82 seconds
Started Apr 28 02:16:44 PM PDT 24
Finished Apr 28 02:28:43 PM PDT 24
Peak memory 208336 kb
Host smart-a094c274-fb5e-45da-becd-335ee846dcbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12056697 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.12056697
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.3056629078
Short name T240
Test name
Test status
Simulation time 81231623939 ps
CPU time 315.66 seconds
Started Apr 28 02:17:34 PM PDT 24
Finished Apr 28 02:22:50 PM PDT 24
Peak memory 191212 kb
Host smart-a0b7b360-4f57-419f-b052-743af3ea6dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056629078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3056629078
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.991944320
Short name T354
Test name
Test status
Simulation time 8305606800 ps
CPU time 61.77 seconds
Started Apr 28 02:17:39 PM PDT 24
Finished Apr 28 02:18:41 PM PDT 24
Peak memory 183028 kb
Host smart-c56f3b24-0152-43cd-9b86-4da1c8fecd66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991944320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.991944320
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.585713599
Short name T325
Test name
Test status
Simulation time 8740928424 ps
CPU time 19.24 seconds
Started Apr 28 02:17:38 PM PDT 24
Finished Apr 28 02:17:58 PM PDT 24
Peak memory 183004 kb
Host smart-9ee87e43-7eca-4985-befa-aaab6728deef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585713599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.585713599
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.78378524
Short name T381
Test name
Test status
Simulation time 35201665971 ps
CPU time 54.99 seconds
Started Apr 28 02:17:40 PM PDT 24
Finished Apr 28 02:18:35 PM PDT 24
Peak memory 183012 kb
Host smart-102754d9-e3c4-4d21-8d04-baeac6257e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78378524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.78378524
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1629685752
Short name T366
Test name
Test status
Simulation time 28494429211 ps
CPU time 58.13 seconds
Started Apr 28 02:17:37 PM PDT 24
Finished Apr 28 02:18:36 PM PDT 24
Peak memory 183032 kb
Host smart-d884700d-a56b-43df-afaa-649b77bd034d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629685752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1629685752
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.452731338
Short name T149
Test name
Test status
Simulation time 63607057725 ps
CPU time 157.18 seconds
Started Apr 28 02:17:38 PM PDT 24
Finished Apr 28 02:20:15 PM PDT 24
Peak memory 191284 kb
Host smart-8be73da9-2400-4bac-b818-582a08d146cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452731338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.452731338
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3689346153
Short name T317
Test name
Test status
Simulation time 40574243335 ps
CPU time 17.65 seconds
Started Apr 28 02:16:42 PM PDT 24
Finished Apr 28 02:17:00 PM PDT 24
Peak memory 183056 kb
Host smart-ba97f826-f6c2-4bfe-a842-a92e2263b5ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689346153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3689346153
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3046979552
Short name T398
Test name
Test status
Simulation time 60140118729 ps
CPU time 82.95 seconds
Started Apr 28 02:16:44 PM PDT 24
Finished Apr 28 02:18:08 PM PDT 24
Peak memory 183072 kb
Host smart-9eaef16c-7074-4e5c-9b0a-40ea96bbe234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046979552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3046979552
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1561199355
Short name T420
Test name
Test status
Simulation time 21821659786 ps
CPU time 729.86 seconds
Started Apr 28 02:16:45 PM PDT 24
Finished Apr 28 02:28:55 PM PDT 24
Peak memory 182940 kb
Host smart-c027dfb3-9580-4abc-ac8c-03f9d918ee3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561199355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1561199355
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2726867965
Short name T9
Test name
Test status
Simulation time 46894859340 ps
CPU time 78.33 seconds
Started Apr 28 02:16:45 PM PDT 24
Finished Apr 28 02:18:03 PM PDT 24
Peak memory 183052 kb
Host smart-5569ee83-ec39-4d5b-b473-347fb6cb9f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726867965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2726867965
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2016155189
Short name T68
Test name
Test status
Simulation time 1209266919774 ps
CPU time 502.27 seconds
Started Apr 28 02:16:43 PM PDT 24
Finished Apr 28 02:25:06 PM PDT 24
Peak memory 195056 kb
Host smart-b9d65208-20ae-47c5-a51b-86896b0a5e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016155189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2016155189
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.869695500
Short name T196
Test name
Test status
Simulation time 84119810661 ps
CPU time 128.9 seconds
Started Apr 28 02:17:39 PM PDT 24
Finished Apr 28 02:19:48 PM PDT 24
Peak memory 191232 kb
Host smart-14ef3746-12c2-4cae-8f36-794445f79729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869695500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.869695500
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2150123393
Short name T230
Test name
Test status
Simulation time 921410936503 ps
CPU time 401.5 seconds
Started Apr 28 02:17:38 PM PDT 24
Finished Apr 28 02:24:21 PM PDT 24
Peak memory 191260 kb
Host smart-7deab545-13a1-4524-a64a-68cdb4ee2e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150123393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2150123393
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2775727460
Short name T233
Test name
Test status
Simulation time 227458231480 ps
CPU time 107.28 seconds
Started Apr 28 02:17:44 PM PDT 24
Finished Apr 28 02:19:31 PM PDT 24
Peak memory 183068 kb
Host smart-19e65955-df2f-4d01-9aec-8bbe1f7d8ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775727460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2775727460
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3744280925
Short name T268
Test name
Test status
Simulation time 205416693850 ps
CPU time 377.44 seconds
Started Apr 28 02:17:44 PM PDT 24
Finished Apr 28 02:24:02 PM PDT 24
Peak memory 191220 kb
Host smart-86ea2c17-3390-4bed-8409-a04d4ce9376e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744280925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3744280925
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3267574631
Short name T179
Test name
Test status
Simulation time 192841155184 ps
CPU time 423.86 seconds
Started Apr 28 02:17:45 PM PDT 24
Finished Apr 28 02:24:49 PM PDT 24
Peak memory 191212 kb
Host smart-2ff547b8-686c-4dd7-9e87-fbb83a1a010d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267574631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3267574631
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.22015
Short name T224
Test name
Test status
Simulation time 300110510321 ps
CPU time 869.67 seconds
Started Apr 28 02:17:44 PM PDT 24
Finished Apr 28 02:32:14 PM PDT 24
Peak memory 191244 kb
Host smart-736f0d2a-8c0c-4a9f-8b58-3cf6b614e3ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.22015
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3820977771
Short name T188
Test name
Test status
Simulation time 152707543840 ps
CPU time 389.22 seconds
Started Apr 28 02:17:45 PM PDT 24
Finished Apr 28 02:24:14 PM PDT 24
Peak memory 191240 kb
Host smart-a522557d-cb71-4ed3-b689-26246351eb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820977771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3820977771
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3909945495
Short name T171
Test name
Test status
Simulation time 149123057703 ps
CPU time 106.87 seconds
Started Apr 28 02:17:43 PM PDT 24
Finished Apr 28 02:19:30 PM PDT 24
Peak memory 191268 kb
Host smart-112f98eb-ef25-46a2-9e86-29c0394fa871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909945495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3909945495
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1206300350
Short name T184
Test name
Test status
Simulation time 188161422918 ps
CPU time 627.44 seconds
Started Apr 28 02:17:49 PM PDT 24
Finished Apr 28 02:28:17 PM PDT 24
Peak memory 191280 kb
Host smart-288d8403-d5b9-4f09-b1b1-0d93e68ccb68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206300350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1206300350
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1855848149
Short name T157
Test name
Test status
Simulation time 182368394978 ps
CPU time 377.5 seconds
Started Apr 28 02:17:50 PM PDT 24
Finished Apr 28 02:24:08 PM PDT 24
Peak memory 191256 kb
Host smart-d957f00a-48f3-4670-8fcd-bcdd47c72d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855848149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1855848149
Directory /workspace/99.rv_timer_random/latest
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