Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 584
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T510 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1949735503 Apr 30 03:07:30 PM PDT 24 Apr 30 03:07:32 PM PDT 24 13480612 ps
T511 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3955243622 Apr 30 03:07:46 PM PDT 24 Apr 30 03:07:47 PM PDT 24 50677660 ps
T512 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2374282751 Apr 30 03:07:30 PM PDT 24 Apr 30 03:07:31 PM PDT 24 57603706 ps
T513 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3203468773 Apr 30 03:07:43 PM PDT 24 Apr 30 03:07:45 PM PDT 24 18983437 ps
T514 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1920069004 Apr 30 03:07:30 PM PDT 24 Apr 30 03:07:33 PM PDT 24 125064941 ps
T515 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1370862447 Apr 30 03:07:17 PM PDT 24 Apr 30 03:07:18 PM PDT 24 98430301 ps
T80 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1084991435 Apr 30 03:07:17 PM PDT 24 Apr 30 03:07:20 PM PDT 24 235318670 ps
T79 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1391512150 Apr 30 03:07:25 PM PDT 24 Apr 30 03:07:27 PM PDT 24 76950279 ps
T516 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.297854177 Apr 30 03:07:37 PM PDT 24 Apr 30 03:07:38 PM PDT 24 19543249 ps
T517 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3222333749 Apr 30 03:07:27 PM PDT 24 Apr 30 03:07:28 PM PDT 24 17044247 ps
T518 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2652340058 Apr 30 03:07:44 PM PDT 24 Apr 30 03:07:45 PM PDT 24 17381795 ps
T519 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3719951227 Apr 30 03:07:38 PM PDT 24 Apr 30 03:07:39 PM PDT 24 12037957 ps
T520 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2869656294 Apr 30 03:07:11 PM PDT 24 Apr 30 03:07:15 PM PDT 24 829933855 ps
T521 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.639744772 Apr 30 03:07:45 PM PDT 24 Apr 30 03:07:47 PM PDT 24 41293383 ps
T522 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3631846300 Apr 30 03:07:37 PM PDT 24 Apr 30 03:07:39 PM PDT 24 45636149 ps
T523 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1242678431 Apr 30 03:07:36 PM PDT 24 Apr 30 03:07:37 PM PDT 24 15956973 ps
T524 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2533454593 Apr 30 03:07:25 PM PDT 24 Apr 30 03:07:27 PM PDT 24 366697314 ps
T525 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.726285394 Apr 30 03:07:41 PM PDT 24 Apr 30 03:07:43 PM PDT 24 59623072 ps
T90 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.785331385 Apr 30 03:07:08 PM PDT 24 Apr 30 03:07:09 PM PDT 24 35004255 ps
T92 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1867139068 Apr 30 03:07:32 PM PDT 24 Apr 30 03:07:33 PM PDT 24 18099693 ps
T526 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1367412838 Apr 30 03:07:17 PM PDT 24 Apr 30 03:07:18 PM PDT 24 25604673 ps
T527 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.275098943 Apr 30 03:07:25 PM PDT 24 Apr 30 03:07:26 PM PDT 24 19437625 ps
T528 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1653746829 Apr 30 03:07:17 PM PDT 24 Apr 30 03:07:20 PM PDT 24 83747321 ps
T529 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.109581080 Apr 30 03:07:46 PM PDT 24 Apr 30 03:07:48 PM PDT 24 39880542 ps
T530 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2842544729 Apr 30 03:07:38 PM PDT 24 Apr 30 03:07:39 PM PDT 24 16405643 ps
T531 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.147065229 Apr 30 03:07:27 PM PDT 24 Apr 30 03:07:28 PM PDT 24 482722644 ps
T91 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4071055750 Apr 30 03:07:30 PM PDT 24 Apr 30 03:07:32 PM PDT 24 19748223 ps
T532 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1092894452 Apr 30 03:07:10 PM PDT 24 Apr 30 03:07:12 PM PDT 24 28655529 ps
T533 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2991798027 Apr 30 03:07:37 PM PDT 24 Apr 30 03:07:39 PM PDT 24 86289343 ps
T534 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2101317704 Apr 30 03:07:27 PM PDT 24 Apr 30 03:07:30 PM PDT 24 174810333 ps
T535 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.233647176 Apr 30 03:07:16 PM PDT 24 Apr 30 03:07:17 PM PDT 24 24019969 ps
T536 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3632461759 Apr 30 03:07:26 PM PDT 24 Apr 30 03:07:27 PM PDT 24 31123549 ps
T537 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.690154928 Apr 30 03:07:31 PM PDT 24 Apr 30 03:07:33 PM PDT 24 92061324 ps
T538 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2222082684 Apr 30 03:07:28 PM PDT 24 Apr 30 03:07:30 PM PDT 24 115180807 ps
T539 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1469539853 Apr 30 03:07:38 PM PDT 24 Apr 30 03:07:40 PM PDT 24 39103676 ps
T104 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1521704278 Apr 30 03:07:28 PM PDT 24 Apr 30 03:07:30 PM PDT 24 151093899 ps
T540 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.516982763 Apr 30 03:07:23 PM PDT 24 Apr 30 03:07:26 PM PDT 24 883750280 ps
T541 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1479942101 Apr 30 03:07:36 PM PDT 24 Apr 30 03:07:38 PM PDT 24 13271676 ps
T542 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.833686752 Apr 30 03:07:27 PM PDT 24 Apr 30 03:07:29 PM PDT 24 55105804 ps
T543 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.176105755 Apr 30 03:07:30 PM PDT 24 Apr 30 03:07:34 PM PDT 24 155012294 ps
T544 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2463206538 Apr 30 03:07:26 PM PDT 24 Apr 30 03:07:28 PM PDT 24 242549936 ps
T103 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1185948494 Apr 30 03:07:30 PM PDT 24 Apr 30 03:07:32 PM PDT 24 438635001 ps
T545 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2536756243 Apr 30 03:07:34 PM PDT 24 Apr 30 03:07:36 PM PDT 24 2073723363 ps
T546 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3582057263 Apr 30 03:07:37 PM PDT 24 Apr 30 03:07:39 PM PDT 24 24042512 ps
T547 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.918973954 Apr 30 03:07:29 PM PDT 24 Apr 30 03:07:31 PM PDT 24 190767065 ps
T548 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1892855720 Apr 30 03:07:29 PM PDT 24 Apr 30 03:07:30 PM PDT 24 63003509 ps
T549 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3537807141 Apr 30 03:07:31 PM PDT 24 Apr 30 03:07:33 PM PDT 24 34756739 ps
T550 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1244385540 Apr 30 03:07:29 PM PDT 24 Apr 30 03:07:31 PM PDT 24 181655393 ps
T551 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1037258112 Apr 30 03:07:38 PM PDT 24 Apr 30 03:07:40 PM PDT 24 12714422 ps
T552 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1853322502 Apr 30 03:07:10 PM PDT 24 Apr 30 03:07:13 PM PDT 24 792637353 ps
T553 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1905685219 Apr 30 03:07:09 PM PDT 24 Apr 30 03:07:10 PM PDT 24 17510939 ps
T554 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3647015193 Apr 30 03:07:38 PM PDT 24 Apr 30 03:07:40 PM PDT 24 17452347 ps
T555 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1841992570 Apr 30 03:07:09 PM PDT 24 Apr 30 03:07:10 PM PDT 24 24929656 ps
T556 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1998441629 Apr 30 03:07:29 PM PDT 24 Apr 30 03:07:32 PM PDT 24 378991163 ps
T557 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3927505773 Apr 30 03:07:25 PM PDT 24 Apr 30 03:07:27 PM PDT 24 12897459 ps
T105 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1572539130 Apr 30 03:07:43 PM PDT 24 Apr 30 03:07:44 PM PDT 24 79983923 ps
T558 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2293211446 Apr 30 03:07:43 PM PDT 24 Apr 30 03:07:44 PM PDT 24 55418310 ps
T559 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2224711703 Apr 30 03:07:32 PM PDT 24 Apr 30 03:07:33 PM PDT 24 36274260 ps
T93 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3074449352 Apr 30 03:07:23 PM PDT 24 Apr 30 03:07:24 PM PDT 24 19075160 ps
T560 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.783883168 Apr 30 03:07:27 PM PDT 24 Apr 30 03:07:28 PM PDT 24 23020069 ps
T561 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3813162479 Apr 30 03:07:28 PM PDT 24 Apr 30 03:07:30 PM PDT 24 147312254 ps
T562 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2123851623 Apr 30 03:07:37 PM PDT 24 Apr 30 03:07:39 PM PDT 24 38084510 ps
T563 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1244807406 Apr 30 03:07:45 PM PDT 24 Apr 30 03:07:46 PM PDT 24 51581556 ps
T564 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1374439842 Apr 30 03:07:26 PM PDT 24 Apr 30 03:07:28 PM PDT 24 12384947 ps
T565 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2628002869 Apr 30 03:07:09 PM PDT 24 Apr 30 03:07:12 PM PDT 24 294547038 ps
T566 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2090013185 Apr 30 03:07:45 PM PDT 24 Apr 30 03:07:47 PM PDT 24 24525389 ps
T567 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2158607685 Apr 30 03:07:30 PM PDT 24 Apr 30 03:07:32 PM PDT 24 19687485 ps
T568 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.699383562 Apr 30 03:07:24 PM PDT 24 Apr 30 03:07:26 PM PDT 24 61688136 ps
T569 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.787885319 Apr 30 03:07:36 PM PDT 24 Apr 30 03:07:38 PM PDT 24 15658993 ps
T570 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1389265161 Apr 30 03:07:22 PM PDT 24 Apr 30 03:07:24 PM PDT 24 231793456 ps
T571 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.4217153693 Apr 30 03:07:12 PM PDT 24 Apr 30 03:07:15 PM PDT 24 2296125765 ps
T572 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1960644930 Apr 30 03:07:27 PM PDT 24 Apr 30 03:07:28 PM PDT 24 15538859 ps
T573 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.809161392 Apr 30 03:07:44 PM PDT 24 Apr 30 03:07:45 PM PDT 24 171767194 ps
T574 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1638093881 Apr 30 03:07:29 PM PDT 24 Apr 30 03:07:30 PM PDT 24 20582815 ps
T575 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2517816824 Apr 30 03:07:38 PM PDT 24 Apr 30 03:07:40 PM PDT 24 41698670 ps
T576 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1969754395 Apr 30 03:07:24 PM PDT 24 Apr 30 03:07:25 PM PDT 24 22929558 ps
T577 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1747543595 Apr 30 03:07:45 PM PDT 24 Apr 30 03:07:46 PM PDT 24 11314067 ps
T578 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.570257507 Apr 30 03:07:38 PM PDT 24 Apr 30 03:07:40 PM PDT 24 68691193 ps
T579 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3674217197 Apr 30 03:07:39 PM PDT 24 Apr 30 03:07:41 PM PDT 24 33084786 ps
T580 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.227792006 Apr 30 03:07:36 PM PDT 24 Apr 30 03:07:38 PM PDT 24 93342939 ps
T581 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2120093012 Apr 30 03:07:23 PM PDT 24 Apr 30 03:07:24 PM PDT 24 12013683 ps
T582 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3998059211 Apr 30 03:07:45 PM PDT 24 Apr 30 03:07:47 PM PDT 24 17785757 ps
T583 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2187611925 Apr 30 03:07:11 PM PDT 24 Apr 30 03:07:12 PM PDT 24 13374747 ps
T584 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4035840205 Apr 30 03:07:26 PM PDT 24 Apr 30 03:07:28 PM PDT 24 158767094 ps

Test location /workspace/coverage/default/89.rv_timer_random.113252210
Short name T9
Test name
Test status
Simulation time 280651772524 ps
CPU time 951.13 seconds
Started Apr 30 03:09:43 PM PDT 24
Finished Apr 30 03:25:34 PM PDT 24
Peak memory 191184 kb
Host smart-09c1f1f2-9001-490c-b7cb-77673fcdcdeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113252210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.113252210
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.82484565
Short name T12
Test name
Test status
Simulation time 75559017247 ps
CPU time 546.81 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:17:34 PM PDT 24
Peak memory 205864 kb
Host smart-081a24f3-0e55-417d-8daa-5a02f63b91b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82484565 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.82484565
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2092643135
Short name T62
Test name
Test status
Simulation time 560823231082 ps
CPU time 1487.39 seconds
Started Apr 30 03:07:59 PM PDT 24
Finished Apr 30 03:32:47 PM PDT 24
Peak memory 193788 kb
Host smart-5d306019-8c82-41bd-919e-2a72a6814607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092643135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2092643135
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1877722736
Short name T18
Test name
Test status
Simulation time 40679276 ps
CPU time 0.75 seconds
Started Apr 30 03:07:46 PM PDT 24
Finished Apr 30 03:07:48 PM PDT 24
Peak memory 213416 kb
Host smart-62626324-034c-42ad-882f-e70e116219a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877722736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1877722736
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2671030555
Short name T119
Test name
Test status
Simulation time 2796484814809 ps
CPU time 3004.9 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:58:18 PM PDT 24
Peak memory 191172 kb
Host smart-c1daf90f-ee21-4fb3-b862-ecf98606950d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671030555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2671030555
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.314981912
Short name T178
Test name
Test status
Simulation time 598596529627 ps
CPU time 1722.25 seconds
Started Apr 30 03:07:44 PM PDT 24
Finished Apr 30 03:36:27 PM PDT 24
Peak memory 195912 kb
Host smart-793482f1-a07e-43d4-af17-7eafd6dba379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314981912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.314981912
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3236008601
Short name T116
Test name
Test status
Simulation time 405134942533 ps
CPU time 1519.6 seconds
Started Apr 30 03:08:05 PM PDT 24
Finished Apr 30 03:33:25 PM PDT 24
Peak memory 191208 kb
Host smart-ea92c933-68ee-459e-b6bc-c3caa2025efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236008601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3236008601
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1903311947
Short name T153
Test name
Test status
Simulation time 966899999026 ps
CPU time 1079.53 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:26:26 PM PDT 24
Peak memory 191304 kb
Host smart-0ba56fd3-03b8-4205-ace4-f76ca5f93741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903311947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1903311947
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.254405816
Short name T33
Test name
Test status
Simulation time 1390278937 ps
CPU time 2.56 seconds
Started Apr 30 03:07:17 PM PDT 24
Finished Apr 30 03:07:20 PM PDT 24
Peak memory 191064 kb
Host smart-ef381b7c-7a38-490f-91f3-1b2e05762b9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254405816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.254405816
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.4065241124
Short name T237
Test name
Test status
Simulation time 2162625066479 ps
CPU time 1724.26 seconds
Started Apr 30 03:07:57 PM PDT 24
Finished Apr 30 03:36:43 PM PDT 24
Peak memory 191184 kb
Host smart-120a34b7-21f2-420c-a201-6ab2d4f51686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065241124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
4065241124
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.303382053
Short name T340
Test name
Test status
Simulation time 1585598385117 ps
CPU time 2028.55 seconds
Started Apr 30 03:08:48 PM PDT 24
Finished Apr 30 03:42:37 PM PDT 24
Peak memory 191216 kb
Host smart-d8ad24b6-7251-42a5-a540-a31761cc1ea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303382053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
303382053
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2428105745
Short name T102
Test name
Test status
Simulation time 121938459 ps
CPU time 1.37 seconds
Started Apr 30 03:07:09 PM PDT 24
Finished Apr 30 03:07:10 PM PDT 24
Peak memory 195632 kb
Host smart-e2950026-955b-4180-b67d-94703fdf0241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428105745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2428105745
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1145719234
Short name T265
Test name
Test status
Simulation time 564042192519 ps
CPU time 1108.74 seconds
Started Apr 30 03:08:24 PM PDT 24
Finished Apr 30 03:26:53 PM PDT 24
Peak memory 191312 kb
Host smart-6c3afd54-a328-43c5-9063-f3f90dd3942e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145719234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1145719234
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1163287258
Short name T164
Test name
Test status
Simulation time 487768651873 ps
CPU time 1191.49 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:28:13 PM PDT 24
Peak memory 191296 kb
Host smart-8677cfde-31d1-416b-830a-02f0b45a4e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163287258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1163287258
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/154.rv_timer_random.3937678000
Short name T181
Test name
Test status
Simulation time 106451065880 ps
CPU time 1415.79 seconds
Started Apr 30 03:10:28 PM PDT 24
Finished Apr 30 03:34:05 PM PDT 24
Peak memory 191268 kb
Host smart-9c318a7b-4a57-489e-9207-784c8e632652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937678000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3937678000
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2740594153
Short name T112
Test name
Test status
Simulation time 116676952401 ps
CPU time 359.5 seconds
Started Apr 30 03:09:51 PM PDT 24
Finished Apr 30 03:15:51 PM PDT 24
Peak memory 183040 kb
Host smart-9742ee75-e446-4c8a-903f-8e6e05eebf3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740594153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2740594153
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1602840691
Short name T302
Test name
Test status
Simulation time 4266710038901 ps
CPU time 2341.83 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:47:07 PM PDT 24
Peak memory 191232 kb
Host smart-f83e9672-661c-4e4a-a4bb-c08f088e541b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602840691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1602840691
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2437185306
Short name T217
Test name
Test status
Simulation time 188152637955 ps
CPU time 324.89 seconds
Started Apr 30 03:08:21 PM PDT 24
Finished Apr 30 03:13:47 PM PDT 24
Peak memory 194624 kb
Host smart-69281a3a-3080-4ba6-b634-d733478f09fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437185306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2437185306
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3841446449
Short name T109
Test name
Test status
Simulation time 472025788915 ps
CPU time 1374.02 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:31:05 PM PDT 24
Peak memory 191184 kb
Host smart-b03dcebf-6d8c-4151-ab6e-4456da3bc386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841446449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3841446449
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2132755781
Short name T24
Test name
Test status
Simulation time 695657279601 ps
CPU time 2049.09 seconds
Started Apr 30 03:07:47 PM PDT 24
Finished Apr 30 03:41:57 PM PDT 24
Peak memory 191200 kb
Host smart-490b5dae-c3eb-4b04-84e1-b2b75e08e942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132755781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2132755781
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.4059585954
Short name T189
Test name
Test status
Simulation time 425677611582 ps
CPU time 1129.75 seconds
Started Apr 30 03:08:24 PM PDT 24
Finished Apr 30 03:27:14 PM PDT 24
Peak memory 191312 kb
Host smart-9f04c151-00c8-4715-824b-a44cbbf973a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059585954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.4059585954
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1894948976
Short name T158
Test name
Test status
Simulation time 1464973560416 ps
CPU time 1037.5 seconds
Started Apr 30 03:08:54 PM PDT 24
Finished Apr 30 03:26:12 PM PDT 24
Peak memory 191252 kb
Host smart-99697af5-f276-4677-8c30-da49c35b96e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894948976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1894948976
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.3596056746
Short name T44
Test name
Test status
Simulation time 311594448679 ps
CPU time 327.42 seconds
Started Apr 30 03:10:02 PM PDT 24
Finished Apr 30 03:15:30 PM PDT 24
Peak memory 191260 kb
Host smart-0af4fdb8-cb3f-4123-9ce4-b2454f2e37c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596056746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3596056746
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.646796106
Short name T140
Test name
Test status
Simulation time 2206942051906 ps
CPU time 1152.33 seconds
Started Apr 30 03:08:29 PM PDT 24
Finished Apr 30 03:27:42 PM PDT 24
Peak memory 191224 kb
Host smart-dc5940f2-cd5c-4f08-9848-d6a3728339ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646796106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
646796106
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3992908087
Short name T188
Test name
Test status
Simulation time 355656545226 ps
CPU time 1159.87 seconds
Started Apr 30 03:08:34 PM PDT 24
Finished Apr 30 03:27:54 PM PDT 24
Peak memory 191240 kb
Host smart-a4988309-8e7d-43f1-945f-88467d6e9c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992908087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3992908087
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.736515804
Short name T180
Test name
Test status
Simulation time 313544496490 ps
CPU time 269.41 seconds
Started Apr 30 03:09:57 PM PDT 24
Finished Apr 30 03:14:27 PM PDT 24
Peak memory 191268 kb
Host smart-6e227828-5947-49f5-9d95-112f9ce8c6ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736515804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.736515804
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.624559730
Short name T328
Test name
Test status
Simulation time 116856847674 ps
CPU time 432.09 seconds
Started Apr 30 03:10:38 PM PDT 24
Finished Apr 30 03:17:51 PM PDT 24
Peak memory 191256 kb
Host smart-50d97ee7-5693-49ba-b190-7848fb712c06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624559730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.624559730
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2612433458
Short name T36
Test name
Test status
Simulation time 1423776591860 ps
CPU time 1144.71 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:27:16 PM PDT 24
Peak memory 196020 kb
Host smart-4310f01f-5f41-427a-ad17-466557d8e478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612433458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2612433458
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3121714389
Short name T205
Test name
Test status
Simulation time 1695102023065 ps
CPU time 1572.8 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:34:31 PM PDT 24
Peak memory 196200 kb
Host smart-62c79daf-9218-420f-99bc-6210c02795fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121714389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3121714389
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1292660730
Short name T154
Test name
Test status
Simulation time 430477152244 ps
CPU time 1290.59 seconds
Started Apr 30 03:09:14 PM PDT 24
Finished Apr 30 03:30:45 PM PDT 24
Peak memory 191192 kb
Host smart-dd46be5b-e8a9-47da-bd3a-35d2b343bcc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292660730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1292660730
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.3040800042
Short name T47
Test name
Test status
Simulation time 384552148230 ps
CPU time 153.17 seconds
Started Apr 30 03:10:36 PM PDT 24
Finished Apr 30 03:13:10 PM PDT 24
Peak memory 191252 kb
Host smart-ce10e22a-babf-4502-a4d3-746b25be45f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040800042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3040800042
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1307713729
Short name T212
Test name
Test status
Simulation time 561476840458 ps
CPU time 270.28 seconds
Started Apr 30 03:09:21 PM PDT 24
Finished Apr 30 03:13:51 PM PDT 24
Peak memory 191156 kb
Host smart-c0a2f845-5abf-4ff8-ba00-6bf9cca83dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307713729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1307713729
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4113253844
Short name T108
Test name
Test status
Simulation time 839547858806 ps
CPU time 515.15 seconds
Started Apr 30 03:09:36 PM PDT 24
Finished Apr 30 03:18:11 PM PDT 24
Peak memory 191268 kb
Host smart-4f9b2b35-3b89-427a-b621-14151c0c97aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113253844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4113253844
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1013401522
Short name T106
Test name
Test status
Simulation time 108078633055 ps
CPU time 109.07 seconds
Started Apr 30 03:07:42 PM PDT 24
Finished Apr 30 03:09:32 PM PDT 24
Peak memory 194076 kb
Host smart-2ea96ce3-784b-499b-995e-21b529ae833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013401522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1013401522
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.681087493
Short name T251
Test name
Test status
Simulation time 601584057089 ps
CPU time 624.7 seconds
Started Apr 30 03:08:05 PM PDT 24
Finished Apr 30 03:18:30 PM PDT 24
Peak memory 191276 kb
Host smart-256a8f9e-fd19-49ab-aecf-5123c75a43fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681087493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
681087493
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/153.rv_timer_random.1037683468
Short name T223
Test name
Test status
Simulation time 185580383944 ps
CPU time 737.7 seconds
Started Apr 30 03:10:18 PM PDT 24
Finished Apr 30 03:22:37 PM PDT 24
Peak memory 191276 kb
Host smart-ccbf7736-fe9c-4e9e-b778-9a0b63da4e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037683468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1037683468
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1892372356
Short name T25
Test name
Test status
Simulation time 235426974562 ps
CPU time 314.38 seconds
Started Apr 30 03:09:19 PM PDT 24
Finished Apr 30 03:14:34 PM PDT 24
Peak memory 191268 kb
Host smart-6b90b37e-fb17-4cb1-8082-4a10ae9c9545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892372356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1892372356
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1082362649
Short name T273
Test name
Test status
Simulation time 484237709041 ps
CPU time 248.57 seconds
Started Apr 30 03:07:56 PM PDT 24
Finished Apr 30 03:12:06 PM PDT 24
Peak memory 195544 kb
Host smart-6a17b0ff-7c06-42bd-991e-f1b0e73ee9ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082362649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1082362649
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.228901765
Short name T308
Test name
Test status
Simulation time 325242860824 ps
CPU time 347.16 seconds
Started Apr 30 03:10:18 PM PDT 24
Finished Apr 30 03:16:06 PM PDT 24
Peak memory 191228 kb
Host smart-28f04769-e207-434a-a801-87743aefc341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228901765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.228901765
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3733107339
Short name T157
Test name
Test status
Simulation time 128496695880 ps
CPU time 503.54 seconds
Started Apr 30 03:10:26 PM PDT 24
Finished Apr 30 03:18:51 PM PDT 24
Peak memory 191284 kb
Host smart-846301bd-171c-468e-9588-175bdcb3fc79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733107339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3733107339
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2920997903
Short name T169
Test name
Test status
Simulation time 266839615542 ps
CPU time 116.91 seconds
Started Apr 30 03:10:38 PM PDT 24
Finished Apr 30 03:12:35 PM PDT 24
Peak memory 191260 kb
Host smart-5d316792-3a24-42a5-a04a-4f449921ba1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920997903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2920997903
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.302092787
Short name T131
Test name
Test status
Simulation time 96004745440 ps
CPU time 161.28 seconds
Started Apr 30 03:08:10 PM PDT 24
Finished Apr 30 03:10:52 PM PDT 24
Peak memory 191196 kb
Host smart-24e83477-9393-4d1e-8f13-957edde67827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302092787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.302092787
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3542930853
Short name T283
Test name
Test status
Simulation time 69061793720 ps
CPU time 349.49 seconds
Started Apr 30 03:10:49 PM PDT 24
Finished Apr 30 03:16:40 PM PDT 24
Peak memory 191248 kb
Host smart-b773c621-fb75-4a43-ba51-0a2c5394bc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542930853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3542930853
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.546369498
Short name T85
Test name
Test status
Simulation time 60176969183 ps
CPU time 111.31 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:10:05 PM PDT 24
Peak memory 183024 kb
Host smart-1a566508-d598-43f1-b514-104d29a0290e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546369498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.546369498
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_random.310835639
Short name T242
Test name
Test status
Simulation time 319863224270 ps
CPU time 493.35 seconds
Started Apr 30 03:09:14 PM PDT 24
Finished Apr 30 03:17:28 PM PDT 24
Peak memory 194548 kb
Host smart-7b2eca79-fa32-487a-ae2b-faff16c334f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310835639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.310835639
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2074332839
Short name T319
Test name
Test status
Simulation time 4049726011418 ps
CPU time 989.02 seconds
Started Apr 30 03:07:46 PM PDT 24
Finished Apr 30 03:24:16 PM PDT 24
Peak memory 191300 kb
Host smart-b1258592-c63b-4d83-9a42-2de9cc408c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074332839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2074332839
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random.1445265662
Short name T425
Test name
Test status
Simulation time 200967865155 ps
CPU time 161.51 seconds
Started Apr 30 03:08:00 PM PDT 24
Finished Apr 30 03:10:42 PM PDT 24
Peak memory 191228 kb
Host smart-3e2048a3-be9f-4677-9015-6cffbfefcc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445265662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1445265662
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3243754100
Short name T225
Test name
Test status
Simulation time 479284605182 ps
CPU time 346.66 seconds
Started Apr 30 03:09:50 PM PDT 24
Finished Apr 30 03:15:37 PM PDT 24
Peak memory 191228 kb
Host smart-2726b3a2-4127-4ac8-95f5-5426b8580b90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243754100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3243754100
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1270708004
Short name T142
Test name
Test status
Simulation time 120558319073 ps
CPU time 342.58 seconds
Started Apr 30 03:10:02 PM PDT 24
Finished Apr 30 03:15:45 PM PDT 24
Peak memory 191252 kb
Host smart-949c8b9a-f7bd-48bd-93ba-1356bb1ee7d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270708004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1270708004
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.572092158
Short name T218
Test name
Test status
Simulation time 249131858678 ps
CPU time 157.87 seconds
Started Apr 30 03:10:02 PM PDT 24
Finished Apr 30 03:12:41 PM PDT 24
Peak memory 191252 kb
Host smart-50e8d22d-2f13-4389-85b8-7b60f9f3b629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572092158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.572092158
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1023357388
Short name T239
Test name
Test status
Simulation time 275207861949 ps
CPU time 247.39 seconds
Started Apr 30 03:10:02 PM PDT 24
Finished Apr 30 03:14:10 PM PDT 24
Peak memory 191220 kb
Host smart-58e0c515-f371-4a8d-b630-95f9a8b89c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023357388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1023357388
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2885717155
Short name T282
Test name
Test status
Simulation time 780095193133 ps
CPU time 618.24 seconds
Started Apr 30 03:10:44 PM PDT 24
Finished Apr 30 03:21:03 PM PDT 24
Peak memory 191288 kb
Host smart-132678da-85e1-47fa-b265-081c9399a2a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885717155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2885717155
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1830091300
Short name T346
Test name
Test status
Simulation time 163412066536 ps
CPU time 152 seconds
Started Apr 30 03:10:46 PM PDT 24
Finished Apr 30 03:13:18 PM PDT 24
Peak memory 191244 kb
Host smart-5cb8e674-9b17-4413-a3e0-ff93d3043898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830091300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1830091300
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2989082080
Short name T209
Test name
Test status
Simulation time 739952900122 ps
CPU time 865.02 seconds
Started Apr 30 03:09:20 PM PDT 24
Finished Apr 30 03:23:45 PM PDT 24
Peak memory 194712 kb
Host smart-c1500924-09df-4061-8ba1-20b509416522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989082080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2989082080
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2324529921
Short name T96
Test name
Test status
Simulation time 43121350 ps
CPU time 0.6 seconds
Started Apr 30 03:07:12 PM PDT 24
Finished Apr 30 03:07:13 PM PDT 24
Peak memory 182752 kb
Host smart-eef7cc38-f462-455c-b5de-35dd0a43a7c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324529921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2324529921
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/115.rv_timer_random.1372584775
Short name T256
Test name
Test status
Simulation time 162466814563 ps
CPU time 454.99 seconds
Started Apr 30 03:09:56 PM PDT 24
Finished Apr 30 03:17:32 PM PDT 24
Peak memory 191184 kb
Host smart-8eef5dc7-da84-45b9-8681-dd2514827b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372584775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1372584775
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2307747296
Short name T126
Test name
Test status
Simulation time 286402240895 ps
CPU time 404.84 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:14:50 PM PDT 24
Peak memory 191212 kb
Host smart-11b2da8a-ce34-4531-a05c-2437b34c51f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307747296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2307747296
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.168772273
Short name T233
Test name
Test status
Simulation time 357817284921 ps
CPU time 260.63 seconds
Started Apr 30 03:10:04 PM PDT 24
Finished Apr 30 03:14:26 PM PDT 24
Peak memory 191248 kb
Host smart-8904ed8f-3a15-4738-bb3e-6e37f4fe9b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168772273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.168772273
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3746451766
Short name T280
Test name
Test status
Simulation time 442757047513 ps
CPU time 745.47 seconds
Started Apr 30 03:10:11 PM PDT 24
Finished Apr 30 03:22:37 PM PDT 24
Peak memory 191236 kb
Host smart-9b7a0637-b78d-49ce-9191-ad091f75a9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746451766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3746451766
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3003447674
Short name T129
Test name
Test status
Simulation time 112332779425 ps
CPU time 399.1 seconds
Started Apr 30 03:10:31 PM PDT 24
Finished Apr 30 03:17:11 PM PDT 24
Peak memory 194816 kb
Host smart-9cc5af04-5ad2-48a4-a7b4-402e1d3711b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003447674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3003447674
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.350542824
Short name T135
Test name
Test status
Simulation time 387737438426 ps
CPU time 95.22 seconds
Started Apr 30 03:10:37 PM PDT 24
Finished Apr 30 03:12:13 PM PDT 24
Peak memory 191248 kb
Host smart-d2a9bf34-f21e-4392-8708-9fa438b7eee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350542824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.350542824
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.2316763926
Short name T243
Test name
Test status
Simulation time 176601256987 ps
CPU time 103.33 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:09:57 PM PDT 24
Peak memory 191272 kb
Host smart-da899791-e38e-422a-8f5e-80734a0206b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316763926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2316763926
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3863583915
Short name T146
Test name
Test status
Simulation time 82291488924 ps
CPU time 127.62 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:10:20 PM PDT 24
Peak memory 191248 kb
Host smart-6ebf2678-d905-4da7-91d3-49ad78532ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863583915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3863583915
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/199.rv_timer_random.3090478652
Short name T229
Test name
Test status
Simulation time 87311079055 ps
CPU time 162.69 seconds
Started Apr 30 03:10:47 PM PDT 24
Finished Apr 30 03:13:30 PM PDT 24
Peak memory 191284 kb
Host smart-27ccc246-c8bd-4347-a970-2490f549a8ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090478652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3090478652
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.899808967
Short name T143
Test name
Test status
Simulation time 47607799718 ps
CPU time 146.78 seconds
Started Apr 30 03:08:15 PM PDT 24
Finished Apr 30 03:10:42 PM PDT 24
Peak memory 191224 kb
Host smart-8a09701c-29a9-4a75-bbc2-a6d1a3320af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899808967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.899808967
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3545266540
Short name T48
Test name
Test status
Simulation time 1704739347454 ps
CPU time 834.41 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:22:08 PM PDT 24
Peak memory 191308 kb
Host smart-f3924400-9c6c-4117-924d-6e4fefd24241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545266540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3545266540
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1781667640
Short name T118
Test name
Test status
Simulation time 398595834681 ps
CPU time 681.51 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:19:34 PM PDT 24
Peak memory 183056 kb
Host smart-5b6a6323-8c86-442b-aebb-ae3f3aee5ad4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781667640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1781667640
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.3779244538
Short name T268
Test name
Test status
Simulation time 395735425745 ps
CPU time 3152.15 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 04:00:53 PM PDT 24
Peak memory 191272 kb
Host smart-73983764-060a-41fc-8d04-ca90d617104c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779244538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3779244538
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1617578159
Short name T13
Test name
Test status
Simulation time 493461757206 ps
CPU time 275.93 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:12:55 PM PDT 24
Peak memory 183088 kb
Host smart-171f3fa9-4a85-4f4f-9ed5-af7a03e4dc0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617578159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1617578159
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/54.rv_timer_random.2012483009
Short name T249
Test name
Test status
Simulation time 114356948524 ps
CPU time 251.71 seconds
Started Apr 30 03:09:20 PM PDT 24
Finished Apr 30 03:13:33 PM PDT 24
Peak memory 191276 kb
Host smart-278056a0-2878-4fb3-93f3-966efb5a061d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012483009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2012483009
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.3083749719
Short name T289
Test name
Test status
Simulation time 412069477256 ps
CPU time 186 seconds
Started Apr 30 03:08:00 PM PDT 24
Finished Apr 30 03:11:07 PM PDT 24
Peak memory 191264 kb
Host smart-02954bf1-b410-43ed-a96d-4a4f5eadf85b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083749719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3083749719
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3785356747
Short name T203
Test name
Test status
Simulation time 687888720570 ps
CPU time 417.38 seconds
Started Apr 30 03:10:02 PM PDT 24
Finished Apr 30 03:17:00 PM PDT 24
Peak memory 191224 kb
Host smart-3322e8b8-a9b0-4a07-a71d-5c0a35984be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785356747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3785356747
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1019549227
Short name T335
Test name
Test status
Simulation time 1664116735889 ps
CPU time 631.9 seconds
Started Apr 30 03:08:06 PM PDT 24
Finished Apr 30 03:18:38 PM PDT 24
Peak memory 183020 kb
Host smart-2278f32e-5af7-4f7d-a12a-45919001b401
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019549227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1019549227
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.169984691
Short name T144
Test name
Test status
Simulation time 83011975267 ps
CPU time 143.56 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:10:42 PM PDT 24
Peak memory 183064 kb
Host smart-4f48aefb-7967-4be7-9dc9-499c306d0e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169984691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.169984691
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/148.rv_timer_random.598500402
Short name T177
Test name
Test status
Simulation time 108881248541 ps
CPU time 301.53 seconds
Started Apr 30 03:10:18 PM PDT 24
Finished Apr 30 03:15:20 PM PDT 24
Peak memory 191228 kb
Host smart-80509d9a-9228-4f81-8a70-3cd9c893e3be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598500402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.598500402
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1535874528
Short name T344
Test name
Test status
Simulation time 103678161768 ps
CPU time 165.41 seconds
Started Apr 30 03:10:19 PM PDT 24
Finished Apr 30 03:13:05 PM PDT 24
Peak memory 191244 kb
Host smart-7408ecbb-9e24-4a93-915b-5e8b1331749a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535874528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1535874528
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.4007892667
Short name T172
Test name
Test status
Simulation time 75749046741 ps
CPU time 106.8 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:10:06 PM PDT 24
Peak memory 194836 kb
Host smart-bbca65c7-40ac-41f4-91ca-413ee8f10211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007892667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4007892667
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.917567679
Short name T7
Test name
Test status
Simulation time 239167605388 ps
CPU time 149.63 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:10:43 PM PDT 24
Peak memory 183012 kb
Host smart-478004c1-8109-4b3f-b18a-5b03b9a8c928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917567679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.917567679
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/174.rv_timer_random.384904756
Short name T2
Test name
Test status
Simulation time 373641977757 ps
CPU time 171.98 seconds
Started Apr 30 03:10:30 PM PDT 24
Finished Apr 30 03:13:23 PM PDT 24
Peak memory 191196 kb
Host smart-086f0a9a-d37d-49cc-b79c-76f4a386b238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384904756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.384904756
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2718049089
Short name T342
Test name
Test status
Simulation time 60828146481 ps
CPU time 97.15 seconds
Started Apr 30 03:10:32 PM PDT 24
Finished Apr 30 03:12:10 PM PDT 24
Peak memory 191284 kb
Host smart-9a30a896-5d63-4376-9237-0b6f8677b32e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718049089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2718049089
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1338703878
Short name T446
Test name
Test status
Simulation time 197449570489 ps
CPU time 90.6 seconds
Started Apr 30 03:10:38 PM PDT 24
Finished Apr 30 03:12:09 PM PDT 24
Peak memory 183068 kb
Host smart-339beda9-7477-4ef0-b2af-8e286c990c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338703878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1338703878
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.826296823
Short name T349
Test name
Test status
Simulation time 195419007964 ps
CPU time 156.54 seconds
Started Apr 30 03:10:44 PM PDT 24
Finished Apr 30 03:13:21 PM PDT 24
Peak memory 191264 kb
Host smart-f91d5b76-b68c-4bcb-98c3-74d76860d762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826296823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.826296823
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1702709834
Short name T298
Test name
Test status
Simulation time 273385983368 ps
CPU time 720.2 seconds
Started Apr 30 03:10:43 PM PDT 24
Finished Apr 30 03:22:43 PM PDT 24
Peak memory 191236 kb
Host smart-91d3cd76-dcd9-42c6-b528-0d35cdd30e52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702709834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1702709834
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1723171818
Short name T356
Test name
Test status
Simulation time 358988360121 ps
CPU time 177.37 seconds
Started Apr 30 03:08:10 PM PDT 24
Finished Apr 30 03:11:08 PM PDT 24
Peak memory 183060 kb
Host smart-ff935e24-889a-4b23-bc97-30b7dddee6c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723171818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1723171818
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/197.rv_timer_random.2068055766
Short name T300
Test name
Test status
Simulation time 122530855940 ps
CPU time 312.16 seconds
Started Apr 30 03:10:48 PM PDT 24
Finished Apr 30 03:16:01 PM PDT 24
Peak memory 191260 kb
Host smart-56d660c6-6019-4fd4-a7c5-952ea5ed2e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068055766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2068055766
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.403730303
Short name T208
Test name
Test status
Simulation time 298417128464 ps
CPU time 250.22 seconds
Started Apr 30 03:08:10 PM PDT 24
Finished Apr 30 03:12:21 PM PDT 24
Peak memory 191272 kb
Host smart-b0b6ba9b-ab42-4096-a5dd-aaa92a25cf3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403730303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.403730303
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.25457387
Short name T41
Test name
Test status
Simulation time 28294529593 ps
CPU time 224.24 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:11:55 PM PDT 24
Peak memory 197624 kb
Host smart-e25bfa64-b60b-4ff8-9b7d-ccb351ddea91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25457387 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.25457387
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3143397978
Short name T362
Test name
Test status
Simulation time 74414374092 ps
CPU time 134.48 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:10:27 PM PDT 24
Peak memory 182960 kb
Host smart-b60a6d2c-7f5c-4302-a498-072918ce8dce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143397978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3143397978
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.620615383
Short name T296
Test name
Test status
Simulation time 356281732524 ps
CPU time 308.8 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:13:36 PM PDT 24
Peak memory 183040 kb
Host smart-f2b75d78-2c94-4cba-b387-019d4dc94ae7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620615383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.620615383
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random.520654471
Short name T192
Test name
Test status
Simulation time 451637480116 ps
CPU time 644.22 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:19:11 PM PDT 24
Peak memory 193748 kb
Host smart-6b067c08-1862-48e0-aa3f-65edec84b85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520654471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.520654471
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.2586867536
Short name T128
Test name
Test status
Simulation time 498665747739 ps
CPU time 672.61 seconds
Started Apr 30 03:08:51 PM PDT 24
Finished Apr 30 03:20:04 PM PDT 24
Peak memory 191184 kb
Host smart-2e0b89db-d636-4d3c-b4b4-959ab2b5b517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586867536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2586867536
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2886907946
Short name T245
Test name
Test status
Simulation time 94225183308 ps
CPU time 165.51 seconds
Started Apr 30 03:07:57 PM PDT 24
Finished Apr 30 03:10:44 PM PDT 24
Peak memory 191220 kb
Host smart-ed6b7bc0-c439-4111-8263-cfc621279503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886907946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2886907946
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1003120008
Short name T57
Test name
Test status
Simulation time 38840696 ps
CPU time 0.81 seconds
Started Apr 30 03:07:11 PM PDT 24
Finished Apr 30 03:07:12 PM PDT 24
Peak memory 182720 kb
Host smart-b0077afa-c0af-42e3-bcb4-fa22e8202815
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003120008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1003120008
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1853322502
Short name T552
Test name
Test status
Simulation time 792637353 ps
CPU time 2.52 seconds
Started Apr 30 03:07:10 PM PDT 24
Finished Apr 30 03:07:13 PM PDT 24
Peak memory 193888 kb
Host smart-206fb806-0c3f-465f-ae18-d914a3304d02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853322502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1853322502
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3413726954
Short name T77
Test name
Test status
Simulation time 58492666 ps
CPU time 0.56 seconds
Started Apr 30 03:07:08 PM PDT 24
Finished Apr 30 03:07:09 PM PDT 24
Peak memory 182744 kb
Host smart-09408be9-cebf-4174-8dbc-549fd14dbfe6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413726954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3413726954
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3947246722
Short name T502
Test name
Test status
Simulation time 71776232 ps
CPU time 1.64 seconds
Started Apr 30 03:07:09 PM PDT 24
Finished Apr 30 03:07:12 PM PDT 24
Peak memory 197608 kb
Host smart-211eb81c-b118-4445-8256-2665d12499a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947246722 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3947246722
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2315679911
Short name T497
Test name
Test status
Simulation time 12067036 ps
CPU time 0.55 seconds
Started Apr 30 03:07:11 PM PDT 24
Finished Apr 30 03:07:12 PM PDT 24
Peak memory 182600 kb
Host smart-d7823bb7-ba30-40ca-806e-1330af291699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315679911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2315679911
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1233493055
Short name T478
Test name
Test status
Simulation time 34185725 ps
CPU time 0.63 seconds
Started Apr 30 03:07:10 PM PDT 24
Finished Apr 30 03:07:11 PM PDT 24
Peak memory 192012 kb
Host smart-efd1cd5b-ed11-40ad-b258-746903d23583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233493055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1233493055
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.4217153693
Short name T571
Test name
Test status
Simulation time 2296125765 ps
CPU time 2.3 seconds
Started Apr 30 03:07:12 PM PDT 24
Finished Apr 30 03:07:15 PM PDT 24
Peak memory 197652 kb
Host smart-15a83b1f-966d-4fe6-ba20-2bb2d3985c44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217153693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.4217153693
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3950546268
Short name T501
Test name
Test status
Simulation time 69871555 ps
CPU time 1.1 seconds
Started Apr 30 03:07:11 PM PDT 24
Finished Apr 30 03:07:13 PM PDT 24
Peak memory 183196 kb
Host smart-810e3b89-a28d-402f-96eb-6d4a9b26a741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950546268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3950546268
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.785331385
Short name T90
Test name
Test status
Simulation time 35004255 ps
CPU time 0.81 seconds
Started Apr 30 03:07:08 PM PDT 24
Finished Apr 30 03:07:09 PM PDT 24
Peak memory 192780 kb
Host smart-4bd6f3ee-5681-45ae-9a1e-ea089436bd53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785331385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.785331385
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2869656294
Short name T520
Test name
Test status
Simulation time 829933855 ps
CPU time 3.69 seconds
Started Apr 30 03:07:11 PM PDT 24
Finished Apr 30 03:07:15 PM PDT 24
Peak memory 191212 kb
Host smart-b7bfc360-8f1a-4a8c-866f-567bbfafd9d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869656294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2869656294
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1092894452
Short name T532
Test name
Test status
Simulation time 28655529 ps
CPU time 0.58 seconds
Started Apr 30 03:07:10 PM PDT 24
Finished Apr 30 03:07:12 PM PDT 24
Peak memory 182788 kb
Host smart-a4ec2528-ec40-4472-b956-4207d70c197e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092894452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1092894452
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1905685219
Short name T553
Test name
Test status
Simulation time 17510939 ps
CPU time 0.6 seconds
Started Apr 30 03:07:09 PM PDT 24
Finished Apr 30 03:07:10 PM PDT 24
Peak memory 193128 kb
Host smart-0c89a198-30d5-4bb7-8546-67138d9d1c82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905685219 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1905685219
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.427005579
Short name T507
Test name
Test status
Simulation time 25888574 ps
CPU time 0.6 seconds
Started Apr 30 03:07:12 PM PDT 24
Finished Apr 30 03:07:13 PM PDT 24
Peak memory 182468 kb
Host smart-cf6532ce-c6b1-4c34-bf85-2747ea791f2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427005579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.427005579
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2187611925
Short name T583
Test name
Test status
Simulation time 13374747 ps
CPU time 0.56 seconds
Started Apr 30 03:07:11 PM PDT 24
Finished Apr 30 03:07:12 PM PDT 24
Peak memory 182616 kb
Host smart-6ff3ef1d-5e88-4a91-8224-84279d766a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187611925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2187611925
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1841992570
Short name T555
Test name
Test status
Simulation time 24929656 ps
CPU time 0.65 seconds
Started Apr 30 03:07:09 PM PDT 24
Finished Apr 30 03:07:10 PM PDT 24
Peak memory 191692 kb
Host smart-aa402cc0-e5d5-4016-85e1-c8545fc50d4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841992570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1841992570
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1541837841
Short name T462
Test name
Test status
Simulation time 275556082 ps
CPU time 2.71 seconds
Started Apr 30 03:07:12 PM PDT 24
Finished Apr 30 03:07:15 PM PDT 24
Peak memory 197588 kb
Host smart-6610bd7a-bc58-46fd-8da8-7ddf7d3b020d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541837841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1541837841
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.147065229
Short name T531
Test name
Test status
Simulation time 482722644 ps
CPU time 0.9 seconds
Started Apr 30 03:07:27 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 196384 kb
Host smart-25554061-e4c3-4562-903b-ff10dbb7634a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147065229 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.147065229
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.844597822
Short name T73
Test name
Test status
Simulation time 15787018 ps
CPU time 0.56 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 182756 kb
Host smart-f0d52d41-5dd3-4cb3-bfff-95f92bedb9a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844597822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.844597822
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1638093881
Short name T574
Test name
Test status
Simulation time 20582815 ps
CPU time 0.54 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 182096 kb
Host smart-56dcfbab-e7bb-4546-a906-10a155a0fc0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638093881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1638093881
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.833686752
Short name T542
Test name
Test status
Simulation time 55105804 ps
CPU time 0.69 seconds
Started Apr 30 03:07:27 PM PDT 24
Finished Apr 30 03:07:29 PM PDT 24
Peak memory 191768 kb
Host smart-3d23c48f-dc74-41fd-b4f1-c410f3f8e232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833686752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.833686752
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.376314153
Short name T54
Test name
Test status
Simulation time 145356193 ps
CPU time 1.48 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:27 PM PDT 24
Peak memory 197680 kb
Host smart-7a615faf-783b-4aa6-99d1-1c1234435a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376314153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.376314153
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1521704278
Short name T104
Test name
Test status
Simulation time 151093899 ps
CPU time 1.03 seconds
Started Apr 30 03:07:28 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 195152 kb
Host smart-c9d0db93-e703-482d-875c-7c828f099350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521704278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1521704278
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2991798027
Short name T533
Test name
Test status
Simulation time 86289343 ps
CPU time 1.04 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:39 PM PDT 24
Peak memory 197432 kb
Host smart-7e20134d-b9f8-4e80-b469-9142f6870b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991798027 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2991798027
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4071055750
Short name T91
Test name
Test status
Simulation time 19748223 ps
CPU time 0.54 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 182488 kb
Host smart-fc077e00-b992-4a1a-9da1-4dc5fadad56a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071055750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4071055750
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.275098943
Short name T527
Test name
Test status
Simulation time 19437625 ps
CPU time 0.52 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 182332 kb
Host smart-8483c7a7-e352-42f9-bf87-e27f839e9674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275098943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.275098943
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2990220962
Short name T99
Test name
Test status
Simulation time 18927226 ps
CPU time 0.69 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:31 PM PDT 24
Peak memory 192920 kb
Host smart-d8158f58-808b-478d-97a3-be6b440710ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990220962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2990220962
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3546172542
Short name T52
Test name
Test status
Simulation time 140436099 ps
CPU time 1.86 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 197616 kb
Host smart-4ef8c297-7b25-4330-9b48-d9eff273910e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546172542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3546172542
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4035840205
Short name T584
Test name
Test status
Simulation time 158767094 ps
CPU time 1.32 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 195448 kb
Host smart-8bf3b0fd-319b-43a0-96c1-694ca717be49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035840205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.4035840205
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1330571538
Short name T479
Test name
Test status
Simulation time 30581267 ps
CPU time 1.21 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:31 PM PDT 24
Peak memory 197356 kb
Host smart-65b6d582-4f28-4336-ac54-044cdd59044a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330571538 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1330571538
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1867139068
Short name T92
Test name
Test status
Simulation time 18099693 ps
CPU time 0.63 seconds
Started Apr 30 03:07:32 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 182752 kb
Host smart-e25d48ec-5ec2-4457-a3f2-e5d30aa9f653
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867139068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1867139068
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3207559487
Short name T483
Test name
Test status
Simulation time 33364072 ps
CPU time 0.52 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:31 PM PDT 24
Peak memory 182132 kb
Host smart-af1caec4-8043-475f-8835-0b4abff00fed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207559487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3207559487
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2393062445
Short name T100
Test name
Test status
Simulation time 15704949 ps
CPU time 0.69 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 192808 kb
Host smart-649f8a82-c572-484a-aaf7-085a965cff71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393062445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2393062445
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.831177311
Short name T463
Test name
Test status
Simulation time 49522121 ps
CPU time 2.26 seconds
Started Apr 30 03:07:34 PM PDT 24
Finished Apr 30 03:07:37 PM PDT 24
Peak memory 197232 kb
Host smart-306d3e0a-c617-4a3b-9e80-10b7eb8fa119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831177311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.831177311
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1185948494
Short name T103
Test name
Test status
Simulation time 438635001 ps
CPU time 1.34 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 195288 kb
Host smart-6d3bfae4-546d-46e7-9b96-252d377de8b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185948494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1185948494
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2787973879
Short name T508
Test name
Test status
Simulation time 27815295 ps
CPU time 0.84 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 195632 kb
Host smart-4ee0c1f1-c6b4-471c-9b71-5c6a50334657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787973879 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2787973879
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2088243887
Short name T482
Test name
Test status
Simulation time 31396419 ps
CPU time 0.53 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 182676 kb
Host smart-07f5f4be-80a0-497d-b8ce-115b67f4a16b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088243887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2088243887
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1968192634
Short name T470
Test name
Test status
Simulation time 46649400 ps
CPU time 0.56 seconds
Started Apr 30 03:07:36 PM PDT 24
Finished Apr 30 03:07:38 PM PDT 24
Peak memory 182712 kb
Host smart-1af00944-98f4-4024-aad7-aeff020031be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968192634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1968192634
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.43168664
Short name T95
Test name
Test status
Simulation time 18772441 ps
CPU time 0.72 seconds
Started Apr 30 03:07:32 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 192140 kb
Host smart-c8ffca64-69e0-4a03-86e3-91fdbda07e3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43168664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_tim
er_same_csr_outstanding.43168664
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1998441629
Short name T556
Test name
Test status
Simulation time 378991163 ps
CPU time 1.33 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 197580 kb
Host smart-61104373-ef8e-41a0-b1a9-729b4ae902a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998441629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1998441629
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2536756243
Short name T545
Test name
Test status
Simulation time 2073723363 ps
CPU time 1.39 seconds
Started Apr 30 03:07:34 PM PDT 24
Finished Apr 30 03:07:36 PM PDT 24
Peak memory 195016 kb
Host smart-ff1660e6-a173-415f-a37a-7d33846fb43b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536756243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2536756243
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2158607685
Short name T567
Test name
Test status
Simulation time 19687485 ps
CPU time 0.69 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 194548 kb
Host smart-59de0c5c-aff1-4dd0-96a4-e28b4f5422e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158607685 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2158607685
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4146535669
Short name T76
Test name
Test status
Simulation time 34692397 ps
CPU time 0.61 seconds
Started Apr 30 03:07:31 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 182708 kb
Host smart-9ef824d9-92fa-4a43-8b82-89f8feee29cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146535669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4146535669
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3431318993
Short name T476
Test name
Test status
Simulation time 21932437 ps
CPU time 0.53 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:38 PM PDT 24
Peak memory 182644 kb
Host smart-9acdbbd2-7a4c-4b55-a8a3-8527e9dd1774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431318993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3431318993
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.799223759
Short name T94
Test name
Test status
Simulation time 14641926 ps
CPU time 0.7 seconds
Started Apr 30 03:07:34 PM PDT 24
Finished Apr 30 03:07:35 PM PDT 24
Peak memory 192704 kb
Host smart-0444c108-41ed-41d3-8eb4-4976c75d24c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799223759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.799223759
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.176105755
Short name T543
Test name
Test status
Simulation time 155012294 ps
CPU time 2.31 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:34 PM PDT 24
Peak memory 197576 kb
Host smart-3779bd61-4877-438c-933c-05957143ce15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176105755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.176105755
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.703656149
Short name T31
Test name
Test status
Simulation time 77296203 ps
CPU time 0.83 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 193880 kb
Host smart-de0d6ff4-be68-4448-a196-9a8ee3f19469
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703656149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.703656149
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2374282751
Short name T512
Test name
Test status
Simulation time 57603706 ps
CPU time 0.6 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:31 PM PDT 24
Peak memory 193036 kb
Host smart-3d43e358-4b74-43de-8ea4-16d71a9d0dd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374282751 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2374282751
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1967172510
Short name T51
Test name
Test status
Simulation time 16456576 ps
CPU time 0.59 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182756 kb
Host smart-18a4f7f5-2557-4f8c-b1c1-b2a58612b295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967172510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1967172510
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2517816824
Short name T575
Test name
Test status
Simulation time 41698670 ps
CPU time 0.57 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182648 kb
Host smart-202d717a-d557-4e8f-85af-b6b5db0e95cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517816824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2517816824
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2224711703
Short name T559
Test name
Test status
Simulation time 36274260 ps
CPU time 0.61 seconds
Started Apr 30 03:07:32 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 192264 kb
Host smart-36b3ca88-9c50-426d-a55f-716ba12308e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224711703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2224711703
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3631846300
Short name T522
Test name
Test status
Simulation time 45636149 ps
CPU time 0.75 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:39 PM PDT 24
Peak memory 191464 kb
Host smart-b77b189b-442e-4584-9185-d1a50d5ea86f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631846300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3631846300
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3836627148
Short name T500
Test name
Test status
Simulation time 551424815 ps
CPU time 1.3 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 183424 kb
Host smart-63d18c63-e787-44ee-aab3-f8d70c854770
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836627148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3836627148
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.690154928
Short name T537
Test name
Test status
Simulation time 92061324 ps
CPU time 0.72 seconds
Started Apr 30 03:07:31 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 195120 kb
Host smart-67101634-33c3-4010-bc70-01de5b1d04d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690154928 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.690154928
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1949735503
Short name T510
Test name
Test status
Simulation time 13480612 ps
CPU time 0.56 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 182684 kb
Host smart-51475fc9-9dd4-4282-b6ff-c24a27146107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949735503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1949735503
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2118256177
Short name T495
Test name
Test status
Simulation time 32029722 ps
CPU time 0.54 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 182688 kb
Host smart-6077730f-47d8-49ba-b91d-268a7ecefe6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118256177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2118256177
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2921296142
Short name T53
Test name
Test status
Simulation time 137336218 ps
CPU time 0.64 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:31 PM PDT 24
Peak memory 191788 kb
Host smart-1c34eea2-7361-492f-a741-aeb4acfe2092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921296142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2921296142
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3537807141
Short name T549
Test name
Test status
Simulation time 34756739 ps
CPU time 1.53 seconds
Started Apr 30 03:07:31 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 197688 kb
Host smart-b7e0850d-d2e8-4c3b-9408-ae81b70a527c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537807141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3537807141
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.918973954
Short name T547
Test name
Test status
Simulation time 190767065 ps
CPU time 0.82 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:31 PM PDT 24
Peak memory 193368 kb
Host smart-10b24459-fe6e-4e17-b097-095eb0cbb8ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918973954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.918973954
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2090013185
Short name T566
Test name
Test status
Simulation time 24525389 ps
CPU time 0.79 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:07:47 PM PDT 24
Peak memory 194844 kb
Host smart-4834794a-2c40-4ae3-af85-ebb536041e99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090013185 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2090013185
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.255446582
Short name T492
Test name
Test status
Simulation time 98111132 ps
CPU time 0.51 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:38 PM PDT 24
Peak memory 182696 kb
Host smart-9a010321-0813-4efe-a0f7-de13f19a4bbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255446582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.255446582
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1016236584
Short name T489
Test name
Test status
Simulation time 22837094 ps
CPU time 0.54 seconds
Started Apr 30 03:07:40 PM PDT 24
Finished Apr 30 03:07:41 PM PDT 24
Peak memory 182584 kb
Host smart-46ba5e55-d494-4d66-bf2e-edefc6992c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016236584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1016236584
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2897250138
Short name T498
Test name
Test status
Simulation time 171854642 ps
CPU time 0.67 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:07:46 PM PDT 24
Peak memory 192256 kb
Host smart-91d37786-0a67-4a65-854f-e4740625c1bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897250138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2897250138
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3097225936
Short name T457
Test name
Test status
Simulation time 88318292 ps
CPU time 2.31 seconds
Started Apr 30 03:07:31 PM PDT 24
Finished Apr 30 03:07:34 PM PDT 24
Peak memory 197664 kb
Host smart-9d2d89e4-d238-40cf-90e6-32805842b679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097225936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3097225936
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1518307639
Short name T55
Test name
Test status
Simulation time 390831185 ps
CPU time 0.79 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 193424 kb
Host smart-24ab6b3e-af76-457a-8fd0-e96d3d1c1754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518307639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1518307639
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3711507886
Short name T466
Test name
Test status
Simulation time 65515684 ps
CPU time 1.19 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 197616 kb
Host smart-53b442e0-0b10-4220-9df8-2bfa42bc798d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711507886 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3711507886
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3647015193
Short name T554
Test name
Test status
Simulation time 17452347 ps
CPU time 0.53 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182580 kb
Host smart-559df5c4-9274-4ae8-a437-0b78fde6d84e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647015193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3647015193
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.787885319
Short name T569
Test name
Test status
Simulation time 15658993 ps
CPU time 0.61 seconds
Started Apr 30 03:07:36 PM PDT 24
Finished Apr 30 03:07:38 PM PDT 24
Peak memory 182632 kb
Host smart-4dbbadef-2175-491a-aae7-0752b5d33704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787885319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.787885319
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.777781497
Short name T56
Test name
Test status
Simulation time 21525103 ps
CPU time 0.59 seconds
Started Apr 30 03:07:35 PM PDT 24
Finished Apr 30 03:07:36 PM PDT 24
Peak memory 191632 kb
Host smart-950af166-fdc3-4783-9549-c4aa77e30038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777781497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.777781497
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4060438858
Short name T506
Test name
Test status
Simulation time 816200164 ps
CPU time 3.39 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:41 PM PDT 24
Peak memory 197604 kb
Host smart-adbb966a-b6d0-4691-99d7-f069dc0b380f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060438858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4060438858
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1918572307
Short name T32
Test name
Test status
Simulation time 85097919 ps
CPU time 1.07 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:41 PM PDT 24
Peak memory 195092 kb
Host smart-d77ca6f4-41f6-4796-99b1-842447de769b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918572307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1918572307
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.227792006
Short name T580
Test name
Test status
Simulation time 93342939 ps
CPU time 0.66 seconds
Started Apr 30 03:07:36 PM PDT 24
Finished Apr 30 03:07:38 PM PDT 24
Peak memory 193964 kb
Host smart-b898a5d0-c0fd-4ffe-8280-3e77afeecb4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227792006 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.227792006
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2123851623
Short name T562
Test name
Test status
Simulation time 38084510 ps
CPU time 0.66 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:39 PM PDT 24
Peak memory 182680 kb
Host smart-fe48a5fc-9235-496b-82cf-63bdb13bf45e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123851623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2123851623
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2679675181
Short name T475
Test name
Test status
Simulation time 13990929 ps
CPU time 0.53 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182296 kb
Host smart-683a8f4d-b4e0-4301-bec6-0e00646bf428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679675181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2679675181
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2284991662
Short name T75
Test name
Test status
Simulation time 110633769 ps
CPU time 0.66 seconds
Started Apr 30 03:07:35 PM PDT 24
Finished Apr 30 03:07:36 PM PDT 24
Peak memory 191652 kb
Host smart-f088d6d8-1f00-40f5-9d50-264e8be68ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284991662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2284991662
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.570257507
Short name T578
Test name
Test status
Simulation time 68691193 ps
CPU time 0.91 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 196944 kb
Host smart-35b16199-c319-40e3-93b5-ff93e475c4ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570257507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.570257507
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1572539130
Short name T105
Test name
Test status
Simulation time 79983923 ps
CPU time 0.84 seconds
Started Apr 30 03:07:43 PM PDT 24
Finished Apr 30 03:07:44 PM PDT 24
Peak memory 193336 kb
Host smart-92621324-aa4e-4931-9f38-21c73caeea8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572539130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1572539130
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1905410128
Short name T34
Test name
Test status
Simulation time 297552539 ps
CPU time 0.76 seconds
Started Apr 30 03:07:18 PM PDT 24
Finished Apr 30 03:07:20 PM PDT 24
Peak memory 192472 kb
Host smart-02e1a00d-23b1-496e-9a1d-24bb12b9c188
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905410128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1905410128
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.516982763
Short name T540
Test name
Test status
Simulation time 883750280 ps
CPU time 2.41 seconds
Started Apr 30 03:07:23 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 191128 kb
Host smart-aa544d20-18e3-4408-bae3-140479d32dae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516982763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.516982763
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.633190956
Short name T493
Test name
Test status
Simulation time 18902737 ps
CPU time 0.58 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:27 PM PDT 24
Peak memory 182724 kb
Host smart-e21c2ffa-a269-4ec8-b395-69799f9ceab1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633190956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.633190956
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.621429314
Short name T486
Test name
Test status
Simulation time 45451274 ps
CPU time 1.21 seconds
Started Apr 30 03:07:22 PM PDT 24
Finished Apr 30 03:07:24 PM PDT 24
Peak memory 197876 kb
Host smart-83b85a3d-43ce-445b-9762-2e6c3a348e66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621429314 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.621429314
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4095703536
Short name T474
Test name
Test status
Simulation time 36763391 ps
CPU time 0.53 seconds
Started Apr 30 03:07:17 PM PDT 24
Finished Apr 30 03:07:19 PM PDT 24
Peak memory 182492 kb
Host smart-47fb02de-1e6a-4468-a816-5b8d36ff332a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095703536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.4095703536
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1043693098
Short name T465
Test name
Test status
Simulation time 24719094 ps
CPU time 0.6 seconds
Started Apr 30 03:07:22 PM PDT 24
Finished Apr 30 03:07:23 PM PDT 24
Peak memory 182656 kb
Host smart-cb05c69d-eb9b-404e-9bf7-77f5671bb4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043693098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1043693098
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1999575861
Short name T485
Test name
Test status
Simulation time 15671126 ps
CPU time 0.61 seconds
Started Apr 30 03:07:23 PM PDT 24
Finished Apr 30 03:07:25 PM PDT 24
Peak memory 191788 kb
Host smart-f7dc23f4-830c-4bd5-bba4-71dbe5d7b0b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999575861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1999575861
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2628002869
Short name T565
Test name
Test status
Simulation time 294547038 ps
CPU time 2.65 seconds
Started Apr 30 03:07:09 PM PDT 24
Finished Apr 30 03:07:12 PM PDT 24
Peak memory 197616 kb
Host smart-8960a4a1-2abe-4cbe-8fd1-c9f5aa04c379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628002869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2628002869
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3680911197
Short name T481
Test name
Test status
Simulation time 699159521 ps
CPU time 0.78 seconds
Started Apr 30 03:07:18 PM PDT 24
Finished Apr 30 03:07:19 PM PDT 24
Peak memory 182940 kb
Host smart-3f7fb535-c82b-4ffc-9359-9d0dc9856d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680911197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3680911197
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3719951227
Short name T519
Test name
Test status
Simulation time 12037957 ps
CPU time 0.54 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:39 PM PDT 24
Peak memory 182572 kb
Host smart-a750ac1b-59e8-410d-8048-d837bfb35255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719951227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3719951227
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1479942101
Short name T541
Test name
Test status
Simulation time 13271676 ps
CPU time 0.51 seconds
Started Apr 30 03:07:36 PM PDT 24
Finished Apr 30 03:07:38 PM PDT 24
Peak memory 182064 kb
Host smart-188fc317-550f-4d0b-9f2f-0cfcd2845560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479942101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1479942101
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.224414265
Short name T456
Test name
Test status
Simulation time 33702464 ps
CPU time 0.56 seconds
Started Apr 30 03:07:36 PM PDT 24
Finished Apr 30 03:07:37 PM PDT 24
Peak memory 182616 kb
Host smart-7eb157f7-36b0-4fbe-8178-52cec0cdbb8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224414265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.224414265
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1447431888
Short name T468
Test name
Test status
Simulation time 40815852 ps
CPU time 0.54 seconds
Started Apr 30 03:07:36 PM PDT 24
Finished Apr 30 03:07:37 PM PDT 24
Peak memory 182724 kb
Host smart-310b5479-818f-4241-aeb6-09a55f88776d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447431888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1447431888
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3747866150
Short name T487
Test name
Test status
Simulation time 12324990 ps
CPU time 0.51 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182148 kb
Host smart-f35f568b-8d33-47b5-864e-f2464bd6a0a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747866150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3747866150
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.639744772
Short name T521
Test name
Test status
Simulation time 41293383 ps
CPU time 0.54 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:07:47 PM PDT 24
Peak memory 182280 kb
Host smart-45733fdf-98df-4bbc-b417-a7644d11b044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639744772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.639744772
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3582057263
Short name T546
Test name
Test status
Simulation time 24042512 ps
CPU time 0.53 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:39 PM PDT 24
Peak memory 182152 kb
Host smart-0a004d8f-d95f-4df1-87de-8daf1aa55af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582057263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3582057263
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1469539853
Short name T539
Test name
Test status
Simulation time 39103676 ps
CPU time 0.53 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182724 kb
Host smart-18ddb114-394a-4ccb-b75b-8275c2bb9344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469539853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1469539853
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2842544729
Short name T530
Test name
Test status
Simulation time 16405643 ps
CPU time 0.55 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:39 PM PDT 24
Peak memory 182660 kb
Host smart-eb728868-e3c9-4e7d-96fe-055d60acac56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842544729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2842544729
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3674217197
Short name T579
Test name
Test status
Simulation time 33084786 ps
CPU time 0.52 seconds
Started Apr 30 03:07:39 PM PDT 24
Finished Apr 30 03:07:41 PM PDT 24
Peak memory 182592 kb
Host smart-091c1f41-1b78-49f4-82ea-cf2c4ab76c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674217197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3674217197
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.878399232
Short name T491
Test name
Test status
Simulation time 114296573 ps
CPU time 0.7 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 182796 kb
Host smart-b04a44e0-6c50-44b7-b747-34890949ed47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878399232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.878399232
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.233647176
Short name T535
Test name
Test status
Simulation time 24019969 ps
CPU time 0.52 seconds
Started Apr 30 03:07:16 PM PDT 24
Finished Apr 30 03:07:17 PM PDT 24
Peak memory 182136 kb
Host smart-74b85172-2fdf-4ce9-8b72-cff79df4f92a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233647176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.233647176
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2806529238
Short name T464
Test name
Test status
Simulation time 54431794 ps
CPU time 1.34 seconds
Started Apr 30 03:07:24 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 197580 kb
Host smart-add87670-bf68-4c68-be1d-6a5eb5367688
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806529238 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2806529238
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3074449352
Short name T93
Test name
Test status
Simulation time 19075160 ps
CPU time 0.63 seconds
Started Apr 30 03:07:23 PM PDT 24
Finished Apr 30 03:07:24 PM PDT 24
Peak memory 182724 kb
Host smart-bb943db2-67d8-4f7d-9278-6b8e2cefe646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074449352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3074449352
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.819459542
Short name T480
Test name
Test status
Simulation time 19305621 ps
CPU time 0.57 seconds
Started Apr 30 03:07:15 PM PDT 24
Finished Apr 30 03:07:16 PM PDT 24
Peak memory 182644 kb
Host smart-8421a7e7-c43e-4ac8-9725-b75300413d0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819459542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.819459542
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3776303829
Short name T97
Test name
Test status
Simulation time 230983009 ps
CPU time 0.79 seconds
Started Apr 30 03:07:18 PM PDT 24
Finished Apr 30 03:07:19 PM PDT 24
Peak memory 191740 kb
Host smart-b5f2c9cd-4779-49bb-a49c-0121a67ab8a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776303829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3776303829
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1653746829
Short name T528
Test name
Test status
Simulation time 83747321 ps
CPU time 2.23 seconds
Started Apr 30 03:07:17 PM PDT 24
Finished Apr 30 03:07:20 PM PDT 24
Peak memory 197660 kb
Host smart-994f7979-cd7d-45f7-8e3c-ca8d3f65d514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653746829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1653746829
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.992754527
Short name T30
Test name
Test status
Simulation time 52458623 ps
CPU time 0.81 seconds
Started Apr 30 03:07:24 PM PDT 24
Finished Apr 30 03:07:25 PM PDT 24
Peak memory 183056 kb
Host smart-4a07f4e7-63a2-443d-acf6-413bea3c286c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992754527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.992754527
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.4132913186
Short name T467
Test name
Test status
Simulation time 44078214 ps
CPU time 0.55 seconds
Started Apr 30 03:07:36 PM PDT 24
Finished Apr 30 03:07:37 PM PDT 24
Peak memory 182672 kb
Host smart-98741d1b-eb2b-4c44-96f8-fa8233507345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132913186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.4132913186
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3035804100
Short name T509
Test name
Test status
Simulation time 53997237 ps
CPU time 0.53 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182668 kb
Host smart-d3b1319b-b8b3-420e-8d96-69d21c6db973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035804100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3035804100
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.182389626
Short name T458
Test name
Test status
Simulation time 31487408 ps
CPU time 0.52 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182072 kb
Host smart-041af3f8-020e-4d8f-8931-97afa47f3b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182389626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.182389626
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1037258112
Short name T551
Test name
Test status
Simulation time 12714422 ps
CPU time 0.53 seconds
Started Apr 30 03:07:38 PM PDT 24
Finished Apr 30 03:07:40 PM PDT 24
Peak memory 182052 kb
Host smart-d4e954ff-2014-4c70-8546-06e63a0a6d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037258112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1037258112
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1242678431
Short name T523
Test name
Test status
Simulation time 15956973 ps
CPU time 0.56 seconds
Started Apr 30 03:07:36 PM PDT 24
Finished Apr 30 03:07:37 PM PDT 24
Peak memory 182632 kb
Host smart-301d482e-47ec-4d89-8e1d-998534da2122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242678431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1242678431
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1360023273
Short name T471
Test name
Test status
Simulation time 89236595 ps
CPU time 0.53 seconds
Started Apr 30 03:07:35 PM PDT 24
Finished Apr 30 03:07:36 PM PDT 24
Peak memory 182580 kb
Host smart-bc970d15-8b13-42ff-909f-8cb33bd64ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360023273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1360023273
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.297854177
Short name T516
Test name
Test status
Simulation time 19543249 ps
CPU time 0.56 seconds
Started Apr 30 03:07:37 PM PDT 24
Finished Apr 30 03:07:38 PM PDT 24
Peak memory 182688 kb
Host smart-81ff93e4-493a-49a9-b3d1-6d682cdb6bfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297854177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.297854177
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2652340058
Short name T518
Test name
Test status
Simulation time 17381795 ps
CPU time 0.59 seconds
Started Apr 30 03:07:44 PM PDT 24
Finished Apr 30 03:07:45 PM PDT 24
Peak memory 182616 kb
Host smart-937cb58a-20d6-41ec-bae8-97a2c3e0e7ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652340058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2652340058
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3998059211
Short name T582
Test name
Test status
Simulation time 17785757 ps
CPU time 0.55 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:07:47 PM PDT 24
Peak memory 182528 kb
Host smart-c606a086-edab-4a9e-8e90-24c93d209369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998059211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3998059211
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1244807406
Short name T563
Test name
Test status
Simulation time 51581556 ps
CPU time 0.5 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:07:46 PM PDT 24
Peak memory 182148 kb
Host smart-12236539-78cb-4903-a6af-dd00052d6f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244807406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1244807406
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2065805257
Short name T35
Test name
Test status
Simulation time 17710203 ps
CPU time 0.78 seconds
Started Apr 30 03:07:17 PM PDT 24
Finished Apr 30 03:07:18 PM PDT 24
Peak memory 182768 kb
Host smart-f9f29cb6-2ec0-4d66-9267-f4644476ed7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065805257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2065805257
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1084991435
Short name T80
Test name
Test status
Simulation time 235318670 ps
CPU time 2.35 seconds
Started Apr 30 03:07:17 PM PDT 24
Finished Apr 30 03:07:20 PM PDT 24
Peak memory 193604 kb
Host smart-3d45513c-9090-4573-bfd1-244de729afbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084991435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1084991435
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1391512150
Short name T79
Test name
Test status
Simulation time 76950279 ps
CPU time 0.57 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:27 PM PDT 24
Peak memory 192008 kb
Host smart-2724a901-7abe-4428-b5e1-7ef9d84b702d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391512150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1391512150
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2554150698
Short name T469
Test name
Test status
Simulation time 29773124 ps
CPU time 1.3 seconds
Started Apr 30 03:07:27 PM PDT 24
Finished Apr 30 03:07:29 PM PDT 24
Peak memory 197648 kb
Host smart-5c0d766f-a9f7-4e72-aa5c-42aec15bd0ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554150698 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2554150698
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2120093012
Short name T581
Test name
Test status
Simulation time 12013683 ps
CPU time 0.55 seconds
Started Apr 30 03:07:23 PM PDT 24
Finished Apr 30 03:07:24 PM PDT 24
Peak memory 182692 kb
Host smart-7171ff5e-9be8-4a34-b899-08ac5784ba12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120093012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2120093012
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2595701546
Short name T477
Test name
Test status
Simulation time 20333588 ps
CPU time 0.51 seconds
Started Apr 30 03:07:22 PM PDT 24
Finished Apr 30 03:07:24 PM PDT 24
Peak memory 182068 kb
Host smart-7e51fc64-f910-4fda-962d-3dfedb5383fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595701546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2595701546
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3486837525
Short name T488
Test name
Test status
Simulation time 59419289 ps
CPU time 0.73 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 193252 kb
Host smart-0510c864-e606-4643-baed-8305d5195e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486837525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3486837525
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2101317704
Short name T534
Test name
Test status
Simulation time 174810333 ps
CPU time 2.89 seconds
Started Apr 30 03:07:27 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 197600 kb
Host smart-2bc88d1b-daf3-4d96-9770-af90eaf83c63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101317704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2101317704
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1370862447
Short name T515
Test name
Test status
Simulation time 98430301 ps
CPU time 0.78 seconds
Started Apr 30 03:07:17 PM PDT 24
Finished Apr 30 03:07:18 PM PDT 24
Peak memory 193524 kb
Host smart-61adf462-e069-42af-88ac-e7d39b669da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370862447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1370862447
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2293211446
Short name T558
Test name
Test status
Simulation time 55418310 ps
CPU time 0.55 seconds
Started Apr 30 03:07:43 PM PDT 24
Finished Apr 30 03:07:44 PM PDT 24
Peak memory 182624 kb
Host smart-4aaf5aea-1417-44e2-992c-0d31dbddae6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293211446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2293211446
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.726285394
Short name T525
Test name
Test status
Simulation time 59623072 ps
CPU time 0.53 seconds
Started Apr 30 03:07:41 PM PDT 24
Finished Apr 30 03:07:43 PM PDT 24
Peak memory 182708 kb
Host smart-09b07fd5-976c-4c8b-af0e-1f0236ae7439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726285394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.726285394
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1072576270
Short name T499
Test name
Test status
Simulation time 35106009 ps
CPU time 0.55 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:07:46 PM PDT 24
Peak memory 182624 kb
Host smart-e08d93bc-5ca6-465d-8562-7c78c54b759b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072576270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1072576270
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.809161392
Short name T573
Test name
Test status
Simulation time 171767194 ps
CPU time 0.59 seconds
Started Apr 30 03:07:44 PM PDT 24
Finished Apr 30 03:07:45 PM PDT 24
Peak memory 182668 kb
Host smart-a07c67d4-7429-4c55-a240-7efd32d66693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809161392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.809161392
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3176532290
Short name T503
Test name
Test status
Simulation time 17519879 ps
CPU time 0.53 seconds
Started Apr 30 03:07:43 PM PDT 24
Finished Apr 30 03:07:44 PM PDT 24
Peak memory 182700 kb
Host smart-0c092a75-9df3-4827-8512-f321d1a4e0f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176532290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3176532290
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2855468790
Short name T460
Test name
Test status
Simulation time 40362665 ps
CPU time 0.53 seconds
Started Apr 30 03:07:46 PM PDT 24
Finished Apr 30 03:07:47 PM PDT 24
Peak memory 182296 kb
Host smart-2d8df2e7-1ef1-430d-8185-9bcbb0e2a67e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855468790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2855468790
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3203468773
Short name T513
Test name
Test status
Simulation time 18983437 ps
CPU time 0.52 seconds
Started Apr 30 03:07:43 PM PDT 24
Finished Apr 30 03:07:45 PM PDT 24
Peak memory 182108 kb
Host smart-5c670e4e-c5e2-4de3-8757-07c6528458e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203468773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3203468773
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.109581080
Short name T529
Test name
Test status
Simulation time 39880542 ps
CPU time 0.56 seconds
Started Apr 30 03:07:46 PM PDT 24
Finished Apr 30 03:07:48 PM PDT 24
Peak memory 182604 kb
Host smart-befca077-6b37-48db-b9c0-306707e1aa39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109581080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.109581080
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1747543595
Short name T577
Test name
Test status
Simulation time 11314067 ps
CPU time 0.52 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:07:46 PM PDT 24
Peak memory 182128 kb
Host smart-d42e0de4-cb6f-4156-b2d8-2fbbacbf25d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747543595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1747543595
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3955243622
Short name T511
Test name
Test status
Simulation time 50677660 ps
CPU time 0.55 seconds
Started Apr 30 03:07:46 PM PDT 24
Finished Apr 30 03:07:47 PM PDT 24
Peak memory 182708 kb
Host smart-0c20ab12-1b43-4333-a7e2-ea1787fca8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955243622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3955243622
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.699383562
Short name T568
Test name
Test status
Simulation time 61688136 ps
CPU time 0.83 seconds
Started Apr 30 03:07:24 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 197248 kb
Host smart-d9882692-980a-4323-8231-32a50104237c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699383562 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.699383562
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.783883168
Short name T560
Test name
Test status
Simulation time 23020069 ps
CPU time 0.54 seconds
Started Apr 30 03:07:27 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 182784 kb
Host smart-1eb2bd1b-3c9e-405e-880f-07d2bfa43a61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783883168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.783883168
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1367412838
Short name T526
Test name
Test status
Simulation time 25604673 ps
CPU time 0.55 seconds
Started Apr 30 03:07:17 PM PDT 24
Finished Apr 30 03:07:18 PM PDT 24
Peak memory 182136 kb
Host smart-0f28b742-7abb-4a08-b70b-5c58f82e1241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367412838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1367412838
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2533454593
Short name T524
Test name
Test status
Simulation time 366697314 ps
CPU time 0.7 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:27 PM PDT 24
Peak memory 191680 kb
Host smart-f80ad9d6-8741-43ab-a9ea-1d02e26e1b7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533454593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2533454593
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1389265161
Short name T570
Test name
Test status
Simulation time 231793456 ps
CPU time 2.21 seconds
Started Apr 30 03:07:22 PM PDT 24
Finished Apr 30 03:07:24 PM PDT 24
Peak memory 197572 kb
Host smart-839739ef-88ce-410a-b8e9-d06cdaaea854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389265161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1389265161
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3172296251
Short name T505
Test name
Test status
Simulation time 258380821 ps
CPU time 1.09 seconds
Started Apr 30 03:07:16 PM PDT 24
Finished Apr 30 03:07:17 PM PDT 24
Peak memory 195000 kb
Host smart-9f9a46c8-b806-4201-a36f-ec7cd88c6ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172296251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3172296251
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1525897434
Short name T472
Test name
Test status
Simulation time 52671789 ps
CPU time 1.29 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 197652 kb
Host smart-6595d3fb-10e9-4db1-bde7-f8c9445ed26a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525897434 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1525897434
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1025004693
Short name T484
Test name
Test status
Simulation time 21609819 ps
CPU time 0.53 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 182468 kb
Host smart-9467510b-a785-4a30-8250-d285208a9872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025004693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1025004693
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3222333749
Short name T517
Test name
Test status
Simulation time 17044247 ps
CPU time 0.54 seconds
Started Apr 30 03:07:27 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 182008 kb
Host smart-3e0e9d17-b9d8-4d0b-a372-18d593da5f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222333749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3222333749
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1389212260
Short name T490
Test name
Test status
Simulation time 188751768 ps
CPU time 0.72 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 191824 kb
Host smart-488982d2-9dd0-4d41-9fcb-3555b948667b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389212260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1389212260
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3583716501
Short name T459
Test name
Test status
Simulation time 150666626 ps
CPU time 2.05 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 197688 kb
Host smart-aaaf3b42-2bba-4aec-9da4-daa3d921c743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583716501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3583716501
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3813162479
Short name T561
Test name
Test status
Simulation time 147312254 ps
CPU time 1.39 seconds
Started Apr 30 03:07:28 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 195412 kb
Host smart-3d3b55fc-9ebd-425a-a8d7-2960a3bb77db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813162479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3813162479
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1969754395
Short name T576
Test name
Test status
Simulation time 22929558 ps
CPU time 0.73 seconds
Started Apr 30 03:07:24 PM PDT 24
Finished Apr 30 03:07:25 PM PDT 24
Peak memory 195396 kb
Host smart-93b2b8e0-e69c-405f-b3ad-972ec352de61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969754395 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1969754395
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1200830829
Short name T74
Test name
Test status
Simulation time 104552184 ps
CPU time 0.57 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 182716 kb
Host smart-7c88c2fd-688f-4fcb-a7c4-456fb2831ec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200830829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1200830829
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3927505773
Short name T557
Test name
Test status
Simulation time 12897459 ps
CPU time 0.57 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:27 PM PDT 24
Peak memory 182228 kb
Host smart-3c718165-5cd7-4516-a5c6-c35f9301a4ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927505773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3927505773
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3632461759
Short name T536
Test name
Test status
Simulation time 31123549 ps
CPU time 0.71 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:27 PM PDT 24
Peak memory 192196 kb
Host smart-e4ed0c5a-98bf-4db0-80e3-08e90c038578
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632461759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3632461759
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2222082684
Short name T538
Test name
Test status
Simulation time 115180807 ps
CPU time 1.27 seconds
Started Apr 30 03:07:28 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 197688 kb
Host smart-7461f9e7-3436-404b-903c-d1a865934556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222082684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2222082684
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2494211364
Short name T504
Test name
Test status
Simulation time 51617426 ps
CPU time 0.82 seconds
Started Apr 30 03:07:24 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 193556 kb
Host smart-2424d8a9-c886-4d8e-aa82-fe998b4cdad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494211364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2494211364
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1920069004
Short name T514
Test name
Test status
Simulation time 125064941 ps
CPU time 0.95 seconds
Started Apr 30 03:07:30 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 196924 kb
Host smart-f9245e44-6166-4450-bafa-45a5364bdcd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920069004 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1920069004
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2686008471
Short name T496
Test name
Test status
Simulation time 33334645 ps
CPU time 0.53 seconds
Started Apr 30 03:07:24 PM PDT 24
Finished Apr 30 03:07:25 PM PDT 24
Peak memory 182792 kb
Host smart-0035cc61-940f-4504-9962-aae1997b2ad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686008471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2686008471
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1892855720
Short name T548
Test name
Test status
Simulation time 63003509 ps
CPU time 0.56 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 182688 kb
Host smart-bd1d2d4d-11b9-42ba-9af3-36a25b73d7d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892855720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1892855720
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3092770423
Short name T98
Test name
Test status
Simulation time 18499148 ps
CPU time 0.78 seconds
Started Apr 30 03:07:25 PM PDT 24
Finished Apr 30 03:07:26 PM PDT 24
Peak memory 191824 kb
Host smart-82ebb0f4-3d3c-4083-abbe-cdb923f65e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092770423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3092770423
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2463206538
Short name T544
Test name
Test status
Simulation time 242549936 ps
CPU time 1.93 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 197608 kb
Host smart-4e96cce4-5658-4cc7-9f9c-314beb2c32be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463206538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2463206538
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1244385540
Short name T550
Test name
Test status
Simulation time 181655393 ps
CPU time 1.32 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:31 PM PDT 24
Peak memory 195636 kb
Host smart-f3d6feee-c35c-4d6b-b361-16821baf0e44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244385540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1244385540
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3376656359
Short name T494
Test name
Test status
Simulation time 39103430 ps
CPU time 0.82 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 196540 kb
Host smart-20fa86f6-f18e-4135-8ac0-5ece35e76cca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376656359 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3376656359
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.4205462038
Short name T78
Test name
Test status
Simulation time 12099496 ps
CPU time 0.59 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 182724 kb
Host smart-bb937d38-1b32-4bba-ab00-3898f4b3b50d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205462038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.4205462038
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1374439842
Short name T564
Test name
Test status
Simulation time 12384947 ps
CPU time 0.53 seconds
Started Apr 30 03:07:26 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 182208 kb
Host smart-94612f0b-eb1e-434a-a6fd-773e31d57a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374439842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1374439842
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1960644930
Short name T572
Test name
Test status
Simulation time 15538859 ps
CPU time 0.58 seconds
Started Apr 30 03:07:27 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 191432 kb
Host smart-414e81ba-77d5-4690-9f87-ab1ba1f487ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960644930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1960644930
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2391658765
Short name T461
Test name
Test status
Simulation time 106010969 ps
CPU time 2.21 seconds
Started Apr 30 03:07:27 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 197696 kb
Host smart-3a7d637e-c4c5-4134-9864-66b7e4f5e35d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391658765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2391658765
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3101372838
Short name T473
Test name
Test status
Simulation time 49168691 ps
CPU time 0.83 seconds
Started Apr 30 03:07:29 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 193672 kb
Host smart-04a61e37-201f-4795-ba53-cecd08e2ae9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101372838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3101372838
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4050675410
Short name T139
Test name
Test status
Simulation time 161694879231 ps
CPU time 202.21 seconds
Started Apr 30 03:07:44 PM PDT 24
Finished Apr 30 03:11:07 PM PDT 24
Peak memory 182976 kb
Host smart-d7db2f6b-7c56-4d9f-91f6-1525fe024b93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050675410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4050675410
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.4212193468
Short name T388
Test name
Test status
Simulation time 337306960989 ps
CPU time 147.14 seconds
Started Apr 30 03:07:43 PM PDT 24
Finished Apr 30 03:10:11 PM PDT 24
Peak memory 183008 kb
Host smart-c03c83bf-ede1-470a-bdbc-f51098095030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212193468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4212193468
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3651404659
Short name T321
Test name
Test status
Simulation time 789139372293 ps
CPU time 1658.11 seconds
Started Apr 30 03:07:51 PM PDT 24
Finished Apr 30 03:35:30 PM PDT 24
Peak memory 191192 kb
Host smart-3ea4e977-5626-4070-8f52-ddef8008d693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651404659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3651404659
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2637384380
Short name T17
Test name
Test status
Simulation time 36203694 ps
CPU time 0.73 seconds
Started Apr 30 03:07:44 PM PDT 24
Finished Apr 30 03:07:45 PM PDT 24
Peak memory 214012 kb
Host smart-a798e9ab-67c1-4a16-bc39-422946dcfa8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637384380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2637384380
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.627135919
Short name T428
Test name
Test status
Simulation time 96738674606 ps
CPU time 168.05 seconds
Started Apr 30 03:07:46 PM PDT 24
Finished Apr 30 03:10:35 PM PDT 24
Peak memory 183032 kb
Host smart-f528504f-dc54-4679-859b-3a7c1c65d12c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627135919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.627135919
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2532505511
Short name T438
Test name
Test status
Simulation time 833844853731 ps
CPU time 183.18 seconds
Started Apr 30 03:07:47 PM PDT 24
Finished Apr 30 03:10:51 PM PDT 24
Peak memory 182984 kb
Host smart-3968c329-3ffb-49ef-899b-2f4f8e55ceaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532505511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2532505511
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2616705613
Short name T355
Test name
Test status
Simulation time 190452690979 ps
CPU time 324.31 seconds
Started Apr 30 03:07:47 PM PDT 24
Finished Apr 30 03:13:12 PM PDT 24
Peak memory 191244 kb
Host smart-dbf88866-6c49-4abf-9128-777a92175620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616705613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2616705613
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2667608718
Short name T86
Test name
Test status
Simulation time 287346513590 ps
CPU time 160.79 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:10:26 PM PDT 24
Peak memory 183004 kb
Host smart-cf955bb4-5031-4977-befe-5c65369be6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667608718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2667608718
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1790897157
Short name T137
Test name
Test status
Simulation time 841892951564 ps
CPU time 1039.64 seconds
Started Apr 30 03:07:57 PM PDT 24
Finished Apr 30 03:25:18 PM PDT 24
Peak memory 183000 kb
Host smart-6dd6f39d-5708-4edf-bacf-0135ecfa4c55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790897157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1790897157
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3581769364
Short name T389
Test name
Test status
Simulation time 72892619508 ps
CPU time 59.43 seconds
Started Apr 30 03:07:57 PM PDT 24
Finished Apr 30 03:08:58 PM PDT 24
Peak memory 183008 kb
Host smart-b53337ba-9ad4-46ec-8667-358dfe4019f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581769364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3581769364
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3527393123
Short name T377
Test name
Test status
Simulation time 389550461 ps
CPU time 1.25 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:08:06 PM PDT 24
Peak memory 182988 kb
Host smart-60d02311-85d8-4012-91fe-41e00daaef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527393123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3527393123
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.4077132010
Short name T407
Test name
Test status
Simulation time 43220088062 ps
CPU time 243 seconds
Started Apr 30 03:08:17 PM PDT 24
Finished Apr 30 03:12:21 PM PDT 24
Peak memory 197724 kb
Host smart-0da27265-df01-4b99-b8e2-4555b3ae7505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077132010 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.4077132010
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.76049637
Short name T406
Test name
Test status
Simulation time 638756403511 ps
CPU time 183.49 seconds
Started Apr 30 03:09:51 PM PDT 24
Finished Apr 30 03:12:55 PM PDT 24
Peak memory 191268 kb
Host smart-6e958583-2e3c-469a-82f7-f10b0a704c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76049637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.76049637
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.4016685175
Short name T442
Test name
Test status
Simulation time 22082532659 ps
CPU time 84.58 seconds
Started Apr 30 03:09:55 PM PDT 24
Finished Apr 30 03:11:20 PM PDT 24
Peak memory 191208 kb
Host smart-15efb42f-f682-435d-868a-dfd9cfd7dcd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016685175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4016685175
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1284093407
Short name T238
Test name
Test status
Simulation time 513110439207 ps
CPU time 580.65 seconds
Started Apr 30 03:09:55 PM PDT 24
Finished Apr 30 03:19:37 PM PDT 24
Peak memory 191208 kb
Host smart-362338b2-3a6d-4ee1-a4ba-daff956e6af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284093407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1284093407
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2135387632
Short name T204
Test name
Test status
Simulation time 372190160338 ps
CPU time 188.83 seconds
Started Apr 30 03:09:55 PM PDT 24
Finished Apr 30 03:13:04 PM PDT 24
Peak memory 191200 kb
Host smart-376a6ab6-4d1d-4ac7-8572-8bffa011c477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135387632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2135387632
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3076977265
Short name T27
Test name
Test status
Simulation time 35838255472 ps
CPU time 227.58 seconds
Started Apr 30 03:09:49 PM PDT 24
Finished Apr 30 03:13:37 PM PDT 24
Peak memory 183020 kb
Host smart-cccbd4d0-1938-4382-8657-f9178c4bbf12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076977265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3076977265
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2443705695
Short name T165
Test name
Test status
Simulation time 61862900794 ps
CPU time 391.13 seconds
Started Apr 30 03:09:51 PM PDT 24
Finished Apr 30 03:16:22 PM PDT 24
Peak memory 191268 kb
Host smart-4eafe1b3-0cb8-4515-becb-0db3dcb51c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443705695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2443705695
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1692561637
Short name T134
Test name
Test status
Simulation time 301886478869 ps
CPU time 427.88 seconds
Started Apr 30 03:09:55 PM PDT 24
Finished Apr 30 03:17:03 PM PDT 24
Peak memory 191208 kb
Host smart-ab68027d-b097-4d6b-b91e-797964944a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692561637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1692561637
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.127636706
Short name T439
Test name
Test status
Simulation time 487386602941 ps
CPU time 237.79 seconds
Started Apr 30 03:09:57 PM PDT 24
Finished Apr 30 03:13:55 PM PDT 24
Peak memory 191188 kb
Host smart-6c170cab-06d9-485d-8499-f544bc1402f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127636706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.127636706
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.954580458
Short name T324
Test name
Test status
Simulation time 337767893273 ps
CPU time 153.94 seconds
Started Apr 30 03:09:58 PM PDT 24
Finished Apr 30 03:12:32 PM PDT 24
Peak memory 191188 kb
Host smart-4eb57237-14ad-4ada-a7bb-e30e0afa37c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954580458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.954580458
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2328412683
Short name T82
Test name
Test status
Simulation time 10100234965 ps
CPU time 19.55 seconds
Started Apr 30 03:08:05 PM PDT 24
Finished Apr 30 03:08:26 PM PDT 24
Peak memory 182980 kb
Host smart-0d7affa5-c94c-4967-8dbe-0dfbf255b3c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328412683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2328412683
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.249136805
Short name T398
Test name
Test status
Simulation time 64892356308 ps
CPU time 97.11 seconds
Started Apr 30 03:08:03 PM PDT 24
Finished Apr 30 03:09:41 PM PDT 24
Peak memory 182984 kb
Host smart-56db11ef-73a7-4bbd-8163-b86ed31cdff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249136805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.249136805
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1080398007
Short name T120
Test name
Test status
Simulation time 9132663387 ps
CPU time 54.94 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:09:13 PM PDT 24
Peak memory 183056 kb
Host smart-2225ca38-5259-4445-a3cd-b6bf66f0f71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080398007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1080398007
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1229374757
Short name T337
Test name
Test status
Simulation time 22785630845 ps
CPU time 36.04 seconds
Started Apr 30 03:08:05 PM PDT 24
Finished Apr 30 03:08:42 PM PDT 24
Peak memory 191288 kb
Host smart-4d8fcde3-40bb-41f5-98c7-c2eb650b228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229374757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1229374757
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1299136329
Short name T313
Test name
Test status
Simulation time 205171930991 ps
CPU time 249.98 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:12:14 PM PDT 24
Peak memory 191272 kb
Host smart-9c75f3b6-ca0b-4b05-acc6-a287c2537366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299136329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1299136329
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.4226741596
Short name T10
Test name
Test status
Simulation time 12391036662 ps
CPU time 34.16 seconds
Started Apr 30 03:09:57 PM PDT 24
Finished Apr 30 03:10:32 PM PDT 24
Peak memory 183072 kb
Host smart-6a6d19ba-f8cc-46a0-b5c3-356e59d0d4a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226741596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4226741596
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1332926855
Short name T28
Test name
Test status
Simulation time 113170274809 ps
CPU time 304.08 seconds
Started Apr 30 03:09:55 PM PDT 24
Finished Apr 30 03:14:59 PM PDT 24
Peak memory 191188 kb
Host smart-0e8bd0fa-d1d2-42b9-b8db-c063cadda773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332926855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1332926855
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2338358022
Short name T339
Test name
Test status
Simulation time 754697171061 ps
CPU time 1306.21 seconds
Started Apr 30 03:09:57 PM PDT 24
Finished Apr 30 03:31:44 PM PDT 24
Peak memory 191208 kb
Host smart-9bca5791-af6b-4a11-9387-2c311d6585d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338358022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2338358022
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2783644683
Short name T418
Test name
Test status
Simulation time 151552083009 ps
CPU time 79.75 seconds
Started Apr 30 03:09:57 PM PDT 24
Finished Apr 30 03:11:18 PM PDT 24
Peak memory 191284 kb
Host smart-2c3cccf1-ba75-423a-aed4-11309c6d554b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783644683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2783644683
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1674494653
Short name T441
Test name
Test status
Simulation time 501513162618 ps
CPU time 222.58 seconds
Started Apr 30 03:08:09 PM PDT 24
Finished Apr 30 03:11:52 PM PDT 24
Peak memory 183052 kb
Host smart-6c7568f9-85e6-431e-94b9-c8b225175046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674494653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1674494653
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3533358937
Short name T404
Test name
Test status
Simulation time 78821003228 ps
CPU time 624.78 seconds
Started Apr 30 03:08:07 PM PDT 24
Finished Apr 30 03:18:32 PM PDT 24
Peak memory 191152 kb
Host smart-9ecfa80f-b2d1-44d7-a6da-1c76c218a078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533358937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3533358937
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4214759773
Short name T257
Test name
Test status
Simulation time 42342938579 ps
CPU time 39.28 seconds
Started Apr 30 03:08:10 PM PDT 24
Finished Apr 30 03:08:50 PM PDT 24
Peak memory 183076 kb
Host smart-6c45db63-2911-42dc-bba4-97ac009fef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214759773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4214759773
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.545926326
Short name T40
Test name
Test status
Simulation time 67438684787 ps
CPU time 542.51 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:17:22 PM PDT 24
Peak memory 197684 kb
Host smart-fcbf0985-5b37-4319-b083-92b53ae9f461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545926326 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.545926326
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.686169405
Short name T70
Test name
Test status
Simulation time 114213820991 ps
CPU time 1048.66 seconds
Started Apr 30 03:10:04 PM PDT 24
Finished Apr 30 03:27:34 PM PDT 24
Peak memory 194380 kb
Host smart-db83787f-add1-4968-8e26-b3ec3bf1ebf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686169405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.686169405
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2833615156
Short name T267
Test name
Test status
Simulation time 125063699771 ps
CPU time 388.21 seconds
Started Apr 30 03:10:05 PM PDT 24
Finished Apr 30 03:16:34 PM PDT 24
Peak memory 191248 kb
Host smart-f400302e-4eca-448d-97ca-81d0624e9650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833615156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2833615156
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2044111621
Short name T69
Test name
Test status
Simulation time 127602537693 ps
CPU time 129.28 seconds
Started Apr 30 03:10:06 PM PDT 24
Finished Apr 30 03:12:16 PM PDT 24
Peak memory 191440 kb
Host smart-5918f1e5-4eb4-49d7-99e3-115ff2132565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044111621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2044111621
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3804518676
Short name T156
Test name
Test status
Simulation time 553452256269 ps
CPU time 312.14 seconds
Started Apr 30 03:10:04 PM PDT 24
Finished Apr 30 03:15:17 PM PDT 24
Peak memory 191236 kb
Host smart-315deebb-164b-4a93-a34c-4b3c4a06ee8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804518676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3804518676
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1240385107
Short name T294
Test name
Test status
Simulation time 92614398732 ps
CPU time 85.52 seconds
Started Apr 30 03:10:05 PM PDT 24
Finished Apr 30 03:11:31 PM PDT 24
Peak memory 191292 kb
Host smart-a82e749c-ee8a-48f2-9868-7c1340d72625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240385107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1240385107
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.87945217
Short name T167
Test name
Test status
Simulation time 1385321042233 ps
CPU time 1367.53 seconds
Started Apr 30 03:10:04 PM PDT 24
Finished Apr 30 03:32:53 PM PDT 24
Peak memory 191196 kb
Host smart-a48d9ce2-076a-407b-b22e-bc79ff2cfaea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87945217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.87945217
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3457613198
Short name T277
Test name
Test status
Simulation time 264244069574 ps
CPU time 276.08 seconds
Started Apr 30 03:10:04 PM PDT 24
Finished Apr 30 03:14:40 PM PDT 24
Peak memory 191244 kb
Host smart-7e9f7a60-0064-45c9-8b92-de275c28ed00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457613198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3457613198
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1073414825
Short name T314
Test name
Test status
Simulation time 85369533657 ps
CPU time 229.88 seconds
Started Apr 30 03:10:07 PM PDT 24
Finished Apr 30 03:13:57 PM PDT 24
Peak memory 183012 kb
Host smart-dedc5074-3e71-4b22-b260-4d9a4c13cc90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073414825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1073414825
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.264015268
Short name T333
Test name
Test status
Simulation time 871381144301 ps
CPU time 191.34 seconds
Started Apr 30 03:10:04 PM PDT 24
Finished Apr 30 03:13:16 PM PDT 24
Peak memory 191180 kb
Host smart-873af01a-4197-4f25-ae5d-b78854aecba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264015268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.264015268
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2685995833
Short name T171
Test name
Test status
Simulation time 139482275083 ps
CPU time 657.17 seconds
Started Apr 30 03:10:04 PM PDT 24
Finished Apr 30 03:21:02 PM PDT 24
Peak memory 191284 kb
Host smart-04d84945-42a7-4ced-a828-17fe97686586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685995833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2685995833
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4227486945
Short name T150
Test name
Test status
Simulation time 6669261518 ps
CPU time 11.37 seconds
Started Apr 30 03:08:02 PM PDT 24
Finished Apr 30 03:08:14 PM PDT 24
Peak memory 183260 kb
Host smart-a0376473-87ee-499e-8916-d7de13d554ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227486945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4227486945
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1343034318
Short name T408
Test name
Test status
Simulation time 808954691813 ps
CPU time 228.5 seconds
Started Apr 30 03:08:05 PM PDT 24
Finished Apr 30 03:11:54 PM PDT 24
Peak memory 183052 kb
Host smart-0e0c1248-6172-4207-a5f9-a24e9088c69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343034318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1343034318
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.795683083
Short name T336
Test name
Test status
Simulation time 46905681393 ps
CPU time 72.15 seconds
Started Apr 30 03:08:05 PM PDT 24
Finished Apr 30 03:09:18 PM PDT 24
Peak memory 191240 kb
Host smart-4653ad29-a9f6-49a1-88df-4b26eb990ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795683083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.795683083
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.769329377
Short name T393
Test name
Test status
Simulation time 58541615 ps
CPU time 0.56 seconds
Started Apr 30 03:08:17 PM PDT 24
Finished Apr 30 03:08:18 PM PDT 24
Peak memory 182868 kb
Host smart-4bd3d968-3c07-4b6d-90ae-a189ec509d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769329377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.769329377
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3398907402
Short name T211
Test name
Test status
Simulation time 5925011852164 ps
CPU time 1034.2 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:25:19 PM PDT 24
Peak memory 196440 kb
Host smart-799861d3-2f70-44b4-be6a-7ce064401b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398907402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3398907402
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.1881799128
Short name T357
Test name
Test status
Simulation time 213812897593 ps
CPU time 127.91 seconds
Started Apr 30 03:10:05 PM PDT 24
Finished Apr 30 03:12:14 PM PDT 24
Peak memory 183060 kb
Host smart-59978344-4d21-4b8c-8120-a744f0ecd6d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881799128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1881799128
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2757582057
Short name T304
Test name
Test status
Simulation time 574597137545 ps
CPU time 226.96 seconds
Started Apr 30 03:10:04 PM PDT 24
Finished Apr 30 03:13:52 PM PDT 24
Peak memory 191272 kb
Host smart-b11c00e1-1fc7-49f4-b261-41bcfef62be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757582057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2757582057
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3246906131
Short name T193
Test name
Test status
Simulation time 23815446115 ps
CPU time 19.92 seconds
Started Apr 30 03:10:12 PM PDT 24
Finished Apr 30 03:10:32 PM PDT 24
Peak memory 183092 kb
Host smart-d4eed399-910f-4bbf-95c7-7641d9f4ac71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246906131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3246906131
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1249517607
Short name T394
Test name
Test status
Simulation time 112383342399 ps
CPU time 134.39 seconds
Started Apr 30 03:10:13 PM PDT 24
Finished Apr 30 03:12:28 PM PDT 24
Peak memory 191272 kb
Host smart-cee98d13-78b7-4f46-ac31-9e02b6957b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249517607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1249517607
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1012710582
Short name T259
Test name
Test status
Simulation time 492608811089 ps
CPU time 182.66 seconds
Started Apr 30 03:10:12 PM PDT 24
Finished Apr 30 03:13:15 PM PDT 24
Peak memory 191260 kb
Host smart-313b55b9-3eea-448f-9633-7418551fd26f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012710582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1012710582
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.510122305
Short name T65
Test name
Test status
Simulation time 431589657829 ps
CPU time 143.65 seconds
Started Apr 30 03:10:13 PM PDT 24
Finished Apr 30 03:12:37 PM PDT 24
Peak memory 191232 kb
Host smart-1b552a59-251a-4743-ae0d-9581eeeeb016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510122305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.510122305
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.859903741
Short name T145
Test name
Test status
Simulation time 509568431761 ps
CPU time 217.73 seconds
Started Apr 30 03:10:12 PM PDT 24
Finished Apr 30 03:13:50 PM PDT 24
Peak memory 191216 kb
Host smart-ab729f28-00e0-4004-9724-951036d8c4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859903741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.859903741
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3031754515
Short name T329
Test name
Test status
Simulation time 19163980744 ps
CPU time 31.27 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:08:50 PM PDT 24
Peak memory 183076 kb
Host smart-3df74b45-b1ef-4067-afe8-3ee2b07f8781
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031754515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3031754515
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2523614593
Short name T380
Test name
Test status
Simulation time 180549729416 ps
CPU time 76.07 seconds
Started Apr 30 03:08:07 PM PDT 24
Finished Apr 30 03:09:23 PM PDT 24
Peak memory 182844 kb
Host smart-4261c883-83ee-4a48-b1be-d8c1f4ec85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523614593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2523614593
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3883069462
Short name T327
Test name
Test status
Simulation time 733656502663 ps
CPU time 278 seconds
Started Apr 30 03:08:17 PM PDT 24
Finished Apr 30 03:12:56 PM PDT 24
Peak memory 191256 kb
Host smart-4afa665e-10c8-48cb-8ec7-18d8209d6922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883069462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3883069462
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.1801284170
Short name T182
Test name
Test status
Simulation time 33849392010 ps
CPU time 56.45 seconds
Started Apr 30 03:10:15 PM PDT 24
Finished Apr 30 03:11:12 PM PDT 24
Peak memory 192328 kb
Host smart-8794c6c0-3e25-4364-9935-4fb9f22644fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801284170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1801284170
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1768321223
Short name T232
Test name
Test status
Simulation time 238688146471 ps
CPU time 1164.77 seconds
Started Apr 30 03:10:14 PM PDT 24
Finished Apr 30 03:29:39 PM PDT 24
Peak memory 191244 kb
Host smart-4ad42ea3-e40b-4a54-8fcc-2ee3ceb2b80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768321223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1768321223
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1976452739
Short name T292
Test name
Test status
Simulation time 780903659235 ps
CPU time 329.43 seconds
Started Apr 30 03:10:19 PM PDT 24
Finished Apr 30 03:15:49 PM PDT 24
Peak memory 191280 kb
Host smart-cc9d701a-f852-4e9f-93f8-e8dcbc76f151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976452739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1976452739
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2776135322
Short name T8
Test name
Test status
Simulation time 69824038868 ps
CPU time 141.43 seconds
Started Apr 30 03:10:19 PM PDT 24
Finished Apr 30 03:12:41 PM PDT 24
Peak memory 191244 kb
Host smart-b57b7703-0ae2-4ef0-9d23-1febc3497824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776135322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2776135322
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2721648578
Short name T322
Test name
Test status
Simulation time 28675375450 ps
CPU time 48.39 seconds
Started Apr 30 03:10:20 PM PDT 24
Finished Apr 30 03:11:09 PM PDT 24
Peak memory 183068 kb
Host smart-6357d4ea-6a46-4bae-85c5-8e591b2783e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721648578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2721648578
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2334761867
Short name T3
Test name
Test status
Simulation time 336990558562 ps
CPU time 159.33 seconds
Started Apr 30 03:10:18 PM PDT 24
Finished Apr 30 03:12:58 PM PDT 24
Peak memory 191272 kb
Host smart-c270153d-8138-4835-899e-b4324b9eaefb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334761867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2334761867
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2394190924
Short name T151
Test name
Test status
Simulation time 15146021543 ps
CPU time 76.17 seconds
Started Apr 30 03:10:19 PM PDT 24
Finished Apr 30 03:11:35 PM PDT 24
Peak memory 191432 kb
Host smart-6ab00287-9b77-4da5-b60f-08e56a82b6da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394190924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2394190924
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1849614113
Short name T195
Test name
Test status
Simulation time 17567384643 ps
CPU time 130.09 seconds
Started Apr 30 03:10:19 PM PDT 24
Finished Apr 30 03:12:30 PM PDT 24
Peak memory 183036 kb
Host smart-80335345-485b-416e-8b2e-4bf469fdeac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849614113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1849614113
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2235105038
Short name T175
Test name
Test status
Simulation time 66526815780 ps
CPU time 107.6 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:09:53 PM PDT 24
Peak memory 183008 kb
Host smart-1b384a4e-2caa-4f7d-83b7-07ed01b61e3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235105038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2235105038
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.924836216
Short name T375
Test name
Test status
Simulation time 148731397999 ps
CPU time 121.27 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:10:20 PM PDT 24
Peak memory 183060 kb
Host smart-6a15451f-a1f1-4ec5-8358-170e79eb0906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924836216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.924836216
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.528844923
Short name T221
Test name
Test status
Simulation time 181600728103 ps
CPU time 887.95 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:22:53 PM PDT 24
Peak memory 191232 kb
Host smart-e8b832ae-6594-44b5-a2b0-51f82cb3f317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528844923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.528844923
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.487979232
Short name T399
Test name
Test status
Simulation time 24112072184 ps
CPU time 37.03 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:08:42 PM PDT 24
Peak memory 182944 kb
Host smart-6e741ee0-9fbf-4186-9d88-99b79032612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487979232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.487979232
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.1851218818
Short name T455
Test name
Test status
Simulation time 39455876031 ps
CPU time 412.03 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:14:57 PM PDT 24
Peak memory 205820 kb
Host smart-3067ece7-65b0-436b-9200-54a8c08e2cde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851218818 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.1851218818
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.800899572
Short name T213
Test name
Test status
Simulation time 289467564891 ps
CPU time 214.44 seconds
Started Apr 30 03:10:18 PM PDT 24
Finished Apr 30 03:13:53 PM PDT 24
Peak memory 191184 kb
Host smart-cdfc5327-6bde-4182-bcf6-738c4cbd5b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800899572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.800899572
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.955981208
Short name T305
Test name
Test status
Simulation time 15631477542 ps
CPU time 132.08 seconds
Started Apr 30 03:10:18 PM PDT 24
Finished Apr 30 03:12:30 PM PDT 24
Peak memory 183036 kb
Host smart-e99c6118-1ac4-44d6-8202-616c3c791ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955981208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.955981208
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2724930007
Short name T207
Test name
Test status
Simulation time 45880178638 ps
CPU time 319.5 seconds
Started Apr 30 03:10:25 PM PDT 24
Finished Apr 30 03:15:45 PM PDT 24
Peak memory 191196 kb
Host smart-bf473915-e852-47c0-bb7f-27ea257258da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724930007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2724930007
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1658538966
Short name T293
Test name
Test status
Simulation time 1180460961 ps
CPU time 2.63 seconds
Started Apr 30 03:10:25 PM PDT 24
Finished Apr 30 03:10:28 PM PDT 24
Peak memory 182876 kb
Host smart-8e046a95-d0ed-43d7-84cc-324ea2ba48f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658538966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1658538966
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1609731700
Short name T67
Test name
Test status
Simulation time 409822474365 ps
CPU time 231.12 seconds
Started Apr 30 03:10:25 PM PDT 24
Finished Apr 30 03:14:16 PM PDT 24
Peak memory 191288 kb
Host smart-2126d3d3-39a6-40e7-9c8a-e2632d931622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609731700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1609731700
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2132676211
Short name T291
Test name
Test status
Simulation time 31036328618 ps
CPU time 49.41 seconds
Started Apr 30 03:10:30 PM PDT 24
Finished Apr 30 03:11:20 PM PDT 24
Peak memory 183072 kb
Host smart-c3c0f96b-ed52-42d6-93bf-de1ae6376fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132676211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2132676211
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.663140295
Short name T445
Test name
Test status
Simulation time 249191502765 ps
CPU time 419.75 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:15:04 PM PDT 24
Peak memory 182988 kb
Host smart-64c63b27-c47a-435f-9dc2-2f1a5a71876d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663140295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.663140295
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1771400539
Short name T374
Test name
Test status
Simulation time 69102775520 ps
CPU time 49.5 seconds
Started Apr 30 03:08:10 PM PDT 24
Finished Apr 30 03:09:00 PM PDT 24
Peak memory 183060 kb
Host smart-6b2ca6ef-1922-4ccd-b865-dc3b260cc081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771400539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1771400539
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3724472036
Short name T415
Test name
Test status
Simulation time 107117147505 ps
CPU time 189.72 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:11:29 PM PDT 24
Peak memory 191256 kb
Host smart-fb0e24e8-b3ba-4581-bd1c-9e20173fb244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724472036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3724472036
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1458591766
Short name T199
Test name
Test status
Simulation time 51677838851 ps
CPU time 144.38 seconds
Started Apr 30 03:08:03 PM PDT 24
Finished Apr 30 03:10:28 PM PDT 24
Peak memory 191280 kb
Host smart-846947b6-5c65-4025-904d-bab5c8e3b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458591766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1458591766
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.953551508
Short name T11
Test name
Test status
Simulation time 268308987545 ps
CPU time 152.57 seconds
Started Apr 30 03:08:05 PM PDT 24
Finished Apr 30 03:10:39 PM PDT 24
Peak memory 191216 kb
Host smart-d583a21a-e357-446a-96f6-e1b236fd2f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953551508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
953551508
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1247009672
Short name T226
Test name
Test status
Simulation time 95444791929 ps
CPU time 932.5 seconds
Started Apr 30 03:10:31 PM PDT 24
Finished Apr 30 03:26:04 PM PDT 24
Peak memory 191228 kb
Host smart-65cf0aaf-01ce-4597-9e0c-ba23a80dfc79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247009672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1247009672
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1350315207
Short name T83
Test name
Test status
Simulation time 430579198785 ps
CPU time 989.04 seconds
Started Apr 30 03:10:37 PM PDT 24
Finished Apr 30 03:27:06 PM PDT 24
Peak memory 194016 kb
Host smart-932024fc-74bf-4f60-9871-006ce611bc1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350315207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1350315207
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2174813300
Short name T214
Test name
Test status
Simulation time 231825181659 ps
CPU time 141.95 seconds
Started Apr 30 03:10:30 PM PDT 24
Finished Apr 30 03:12:53 PM PDT 24
Peak memory 191276 kb
Host smart-cac299dd-2526-47fc-84e8-ea8446881bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174813300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2174813300
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1508122338
Short name T1
Test name
Test status
Simulation time 173489766740 ps
CPU time 120.6 seconds
Started Apr 30 03:10:31 PM PDT 24
Finished Apr 30 03:12:32 PM PDT 24
Peak memory 191224 kb
Host smart-62463daf-15c4-46ce-8f13-43a19d965907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508122338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1508122338
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2882070914
Short name T276
Test name
Test status
Simulation time 104465089381 ps
CPU time 175.24 seconds
Started Apr 30 03:10:30 PM PDT 24
Finished Apr 30 03:13:26 PM PDT 24
Peak memory 191228 kb
Host smart-0112d06d-47bd-40a6-828e-0427b2fab2a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882070914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2882070914
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3551999193
Short name T343
Test name
Test status
Simulation time 96516380849 ps
CPU time 89.9 seconds
Started Apr 30 03:10:32 PM PDT 24
Finished Apr 30 03:12:03 PM PDT 24
Peak memory 183064 kb
Host smart-1b86c647-7484-4496-839f-3a314920d8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551999193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3551999193
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.621962055
Short name T318
Test name
Test status
Simulation time 31628715377 ps
CPU time 48.63 seconds
Started Apr 30 03:10:32 PM PDT 24
Finished Apr 30 03:11:21 PM PDT 24
Peak memory 182916 kb
Host smart-04a6c0a5-195d-411d-8774-0f8818655541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621962055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.621962055
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3398426130
Short name T422
Test name
Test status
Simulation time 128942337774 ps
CPU time 298.96 seconds
Started Apr 30 03:10:31 PM PDT 24
Finished Apr 30 03:15:31 PM PDT 24
Peak memory 191244 kb
Host smart-3675b4a5-e75a-4453-b5a4-d4469ad10ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398426130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3398426130
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3671849531
Short name T184
Test name
Test status
Simulation time 115956426620 ps
CPU time 109.96 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:10:02 PM PDT 24
Peak memory 183028 kb
Host smart-419cc436-4f0a-4b53-aedc-fd3b65d6745f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671849531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3671849531
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1704090628
Short name T427
Test name
Test status
Simulation time 141865029158 ps
CPU time 53.31 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:09:05 PM PDT 24
Peak memory 183016 kb
Host smart-6af2f682-00e9-44ed-b4a1-63d1780b6693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704090628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1704090628
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/171.rv_timer_random.1549186768
Short name T435
Test name
Test status
Simulation time 71334732955 ps
CPU time 259.46 seconds
Started Apr 30 03:10:37 PM PDT 24
Finished Apr 30 03:14:57 PM PDT 24
Peak memory 191240 kb
Host smart-6268e008-6c15-4797-8b64-93a2a46388d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549186768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1549186768
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1998971318
Short name T122
Test name
Test status
Simulation time 173730989552 ps
CPU time 197.66 seconds
Started Apr 30 03:10:32 PM PDT 24
Finished Apr 30 03:13:51 PM PDT 24
Peak memory 191240 kb
Host smart-59adfd14-ab06-40bd-9498-54cd86545d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998971318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1998971318
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1727189455
Short name T185
Test name
Test status
Simulation time 90973175990 ps
CPU time 214.74 seconds
Started Apr 30 03:10:34 PM PDT 24
Finished Apr 30 03:14:10 PM PDT 24
Peak memory 191228 kb
Host smart-990213bb-1b83-4039-a399-5463a07be4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727189455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1727189455
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.686653758
Short name T206
Test name
Test status
Simulation time 442691004295 ps
CPU time 820.8 seconds
Started Apr 30 03:10:31 PM PDT 24
Finished Apr 30 03:24:13 PM PDT 24
Peak memory 191264 kb
Host smart-912cd0c1-4431-46d8-9504-037d8d805cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686653758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.686653758
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.387163604
Short name T255
Test name
Test status
Simulation time 69280087019 ps
CPU time 81.49 seconds
Started Apr 30 03:10:39 PM PDT 24
Finished Apr 30 03:12:01 PM PDT 24
Peak memory 183068 kb
Host smart-e4ba2538-e987-45de-9af9-e950eebaf635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387163604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.387163604
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.50680607
Short name T117
Test name
Test status
Simulation time 3553248129524 ps
CPU time 863.17 seconds
Started Apr 30 03:08:15 PM PDT 24
Finished Apr 30 03:22:39 PM PDT 24
Peak memory 183068 kb
Host smart-90a7f2dd-0c26-4b31-be07-fcbff1c8ce4a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50680607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.rv_timer_cfg_update_on_fly.50680607
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2617839398
Short name T434
Test name
Test status
Simulation time 195344042692 ps
CPU time 88.89 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:09:43 PM PDT 24
Peak memory 183028 kb
Host smart-c11198c7-7243-4d2a-9d99-164610baa619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617839398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2617839398
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.456396566
Short name T401
Test name
Test status
Simulation time 7958577978 ps
CPU time 14.35 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:08:27 PM PDT 24
Peak memory 183024 kb
Host smart-f0230a95-fbc6-4c12-984c-566af6baf271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456396566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.456396566
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1427868587
Short name T364
Test name
Test status
Simulation time 96736751774 ps
CPU time 134.73 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:10:28 PM PDT 24
Peak memory 191244 kb
Host smart-1d67d37c-1bdc-43f4-8e5d-c6df9e80590d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427868587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1427868587
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.1263291389
Short name T290
Test name
Test status
Simulation time 254637141741 ps
CPU time 131.02 seconds
Started Apr 30 03:10:37 PM PDT 24
Finished Apr 30 03:12:49 PM PDT 24
Peak memory 191292 kb
Host smart-c7b174a7-2012-4bd9-8716-20f3de57a338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263291389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1263291389
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.398343989
Short name T338
Test name
Test status
Simulation time 132030014048 ps
CPU time 208.68 seconds
Started Apr 30 03:10:38 PM PDT 24
Finished Apr 30 03:14:07 PM PDT 24
Peak memory 191212 kb
Host smart-c1548a28-2358-485b-ae2e-48d266b6a9e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398343989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.398343989
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1897562079
Short name T326
Test name
Test status
Simulation time 6345700957 ps
CPU time 68.81 seconds
Started Apr 30 03:10:37 PM PDT 24
Finished Apr 30 03:11:47 PM PDT 24
Peak memory 183060 kb
Host smart-d5488394-8c56-42bc-aa4e-f00cb9885604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897562079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1897562079
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.4218191472
Short name T220
Test name
Test status
Simulation time 37055353696 ps
CPU time 90.76 seconds
Started Apr 30 03:10:44 PM PDT 24
Finished Apr 30 03:12:15 PM PDT 24
Peak memory 191272 kb
Host smart-f266e685-5e69-4c4e-82b1-d931a03f2dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218191472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.4218191472
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2280272269
Short name T240
Test name
Test status
Simulation time 521292763214 ps
CPU time 1108.14 seconds
Started Apr 30 03:10:44 PM PDT 24
Finished Apr 30 03:29:13 PM PDT 24
Peak memory 191256 kb
Host smart-2d4bfa92-f5ae-4307-8b3c-ea088e635adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280272269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2280272269
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3444753628
Short name T68
Test name
Test status
Simulation time 234845176374 ps
CPU time 136.91 seconds
Started Apr 30 03:10:43 PM PDT 24
Finished Apr 30 03:13:00 PM PDT 24
Peak memory 191248 kb
Host smart-e331557f-e3e5-404f-83e9-7aa8bf4ac2a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444753628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3444753628
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4076640892
Short name T173
Test name
Test status
Simulation time 151022548280 ps
CPU time 143.55 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:10:36 PM PDT 24
Peak memory 183116 kb
Host smart-57078720-082a-4663-820f-c8f45dc21886
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076640892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4076640892
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.4046725704
Short name T392
Test name
Test status
Simulation time 70812204571 ps
CPU time 105.38 seconds
Started Apr 30 03:08:17 PM PDT 24
Finished Apr 30 03:10:03 PM PDT 24
Peak memory 182996 kb
Host smart-864125f0-2c5d-4a41-b973-b6de22bdf453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046725704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4046725704
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.435071220
Short name T50
Test name
Test status
Simulation time 36802373575 ps
CPU time 161.98 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:10:55 PM PDT 24
Peak memory 197704 kb
Host smart-8a699145-c112-4f4f-a471-4742f5b4edee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435071220 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.435071220
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.rv_timer_random.3508157734
Short name T114
Test name
Test status
Simulation time 380190591681 ps
CPU time 679.57 seconds
Started Apr 30 03:10:44 PM PDT 24
Finished Apr 30 03:22:04 PM PDT 24
Peak memory 191212 kb
Host smart-9151fca3-6e14-4d9f-8d9d-afcc6f068bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508157734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3508157734
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.228224200
Short name T183
Test name
Test status
Simulation time 333992696566 ps
CPU time 74.13 seconds
Started Apr 30 03:10:45 PM PDT 24
Finished Apr 30 03:12:00 PM PDT 24
Peak memory 191260 kb
Host smart-23f781fb-9df4-4e7d-a952-a0de13847cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228224200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.228224200
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3792157573
Short name T354
Test name
Test status
Simulation time 50126207413 ps
CPU time 42.95 seconds
Started Apr 30 03:10:41 PM PDT 24
Finished Apr 30 03:11:25 PM PDT 24
Peak memory 191192 kb
Host smart-d014d6cd-598a-4cf3-a28d-ea86f9d70129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792157573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3792157573
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2454335276
Short name T264
Test name
Test status
Simulation time 1098520264821 ps
CPU time 281.59 seconds
Started Apr 30 03:10:46 PM PDT 24
Finished Apr 30 03:15:28 PM PDT 24
Peak memory 191216 kb
Host smart-bd5712ca-79ac-4626-a5fe-d8b1d63c4038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454335276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2454335276
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3072847516
Short name T450
Test name
Test status
Simulation time 245709490591 ps
CPU time 354.92 seconds
Started Apr 30 03:10:45 PM PDT 24
Finished Apr 30 03:16:40 PM PDT 24
Peak memory 191260 kb
Host smart-fa685746-85ad-49be-b409-66ff06a1c349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072847516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3072847516
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3729148396
Short name T123
Test name
Test status
Simulation time 76160076269 ps
CPU time 173.47 seconds
Started Apr 30 03:10:48 PM PDT 24
Finished Apr 30 03:13:42 PM PDT 24
Peak memory 191252 kb
Host smart-a20d02f1-0200-4ef6-b980-a029584746de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729148396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3729148396
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1789778054
Short name T194
Test name
Test status
Simulation time 592350366343 ps
CPU time 978.55 seconds
Started Apr 30 03:07:43 PM PDT 24
Finished Apr 30 03:24:03 PM PDT 24
Peak memory 183016 kb
Host smart-88b7e90c-8c3c-4556-88b6-7ec711a3836b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789778054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1789778054
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1551854707
Short name T419
Test name
Test status
Simulation time 76806244549 ps
CPU time 32.65 seconds
Started Apr 30 03:07:47 PM PDT 24
Finished Apr 30 03:08:21 PM PDT 24
Peak memory 183052 kb
Host smart-2c2b4a94-7c94-43af-9ad2-191f6920446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551854707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1551854707
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3896060238
Short name T403
Test name
Test status
Simulation time 56230064563 ps
CPU time 220.52 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:11:27 PM PDT 24
Peak memory 183068 kb
Host smart-3408ea4f-6c3f-4a63-85a0-b81d876fd5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896060238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3896060238
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.966939973
Short name T152
Test name
Test status
Simulation time 22657467423 ps
CPU time 19.87 seconds
Started Apr 30 03:07:46 PM PDT 24
Finished Apr 30 03:08:07 PM PDT 24
Peak memory 182852 kb
Host smart-acf6aa1a-ebd5-426a-bf3c-9bcf195a26bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966939973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.966939973
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3322229586
Short name T21
Test name
Test status
Simulation time 230174232 ps
CPU time 0.82 seconds
Started Apr 30 03:07:45 PM PDT 24
Finished Apr 30 03:07:47 PM PDT 24
Peak memory 214092 kb
Host smart-9aa48e1a-cf3c-404c-aac8-b1b852dea372
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322229586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3322229586
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.139929273
Short name T66
Test name
Test status
Simulation time 21956888495 ps
CPU time 7.51 seconds
Started Apr 30 03:08:15 PM PDT 24
Finished Apr 30 03:08:23 PM PDT 24
Peak memory 183044 kb
Host smart-e068e03f-251f-4016-aa01-fea830153ae4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139929273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.139929273
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1831544709
Short name T45
Test name
Test status
Simulation time 151097031145 ps
CPU time 69.56 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:09:24 PM PDT 24
Peak memory 183024 kb
Host smart-e67b1eb1-8417-42a8-82e9-92c17d2ee88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831544709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1831544709
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2177208494
Short name T452
Test name
Test status
Simulation time 137150279161 ps
CPU time 79.91 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:09:32 PM PDT 24
Peak memory 191256 kb
Host smart-5603bd66-0f32-4b5e-826f-f6c689d11b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177208494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2177208494
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.406673732
Short name T285
Test name
Test status
Simulation time 97819534492 ps
CPU time 141.66 seconds
Started Apr 30 03:08:10 PM PDT 24
Finished Apr 30 03:10:32 PM PDT 24
Peak memory 191232 kb
Host smart-91da4df3-50dc-4690-93f8-d401b09c502a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406673732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
406673732
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3309303758
Short name T316
Test name
Test status
Simulation time 59232275230 ps
CPU time 100.83 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:09:52 PM PDT 24
Peak memory 183000 kb
Host smart-55eabaad-7ff2-423a-87a4-502524b09128
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309303758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3309303758
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1228332908
Short name T433
Test name
Test status
Simulation time 11940984671 ps
CPU time 9.57 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:08:24 PM PDT 24
Peak memory 183080 kb
Host smart-8d4cf3c8-33df-4c54-a866-d9153578a025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228332908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1228332908
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2597071010
Short name T202
Test name
Test status
Simulation time 579868512270 ps
CPU time 554.56 seconds
Started Apr 30 03:08:14 PM PDT 24
Finished Apr 30 03:17:29 PM PDT 24
Peak memory 191276 kb
Host smart-0f828a04-dd3d-4e26-b926-9aa490a4e2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597071010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2597071010
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1472348988
Short name T4
Test name
Test status
Simulation time 7234319497 ps
CPU time 11.08 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:08:24 PM PDT 24
Peak memory 191156 kb
Host smart-be333e86-5e15-4d2a-88b7-b5afa983ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472348988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1472348988
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.4076198368
Short name T42
Test name
Test status
Simulation time 79357705163 ps
CPU time 868.31 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:22:42 PM PDT 24
Peak memory 214092 kb
Host smart-5fb3dc67-620c-4dd7-946f-5799cd5f38b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076198368 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.4076198368
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1223912970
Short name T382
Test name
Test status
Simulation time 156106548145 ps
CPU time 138.33 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:10:31 PM PDT 24
Peak memory 183032 kb
Host smart-4d274fd0-3b64-42d1-a25a-fb37ffcc1615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223912970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1223912970
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1868608894
Short name T196
Test name
Test status
Simulation time 115238727734 ps
CPU time 110.52 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:10:05 PM PDT 24
Peak memory 191268 kb
Host smart-b949a9ed-d321-4a72-befe-a45bc765592f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868608894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1868608894
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1790716102
Short name T160
Test name
Test status
Simulation time 71706174565 ps
CPU time 733.39 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:20:27 PM PDT 24
Peak memory 183040 kb
Host smart-6c037aab-ba19-4687-a221-dc3477bede72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790716102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1790716102
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1428862852
Short name T174
Test name
Test status
Simulation time 7133308513283 ps
CPU time 1633.99 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:35:28 PM PDT 24
Peak memory 195720 kb
Host smart-5d6521b7-5c49-47ea-a074-bb4fa257f6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428862852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1428862852
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3190975215
Short name T420
Test name
Test status
Simulation time 168199028355 ps
CPU time 111.53 seconds
Started Apr 30 03:08:13 PM PDT 24
Finished Apr 30 03:10:05 PM PDT 24
Peak memory 183080 kb
Host smart-cf0b3475-0c82-4c56-9db7-d863f10bcd32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190975215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3190975215
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1937899218
Short name T391
Test name
Test status
Simulation time 39994694843 ps
CPU time 61.12 seconds
Started Apr 30 03:08:15 PM PDT 24
Finished Apr 30 03:09:17 PM PDT 24
Peak memory 183036 kb
Host smart-f5252ec3-1928-464f-b5f6-f65e6cd05027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937899218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1937899218
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2029076516
Short name T443
Test name
Test status
Simulation time 184363393665 ps
CPU time 847.6 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:22:20 PM PDT 24
Peak memory 183020 kb
Host smart-2221726f-fdcd-4a15-85ae-84734a297070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029076516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2029076516
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4169574862
Short name T303
Test name
Test status
Simulation time 50090529618 ps
CPU time 78.45 seconds
Started Apr 30 03:08:09 PM PDT 24
Finished Apr 30 03:09:28 PM PDT 24
Peak memory 183044 kb
Host smart-28317bc8-4534-4295-bffe-545afc957b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169574862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4169574862
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3854907095
Short name T366
Test name
Test status
Simulation time 315733371902 ps
CPU time 241.46 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:12:14 PM PDT 24
Peak memory 194000 kb
Host smart-5ae41ef2-15b6-45d9-ab19-66618788a272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854907095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3854907095
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2010451755
Short name T423
Test name
Test status
Simulation time 269249898830 ps
CPU time 152.53 seconds
Started Apr 30 03:08:15 PM PDT 24
Finished Apr 30 03:10:48 PM PDT 24
Peak memory 183048 kb
Host smart-51f7ab7f-de6c-4215-b60e-ad17ead3a252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010451755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2010451755
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.494875552
Short name T368
Test name
Test status
Simulation time 102870927 ps
CPU time 0.6 seconds
Started Apr 30 03:08:11 PM PDT 24
Finished Apr 30 03:08:12 PM PDT 24
Peak memory 182784 kb
Host smart-b271f098-21ab-41cb-8676-5eaf12d423d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494875552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.494875552
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1457185578
Short name T409
Test name
Test status
Simulation time 102335666238 ps
CPU time 147.44 seconds
Started Apr 30 03:08:15 PM PDT 24
Finished Apr 30 03:10:42 PM PDT 24
Peak memory 183056 kb
Host smart-5eddf272-8945-4b8c-a78e-35728a3a8dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457185578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1457185578
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2562424156
Short name T241
Test name
Test status
Simulation time 4962534668 ps
CPU time 2.78 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:08:16 PM PDT 24
Peak memory 183048 kb
Host smart-53b0787e-ec8b-42de-b9c3-db5ebe1c1294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562424156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2562424156
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2288298654
Short name T315
Test name
Test status
Simulation time 191135272488 ps
CPU time 88.74 seconds
Started Apr 30 03:08:12 PM PDT 24
Finished Apr 30 03:09:42 PM PDT 24
Peak memory 195132 kb
Host smart-f47e12fd-b9d9-4c82-9922-62fd6f311296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288298654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2288298654
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3825603893
Short name T14
Test name
Test status
Simulation time 694735581428 ps
CPU time 314.95 seconds
Started Apr 30 03:08:21 PM PDT 24
Finished Apr 30 03:13:36 PM PDT 24
Peak memory 183072 kb
Host smart-944952ea-afa3-48d6-bd58-b7168e0bd782
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825603893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3825603893
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3168663576
Short name T444
Test name
Test status
Simulation time 3312463780 ps
CPU time 5.58 seconds
Started Apr 30 03:08:19 PM PDT 24
Finished Apr 30 03:08:25 PM PDT 24
Peak memory 182840 kb
Host smart-b29ee571-156b-43fe-9916-b300fc4bea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168663576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3168663576
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.4051797633
Short name T417
Test name
Test status
Simulation time 3286542170 ps
CPU time 2.33 seconds
Started Apr 30 03:08:21 PM PDT 24
Finished Apr 30 03:08:24 PM PDT 24
Peak memory 182836 kb
Host smart-c462e2e5-a25e-4e7e-9112-fd18e1b461c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051797633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.4051797633
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3896863174
Short name T262
Test name
Test status
Simulation time 20512569111 ps
CPU time 345.78 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:14:06 PM PDT 24
Peak memory 183104 kb
Host smart-8b1ea371-9f4f-4df1-b018-2227571a03ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896863174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3896863174
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1831881847
Short name T198
Test name
Test status
Simulation time 207517544288 ps
CPU time 1117.44 seconds
Started Apr 30 03:08:22 PM PDT 24
Finished Apr 30 03:27:00 PM PDT 24
Peak memory 194780 kb
Host smart-db0c4414-7e45-4694-b146-305f3d9007b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831881847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1831881847
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.355811088
Short name T261
Test name
Test status
Simulation time 2180409494302 ps
CPU time 662.69 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:19:24 PM PDT 24
Peak memory 183064 kb
Host smart-7ed875f9-d134-451b-b89a-82fd3f077806
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355811088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.355811088
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1177500521
Short name T89
Test name
Test status
Simulation time 110320815298 ps
CPU time 147.24 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:10:46 PM PDT 24
Peak memory 183008 kb
Host smart-3697527a-be89-4267-8630-a2db140fbe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177500521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1177500521
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.93305978
Short name T266
Test name
Test status
Simulation time 103759562043 ps
CPU time 201.12 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:11:40 PM PDT 24
Peak memory 183096 kb
Host smart-cc13f409-4b1e-49a6-bab3-287e4c238186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93305978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.93305978
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2063087689
Short name T235
Test name
Test status
Simulation time 743440318737 ps
CPU time 372.5 seconds
Started Apr 30 03:08:24 PM PDT 24
Finished Apr 30 03:14:38 PM PDT 24
Peak memory 183108 kb
Host smart-04ebd4eb-b694-4f9a-8b58-08f869f7c4f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063087689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2063087689
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3007399757
Short name T378
Test name
Test status
Simulation time 117557179073 ps
CPU time 53.54 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:09:14 PM PDT 24
Peak memory 183032 kb
Host smart-b8425efe-bca8-4c20-9458-9d822902e9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007399757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3007399757
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1390072833
Short name T299
Test name
Test status
Simulation time 735795463304 ps
CPU time 404.56 seconds
Started Apr 30 03:08:17 PM PDT 24
Finished Apr 30 03:15:02 PM PDT 24
Peak memory 191276 kb
Host smart-43b9fb4c-0962-4df2-8be3-ae07203292e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390072833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1390072833
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3092857161
Short name T253
Test name
Test status
Simulation time 159144941272 ps
CPU time 266.28 seconds
Started Apr 30 03:08:21 PM PDT 24
Finished Apr 30 03:12:48 PM PDT 24
Peak memory 183040 kb
Host smart-c7e78392-cc20-4b18-924e-696db7a0d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092857161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3092857161
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2545193673
Short name T396
Test name
Test status
Simulation time 112612624502 ps
CPU time 93.86 seconds
Started Apr 30 03:08:21 PM PDT 24
Finished Apr 30 03:09:56 PM PDT 24
Peak memory 183060 kb
Host smart-530061a5-b075-4229-a3b6-3da8cb815cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545193673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2545193673
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2184961920
Short name T301
Test name
Test status
Simulation time 191792718742 ps
CPU time 173.75 seconds
Started Apr 30 03:08:17 PM PDT 24
Finished Apr 30 03:11:12 PM PDT 24
Peak memory 191244 kb
Host smart-20bbe8b2-33f3-467c-9bc7-c6b3c1bbd12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184961920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2184961920
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.355751686
Short name T381
Test name
Test status
Simulation time 14122537640 ps
CPU time 15.69 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:08:36 PM PDT 24
Peak memory 183052 kb
Host smart-485d437b-a9b5-444b-84d9-c0439899a623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355751686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.355751686
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1267162558
Short name T63
Test name
Test status
Simulation time 1828481248459 ps
CPU time 1140.71 seconds
Started Apr 30 03:08:19 PM PDT 24
Finished Apr 30 03:27:21 PM PDT 24
Peak memory 191180 kb
Host smart-afa8fdeb-7d44-4be0-b8db-4133bacca25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267162558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1267162558
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4290631905
Short name T187
Test name
Test status
Simulation time 123458523196 ps
CPU time 223.56 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:11:35 PM PDT 24
Peak memory 183084 kb
Host smart-587dac08-b9cc-4821-9cbe-7c939cff74e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290631905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4290631905
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1607557494
Short name T454
Test name
Test status
Simulation time 320398475590 ps
CPU time 131.68 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:10:02 PM PDT 24
Peak memory 183080 kb
Host smart-5dd536a6-5d69-4ce8-81c6-524dacb662e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607557494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1607557494
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1168435111
Short name T306
Test name
Test status
Simulation time 333775944794 ps
CPU time 1306.04 seconds
Started Apr 30 03:07:51 PM PDT 24
Finished Apr 30 03:29:38 PM PDT 24
Peak memory 191204 kb
Host smart-c5f30182-797e-4f0c-9030-700c34f2c011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168435111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1168435111
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2695273763
Short name T451
Test name
Test status
Simulation time 62223656 ps
CPU time 0.67 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:07:51 PM PDT 24
Peak memory 191568 kb
Host smart-630b2abb-0576-4ef1-9da0-b6e370cda4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695273763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2695273763
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.673499758
Short name T20
Test name
Test status
Simulation time 249998066 ps
CPU time 0.92 seconds
Started Apr 30 03:07:52 PM PDT 24
Finished Apr 30 03:07:54 PM PDT 24
Peak memory 213524 kb
Host smart-5eefb45c-2894-4a70-b976-3be6f3b92f92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673499758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.673499758
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3752823435
Short name T258
Test name
Test status
Simulation time 114331664901 ps
CPU time 229.05 seconds
Started Apr 30 03:07:52 PM PDT 24
Finished Apr 30 03:11:42 PM PDT 24
Peak memory 191248 kb
Host smart-b6d8c445-6cd4-46d7-be37-abcfd5abea2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752823435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3752823435
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2160369664
Short name T222
Test name
Test status
Simulation time 45327659189 ps
CPU time 28.09 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:08:49 PM PDT 24
Peak memory 183024 kb
Host smart-2475932f-edd3-45d1-8253-cc9b96de96d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160369664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2160369664
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3932220007
Short name T371
Test name
Test status
Simulation time 352637086385 ps
CPU time 154.45 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:10:53 PM PDT 24
Peak memory 183000 kb
Host smart-46d54ccf-6abf-477a-9a41-5f71d019580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932220007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3932220007
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2139115605
Short name T248
Test name
Test status
Simulation time 177777929639 ps
CPU time 234.4 seconds
Started Apr 30 03:08:17 PM PDT 24
Finished Apr 30 03:12:12 PM PDT 24
Peak memory 191244 kb
Host smart-a2598565-f4c4-4bcb-b352-739ebd9a169a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139115605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2139115605
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1869015579
Short name T270
Test name
Test status
Simulation time 74564822892 ps
CPU time 119.25 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:10:20 PM PDT 24
Peak memory 190876 kb
Host smart-b873174c-dee4-40a0-9cf9-0161dc5f21ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869015579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1869015579
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2688581197
Short name T170
Test name
Test status
Simulation time 860732665027 ps
CPU time 460.16 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:16:07 PM PDT 24
Peak memory 183112 kb
Host smart-2d24ccd4-0e33-4451-b9ef-ded007d2cbe1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688581197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2688581197
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3839426661
Short name T384
Test name
Test status
Simulation time 681277099390 ps
CPU time 137.13 seconds
Started Apr 30 03:08:18 PM PDT 24
Finished Apr 30 03:10:36 PM PDT 24
Peak memory 183056 kb
Host smart-c633347e-4391-486d-a0d6-0dad6e41e574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839426661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3839426661
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2206873833
Short name T6
Test name
Test status
Simulation time 1364735519649 ps
CPU time 410.57 seconds
Started Apr 30 03:08:17 PM PDT 24
Finished Apr 30 03:15:08 PM PDT 24
Peak memory 191264 kb
Host smart-e187b20d-471b-4010-8739-53d70496ec38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206873833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2206873833
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.705438377
Short name T341
Test name
Test status
Simulation time 19126120490 ps
CPU time 31.71 seconds
Started Apr 30 03:08:19 PM PDT 24
Finished Apr 30 03:08:52 PM PDT 24
Peak memory 194528 kb
Host smart-44328458-2cc3-40fb-b8b3-ed8dc7e84b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705438377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.705438377
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2260000141
Short name T431
Test name
Test status
Simulation time 34714467426 ps
CPU time 126.93 seconds
Started Apr 30 03:08:22 PM PDT 24
Finished Apr 30 03:10:29 PM PDT 24
Peak memory 197652 kb
Host smart-7d84019b-4645-4e4a-a661-170c7dc9035a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260000141 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2260000141
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.205219441
Short name T166
Test name
Test status
Simulation time 979373689136 ps
CPU time 558.48 seconds
Started Apr 30 03:08:23 PM PDT 24
Finished Apr 30 03:17:42 PM PDT 24
Peak memory 183076 kb
Host smart-dbfec50a-8619-4b70-848f-5b547c6609ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205219441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.205219441
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3959362321
Short name T383
Test name
Test status
Simulation time 128547062938 ps
CPU time 50.08 seconds
Started Apr 30 03:08:23 PM PDT 24
Finished Apr 30 03:09:13 PM PDT 24
Peak memory 183072 kb
Host smart-7caefcc1-2120-4409-acd1-e858c5d83bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959362321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3959362321
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2018677689
Short name T111
Test name
Test status
Simulation time 62231979116 ps
CPU time 105.95 seconds
Started Apr 30 03:08:22 PM PDT 24
Finished Apr 30 03:10:09 PM PDT 24
Peak memory 191152 kb
Host smart-1b91ce47-adda-4aa6-92d6-38d3e7a90a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018677689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2018677689
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1908141572
Short name T325
Test name
Test status
Simulation time 536550689327 ps
CPU time 161.16 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:11:02 PM PDT 24
Peak memory 182636 kb
Host smart-8ca8a772-f2c9-4c59-baf1-5cecd91de15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908141572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1908141572
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3677421546
Short name T359
Test name
Test status
Simulation time 101104278994 ps
CPU time 159.69 seconds
Started Apr 30 03:08:24 PM PDT 24
Finished Apr 30 03:11:05 PM PDT 24
Peak memory 183056 kb
Host smart-5b05ce5a-271a-451f-9d0d-87262da2bda6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677421546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3677421546
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3039551590
Short name T372
Test name
Test status
Simulation time 165926651167 ps
CPU time 138.18 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:10:44 PM PDT 24
Peak memory 183088 kb
Host smart-966c4ec7-4277-4ce8-9111-75b6c3272ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039551590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3039551590
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.4184661916
Short name T281
Test name
Test status
Simulation time 122655499165 ps
CPU time 180.78 seconds
Started Apr 30 03:08:20 PM PDT 24
Finished Apr 30 03:11:21 PM PDT 24
Peak memory 191212 kb
Host smart-975d6b79-e59b-4300-bbe3-20467a59a8b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184661916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.4184661916
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2675628663
Short name T161
Test name
Test status
Simulation time 177795061197 ps
CPU time 114.03 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:10:21 PM PDT 24
Peak memory 191276 kb
Host smart-6535b225-52a4-4bc6-9ac4-bcc742e6d188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675628663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2675628663
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.269335414
Short name T271
Test name
Test status
Simulation time 181364714217 ps
CPU time 352.06 seconds
Started Apr 30 03:08:28 PM PDT 24
Finished Apr 30 03:14:20 PM PDT 24
Peak memory 191184 kb
Host smart-b0d7ecb1-62d6-433d-b782-5975f9548957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269335414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
269335414
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.4098490810
Short name T39
Test name
Test status
Simulation time 42710310988 ps
CPU time 409.5 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:15:17 PM PDT 24
Peak memory 205848 kb
Host smart-f975e9c6-c023-4473-9d10-f155efc0d690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098490810 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.4098490810
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.4072510585
Short name T148
Test name
Test status
Simulation time 78160371507 ps
CPU time 39.86 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:09:07 PM PDT 24
Peak memory 183044 kb
Host smart-0758361f-9af7-4525-9131-e44e7064e3d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072510585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.4072510585
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2937487166
Short name T379
Test name
Test status
Simulation time 261570528184 ps
CPU time 52.52 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:09:20 PM PDT 24
Peak memory 183012 kb
Host smart-4ce17955-ea76-494d-a9fa-a27fb0d91e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937487166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2937487166
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1838050358
Short name T121
Test name
Test status
Simulation time 151309703241 ps
CPU time 775.67 seconds
Started Apr 30 03:08:29 PM PDT 24
Finished Apr 30 03:21:25 PM PDT 24
Peak memory 191208 kb
Host smart-d804d993-85aa-4e66-b6e2-d80aff4a1a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838050358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1838050358
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.125497571
Short name T155
Test name
Test status
Simulation time 156690357066 ps
CPU time 440.33 seconds
Started Apr 30 03:08:24 PM PDT 24
Finished Apr 30 03:15:46 PM PDT 24
Peak memory 194708 kb
Host smart-1523c92c-5486-4b1c-bbd2-36b82fe92502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125497571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.125497571
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2088836379
Short name T58
Test name
Test status
Simulation time 588393111089 ps
CPU time 387.87 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:14:55 PM PDT 24
Peak memory 196212 kb
Host smart-315f0db7-4ef6-46ad-b4ba-a541e815f1de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088836379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2088836379
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3909170673
Short name T405
Test name
Test status
Simulation time 99361480039 ps
CPU time 73.55 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:09:41 PM PDT 24
Peak memory 183016 kb
Host smart-1b685863-de51-4fc3-9a62-00b3f23c1b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909170673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3909170673
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.4211172695
Short name T190
Test name
Test status
Simulation time 811695883160 ps
CPU time 1112.17 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:27:00 PM PDT 24
Peak memory 191256 kb
Host smart-ae872a56-9f90-4256-a74c-6864262dd0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211172695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4211172695
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1651658156
Short name T387
Test name
Test status
Simulation time 8431857912 ps
CPU time 9.07 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:08:36 PM PDT 24
Peak memory 183068 kb
Host smart-56858179-0c1d-40f7-87bc-15d25a23d0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651658156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1651658156
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.2268795179
Short name T101
Test name
Test status
Simulation time 111386658203 ps
CPU time 239.26 seconds
Started Apr 30 03:08:32 PM PDT 24
Finished Apr 30 03:12:32 PM PDT 24
Peak memory 205852 kb
Host smart-b93bbbb6-ffbd-4f17-b715-dbdaa8a6c76b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268795179 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.2268795179
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3813135129
Short name T361
Test name
Test status
Simulation time 1109307637239 ps
CPU time 602.63 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:18:30 PM PDT 24
Peak memory 183016 kb
Host smart-0bce07c0-bf9c-48db-a9c0-a518706964ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813135129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3813135129
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3757834220
Short name T369
Test name
Test status
Simulation time 852511789388 ps
CPU time 343.11 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:14:10 PM PDT 24
Peak memory 183060 kb
Host smart-32356df4-4bd6-43ae-9a24-cbd540d6c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757834220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3757834220
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3422663327
Short name T311
Test name
Test status
Simulation time 50246120506 ps
CPU time 1811.91 seconds
Started Apr 30 03:08:25 PM PDT 24
Finished Apr 30 03:38:39 PM PDT 24
Peak memory 192588 kb
Host smart-eeec761a-81fd-4211-97c7-c12ed00a6fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422663327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3422663327
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2486925059
Short name T234
Test name
Test status
Simulation time 8619721921 ps
CPU time 11.88 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:08:39 PM PDT 24
Peak memory 191232 kb
Host smart-0b7f1385-296e-432b-9b0d-33ea99e2c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486925059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2486925059
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.4280445805
Short name T133
Test name
Test status
Simulation time 622089097335 ps
CPU time 966.61 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:24:34 PM PDT 24
Peak memory 183056 kb
Host smart-f6b97856-a95e-4348-9da9-d75cbb028eaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280445805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.4280445805
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.167015717
Short name T5
Test name
Test status
Simulation time 19781548667 ps
CPU time 30.89 seconds
Started Apr 30 03:08:24 PM PDT 24
Finished Apr 30 03:08:55 PM PDT 24
Peak memory 183000 kb
Host smart-75602038-b17f-4991-9f47-cd8e0efcc5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167015717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.167015717
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3453654781
Short name T247
Test name
Test status
Simulation time 73906793946 ps
CPU time 2031.18 seconds
Started Apr 30 03:08:26 PM PDT 24
Finished Apr 30 03:42:19 PM PDT 24
Peak memory 183004 kb
Host smart-61236a0e-74cc-469f-8b7c-3282a9647344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453654781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3453654781
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1383599023
Short name T125
Test name
Test status
Simulation time 793752142487 ps
CPU time 401.66 seconds
Started Apr 30 03:08:33 PM PDT 24
Finished Apr 30 03:15:15 PM PDT 24
Peak memory 183076 kb
Host smart-7c1b6f95-fae9-4734-98f7-f1b0a7116567
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383599023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1383599023
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.226086247
Short name T416
Test name
Test status
Simulation time 142013310493 ps
CPU time 198.39 seconds
Started Apr 30 03:08:35 PM PDT 24
Finished Apr 30 03:11:54 PM PDT 24
Peak memory 183076 kb
Host smart-80ce64f2-664b-453c-a255-7236c0898375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226086247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.226086247
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3581512114
Short name T127
Test name
Test status
Simulation time 165071599366 ps
CPU time 334.31 seconds
Started Apr 30 03:08:33 PM PDT 24
Finished Apr 30 03:14:08 PM PDT 24
Peak memory 191228 kb
Host smart-0e5ad187-4e51-42d6-ba10-a598c879dc3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581512114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3581512114
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1287549337
Short name T215
Test name
Test status
Simulation time 45245371944 ps
CPU time 59.71 seconds
Started Apr 30 03:08:35 PM PDT 24
Finished Apr 30 03:09:36 PM PDT 24
Peak memory 195188 kb
Host smart-f24dc6d9-78d2-46d8-a762-aaf5a3a29333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287549337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1287549337
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.400452746
Short name T230
Test name
Test status
Simulation time 147441076584 ps
CPU time 355.02 seconds
Started Apr 30 03:08:38 PM PDT 24
Finished Apr 30 03:14:34 PM PDT 24
Peak memory 191180 kb
Host smart-1a235214-c85c-43ca-b25c-1b70fd1e4d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400452746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
400452746
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2174420600
Short name T228
Test name
Test status
Simulation time 379719472197 ps
CPU time 595.8 seconds
Started Apr 30 03:08:34 PM PDT 24
Finished Apr 30 03:18:30 PM PDT 24
Peak memory 183044 kb
Host smart-63f80dd8-3d25-417f-b0fd-2ad3544c039a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174420600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2174420600
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1824985506
Short name T395
Test name
Test status
Simulation time 26382958608 ps
CPU time 36.12 seconds
Started Apr 30 03:08:35 PM PDT 24
Finished Apr 30 03:09:12 PM PDT 24
Peak memory 183008 kb
Host smart-64dbad03-b41b-4988-bc5a-16847a7dda02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824985506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1824985506
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.769313945
Short name T136
Test name
Test status
Simulation time 316296099820 ps
CPU time 177.51 seconds
Started Apr 30 03:08:34 PM PDT 24
Finished Apr 30 03:11:32 PM PDT 24
Peak memory 191212 kb
Host smart-5b267e3e-b99f-4264-94a2-8d3ea84a1787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769313945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.769313945
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1802066610
Short name T426
Test name
Test status
Simulation time 50450019079 ps
CPU time 77.1 seconds
Started Apr 30 03:08:35 PM PDT 24
Finished Apr 30 03:09:53 PM PDT 24
Peak memory 183036 kb
Host smart-6ca52d7f-5330-4122-b1bf-a8a14796ae5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802066610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1802066610
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4090088018
Short name T386
Test name
Test status
Simulation time 128331350911 ps
CPU time 187.57 seconds
Started Apr 30 03:08:35 PM PDT 24
Finished Apr 30 03:11:43 PM PDT 24
Peak memory 194544 kb
Host smart-6eafc5e7-6744-49a3-9319-a86543ab22c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090088018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4090088018
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3470760627
Short name T288
Test name
Test status
Simulation time 97076970097 ps
CPU time 180.77 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:10:51 PM PDT 24
Peak memory 183068 kb
Host smart-1ed7c16b-6d41-464b-9daf-f3d83ea1a70b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470760627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3470760627
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.237968417
Short name T373
Test name
Test status
Simulation time 106026939132 ps
CPU time 113.13 seconds
Started Apr 30 03:07:51 PM PDT 24
Finished Apr 30 03:09:45 PM PDT 24
Peak memory 183076 kb
Host smart-6f342f02-ead0-40ef-b46a-a92b63ece8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237968417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.237968417
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3243193193
Short name T421
Test name
Test status
Simulation time 314497349689 ps
CPU time 132.88 seconds
Started Apr 30 03:07:52 PM PDT 24
Finished Apr 30 03:10:06 PM PDT 24
Peak memory 191280 kb
Host smart-8f2b0f9b-d861-4bee-adfa-64d147124696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243193193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3243193193
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1153858492
Short name T269
Test name
Test status
Simulation time 88275074322 ps
CPU time 1359.54 seconds
Started Apr 30 03:07:51 PM PDT 24
Finished Apr 30 03:30:31 PM PDT 24
Peak memory 191212 kb
Host smart-42e1e0a2-ce77-42e1-bce6-00efb3bab2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153858492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1153858492
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1130751064
Short name T19
Test name
Test status
Simulation time 57530927 ps
CPU time 0.8 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:07:52 PM PDT 24
Peak memory 214260 kb
Host smart-e3aa3d9e-9cba-4934-aba3-ddd5d5567a99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130751064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1130751064
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3681534824
Short name T413
Test name
Test status
Simulation time 37161695 ps
CPU time 0.64 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:07:51 PM PDT 24
Peak memory 182836 kb
Host smart-d1ea64b2-3c25-4a34-b9b8-44637b1d2fb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681534824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3681534824
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4025627950
Short name T227
Test name
Test status
Simulation time 3217183855 ps
CPU time 5.67 seconds
Started Apr 30 03:08:36 PM PDT 24
Finished Apr 30 03:08:42 PM PDT 24
Peak memory 183036 kb
Host smart-b1ba6c7c-addf-40f8-9947-f7ea98374528
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025627950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4025627950
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3688805674
Short name T390
Test name
Test status
Simulation time 549493337176 ps
CPU time 278.75 seconds
Started Apr 30 03:08:35 PM PDT 24
Finished Apr 30 03:13:14 PM PDT 24
Peak memory 182996 kb
Host smart-f9935f08-5484-4773-8ae6-24d752898ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688805674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3688805674
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.121640846
Short name T250
Test name
Test status
Simulation time 159871656473 ps
CPU time 1106.07 seconds
Started Apr 30 03:08:35 PM PDT 24
Finished Apr 30 03:27:02 PM PDT 24
Peak memory 191176 kb
Host smart-2f930bd0-d965-4bb6-bd55-195c7b125a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121640846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.121640846
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2286426814
Short name T87
Test name
Test status
Simulation time 28121526620 ps
CPU time 43.35 seconds
Started Apr 30 03:08:43 PM PDT 24
Finished Apr 30 03:09:27 PM PDT 24
Peak memory 183036 kb
Host smart-f7ea93ee-a55a-4af1-97c5-7014777180e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286426814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2286426814
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.809505953
Short name T64
Test name
Test status
Simulation time 188663143642 ps
CPU time 299.03 seconds
Started Apr 30 03:08:43 PM PDT 24
Finished Apr 30 03:13:42 PM PDT 24
Peak memory 191252 kb
Host smart-91c56cc9-65da-45c1-a25c-bf921e98de8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809505953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
809505953
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.638250845
Short name T201
Test name
Test status
Simulation time 162771091608 ps
CPU time 150.81 seconds
Started Apr 30 03:08:39 PM PDT 24
Finished Apr 30 03:11:11 PM PDT 24
Peak memory 183036 kb
Host smart-c4f15294-24bb-430c-9d52-8cb6df1bca36
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638250845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.638250845
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3313746848
Short name T370
Test name
Test status
Simulation time 126731790261 ps
CPU time 131.29 seconds
Started Apr 30 03:08:39 PM PDT 24
Finished Apr 30 03:10:51 PM PDT 24
Peak memory 182992 kb
Host smart-1b9555e8-269a-4ecd-8306-0fe7c72aa400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313746848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3313746848
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3057008863
Short name T358
Test name
Test status
Simulation time 61052570443 ps
CPU time 99.82 seconds
Started Apr 30 03:08:43 PM PDT 24
Finished Apr 30 03:10:23 PM PDT 24
Peak memory 191244 kb
Host smart-107ed453-abc8-4f95-9823-aaf8c0c616d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057008863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3057008863
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.263169286
Short name T414
Test name
Test status
Simulation time 324776343821 ps
CPU time 322.59 seconds
Started Apr 30 03:08:39 PM PDT 24
Finished Apr 30 03:14:02 PM PDT 24
Peak memory 191220 kb
Host smart-05ca7632-70ff-4f49-a159-59eb630a3003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263169286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.263169286
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.422688402
Short name T110
Test name
Test status
Simulation time 74236937840 ps
CPU time 110.92 seconds
Started Apr 30 03:08:48 PM PDT 24
Finished Apr 30 03:10:39 PM PDT 24
Peak memory 183028 kb
Host smart-afd7b5e0-39fc-4592-8817-0d9cd0d3d65d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422688402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.422688402
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1164023958
Short name T385
Test name
Test status
Simulation time 392820409649 ps
CPU time 152.8 seconds
Started Apr 30 03:08:47 PM PDT 24
Finished Apr 30 03:11:20 PM PDT 24
Peak memory 183068 kb
Host smart-6b588e56-5e51-4b07-8c71-67155865a2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164023958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1164023958
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1597065362
Short name T132
Test name
Test status
Simulation time 275976472376 ps
CPU time 911.64 seconds
Started Apr 30 03:08:46 PM PDT 24
Finished Apr 30 03:23:58 PM PDT 24
Peak memory 191228 kb
Host smart-4a44287f-c5aa-44c8-8c3c-25a59bf1aedc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597065362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1597065362
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.4214971325
Short name T236
Test name
Test status
Simulation time 9046246702 ps
CPU time 4.79 seconds
Started Apr 30 03:08:47 PM PDT 24
Finished Apr 30 03:08:53 PM PDT 24
Peak memory 191248 kb
Host smart-c782371d-e099-4cd7-b771-2d69c75fed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214971325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.4214971325
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2061161640
Short name T440
Test name
Test status
Simulation time 393870636922 ps
CPU time 392.91 seconds
Started Apr 30 03:08:52 PM PDT 24
Finished Apr 30 03:15:26 PM PDT 24
Peak memory 183260 kb
Host smart-0232c387-058d-411d-b7d5-af210212e1ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061161640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2061161640
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3937441469
Short name T365
Test name
Test status
Simulation time 88387030990 ps
CPU time 67.93 seconds
Started Apr 30 03:08:51 PM PDT 24
Finished Apr 30 03:09:59 PM PDT 24
Peak memory 183076 kb
Host smart-913668dd-f9a3-4e82-acbd-c20fec99c27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937441469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3937441469
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.688303189
Short name T286
Test name
Test status
Simulation time 57339869309 ps
CPU time 85.87 seconds
Started Apr 30 03:08:55 PM PDT 24
Finished Apr 30 03:10:21 PM PDT 24
Peak memory 191232 kb
Host smart-36b8fbb4-fc4d-4093-b5f8-50f14b42e912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688303189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.688303189
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2855602175
Short name T402
Test name
Test status
Simulation time 431653617121 ps
CPU time 596.19 seconds
Started Apr 30 03:08:53 PM PDT 24
Finished Apr 30 03:18:50 PM PDT 24
Peak memory 191292 kb
Host smart-e2cd2921-eb63-4a50-a93c-0df179cf4fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855602175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2855602175
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.192053711
Short name T16
Test name
Test status
Simulation time 133430550431 ps
CPU time 612.13 seconds
Started Apr 30 03:08:51 PM PDT 24
Finished Apr 30 03:19:04 PM PDT 24
Peak memory 198700 kb
Host smart-29e87ef8-c857-4ff9-83bb-cdfe2b037f02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192053711 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.192053711
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1741314996
Short name T260
Test name
Test status
Simulation time 651529871782 ps
CPU time 641.67 seconds
Started Apr 30 03:09:04 PM PDT 24
Finished Apr 30 03:19:46 PM PDT 24
Peak memory 183076 kb
Host smart-e6f3dec8-cc71-4436-957a-553a1861249f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741314996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1741314996
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.355767477
Short name T376
Test name
Test status
Simulation time 646236930922 ps
CPU time 241.48 seconds
Started Apr 30 03:08:53 PM PDT 24
Finished Apr 30 03:12:55 PM PDT 24
Peak memory 183056 kb
Host smart-b0841e60-fecf-4a61-9c28-a7edc607543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355767477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.355767477
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2221049794
Short name T22
Test name
Test status
Simulation time 49181512013 ps
CPU time 345.88 seconds
Started Apr 30 03:08:52 PM PDT 24
Finished Apr 30 03:14:38 PM PDT 24
Peak memory 183052 kb
Host smart-c7297f8d-6323-4f96-a514-ee130f2da929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221049794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2221049794
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1555599436
Short name T323
Test name
Test status
Simulation time 24786778064 ps
CPU time 36.37 seconds
Started Apr 30 03:09:02 PM PDT 24
Finished Apr 30 03:09:39 PM PDT 24
Peak memory 183044 kb
Host smart-11fe3f67-d87d-4721-b4c9-eb862ef04543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555599436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1555599436
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3832739953
Short name T60
Test name
Test status
Simulation time 354944146196 ps
CPU time 732.5 seconds
Started Apr 30 03:09:00 PM PDT 24
Finished Apr 30 03:21:13 PM PDT 24
Peak memory 195600 kb
Host smart-19e5943f-3ac7-443f-bc51-e6172380bf3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832739953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3832739953
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.362991039
Short name T37
Test name
Test status
Simulation time 83366370215 ps
CPU time 906.56 seconds
Started Apr 30 03:08:58 PM PDT 24
Finished Apr 30 03:24:05 PM PDT 24
Peak memory 205844 kb
Host smart-c4c3ff31-762f-4f07-be01-383834e9f8ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362991039 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.362991039
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3312979111
Short name T297
Test name
Test status
Simulation time 666314055650 ps
CPU time 598.26 seconds
Started Apr 30 03:09:03 PM PDT 24
Finished Apr 30 03:19:01 PM PDT 24
Peak memory 183052 kb
Host smart-49a8599c-d453-4752-afb2-52e83a1e1e28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312979111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3312979111
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.4076931541
Short name T23
Test name
Test status
Simulation time 119066944002 ps
CPU time 103.53 seconds
Started Apr 30 03:08:58 PM PDT 24
Finished Apr 30 03:10:42 PM PDT 24
Peak memory 183052 kb
Host smart-650aa008-482a-4e12-8daf-2de624fd6254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076931541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.4076931541
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3469283194
Short name T278
Test name
Test status
Simulation time 707723885902 ps
CPU time 381.41 seconds
Started Apr 30 03:09:00 PM PDT 24
Finished Apr 30 03:15:22 PM PDT 24
Peak memory 191224 kb
Host smart-c84d5832-50e0-41fb-b15c-202718822272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469283194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3469283194
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1581968999
Short name T29
Test name
Test status
Simulation time 49578773849 ps
CPU time 82.24 seconds
Started Apr 30 03:09:00 PM PDT 24
Finished Apr 30 03:10:22 PM PDT 24
Peak memory 183040 kb
Host smart-251294d8-df9e-492e-a8c1-a8d6110811fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581968999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1581968999
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1168885657
Short name T330
Test name
Test status
Simulation time 114607848628 ps
CPU time 200.39 seconds
Started Apr 30 03:08:59 PM PDT 24
Finished Apr 30 03:12:20 PM PDT 24
Peak memory 191292 kb
Host smart-7235fca7-827c-411f-9102-acbd918d09da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168885657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1168885657
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3324363698
Short name T309
Test name
Test status
Simulation time 283223288787 ps
CPU time 423.83 seconds
Started Apr 30 03:09:06 PM PDT 24
Finished Apr 30 03:16:10 PM PDT 24
Peak memory 183048 kb
Host smart-04f884d7-cfea-40dd-85b4-5e65c94f9aa2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324363698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3324363698
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2266097305
Short name T437
Test name
Test status
Simulation time 398043504145 ps
CPU time 270.69 seconds
Started Apr 30 03:09:07 PM PDT 24
Finished Apr 30 03:13:38 PM PDT 24
Peak memory 182984 kb
Host smart-37933807-1621-4ed7-9c1a-d774e8cf8482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266097305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2266097305
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1400482526
Short name T347
Test name
Test status
Simulation time 51158264882 ps
CPU time 159.35 seconds
Started Apr 30 03:08:59 PM PDT 24
Finished Apr 30 03:11:39 PM PDT 24
Peak memory 191196 kb
Host smart-c5ce132e-c9c1-46fe-bbb3-83ca07b48eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400482526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1400482526
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1337869030
Short name T84
Test name
Test status
Simulation time 72007759093 ps
CPU time 56.86 seconds
Started Apr 30 03:09:07 PM PDT 24
Finished Apr 30 03:10:04 PM PDT 24
Peak memory 183076 kb
Host smart-dfd08f4a-345f-4bf7-b056-cd5e25b64a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337869030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1337869030
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1272879965
Short name T163
Test name
Test status
Simulation time 491177727312 ps
CPU time 2138.41 seconds
Started Apr 30 03:09:06 PM PDT 24
Finished Apr 30 03:44:45 PM PDT 24
Peak memory 191248 kb
Host smart-6e264344-351d-4966-a297-9eadfae17732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272879965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1272879965
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.751385035
Short name T15
Test name
Test status
Simulation time 19298578707 ps
CPU time 162.39 seconds
Started Apr 30 03:09:06 PM PDT 24
Finished Apr 30 03:11:49 PM PDT 24
Peak memory 196656 kb
Host smart-93f55840-f4e1-450c-ab2a-1b94232f8be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751385035 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.751385035
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2979540958
Short name T231
Test name
Test status
Simulation time 29615852477 ps
CPU time 8.07 seconds
Started Apr 30 03:09:06 PM PDT 24
Finished Apr 30 03:09:14 PM PDT 24
Peak memory 183000 kb
Host smart-f2edb49b-1c15-4297-ab2f-0c14a94c08c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979540958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2979540958
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.380581844
Short name T410
Test name
Test status
Simulation time 301943314726 ps
CPU time 140.62 seconds
Started Apr 30 03:09:07 PM PDT 24
Finished Apr 30 03:11:28 PM PDT 24
Peak memory 182968 kb
Host smart-edeb2046-a455-48ac-a5c5-6ca3b5e48a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380581844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.380581844
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2010633897
Short name T200
Test name
Test status
Simulation time 127744062461 ps
CPU time 554.64 seconds
Started Apr 30 03:09:06 PM PDT 24
Finished Apr 30 03:18:22 PM PDT 24
Peak memory 191432 kb
Host smart-ad49e16e-d6e5-4a93-b688-4c1840924cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010633897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2010633897
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2318399976
Short name T246
Test name
Test status
Simulation time 9148292100 ps
CPU time 53.84 seconds
Started Apr 30 03:09:06 PM PDT 24
Finished Apr 30 03:10:01 PM PDT 24
Peak memory 191304 kb
Host smart-9049c5d2-b0b9-4071-b30e-3d453d772feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318399976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2318399976
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2786918728
Short name T397
Test name
Test status
Simulation time 26242133890 ps
CPU time 38.5 seconds
Started Apr 30 03:09:14 PM PDT 24
Finished Apr 30 03:09:52 PM PDT 24
Peak memory 183088 kb
Host smart-10ad0e8a-005e-494b-b420-e78053e289ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786918728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2786918728
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.123783168
Short name T320
Test name
Test status
Simulation time 357578178987 ps
CPU time 649.73 seconds
Started Apr 30 03:09:13 PM PDT 24
Finished Apr 30 03:20:03 PM PDT 24
Peak memory 182972 kb
Host smart-5d376c85-4e07-42cd-9831-661cb9e17931
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123783168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.123783168
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3284603505
Short name T412
Test name
Test status
Simulation time 311918882585 ps
CPU time 302.78 seconds
Started Apr 30 03:09:11 PM PDT 24
Finished Apr 30 03:14:15 PM PDT 24
Peak memory 183096 kb
Host smart-13b56286-b6fd-42d8-b589-ef18a1ed1431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284603505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3284603505
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2576459996
Short name T168
Test name
Test status
Simulation time 37233655809 ps
CPU time 59.53 seconds
Started Apr 30 03:09:12 PM PDT 24
Finished Apr 30 03:10:12 PM PDT 24
Peak memory 183012 kb
Host smart-a7fa4ac7-aef7-45a7-8c49-410ba9cf2a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576459996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2576459996
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3943073989
Short name T317
Test name
Test status
Simulation time 96969064215 ps
CPU time 364.74 seconds
Started Apr 30 03:09:12 PM PDT 24
Finished Apr 30 03:15:18 PM PDT 24
Peak memory 191172 kb
Host smart-4d190341-1904-467a-b174-cba787a65472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943073989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3943073989
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3312718910
Short name T46
Test name
Test status
Simulation time 5537948980 ps
CPU time 10.02 seconds
Started Apr 30 03:09:20 PM PDT 24
Finished Apr 30 03:09:31 PM PDT 24
Peak memory 183044 kb
Host smart-d7645701-4ade-48e3-b9f5-a6474bea3389
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312718910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3312718910
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2046796409
Short name T367
Test name
Test status
Simulation time 343125535291 ps
CPU time 146.73 seconds
Started Apr 30 03:09:23 PM PDT 24
Finished Apr 30 03:11:50 PM PDT 24
Peak memory 183072 kb
Host smart-8eb49510-986c-475a-b592-77f8f2a22e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046796409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2046796409
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.4123419517
Short name T130
Test name
Test status
Simulation time 123230821424 ps
CPU time 82.41 seconds
Started Apr 30 03:09:20 PM PDT 24
Finished Apr 30 03:10:42 PM PDT 24
Peak memory 191228 kb
Host smart-4a8983c9-8697-4e1f-a1f6-726ebb9d546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123419517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4123419517
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3889706289
Short name T295
Test name
Test status
Simulation time 855366634813 ps
CPU time 494.1 seconds
Started Apr 30 03:07:51 PM PDT 24
Finished Apr 30 03:16:07 PM PDT 24
Peak memory 183068 kb
Host smart-3e3d67e5-2b79-48d7-a255-2bfdbb089d5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889706289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3889706289
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1484272309
Short name T400
Test name
Test status
Simulation time 114146298189 ps
CPU time 27.35 seconds
Started Apr 30 03:07:51 PM PDT 24
Finished Apr 30 03:08:19 PM PDT 24
Peak memory 183000 kb
Host smart-3962a99e-7837-4d3d-af28-55cd35bfa7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484272309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1484272309
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1677065432
Short name T107
Test name
Test status
Simulation time 86038318943 ps
CPU time 139.43 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:10:10 PM PDT 24
Peak memory 191256 kb
Host smart-6526408f-fcf0-43ad-8d5a-cf56344e3bde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677065432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1677065432
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2367249502
Short name T453
Test name
Test status
Simulation time 731412056 ps
CPU time 1.02 seconds
Started Apr 30 03:07:52 PM PDT 24
Finished Apr 30 03:07:54 PM PDT 24
Peak memory 191508 kb
Host smart-68301d02-6de2-400b-9bb7-7606413d0070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367249502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2367249502
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3102060282
Short name T59
Test name
Test status
Simulation time 163790321969 ps
CPU time 378.33 seconds
Started Apr 30 03:07:52 PM PDT 24
Finished Apr 30 03:14:12 PM PDT 24
Peak memory 191240 kb
Host smart-4ffbba59-5d9d-4525-8426-b86dc3eae695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102060282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3102060282
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1180598322
Short name T43
Test name
Test status
Simulation time 78173142723 ps
CPU time 152.38 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:10:23 PM PDT 24
Peak memory 197628 kb
Host smart-7a4f8923-c5da-4cda-beb1-394334f15eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180598322 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1180598322
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.139143004
Short name T351
Test name
Test status
Simulation time 109004021127 ps
CPU time 85.34 seconds
Started Apr 30 03:09:23 PM PDT 24
Finished Apr 30 03:10:49 PM PDT 24
Peak memory 183068 kb
Host smart-28e26aab-db27-4219-92b9-5aac12844528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139143004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.139143004
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2533314500
Short name T331
Test name
Test status
Simulation time 377121510677 ps
CPU time 332.45 seconds
Started Apr 30 03:09:22 PM PDT 24
Finished Apr 30 03:14:55 PM PDT 24
Peak memory 191276 kb
Host smart-bc8bda9d-72e3-45ce-b740-f9065ebd1a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533314500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2533314500
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3765182760
Short name T432
Test name
Test status
Simulation time 369684217869 ps
CPU time 162.51 seconds
Started Apr 30 03:09:18 PM PDT 24
Finished Apr 30 03:12:01 PM PDT 24
Peak memory 191284 kb
Host smart-dd6585ab-de58-4657-8980-0d36697549ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765182760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3765182760
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.862765027
Short name T197
Test name
Test status
Simulation time 1501116046488 ps
CPU time 736.82 seconds
Started Apr 30 03:09:20 PM PDT 24
Finished Apr 30 03:21:38 PM PDT 24
Peak memory 191220 kb
Host smart-007be38f-fb8e-463f-8236-df36f3d03964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862765027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.862765027
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3954538744
Short name T113
Test name
Test status
Simulation time 81285961654 ps
CPU time 149.38 seconds
Started Apr 30 03:09:22 PM PDT 24
Finished Apr 30 03:11:52 PM PDT 24
Peak memory 191268 kb
Host smart-58d1937e-b0b6-447b-914c-61f30989591e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954538744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3954538744
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1698315519
Short name T263
Test name
Test status
Simulation time 399851618485 ps
CPU time 141.48 seconds
Started Apr 30 03:09:29 PM PDT 24
Finished Apr 30 03:11:51 PM PDT 24
Peak memory 191196 kb
Host smart-2386f474-dec2-4d8b-be4e-00767a8bdf70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698315519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1698315519
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2036478174
Short name T254
Test name
Test status
Simulation time 57479727612 ps
CPU time 458.8 seconds
Started Apr 30 03:09:29 PM PDT 24
Finished Apr 30 03:17:09 PM PDT 24
Peak memory 191184 kb
Host smart-1f1820ca-0662-4472-a79c-e4bdf3e376a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036478174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2036478174
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.104710339
Short name T88
Test name
Test status
Simulation time 1027869115584 ps
CPU time 248.11 seconds
Started Apr 30 03:07:51 PM PDT 24
Finished Apr 30 03:12:00 PM PDT 24
Peak memory 183088 kb
Host smart-82458916-439c-4407-ab88-1d2db0378e6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104710339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.104710339
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3417551520
Short name T71
Test name
Test status
Simulation time 734208146975 ps
CPU time 279.88 seconds
Started Apr 30 03:07:51 PM PDT 24
Finished Apr 30 03:12:32 PM PDT 24
Peak memory 183068 kb
Host smart-42d63884-0dca-4db4-9cd2-881d6ded7311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417551520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3417551520
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2544556869
Short name T447
Test name
Test status
Simulation time 86375837260 ps
CPU time 76.07 seconds
Started Apr 30 03:07:50 PM PDT 24
Finished Apr 30 03:09:07 PM PDT 24
Peak memory 183048 kb
Host smart-e9e912f2-6b9f-40ca-92b4-5d57b388ca03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544556869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2544556869
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2717055375
Short name T411
Test name
Test status
Simulation time 5427771189 ps
CPU time 15.91 seconds
Started Apr 30 03:07:52 PM PDT 24
Finished Apr 30 03:08:09 PM PDT 24
Peak memory 191264 kb
Host smart-49a00dfe-dcde-4199-8ced-af5f618617c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717055375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2717055375
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1147183015
Short name T61
Test name
Test status
Simulation time 92208622 ps
CPU time 0.61 seconds
Started Apr 30 03:07:54 PM PDT 24
Finished Apr 30 03:07:56 PM PDT 24
Peak memory 182844 kb
Host smart-75b88cfa-2045-49cc-8438-2f0122e832b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147183015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1147183015
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3134448881
Short name T176
Test name
Test status
Simulation time 547019126164 ps
CPU time 1007.97 seconds
Started Apr 30 03:09:28 PM PDT 24
Finished Apr 30 03:26:17 PM PDT 24
Peak memory 191248 kb
Host smart-b2917d87-07c7-402c-a293-d5226ba21f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134448881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3134448881
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1493139381
Short name T272
Test name
Test status
Simulation time 402254336115 ps
CPU time 165.4 seconds
Started Apr 30 03:09:29 PM PDT 24
Finished Apr 30 03:12:14 PM PDT 24
Peak memory 191184 kb
Host smart-c2c924fc-50e7-4dcf-bf96-bec41fef942c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493139381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1493139381
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4201239905
Short name T224
Test name
Test status
Simulation time 582558588713 ps
CPU time 450 seconds
Started Apr 30 03:09:28 PM PDT 24
Finished Apr 30 03:16:59 PM PDT 24
Peak memory 194372 kb
Host smart-9123e3a1-0637-4182-ad97-9a54de48c33f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201239905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4201239905
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3366028463
Short name T210
Test name
Test status
Simulation time 324015214590 ps
CPU time 634.38 seconds
Started Apr 30 03:09:30 PM PDT 24
Finished Apr 30 03:20:05 PM PDT 24
Peak memory 191264 kb
Host smart-4475eb1e-b746-4f0f-bf20-14647968458c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366028463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3366028463
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1459350859
Short name T162
Test name
Test status
Simulation time 465427683068 ps
CPU time 244.82 seconds
Started Apr 30 03:09:28 PM PDT 24
Finished Apr 30 03:13:34 PM PDT 24
Peak memory 191248 kb
Host smart-5570df88-5d8b-4be8-b245-2a1da8db5411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459350859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1459350859
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2559032234
Short name T244
Test name
Test status
Simulation time 379219492278 ps
CPU time 186.71 seconds
Started Apr 30 03:09:27 PM PDT 24
Finished Apr 30 03:12:35 PM PDT 24
Peak memory 193564 kb
Host smart-0811461b-c709-4de7-9ee9-dd22f71e2e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559032234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2559032234
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.629855055
Short name T449
Test name
Test status
Simulation time 56067974829 ps
CPU time 82.27 seconds
Started Apr 30 03:09:29 PM PDT 24
Finished Apr 30 03:10:51 PM PDT 24
Peak memory 194604 kb
Host smart-ee372d3b-aa82-4715-a73c-8097f4a969fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629855055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.629855055
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2224453958
Short name T436
Test name
Test status
Simulation time 35864473901 ps
CPU time 53.85 seconds
Started Apr 30 03:09:27 PM PDT 24
Finished Apr 30 03:10:22 PM PDT 24
Peak memory 183032 kb
Host smart-dc6969b3-1867-4818-a92b-1f36d3adb92c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224453958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2224453958
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3888494464
Short name T191
Test name
Test status
Simulation time 51367797450 ps
CPU time 59.49 seconds
Started Apr 30 03:09:38 PM PDT 24
Finished Apr 30 03:10:38 PM PDT 24
Peak memory 191212 kb
Host smart-0f9e21e2-fd2f-4576-82cf-9d24abdd4905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888494464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3888494464
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.376445611
Short name T275
Test name
Test status
Simulation time 50430893859 ps
CPU time 38.3 seconds
Started Apr 30 03:09:33 PM PDT 24
Finished Apr 30 03:10:12 PM PDT 24
Peak memory 182860 kb
Host smart-b91236f5-5509-4c37-bff5-973adc2cbdf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376445611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.376445611
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.339531125
Short name T350
Test name
Test status
Simulation time 23500935466 ps
CPU time 21.18 seconds
Started Apr 30 03:07:58 PM PDT 24
Finished Apr 30 03:08:20 PM PDT 24
Peak memory 183032 kb
Host smart-b3407b92-3469-4818-a5bf-8f1b4205c71c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339531125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.339531125
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_random.3643429457
Short name T115
Test name
Test status
Simulation time 109182764857 ps
CPU time 117.15 seconds
Started Apr 30 03:07:57 PM PDT 24
Finished Apr 30 03:09:55 PM PDT 24
Peak memory 191204 kb
Host smart-ccaa32ef-9ed8-48e0-b973-d9f9fbf33cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643429457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3643429457
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.997017706
Short name T26
Test name
Test status
Simulation time 131148876 ps
CPU time 0.58 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:08:05 PM PDT 24
Peak memory 182880 kb
Host smart-deee774b-b6fe-41a8-9e3d-905d42e14765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997017706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.997017706
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3117882053
Short name T348
Test name
Test status
Simulation time 564902327847 ps
CPU time 425.48 seconds
Started Apr 30 03:09:36 PM PDT 24
Finished Apr 30 03:16:42 PM PDT 24
Peak memory 191220 kb
Host smart-923170cb-50b9-4a25-a0cd-63fa4506591b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117882053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3117882053
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.42374357
Short name T81
Test name
Test status
Simulation time 449453594727 ps
CPU time 418.33 seconds
Started Apr 30 03:09:39 PM PDT 24
Finished Apr 30 03:16:38 PM PDT 24
Peak memory 191212 kb
Host smart-58a77664-06f9-446a-a23d-798a74bfdb7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42374357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.42374357
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1609656185
Short name T312
Test name
Test status
Simulation time 74992282775 ps
CPU time 120.03 seconds
Started Apr 30 03:09:36 PM PDT 24
Finished Apr 30 03:11:37 PM PDT 24
Peak memory 191216 kb
Host smart-9c9046ae-f8b3-45b9-95fc-2b59d5fa49fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609656185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1609656185
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3807992405
Short name T138
Test name
Test status
Simulation time 717838842250 ps
CPU time 1013.44 seconds
Started Apr 30 03:09:36 PM PDT 24
Finished Apr 30 03:26:30 PM PDT 24
Peak memory 193752 kb
Host smart-3ceca121-571b-4433-83c2-cad3e9071ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807992405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3807992405
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4142606161
Short name T274
Test name
Test status
Simulation time 492126544353 ps
CPU time 288.4 seconds
Started Apr 30 03:09:35 PM PDT 24
Finished Apr 30 03:14:24 PM PDT 24
Peak memory 191204 kb
Host smart-80233d04-32d8-40cf-9f56-b49600af158a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142606161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4142606161
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.75875790
Short name T352
Test name
Test status
Simulation time 381413136362 ps
CPU time 192.47 seconds
Started Apr 30 03:09:38 PM PDT 24
Finished Apr 30 03:12:51 PM PDT 24
Peak memory 193864 kb
Host smart-5527217d-04f6-436a-8ed4-582c2ea130f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75875790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.75875790
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2588174471
Short name T279
Test name
Test status
Simulation time 161228866255 ps
CPU time 183.98 seconds
Started Apr 30 03:09:34 PM PDT 24
Finished Apr 30 03:12:38 PM PDT 24
Peak memory 191264 kb
Host smart-6a07531b-2692-4608-9c5b-6bc43adff41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588174471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2588174471
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1156684763
Short name T179
Test name
Test status
Simulation time 864989315518 ps
CPU time 628.68 seconds
Started Apr 30 03:09:37 PM PDT 24
Finished Apr 30 03:20:06 PM PDT 24
Peak memory 191268 kb
Host smart-433fa5ac-b2cd-4c9b-a47f-a48c8310c250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156684763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1156684763
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2418935082
Short name T284
Test name
Test status
Simulation time 40109883180 ps
CPU time 67.04 seconds
Started Apr 30 03:09:38 PM PDT 24
Finished Apr 30 03:10:46 PM PDT 24
Peak memory 182912 kb
Host smart-a239a53a-8b5c-4f20-950a-54842983a737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418935082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2418935082
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3409993639
Short name T360
Test name
Test status
Simulation time 367929409405 ps
CPU time 203.81 seconds
Started Apr 30 03:07:58 PM PDT 24
Finished Apr 30 03:11:22 PM PDT 24
Peak memory 183112 kb
Host smart-5ac6695c-ea91-4ce3-ba99-1d2220225e58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409993639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3409993639
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1236365401
Short name T429
Test name
Test status
Simulation time 572914758897 ps
CPU time 266.36 seconds
Started Apr 30 03:07:59 PM PDT 24
Finished Apr 30 03:12:26 PM PDT 24
Peak memory 183028 kb
Host smart-8d020206-9f2c-4e2d-a148-339b7b18afa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236365401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1236365401
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1601834702
Short name T334
Test name
Test status
Simulation time 483309353234 ps
CPU time 131.17 seconds
Started Apr 30 03:07:58 PM PDT 24
Finished Apr 30 03:10:10 PM PDT 24
Peak memory 182992 kb
Host smart-f3ec8e0a-4530-44f1-8d2a-4891e32bf5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601834702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1601834702
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1847093982
Short name T353
Test name
Test status
Simulation time 171020159936 ps
CPU time 83.77 seconds
Started Apr 30 03:08:04 PM PDT 24
Finished Apr 30 03:09:28 PM PDT 24
Peak memory 183072 kb
Host smart-559a2225-386d-4510-b1e6-52c937c7ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847093982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1847093982
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.674434420
Short name T38
Test name
Test status
Simulation time 149273941857 ps
CPU time 1352.86 seconds
Started Apr 30 03:07:59 PM PDT 24
Finished Apr 30 03:30:33 PM PDT 24
Peak memory 212200 kb
Host smart-d53abc31-e229-4aca-a948-86579b7f829d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674434420 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.674434420
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1844588258
Short name T310
Test name
Test status
Simulation time 30748906056 ps
CPU time 26.86 seconds
Started Apr 30 03:09:35 PM PDT 24
Finished Apr 30 03:10:02 PM PDT 24
Peak memory 183020 kb
Host smart-6d21732e-c6aa-4305-95b2-b859a73951a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844588258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1844588258
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3484446383
Short name T49
Test name
Test status
Simulation time 1301277803080 ps
CPU time 292.18 seconds
Started Apr 30 03:09:36 PM PDT 24
Finished Apr 30 03:14:29 PM PDT 24
Peak memory 191260 kb
Host smart-9dd18807-c293-48ea-ace6-d72795384d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484446383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3484446383
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3095638734
Short name T345
Test name
Test status
Simulation time 65975335545 ps
CPU time 107.96 seconds
Started Apr 30 03:09:38 PM PDT 24
Finished Apr 30 03:11:27 PM PDT 24
Peak memory 191256 kb
Host smart-eb27fd76-5fe3-4f8d-83fb-71870db4e36a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095638734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3095638734
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3004572142
Short name T124
Test name
Test status
Simulation time 23366750798 ps
CPU time 40.51 seconds
Started Apr 30 03:09:35 PM PDT 24
Finished Apr 30 03:10:16 PM PDT 24
Peak memory 191276 kb
Host smart-3a7e69a9-53f5-4121-8913-ed0931bb4cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004572142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3004572142
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2220849182
Short name T448
Test name
Test status
Simulation time 104082891224 ps
CPU time 251.09 seconds
Started Apr 30 03:09:42 PM PDT 24
Finished Apr 30 03:13:54 PM PDT 24
Peak memory 191236 kb
Host smart-ab774bd9-956e-40ec-afb0-58994aa46157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220849182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2220849182
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.164500600
Short name T149
Test name
Test status
Simulation time 98750172688 ps
CPU time 211.63 seconds
Started Apr 30 03:09:45 PM PDT 24
Finished Apr 30 03:13:17 PM PDT 24
Peak memory 191196 kb
Host smart-f7d93cef-6afc-4e2f-ba7e-4772e239851c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164500600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.164500600
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.801431333
Short name T287
Test name
Test status
Simulation time 71146184881 ps
CPU time 168.06 seconds
Started Apr 30 03:09:42 PM PDT 24
Finished Apr 30 03:12:31 PM PDT 24
Peak memory 191196 kb
Host smart-2dd222d8-3ad9-44b3-8a7a-8e0d487356fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801431333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.801431333
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.11186044
Short name T307
Test name
Test status
Simulation time 58872190687 ps
CPU time 93.66 seconds
Started Apr 30 03:09:43 PM PDT 24
Finished Apr 30 03:11:17 PM PDT 24
Peak memory 191256 kb
Host smart-6d8e182a-ff60-4621-b63e-4250b9a23157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11186044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.11186044
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2281767030
Short name T159
Test name
Test status
Simulation time 1526988248042 ps
CPU time 469.48 seconds
Started Apr 30 03:09:43 PM PDT 24
Finished Apr 30 03:17:33 PM PDT 24
Peak memory 191244 kb
Host smart-4ab18163-9860-4676-bb5f-2b975f1c135e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281767030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2281767030
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3561247729
Short name T216
Test name
Test status
Simulation time 43825922639 ps
CPU time 41.14 seconds
Started Apr 30 03:08:03 PM PDT 24
Finished Apr 30 03:08:45 PM PDT 24
Peak memory 183076 kb
Host smart-a1db71b2-ad9a-40c5-b005-7caf57deffb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561247729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3561247729
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.781087844
Short name T72
Test name
Test status
Simulation time 143507056677 ps
CPU time 61.29 seconds
Started Apr 30 03:07:57 PM PDT 24
Finished Apr 30 03:09:00 PM PDT 24
Peak memory 183020 kb
Host smart-48f26e51-76fc-44de-a665-6aa8fd29a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781087844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.781087844
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/90.rv_timer_random.3938950038
Short name T252
Test name
Test status
Simulation time 75180951203 ps
CPU time 72.76 seconds
Started Apr 30 03:09:42 PM PDT 24
Finished Apr 30 03:10:55 PM PDT 24
Peak memory 191216 kb
Host smart-3a2379cc-64da-4fea-9560-7e711692f431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938950038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3938950038
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1840971846
Short name T186
Test name
Test status
Simulation time 177837110396 ps
CPU time 207.45 seconds
Started Apr 30 03:09:44 PM PDT 24
Finished Apr 30 03:13:12 PM PDT 24
Peak memory 191256 kb
Host smart-05922405-1fec-46af-b619-cce46e61a023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840971846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1840971846
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1947861718
Short name T424
Test name
Test status
Simulation time 82590610661 ps
CPU time 140.19 seconds
Started Apr 30 03:09:43 PM PDT 24
Finished Apr 30 03:12:04 PM PDT 24
Peak memory 183064 kb
Host smart-b48a5ef3-47c9-4997-9223-ab607451ec3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947861718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1947861718
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3339097810
Short name T219
Test name
Test status
Simulation time 222406048497 ps
CPU time 245.62 seconds
Started Apr 30 03:09:42 PM PDT 24
Finished Apr 30 03:13:48 PM PDT 24
Peak memory 191204 kb
Host smart-36cc4aa2-d729-41ae-b1f8-86c375f4d12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339097810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3339097810
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.4292890511
Short name T363
Test name
Test status
Simulation time 110866893417 ps
CPU time 47.32 seconds
Started Apr 30 03:09:43 PM PDT 24
Finished Apr 30 03:10:31 PM PDT 24
Peak memory 183012 kb
Host smart-1485c8e8-d456-4dc1-9cf9-64902e94ac8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292890511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4292890511
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3433724419
Short name T430
Test name
Test status
Simulation time 610274694109 ps
CPU time 573.29 seconds
Started Apr 30 03:09:42 PM PDT 24
Finished Apr 30 03:19:16 PM PDT 24
Peak memory 191260 kb
Host smart-62ceb042-bde4-4bce-b20e-ed85b41cbfcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433724419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3433724419
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1259796376
Short name T141
Test name
Test status
Simulation time 4256425138 ps
CPU time 50.83 seconds
Started Apr 30 03:09:43 PM PDT 24
Finished Apr 30 03:10:34 PM PDT 24
Peak memory 183060 kb
Host smart-b4e59773-ab2e-4d21-b2d6-6d754dcf1fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259796376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1259796376
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2721224165
Short name T332
Test name
Test status
Simulation time 79521164397 ps
CPU time 313.8 seconds
Started Apr 30 03:09:43 PM PDT 24
Finished Apr 30 03:14:57 PM PDT 24
Peak memory 192232 kb
Host smart-ca21fab3-5e3f-4bd2-a592-270df6790fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721224165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2721224165
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3479768289
Short name T147
Test name
Test status
Simulation time 77138183963 ps
CPU time 108.62 seconds
Started Apr 30 03:09:42 PM PDT 24
Finished Apr 30 03:11:32 PM PDT 24
Peak memory 191172 kb
Host smart-ffd44429-dc42-470a-a2b3-43d78f9354bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479768289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3479768289
Directory /workspace/98.rv_timer_random/latest
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