Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 580
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T510 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.569307991 May 02 01:18:37 PM PDT 24 May 02 01:18:38 PM PDT 24 17060290 ps
T511 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1164540994 May 02 01:17:14 PM PDT 24 May 02 01:17:15 PM PDT 24 28839413 ps
T512 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1651907965 May 02 01:17:59 PM PDT 24 May 02 01:18:02 PM PDT 24 457527876 ps
T90 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.725941882 May 02 01:16:30 PM PDT 24 May 02 01:16:31 PM PDT 24 164627494 ps
T513 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3820736518 May 02 01:17:35 PM PDT 24 May 02 01:17:37 PM PDT 24 172299963 ps
T514 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3981464014 May 02 01:16:25 PM PDT 24 May 02 01:16:27 PM PDT 24 71500990 ps
T515 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1298519431 May 02 01:17:28 PM PDT 24 May 02 01:17:29 PM PDT 24 122242797 ps
T516 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2815172490 May 02 01:18:06 PM PDT 24 May 02 01:18:07 PM PDT 24 208882093 ps
T517 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3154900950 May 02 01:17:35 PM PDT 24 May 02 01:17:37 PM PDT 24 89041847 ps
T518 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3183222305 May 02 01:18:29 PM PDT 24 May 02 01:18:30 PM PDT 24 37781136 ps
T519 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2637650815 May 02 01:18:15 PM PDT 24 May 02 01:18:17 PM PDT 24 13014312 ps
T520 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3160468794 May 02 01:18:39 PM PDT 24 May 02 01:18:40 PM PDT 24 12677607 ps
T521 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1076552983 May 02 01:18:39 PM PDT 24 May 02 01:18:40 PM PDT 24 82036830 ps
T115 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1921134697 May 02 01:17:43 PM PDT 24 May 02 01:17:44 PM PDT 24 163429662 ps
T522 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.957881434 May 02 01:17:51 PM PDT 24 May 02 01:17:52 PM PDT 24 18639174 ps
T116 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3053608284 May 02 01:18:11 PM PDT 24 May 02 01:18:12 PM PDT 24 40497151 ps
T523 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3042413017 May 02 01:18:28 PM PDT 24 May 02 01:18:29 PM PDT 24 23309785 ps
T120 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1260493454 May 02 01:17:35 PM PDT 24 May 02 01:17:37 PM PDT 24 139693054 ps
T524 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2842893826 May 02 01:18:07 PM PDT 24 May 02 01:18:08 PM PDT 24 25817590 ps
T525 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3865284076 May 02 01:18:10 PM PDT 24 May 02 01:18:11 PM PDT 24 19197555 ps
T526 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3502007236 May 02 01:18:16 PM PDT 24 May 02 01:18:18 PM PDT 24 40554248 ps
T527 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2265603880 May 02 01:16:57 PM PDT 24 May 02 01:16:59 PM PDT 24 13278320 ps
T91 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.349464971 May 02 01:17:50 PM PDT 24 May 02 01:17:51 PM PDT 24 45720737 ps
T528 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1228738161 May 02 01:18:38 PM PDT 24 May 02 01:18:39 PM PDT 24 50162926 ps
T529 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1911867829 May 02 01:17:36 PM PDT 24 May 02 01:17:37 PM PDT 24 56864199 ps
T92 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3231902561 May 02 01:17:45 PM PDT 24 May 02 01:17:46 PM PDT 24 43342929 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.18778940 May 02 01:15:26 PM PDT 24 May 02 01:15:27 PM PDT 24 172335257 ps
T531 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2687637001 May 02 01:17:35 PM PDT 24 May 02 01:17:37 PM PDT 24 33774555 ps
T532 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.340423303 May 02 01:18:30 PM PDT 24 May 02 01:18:31 PM PDT 24 57663032 ps
T533 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.898526027 May 02 01:17:43 PM PDT 24 May 02 01:17:45 PM PDT 24 182629594 ps
T534 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3805151214 May 02 01:18:37 PM PDT 24 May 02 01:18:39 PM PDT 24 81021266 ps
T535 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1261005569 May 02 01:15:41 PM PDT 24 May 02 01:15:45 PM PDT 24 5477558306 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.380605364 May 02 01:16:25 PM PDT 24 May 02 01:16:27 PM PDT 24 77183591 ps
T537 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.474042293 May 02 01:18:07 PM PDT 24 May 02 01:18:09 PM PDT 24 115123318 ps
T538 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2828573929 May 02 01:17:58 PM PDT 24 May 02 01:18:01 PM PDT 24 141785795 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3260584634 May 02 01:17:06 PM PDT 24 May 02 01:17:07 PM PDT 24 12278374 ps
T540 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.30256255 May 02 01:16:38 PM PDT 24 May 02 01:16:39 PM PDT 24 59757580 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3435268168 May 02 01:17:29 PM PDT 24 May 02 01:17:30 PM PDT 24 22049525 ps
T542 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2246607069 May 02 01:18:08 PM PDT 24 May 02 01:18:09 PM PDT 24 26289368 ps
T543 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.749427156 May 02 01:17:05 PM PDT 24 May 02 01:17:06 PM PDT 24 30454663 ps
T544 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.109901814 May 02 01:17:27 PM PDT 24 May 02 01:17:29 PM PDT 24 277700411 ps
T93 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2346241221 May 02 01:17:06 PM PDT 24 May 02 01:17:08 PM PDT 24 24769540 ps
T545 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1609439724 May 02 01:17:52 PM PDT 24 May 02 01:17:54 PM PDT 24 101872130 ps
T546 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2063239355 May 02 01:18:36 PM PDT 24 May 02 01:18:37 PM PDT 24 40983632 ps
T547 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1622217466 May 02 01:17:42 PM PDT 24 May 02 01:17:43 PM PDT 24 113524098 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3884297102 May 02 01:16:12 PM PDT 24 May 02 01:16:13 PM PDT 24 60824575 ps
T549 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.100023959 May 02 01:17:20 PM PDT 24 May 02 01:17:21 PM PDT 24 11085097 ps
T550 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.412212293 May 02 01:18:36 PM PDT 24 May 02 01:18:38 PM PDT 24 15265592 ps
T551 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3051870806 May 02 01:16:55 PM PDT 24 May 02 01:16:57 PM PDT 24 34598762 ps
T552 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3585876936 May 02 01:18:11 PM PDT 24 May 02 01:18:13 PM PDT 24 80844182 ps
T95 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4287682783 May 02 01:17:52 PM PDT 24 May 02 01:17:54 PM PDT 24 56961285 ps
T553 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1964458817 May 02 01:17:51 PM PDT 24 May 02 01:17:53 PM PDT 24 72517259 ps
T554 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3105033422 May 02 01:16:56 PM PDT 24 May 02 01:16:58 PM PDT 24 46144592 ps
T555 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2690180065 May 02 01:16:06 PM PDT 24 May 02 01:16:08 PM PDT 24 49459502 ps
T556 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1817902174 May 02 01:15:39 PM PDT 24 May 02 01:15:41 PM PDT 24 143002933 ps
T557 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2528453349 May 02 01:16:39 PM PDT 24 May 02 01:16:40 PM PDT 24 55725080 ps
T558 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.125060211 May 02 01:18:15 PM PDT 24 May 02 01:18:16 PM PDT 24 33454738 ps
T559 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3366228296 May 02 01:17:28 PM PDT 24 May 02 01:17:29 PM PDT 24 13131676 ps
T560 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.4137354911 May 02 01:17:27 PM PDT 24 May 02 01:17:29 PM PDT 24 73140330 ps
T94 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1978009229 May 02 01:16:25 PM PDT 24 May 02 01:16:27 PM PDT 24 33186182 ps
T561 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1111472870 May 02 01:17:13 PM PDT 24 May 02 01:17:15 PM PDT 24 441841248 ps
T562 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2620710904 May 02 01:16:39 PM PDT 24 May 02 01:16:40 PM PDT 24 80210256 ps
T563 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2024272958 May 02 01:16:49 PM PDT 24 May 02 01:16:50 PM PDT 24 18881767 ps
T564 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.966918427 May 02 01:17:51 PM PDT 24 May 02 01:17:53 PM PDT 24 57240150 ps
T565 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4259437058 May 02 01:16:16 PM PDT 24 May 02 01:16:17 PM PDT 24 27469353 ps
T566 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3194720540 May 02 01:17:59 PM PDT 24 May 02 01:18:00 PM PDT 24 54806641 ps
T567 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2196592215 May 02 01:17:52 PM PDT 24 May 02 01:17:54 PM PDT 24 452652809 ps
T568 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1964238831 May 02 01:18:37 PM PDT 24 May 02 01:18:39 PM PDT 24 15366817 ps
T569 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.662862507 May 02 01:17:52 PM PDT 24 May 02 01:17:54 PM PDT 24 53296493 ps
T570 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2870311061 May 02 01:18:00 PM PDT 24 May 02 01:18:01 PM PDT 24 26598352 ps
T571 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3386779537 May 02 01:17:22 PM PDT 24 May 02 01:17:23 PM PDT 24 32884593 ps
T572 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3972662422 May 02 01:15:27 PM PDT 24 May 02 01:15:29 PM PDT 24 56624031 ps
T573 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3867637787 May 02 01:16:38 PM PDT 24 May 02 01:16:41 PM PDT 24 179057602 ps
T574 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1059267755 May 02 01:18:14 PM PDT 24 May 02 01:18:15 PM PDT 24 14117794 ps
T575 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.401642410 May 02 01:15:34 PM PDT 24 May 02 01:15:36 PM PDT 24 27985729 ps
T576 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3379755775 May 02 01:15:41 PM PDT 24 May 02 01:15:43 PM PDT 24 17554644 ps
T577 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3101877680 May 02 01:18:00 PM PDT 24 May 02 01:18:02 PM PDT 24 36817326 ps
T578 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1081944890 May 02 01:15:56 PM PDT 24 May 02 01:16:00 PM PDT 24 293958497 ps
T579 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4229771373 May 02 01:18:41 PM PDT 24 May 02 01:18:42 PM PDT 24 18005608 ps
T580 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2768414511 May 02 01:16:23 PM PDT 24 May 02 01:16:25 PM PDT 24 319690754 ps

Test location /workspace/coverage/default/163.rv_timer_random.1042980556
Short name T3
Test name
Test status
Simulation time 117354830120 ps
CPU time 180.7 seconds
Started May 02 01:30:21 PM PDT 24
Finished May 02 01:33:23 PM PDT 24
Peak memory 191220 kb
Host smart-0dc29864-6c16-4bed-9792-d05a2ed3d38b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042980556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1042980556
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.377004895
Short name T12
Test name
Test status
Simulation time 151268888177 ps
CPU time 1057.18 seconds
Started May 02 01:21:29 PM PDT 24
Finished May 02 01:39:07 PM PDT 24
Peak memory 212416 kb
Host smart-266bd1eb-051e-43c1-bceb-44a5eda234c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377004895 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.377004895
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1695617830
Short name T1
Test name
Test status
Simulation time 3676517740508 ps
CPU time 2971.21 seconds
Started May 02 01:26:39 PM PDT 24
Finished May 02 02:16:11 PM PDT 24
Peak memory 191156 kb
Host smart-df21d163-aa12-458e-ad94-8c5cce8dc9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695617830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1695617830
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3294031445
Short name T15
Test name
Test status
Simulation time 87191275 ps
CPU time 0.94 seconds
Started May 02 01:18:42 PM PDT 24
Finished May 02 01:18:44 PM PDT 24
Peak memory 215888 kb
Host smart-9f781fe0-94cc-4b0f-ae87-bcf2c4ec4bbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294031445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3294031445
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2785007763
Short name T82
Test name
Test status
Simulation time 1508827250733 ps
CPU time 5220.91 seconds
Started May 02 01:24:07 PM PDT 24
Finished May 02 02:51:10 PM PDT 24
Peak memory 191200 kb
Host smart-0ce75c52-271e-450b-a569-22a4467657a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785007763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2785007763
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4193358496
Short name T8
Test name
Test status
Simulation time 565541966824 ps
CPU time 1055.56 seconds
Started May 02 01:23:45 PM PDT 24
Finished May 02 01:41:21 PM PDT 24
Peak memory 191256 kb
Host smart-179f9d37-1458-47ad-bd2a-10d95bcd00a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193358496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4193358496
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1998024629
Short name T127
Test name
Test status
Simulation time 1366269443001 ps
CPU time 1302.02 seconds
Started May 02 01:23:25 PM PDT 24
Finished May 02 01:45:08 PM PDT 24
Peak memory 196368 kb
Host smart-d6641c52-d364-4ebd-8001-deba7021dcb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998024629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1998024629
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.276242010
Short name T303
Test name
Test status
Simulation time 1421395219677 ps
CPU time 2467.33 seconds
Started May 02 01:18:43 PM PDT 24
Finished May 02 01:59:51 PM PDT 24
Peak memory 191220 kb
Host smart-1b193068-6975-44a5-b7d8-671fffed6c06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276242010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.276242010
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1003627196
Short name T73
Test name
Test status
Simulation time 16656965 ps
CPU time 0.58 seconds
Started May 02 01:16:24 PM PDT 24
Finished May 02 01:16:26 PM PDT 24
Peak memory 182752 kb
Host smart-001378b6-899e-48a6-bb14-b8a72a9b8582
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003627196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1003627196
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2807267050
Short name T131
Test name
Test status
Simulation time 2176115321916 ps
CPU time 1375.78 seconds
Started May 02 01:23:05 PM PDT 24
Finished May 02 01:46:02 PM PDT 24
Peak memory 195176 kb
Host smart-38024c9d-d62c-48c9-943b-c1f00ea5bd2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807267050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2807267050
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1040899655
Short name T208
Test name
Test status
Simulation time 499135398952 ps
CPU time 1128.48 seconds
Started May 02 01:20:42 PM PDT 24
Finished May 02 01:39:31 PM PDT 24
Peak memory 191228 kb
Host smart-9aefcde5-13cf-4091-ba2e-835915bafb85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040899655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1040899655
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2019864253
Short name T136
Test name
Test status
Simulation time 763977771454 ps
CPU time 3764.2 seconds
Started May 02 01:18:54 PM PDT 24
Finished May 02 02:21:40 PM PDT 24
Peak memory 191240 kb
Host smart-93e19ccc-9891-4b8d-a812-0eef14075d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019864253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2019864253
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3564910285
Short name T224
Test name
Test status
Simulation time 523074711416 ps
CPU time 1815.55 seconds
Started May 02 01:25:01 PM PDT 24
Finished May 02 01:55:17 PM PDT 24
Peak memory 191140 kb
Host smart-512c3630-9f8c-4d0a-b56c-e17023efb391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564910285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3564910285
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2339976435
Short name T114
Test name
Test status
Simulation time 124109823 ps
CPU time 1.53 seconds
Started May 02 01:17:23 PM PDT 24
Finished May 02 01:17:25 PM PDT 24
Peak memory 195316 kb
Host smart-a4b21a7e-d0ef-40ab-a89c-41dbb14ba182
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339976435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2339976435
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/125.rv_timer_random.1437701481
Short name T226
Test name
Test status
Simulation time 294408821074 ps
CPU time 235.7 seconds
Started May 02 01:29:07 PM PDT 24
Finished May 02 01:33:04 PM PDT 24
Peak memory 191140 kb
Host smart-cf17dd7c-6c37-45f9-be63-d0a26664e94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437701481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1437701481
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.158914498
Short name T167
Test name
Test status
Simulation time 606352872898 ps
CPU time 1092.86 seconds
Started May 02 01:27:36 PM PDT 24
Finished May 02 01:45:50 PM PDT 24
Peak memory 191256 kb
Host smart-47d1adda-f642-4857-a152-6a9bcd97c16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158914498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.158914498
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.481778822
Short name T310
Test name
Test status
Simulation time 666704740544 ps
CPU time 2143.44 seconds
Started May 02 01:18:37 PM PDT 24
Finished May 02 01:54:21 PM PDT 24
Peak memory 191140 kb
Host smart-0f3d5d03-2f71-441b-bd71-fbcb5ab38da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481778822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.481778822
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3218814436
Short name T108
Test name
Test status
Simulation time 1146091714054 ps
CPU time 1561.57 seconds
Started May 02 01:28:50 PM PDT 24
Finished May 02 01:54:52 PM PDT 24
Peak memory 191208 kb
Host smart-ba62d23c-c305-4025-acaf-8252c8075da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218814436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3218814436
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1172201059
Short name T163
Test name
Test status
Simulation time 930602585091 ps
CPU time 480.98 seconds
Started May 02 01:18:56 PM PDT 24
Finished May 02 01:26:58 PM PDT 24
Peak memory 195712 kb
Host smart-aa44c388-53f2-4dbe-9273-59a16565c61b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172201059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1172201059
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2965600267
Short name T187
Test name
Test status
Simulation time 934024985342 ps
CPU time 2534.64 seconds
Started May 02 01:18:48 PM PDT 24
Finished May 02 02:01:04 PM PDT 24
Peak memory 191232 kb
Host smart-6b1e0e35-7011-42a3-a676-d74dc376f61b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965600267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2965600267
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.789698246
Short name T332
Test name
Test status
Simulation time 1874089156439 ps
CPU time 747.85 seconds
Started May 02 01:25:26 PM PDT 24
Finished May 02 01:37:55 PM PDT 24
Peak memory 191200 kb
Host smart-4f31f154-32f2-4f5a-a582-d0540f2baa29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789698246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
789698246
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/134.rv_timer_random.242109117
Short name T181
Test name
Test status
Simulation time 659546037885 ps
CPU time 1636.38 seconds
Started May 02 01:29:27 PM PDT 24
Finished May 02 01:56:44 PM PDT 24
Peak memory 191236 kb
Host smart-c9b7c294-2589-48b3-a6dc-ea03b0ac103d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242109117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.242109117
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.526321825
Short name T140
Test name
Test status
Simulation time 448270685729 ps
CPU time 773.62 seconds
Started May 02 01:28:44 PM PDT 24
Finished May 02 01:41:38 PM PDT 24
Peak memory 191252 kb
Host smart-10106f01-93c3-4993-9b35-040b1723b202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526321825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.526321825
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1170740161
Short name T216
Test name
Test status
Simulation time 412934324501 ps
CPU time 789.46 seconds
Started May 02 01:20:14 PM PDT 24
Finished May 02 01:33:24 PM PDT 24
Peak memory 191212 kb
Host smart-52bddbf2-a4ec-42e8-a754-15d64cb58845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170740161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1170740161
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.3917259238
Short name T262
Test name
Test status
Simulation time 568709020247 ps
CPU time 566.42 seconds
Started May 02 01:30:52 PM PDT 24
Finished May 02 01:40:19 PM PDT 24
Peak memory 191212 kb
Host smart-e599264a-5691-4ada-952d-fae761d9565b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917259238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3917259238
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.102053147
Short name T104
Test name
Test status
Simulation time 675066388174 ps
CPU time 2606.59 seconds
Started May 02 01:28:14 PM PDT 24
Finished May 02 02:11:42 PM PDT 24
Peak memory 191236 kb
Host smart-ca815741-7dd6-4033-861f-3ae6a49b6483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102053147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.102053147
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1279726621
Short name T138
Test name
Test status
Simulation time 830879396467 ps
CPU time 674.67 seconds
Started May 02 01:28:59 PM PDT 24
Finished May 02 01:40:14 PM PDT 24
Peak memory 191228 kb
Host smart-2896b8f6-1bcd-4b0d-aca7-725b17a84e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279726621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1279726621
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.4178758120
Short name T173
Test name
Test status
Simulation time 472568339960 ps
CPU time 328.08 seconds
Started May 02 01:29:51 PM PDT 24
Finished May 02 01:35:20 PM PDT 24
Peak memory 191184 kb
Host smart-56da8335-1f93-4181-bde9-2df2a50327aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178758120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4178758120
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1211561783
Short name T183
Test name
Test status
Simulation time 548305644357 ps
CPU time 1355.94 seconds
Started May 02 01:22:16 PM PDT 24
Finished May 02 01:44:53 PM PDT 24
Peak memory 191140 kb
Host smart-c5ccef5f-d979-43cb-bbc0-69b089032232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211561783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1211561783
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random.3446072204
Short name T219
Test name
Test status
Simulation time 154415308945 ps
CPU time 540.08 seconds
Started May 02 01:24:06 PM PDT 24
Finished May 02 01:33:07 PM PDT 24
Peak memory 191252 kb
Host smart-737358ee-5515-4e70-97cc-c57143e120c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446072204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3446072204
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3709431591
Short name T188
Test name
Test status
Simulation time 454080249310 ps
CPU time 2152.01 seconds
Started May 02 01:26:00 PM PDT 24
Finished May 02 02:01:53 PM PDT 24
Peak memory 191188 kb
Host smart-1abf3e0a-11c5-4481-ab77-f67a93fb4c43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709431591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3709431591
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/145.rv_timer_random.1435546965
Short name T243
Test name
Test status
Simulation time 171943575851 ps
CPU time 716.2 seconds
Started May 02 01:29:42 PM PDT 24
Finished May 02 01:41:39 PM PDT 24
Peak memory 191228 kb
Host smart-4c457806-1a49-4ee1-bc5f-2194000eff33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435546965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1435546965
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2383163603
Short name T283
Test name
Test status
Simulation time 662974933152 ps
CPU time 614.97 seconds
Started May 02 01:29:57 PM PDT 24
Finished May 02 01:40:12 PM PDT 24
Peak memory 191252 kb
Host smart-10c70e72-9089-4601-ac49-6a95b00169e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383163603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2383163603
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3986467921
Short name T340
Test name
Test status
Simulation time 132180059247 ps
CPU time 189.11 seconds
Started May 02 01:30:30 PM PDT 24
Finished May 02 01:33:40 PM PDT 24
Peak memory 191100 kb
Host smart-b7021a31-9b7b-4e8e-a28d-cf90d4dcdb34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986467921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3986467921
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2711789372
Short name T61
Test name
Test status
Simulation time 1452733666806 ps
CPU time 972.74 seconds
Started May 02 01:18:53 PM PDT 24
Finished May 02 01:35:07 PM PDT 24
Peak memory 191220 kb
Host smart-2fde075d-d423-4ca5-8538-dffa6603e4b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711789372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2711789372
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.2410391927
Short name T121
Test name
Test status
Simulation time 1322406579508 ps
CPU time 1379.82 seconds
Started May 02 01:26:54 PM PDT 24
Finished May 02 01:49:55 PM PDT 24
Peak memory 191208 kb
Host smart-dd2853b0-dde6-421c-bbb0-f4c0ea10b8b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410391927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2410391927
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3883488950
Short name T33
Test name
Test status
Simulation time 62469303 ps
CPU time 0.62 seconds
Started May 02 01:15:40 PM PDT 24
Finished May 02 01:15:43 PM PDT 24
Peak memory 191576 kb
Host smart-6715eaa1-cdc5-4f80-bb9a-aff06cd6bb6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883488950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3883488950
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1552069313
Short name T168
Test name
Test status
Simulation time 646823998586 ps
CPU time 1567.9 seconds
Started May 02 01:18:46 PM PDT 24
Finished May 02 01:44:54 PM PDT 24
Peak memory 191140 kb
Host smart-b3643305-e2ae-479d-beee-ae4cad05779c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552069313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1552069313
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.325917296
Short name T221
Test name
Test status
Simulation time 1137164881920 ps
CPU time 1645.95 seconds
Started May 02 01:19:22 PM PDT 24
Finished May 02 01:46:49 PM PDT 24
Peak memory 195748 kb
Host smart-bc7ad7eb-db2d-4962-be06-0143069b7746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325917296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
325917296
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/108.rv_timer_random.4171543866
Short name T130
Test name
Test status
Simulation time 365218440164 ps
CPU time 2267.55 seconds
Started May 02 01:28:42 PM PDT 24
Finished May 02 02:06:31 PM PDT 24
Peak memory 191160 kb
Host smart-88b04bf5-509e-4eba-82bd-1ddba6ae6151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171543866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.4171543866
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3619966882
Short name T321
Test name
Test status
Simulation time 311126193783 ps
CPU time 252.8 seconds
Started May 02 01:28:44 PM PDT 24
Finished May 02 01:32:57 PM PDT 24
Peak memory 191236 kb
Host smart-2b81a745-bfbd-4776-88dc-bb3c350459f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619966882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3619966882
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.4207958317
Short name T160
Test name
Test status
Simulation time 1339537444909 ps
CPU time 547.87 seconds
Started May 02 01:28:52 PM PDT 24
Finished May 02 01:38:00 PM PDT 24
Peak memory 191272 kb
Host smart-23b972b7-676c-4ec8-a481-2d3c160065f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207958317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4207958317
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.1429269694
Short name T267
Test name
Test status
Simulation time 286901245300 ps
CPU time 280.44 seconds
Started May 02 01:29:34 PM PDT 24
Finished May 02 01:34:15 PM PDT 24
Peak memory 193660 kb
Host smart-10b81e80-8766-4e8f-9e27-a7385384f5bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429269694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1429269694
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2186914035
Short name T297
Test name
Test status
Simulation time 244012201558 ps
CPU time 293.05 seconds
Started May 02 01:30:38 PM PDT 24
Finished May 02 01:35:32 PM PDT 24
Peak memory 191244 kb
Host smart-d76919ca-e07d-4d4d-884c-2317ad89838a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186914035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2186914035
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3881680111
Short name T54
Test name
Test status
Simulation time 148307780615 ps
CPU time 429.48 seconds
Started May 02 01:30:52 PM PDT 24
Finished May 02 01:38:03 PM PDT 24
Peak memory 191232 kb
Host smart-625f8351-e3c2-4338-a91c-f22faf308e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881680111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3881680111
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.594518305
Short name T311
Test name
Test status
Simulation time 1332603016988 ps
CPU time 693.9 seconds
Started May 02 01:30:53 PM PDT 24
Finished May 02 01:42:27 PM PDT 24
Peak memory 191256 kb
Host smart-12be876d-81e9-4078-966e-7e225a4df475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594518305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.594518305
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3097995117
Short name T159
Test name
Test status
Simulation time 49448061685 ps
CPU time 41.47 seconds
Started May 02 01:22:09 PM PDT 24
Finished May 02 01:22:51 PM PDT 24
Peak memory 191132 kb
Host smart-5cde162c-d018-42f0-9cd4-9b57337fd071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097995117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3097995117
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1981611145
Short name T81
Test name
Test status
Simulation time 23173029724 ps
CPU time 39.65 seconds
Started May 02 01:24:08 PM PDT 24
Finished May 02 01:24:48 PM PDT 24
Peak memory 183028 kb
Host smart-b535dd9e-c7bc-4efb-a6b0-bb27b01b0e5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981611145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1981611145
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random.450591455
Short name T191
Test name
Test status
Simulation time 124139450547 ps
CPU time 399.76 seconds
Started May 02 01:25:18 PM PDT 24
Finished May 02 01:31:58 PM PDT 24
Peak memory 191228 kb
Host smart-462c6d7e-cd7c-44fa-8ad3-17e06e33b39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450591455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.450591455
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3850867500
Short name T213
Test name
Test status
Simulation time 1819219073061 ps
CPU time 915.64 seconds
Started May 02 01:19:11 PM PDT 24
Finished May 02 01:34:28 PM PDT 24
Peak memory 183060 kb
Host smart-038c5644-f6c3-45f0-a7bf-a80405485e0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850867500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3850867500
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/110.rv_timer_random.3236139763
Short name T155
Test name
Test status
Simulation time 273293283259 ps
CPU time 484.68 seconds
Started May 02 01:28:42 PM PDT 24
Finished May 02 01:36:48 PM PDT 24
Peak memory 191240 kb
Host smart-54c1d2ee-1196-429d-a71d-5932e8e86a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236139763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3236139763
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.797254799
Short name T46
Test name
Test status
Simulation time 90710879022 ps
CPU time 46.15 seconds
Started May 02 01:29:08 PM PDT 24
Finished May 02 01:29:55 PM PDT 24
Peak memory 191076 kb
Host smart-e0fbf0e0-defb-4002-a7c1-554c0915dd3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797254799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.797254799
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1789595667
Short name T325
Test name
Test status
Simulation time 386993192550 ps
CPU time 742.15 seconds
Started May 02 01:29:35 PM PDT 24
Finished May 02 01:41:58 PM PDT 24
Peak memory 191192 kb
Host smart-52ebe7ac-bfbc-4460-8a44-294e851dc659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789595667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1789595667
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.92862701
Short name T180
Test name
Test status
Simulation time 188514482097 ps
CPU time 287.46 seconds
Started May 02 01:29:50 PM PDT 24
Finished May 02 01:34:38 PM PDT 24
Peak memory 191260 kb
Host smart-66f44d7e-5ba1-4af2-be1d-f0894acbfb05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92862701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.92862701
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.479848821
Short name T79
Test name
Test status
Simulation time 526023273256 ps
CPU time 402.35 seconds
Started May 02 01:20:51 PM PDT 24
Finished May 02 01:27:33 PM PDT 24
Peak memory 182956 kb
Host smart-5eda3d1a-7e3b-44dd-bf47-8bbca7daddd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479848821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.479848821
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/199.rv_timer_random.1067215726
Short name T133
Test name
Test status
Simulation time 87855507528 ps
CPU time 177.26 seconds
Started May 02 01:31:23 PM PDT 24
Finished May 02 01:34:21 PM PDT 24
Peak memory 191248 kb
Host smart-a0118d49-589a-427d-bb5f-fb8141acb301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067215726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1067215726
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1181352657
Short name T74
Test name
Test status
Simulation time 27375114 ps
CPU time 0.71 seconds
Started May 02 01:16:05 PM PDT 24
Finished May 02 01:16:07 PM PDT 24
Peak memory 191952 kb
Host smart-97d903e1-78e5-4532-a336-cbe51dba6743
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181352657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1181352657
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/106.rv_timer_random.3801729801
Short name T317
Test name
Test status
Simulation time 5459398633 ps
CPU time 11.53 seconds
Started May 02 01:28:42 PM PDT 24
Finished May 02 01:28:54 PM PDT 24
Peak memory 191208 kb
Host smart-fb17a2d9-7951-42e0-82bd-0e01f9095db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801729801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3801729801
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2975348736
Short name T319
Test name
Test status
Simulation time 36495666427 ps
CPU time 52.46 seconds
Started May 02 01:28:51 PM PDT 24
Finished May 02 01:29:44 PM PDT 24
Peak memory 191256 kb
Host smart-9ced5aa3-4097-44e1-b264-473346901c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975348736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2975348736
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3755673667
Short name T422
Test name
Test status
Simulation time 54585435350 ps
CPU time 106.68 seconds
Started May 02 01:29:01 PM PDT 24
Finished May 02 01:30:48 PM PDT 24
Peak memory 191156 kb
Host smart-84cc7db5-10fe-4ced-b2df-6f1f9e61a6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755673667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3755673667
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.2800636877
Short name T298
Test name
Test status
Simulation time 1211464687396 ps
CPU time 276.08 seconds
Started May 02 01:19:42 PM PDT 24
Finished May 02 01:24:19 PM PDT 24
Peak memory 191196 kb
Host smart-4fb312dd-0fc0-418b-8794-647267a88cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800636877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2800636877
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3169557435
Short name T240
Test name
Test status
Simulation time 22819462786 ps
CPU time 46.37 seconds
Started May 02 01:29:36 PM PDT 24
Finished May 02 01:30:24 PM PDT 24
Peak memory 183028 kb
Host smart-2edae4ba-a769-41a7-b71f-2feb6f9fc4a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169557435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3169557435
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2455436550
Short name T143
Test name
Test status
Simulation time 462269749384 ps
CPU time 638.16 seconds
Started May 02 01:30:21 PM PDT 24
Finished May 02 01:41:00 PM PDT 24
Peak memory 191244 kb
Host smart-0ca78de9-1acb-4cbf-8cc7-26cdf4e1cf34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455436550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2455436550
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.3462053082
Short name T215
Test name
Test status
Simulation time 355508683293 ps
CPU time 328.51 seconds
Started May 02 01:30:29 PM PDT 24
Finished May 02 01:35:58 PM PDT 24
Peak memory 191136 kb
Host smart-4497fefe-f4f4-44da-87a9-773cdc90d9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462053082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3462053082
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4091143938
Short name T339
Test name
Test status
Simulation time 75230879410 ps
CPU time 124.08 seconds
Started May 02 01:31:45 PM PDT 24
Finished May 02 01:33:50 PM PDT 24
Peak memory 191236 kb
Host smart-1d874cca-00c1-4a88-8802-f59db0fa20db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091143938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4091143938
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.629281150
Short name T223
Test name
Test status
Simulation time 152402000632 ps
CPU time 642.88 seconds
Started May 02 01:21:21 PM PDT 24
Finished May 02 01:32:05 PM PDT 24
Peak memory 191220 kb
Host smart-b7fd0dd0-89a2-493b-a398-91bc7831eb17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629281150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.629281150
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4187833539
Short name T256
Test name
Test status
Simulation time 992183073536 ps
CPU time 1455.62 seconds
Started May 02 01:21:57 PM PDT 24
Finished May 02 01:46:14 PM PDT 24
Peak memory 191184 kb
Host smart-d0bbcda8-e2cf-4f1b-9607-3e2bd7514f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187833539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4187833539
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.687142399
Short name T333
Test name
Test status
Simulation time 13564689707 ps
CPU time 22.03 seconds
Started May 02 01:21:58 PM PDT 24
Finished May 02 01:22:21 PM PDT 24
Peak memory 182960 kb
Host smart-3a28e67e-1dda-49c4-8138-60f40dbe15db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687142399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.687142399
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.1145444644
Short name T193
Test name
Test status
Simulation time 505215510202 ps
CPU time 281.79 seconds
Started May 02 01:22:38 PM PDT 24
Finished May 02 01:27:20 PM PDT 24
Peak memory 191256 kb
Host smart-8e7af0d9-7a2a-4959-965c-56952ae0b176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145444644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1145444644
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.56127937
Short name T137
Test name
Test status
Simulation time 186124694818 ps
CPU time 296.01 seconds
Started May 02 01:25:53 PM PDT 24
Finished May 02 01:30:49 PM PDT 24
Peak memory 191264 kb
Host smart-32041e9f-c638-49ad-9feb-0facd288e1f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56127937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.56127937
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2368865160
Short name T336
Test name
Test status
Simulation time 128875894356 ps
CPU time 140.04 seconds
Started May 02 01:26:09 PM PDT 24
Finished May 02 01:28:29 PM PDT 24
Peak memory 183064 kb
Host smart-d6a5bfdf-c2a2-4124-bc4d-350572423ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368865160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2368865160
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3830940827
Short name T171
Test name
Test status
Simulation time 2225633405762 ps
CPU time 1287.37 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:40:24 PM PDT 24
Peak memory 182984 kb
Host smart-b0f98bef-2f64-45de-9535-b3d8bb0a6696
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830940827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3830940827
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.18778940
Short name T530
Test name
Test status
Simulation time 172335257 ps
CPU time 0.84 seconds
Started May 02 01:15:26 PM PDT 24
Finished May 02 01:15:27 PM PDT 24
Peak memory 183044 kb
Host smart-c302bbb8-337e-4aeb-be6e-0c4132c77e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18778940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg
_err.18778940
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3281560743
Short name T304
Test name
Test status
Simulation time 147980834630 ps
CPU time 450.95 seconds
Started May 02 01:18:38 PM PDT 24
Finished May 02 01:26:10 PM PDT 24
Peak memory 191112 kb
Host smart-90008828-3031-49e2-ae53-c7eaa2a62c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281560743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3281560743
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/107.rv_timer_random.1656094637
Short name T212
Test name
Test status
Simulation time 486859756659 ps
CPU time 250.19 seconds
Started May 02 01:28:43 PM PDT 24
Finished May 02 01:32:54 PM PDT 24
Peak memory 191184 kb
Host smart-2c6714e5-014e-4a3a-996c-dab51dd771b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656094637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1656094637
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3975929197
Short name T305
Test name
Test status
Simulation time 263376958040 ps
CPU time 1102.09 seconds
Started May 02 01:28:42 PM PDT 24
Finished May 02 01:47:05 PM PDT 24
Peak memory 191240 kb
Host smart-e59402ca-7ec4-4875-bcde-fda3f94b0dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975929197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3975929197
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.4118131758
Short name T220
Test name
Test status
Simulation time 3209504726355 ps
CPU time 873.76 seconds
Started May 02 01:19:41 PM PDT 24
Finished May 02 01:34:15 PM PDT 24
Peak memory 191244 kb
Host smart-3c6a3de5-a112-431a-9648-32639022f71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118131758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.4118131758
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/124.rv_timer_random.1878668060
Short name T236
Test name
Test status
Simulation time 128870649931 ps
CPU time 511.04 seconds
Started May 02 01:29:01 PM PDT 24
Finished May 02 01:37:33 PM PDT 24
Peak memory 191184 kb
Host smart-e0544a4f-ce37-48ca-ac25-b2c3c67687db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878668060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1878668060
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.917232129
Short name T166
Test name
Test status
Simulation time 626870230751 ps
CPU time 319.04 seconds
Started May 02 01:29:37 PM PDT 24
Finished May 02 01:34:57 PM PDT 24
Peak memory 191228 kb
Host smart-ab0f5863-f43c-46a3-957b-f1ccf754c337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917232129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.917232129
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3019222578
Short name T271
Test name
Test status
Simulation time 1034480492901 ps
CPU time 354.5 seconds
Started May 02 01:29:41 PM PDT 24
Finished May 02 01:35:37 PM PDT 24
Peak memory 191224 kb
Host smart-1ca58a91-4f7d-4a45-afcb-8edf5cd04ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019222578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3019222578
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2270467306
Short name T254
Test name
Test status
Simulation time 250010350375 ps
CPU time 383.67 seconds
Started May 02 01:29:58 PM PDT 24
Finished May 02 01:36:23 PM PDT 24
Peak memory 191252 kb
Host smart-e9fc33b2-07d6-40e7-a1c8-eb7f12655bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270467306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2270467306
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.182306308
Short name T206
Test name
Test status
Simulation time 381833647211 ps
CPU time 255.37 seconds
Started May 02 01:29:58 PM PDT 24
Finished May 02 01:34:14 PM PDT 24
Peak memory 191256 kb
Host smart-b2214a42-f224-4fb0-8f57-be08c94a088a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182306308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.182306308
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1383559596
Short name T308
Test name
Test status
Simulation time 110486092437 ps
CPU time 1548.37 seconds
Started May 02 01:29:59 PM PDT 24
Finished May 02 01:55:48 PM PDT 24
Peak memory 191248 kb
Host smart-b46b7bae-265e-4c39-9f82-4c063da634fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383559596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1383559596
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3581689934
Short name T230
Test name
Test status
Simulation time 41655002230 ps
CPU time 154.93 seconds
Started May 02 01:20:19 PM PDT 24
Finished May 02 01:22:55 PM PDT 24
Peak memory 191092 kb
Host smart-b1223e4a-3dc9-468c-8581-0e9c0ba58780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581689934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3581689934
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3591005827
Short name T107
Test name
Test status
Simulation time 167002573673 ps
CPU time 1203.35 seconds
Started May 02 01:30:36 PM PDT 24
Finished May 02 01:50:40 PM PDT 24
Peak memory 191096 kb
Host smart-768a5b2e-05bb-492a-881e-01c4892329a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591005827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3591005827
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.4148755698
Short name T151
Test name
Test status
Simulation time 116267503840 ps
CPU time 421.35 seconds
Started May 02 01:30:44 PM PDT 24
Finished May 02 01:37:46 PM PDT 24
Peak memory 191224 kb
Host smart-dbbe1cd8-7fda-4368-83ec-742c973555fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148755698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4148755698
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.365779336
Short name T364
Test name
Test status
Simulation time 89245417689 ps
CPU time 172.44 seconds
Started May 02 01:30:59 PM PDT 24
Finished May 02 01:33:53 PM PDT 24
Peak memory 191248 kb
Host smart-469035d9-4964-4940-b78d-d8cd96dba154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365779336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.365779336
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.787562215
Short name T274
Test name
Test status
Simulation time 61801396199 ps
CPU time 248.69 seconds
Started May 02 01:31:01 PM PDT 24
Finished May 02 01:35:11 PM PDT 24
Peak memory 191228 kb
Host smart-11b3943a-ac34-46e3-ada7-298b0697c6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787562215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.787562215
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.4157533802
Short name T39
Test name
Test status
Simulation time 56583794858 ps
CPU time 604.15 seconds
Started May 02 01:21:19 PM PDT 24
Finished May 02 01:31:24 PM PDT 24
Peak memory 206016 kb
Host smart-367c8375-1551-42f4-bcf6-66528d016d9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157533802 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.4157533802
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3417675026
Short name T313
Test name
Test status
Simulation time 391505825437 ps
CPU time 635.34 seconds
Started May 02 01:22:07 PM PDT 24
Finished May 02 01:32:43 PM PDT 24
Peak memory 183024 kb
Host smart-eefc2dca-5613-4d51-b59f-1c817622eab7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417675026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3417675026
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1672209277
Short name T207
Test name
Test status
Simulation time 41727557615 ps
CPU time 20.27 seconds
Started May 02 01:22:24 PM PDT 24
Finished May 02 01:22:46 PM PDT 24
Peak memory 193828 kb
Host smart-0cde9186-d145-45f8-a310-f44014766018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672209277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1672209277
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.679337874
Short name T135
Test name
Test status
Simulation time 2752627362515 ps
CPU time 1465.45 seconds
Started May 02 01:23:07 PM PDT 24
Finished May 02 01:47:33 PM PDT 24
Peak memory 183052 kb
Host smart-6255a878-bbcc-4a44-b2db-b47e39d7430e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679337874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.679337874
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2352649009
Short name T123
Test name
Test status
Simulation time 445182307291 ps
CPU time 1015.08 seconds
Started May 02 01:23:15 PM PDT 24
Finished May 02 01:40:11 PM PDT 24
Peak memory 195928 kb
Host smart-9c005d61-7aa0-4508-80b7-cf407551ddd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352649009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2352649009
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2294332936
Short name T26
Test name
Test status
Simulation time 237881698463 ps
CPU time 412.91 seconds
Started May 02 01:25:43 PM PDT 24
Finished May 02 01:32:36 PM PDT 24
Peak memory 183052 kb
Host smart-496ca939-b8c4-4bc3-9045-01b7573000fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294332936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2294332936
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.2564560168
Short name T202
Test name
Test status
Simulation time 559858526182 ps
CPU time 625.63 seconds
Started May 02 01:25:35 PM PDT 24
Finished May 02 01:36:02 PM PDT 24
Peak memory 191228 kb
Host smart-02d87566-eec2-4491-8a90-c8f09a55bb6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564560168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2564560168
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random.3857705129
Short name T126
Test name
Test status
Simulation time 201546570723 ps
CPU time 604.77 seconds
Started May 02 01:25:58 PM PDT 24
Finished May 02 01:36:03 PM PDT 24
Peak memory 191204 kb
Host smart-870255fd-c9a0-433b-a153-926919ad1dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857705129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3857705129
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.532683630
Short name T371
Test name
Test status
Simulation time 1232203758164 ps
CPU time 582.11 seconds
Started May 02 01:26:34 PM PDT 24
Finished May 02 01:36:17 PM PDT 24
Peak memory 191236 kb
Host smart-c1280a63-2d82-4c1f-9528-d574b5f30314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532683630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
532683630
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/54.rv_timer_random.2329685160
Short name T210
Test name
Test status
Simulation time 671948812773 ps
CPU time 316.24 seconds
Started May 02 01:26:54 PM PDT 24
Finished May 02 01:32:11 PM PDT 24
Peak memory 191252 kb
Host smart-e89f6796-6445-4ffd-a58d-ea2625b4f696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329685160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2329685160
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.3429548508
Short name T176
Test name
Test status
Simulation time 274920343305 ps
CPU time 123.94 seconds
Started May 02 01:18:56 PM PDT 24
Finished May 02 01:21:01 PM PDT 24
Peak memory 191228 kb
Host smart-769f1ce0-e590-49d8-9659-520835a4dd32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429548508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3429548508
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1460332107
Short name T150
Test name
Test status
Simulation time 454678870466 ps
CPU time 264.71 seconds
Started May 02 01:27:14 PM PDT 24
Finished May 02 01:31:40 PM PDT 24
Peak memory 191184 kb
Host smart-9ef02cef-2d64-4a3b-8377-0f65b1dd4b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460332107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1460332107
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2113167127
Short name T361
Test name
Test status
Simulation time 1445334983293 ps
CPU time 720.74 seconds
Started May 02 01:19:14 PM PDT 24
Finished May 02 01:31:16 PM PDT 24
Peak memory 182996 kb
Host smart-9f369482-7980-49c1-87a2-b4b9dc20bdd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113167127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2113167127
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/72.rv_timer_random.3674610577
Short name T279
Test name
Test status
Simulation time 915120137772 ps
CPU time 797.41 seconds
Started May 02 01:27:28 PM PDT 24
Finished May 02 01:40:47 PM PDT 24
Peak memory 191212 kb
Host smart-d0b5ab28-2f27-4424-9fc0-9977ae930472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674610577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3674610577
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.1036471785
Short name T257
Test name
Test status
Simulation time 168093992523 ps
CPU time 465.58 seconds
Started May 02 01:28:16 PM PDT 24
Finished May 02 01:36:03 PM PDT 24
Peak memory 182940 kb
Host smart-0c2382f1-e251-4634-a450-302b4e0ff949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036471785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1036471785
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2622678856
Short name T228
Test name
Test status
Simulation time 460595347917 ps
CPU time 332.67 seconds
Started May 02 01:28:21 PM PDT 24
Finished May 02 01:33:54 PM PDT 24
Peak memory 191224 kb
Host smart-159dfd1c-4df6-42f5-aeab-31f4168ae0d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622678856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2622678856
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3379755775
Short name T576
Test name
Test status
Simulation time 17554644 ps
CPU time 0.65 seconds
Started May 02 01:15:41 PM PDT 24
Finished May 02 01:15:43 PM PDT 24
Peak memory 182728 kb
Host smart-57b8c1bb-6b34-4f4f-a5a2-ba680d417651
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379755775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3379755775
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1261005569
Short name T535
Test name
Test status
Simulation time 5477558306 ps
CPU time 2.61 seconds
Started May 02 01:15:41 PM PDT 24
Finished May 02 01:15:45 PM PDT 24
Peak memory 191168 kb
Host smart-0304f97f-fe12-4d5c-96cb-dcae224f448d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261005569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1261005569
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.401642410
Short name T575
Test name
Test status
Simulation time 27985729 ps
CPU time 0.56 seconds
Started May 02 01:15:34 PM PDT 24
Finished May 02 01:15:36 PM PDT 24
Peak memory 182656 kb
Host smart-e95d5f83-c94b-48ef-8816-321fd4a03334
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401642410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.401642410
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2156247500
Short name T491
Test name
Test status
Simulation time 45637797 ps
CPU time 1 seconds
Started May 02 01:15:41 PM PDT 24
Finished May 02 01:15:43 PM PDT 24
Peak memory 197440 kb
Host smart-4784b08e-3f2a-42b5-9ca7-69c022d9598c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156247500 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2156247500
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1817902174
Short name T556
Test name
Test status
Simulation time 143002933 ps
CPU time 0.54 seconds
Started May 02 01:15:39 PM PDT 24
Finished May 02 01:15:41 PM PDT 24
Peak memory 182736 kb
Host smart-b410522b-f94e-4e6e-b65d-1acda5579449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817902174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1817902174
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.720720963
Short name T468
Test name
Test status
Simulation time 43511276 ps
CPU time 0.54 seconds
Started May 02 01:15:32 PM PDT 24
Finished May 02 01:15:33 PM PDT 24
Peak memory 182608 kb
Host smart-db6bba4c-664d-4a37-9a9a-b2788d3e2579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720720963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.720720963
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3972662422
Short name T572
Test name
Test status
Simulation time 56624031 ps
CPU time 1.7 seconds
Started May 02 01:15:27 PM PDT 24
Finished May 02 01:15:29 PM PDT 24
Peak memory 197668 kb
Host smart-37417d39-cd44-4a26-bc00-fbb52bd855c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972662422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3972662422
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1081944890
Short name T578
Test name
Test status
Simulation time 293958497 ps
CPU time 3.2 seconds
Started May 02 01:15:56 PM PDT 24
Finished May 02 01:16:00 PM PDT 24
Peak memory 193564 kb
Host smart-c4788c63-21b8-4926-a200-e9b7f92aaebd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081944890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1081944890
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2560289702
Short name T488
Test name
Test status
Simulation time 18872243 ps
CPU time 0.59 seconds
Started May 02 01:15:58 PM PDT 24
Finished May 02 01:15:59 PM PDT 24
Peak memory 182676 kb
Host smart-8d98bce0-9b32-4b0b-9886-c7d57ead83fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560289702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2560289702
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2690180065
Short name T555
Test name
Test status
Simulation time 49459502 ps
CPU time 1.14 seconds
Started May 02 01:16:06 PM PDT 24
Finished May 02 01:16:08 PM PDT 24
Peak memory 197644 kb
Host smart-1a0aea98-5733-4892-b787-d6b1314c3194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690180065 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2690180065
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.166318306
Short name T112
Test name
Test status
Simulation time 15496499 ps
CPU time 0.58 seconds
Started May 02 01:15:57 PM PDT 24
Finished May 02 01:15:58 PM PDT 24
Peak memory 182748 kb
Host smart-ee2c282c-bd9e-49bc-969d-3a2261032bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166318306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.166318306
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3636435520
Short name T489
Test name
Test status
Simulation time 54629257 ps
CPU time 0.54 seconds
Started May 02 01:15:56 PM PDT 24
Finished May 02 01:15:57 PM PDT 24
Peak memory 182704 kb
Host smart-bf8f5500-895d-464b-9b2c-be59fe55cbcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636435520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3636435520
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3939398788
Short name T100
Test name
Test status
Simulation time 29459466 ps
CPU time 0.72 seconds
Started May 02 01:16:07 PM PDT 24
Finished May 02 01:16:08 PM PDT 24
Peak memory 193116 kb
Host smart-01796875-87d9-42ce-91a8-532962135b77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939398788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3939398788
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.762126513
Short name T501
Test name
Test status
Simulation time 56212354 ps
CPU time 2.97 seconds
Started May 02 01:15:49 PM PDT 24
Finished May 02 01:15:53 PM PDT 24
Peak memory 197668 kb
Host smart-248ff01d-904e-44fa-a2c8-0f486d6dcd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762126513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.762126513
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.403348499
Short name T503
Test name
Test status
Simulation time 156888771 ps
CPU time 0.77 seconds
Started May 02 01:16:06 PM PDT 24
Finished May 02 01:16:08 PM PDT 24
Peak memory 193572 kb
Host smart-0b80265e-4080-4dc2-a192-4abf31e7fdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403348499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.403348499
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.59539860
Short name T498
Test name
Test status
Simulation time 213828991 ps
CPU time 0.88 seconds
Started May 02 01:17:27 PM PDT 24
Finished May 02 01:17:29 PM PDT 24
Peak memory 197312 kb
Host smart-5a1d5398-8b3b-4516-bf7c-6c471a3edbac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59539860 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.59539860
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3435268168
Short name T541
Test name
Test status
Simulation time 22049525 ps
CPU time 0.53 seconds
Started May 02 01:17:29 PM PDT 24
Finished May 02 01:17:30 PM PDT 24
Peak memory 182308 kb
Host smart-72fb917f-4f62-4ee1-86e4-fbfa3a7f51ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435268168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3435268168
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.4173657788
Short name T505
Test name
Test status
Simulation time 14433544 ps
CPU time 0.51 seconds
Started May 02 01:17:29 PM PDT 24
Finished May 02 01:17:30 PM PDT 24
Peak memory 182088 kb
Host smart-391bcfb3-d998-4bf0-beda-aa568e32a99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173657788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.4173657788
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1298519431
Short name T515
Test name
Test status
Simulation time 122242797 ps
CPU time 0.77 seconds
Started May 02 01:17:28 PM PDT 24
Finished May 02 01:17:29 PM PDT 24
Peak memory 191712 kb
Host smart-310b7020-afe1-46df-bad8-9096d28d200b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298519431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1298519431
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2326934701
Short name T504
Test name
Test status
Simulation time 144325798 ps
CPU time 2.03 seconds
Started May 02 01:17:22 PM PDT 24
Finished May 02 01:17:24 PM PDT 24
Peak memory 197644 kb
Host smart-c0b3ba7a-f4a4-4c9d-956a-483358639b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326934701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2326934701
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3154900950
Short name T517
Test name
Test status
Simulation time 89041847 ps
CPU time 1.16 seconds
Started May 02 01:17:35 PM PDT 24
Finished May 02 01:17:37 PM PDT 24
Peak memory 197648 kb
Host smart-57fe36f8-6aa5-41df-9465-baab95bbadb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154900950 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3154900950
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1602588505
Short name T77
Test name
Test status
Simulation time 26438196 ps
CPU time 0.58 seconds
Started May 02 01:17:28 PM PDT 24
Finished May 02 01:17:30 PM PDT 24
Peak memory 182744 kb
Host smart-7be18ebd-4ec7-46d9-91e4-8671090a2893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602588505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1602588505
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3366228296
Short name T559
Test name
Test status
Simulation time 13131676 ps
CPU time 0.51 seconds
Started May 02 01:17:28 PM PDT 24
Finished May 02 01:17:29 PM PDT 24
Peak memory 182012 kb
Host smart-c17e82e8-3553-4ad6-bf16-118b802f4da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366228296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3366228296
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1437998574
Short name T96
Test name
Test status
Simulation time 14476413 ps
CPU time 0.61 seconds
Started May 02 01:17:36 PM PDT 24
Finished May 02 01:17:37 PM PDT 24
Peak memory 192036 kb
Host smart-223480c4-ddee-409e-b7b5-cbe9f77427c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437998574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1437998574
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.4137354911
Short name T560
Test name
Test status
Simulation time 73140330 ps
CPU time 1.85 seconds
Started May 02 01:17:27 PM PDT 24
Finished May 02 01:17:29 PM PDT 24
Peak memory 196996 kb
Host smart-7ec8b653-8e52-45ef-ad09-b49f3b3cc69f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137354911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.4137354911
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.109901814
Short name T544
Test name
Test status
Simulation time 277700411 ps
CPU time 1.06 seconds
Started May 02 01:17:27 PM PDT 24
Finished May 02 01:17:29 PM PDT 24
Peak memory 195288 kb
Host smart-4f4acd44-a546-4d7e-8be5-5d57d7e99f11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109901814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.109901814
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2687637001
Short name T531
Test name
Test status
Simulation time 33774555 ps
CPU time 1.44 seconds
Started May 02 01:17:35 PM PDT 24
Finished May 02 01:17:37 PM PDT 24
Peak memory 197648 kb
Host smart-41fb2a93-9048-44fd-a42b-7ad265577cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687637001 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2687637001
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3857148742
Short name T481
Test name
Test status
Simulation time 14960895 ps
CPU time 0.54 seconds
Started May 02 01:17:35 PM PDT 24
Finished May 02 01:17:37 PM PDT 24
Peak memory 182700 kb
Host smart-355e31de-bf67-4017-823f-139085d96f9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857148742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3857148742
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1911867829
Short name T529
Test name
Test status
Simulation time 56864199 ps
CPU time 0.58 seconds
Started May 02 01:17:36 PM PDT 24
Finished May 02 01:17:37 PM PDT 24
Peak memory 182136 kb
Host smart-1c3d3d9b-31ce-4600-8407-1cd3cea51c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911867829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1911867829
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.361335287
Short name T97
Test name
Test status
Simulation time 15419945 ps
CPU time 0.61 seconds
Started May 02 01:17:36 PM PDT 24
Finished May 02 01:17:37 PM PDT 24
Peak memory 191624 kb
Host smart-006ec4dc-882d-4b5b-b78d-2f1816928843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361335287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.361335287
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3820736518
Short name T513
Test name
Test status
Simulation time 172299963 ps
CPU time 1 seconds
Started May 02 01:17:35 PM PDT 24
Finished May 02 01:17:37 PM PDT 24
Peak memory 197052 kb
Host smart-d904a50c-5a9b-4118-872d-02b34a96248e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820736518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3820736518
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1260493454
Short name T120
Test name
Test status
Simulation time 139693054 ps
CPU time 1.37 seconds
Started May 02 01:17:35 PM PDT 24
Finished May 02 01:17:37 PM PDT 24
Peak memory 194436 kb
Host smart-1e3f7687-86a2-446a-a64b-485df22e0a25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260493454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1260493454
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4011290217
Short name T31
Test name
Test status
Simulation time 23510390 ps
CPU time 0.72 seconds
Started May 02 01:17:41 PM PDT 24
Finished May 02 01:17:42 PM PDT 24
Peak memory 195256 kb
Host smart-cd893006-160a-4964-afc8-bc05e105393d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011290217 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4011290217
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3231902561
Short name T92
Test name
Test status
Simulation time 43342929 ps
CPU time 0.57 seconds
Started May 02 01:17:45 PM PDT 24
Finished May 02 01:17:46 PM PDT 24
Peak memory 182740 kb
Host smart-fa14367a-708a-4626-b7ca-d78c2cb1c9f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231902561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3231902561
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.155149119
Short name T497
Test name
Test status
Simulation time 16306488 ps
CPU time 0.56 seconds
Started May 02 01:17:43 PM PDT 24
Finished May 02 01:17:44 PM PDT 24
Peak memory 182556 kb
Host smart-1b458cba-68e4-44f2-8644-83df2901a430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155149119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.155149119
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1622217466
Short name T547
Test name
Test status
Simulation time 113524098 ps
CPU time 0.69 seconds
Started May 02 01:17:42 PM PDT 24
Finished May 02 01:17:43 PM PDT 24
Peak memory 191680 kb
Host smart-2a457ac4-d3bd-4044-b082-5624ba51414a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622217466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1622217466
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.898526027
Short name T533
Test name
Test status
Simulation time 182629594 ps
CPU time 1.74 seconds
Started May 02 01:17:43 PM PDT 24
Finished May 02 01:17:45 PM PDT 24
Peak memory 197552 kb
Host smart-55b93444-f0d9-4c36-aa32-9623bcc0a896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898526027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.898526027
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1921134697
Short name T115
Test name
Test status
Simulation time 163429662 ps
CPU time 0.85 seconds
Started May 02 01:17:43 PM PDT 24
Finished May 02 01:17:44 PM PDT 24
Peak memory 182976 kb
Host smart-8397c762-aa25-40a6-8950-ce514b2debea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921134697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1921134697
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.662862507
Short name T569
Test name
Test status
Simulation time 53296493 ps
CPU time 1.34 seconds
Started May 02 01:17:52 PM PDT 24
Finished May 02 01:17:54 PM PDT 24
Peak memory 197572 kb
Host smart-8b738b61-2a00-4401-bad4-447e5c6aa57e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662862507 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.662862507
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.349464971
Short name T91
Test name
Test status
Simulation time 45720737 ps
CPU time 0.59 seconds
Started May 02 01:17:50 PM PDT 24
Finished May 02 01:17:51 PM PDT 24
Peak memory 182720 kb
Host smart-d3e8d339-4016-4894-997f-06de46695466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349464971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.349464971
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.963521969
Short name T502
Test name
Test status
Simulation time 18298123 ps
CPU time 0.53 seconds
Started May 02 01:17:50 PM PDT 24
Finished May 02 01:17:52 PM PDT 24
Peak memory 182604 kb
Host smart-a0bb5753-bfd0-4718-9ebc-72a4551f4676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963521969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.963521969
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1002681756
Short name T103
Test name
Test status
Simulation time 57958643 ps
CPU time 0.64 seconds
Started May 02 01:17:52 PM PDT 24
Finished May 02 01:17:53 PM PDT 24
Peak memory 192068 kb
Host smart-ca8a7809-1396-4b85-b36e-fda4a25f9230
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002681756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1002681756
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2196592215
Short name T567
Test name
Test status
Simulation time 452652809 ps
CPU time 1.19 seconds
Started May 02 01:17:52 PM PDT 24
Finished May 02 01:17:54 PM PDT 24
Peak memory 197468 kb
Host smart-954863ac-915f-434e-883f-e507e50e15d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196592215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2196592215
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.836736194
Short name T30
Test name
Test status
Simulation time 671198168 ps
CPU time 0.79 seconds
Started May 02 01:17:53 PM PDT 24
Finished May 02 01:17:54 PM PDT 24
Peak memory 193532 kb
Host smart-69133c4a-bbdd-4258-909f-f82288d7b051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836736194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.836736194
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.966918427
Short name T564
Test name
Test status
Simulation time 57240150 ps
CPU time 0.76 seconds
Started May 02 01:17:51 PM PDT 24
Finished May 02 01:17:53 PM PDT 24
Peak memory 195132 kb
Host smart-f3251a28-7531-4b75-9638-1008da5e6513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966918427 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.966918427
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4287682783
Short name T95
Test name
Test status
Simulation time 56961285 ps
CPU time 0.56 seconds
Started May 02 01:17:52 PM PDT 24
Finished May 02 01:17:54 PM PDT 24
Peak memory 191896 kb
Host smart-1a2530ee-1f08-441e-9942-d4447c6b737c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287682783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4287682783
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1609439724
Short name T545
Test name
Test status
Simulation time 101872130 ps
CPU time 0.5 seconds
Started May 02 01:17:52 PM PDT 24
Finished May 02 01:17:54 PM PDT 24
Peak memory 182320 kb
Host smart-f231174c-d6dc-43bf-80e7-5301b875f55d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609439724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1609439724
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.957881434
Short name T522
Test name
Test status
Simulation time 18639174 ps
CPU time 0.57 seconds
Started May 02 01:17:51 PM PDT 24
Finished May 02 01:17:52 PM PDT 24
Peak memory 191928 kb
Host smart-35c91845-8840-41bf-98a1-dc6740d01709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957881434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.957881434
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1964458817
Short name T553
Test name
Test status
Simulation time 72517259 ps
CPU time 0.98 seconds
Started May 02 01:17:51 PM PDT 24
Finished May 02 01:17:53 PM PDT 24
Peak memory 197384 kb
Host smart-434bcb06-c2f3-47f4-b5af-b8e7773da397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964458817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1964458817
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1084300097
Short name T119
Test name
Test status
Simulation time 83014951 ps
CPU time 1.06 seconds
Started May 02 01:17:51 PM PDT 24
Finished May 02 01:17:53 PM PDT 24
Peak memory 183240 kb
Host smart-a3a0f1e6-0edc-4889-b1a7-bb89040d2fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084300097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1084300097
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3101877680
Short name T577
Test name
Test status
Simulation time 36817326 ps
CPU time 1.49 seconds
Started May 02 01:18:00 PM PDT 24
Finished May 02 01:18:02 PM PDT 24
Peak memory 197648 kb
Host smart-10a6dc6a-5b7a-4448-ba6e-b5390bb344f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101877680 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3101877680
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3194720540
Short name T566
Test name
Test status
Simulation time 54806641 ps
CPU time 0.57 seconds
Started May 02 01:17:59 PM PDT 24
Finished May 02 01:18:00 PM PDT 24
Peak memory 182740 kb
Host smart-fa657b26-b424-4554-b9e9-61ffba7d29a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194720540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3194720540
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2870311061
Short name T570
Test name
Test status
Simulation time 26598352 ps
CPU time 0.53 seconds
Started May 02 01:18:00 PM PDT 24
Finished May 02 01:18:01 PM PDT 24
Peak memory 182612 kb
Host smart-38a4d093-9a81-46f9-8d02-0649438c6861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870311061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2870311061
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2499319611
Short name T508
Test name
Test status
Simulation time 18187263 ps
CPU time 0.6 seconds
Started May 02 01:18:09 PM PDT 24
Finished May 02 01:18:11 PM PDT 24
Peak memory 192100 kb
Host smart-cd549dc2-db11-466d-883f-d15e52231c3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499319611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2499319611
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2828573929
Short name T538
Test name
Test status
Simulation time 141785795 ps
CPU time 2.28 seconds
Started May 02 01:17:58 PM PDT 24
Finished May 02 01:18:01 PM PDT 24
Peak memory 197552 kb
Host smart-fef2ad90-b715-4257-ad82-0c8147af378c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828573929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2828573929
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1651907965
Short name T512
Test name
Test status
Simulation time 457527876 ps
CPU time 1.37 seconds
Started May 02 01:17:59 PM PDT 24
Finished May 02 01:18:02 PM PDT 24
Peak memory 195208 kb
Host smart-f3cbe160-e1a1-494e-beae-a226a16d8d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651907965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1651907965
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4221385489
Short name T495
Test name
Test status
Simulation time 14635395 ps
CPU time 0.66 seconds
Started May 02 01:18:05 PM PDT 24
Finished May 02 01:18:07 PM PDT 24
Peak memory 194316 kb
Host smart-73aa02ed-09a1-4201-8502-ebfa5348a374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221385489 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4221385489
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2474243125
Short name T53
Test name
Test status
Simulation time 14835258 ps
CPU time 0.57 seconds
Started May 02 01:18:11 PM PDT 24
Finished May 02 01:18:12 PM PDT 24
Peak memory 182728 kb
Host smart-d44519a9-3d5e-4cc6-9000-90c9ab451676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474243125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2474243125
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2842893826
Short name T524
Test name
Test status
Simulation time 25817590 ps
CPU time 0.52 seconds
Started May 02 01:18:07 PM PDT 24
Finished May 02 01:18:08 PM PDT 24
Peak memory 182092 kb
Host smart-6769b942-1604-4868-9b3c-e1cb20e462e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842893826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2842893826
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2815172490
Short name T516
Test name
Test status
Simulation time 208882093 ps
CPU time 0.71 seconds
Started May 02 01:18:06 PM PDT 24
Finished May 02 01:18:07 PM PDT 24
Peak memory 191740 kb
Host smart-156b0ac1-782b-4b97-97a1-1b9bac18e6ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815172490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2815172490
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3110124215
Short name T51
Test name
Test status
Simulation time 1279894217 ps
CPU time 1.87 seconds
Started May 02 01:17:59 PM PDT 24
Finished May 02 01:18:01 PM PDT 24
Peak memory 197508 kb
Host smart-f6e87770-25a8-4228-a29d-341b527a672b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110124215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3110124215
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3053608284
Short name T116
Test name
Test status
Simulation time 40497151 ps
CPU time 0.81 seconds
Started May 02 01:18:11 PM PDT 24
Finished May 02 01:18:12 PM PDT 24
Peak memory 193424 kb
Host smart-f4158ce6-beb5-4e91-9103-8eaccc51e5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053608284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3053608284
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3865284076
Short name T525
Test name
Test status
Simulation time 19197555 ps
CPU time 0.84 seconds
Started May 02 01:18:10 PM PDT 24
Finished May 02 01:18:11 PM PDT 24
Peak memory 196304 kb
Host smart-092f888a-94a2-4933-8579-3a37d0d55ecb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865284076 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3865284076
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2481730743
Short name T474
Test name
Test status
Simulation time 53462321 ps
CPU time 0.63 seconds
Started May 02 01:18:07 PM PDT 24
Finished May 02 01:18:09 PM PDT 24
Peak memory 182776 kb
Host smart-d9007d80-350e-442f-b78e-3e86b265b7cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481730743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2481730743
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2246607069
Short name T542
Test name
Test status
Simulation time 26289368 ps
CPU time 0.53 seconds
Started May 02 01:18:08 PM PDT 24
Finished May 02 01:18:09 PM PDT 24
Peak memory 181980 kb
Host smart-e89c9035-780d-4a85-ae86-b49440d95423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246607069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2246607069
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.441211283
Short name T102
Test name
Test status
Simulation time 151591041 ps
CPU time 0.82 seconds
Started May 02 01:18:06 PM PDT 24
Finished May 02 01:18:07 PM PDT 24
Peak memory 193440 kb
Host smart-55b83fac-8563-446d-9023-5fee8cd81543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441211283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.441211283
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2817128712
Short name T499
Test name
Test status
Simulation time 105796440 ps
CPU time 2.04 seconds
Started May 02 01:18:12 PM PDT 24
Finished May 02 01:18:15 PM PDT 24
Peak memory 197564 kb
Host smart-f9e0bb05-ebb1-4563-821d-95d8c320b780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817128712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2817128712
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.308971350
Short name T500
Test name
Test status
Simulation time 153904014 ps
CPU time 0.77 seconds
Started May 02 01:18:10 PM PDT 24
Finished May 02 01:18:11 PM PDT 24
Peak memory 183292 kb
Host smart-51480fd0-99f7-4dc0-b599-ea63ae36c558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308971350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.308971350
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1238244407
Short name T461
Test name
Test status
Simulation time 37388052 ps
CPU time 0.9 seconds
Started May 02 01:18:11 PM PDT 24
Finished May 02 01:18:13 PM PDT 24
Peak memory 196796 kb
Host smart-84ee7cde-f8c8-4628-b47f-f929a345b38c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238244407 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1238244407
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3585876936
Short name T552
Test name
Test status
Simulation time 80844182 ps
CPU time 0.65 seconds
Started May 02 01:18:11 PM PDT 24
Finished May 02 01:18:13 PM PDT 24
Peak memory 182652 kb
Host smart-f7e7b4c5-c92b-4ab9-bf11-5b33baf7e61b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585876936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3585876936
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1051685041
Short name T462
Test name
Test status
Simulation time 28218038 ps
CPU time 0.54 seconds
Started May 02 01:18:11 PM PDT 24
Finished May 02 01:18:12 PM PDT 24
Peak memory 182560 kb
Host smart-1b9890f3-34a9-4324-a874-6c935d031a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051685041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1051685041
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1193020279
Short name T101
Test name
Test status
Simulation time 61307413 ps
CPU time 0.73 seconds
Started May 02 01:18:07 PM PDT 24
Finished May 02 01:18:09 PM PDT 24
Peak memory 193412 kb
Host smart-a9be2d06-7abd-429f-a509-656417f35400
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193020279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1193020279
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.247364030
Short name T465
Test name
Test status
Simulation time 155571310 ps
CPU time 1.79 seconds
Started May 02 01:18:07 PM PDT 24
Finished May 02 01:18:09 PM PDT 24
Peak memory 197560 kb
Host smart-979269bb-e621-47a4-8a91-6494ca7c1150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247364030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.247364030
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.474042293
Short name T537
Test name
Test status
Simulation time 115123318 ps
CPU time 1.31 seconds
Started May 02 01:18:07 PM PDT 24
Finished May 02 01:18:09 PM PDT 24
Peak memory 183144 kb
Host smart-4b5fb9cc-7612-4c0c-b3bb-8523d633f003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474042293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.474042293
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2774970214
Short name T483
Test name
Test status
Simulation time 45668823 ps
CPU time 0.61 seconds
Started May 02 01:16:15 PM PDT 24
Finished May 02 01:16:17 PM PDT 24
Peak memory 182716 kb
Host smart-905ab3fa-f971-4c03-9dae-3205e1d6c97e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774970214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2774970214
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1541079305
Short name T475
Test name
Test status
Simulation time 2472359696 ps
CPU time 3.55 seconds
Started May 02 01:16:17 PM PDT 24
Finished May 02 01:16:21 PM PDT 24
Peak memory 191088 kb
Host smart-c449ec16-2b98-4b6c-9e45-da3587a9cbd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541079305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1541079305
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2838180819
Short name T76
Test name
Test status
Simulation time 14662770 ps
CPU time 0.55 seconds
Started May 02 01:16:16 PM PDT 24
Finished May 02 01:16:18 PM PDT 24
Peak memory 182744 kb
Host smart-ca4fb599-3c94-4df1-a798-b96e80c06407
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838180819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2838180819
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3981464014
Short name T514
Test name
Test status
Simulation time 71500990 ps
CPU time 0.95 seconds
Started May 02 01:16:25 PM PDT 24
Finished May 02 01:16:27 PM PDT 24
Peak memory 197384 kb
Host smart-7cc3064d-cf0b-49d3-a7d2-cdd836cbcc87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981464014 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3981464014
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3532478538
Short name T50
Test name
Test status
Simulation time 14501492 ps
CPU time 0.58 seconds
Started May 02 01:16:16 PM PDT 24
Finished May 02 01:16:17 PM PDT 24
Peak memory 182768 kb
Host smart-f01e40fa-8930-42a0-a343-5891e1a5698d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532478538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3532478538
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2656953146
Short name T457
Test name
Test status
Simulation time 33901338 ps
CPU time 0.51 seconds
Started May 02 01:16:15 PM PDT 24
Finished May 02 01:16:17 PM PDT 24
Peak memory 182116 kb
Host smart-cfe09b6a-bb74-4107-8d2c-3dbd9d61cd77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656953146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2656953146
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4259437058
Short name T565
Test name
Test status
Simulation time 27469353 ps
CPU time 0.7 seconds
Started May 02 01:16:16 PM PDT 24
Finished May 02 01:16:17 PM PDT 24
Peak memory 192312 kb
Host smart-7f51d88e-ff54-45c0-b0a1-f31fcf1bdd6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259437058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4259437058
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3884297102
Short name T548
Test name
Test status
Simulation time 60824575 ps
CPU time 1.24 seconds
Started May 02 01:16:12 PM PDT 24
Finished May 02 01:16:13 PM PDT 24
Peak memory 197524 kb
Host smart-dfa344f0-0591-4106-9aa6-d0512edfac2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884297102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3884297102
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2259569094
Short name T28
Test name
Test status
Simulation time 46009212 ps
CPU time 0.81 seconds
Started May 02 01:16:06 PM PDT 24
Finished May 02 01:16:07 PM PDT 24
Peak memory 193584 kb
Host smart-891946d6-8edd-4f8e-abfd-df5fe17128ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259569094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2259569094
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.954850868
Short name T509
Test name
Test status
Simulation time 32892172 ps
CPU time 0.56 seconds
Started May 02 01:18:15 PM PDT 24
Finished May 02 01:18:16 PM PDT 24
Peak memory 182604 kb
Host smart-f3e3cf0b-47f2-4e67-be2c-fee30bec6ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954850868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.954850868
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.983466574
Short name T469
Test name
Test status
Simulation time 49670512 ps
CPU time 0.55 seconds
Started May 02 01:18:14 PM PDT 24
Finished May 02 01:18:16 PM PDT 24
Peak memory 182592 kb
Host smart-e7b6c2b6-f34e-4a2a-8623-2fb7299704ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983466574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.983466574
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.125060211
Short name T558
Test name
Test status
Simulation time 33454738 ps
CPU time 0.51 seconds
Started May 02 01:18:15 PM PDT 24
Finished May 02 01:18:16 PM PDT 24
Peak memory 182568 kb
Host smart-983fa5b7-91e8-4a3e-afb9-7a7e9c19c36a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125060211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.125060211
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1059267755
Short name T574
Test name
Test status
Simulation time 14117794 ps
CPU time 0.52 seconds
Started May 02 01:18:14 PM PDT 24
Finished May 02 01:18:15 PM PDT 24
Peak memory 182068 kb
Host smart-b0533505-28f2-439b-bf1f-9db17f2a7db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059267755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1059267755
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.371697202
Short name T459
Test name
Test status
Simulation time 13053709 ps
CPU time 0.64 seconds
Started May 02 01:18:16 PM PDT 24
Finished May 02 01:18:18 PM PDT 24
Peak memory 182604 kb
Host smart-c879e755-1027-4af7-8d3a-a26431e83e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371697202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.371697202
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3102715369
Short name T485
Test name
Test status
Simulation time 63763315 ps
CPU time 0.54 seconds
Started May 02 01:18:16 PM PDT 24
Finished May 02 01:18:18 PM PDT 24
Peak memory 182576 kb
Host smart-93a208f6-738c-4a49-91cf-2a85ccdd1671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102715369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3102715369
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2308886431
Short name T490
Test name
Test status
Simulation time 48334291 ps
CPU time 0.51 seconds
Started May 02 01:18:15 PM PDT 24
Finished May 02 01:18:16 PM PDT 24
Peak memory 182032 kb
Host smart-46b55a04-3204-437b-b8f8-ad1dea4d7718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308886431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2308886431
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3502007236
Short name T526
Test name
Test status
Simulation time 40554248 ps
CPU time 0.56 seconds
Started May 02 01:18:16 PM PDT 24
Finished May 02 01:18:18 PM PDT 24
Peak memory 182584 kb
Host smart-22769a9a-18ea-4b72-8d3a-9fd8de1fbaf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502007236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3502007236
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2637650815
Short name T519
Test name
Test status
Simulation time 13014312 ps
CPU time 0.6 seconds
Started May 02 01:18:15 PM PDT 24
Finished May 02 01:18:17 PM PDT 24
Peak memory 182592 kb
Host smart-1492042d-1213-49df-a19e-7a8ee8f56264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637650815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2637650815
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3380662014
Short name T484
Test name
Test status
Simulation time 43941026 ps
CPU time 0.55 seconds
Started May 02 01:18:16 PM PDT 24
Finished May 02 01:18:17 PM PDT 24
Peak memory 182468 kb
Host smart-c5d9cd65-099d-4ccc-a261-2f96ea7aa3b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380662014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3380662014
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.725941882
Short name T90
Test name
Test status
Simulation time 164627494 ps
CPU time 0.75 seconds
Started May 02 01:16:30 PM PDT 24
Finished May 02 01:16:31 PM PDT 24
Peak memory 182776 kb
Host smart-26eb7f04-9a19-4cc4-9443-607c1b78b720
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725941882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.725941882
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3908515618
Short name T75
Test name
Test status
Simulation time 971853464 ps
CPU time 2.63 seconds
Started May 02 01:16:24 PM PDT 24
Finished May 02 01:16:28 PM PDT 24
Peak memory 193580 kb
Host smart-53156c4a-4551-4448-9d5d-f6d1e3266f09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908515618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3908515618
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.758416909
Short name T52
Test name
Test status
Simulation time 24322671 ps
CPU time 0.69 seconds
Started May 02 01:16:39 PM PDT 24
Finished May 02 01:16:41 PM PDT 24
Peak memory 194296 kb
Host smart-ddc1e934-a4e9-4326-90ea-3f9ac16e586b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758416909 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.758416909
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1978009229
Short name T94
Test name
Test status
Simulation time 33186182 ps
CPU time 0.57 seconds
Started May 02 01:16:25 PM PDT 24
Finished May 02 01:16:27 PM PDT 24
Peak memory 182736 kb
Host smart-dc0ff5f2-36c2-44aa-9656-90f616ced0f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978009229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1978009229
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1452828838
Short name T486
Test name
Test status
Simulation time 16062172 ps
CPU time 0.56 seconds
Started May 02 01:16:25 PM PDT 24
Finished May 02 01:16:26 PM PDT 24
Peak memory 182552 kb
Host smart-25303fea-2f6e-4747-8e26-4f59493c45f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452828838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1452828838
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3753790499
Short name T99
Test name
Test status
Simulation time 19580933 ps
CPU time 0.61 seconds
Started May 02 01:16:31 PM PDT 24
Finished May 02 01:16:32 PM PDT 24
Peak memory 191492 kb
Host smart-efbb1072-eb9a-4fcc-978c-b26ab533d499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753790499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3753790499
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.380605364
Short name T536
Test name
Test status
Simulation time 77183591 ps
CPU time 1.78 seconds
Started May 02 01:16:25 PM PDT 24
Finished May 02 01:16:27 PM PDT 24
Peak memory 197564 kb
Host smart-e9a65004-7154-4a20-9f0f-11822858167f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380605364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.380605364
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2768414511
Short name T580
Test name
Test status
Simulation time 319690754 ps
CPU time 1.36 seconds
Started May 02 01:16:23 PM PDT 24
Finished May 02 01:16:25 PM PDT 24
Peak memory 195264 kb
Host smart-7dda4ad8-c007-49d9-b800-5d425c156a30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768414511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2768414511
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.340423303
Short name T532
Test name
Test status
Simulation time 57663032 ps
CPU time 0.53 seconds
Started May 02 01:18:30 PM PDT 24
Finished May 02 01:18:31 PM PDT 24
Peak memory 182300 kb
Host smart-81f21604-d6d2-42d2-b409-d2ac5deeb35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340423303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.340423303
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3183222305
Short name T518
Test name
Test status
Simulation time 37781136 ps
CPU time 0.5 seconds
Started May 02 01:18:29 PM PDT 24
Finished May 02 01:18:30 PM PDT 24
Peak memory 182300 kb
Host smart-026f2430-f586-433d-8335-679e586e31b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183222305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3183222305
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.394975960
Short name T471
Test name
Test status
Simulation time 17171859 ps
CPU time 0.57 seconds
Started May 02 01:18:29 PM PDT 24
Finished May 02 01:18:30 PM PDT 24
Peak memory 182576 kb
Host smart-f3779cd1-01aa-4f69-bf6d-34063a67e006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394975960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.394975960
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3042413017
Short name T523
Test name
Test status
Simulation time 23309785 ps
CPU time 0.54 seconds
Started May 02 01:18:28 PM PDT 24
Finished May 02 01:18:29 PM PDT 24
Peak memory 182248 kb
Host smart-b088cf2c-d92a-4d9a-8339-5ded3c6e92d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042413017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3042413017
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.80705336
Short name T476
Test name
Test status
Simulation time 66699802 ps
CPU time 0.57 seconds
Started May 02 01:18:31 PM PDT 24
Finished May 02 01:18:32 PM PDT 24
Peak memory 182656 kb
Host smart-ffe33312-846a-4bf7-935f-5e284de1399b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80705336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.80705336
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1887863176
Short name T460
Test name
Test status
Simulation time 22207503 ps
CPU time 0.54 seconds
Started May 02 01:18:27 PM PDT 24
Finished May 02 01:18:28 PM PDT 24
Peak memory 182724 kb
Host smart-ae44c297-8d21-44af-9240-2af734bde7a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887863176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1887863176
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4056219572
Short name T496
Test name
Test status
Simulation time 65567613 ps
CPU time 0.56 seconds
Started May 02 01:18:31 PM PDT 24
Finished May 02 01:18:32 PM PDT 24
Peak memory 182668 kb
Host smart-5013cebf-8423-45a6-af20-4da04136c5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056219572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4056219572
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.754802869
Short name T464
Test name
Test status
Simulation time 48024644 ps
CPU time 0.53 seconds
Started May 02 01:18:37 PM PDT 24
Finished May 02 01:18:38 PM PDT 24
Peak memory 182052 kb
Host smart-316af2d9-c72b-4ae6-90cf-d1aa4cb47192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754802869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.754802869
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2063239355
Short name T546
Test name
Test status
Simulation time 40983632 ps
CPU time 0.53 seconds
Started May 02 01:18:36 PM PDT 24
Finished May 02 01:18:37 PM PDT 24
Peak memory 182224 kb
Host smart-4bfca497-f2a2-43b8-ba73-cf2d23ffd6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063239355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2063239355
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4229771373
Short name T579
Test name
Test status
Simulation time 18005608 ps
CPU time 0.57 seconds
Started May 02 01:18:41 PM PDT 24
Finished May 02 01:18:42 PM PDT 24
Peak memory 182684 kb
Host smart-02986ecb-c57c-4afa-af1b-3d2efd6af413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229771373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4229771373
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1231617695
Short name T88
Test name
Test status
Simulation time 156076108 ps
CPU time 0.81 seconds
Started May 02 01:16:48 PM PDT 24
Finished May 02 01:16:49 PM PDT 24
Peak memory 182736 kb
Host smart-d7db97d9-9c9e-4235-a20c-0b988230faab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231617695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1231617695
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2776130002
Short name T493
Test name
Test status
Simulation time 1055591601 ps
CPU time 3.42 seconds
Started May 02 01:16:48 PM PDT 24
Finished May 02 01:16:52 PM PDT 24
Peak memory 182792 kb
Host smart-48483d58-43a8-4afd-96f8-f97e602066b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776130002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2776130002
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.30256255
Short name T540
Test name
Test status
Simulation time 59757580 ps
CPU time 0.57 seconds
Started May 02 01:16:38 PM PDT 24
Finished May 02 01:16:39 PM PDT 24
Peak memory 182640 kb
Host smart-eb3d7e80-cd20-4d5e-8216-4593b59add5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30256255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_res
et.30256255
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.959241140
Short name T458
Test name
Test status
Simulation time 80515840 ps
CPU time 1.02 seconds
Started May 02 01:16:48 PM PDT 24
Finished May 02 01:16:50 PM PDT 24
Peak memory 197456 kb
Host smart-0b5d8250-31c6-43c3-98a9-7b9611bbfc9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959241140 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.959241140
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.382339638
Short name T32
Test name
Test status
Simulation time 19146070 ps
CPU time 0.55 seconds
Started May 02 01:16:39 PM PDT 24
Finished May 02 01:16:40 PM PDT 24
Peak memory 182724 kb
Host smart-3fa4045d-6603-42d1-b9b8-e3ac9a5735d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382339638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.382339638
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2528453349
Short name T557
Test name
Test status
Simulation time 55725080 ps
CPU time 0.55 seconds
Started May 02 01:16:39 PM PDT 24
Finished May 02 01:16:40 PM PDT 24
Peak memory 182548 kb
Host smart-f5e02752-05c5-4cb3-a022-64edc70d5b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528453349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2528453349
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2024272958
Short name T563
Test name
Test status
Simulation time 18881767 ps
CPU time 0.59 seconds
Started May 02 01:16:49 PM PDT 24
Finished May 02 01:16:50 PM PDT 24
Peak memory 191520 kb
Host smart-36e5b999-b44d-4ef3-a2b3-2a105f1d2bf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024272958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2024272958
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3867637787
Short name T573
Test name
Test status
Simulation time 179057602 ps
CPU time 2.43 seconds
Started May 02 01:16:38 PM PDT 24
Finished May 02 01:16:41 PM PDT 24
Peak memory 197592 kb
Host smart-41b6ad5a-8410-4bc1-a0eb-3da4837a6658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867637787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3867637787
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2620710904
Short name T562
Test name
Test status
Simulation time 80210256 ps
CPU time 1.16 seconds
Started May 02 01:16:39 PM PDT 24
Finished May 02 01:16:40 PM PDT 24
Peak memory 183576 kb
Host smart-09037f95-c8a3-4a15-9b4e-d0376100b474
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620710904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2620710904
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.569307991
Short name T510
Test name
Test status
Simulation time 17060290 ps
CPU time 0.58 seconds
Started May 02 01:18:37 PM PDT 24
Finished May 02 01:18:38 PM PDT 24
Peak memory 182584 kb
Host smart-21ff962a-a31f-447a-8b71-b5b3185eec9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569307991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.569307991
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.412212293
Short name T550
Test name
Test status
Simulation time 15265592 ps
CPU time 0.54 seconds
Started May 02 01:18:36 PM PDT 24
Finished May 02 01:18:38 PM PDT 24
Peak memory 182084 kb
Host smart-71ff3459-6b81-4dab-9215-4764a235c9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412212293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.412212293
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1964238831
Short name T568
Test name
Test status
Simulation time 15366817 ps
CPU time 0.52 seconds
Started May 02 01:18:37 PM PDT 24
Finished May 02 01:18:39 PM PDT 24
Peak memory 182196 kb
Host smart-6a748706-9596-4e9a-8336-c794f5b1d600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964238831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1964238831
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3805151214
Short name T534
Test name
Test status
Simulation time 81021266 ps
CPU time 0.52 seconds
Started May 02 01:18:37 PM PDT 24
Finished May 02 01:18:39 PM PDT 24
Peak memory 182480 kb
Host smart-8fbe247f-4cb2-48e2-bac4-86e2b31ee2f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805151214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3805151214
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.539540468
Short name T478
Test name
Test status
Simulation time 14485329 ps
CPU time 0.51 seconds
Started May 02 01:18:36 PM PDT 24
Finished May 02 01:18:37 PM PDT 24
Peak memory 182136 kb
Host smart-73646ad1-6464-4b01-88eb-9c0b0e44b103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539540468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.539540468
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2413156539
Short name T507
Test name
Test status
Simulation time 17870562 ps
CPU time 0.53 seconds
Started May 02 01:18:37 PM PDT 24
Finished May 02 01:18:39 PM PDT 24
Peak memory 182124 kb
Host smart-6e5b3906-b885-42b5-891a-fae233b29727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413156539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2413156539
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1076552983
Short name T521
Test name
Test status
Simulation time 82036830 ps
CPU time 0.59 seconds
Started May 02 01:18:39 PM PDT 24
Finished May 02 01:18:40 PM PDT 24
Peak memory 182640 kb
Host smart-6a467361-6975-4505-aeab-ac3a84c6724f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076552983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1076552983
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1228738161
Short name T528
Test name
Test status
Simulation time 50162926 ps
CPU time 0.54 seconds
Started May 02 01:18:38 PM PDT 24
Finished May 02 01:18:39 PM PDT 24
Peak memory 182120 kb
Host smart-3502df07-3fa8-485c-86ba-2fb226835805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228738161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1228738161
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.978285885
Short name T472
Test name
Test status
Simulation time 14107637 ps
CPU time 0.54 seconds
Started May 02 01:18:39 PM PDT 24
Finished May 02 01:18:41 PM PDT 24
Peak memory 182008 kb
Host smart-141913fe-cc1e-4c33-b4e1-efdd649be72b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978285885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.978285885
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3160468794
Short name T520
Test name
Test status
Simulation time 12677607 ps
CPU time 0.55 seconds
Started May 02 01:18:39 PM PDT 24
Finished May 02 01:18:40 PM PDT 24
Peak memory 182116 kb
Host smart-b01bd0ef-c5f6-45d5-b55b-77c6483a885f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160468794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3160468794
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1240356204
Short name T466
Test name
Test status
Simulation time 91518240 ps
CPU time 0.78 seconds
Started May 02 01:16:57 PM PDT 24
Finished May 02 01:16:59 PM PDT 24
Peak memory 195748 kb
Host smart-efdc83d6-daf4-484e-9a7a-7cd0f3b2d2b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240356204 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1240356204
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2265603880
Short name T527
Test name
Test status
Simulation time 13278320 ps
CPU time 0.58 seconds
Started May 02 01:16:57 PM PDT 24
Finished May 02 01:16:59 PM PDT 24
Peak memory 182760 kb
Host smart-4c236ccf-25e8-473f-9f9a-f0369f836c45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265603880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2265603880
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3556699336
Short name T470
Test name
Test status
Simulation time 23595052 ps
CPU time 0.54 seconds
Started May 02 01:16:46 PM PDT 24
Finished May 02 01:16:48 PM PDT 24
Peak memory 182676 kb
Host smart-ce7aa639-ba75-4b30-9f34-5d9d473f0806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556699336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3556699336
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3105033422
Short name T554
Test name
Test status
Simulation time 46144592 ps
CPU time 0.68 seconds
Started May 02 01:16:56 PM PDT 24
Finished May 02 01:16:58 PM PDT 24
Peak memory 192012 kb
Host smart-77797999-e39c-4bc9-b5b5-b00d1a111ed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105033422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3105033422
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2927920885
Short name T506
Test name
Test status
Simulation time 488161052 ps
CPU time 2.49 seconds
Started May 02 01:16:47 PM PDT 24
Finished May 02 01:16:50 PM PDT 24
Peak memory 197588 kb
Host smart-38a1558d-e5db-4a44-bd01-85b80851e6b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927920885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2927920885
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2574248326
Short name T118
Test name
Test status
Simulation time 75161609 ps
CPU time 1.05 seconds
Started May 02 01:16:49 PM PDT 24
Finished May 02 01:16:51 PM PDT 24
Peak memory 183240 kb
Host smart-631cf775-2c80-40c7-ad36-0010f1d85fe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574248326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2574248326
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3051870806
Short name T551
Test name
Test status
Simulation time 34598762 ps
CPU time 0.86 seconds
Started May 02 01:16:55 PM PDT 24
Finished May 02 01:16:57 PM PDT 24
Peak memory 196652 kb
Host smart-49e4d36c-347c-4ca3-809b-8a8b75fc7e56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051870806 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3051870806
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.798677240
Short name T89
Test name
Test status
Simulation time 14953397 ps
CPU time 0.54 seconds
Started May 02 01:16:57 PM PDT 24
Finished May 02 01:16:58 PM PDT 24
Peak memory 182660 kb
Host smart-aacbd6e0-bfb9-46b1-b765-70751e0e7a1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798677240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.798677240
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2518295915
Short name T482
Test name
Test status
Simulation time 43824236 ps
CPU time 0.55 seconds
Started May 02 01:16:56 PM PDT 24
Finished May 02 01:16:58 PM PDT 24
Peak memory 182688 kb
Host smart-aad6ec62-43d5-4452-ae6f-0a5a98e3ceed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518295915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2518295915
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3546199648
Short name T78
Test name
Test status
Simulation time 723735389 ps
CPU time 0.79 seconds
Started May 02 01:16:58 PM PDT 24
Finished May 02 01:16:59 PM PDT 24
Peak memory 191764 kb
Host smart-531ecd29-3a32-4c83-bd1b-38478b130f27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546199648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3546199648
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2951526686
Short name T463
Test name
Test status
Simulation time 197140546 ps
CPU time 1.22 seconds
Started May 02 01:17:08 PM PDT 24
Finished May 02 01:17:10 PM PDT 24
Peak memory 197144 kb
Host smart-fba25bcf-2fb2-4c34-966b-dcbb2cc303d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951526686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2951526686
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1463753400
Short name T117
Test name
Test status
Simulation time 416839357 ps
CPU time 1.4 seconds
Started May 02 01:16:56 PM PDT 24
Finished May 02 01:16:59 PM PDT 24
Peak memory 195148 kb
Host smart-bbda80d6-289d-4e68-a09f-2d617c35d9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463753400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1463753400
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3163883831
Short name T479
Test name
Test status
Simulation time 123568051 ps
CPU time 0.87 seconds
Started May 02 01:17:07 PM PDT 24
Finished May 02 01:17:09 PM PDT 24
Peak memory 197416 kb
Host smart-687236c9-52a2-471b-a780-e14d16bc4ede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163883831 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3163883831
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.746438474
Short name T480
Test name
Test status
Simulation time 53038246 ps
CPU time 0.61 seconds
Started May 02 01:17:09 PM PDT 24
Finished May 02 01:17:11 PM PDT 24
Peak memory 182744 kb
Host smart-57a1bfec-30d7-4bd2-a874-2737281aa208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746438474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.746438474
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1218586157
Short name T494
Test name
Test status
Simulation time 25583909 ps
CPU time 0.55 seconds
Started May 02 01:17:07 PM PDT 24
Finished May 02 01:17:08 PM PDT 24
Peak memory 182548 kb
Host smart-d897e8bb-903f-40c3-a6eb-d8230b1f858d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218586157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1218586157
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.749427156
Short name T543
Test name
Test status
Simulation time 30454663 ps
CPU time 0.62 seconds
Started May 02 01:17:05 PM PDT 24
Finished May 02 01:17:06 PM PDT 24
Peak memory 192044 kb
Host smart-abddcad5-8182-483b-852d-54c63791182c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749427156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.749427156
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2564619151
Short name T473
Test name
Test status
Simulation time 41313521 ps
CPU time 2.06 seconds
Started May 02 01:17:07 PM PDT 24
Finished May 02 01:17:10 PM PDT 24
Peak memory 197644 kb
Host smart-993d7b55-a501-4f3b-8949-9cf5835b70a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564619151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2564619151
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1605929821
Short name T29
Test name
Test status
Simulation time 248990499 ps
CPU time 0.83 seconds
Started May 02 01:17:07 PM PDT 24
Finished May 02 01:17:09 PM PDT 24
Peak memory 193784 kb
Host smart-cfd68feb-23cf-4080-84dd-35add8f60578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605929821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1605929821
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1164540994
Short name T511
Test name
Test status
Simulation time 28839413 ps
CPU time 0.72 seconds
Started May 02 01:17:14 PM PDT 24
Finished May 02 01:17:15 PM PDT 24
Peak memory 194900 kb
Host smart-03733321-f3f3-4b05-8de9-0f6dd95ca4e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164540994 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1164540994
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2346241221
Short name T93
Test name
Test status
Simulation time 24769540 ps
CPU time 0.55 seconds
Started May 02 01:17:06 PM PDT 24
Finished May 02 01:17:08 PM PDT 24
Peak memory 182736 kb
Host smart-6d10d528-0be5-4c2f-a329-c9f1b4389a3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346241221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2346241221
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3260584634
Short name T539
Test name
Test status
Simulation time 12278374 ps
CPU time 0.55 seconds
Started May 02 01:17:06 PM PDT 24
Finished May 02 01:17:07 PM PDT 24
Peak memory 182696 kb
Host smart-efc84a74-473f-4ace-8542-c4d58546c3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260584634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3260584634
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2771871239
Short name T98
Test name
Test status
Simulation time 320013275 ps
CPU time 0.77 seconds
Started May 02 01:17:13 PM PDT 24
Finished May 02 01:17:14 PM PDT 24
Peak memory 193396 kb
Host smart-0ac2091f-509a-4d7c-9dff-12df064f2a8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771871239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2771871239
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2607456279
Short name T492
Test name
Test status
Simulation time 244375558 ps
CPU time 1.16 seconds
Started May 02 01:17:07 PM PDT 24
Finished May 02 01:17:09 PM PDT 24
Peak memory 195720 kb
Host smart-bb75f4dd-db13-4fa4-af10-030263bb6d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607456279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2607456279
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1417192108
Short name T467
Test name
Test status
Simulation time 481764158 ps
CPU time 1.38 seconds
Started May 02 01:17:06 PM PDT 24
Finished May 02 01:17:08 PM PDT 24
Peak memory 183372 kb
Host smart-00d77475-0fc1-40f5-b8f9-a105787932e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417192108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1417192108
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3394859661
Short name T487
Test name
Test status
Simulation time 40115540 ps
CPU time 0.9 seconds
Started May 02 01:17:20 PM PDT 24
Finished May 02 01:17:21 PM PDT 24
Peak memory 197312 kb
Host smart-873b489b-bb68-432f-b5d6-37240d37feb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394859661 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3394859661
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.100023959
Short name T549
Test name
Test status
Simulation time 11085097 ps
CPU time 0.53 seconds
Started May 02 01:17:20 PM PDT 24
Finished May 02 01:17:21 PM PDT 24
Peak memory 182432 kb
Host smart-28fbd6da-b1db-40c5-8441-ca889af161a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100023959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.100023959
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2516671598
Short name T477
Test name
Test status
Simulation time 39816499 ps
CPU time 0.53 seconds
Started May 02 01:17:19 PM PDT 24
Finished May 02 01:17:20 PM PDT 24
Peak memory 182024 kb
Host smart-146937de-2ce2-4337-bdf1-dda869dd273d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516671598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2516671598
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3386779537
Short name T571
Test name
Test status
Simulation time 32884593 ps
CPU time 0.73 seconds
Started May 02 01:17:22 PM PDT 24
Finished May 02 01:17:23 PM PDT 24
Peak memory 193400 kb
Host smart-433fc371-b38e-4511-b927-22f8e65fda41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386779537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3386779537
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1111472870
Short name T561
Test name
Test status
Simulation time 441841248 ps
CPU time 1.91 seconds
Started May 02 01:17:13 PM PDT 24
Finished May 02 01:17:15 PM PDT 24
Peak memory 197480 kb
Host smart-dc5f597a-711d-4020-8a85-56a15fff781f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111472870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1111472870
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1287139106
Short name T113
Test name
Test status
Simulation time 84138146 ps
CPU time 0.77 seconds
Started May 02 01:17:28 PM PDT 24
Finished May 02 01:17:29 PM PDT 24
Peak memory 193688 kb
Host smart-b5927c15-f2f6-4d4d-ba9c-c5e3cfa398d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287139106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1287139106
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1332135521
Short name T217
Test name
Test status
Simulation time 491988324216 ps
CPU time 498.26 seconds
Started May 02 01:18:37 PM PDT 24
Finished May 02 01:26:57 PM PDT 24
Peak memory 183040 kb
Host smart-96e158a0-0c35-4928-9f61-bbd36d605a10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332135521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1332135521
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2019762029
Short name T314
Test name
Test status
Simulation time 471576461020 ps
CPU time 454.58 seconds
Started May 02 01:18:46 PM PDT 24
Finished May 02 01:26:21 PM PDT 24
Peak memory 183044 kb
Host smart-3c86bafe-f397-4f21-a807-9d39c5c4e7e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019762029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2019762029
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1854368925
Short name T379
Test name
Test status
Simulation time 181279403039 ps
CPU time 75.86 seconds
Started May 02 01:18:41 PM PDT 24
Finished May 02 01:19:58 PM PDT 24
Peak memory 183016 kb
Host smart-82bc89fd-bd04-46a2-a957-323b429b63d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854368925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1854368925
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3224966643
Short name T368
Test name
Test status
Simulation time 640303489035 ps
CPU time 1461.44 seconds
Started May 02 01:18:40 PM PDT 24
Finished May 02 01:43:03 PM PDT 24
Peak memory 191128 kb
Host smart-57302a0e-debd-43fe-88ec-66f9f75ad55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224966643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3224966643
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3888915144
Short name T290
Test name
Test status
Simulation time 25587608309 ps
CPU time 42.45 seconds
Started May 02 01:18:44 PM PDT 24
Finished May 02 01:19:27 PM PDT 24
Peak memory 191120 kb
Host smart-d7097dc8-1bf5-44d9-b49d-b65fa23a26d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888915144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3888915144
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.464000824
Short name T17
Test name
Test status
Simulation time 144653411 ps
CPU time 0.75 seconds
Started May 02 01:18:46 PM PDT 24
Finished May 02 01:18:48 PM PDT 24
Peak memory 213356 kb
Host smart-448e028b-db98-48d7-a819-320f8f88f0ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464000824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.464000824
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.277710348
Short name T307
Test name
Test status
Simulation time 7650978072 ps
CPU time 12.1 seconds
Started May 02 01:19:20 PM PDT 24
Finished May 02 01:19:33 PM PDT 24
Peak memory 183024 kb
Host smart-5ad036a8-ccb7-431e-8aad-6be89a119163
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277710348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.277710348
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3262737207
Short name T400
Test name
Test status
Simulation time 168278179558 ps
CPU time 71.93 seconds
Started May 02 01:19:20 PM PDT 24
Finished May 02 01:20:33 PM PDT 24
Peak memory 183056 kb
Host smart-23cb5c3f-b95f-4c79-9f59-5361a1eff8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262737207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3262737207
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3339061278
Short name T367
Test name
Test status
Simulation time 179067034893 ps
CPU time 1816.31 seconds
Started May 02 01:19:23 PM PDT 24
Finished May 02 01:49:40 PM PDT 24
Peak memory 191260 kb
Host smart-7edfc5b6-b881-4009-8639-39886dac3c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339061278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3339061278
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1164240966
Short name T419
Test name
Test status
Simulation time 4722435951 ps
CPU time 9.58 seconds
Started May 02 01:19:20 PM PDT 24
Finished May 02 01:19:31 PM PDT 24
Peak memory 183060 kb
Host smart-a2cc1259-e959-4b55-8c1c-672e406d49cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164240966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1164240966
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2867735654
Short name T190
Test name
Test status
Simulation time 384457881465 ps
CPU time 893.11 seconds
Started May 02 01:28:29 PM PDT 24
Finished May 02 01:43:23 PM PDT 24
Peak memory 191228 kb
Host smart-cfd0e456-0404-4cc6-815b-3f23973d476f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867735654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2867735654
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3204654370
Short name T225
Test name
Test status
Simulation time 56448582635 ps
CPU time 137.54 seconds
Started May 02 01:28:36 PM PDT 24
Finished May 02 01:30:54 PM PDT 24
Peak memory 191256 kb
Host smart-84e88238-8501-41e3-a72a-13fc5e8a64fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204654370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3204654370
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2084390194
Short name T434
Test name
Test status
Simulation time 21282889665 ps
CPU time 246.41 seconds
Started May 02 01:28:37 PM PDT 24
Finished May 02 01:32:44 PM PDT 24
Peak memory 183068 kb
Host smart-8a319091-495d-4801-a5ce-17e235668024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084390194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2084390194
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3035021128
Short name T265
Test name
Test status
Simulation time 767760226193 ps
CPU time 817.26 seconds
Started May 02 01:28:37 PM PDT 24
Finished May 02 01:42:16 PM PDT 24
Peak memory 191272 kb
Host smart-1bf54a0b-d4d3-4f29-a6ee-b83e86cb0b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035021128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3035021128
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3782710731
Short name T248
Test name
Test status
Simulation time 746542033338 ps
CPU time 1491.34 seconds
Started May 02 01:28:38 PM PDT 24
Finished May 02 01:53:31 PM PDT 24
Peak memory 182900 kb
Host smart-7ebd5a9e-541d-4552-893b-7249702d389e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782710731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3782710731
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2548496065
Short name T87
Test name
Test status
Simulation time 120112250727 ps
CPU time 166.93 seconds
Started May 02 01:28:45 PM PDT 24
Finished May 02 01:31:33 PM PDT 24
Peak memory 191272 kb
Host smart-3d52fd7f-3b96-497e-b4a7-f048f9a3c8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548496065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2548496065
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3457485321
Short name T331
Test name
Test status
Simulation time 90192180794 ps
CPU time 173.74 seconds
Started May 02 01:19:27 PM PDT 24
Finished May 02 01:22:21 PM PDT 24
Peak memory 183044 kb
Host smart-ff244f70-76d9-4348-b96d-7c54d0747938
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457485321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3457485321
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1486197849
Short name T417
Test name
Test status
Simulation time 44456144205 ps
CPU time 19.25 seconds
Started May 02 01:19:26 PM PDT 24
Finished May 02 01:19:46 PM PDT 24
Peak memory 183060 kb
Host smart-df4cd043-ae16-43dd-900e-c54ddd481263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486197849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1486197849
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1131384677
Short name T365
Test name
Test status
Simulation time 26098597069 ps
CPU time 77.25 seconds
Started May 02 01:19:24 PM PDT 24
Finished May 02 01:20:42 PM PDT 24
Peak memory 182944 kb
Host smart-c41a41cb-b650-4fc3-9cba-488a60e5bf24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131384677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1131384677
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2720071494
Short name T377
Test name
Test status
Simulation time 115696347 ps
CPU time 0.6 seconds
Started May 02 01:19:33 PM PDT 24
Finished May 02 01:19:35 PM PDT 24
Peak memory 182792 kb
Host smart-c581da4e-03e2-4d44-bea4-20438b62663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720071494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2720071494
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3347706265
Short name T165
Test name
Test status
Simulation time 1059026094645 ps
CPU time 1237.09 seconds
Started May 02 01:19:34 PM PDT 24
Finished May 02 01:40:11 PM PDT 24
Peak memory 191228 kb
Host smart-2ea65548-5f0b-46e4-a76d-4e2ce0f9809d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347706265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3347706265
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.3505460928
Short name T235
Test name
Test status
Simulation time 41121743732 ps
CPU time 120.6 seconds
Started May 02 01:28:44 PM PDT 24
Finished May 02 01:30:45 PM PDT 24
Peak memory 191140 kb
Host smart-e80b3fd4-7752-454f-8267-6bacb6f61c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505460928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3505460928
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1494407023
Short name T312
Test name
Test status
Simulation time 48778507313 ps
CPU time 83.1 seconds
Started May 02 01:28:50 PM PDT 24
Finished May 02 01:30:14 PM PDT 24
Peak memory 191108 kb
Host smart-330bd3f6-c2a8-436e-8077-8a476fab55f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494407023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1494407023
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.155699837
Short name T270
Test name
Test status
Simulation time 30471029313 ps
CPU time 598.98 seconds
Started May 02 01:28:50 PM PDT 24
Finished May 02 01:38:50 PM PDT 24
Peak memory 191176 kb
Host smart-c4d8b859-ef53-4d24-95de-d86624340fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155699837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.155699837
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3799931672
Short name T356
Test name
Test status
Simulation time 692823719086 ps
CPU time 701.71 seconds
Started May 02 01:28:53 PM PDT 24
Finished May 02 01:40:35 PM PDT 24
Peak memory 191108 kb
Host smart-c2d1ad49-82a0-4425-b0b8-d60194471c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799931672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3799931672
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1516098225
Short name T366
Test name
Test status
Simulation time 9322498869 ps
CPU time 16.13 seconds
Started May 02 01:19:33 PM PDT 24
Finished May 02 01:19:50 PM PDT 24
Peak memory 182956 kb
Host smart-274617a8-0244-415a-9674-670aaf2b7a68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516098225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1516098225
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.862495510
Short name T402
Test name
Test status
Simulation time 125186347695 ps
CPU time 102.14 seconds
Started May 02 01:19:33 PM PDT 24
Finished May 02 01:21:16 PM PDT 24
Peak memory 183024 kb
Host smart-01f10d90-d0d2-4e40-beb6-d9ecb37f4069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862495510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.862495510
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.253514845
Short name T261
Test name
Test status
Simulation time 527701901374 ps
CPU time 1351.21 seconds
Started May 02 01:19:33 PM PDT 24
Finished May 02 01:42:05 PM PDT 24
Peak memory 191228 kb
Host smart-396c15fb-8a38-4927-b2d3-fed83ead85dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253514845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.253514845
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3338715931
Short name T164
Test name
Test status
Simulation time 9375853032 ps
CPU time 6.44 seconds
Started May 02 01:19:35 PM PDT 24
Finished May 02 01:19:42 PM PDT 24
Peak memory 182768 kb
Host smart-5497efe0-485e-4a55-b62e-f248644a9877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338715931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3338715931
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1703999411
Short name T373
Test name
Test status
Simulation time 63443154035 ps
CPU time 62.36 seconds
Started May 02 01:29:01 PM PDT 24
Finished May 02 01:30:04 PM PDT 24
Peak memory 183036 kb
Host smart-73e425c4-07bb-445f-bf1c-09c978c0bce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703999411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1703999411
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.252961059
Short name T189
Test name
Test status
Simulation time 276218633517 ps
CPU time 418.76 seconds
Started May 02 01:29:01 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 191256 kb
Host smart-7344923f-9214-48f4-8e33-cb645bef433d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252961059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.252961059
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4161805275
Short name T229
Test name
Test status
Simulation time 38221668508 ps
CPU time 97.76 seconds
Started May 02 01:29:08 PM PDT 24
Finished May 02 01:30:47 PM PDT 24
Peak memory 191240 kb
Host smart-b4a30f92-89de-48f5-8bc0-ef7c12cac297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161805275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4161805275
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1077420736
Short name T449
Test name
Test status
Simulation time 263608211238 ps
CPU time 130.71 seconds
Started May 02 01:29:10 PM PDT 24
Finished May 02 01:31:22 PM PDT 24
Peak memory 183036 kb
Host smart-9f1e51a4-74b0-432f-b28b-a0b36947b1e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077420736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1077420736
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3723650201
Short name T20
Test name
Test status
Simulation time 99239879783 ps
CPU time 40.83 seconds
Started May 02 01:29:07 PM PDT 24
Finished May 02 01:29:49 PM PDT 24
Peak memory 182936 kb
Host smart-aaf372d8-9cd1-4087-be85-5ebaa5334bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723650201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3723650201
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1953976752
Short name T328
Test name
Test status
Simulation time 40788981530 ps
CPU time 68.66 seconds
Started May 02 01:19:40 PM PDT 24
Finished May 02 01:20:50 PM PDT 24
Peak memory 183016 kb
Host smart-5e864146-7160-469d-b334-29943e1e1903
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953976752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1953976752
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3932160990
Short name T436
Test name
Test status
Simulation time 149677939991 ps
CPU time 36.22 seconds
Started May 02 01:19:41 PM PDT 24
Finished May 02 01:20:18 PM PDT 24
Peak memory 183060 kb
Host smart-d04d5172-287d-4e12-ac9c-185e5d3091ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932160990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3932160990
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2312642348
Short name T453
Test name
Test status
Simulation time 26314385856 ps
CPU time 168.26 seconds
Started May 02 01:20:04 PM PDT 24
Finished May 02 01:22:53 PM PDT 24
Peak memory 183056 kb
Host smart-9bfd3b05-3b6e-4a73-a747-4e6e6b86833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312642348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2312642348
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2356562713
Short name T60
Test name
Test status
Simulation time 287945756434 ps
CPU time 645.35 seconds
Started May 02 01:20:06 PM PDT 24
Finished May 02 01:30:52 PM PDT 24
Peak memory 195808 kb
Host smart-29683237-411c-4cd0-82ee-2f02651f6414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356562713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2356562713
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.3079905830
Short name T161
Test name
Test status
Simulation time 456261052663 ps
CPU time 264.85 seconds
Started May 02 01:29:08 PM PDT 24
Finished May 02 01:33:34 PM PDT 24
Peak memory 194016 kb
Host smart-1b0e60ed-e2b2-4ae0-8a31-983b403a5318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079905830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3079905830
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2206535630
Short name T237
Test name
Test status
Simulation time 276936736371 ps
CPU time 272.99 seconds
Started May 02 01:29:10 PM PDT 24
Finished May 02 01:33:44 PM PDT 24
Peak memory 191236 kb
Host smart-87f8f72b-346a-4d26-9758-62f92f45265d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206535630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2206535630
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2846110269
Short name T253
Test name
Test status
Simulation time 142563117342 ps
CPU time 675.3 seconds
Started May 02 01:29:16 PM PDT 24
Finished May 02 01:40:32 PM PDT 24
Peak memory 191228 kb
Host smart-809ac68e-e42c-4d19-98de-244f00b77ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846110269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2846110269
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1562716827
Short name T233
Test name
Test status
Simulation time 78649088012 ps
CPU time 29.03 seconds
Started May 02 01:29:15 PM PDT 24
Finished May 02 01:29:45 PM PDT 24
Peak memory 183024 kb
Host smart-3444404b-841e-402e-8e60-6c52ca49d57d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562716827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1562716827
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4281275694
Short name T285
Test name
Test status
Simulation time 354119230753 ps
CPU time 168.61 seconds
Started May 02 01:29:26 PM PDT 24
Finished May 02 01:32:15 PM PDT 24
Peak memory 191264 kb
Host smart-d275b70c-6e91-4948-879a-4c1f6532d46f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281275694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4281275694
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.324664350
Short name T343
Test name
Test status
Simulation time 197174025282 ps
CPU time 168.17 seconds
Started May 02 01:29:33 PM PDT 24
Finished May 02 01:32:22 PM PDT 24
Peak memory 193404 kb
Host smart-a9dfda81-5f9f-4e6a-8412-7f58eb48295a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324664350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.324664350
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1565657819
Short name T437
Test name
Test status
Simulation time 129076126003 ps
CPU time 211.29 seconds
Started May 02 01:20:13 PM PDT 24
Finished May 02 01:23:45 PM PDT 24
Peak memory 182904 kb
Host smart-c705b0e3-fc36-435e-a589-45fc3d730fae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565657819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1565657819
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.4214903586
Short name T456
Test name
Test status
Simulation time 231115898819 ps
CPU time 179.73 seconds
Started May 02 01:20:07 PM PDT 24
Finished May 02 01:23:07 PM PDT 24
Peak memory 183040 kb
Host smart-8b6220dd-6674-4266-ab1c-0a55f19db2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214903586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4214903586
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.998675916
Short name T266
Test name
Test status
Simulation time 101636399669 ps
CPU time 1366.54 seconds
Started May 02 01:20:05 PM PDT 24
Finished May 02 01:42:53 PM PDT 24
Peak memory 191204 kb
Host smart-2d1a0677-d69d-435e-b92e-17c3058b24fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998675916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.998675916
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4186091186
Short name T329
Test name
Test status
Simulation time 16217751216 ps
CPU time 15.38 seconds
Started May 02 01:20:14 PM PDT 24
Finished May 02 01:20:30 PM PDT 24
Peak memory 191212 kb
Host smart-4dc9b43f-9c0e-4ab6-934e-b18c21aea000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186091186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4186091186
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.87427134
Short name T157
Test name
Test status
Simulation time 163758117239 ps
CPU time 278.24 seconds
Started May 02 01:20:12 PM PDT 24
Finished May 02 01:24:51 PM PDT 24
Peak memory 191156 kb
Host smart-b62156b7-204d-4a9d-903f-036d035f210c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87427134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.87427134
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.147280844
Short name T278
Test name
Test status
Simulation time 55267470567 ps
CPU time 87.85 seconds
Started May 02 01:29:41 PM PDT 24
Finished May 02 01:31:10 PM PDT 24
Peak memory 191212 kb
Host smart-2dbc0561-2c02-4880-9585-f4324f90a6b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147280844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.147280844
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2404450358
Short name T68
Test name
Test status
Simulation time 343397189281 ps
CPU time 174.3 seconds
Started May 02 01:29:40 PM PDT 24
Finished May 02 01:32:36 PM PDT 24
Peak memory 191264 kb
Host smart-d1424ae5-df53-47b1-b8af-b82f3d6748be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404450358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2404450358
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2389522416
Short name T389
Test name
Test status
Simulation time 147838714012 ps
CPU time 75.66 seconds
Started May 02 01:29:43 PM PDT 24
Finished May 02 01:30:59 PM PDT 24
Peak memory 182936 kb
Host smart-439b6625-24e7-4736-9a39-1a787b0b5e98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389522416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2389522416
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1060816938
Short name T192
Test name
Test status
Simulation time 64973038417 ps
CPU time 110.06 seconds
Started May 02 01:29:49 PM PDT 24
Finished May 02 01:31:40 PM PDT 24
Peak memory 191208 kb
Host smart-86b01a22-0a87-4931-a103-0d63c82a8c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060816938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1060816938
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2905648626
Short name T7
Test name
Test status
Simulation time 49112607850 ps
CPU time 78.43 seconds
Started May 02 01:29:52 PM PDT 24
Finished May 02 01:31:11 PM PDT 24
Peak memory 191120 kb
Host smart-43c789ab-4926-4ffd-88a3-52b1df305e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905648626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2905648626
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3399919083
Short name T178
Test name
Test status
Simulation time 83512500258 ps
CPU time 78 seconds
Started May 02 01:29:49 PM PDT 24
Finished May 02 01:31:07 PM PDT 24
Peak memory 193728 kb
Host smart-0c3c3863-4e6e-4431-b465-9abdb5985e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399919083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3399919083
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.904612018
Short name T5
Test name
Test status
Simulation time 265204663028 ps
CPU time 173.19 seconds
Started May 02 01:29:51 PM PDT 24
Finished May 02 01:32:45 PM PDT 24
Peak memory 191128 kb
Host smart-47de73f5-1c03-4003-b901-f838f805ac54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904612018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.904612018
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1673288543
Short name T259
Test name
Test status
Simulation time 4234929546704 ps
CPU time 992.96 seconds
Started May 02 01:20:15 PM PDT 24
Finished May 02 01:36:49 PM PDT 24
Peak memory 183028 kb
Host smart-af6fcbbc-7ba9-4a3e-b55d-9284923c45ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673288543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1673288543
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2612249103
Short name T386
Test name
Test status
Simulation time 46572558719 ps
CPU time 67.62 seconds
Started May 02 01:20:12 PM PDT 24
Finished May 02 01:21:20 PM PDT 24
Peak memory 183016 kb
Host smart-de264b43-f43e-4251-bf67-846c5bbe60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612249103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2612249103
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2617998085
Short name T247
Test name
Test status
Simulation time 82225472232 ps
CPU time 41.03 seconds
Started May 02 01:20:12 PM PDT 24
Finished May 02 01:20:54 PM PDT 24
Peak memory 182968 kb
Host smart-9ff3a21d-c870-4918-9ebf-c3c5b21a6548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617998085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2617998085
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2292269894
Short name T345
Test name
Test status
Simulation time 25741752299 ps
CPU time 36.73 seconds
Started May 02 01:20:12 PM PDT 24
Finished May 02 01:20:49 PM PDT 24
Peak memory 191156 kb
Host smart-55b022c7-1346-45c5-bfd2-e64a58ba1092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292269894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2292269894
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3389527121
Short name T34
Test name
Test status
Simulation time 300190523242 ps
CPU time 434.96 seconds
Started May 02 01:20:14 PM PDT 24
Finished May 02 01:27:29 PM PDT 24
Peak memory 205928 kb
Host smart-30697280-f7d1-47a9-9bb6-50d95bb34d25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389527121 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3389527121
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.rv_timer_random.743635435
Short name T302
Test name
Test status
Simulation time 189552519443 ps
CPU time 120.65 seconds
Started May 02 01:29:58 PM PDT 24
Finished May 02 01:31:59 PM PDT 24
Peak memory 183020 kb
Host smart-50d70899-2245-47ff-9031-cbffb2054b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743635435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.743635435
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1511969374
Short name T318
Test name
Test status
Simulation time 141397103515 ps
CPU time 411.78 seconds
Started May 02 01:29:56 PM PDT 24
Finished May 02 01:36:48 PM PDT 24
Peak memory 191216 kb
Host smart-8585f205-275c-4088-8f62-72fc5cf45ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511969374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1511969374
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3254491966
Short name T129
Test name
Test status
Simulation time 160881264302 ps
CPU time 502.69 seconds
Started May 02 01:30:06 PM PDT 24
Finished May 02 01:38:30 PM PDT 24
Peak memory 191224 kb
Host smart-74e9fa39-22e8-4a16-b546-9f117bf6ba1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254491966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3254491966
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.4146531679
Short name T64
Test name
Test status
Simulation time 46984770187 ps
CPU time 75.8 seconds
Started May 02 01:30:04 PM PDT 24
Finished May 02 01:31:21 PM PDT 24
Peak memory 193480 kb
Host smart-b713acf9-c4a8-4636-a5dc-ad4ed79ddf50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146531679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4146531679
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2849433418
Short name T142
Test name
Test status
Simulation time 113350244262 ps
CPU time 215.86 seconds
Started May 02 01:20:30 PM PDT 24
Finished May 02 01:24:07 PM PDT 24
Peak memory 183044 kb
Host smart-8429063d-f82b-496e-b677-a79136524b9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849433418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2849433418
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2424176073
Short name T392
Test name
Test status
Simulation time 80374362908 ps
CPU time 115.58 seconds
Started May 02 01:20:20 PM PDT 24
Finished May 02 01:22:16 PM PDT 24
Peak memory 183016 kb
Host smart-2b04a1cd-1562-4d27-9ee2-a7dc862c0330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424176073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2424176073
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2385423027
Short name T301
Test name
Test status
Simulation time 50314635168 ps
CPU time 378.97 seconds
Started May 02 01:20:25 PM PDT 24
Finished May 02 01:26:44 PM PDT 24
Peak memory 194180 kb
Host smart-df9f76ca-78bd-4a04-b876-d17564de475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385423027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2385423027
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3582602305
Short name T125
Test name
Test status
Simulation time 77363803904 ps
CPU time 130.82 seconds
Started May 02 01:30:13 PM PDT 24
Finished May 02 01:32:24 PM PDT 24
Peak memory 191212 kb
Host smart-633b431f-ca7c-4ef4-a9a2-373c4e972b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582602305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3582602305
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3017216941
Short name T186
Test name
Test status
Simulation time 182488644716 ps
CPU time 76.44 seconds
Started May 02 01:30:20 PM PDT 24
Finished May 02 01:31:38 PM PDT 24
Peak memory 191216 kb
Host smart-fb73fe66-704c-4045-8a05-06af6902ab95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017216941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3017216941
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2326707808
Short name T106
Test name
Test status
Simulation time 383362613971 ps
CPU time 727.98 seconds
Started May 02 01:30:21 PM PDT 24
Finished May 02 01:42:30 PM PDT 24
Peak memory 191256 kb
Host smart-e95648b5-62f8-4362-a8e6-10c9a1b6f9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326707808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2326707808
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1970142270
Short name T214
Test name
Test status
Simulation time 91397388282 ps
CPU time 339.5 seconds
Started May 02 01:30:19 PM PDT 24
Finished May 02 01:35:59 PM PDT 24
Peak memory 191212 kb
Host smart-15f26b95-d008-4d09-8972-632fc6dafb4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970142270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1970142270
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3124613412
Short name T372
Test name
Test status
Simulation time 386713694533 ps
CPU time 317.22 seconds
Started May 02 01:30:20 PM PDT 24
Finished May 02 01:35:38 PM PDT 24
Peak memory 191140 kb
Host smart-55f5ffae-0115-41d1-adb2-583cf6361402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124613412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3124613412
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3651914770
Short name T6
Test name
Test status
Simulation time 54412502752 ps
CPU time 43.97 seconds
Started May 02 01:30:30 PM PDT 24
Finished May 02 01:31:15 PM PDT 24
Peak memory 191228 kb
Host smart-6ca07174-f45d-489a-bff7-07c2935a93f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651914770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3651914770
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.127105917
Short name T134
Test name
Test status
Simulation time 667584616566 ps
CPU time 390.62 seconds
Started May 02 01:20:47 PM PDT 24
Finished May 02 01:27:18 PM PDT 24
Peak memory 183052 kb
Host smart-394bb6d9-78dd-489b-83ba-f6bb25b4039e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127105917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.127105917
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.253386178
Short name T25
Test name
Test status
Simulation time 248013681493 ps
CPU time 107.46 seconds
Started May 02 01:20:48 PM PDT 24
Finished May 02 01:22:37 PM PDT 24
Peak memory 183064 kb
Host smart-da994133-7b64-413f-a535-5f092e3afcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253386178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.253386178
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1441037958
Short name T195
Test name
Test status
Simulation time 358811469120 ps
CPU time 164.25 seconds
Started May 02 01:20:42 PM PDT 24
Finished May 02 01:23:27 PM PDT 24
Peak memory 191184 kb
Host smart-1b67968f-c393-49a3-af2e-28871e73c72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441037958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1441037958
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2985501862
Short name T399
Test name
Test status
Simulation time 292813865 ps
CPU time 0.9 seconds
Started May 02 01:20:44 PM PDT 24
Finished May 02 01:20:45 PM PDT 24
Peak memory 182816 kb
Host smart-fc785578-4d26-487d-9aaf-7e43da76d01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985501862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2985501862
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4207310104
Short name T421
Test name
Test status
Simulation time 194060582256 ps
CPU time 46.42 seconds
Started May 02 01:20:47 PM PDT 24
Finished May 02 01:21:34 PM PDT 24
Peak memory 183036 kb
Host smart-7692fab1-0c1a-43c4-ae04-ed500f712837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207310104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4207310104
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.3681154499
Short name T315
Test name
Test status
Simulation time 48030843798 ps
CPU time 597.8 seconds
Started May 02 01:30:28 PM PDT 24
Finished May 02 01:40:26 PM PDT 24
Peak memory 191248 kb
Host smart-8b660aea-083d-4799-afe9-d68e08a759f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681154499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3681154499
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.632315902
Short name T199
Test name
Test status
Simulation time 539200273035 ps
CPU time 277.43 seconds
Started May 02 01:30:38 PM PDT 24
Finished May 02 01:35:16 PM PDT 24
Peak memory 191200 kb
Host smart-9f028547-9340-4e12-b530-0c6a7ccf8a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632315902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.632315902
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2932233510
Short name T141
Test name
Test status
Simulation time 49411917459 ps
CPU time 82.26 seconds
Started May 02 01:30:39 PM PDT 24
Finished May 02 01:32:02 PM PDT 24
Peak memory 193460 kb
Host smart-fe43b83f-fe7f-45d6-9c6e-9a468452b95d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932233510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2932233510
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2206964423
Short name T204
Test name
Test status
Simulation time 351534234016 ps
CPU time 379.76 seconds
Started May 02 01:30:39 PM PDT 24
Finished May 02 01:37:00 PM PDT 24
Peak memory 191244 kb
Host smart-1f785349-5fd8-4fba-9ffa-e5a86ed7f03e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206964423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2206964423
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2963468904
Short name T227
Test name
Test status
Simulation time 940637630227 ps
CPU time 596.51 seconds
Started May 02 01:30:44 PM PDT 24
Finished May 02 01:40:42 PM PDT 24
Peak memory 191220 kb
Host smart-fdecf60c-65cd-49af-bbe4-77eb8041467a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963468904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2963468904
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2068108235
Short name T299
Test name
Test status
Simulation time 570823110647 ps
CPU time 459.06 seconds
Started May 02 01:30:44 PM PDT 24
Finished May 02 01:38:25 PM PDT 24
Peak memory 182948 kb
Host smart-203986c3-6961-409b-a9ef-90a654fb0dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068108235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2068108235
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1108357366
Short name T439
Test name
Test status
Simulation time 15740518711 ps
CPU time 17.53 seconds
Started May 02 01:20:52 PM PDT 24
Finished May 02 01:21:10 PM PDT 24
Peak memory 182988 kb
Host smart-06a641b8-821e-4c68-82a6-cfb7b5b7248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108357366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1108357366
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.4005921684
Short name T22
Test name
Test status
Simulation time 583375533079 ps
CPU time 1603.08 seconds
Started May 02 01:20:53 PM PDT 24
Finished May 02 01:47:37 PM PDT 24
Peak memory 191256 kb
Host smart-71270f26-054e-4ebe-9ffb-c90ab122f042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005921684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4005921684
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3868078654
Short name T347
Test name
Test status
Simulation time 57142517472 ps
CPU time 89.42 seconds
Started May 02 01:20:52 PM PDT 24
Finished May 02 01:22:22 PM PDT 24
Peak memory 191216 kb
Host smart-d62f7819-ed76-478c-a1fd-803ecd729fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868078654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3868078654
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3818356061
Short name T146
Test name
Test status
Simulation time 1267231123854 ps
CPU time 578.8 seconds
Started May 02 01:21:04 PM PDT 24
Finished May 02 01:30:44 PM PDT 24
Peak memory 191260 kb
Host smart-8862d085-7352-4123-844c-64027f1e3601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818356061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3818356061
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2432267826
Short name T49
Test name
Test status
Simulation time 24556713816 ps
CPU time 178.95 seconds
Started May 02 01:21:05 PM PDT 24
Finished May 02 01:24:05 PM PDT 24
Peak memory 197236 kb
Host smart-c396248d-984c-4a91-bdc8-e301efbe32b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432267826 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2432267826
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.38441505
Short name T320
Test name
Test status
Simulation time 222508445699 ps
CPU time 637.75 seconds
Started May 02 01:30:52 PM PDT 24
Finished May 02 01:41:31 PM PDT 24
Peak memory 191220 kb
Host smart-822707d0-c358-46df-bdf7-0d011abc68f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38441505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.38441505
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2276851827
Short name T411
Test name
Test status
Simulation time 234847088548 ps
CPU time 386.47 seconds
Started May 02 01:30:53 PM PDT 24
Finished May 02 01:37:21 PM PDT 24
Peak memory 191156 kb
Host smart-e8f1c529-a16c-4213-960d-fe028f292db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276851827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2276851827
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3636693771
Short name T455
Test name
Test status
Simulation time 206798586829 ps
CPU time 241.92 seconds
Started May 02 01:30:53 PM PDT 24
Finished May 02 01:34:56 PM PDT 24
Peak memory 191100 kb
Host smart-343fbe2d-c14d-4c9e-808d-e9e63a25adf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636693771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3636693771
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.594383106
Short name T388
Test name
Test status
Simulation time 27965917558 ps
CPU time 46.47 seconds
Started May 02 01:31:00 PM PDT 24
Finished May 02 01:31:48 PM PDT 24
Peak memory 183028 kb
Host smart-749b09c6-a15d-4fcc-b12e-8b28c8221dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594383106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.594383106
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2987131234
Short name T357
Test name
Test status
Simulation time 146621931612 ps
CPU time 181.2 seconds
Started May 02 01:31:01 PM PDT 24
Finished May 02 01:34:03 PM PDT 24
Peak memory 191240 kb
Host smart-18618c58-0f72-40a7-a7cd-3479c14be5ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987131234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2987131234
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3943420378
Short name T67
Test name
Test status
Simulation time 872630265288 ps
CPU time 749.81 seconds
Started May 02 01:21:11 PM PDT 24
Finished May 02 01:33:41 PM PDT 24
Peak memory 183064 kb
Host smart-2659c90b-d9ba-4325-ae39-527874126a37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943420378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3943420378
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1651964636
Short name T387
Test name
Test status
Simulation time 87785516620 ps
CPU time 73.04 seconds
Started May 02 01:21:11 PM PDT 24
Finished May 02 01:22:25 PM PDT 24
Peak memory 183052 kb
Host smart-557f957e-f9b8-416d-95a5-9092df3dd609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651964636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1651964636
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1349833541
Short name T139
Test name
Test status
Simulation time 128685051860 ps
CPU time 1881.16 seconds
Started May 02 01:21:07 PM PDT 24
Finished May 02 01:52:29 PM PDT 24
Peak memory 191204 kb
Host smart-5d946d06-290b-4adf-9d78-67c51cdb0e57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349833541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1349833541
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3411297910
Short name T429
Test name
Test status
Simulation time 588121345 ps
CPU time 0.78 seconds
Started May 02 01:21:09 PM PDT 24
Finished May 02 01:21:10 PM PDT 24
Peak memory 191528 kb
Host smart-c66e3c4d-e1fc-444b-b7c1-76a308007906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411297910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3411297910
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1250304091
Short name T414
Test name
Test status
Simulation time 69498368 ps
CPU time 0.54 seconds
Started May 02 01:21:22 PM PDT 24
Finished May 02 01:21:23 PM PDT 24
Peak memory 182360 kb
Host smart-a4153953-055b-4f13-8ac0-f95c4fc3e44c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250304091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1250304091
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.3800150182
Short name T172
Test name
Test status
Simulation time 100506812160 ps
CPU time 244.56 seconds
Started May 02 01:31:00 PM PDT 24
Finished May 02 01:35:06 PM PDT 24
Peak memory 191236 kb
Host smart-259d2e3a-55aa-4098-b883-c303fe00b824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800150182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3800150182
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2803105349
Short name T109
Test name
Test status
Simulation time 168795902413 ps
CPU time 314.39 seconds
Started May 02 01:31:09 PM PDT 24
Finished May 02 01:36:25 PM PDT 24
Peak memory 194768 kb
Host smart-f9c3b56d-4cdf-4076-b7e3-da49b17a3fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803105349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2803105349
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.4071281404
Short name T351
Test name
Test status
Simulation time 107152502871 ps
CPU time 83.08 seconds
Started May 02 01:31:08 PM PDT 24
Finished May 02 01:32:32 PM PDT 24
Peak memory 191240 kb
Host smart-700a207b-7fb6-4570-ae9f-aadd531935a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071281404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.4071281404
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.4278879343
Short name T341
Test name
Test status
Simulation time 310207518560 ps
CPU time 486.14 seconds
Started May 02 01:31:09 PM PDT 24
Finished May 02 01:39:15 PM PDT 24
Peak memory 191236 kb
Host smart-41626eac-24dc-4113-9795-153ab67181a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278879343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4278879343
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4021176812
Short name T418
Test name
Test status
Simulation time 21146160002 ps
CPU time 45.26 seconds
Started May 02 01:31:15 PM PDT 24
Finished May 02 01:32:01 PM PDT 24
Peak memory 191228 kb
Host smart-f61478af-2b29-4647-ae2a-1dafd75771b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021176812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4021176812
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3018578844
Short name T354
Test name
Test status
Simulation time 416296993085 ps
CPU time 300.7 seconds
Started May 02 01:31:15 PM PDT 24
Finished May 02 01:36:17 PM PDT 24
Peak memory 191228 kb
Host smart-ed65147e-ca4e-49ca-8185-9bc918ba87df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018578844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3018578844
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.943184942
Short name T334
Test name
Test status
Simulation time 161988736927 ps
CPU time 1176.32 seconds
Started May 02 01:31:16 PM PDT 24
Finished May 02 01:50:53 PM PDT 24
Peak memory 191220 kb
Host smart-40ac4315-934d-4ff6-ab68-ae2d383ad116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943184942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.943184942
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1960015133
Short name T293
Test name
Test status
Simulation time 243129408782 ps
CPU time 1764.3 seconds
Started May 02 01:31:16 PM PDT 24
Finished May 02 02:00:41 PM PDT 24
Peak memory 191212 kb
Host smart-abd8d882-c434-438a-b307-5bea00df0693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960015133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1960015133
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3830290610
Short name T445
Test name
Test status
Simulation time 1099070719274 ps
CPU time 567.48 seconds
Started May 02 01:18:44 PM PDT 24
Finished May 02 01:28:12 PM PDT 24
Peak memory 183028 kb
Host smart-e6f6808c-6f93-413d-8f44-e8b50d6483a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830290610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3830290610
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.597468924
Short name T423
Test name
Test status
Simulation time 581534041397 ps
CPU time 232.71 seconds
Started May 02 01:18:45 PM PDT 24
Finished May 02 01:22:38 PM PDT 24
Peak memory 183036 kb
Host smart-e2e8666c-40f3-486f-a699-14bb49d04d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597468924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.597468924
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3461712734
Short name T268
Test name
Test status
Simulation time 1008265052047 ps
CPU time 191.73 seconds
Started May 02 01:18:45 PM PDT 24
Finished May 02 01:21:58 PM PDT 24
Peak memory 191228 kb
Host smart-b9366c68-4611-4ae0-beb7-a9cce571919a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461712734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3461712734
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1941487781
Short name T342
Test name
Test status
Simulation time 135141841860 ps
CPU time 65.27 seconds
Started May 02 01:18:45 PM PDT 24
Finished May 02 01:19:51 PM PDT 24
Peak memory 194436 kb
Host smart-9ed7311b-2bb0-424f-942e-2eb45db61a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941487781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1941487781
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3502363420
Short name T14
Test name
Test status
Simulation time 473864543 ps
CPU time 0.94 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:18:57 PM PDT 24
Peak memory 214496 kb
Host smart-0f5db1f9-520b-466d-8e50-5e9dfb2be7a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502363420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3502363420
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3453236156
Short name T156
Test name
Test status
Simulation time 719109721532 ps
CPU time 610.43 seconds
Started May 02 01:21:24 PM PDT 24
Finished May 02 01:31:35 PM PDT 24
Peak memory 182904 kb
Host smart-37b8331e-1aa4-4f0e-b954-5141bc1c7449
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453236156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3453236156
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1991478869
Short name T441
Test name
Test status
Simulation time 140637006461 ps
CPU time 234.6 seconds
Started May 02 01:21:23 PM PDT 24
Finished May 02 01:25:18 PM PDT 24
Peak memory 183060 kb
Host smart-79d6f4f7-1ef1-46c7-b686-bb65fdd3e3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991478869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1991478869
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3762896715
Short name T391
Test name
Test status
Simulation time 388266004 ps
CPU time 0.75 seconds
Started May 02 01:21:23 PM PDT 24
Finished May 02 01:21:25 PM PDT 24
Peak memory 182800 kb
Host smart-d6bac7d6-9bb1-4483-a727-8b88cf6225ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762896715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3762896715
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3216878565
Short name T398
Test name
Test status
Simulation time 99600038830 ps
CPU time 142.08 seconds
Started May 02 01:21:29 PM PDT 24
Finished May 02 01:23:51 PM PDT 24
Peak memory 191256 kb
Host smart-7645f09b-d9da-4788-ba9f-3cd665cf96ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216878565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3216878565
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.39077219
Short name T363
Test name
Test status
Simulation time 278019366 ps
CPU time 0.97 seconds
Started May 02 01:21:37 PM PDT 24
Finished May 02 01:21:38 PM PDT 24
Peak memory 182744 kb
Host smart-6e6bf76a-2ce2-40e4-a860-5c7a8a9bec08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39077219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.rv_timer_cfg_update_on_fly.39077219
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3687248419
Short name T66
Test name
Test status
Simulation time 102144305449 ps
CPU time 142.96 seconds
Started May 02 01:21:28 PM PDT 24
Finished May 02 01:23:52 PM PDT 24
Peak memory 183032 kb
Host smart-990b7320-04f8-48a4-b571-1f5a3903d4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687248419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3687248419
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3567729927
Short name T185
Test name
Test status
Simulation time 350619548761 ps
CPU time 2969.44 seconds
Started May 02 01:21:28 PM PDT 24
Finished May 02 02:10:58 PM PDT 24
Peak memory 191136 kb
Host smart-fd300442-6eb9-4ff9-9a3e-2a61eb18274b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567729927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3567729927
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2022044028
Short name T350
Test name
Test status
Simulation time 503429507021 ps
CPU time 295.37 seconds
Started May 02 01:21:37 PM PDT 24
Finished May 02 01:26:33 PM PDT 24
Peak memory 191168 kb
Host smart-a0456c1b-027c-4805-a4c2-1800510490d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022044028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2022044028
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3696868456
Short name T415
Test name
Test status
Simulation time 63000488156 ps
CPU time 84.95 seconds
Started May 02 01:21:35 PM PDT 24
Finished May 02 01:23:01 PM PDT 24
Peak memory 183064 kb
Host smart-f53d1da5-ec01-46a9-b122-4629c9f87a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696868456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3696868456
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2043830898
Short name T242
Test name
Test status
Simulation time 147728570807 ps
CPU time 131.55 seconds
Started May 02 01:21:57 PM PDT 24
Finished May 02 01:24:09 PM PDT 24
Peak memory 183064 kb
Host smart-9366f652-f450-4379-ac4a-f97de03c87eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043830898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2043830898
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.566032431
Short name T406
Test name
Test status
Simulation time 168972246334 ps
CPU time 210.61 seconds
Started May 02 01:21:56 PM PDT 24
Finished May 02 01:25:27 PM PDT 24
Peak memory 183024 kb
Host smart-b983bad0-b5d9-40fe-8ac2-e980bec7215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566032431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.566032431
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1785295694
Short name T337
Test name
Test status
Simulation time 69517906520 ps
CPU time 111.17 seconds
Started May 02 01:21:38 PM PDT 24
Finished May 02 01:23:29 PM PDT 24
Peak memory 193440 kb
Host smart-883ab77b-4a36-46ec-ba24-cca4b4c8d547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785295694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1785295694
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2040528956
Short name T288
Test name
Test status
Simulation time 196535258605 ps
CPU time 67.26 seconds
Started May 02 01:21:57 PM PDT 24
Finished May 02 01:23:05 PM PDT 24
Peak memory 191132 kb
Host smart-3f076cd7-ae7d-4835-a7b2-2590608b8cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040528956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2040528956
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2841332703
Short name T71
Test name
Test status
Simulation time 109426663083 ps
CPU time 865.13 seconds
Started May 02 01:21:56 PM PDT 24
Finished May 02 01:36:21 PM PDT 24
Peak memory 205856 kb
Host smart-a0a06334-110e-4053-80fe-972fbdd46a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841332703 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2841332703
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_random.1848331941
Short name T323
Test name
Test status
Simulation time 66065220207 ps
CPU time 263.07 seconds
Started May 02 01:21:56 PM PDT 24
Finished May 02 01:26:20 PM PDT 24
Peak memory 191256 kb
Host smart-fb30005f-bb68-469f-be36-dbbe6db12f5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848331941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1848331941
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4162358538
Short name T451
Test name
Test status
Simulation time 18176032335 ps
CPU time 17.69 seconds
Started May 02 01:22:00 PM PDT 24
Finished May 02 01:22:18 PM PDT 24
Peak memory 191224 kb
Host smart-6690d66e-1034-49e7-bbae-d219e5e1003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162358538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4162358538
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1862877376
Short name T440
Test name
Test status
Simulation time 59059607 ps
CPU time 0.57 seconds
Started May 02 01:22:00 PM PDT 24
Finished May 02 01:22:01 PM PDT 24
Peak memory 182796 kb
Host smart-e471532c-c86d-43d3-901b-e136784b7043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862877376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1862877376
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2695855616
Short name T40
Test name
Test status
Simulation time 72082015117 ps
CPU time 777.96 seconds
Started May 02 01:22:02 PM PDT 24
Finished May 02 01:35:01 PM PDT 24
Peak memory 205892 kb
Host smart-a041240f-5d7b-49c8-956c-f4af2acf37b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695855616 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2695855616
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2120021776
Short name T413
Test name
Test status
Simulation time 490121449509 ps
CPU time 150.11 seconds
Started May 02 01:21:57 PM PDT 24
Finished May 02 01:24:28 PM PDT 24
Peak memory 182888 kb
Host smart-fb996619-65ff-4ad6-b167-be8cf5b89264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120021776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2120021776
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2255058591
Short name T23
Test name
Test status
Simulation time 850116267700 ps
CPU time 1638.01 seconds
Started May 02 01:22:01 PM PDT 24
Finished May 02 01:49:20 PM PDT 24
Peak memory 191084 kb
Host smart-95315ef8-376f-47d9-bc12-b1aadc134993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255058591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2255058591
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2895465956
Short name T154
Test name
Test status
Simulation time 574099672926 ps
CPU time 300.01 seconds
Started May 02 01:22:24 PM PDT 24
Finished May 02 01:27:25 PM PDT 24
Peak memory 183044 kb
Host smart-eb5941ca-6eee-4d6f-8648-4ff5bb75c23b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895465956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2895465956
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.403850803
Short name T454
Test name
Test status
Simulation time 116306869383 ps
CPU time 47.93 seconds
Started May 02 01:22:16 PM PDT 24
Finished May 02 01:23:04 PM PDT 24
Peak memory 183016 kb
Host smart-5819d804-d301-4f6c-803d-02d108cd339b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403850803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.403850803
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.386879088
Short name T128
Test name
Test status
Simulation time 51916140723 ps
CPU time 25.98 seconds
Started May 02 01:22:15 PM PDT 24
Finished May 02 01:22:41 PM PDT 24
Peak memory 183028 kb
Host smart-624080a4-b6a4-4c4f-b0ff-04d095a036d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386879088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.386879088
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1281439676
Short name T349
Test name
Test status
Simulation time 137065836013 ps
CPU time 206.78 seconds
Started May 02 01:22:21 PM PDT 24
Finished May 02 01:25:49 PM PDT 24
Peak memory 191236 kb
Host smart-2f17513d-42c1-49b8-97ea-0f22ed23abe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281439676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1281439676
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.15194182
Short name T447
Test name
Test status
Simulation time 81118477743 ps
CPU time 257.94 seconds
Started May 02 01:22:24 PM PDT 24
Finished May 02 01:26:43 PM PDT 24
Peak memory 205776 kb
Host smart-c3828f09-b662-45b4-988c-bb22a588d954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194182 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.15194182
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3176061531
Short name T83
Test name
Test status
Simulation time 492864482339 ps
CPU time 234.8 seconds
Started May 02 01:22:24 PM PDT 24
Finished May 02 01:26:20 PM PDT 24
Peak memory 183064 kb
Host smart-dfd5b395-22dc-476c-94db-4092071c51a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176061531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3176061531
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.627403393
Short name T384
Test name
Test status
Simulation time 486892532789 ps
CPU time 199.63 seconds
Started May 02 01:22:23 PM PDT 24
Finished May 02 01:25:44 PM PDT 24
Peak memory 183012 kb
Host smart-edd7fd0c-fadf-4ba9-8aae-bec36f9a724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627403393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.627403393
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1970923813
Short name T327
Test name
Test status
Simulation time 432398141265 ps
CPU time 258.94 seconds
Started May 02 01:22:23 PM PDT 24
Finished May 02 01:26:43 PM PDT 24
Peak memory 191116 kb
Host smart-8e01204d-f6cf-4440-82d0-8db800f78a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970923813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1970923813
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.887290297
Short name T375
Test name
Test status
Simulation time 2082349806 ps
CPU time 4.31 seconds
Started May 02 01:22:24 PM PDT 24
Finished May 02 01:22:30 PM PDT 24
Peak memory 191188 kb
Host smart-43d794fb-098f-459a-b2af-9b7c34eb4e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887290297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.887290297
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1734228328
Short name T9
Test name
Test status
Simulation time 139136377786 ps
CPU time 725.26 seconds
Started May 02 01:22:31 PM PDT 24
Finished May 02 01:34:37 PM PDT 24
Peak memory 195412 kb
Host smart-cffe5203-7329-463d-8767-b49a8c537884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734228328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1734228328
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.659279818
Short name T145
Test name
Test status
Simulation time 1463610180910 ps
CPU time 508.92 seconds
Started May 02 01:22:40 PM PDT 24
Finished May 02 01:31:10 PM PDT 24
Peak memory 183068 kb
Host smart-4e233e31-4c53-41c6-a95d-7b3ef962deb2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659279818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.659279818
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.907742053
Short name T446
Test name
Test status
Simulation time 116863926115 ps
CPU time 191.89 seconds
Started May 02 01:22:38 PM PDT 24
Finished May 02 01:25:50 PM PDT 24
Peak memory 182988 kb
Host smart-5d196473-07c6-4ec3-a7dd-af19405546e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907742053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.907742053
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3855864082
Short name T428
Test name
Test status
Simulation time 979670904 ps
CPU time 7.24 seconds
Started May 02 01:22:37 PM PDT 24
Finished May 02 01:22:45 PM PDT 24
Peak memory 192160 kb
Host smart-5d39b84c-ccdb-4901-9c9e-2a3840f1b6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855864082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3855864082
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.405344311
Short name T382
Test name
Test status
Simulation time 122249133318 ps
CPU time 167.47 seconds
Started May 02 01:22:48 PM PDT 24
Finished May 02 01:25:36 PM PDT 24
Peak memory 183080 kb
Host smart-74d5f66f-6d2d-4290-9c34-f42829513976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405344311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
405344311
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2503385658
Short name T55
Test name
Test status
Simulation time 1472947980585 ps
CPU time 632.45 seconds
Started May 02 01:22:57 PM PDT 24
Finished May 02 01:33:30 PM PDT 24
Peak memory 182900 kb
Host smart-0325edc3-e6a7-476c-a19d-b69efa51e22b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503385658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2503385658
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.806508079
Short name T409
Test name
Test status
Simulation time 119771271184 ps
CPU time 47.39 seconds
Started May 02 01:22:46 PM PDT 24
Finished May 02 01:23:34 PM PDT 24
Peak memory 183060 kb
Host smart-3e6d197f-b499-464a-9ea0-9b048f9abeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806508079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.806508079
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3520885816
Short name T287
Test name
Test status
Simulation time 53399200227 ps
CPU time 251.82 seconds
Started May 02 01:22:48 PM PDT 24
Finished May 02 01:27:00 PM PDT 24
Peak memory 191196 kb
Host smart-61974ce0-8e43-4e38-b6f1-715a2694f4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520885816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3520885816
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2357921726
Short name T205
Test name
Test status
Simulation time 9165365387 ps
CPU time 16.82 seconds
Started May 02 01:22:58 PM PDT 24
Finished May 02 01:23:15 PM PDT 24
Peak memory 191224 kb
Host smart-54a7544b-9b1e-4ba8-af6d-cfe49a4a0330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357921726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2357921726
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3454451465
Short name T13
Test name
Test status
Simulation time 40706053639 ps
CPU time 160.9 seconds
Started May 02 01:22:58 PM PDT 24
Finished May 02 01:25:39 PM PDT 24
Peak memory 197660 kb
Host smart-17eb2973-e066-458b-a8c6-705296afc8bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454451465 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3454451465
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2074619815
Short name T403
Test name
Test status
Simulation time 88370307114 ps
CPU time 36.77 seconds
Started May 02 01:23:06 PM PDT 24
Finished May 02 01:23:44 PM PDT 24
Peak memory 183016 kb
Host smart-9cf49132-9384-4265-9670-b1fae5ac322d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074619815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2074619815
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2584643713
Short name T209
Test name
Test status
Simulation time 55256732982 ps
CPU time 294.25 seconds
Started May 02 01:23:09 PM PDT 24
Finished May 02 01:28:04 PM PDT 24
Peak memory 191252 kb
Host smart-cadc045e-0fe8-41cd-81fc-4138a389518b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584643713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2584643713
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.713155150
Short name T4
Test name
Test status
Simulation time 39457622 ps
CPU time 0.52 seconds
Started May 02 01:23:06 PM PDT 24
Finished May 02 01:23:07 PM PDT 24
Peak memory 182816 kb
Host smart-629294ab-4c52-4093-b9fb-f84202ca1475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713155150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.713155150
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1564934126
Short name T416
Test name
Test status
Simulation time 217126900893 ps
CPU time 182.45 seconds
Started May 02 01:23:05 PM PDT 24
Finished May 02 01:26:09 PM PDT 24
Peak memory 182964 kb
Host smart-9a4c1753-35e8-4b78-a35d-d27afb7d5fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564934126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1564934126
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.1262949591
Short name T80
Test name
Test status
Simulation time 15798641732 ps
CPU time 131.81 seconds
Started May 02 01:23:07 PM PDT 24
Finished May 02 01:25:19 PM PDT 24
Peak memory 197704 kb
Host smart-6e4e0d65-34df-4f67-a8bc-4482191101c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262949591 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.1262949591
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.908327499
Short name T110
Test name
Test status
Simulation time 592196236496 ps
CPU time 974.93 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:35:11 PM PDT 24
Peak memory 182960 kb
Host smart-314f2da4-01b2-488d-a763-661740ab503c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908327499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.908327499
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2298581155
Short name T410
Test name
Test status
Simulation time 68426628675 ps
CPU time 88.65 seconds
Started May 02 01:18:56 PM PDT 24
Finished May 02 01:20:25 PM PDT 24
Peak memory 183036 kb
Host smart-6a4e322d-aa5e-4cee-8694-8e326add7b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298581155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2298581155
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2059554357
Short name T231
Test name
Test status
Simulation time 49258939171 ps
CPU time 75.84 seconds
Started May 02 01:18:54 PM PDT 24
Finished May 02 01:20:11 PM PDT 24
Peak memory 191080 kb
Host smart-1297fb65-6dfe-4191-a24f-ca07e32d00a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059554357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2059554357
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3063202753
Short name T390
Test name
Test status
Simulation time 84216468 ps
CPU time 1.19 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:18:57 PM PDT 24
Peak memory 191156 kb
Host smart-a122b4b5-bc4e-4bf9-9b1e-ea78333007c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063202753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3063202753
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3250461545
Short name T16
Test name
Test status
Simulation time 96879238 ps
CPU time 0.86 seconds
Started May 02 01:18:56 PM PDT 24
Finished May 02 01:18:58 PM PDT 24
Peak memory 213432 kb
Host smart-dc971b4f-3c52-482b-99ab-dfa4f9023f60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250461545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3250461545
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3004946592
Short name T232
Test name
Test status
Simulation time 876601646579 ps
CPU time 406.56 seconds
Started May 02 01:23:09 PM PDT 24
Finished May 02 01:29:56 PM PDT 24
Peak memory 183036 kb
Host smart-6c59363c-aab3-4750-bb84-f77e1f176ad2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004946592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3004946592
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1612764022
Short name T401
Test name
Test status
Simulation time 281920733219 ps
CPU time 97.85 seconds
Started May 02 01:23:05 PM PDT 24
Finished May 02 01:24:44 PM PDT 24
Peak memory 183016 kb
Host smart-c5d86437-9bf7-4510-927b-d2b7b856d2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612764022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1612764022
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1892076195
Short name T200
Test name
Test status
Simulation time 398313383592 ps
CPU time 838.25 seconds
Started May 02 01:23:07 PM PDT 24
Finished May 02 01:37:06 PM PDT 24
Peak memory 191236 kb
Host smart-acbfb2bd-fbfc-4278-ad8c-7ccf1bc74e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892076195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1892076195
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3256917069
Short name T149
Test name
Test status
Simulation time 85945873802 ps
CPU time 128.84 seconds
Started May 02 01:23:15 PM PDT 24
Finished May 02 01:25:25 PM PDT 24
Peak memory 183032 kb
Host smart-cb311f46-d3c2-4c2e-b418-12f9466c1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256917069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3256917069
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.3963179828
Short name T38
Test name
Test status
Simulation time 107832049018 ps
CPU time 466.59 seconds
Started May 02 01:23:15 PM PDT 24
Finished May 02 01:31:02 PM PDT 24
Peak memory 205824 kb
Host smart-c8cfc72b-2b50-4249-b296-5a3a38470829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963179828 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.3963179828
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1778324409
Short name T369
Test name
Test status
Simulation time 378886709694 ps
CPU time 204.85 seconds
Started May 02 01:23:24 PM PDT 24
Finished May 02 01:26:50 PM PDT 24
Peak memory 183000 kb
Host smart-c718b55b-5781-4e64-90d6-6801c0b6ac50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778324409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1778324409
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3772157579
Short name T105
Test name
Test status
Simulation time 253077285161 ps
CPU time 191.46 seconds
Started May 02 01:23:25 PM PDT 24
Finished May 02 01:26:37 PM PDT 24
Peak memory 183044 kb
Host smart-a22575de-dee9-4fa2-b9af-440c56b127cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772157579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3772157579
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.817933661
Short name T286
Test name
Test status
Simulation time 43045064038 ps
CPU time 69.91 seconds
Started May 02 01:23:26 PM PDT 24
Finished May 02 01:24:37 PM PDT 24
Peak memory 191200 kb
Host smart-3fc6bcd7-ed50-4cc8-9769-ed8b7126df5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817933661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.817933661
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.248776746
Short name T250
Test name
Test status
Simulation time 13083096400 ps
CPU time 22.94 seconds
Started May 02 01:23:24 PM PDT 24
Finished May 02 01:23:48 PM PDT 24
Peak memory 182936 kb
Host smart-d86fa937-0657-49f1-9529-d7e917ac98dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248776746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.248776746
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3198289594
Short name T244
Test name
Test status
Simulation time 82736679841 ps
CPU time 136.44 seconds
Started May 02 01:23:33 PM PDT 24
Finished May 02 01:25:50 PM PDT 24
Peak memory 183052 kb
Host smart-c46b51e2-ca59-4dcd-b872-29e08a30d395
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198289594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3198289594
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3809518493
Short name T84
Test name
Test status
Simulation time 122055811311 ps
CPU time 82.82 seconds
Started May 02 01:23:35 PM PDT 24
Finished May 02 01:24:59 PM PDT 24
Peak memory 182888 kb
Host smart-cf2ba36c-b128-40e8-996e-2d1da8569849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809518493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3809518493
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3926662889
Short name T374
Test name
Test status
Simulation time 543006561433 ps
CPU time 171.84 seconds
Started May 02 01:23:23 PM PDT 24
Finished May 02 01:26:15 PM PDT 24
Peak memory 191248 kb
Host smart-1af6c593-5111-425d-8f67-948b66600887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926662889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3926662889
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1085590556
Short name T306
Test name
Test status
Simulation time 173032751472 ps
CPU time 425.09 seconds
Started May 02 01:23:34 PM PDT 24
Finished May 02 01:30:40 PM PDT 24
Peak memory 183028 kb
Host smart-9e1c4ffe-5be2-4208-8b36-c10159ff9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085590556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1085590556
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.843593375
Short name T452
Test name
Test status
Simulation time 62905328 ps
CPU time 0.56 seconds
Started May 02 01:23:43 PM PDT 24
Finished May 02 01:23:44 PM PDT 24
Peak memory 182844 kb
Host smart-7f858d17-6308-4e79-95bf-494d7ed686fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843593375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
843593375
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1525356171
Short name T194
Test name
Test status
Simulation time 42677355977 ps
CPU time 78.45 seconds
Started May 02 01:23:42 PM PDT 24
Finished May 02 01:25:01 PM PDT 24
Peak memory 182992 kb
Host smart-6cb6766e-bd60-4e14-9a55-acdf364e8ee9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525356171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1525356171
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3590316060
Short name T378
Test name
Test status
Simulation time 236344804943 ps
CPU time 105.51 seconds
Started May 02 01:23:40 PM PDT 24
Finished May 02 01:25:27 PM PDT 24
Peak memory 183040 kb
Host smart-e14ed56b-67e8-4753-99bf-af113e2325b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590316060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3590316060
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.855938204
Short name T255
Test name
Test status
Simulation time 352911711868 ps
CPU time 218.07 seconds
Started May 02 01:23:41 PM PDT 24
Finished May 02 01:27:20 PM PDT 24
Peak memory 191192 kb
Host smart-e7eb088f-f261-4438-88f7-9930c7cd3daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855938204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.855938204
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3167003839
Short name T335
Test name
Test status
Simulation time 37172253599 ps
CPU time 65.02 seconds
Started May 02 01:23:44 PM PDT 24
Finished May 02 01:24:50 PM PDT 24
Peak memory 183032 kb
Host smart-fa985af8-a54f-4c6c-9561-e1466631f9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167003839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3167003839
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.275977459
Short name T198
Test name
Test status
Simulation time 65215872630 ps
CPU time 117.96 seconds
Started May 02 01:23:59 PM PDT 24
Finished May 02 01:25:58 PM PDT 24
Peak memory 183044 kb
Host smart-2ed8b5fd-01da-4b0d-a45f-b3b267194704
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275977459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.275977459
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.1395022828
Short name T197
Test name
Test status
Simulation time 451550103706 ps
CPU time 466.08 seconds
Started May 02 01:23:49 PM PDT 24
Finished May 02 01:31:35 PM PDT 24
Peak memory 191252 kb
Host smart-9eed7ea8-34e4-403d-ae1e-d11dfd72f7b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395022828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1395022828
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1446280033
Short name T196
Test name
Test status
Simulation time 77804232548 ps
CPU time 41.55 seconds
Started May 02 01:23:52 PM PDT 24
Finished May 02 01:24:35 PM PDT 24
Peak memory 194804 kb
Host smart-bac485bf-10be-4e26-ac38-92b6ad1059fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446280033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1446280033
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3641692607
Short name T41
Test name
Test status
Simulation time 129126506635 ps
CPU time 211.92 seconds
Started May 02 01:24:06 PM PDT 24
Finished May 02 01:27:39 PM PDT 24
Peak memory 183040 kb
Host smart-48f6b298-1bbd-4617-9876-ea1bec018147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641692607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3641692607
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2762909099
Short name T234
Test name
Test status
Simulation time 62604943335 ps
CPU time 284.91 seconds
Started May 02 01:24:06 PM PDT 24
Finished May 02 01:28:52 PM PDT 24
Peak memory 191220 kb
Host smart-8eb5518b-9d5b-4612-8435-000fb339723b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762909099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2762909099
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1547691455
Short name T57
Test name
Test status
Simulation time 153762814932 ps
CPU time 27.65 seconds
Started May 02 01:24:16 PM PDT 24
Finished May 02 01:24:44 PM PDT 24
Peak memory 183020 kb
Host smart-63722853-530d-4851-a10f-cbbc4b2f967e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547691455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1547691455
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2773805503
Short name T47
Test name
Test status
Simulation time 371728069758 ps
CPU time 623.94 seconds
Started May 02 01:24:15 PM PDT 24
Finished May 02 01:34:40 PM PDT 24
Peak memory 183044 kb
Host smart-1a9981c0-1151-4b1f-8016-ca27ab90b9bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773805503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2773805503
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.78180629
Short name T427
Test name
Test status
Simulation time 64528708690 ps
CPU time 83.54 seconds
Started May 02 01:24:15 PM PDT 24
Finished May 02 01:25:39 PM PDT 24
Peak memory 183048 kb
Host smart-18d603d1-621b-46ad-92f9-325fff44262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78180629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.78180629
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.4091361088
Short name T296
Test name
Test status
Simulation time 50903397811 ps
CPU time 89.83 seconds
Started May 02 01:24:16 PM PDT 24
Finished May 02 01:25:47 PM PDT 24
Peak memory 183004 kb
Host smart-ccc3e8fb-1a25-49c6-9c8d-cce80455c218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091361088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4091361088
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1528863640
Short name T432
Test name
Test status
Simulation time 35756034434 ps
CPU time 55.41 seconds
Started May 02 01:24:26 PM PDT 24
Finished May 02 01:25:22 PM PDT 24
Peak memory 183052 kb
Host smart-d5d27c86-5f51-4926-8fc6-5e4d476a8914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528863640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1528863640
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3435432748
Short name T397
Test name
Test status
Simulation time 40154487189 ps
CPU time 56.4 seconds
Started May 02 01:24:25 PM PDT 24
Finished May 02 01:25:22 PM PDT 24
Peak memory 183060 kb
Host smart-7b8dcb37-d882-4acf-aeb9-d9fb1c30b815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435432748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3435432748
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.4120308374
Short name T179
Test name
Test status
Simulation time 212790047665 ps
CPU time 108.49 seconds
Started May 02 01:24:25 PM PDT 24
Finished May 02 01:26:14 PM PDT 24
Peak memory 182904 kb
Host smart-ae0c6e66-05d5-4d9f-a929-54a5019409d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120308374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.4120308374
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.38717112
Short name T381
Test name
Test status
Simulation time 293904753369 ps
CPU time 211.01 seconds
Started May 02 01:24:27 PM PDT 24
Finished May 02 01:27:59 PM PDT 24
Peak memory 182916 kb
Host smart-f6d78f6b-46a9-4f43-8684-eb920ddf2d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38717112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.38717112
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.990304357
Short name T246
Test name
Test status
Simulation time 152637202220 ps
CPU time 650.22 seconds
Started May 02 01:24:27 PM PDT 24
Finished May 02 01:35:18 PM PDT 24
Peak memory 191212 kb
Host smart-88ffa4a1-28b8-4062-9f7a-e68d8fcdd816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990304357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.990304357
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1114719828
Short name T326
Test name
Test status
Simulation time 134317725955 ps
CPU time 218.85 seconds
Started May 02 01:24:35 PM PDT 24
Finished May 02 01:28:14 PM PDT 24
Peak memory 191244 kb
Host smart-46a7cf7b-7327-4de0-b43e-47521d3e9d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114719828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1114719828
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4151427318
Short name T353
Test name
Test status
Simulation time 1284554127979 ps
CPU time 756.21 seconds
Started May 02 01:24:36 PM PDT 24
Finished May 02 01:37:13 PM PDT 24
Peak memory 194996 kb
Host smart-ea2d4224-1cae-43f3-9579-538a41e54092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151427318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4151427318
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.664171133
Short name T276
Test name
Test status
Simulation time 276414902493 ps
CPU time 450.79 seconds
Started May 02 01:24:42 PM PDT 24
Finished May 02 01:32:14 PM PDT 24
Peak memory 183048 kb
Host smart-3b879443-c3ed-4d6c-9719-a1b34bc2fea0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664171133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.664171133
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2770634097
Short name T396
Test name
Test status
Simulation time 99566945672 ps
CPU time 153.74 seconds
Started May 02 01:24:41 PM PDT 24
Finished May 02 01:27:16 PM PDT 24
Peak memory 182988 kb
Host smart-a2ae2163-2c55-4aa1-be86-971c7a223e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770634097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2770634097
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3683288445
Short name T362
Test name
Test status
Simulation time 183022308173 ps
CPU time 307.64 seconds
Started May 02 01:24:36 PM PDT 24
Finished May 02 01:29:44 PM PDT 24
Peak memory 191236 kb
Host smart-ffdf5446-2e23-45a7-9103-74de7c8c6013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683288445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3683288445
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2844069154
Short name T249
Test name
Test status
Simulation time 521103340542 ps
CPU time 252.05 seconds
Started May 02 01:24:41 PM PDT 24
Finished May 02 01:28:55 PM PDT 24
Peak memory 194720 kb
Host smart-77e43801-da2c-40dc-a7a9-e694c5e71a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844069154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2844069154
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4176160088
Short name T383
Test name
Test status
Simulation time 237928332431 ps
CPU time 191.06 seconds
Started May 02 01:24:43 PM PDT 24
Finished May 02 01:27:55 PM PDT 24
Peak memory 194440 kb
Host smart-be8cbf29-38e7-4e39-8bd3-3e270b32115c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176160088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4176160088
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1418726941
Short name T309
Test name
Test status
Simulation time 127139989902 ps
CPU time 217.1 seconds
Started May 02 01:24:50 PM PDT 24
Finished May 02 01:28:28 PM PDT 24
Peak memory 183048 kb
Host smart-7518a4b9-2b6e-44a6-b265-d988bf692074
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418726941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1418726941
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2480025684
Short name T27
Test name
Test status
Simulation time 129800852695 ps
CPU time 209.5 seconds
Started May 02 01:24:50 PM PDT 24
Finished May 02 01:28:20 PM PDT 24
Peak memory 183052 kb
Host smart-81717870-ea1a-409e-8d5e-2c877df57d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480025684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2480025684
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3421803212
Short name T338
Test name
Test status
Simulation time 85668634206 ps
CPU time 70.08 seconds
Started May 02 01:24:50 PM PDT 24
Finished May 02 01:26:01 PM PDT 24
Peak memory 191240 kb
Host smart-79c14005-164a-461d-9912-454422807a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421803212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3421803212
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1623855639
Short name T152
Test name
Test status
Simulation time 109906830629 ps
CPU time 525.25 seconds
Started May 02 01:24:50 PM PDT 24
Finished May 02 01:33:36 PM PDT 24
Peak memory 191240 kb
Host smart-e993219a-fffd-475b-ae49-5dd26a7f7d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623855639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1623855639
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.694183827
Short name T295
Test name
Test status
Simulation time 46747344878 ps
CPU time 26.76 seconds
Started May 02 01:19:01 PM PDT 24
Finished May 02 01:19:29 PM PDT 24
Peak memory 183024 kb
Host smart-0905ef72-73bb-4ab0-9312-e4d2651d4d9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694183827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.694183827
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random.2881833898
Short name T239
Test name
Test status
Simulation time 376598821971 ps
CPU time 167.46 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:21:44 PM PDT 24
Peak memory 191252 kb
Host smart-090ccbf0-3c34-4af1-8cad-7e7c65a53cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881833898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2881833898
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.863015543
Short name T63
Test name
Test status
Simulation time 210006159988 ps
CPU time 93.76 seconds
Started May 02 01:18:57 PM PDT 24
Finished May 02 01:20:32 PM PDT 24
Peak memory 194508 kb
Host smart-b1c79183-a7e5-42a5-a4b2-d77a645bc85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863015543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.863015543
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3355032227
Short name T18
Test name
Test status
Simulation time 467721769 ps
CPU time 0.94 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:18:57 PM PDT 24
Peak memory 214476 kb
Host smart-dfbfc21a-fec1-4e13-b763-f57d88168711
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355032227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3355032227
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2916549227
Short name T444
Test name
Test status
Simulation time 713989679985 ps
CPU time 255.78 seconds
Started May 02 01:25:11 PM PDT 24
Finished May 02 01:29:28 PM PDT 24
Peak memory 183036 kb
Host smart-3b6c01fa-2bef-49b3-b5fc-f4e2007ea586
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916549227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2916549227
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2636469515
Short name T448
Test name
Test status
Simulation time 39108367754 ps
CPU time 50.01 seconds
Started May 02 01:25:09 PM PDT 24
Finished May 02 01:26:00 PM PDT 24
Peak memory 182988 kb
Host smart-417fb4c9-464c-4226-b9b6-2bdb65383652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636469515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2636469515
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3746733251
Short name T241
Test name
Test status
Simulation time 813044522550 ps
CPU time 1037.29 seconds
Started May 02 01:25:02 PM PDT 24
Finished May 02 01:42:20 PM PDT 24
Peak memory 191204 kb
Host smart-6ff334e9-2466-46ea-a252-191ba4911a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746733251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3746733251
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1781496652
Short name T380
Test name
Test status
Simulation time 202988667 ps
CPU time 0.62 seconds
Started May 02 01:25:09 PM PDT 24
Finished May 02 01:25:11 PM PDT 24
Peak memory 182752 kb
Host smart-e962e34f-ffa4-4bc1-b41e-fd30251a7f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781496652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1781496652
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1445474990
Short name T56
Test name
Test status
Simulation time 1629428518763 ps
CPU time 1180.98 seconds
Started May 02 01:25:19 PM PDT 24
Finished May 02 01:45:01 PM PDT 24
Peak memory 195400 kb
Host smart-4a9d8ccf-1110-456d-ae14-a59199cafb35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445474990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1445474990
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1359086291
Short name T19
Test name
Test status
Simulation time 1642490975061 ps
CPU time 910.31 seconds
Started May 02 01:25:19 PM PDT 24
Finished May 02 01:40:30 PM PDT 24
Peak memory 183020 kb
Host smart-d6872f03-cef1-439f-a7e3-26caa2fcade8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359086291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1359086291
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3023928131
Short name T407
Test name
Test status
Simulation time 68497784284 ps
CPU time 89.1 seconds
Started May 02 01:25:19 PM PDT 24
Finished May 02 01:26:49 PM PDT 24
Peak memory 183020 kb
Host smart-230fd20f-0090-44a6-9686-c028c39e8648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023928131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3023928131
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.413840181
Short name T294
Test name
Test status
Simulation time 117952546340 ps
CPU time 41.17 seconds
Started May 02 01:25:28 PM PDT 24
Finished May 02 01:26:09 PM PDT 24
Peak memory 191200 kb
Host smart-e6fb3344-d855-4665-9bab-cc915d4518c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413840181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.413840181
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2654190100
Short name T245
Test name
Test status
Simulation time 2322588854089 ps
CPU time 1283.28 seconds
Started May 02 01:25:27 PM PDT 24
Finished May 02 01:46:51 PM PDT 24
Peak memory 183060 kb
Host smart-89fb09fc-b072-4638-81bc-2a977d754e2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654190100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2654190100
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2264073470
Short name T42
Test name
Test status
Simulation time 582169461356 ps
CPU time 233.34 seconds
Started May 02 01:25:29 PM PDT 24
Finished May 02 01:29:22 PM PDT 24
Peak memory 183040 kb
Host smart-471fafe8-cc4a-402a-ac83-d53ebd62392d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264073470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2264073470
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.400264573
Short name T420
Test name
Test status
Simulation time 13152987185 ps
CPU time 6.63 seconds
Started May 02 01:25:28 PM PDT 24
Finished May 02 01:25:36 PM PDT 24
Peak memory 183020 kb
Host smart-6078aaef-89c0-473d-a64c-5e3f68f5d9fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400264573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.400264573
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1384260697
Short name T281
Test name
Test status
Simulation time 137346706372 ps
CPU time 71.04 seconds
Started May 02 01:25:27 PM PDT 24
Finished May 02 01:26:39 PM PDT 24
Peak memory 191244 kb
Host smart-5f446eb5-75eb-4909-9a43-16388fc67b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384260697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1384260697
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3243050876
Short name T59
Test name
Test status
Simulation time 332599638864 ps
CPU time 784.41 seconds
Started May 02 01:25:35 PM PDT 24
Finished May 02 01:38:40 PM PDT 24
Peak memory 195088 kb
Host smart-df12f182-a8ac-48e1-be42-c339b11bdb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243050876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3243050876
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.137230198
Short name T442
Test name
Test status
Simulation time 83518344008 ps
CPU time 138.94 seconds
Started May 02 01:25:43 PM PDT 24
Finished May 02 01:28:03 PM PDT 24
Peak memory 193440 kb
Host smart-6aee9e18-eaa5-4f73-9526-ff24407d6a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137230198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.137230198
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.3299350930
Short name T36
Test name
Test status
Simulation time 83688152556 ps
CPU time 644.93 seconds
Started May 02 01:25:52 PM PDT 24
Finished May 02 01:36:38 PM PDT 24
Peak memory 210144 kb
Host smart-96ad6850-de0c-44f5-b787-895c047da115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299350930 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.3299350930
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.853173415
Short name T86
Test name
Test status
Simulation time 334657114882 ps
CPU time 187.5 seconds
Started May 02 01:25:59 PM PDT 24
Finished May 02 01:29:07 PM PDT 24
Peak memory 183024 kb
Host smart-6f29ff45-4799-4634-9e24-b9d8673cf3d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853173415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.853173415
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2893864982
Short name T430
Test name
Test status
Simulation time 118889254914 ps
CPU time 98.53 seconds
Started May 02 01:25:58 PM PDT 24
Finished May 02 01:27:37 PM PDT 24
Peak memory 183060 kb
Host smart-657e547e-0414-4ad5-bd9b-6d014af45475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893864982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2893864982
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.619020443
Short name T43
Test name
Test status
Simulation time 3099931581 ps
CPU time 6.64 seconds
Started May 02 01:25:58 PM PDT 24
Finished May 02 01:26:06 PM PDT 24
Peak memory 182992 kb
Host smart-1f480afa-5600-469b-bced-9af4a074ad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619020443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.619020443
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3155975111
Short name T264
Test name
Test status
Simulation time 2605910287407 ps
CPU time 1477.5 seconds
Started May 02 01:26:07 PM PDT 24
Finished May 02 01:50:45 PM PDT 24
Peak memory 183052 kb
Host smart-e7df4a64-8d52-4702-865f-6e628fa9e3a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155975111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3155975111
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.304133417
Short name T404
Test name
Test status
Simulation time 140003820363 ps
CPU time 188.84 seconds
Started May 02 01:26:10 PM PDT 24
Finished May 02 01:29:19 PM PDT 24
Peak memory 182936 kb
Host smart-4d8b7c1d-f371-4103-ad4f-0a5e90398d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304133417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.304133417
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2701906150
Short name T359
Test name
Test status
Simulation time 218275189676 ps
CPU time 186.88 seconds
Started May 02 01:26:07 PM PDT 24
Finished May 02 01:29:14 PM PDT 24
Peak memory 191216 kb
Host smart-775503b3-f608-4184-a809-fbb50180e8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701906150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2701906150
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2460580203
Short name T122
Test name
Test status
Simulation time 160111328450 ps
CPU time 248.17 seconds
Started May 02 01:26:15 PM PDT 24
Finished May 02 01:30:24 PM PDT 24
Peak memory 191236 kb
Host smart-4b3d6433-4547-48bd-b2fa-346338323c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460580203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2460580203
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2703068412
Short name T282
Test name
Test status
Simulation time 765439935415 ps
CPU time 410.91 seconds
Started May 02 01:26:15 PM PDT 24
Finished May 02 01:33:07 PM PDT 24
Peak memory 183068 kb
Host smart-3192de98-853e-43a5-ba94-ae7ac553b636
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703068412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2703068412
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.318098302
Short name T405
Test name
Test status
Simulation time 81074466139 ps
CPU time 108.34 seconds
Started May 02 01:26:15 PM PDT 24
Finished May 02 01:28:04 PM PDT 24
Peak memory 183036 kb
Host smart-69d907d5-4e34-44ac-a761-875e527e53d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318098302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.318098302
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2347288381
Short name T222
Test name
Test status
Simulation time 87739924782 ps
CPU time 193.56 seconds
Started May 02 01:26:16 PM PDT 24
Finished May 02 01:29:30 PM PDT 24
Peak memory 191252 kb
Host smart-b8071131-33cf-4b0b-acbe-0af28449b6e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347288381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2347288381
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3441164152
Short name T275
Test name
Test status
Simulation time 165164821269 ps
CPU time 79.94 seconds
Started May 02 01:26:24 PM PDT 24
Finished May 02 01:27:45 PM PDT 24
Peak memory 191196 kb
Host smart-94782d6c-d50f-4ce5-91ad-9e685ed1ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441164152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3441164152
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.467039407
Short name T385
Test name
Test status
Simulation time 3491656876367 ps
CPU time 486.38 seconds
Started May 02 01:26:23 PM PDT 24
Finished May 02 01:34:30 PM PDT 24
Peak memory 194692 kb
Host smart-7cc898ff-317e-4e7f-873b-38a1d8fbe59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467039407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
467039407
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2181455112
Short name T147
Test name
Test status
Simulation time 124515962301 ps
CPU time 224.52 seconds
Started May 02 01:26:32 PM PDT 24
Finished May 02 01:30:17 PM PDT 24
Peak memory 183064 kb
Host smart-061c3734-8416-4cf9-b4b1-6bfbad253e05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181455112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2181455112
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.152171294
Short name T395
Test name
Test status
Simulation time 331449636309 ps
CPU time 147.93 seconds
Started May 02 01:26:22 PM PDT 24
Finished May 02 01:28:51 PM PDT 24
Peak memory 183016 kb
Host smart-7fdab8ae-72a1-4fcd-8074-4f53eabbedce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152171294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.152171294
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3301878072
Short name T263
Test name
Test status
Simulation time 142937416856 ps
CPU time 126.46 seconds
Started May 02 01:26:25 PM PDT 24
Finished May 02 01:28:33 PM PDT 24
Peak memory 191124 kb
Host smart-13a43e3c-af23-482a-9db8-ee185d827e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301878072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3301878072
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.304655018
Short name T431
Test name
Test status
Simulation time 371240393 ps
CPU time 0.85 seconds
Started May 02 01:26:29 PM PDT 24
Finished May 02 01:26:31 PM PDT 24
Peak memory 191396 kb
Host smart-672a5854-efd0-48e0-82b3-58f756d56ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304655018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.304655018
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.965009678
Short name T37
Test name
Test status
Simulation time 400580280103 ps
CPU time 484.58 seconds
Started May 02 01:26:31 PM PDT 24
Finished May 02 01:34:36 PM PDT 24
Peak memory 205840 kb
Host smart-870150dc-db6e-4d0c-9268-93e8fe92000b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965009678 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.965009678
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4196075881
Short name T44
Test name
Test status
Simulation time 2802180015923 ps
CPU time 649.96 seconds
Started May 02 01:26:38 PM PDT 24
Finished May 02 01:37:29 PM PDT 24
Peak memory 183056 kb
Host smart-dee1b6bc-29e5-4a8e-b461-eb12504f137b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196075881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.4196075881
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3430633669
Short name T393
Test name
Test status
Simulation time 67735417007 ps
CPU time 101.1 seconds
Started May 02 01:26:38 PM PDT 24
Finished May 02 01:28:20 PM PDT 24
Peak memory 183016 kb
Host smart-cd62e76d-fa8c-4551-b799-405862a984ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430633669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3430633669
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1195236063
Short name T211
Test name
Test status
Simulation time 71487843127 ps
CPU time 112.58 seconds
Started May 02 01:26:34 PM PDT 24
Finished May 02 01:28:27 PM PDT 24
Peak memory 191228 kb
Host smart-808dba9f-7231-4292-8b56-c4909f95063c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195236063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1195236063
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.997566351
Short name T433
Test name
Test status
Simulation time 254665322027 ps
CPU time 353.47 seconds
Started May 02 01:26:41 PM PDT 24
Finished May 02 01:32:35 PM PDT 24
Peak memory 183024 kb
Host smart-7f69ab42-f624-4989-8497-33ad5f8ac762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997566351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.997566351
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1559392387
Short name T352
Test name
Test status
Simulation time 420271110756 ps
CPU time 726.65 seconds
Started May 02 01:26:46 PM PDT 24
Finished May 02 01:38:53 PM PDT 24
Peak memory 183016 kb
Host smart-03f2c46b-7bc1-4693-b6a8-f582a83a3dff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559392387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1559392387
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.219350586
Short name T450
Test name
Test status
Simulation time 83156862551 ps
CPU time 108.15 seconds
Started May 02 01:26:45 PM PDT 24
Finished May 02 01:28:34 PM PDT 24
Peak memory 182944 kb
Host smart-ba7e286c-0dc2-4e64-b080-80cf16bc2ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219350586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.219350586
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1076020997
Short name T260
Test name
Test status
Simulation time 69356772578 ps
CPU time 411.13 seconds
Started May 02 01:26:46 PM PDT 24
Finished May 02 01:33:38 PM PDT 24
Peak memory 191184 kb
Host smart-3bebd8fe-59a6-44d7-95dd-65064116cf79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076020997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1076020997
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2756413123
Short name T69
Test name
Test status
Simulation time 133038535341 ps
CPU time 105.41 seconds
Started May 02 01:26:47 PM PDT 24
Finished May 02 01:28:33 PM PDT 24
Peak memory 182880 kb
Host smart-5a423f54-0d7f-43fc-b6e6-c518fe30376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756413123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2756413123
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2794098903
Short name T58
Test name
Test status
Simulation time 23240109 ps
CPU time 0.55 seconds
Started May 02 01:26:53 PM PDT 24
Finished May 02 01:26:55 PM PDT 24
Peak memory 182864 kb
Host smart-c4e8884f-889e-4e8f-95a2-d0c63a7ccd82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794098903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2794098903
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3856318633
Short name T376
Test name
Test status
Simulation time 5395583268 ps
CPU time 4.39 seconds
Started May 02 01:18:56 PM PDT 24
Finished May 02 01:19:01 PM PDT 24
Peak memory 182888 kb
Host smart-b7db8a88-0404-4842-94a7-454f6d01ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856318633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3856318633
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1836956893
Short name T153
Test name
Test status
Simulation time 346378965788 ps
CPU time 1333.58 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:41:10 PM PDT 24
Peak memory 191156 kb
Host smart-f396fce2-63fc-49f7-9add-ee3363e362d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836956893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1836956893
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3918873881
Short name T425
Test name
Test status
Simulation time 121512539 ps
CPU time 0.74 seconds
Started May 02 01:18:56 PM PDT 24
Finished May 02 01:18:58 PM PDT 24
Peak memory 182808 kb
Host smart-57d69fb1-a9b3-4087-bbb4-a728b381039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918873881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3918873881
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.678785096
Short name T11
Test name
Test status
Simulation time 81043322328 ps
CPU time 544.42 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:28:01 PM PDT 24
Peak memory 205884 kb
Host smart-64f9d90e-0306-4731-8e29-06248a0f40ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678785096 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.678785096
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1125118594
Short name T330
Test name
Test status
Simulation time 117449518030 ps
CPU time 286.62 seconds
Started May 02 01:26:54 PM PDT 24
Finished May 02 01:31:41 PM PDT 24
Peak memory 191084 kb
Host smart-cb06a119-9937-4094-9c79-057519bf564c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125118594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1125118594
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.141929415
Short name T408
Test name
Test status
Simulation time 50709835636 ps
CPU time 78.11 seconds
Started May 02 01:26:55 PM PDT 24
Finished May 02 01:28:13 PM PDT 24
Peak memory 182884 kb
Host smart-5ac94dea-6361-4812-939a-fe542a115106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141929415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.141929415
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4194754185
Short name T144
Test name
Test status
Simulation time 134592772774 ps
CPU time 203.92 seconds
Started May 02 01:26:54 PM PDT 24
Finished May 02 01:30:18 PM PDT 24
Peak memory 191184 kb
Host smart-da6e31f6-d86d-44d6-9749-356bf1b0e939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194754185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4194754185
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.535507454
Short name T346
Test name
Test status
Simulation time 224161929815 ps
CPU time 138.91 seconds
Started May 02 01:26:53 PM PDT 24
Finished May 02 01:29:12 PM PDT 24
Peak memory 191256 kb
Host smart-cd3f5b3f-a8b9-4fdf-b722-46e4de0fc661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535507454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.535507454
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2621461437
Short name T284
Test name
Test status
Simulation time 164739643745 ps
CPU time 130.97 seconds
Started May 02 01:27:01 PM PDT 24
Finished May 02 01:29:13 PM PDT 24
Peak memory 191232 kb
Host smart-c5cb57d5-60dd-4978-bed1-3f39c7b9476d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621461437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2621461437
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3189108668
Short name T203
Test name
Test status
Simulation time 283756029118 ps
CPU time 122.21 seconds
Started May 02 01:27:00 PM PDT 24
Finished May 02 01:29:02 PM PDT 24
Peak memory 191256 kb
Host smart-9b386cb6-562f-4301-ab46-3d664b27ade5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189108668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3189108668
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3239885120
Short name T344
Test name
Test status
Simulation time 22390917013 ps
CPU time 35.61 seconds
Started May 02 01:27:02 PM PDT 24
Finished May 02 01:27:39 PM PDT 24
Peak memory 182884 kb
Host smart-e430e505-1d20-487d-9100-f76dddf7aa0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239885120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3239885120
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1595152265
Short name T184
Test name
Test status
Simulation time 386956670368 ps
CPU time 313.23 seconds
Started May 02 01:27:05 PM PDT 24
Finished May 02 01:32:19 PM PDT 24
Peak memory 191224 kb
Host smart-5d3a7ca6-e848-45a7-8d53-e3758bbdb923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595152265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1595152265
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3353830230
Short name T438
Test name
Test status
Simulation time 364122615565 ps
CPU time 613.02 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:29:09 PM PDT 24
Peak memory 183056 kb
Host smart-30c34b60-369d-4b88-a957-3d2aa21b757f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353830230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3353830230
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.864920291
Short name T2
Test name
Test status
Simulation time 1642233181 ps
CPU time 1.14 seconds
Started May 02 01:18:55 PM PDT 24
Finished May 02 01:18:58 PM PDT 24
Peak memory 182744 kb
Host smart-e8f35f9f-dfdd-4280-8049-21cba3de8f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864920291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.864920291
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2803160180
Short name T182
Test name
Test status
Simulation time 25249645877 ps
CPU time 58.36 seconds
Started May 02 01:19:02 PM PDT 24
Finished May 02 01:20:02 PM PDT 24
Peak memory 183008 kb
Host smart-8327053d-a608-47e9-8600-b3e32c02dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803160180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2803160180
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2993062800
Short name T201
Test name
Test status
Simulation time 377810688698 ps
CPU time 1272.23 seconds
Started May 02 01:19:13 PM PDT 24
Finished May 02 01:40:26 PM PDT 24
Peak memory 195448 kb
Host smart-bdfb9a29-e0d2-46f1-9738-d0920fdca61b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993062800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2993062800
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3125207693
Short name T111
Test name
Test status
Simulation time 308648416798 ps
CPU time 408.81 seconds
Started May 02 01:19:05 PM PDT 24
Finished May 02 01:25:55 PM PDT 24
Peak memory 205900 kb
Host smart-9ab40b33-8bad-4498-b62f-3d94bf68f68f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125207693 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3125207693
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1905180799
Short name T24
Test name
Test status
Simulation time 394607540754 ps
CPU time 182.54 seconds
Started May 02 01:27:05 PM PDT 24
Finished May 02 01:30:08 PM PDT 24
Peak memory 191224 kb
Host smart-cb69682b-3d48-43a2-b1b9-58c2f9a316e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905180799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1905180799
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.333818800
Short name T174
Test name
Test status
Simulation time 481739693560 ps
CPU time 693.69 seconds
Started May 02 01:27:14 PM PDT 24
Finished May 02 01:38:49 PM PDT 24
Peak memory 195708 kb
Host smart-c5eb4798-9d00-4a9b-a19b-086f4c0bbc3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333818800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.333818800
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.259988758
Short name T132
Test name
Test status
Simulation time 862579849651 ps
CPU time 790.03 seconds
Started May 02 01:27:13 PM PDT 24
Finished May 02 01:40:23 PM PDT 24
Peak memory 191232 kb
Host smart-d2da0f6a-60b5-4e3b-b049-d5fe9aff92c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259988758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.259988758
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.599066691
Short name T358
Test name
Test status
Simulation time 1166045350 ps
CPU time 2.41 seconds
Started May 02 01:27:14 PM PDT 24
Finished May 02 01:27:18 PM PDT 24
Peak memory 182824 kb
Host smart-a12cbb68-eb56-42d4-8061-8c33cc617ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599066691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.599066691
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1743079110
Short name T175
Test name
Test status
Simulation time 213368573876 ps
CPU time 233.84 seconds
Started May 02 01:27:20 PM PDT 24
Finished May 02 01:31:15 PM PDT 24
Peak memory 191228 kb
Host smart-ff13a2e4-3cfb-4aea-b023-45e95288ae21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743079110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1743079110
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3450897529
Short name T272
Test name
Test status
Simulation time 247588595781 ps
CPU time 347.68 seconds
Started May 02 01:27:20 PM PDT 24
Finished May 02 01:33:08 PM PDT 24
Peak memory 193324 kb
Host smart-be90dc8a-6847-45e3-9503-020bad4ab0fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450897529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3450897529
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.581119075
Short name T162
Test name
Test status
Simulation time 107944350572 ps
CPU time 54.13 seconds
Started May 02 01:27:21 PM PDT 24
Finished May 02 01:28:16 PM PDT 24
Peak memory 183000 kb
Host smart-760e453b-3dbe-4590-b991-8a7ebd8b1f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581119075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.581119075
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3129942200
Short name T218
Test name
Test status
Simulation time 13532299351 ps
CPU time 24.46 seconds
Started May 02 01:27:21 PM PDT 24
Finished May 02 01:27:46 PM PDT 24
Peak memory 193356 kb
Host smart-5c1fa7c7-8595-47be-800e-edc4eb718581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129942200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3129942200
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1714668412
Short name T289
Test name
Test status
Simulation time 66536198458 ps
CPU time 43.69 seconds
Started May 02 01:27:21 PM PDT 24
Finished May 02 01:28:05 PM PDT 24
Peak memory 182928 kb
Host smart-b972e548-380e-469a-8455-25f64141e033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714668412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1714668412
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1566915615
Short name T394
Test name
Test status
Simulation time 51212666907 ps
CPU time 77.93 seconds
Started May 02 01:19:11 PM PDT 24
Finished May 02 01:20:30 PM PDT 24
Peak memory 183032 kb
Host smart-3b3e92a7-6757-446b-b205-7c33d5e6f767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566915615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1566915615
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2832491100
Short name T45
Test name
Test status
Simulation time 727972351735 ps
CPU time 985.84 seconds
Started May 02 01:19:11 PM PDT 24
Finished May 02 01:35:38 PM PDT 24
Peak memory 191252 kb
Host smart-512ff1e5-21e5-4290-b9c6-bb60c0895289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832491100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2832491100
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.906756337
Short name T158
Test name
Test status
Simulation time 83028326260 ps
CPU time 298.58 seconds
Started May 02 01:19:11 PM PDT 24
Finished May 02 01:24:11 PM PDT 24
Peak memory 191248 kb
Host smart-0870fd10-dab9-4ac0-b5e4-536be4ad4f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906756337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.906756337
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1200194545
Short name T412
Test name
Test status
Simulation time 419625254849 ps
CPU time 179.09 seconds
Started May 02 01:19:10 PM PDT 24
Finished May 02 01:22:10 PM PDT 24
Peak memory 183032 kb
Host smart-f6874573-66db-4bf1-b298-8337cbfc2099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200194545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1200194545
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3492709377
Short name T35
Test name
Test status
Simulation time 39374095823 ps
CPU time 241.4 seconds
Started May 02 01:19:13 PM PDT 24
Finished May 02 01:23:15 PM PDT 24
Peak memory 197708 kb
Host smart-014c6190-f1cf-45af-9c01-f3cf0223294b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492709377 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3492709377
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2630438062
Short name T48
Test name
Test status
Simulation time 272223576684 ps
CPU time 656 seconds
Started May 02 01:27:28 PM PDT 24
Finished May 02 01:38:25 PM PDT 24
Peak memory 191252 kb
Host smart-0f435e84-8ee1-4668-a258-ad9f8cf46e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630438062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2630438062
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2646095103
Short name T322
Test name
Test status
Simulation time 385208478126 ps
CPU time 414.06 seconds
Started May 02 01:27:28 PM PDT 24
Finished May 02 01:34:23 PM PDT 24
Peak memory 191116 kb
Host smart-a0054e0e-9be9-43bf-81c0-01df066f3c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646095103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2646095103
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.449124549
Short name T443
Test name
Test status
Simulation time 210548871191 ps
CPU time 419.38 seconds
Started May 02 01:27:36 PM PDT 24
Finished May 02 01:34:37 PM PDT 24
Peak memory 191204 kb
Host smart-c25e863a-3893-40fc-97d9-93f52f528c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449124549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.449124549
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1014579490
Short name T426
Test name
Test status
Simulation time 31126447112 ps
CPU time 61.37 seconds
Started May 02 01:27:38 PM PDT 24
Finished May 02 01:28:40 PM PDT 24
Peak memory 182992 kb
Host smart-8c629dc1-8036-415d-8014-fc680d395115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014579490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1014579490
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2740220476
Short name T273
Test name
Test status
Simulation time 74128463371 ps
CPU time 208.51 seconds
Started May 02 01:27:37 PM PDT 24
Finished May 02 01:31:06 PM PDT 24
Peak memory 191216 kb
Host smart-5636874a-33e9-4d6b-bb64-b2c250b79788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740220476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2740220476
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.766308835
Short name T177
Test name
Test status
Simulation time 1699163686450 ps
CPU time 2695.04 seconds
Started May 02 01:27:48 PM PDT 24
Finished May 02 02:12:44 PM PDT 24
Peak memory 191212 kb
Host smart-abd71e3c-e5d5-4744-bb6c-88527d84480e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766308835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.766308835
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2715382512
Short name T258
Test name
Test status
Simulation time 39985365710 ps
CPU time 81.08 seconds
Started May 02 01:27:45 PM PDT 24
Finished May 02 01:29:07 PM PDT 24
Peak memory 183056 kb
Host smart-4af65c92-3682-4b92-9032-d7411881b77f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715382512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2715382512
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2642623048
Short name T65
Test name
Test status
Simulation time 151167019770 ps
CPU time 198 seconds
Started May 02 01:27:52 PM PDT 24
Finished May 02 01:31:11 PM PDT 24
Peak memory 191184 kb
Host smart-d8667017-b5d0-4b66-8c85-4a12f1f2d1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642623048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2642623048
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.692318416
Short name T10
Test name
Test status
Simulation time 141221844545 ps
CPU time 59.91 seconds
Started May 02 01:19:11 PM PDT 24
Finished May 02 01:20:12 PM PDT 24
Peak memory 182948 kb
Host smart-9ec5fc51-02f5-4b0e-923c-6688ae3cdf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692318416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.692318416
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3308069173
Short name T62
Test name
Test status
Simulation time 127612456023 ps
CPU time 110.09 seconds
Started May 02 01:19:10 PM PDT 24
Finished May 02 01:21:01 PM PDT 24
Peak memory 191244 kb
Host smart-0cafe2ba-8885-4a9c-8ddb-0bd5954a150c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308069173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3308069173
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.324513118
Short name T277
Test name
Test status
Simulation time 160348611232 ps
CPU time 94.04 seconds
Started May 02 01:19:23 PM PDT 24
Finished May 02 01:20:58 PM PDT 24
Peak memory 182916 kb
Host smart-659ec627-a6d1-4c68-a89e-87898d77f9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324513118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.324513118
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1156274451
Short name T300
Test name
Test status
Simulation time 3428992265999 ps
CPU time 2301.7 seconds
Started May 02 01:19:24 PM PDT 24
Finished May 02 01:57:46 PM PDT 24
Peak memory 191132 kb
Host smart-24c3887c-6396-4b0b-bc1d-895e90e7497d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156274451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1156274451
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.2140274885
Short name T72
Test name
Test status
Simulation time 86976754907 ps
CPU time 1015.35 seconds
Started May 02 01:19:18 PM PDT 24
Finished May 02 01:36:15 PM PDT 24
Peak memory 211484 kb
Host smart-0f617fae-e00e-481f-bb10-6a881f0d9ff6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140274885 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.2140274885
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.907294398
Short name T370
Test name
Test status
Simulation time 71416384373 ps
CPU time 904.74 seconds
Started May 02 01:27:51 PM PDT 24
Finished May 02 01:42:56 PM PDT 24
Peak memory 191076 kb
Host smart-0aee3a7e-1eea-40d8-92d7-8c9735fda0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907294398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.907294398
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.4119654468
Short name T360
Test name
Test status
Simulation time 272057243904 ps
CPU time 249.15 seconds
Started May 02 01:27:59 PM PDT 24
Finished May 02 01:32:09 PM PDT 24
Peak memory 193368 kb
Host smart-edaeb7e7-37b5-440d-8167-f42407e089c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119654468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4119654468
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1536001350
Short name T252
Test name
Test status
Simulation time 479563113904 ps
CPU time 246.1 seconds
Started May 02 01:27:59 PM PDT 24
Finished May 02 01:32:06 PM PDT 24
Peak memory 191248 kb
Host smart-ef9cf87c-e1a9-499c-888d-bd54cea913ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536001350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1536001350
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1057048691
Short name T291
Test name
Test status
Simulation time 25960823690 ps
CPU time 46.23 seconds
Started May 02 01:27:59 PM PDT 24
Finished May 02 01:28:46 PM PDT 24
Peak memory 183056 kb
Host smart-7f211a41-0f63-4acc-a517-5aae3fa42ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057048691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1057048691
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2128456109
Short name T424
Test name
Test status
Simulation time 160583655950 ps
CPU time 83.15 seconds
Started May 02 01:27:58 PM PDT 24
Finished May 02 01:29:22 PM PDT 24
Peak memory 182920 kb
Host smart-5c7d7fac-05a6-4145-b8c1-a78757d27a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128456109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2128456109
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.26175001
Short name T124
Test name
Test status
Simulation time 497771717143 ps
CPU time 558.49 seconds
Started May 02 01:28:05 PM PDT 24
Finished May 02 01:37:24 PM PDT 24
Peak memory 191208 kb
Host smart-505445f4-e270-4444-a6a6-e8ee124711aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26175001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.26175001
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2067798190
Short name T148
Test name
Test status
Simulation time 58349719673 ps
CPU time 192.3 seconds
Started May 02 01:28:08 PM PDT 24
Finished May 02 01:31:21 PM PDT 24
Peak memory 191232 kb
Host smart-c4bcd874-9c7b-4ec9-b361-cae0920c4989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067798190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2067798190
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1874633457
Short name T238
Test name
Test status
Simulation time 225424566564 ps
CPU time 1805.55 seconds
Started May 02 01:28:06 PM PDT 24
Finished May 02 01:58:13 PM PDT 24
Peak memory 191236 kb
Host smart-b5d11d7b-794a-4a1e-81b4-b5d530f0ea7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874633457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1874633457
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.757923354
Short name T316
Test name
Test status
Simulation time 209141081396 ps
CPU time 235.02 seconds
Started May 02 01:28:16 PM PDT 24
Finished May 02 01:32:12 PM PDT 24
Peak memory 191132 kb
Host smart-9fc4d1b7-ef72-4697-92e9-84befbf1ac64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757923354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.757923354
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1431760397
Short name T292
Test name
Test status
Simulation time 21316809942 ps
CPU time 11.26 seconds
Started May 02 01:19:20 PM PDT 24
Finished May 02 01:19:33 PM PDT 24
Peak memory 182900 kb
Host smart-8f8e1cbc-3508-4a87-a40a-f22fb9a7bce8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431760397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1431760397
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2046844517
Short name T435
Test name
Test status
Simulation time 349151074022 ps
CPU time 143.22 seconds
Started May 02 01:19:20 PM PDT 24
Finished May 02 01:21:44 PM PDT 24
Peak memory 183020 kb
Host smart-b6551cf3-8fe3-442f-8033-22fd3d0ebcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046844517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2046844517
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.179246970
Short name T85
Test name
Test status
Simulation time 53240641980 ps
CPU time 80.76 seconds
Started May 02 01:19:21 PM PDT 24
Finished May 02 01:20:42 PM PDT 24
Peak memory 193520 kb
Host smart-e748a932-6f5c-4c5d-82cb-b9c1906c7b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179246970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.179246970
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2191121522
Short name T251
Test name
Test status
Simulation time 47178874142 ps
CPU time 78.69 seconds
Started May 02 01:19:23 PM PDT 24
Finished May 02 01:20:43 PM PDT 24
Peak memory 191116 kb
Host smart-863c99fb-df57-43bc-b608-561c85889df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191121522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2191121522
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.4212103613
Short name T280
Test name
Test status
Simulation time 339953995930 ps
CPU time 944.04 seconds
Started May 02 01:19:20 PM PDT 24
Finished May 02 01:35:06 PM PDT 24
Peak memory 191224 kb
Host smart-d46729c7-40df-476d-bb3e-3a2a98731d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212103613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
4212103613
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.1251541855
Short name T169
Test name
Test status
Simulation time 280231493914 ps
CPU time 144.77 seconds
Started May 02 01:28:14 PM PDT 24
Finished May 02 01:30:40 PM PDT 24
Peak memory 191228 kb
Host smart-3e3ebf38-c90c-4731-b5c4-111c871ba4e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251541855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1251541855
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.4056529280
Short name T70
Test name
Test status
Simulation time 124883054803 ps
CPU time 775.26 seconds
Started May 02 01:28:14 PM PDT 24
Finished May 02 01:41:11 PM PDT 24
Peak memory 191220 kb
Host smart-1896e4ad-6b95-481e-a684-025968ff77c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056529280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.4056529280
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2702169098
Short name T355
Test name
Test status
Simulation time 759973482434 ps
CPU time 385.9 seconds
Started May 02 01:28:14 PM PDT 24
Finished May 02 01:34:41 PM PDT 24
Peak memory 191252 kb
Host smart-3d3f8002-cdf6-49ac-aca6-00307838591d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702169098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2702169098
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2611785949
Short name T170
Test name
Test status
Simulation time 715379814742 ps
CPU time 320.17 seconds
Started May 02 01:28:14 PM PDT 24
Finished May 02 01:33:36 PM PDT 24
Peak memory 191092 kb
Host smart-2ec1b81d-fe34-4bd9-9ffc-d8aaeb248e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611785949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2611785949
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1987006109
Short name T21
Test name
Test status
Simulation time 130181941429 ps
CPU time 336.05 seconds
Started May 02 01:28:15 PM PDT 24
Finished May 02 01:33:52 PM PDT 24
Peak memory 191136 kb
Host smart-d340412a-0f81-40e3-a744-517500a82eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987006109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1987006109
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.716381136
Short name T348
Test name
Test status
Simulation time 128604738895 ps
CPU time 135.34 seconds
Started May 02 01:28:22 PM PDT 24
Finished May 02 01:30:38 PM PDT 24
Peak memory 191204 kb
Host smart-7b722352-7ddb-4596-9a7e-a7bc743acb1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716381136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.716381136
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2610650492
Short name T324
Test name
Test status
Simulation time 41771282878 ps
CPU time 68.71 seconds
Started May 02 01:28:30 PM PDT 24
Finished May 02 01:29:39 PM PDT 24
Peak memory 194312 kb
Host smart-aa2dd930-aa70-4711-a004-c66758229b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610650492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2610650492
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2986639229
Short name T269
Test name
Test status
Simulation time 501511545083 ps
CPU time 510.82 seconds
Started May 02 01:28:28 PM PDT 24
Finished May 02 01:37:00 PM PDT 24
Peak memory 191076 kb
Host smart-af3976c2-6603-4a2f-a16b-b6ae9da4d72c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986639229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2986639229
Directory /workspace/99.rv_timer_random/latest
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