Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
1307 |
1 |
|
T6 |
44 |
|
T11 |
38 |
|
T14 |
31 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
682 |
1 |
|
T6 |
20 |
|
T11 |
26 |
|
T14 |
5 |
auto[1] |
625 |
1 |
|
T6 |
24 |
|
T11 |
12 |
|
T14 |
26 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
482 |
1 |
|
T6 |
26 |
|
T11 |
22 |
|
T14 |
10 |
auto[1] |
825 |
1 |
|
T6 |
18 |
|
T11 |
16 |
|
T14 |
21 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
739 |
1 |
|
T6 |
30 |
|
T11 |
25 |
|
T14 |
18 |
auto[1] |
568 |
1 |
|
T6 |
14 |
|
T11 |
13 |
|
T14 |
13 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
268 |
1 |
|
T6 |
11 |
|
T11 |
17 |
|
T14 |
2 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
125 |
1 |
|
T6 |
2 |
|
T11 |
2 |
|
T14 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
214 |
1 |
|
T6 |
15 |
|
T11 |
5 |
|
T14 |
8 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
132 |
1 |
|
T6 |
2 |
|
T11 |
1 |
|
T14 |
7 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
289 |
1 |
|
T6 |
7 |
|
T11 |
7 |
|
T14 |
2 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
279 |
1 |
|
T6 |
7 |
|
T11 |
6 |
|
T14 |
11 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |