| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.59 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.43 |
| T507 | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1360888171 | May 05 01:23:49 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 52046628 ps | ||
| T508 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2217691971 | May 05 01:23:32 PM PDT 24 | May 05 01:23:33 PM PDT 24 | 29382980 ps | ||
| T509 | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2430895664 | May 05 01:23:45 PM PDT 24 | May 05 01:23:49 PM PDT 24 | 196846769 ps | ||
| T510 | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3087964874 | May 05 01:23:42 PM PDT 24 | May 05 01:23:44 PM PDT 24 | 466843896 ps | ||
| T511 | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.843081256 | May 05 01:23:51 PM PDT 24 | May 05 01:23:52 PM PDT 24 | 35983762 ps | ||
| T512 | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2200764503 | May 05 01:23:50 PM PDT 24 | May 05 01:23:51 PM PDT 24 | 12543592 ps | ||
| T513 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3297828452 | May 05 01:23:26 PM PDT 24 | May 05 01:23:27 PM PDT 24 | 25856768 ps | ||
| T514 | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1544499633 | May 05 01:23:37 PM PDT 24 | May 05 01:23:38 PM PDT 24 | 168675661 ps | ||
| T515 | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1950413647 | May 05 01:23:47 PM PDT 24 | May 05 01:23:49 PM PDT 24 | 195391412 ps | ||
| T516 | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4142949554 | May 05 01:23:41 PM PDT 24 | May 05 01:23:42 PM PDT 24 | 28104406 ps | ||
| T517 | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1722197938 | May 05 01:23:30 PM PDT 24 | May 05 01:23:33 PM PDT 24 | 164524471 ps | ||
| T518 | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2104655717 | May 05 01:23:49 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 11097265 ps | ||
| T519 | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1293382765 | May 05 01:23:50 PM PDT 24 | May 05 01:23:51 PM PDT 24 | 30962351 ps | ||
| T520 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1678914695 | May 05 01:23:24 PM PDT 24 | May 05 01:23:27 PM PDT 24 | 196791772 ps | ||
| T521 | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1693138851 | May 05 01:23:41 PM PDT 24 | May 05 01:23:42 PM PDT 24 | 26831697 ps | ||
| T522 | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2541971400 | May 05 01:23:56 PM PDT 24 | May 05 01:23:57 PM PDT 24 | 15082042 ps | ||
| T523 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.977081984 | May 05 01:23:32 PM PDT 24 | May 05 01:23:33 PM PDT 24 | 128414188 ps | ||
| T524 | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2355796687 | May 05 01:23:35 PM PDT 24 | May 05 01:23:36 PM PDT 24 | 156378975 ps | ||
| T525 | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.233851236 | May 05 01:23:34 PM PDT 24 | May 05 01:23:36 PM PDT 24 | 287824877 ps | ||
| T95 | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.833473178 | May 05 01:23:34 PM PDT 24 | May 05 01:23:35 PM PDT 24 | 134953011 ps | ||
| T96 | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1569188643 | May 05 01:23:46 PM PDT 24 | May 05 01:23:48 PM PDT 24 | 597389931 ps | ||
| T526 | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3076535731 | May 05 01:23:58 PM PDT 24 | May 05 01:24:00 PM PDT 24 | 29517024 ps | ||
| T527 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2289843053 | May 05 01:23:29 PM PDT 24 | May 05 01:23:31 PM PDT 24 | 979222282 ps | ||
| T528 | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1023376848 | May 05 01:23:56 PM PDT 24 | May 05 01:23:57 PM PDT 24 | 20407346 ps | ||
| T529 | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1202663539 | May 05 01:23:42 PM PDT 24 | May 05 01:23:45 PM PDT 24 | 171265258 ps | ||
| T530 | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2283441782 | May 05 01:23:52 PM PDT 24 | May 05 01:23:53 PM PDT 24 | 12244171 ps | ||
| T531 | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.998680062 | May 05 01:23:47 PM PDT 24 | May 05 01:23:49 PM PDT 24 | 32857306 ps | ||
| T532 | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.749692876 | May 05 01:23:31 PM PDT 24 | May 05 01:23:32 PM PDT 24 | 14493011 ps | ||
| T533 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4015270424 | May 05 01:23:37 PM PDT 24 | May 05 01:23:38 PM PDT 24 | 40459137 ps | ||
| T84 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.59179395 | May 05 01:23:31 PM PDT 24 | May 05 01:23:35 PM PDT 24 | 151531735 ps | ||
| T534 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2958770230 | May 05 01:23:33 PM PDT 24 | May 05 01:23:34 PM PDT 24 | 31386804 ps | ||
| T535 | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1346331071 | May 05 01:23:51 PM PDT 24 | May 05 01:23:52 PM PDT 24 | 149097559 ps | ||
| T536 | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.265273512 | May 05 01:23:51 PM PDT 24 | May 05 01:23:53 PM PDT 24 | 18302038 ps | ||
| T537 | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2331232179 | May 05 01:23:24 PM PDT 24 | May 05 01:23:25 PM PDT 24 | 69727707 ps | ||
| T538 | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.646795289 | May 05 01:23:51 PM PDT 24 | May 05 01:23:52 PM PDT 24 | 97899140 ps | ||
| T539 | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.208795027 | May 05 01:23:49 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 15038532 ps | ||
| T82 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3499141428 | May 05 01:23:43 PM PDT 24 | May 05 01:23:44 PM PDT 24 | 12592151 ps | ||
| T540 | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2429256995 | May 05 01:23:52 PM PDT 24 | May 05 01:23:54 PM PDT 24 | 13858773 ps | ||
| T541 | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2235268345 | May 05 01:23:49 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 100454674 ps | ||
| T542 | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.214320201 | May 05 01:23:40 PM PDT 24 | May 05 01:23:42 PM PDT 24 | 1229325984 ps | ||
| T543 | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2479879371 | May 05 01:23:36 PM PDT 24 | May 05 01:23:38 PM PDT 24 | 599315190 ps | ||
| T544 | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2774110466 | May 05 01:23:34 PM PDT 24 | May 05 01:23:37 PM PDT 24 | 49346195 ps | ||
| T545 | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.915885140 | May 05 01:23:56 PM PDT 24 | May 05 01:23:57 PM PDT 24 | 24389295 ps | ||
| T546 | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1527063972 | May 05 01:23:56 PM PDT 24 | May 05 01:23:57 PM PDT 24 | 39411629 ps | ||
| T86 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.689439897 | May 05 01:23:25 PM PDT 24 | May 05 01:23:26 PM PDT 24 | 16177391 ps | ||
| T547 | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.892671796 | May 05 01:23:47 PM PDT 24 | May 05 01:23:48 PM PDT 24 | 45678117 ps | ||
| T548 | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2706664069 | May 05 01:23:55 PM PDT 24 | May 05 01:23:56 PM PDT 24 | 43182399 ps | ||
| T549 | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1061634473 | May 05 01:23:48 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 66078033 ps | ||
| T550 | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1698803572 | May 05 01:23:47 PM PDT 24 | May 05 01:23:49 PM PDT 24 | 226712318 ps | ||
| T551 | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3209491661 | May 05 01:23:27 PM PDT 24 | May 05 01:23:29 PM PDT 24 | 38481348 ps | ||
| T552 | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2389979803 | May 05 01:23:51 PM PDT 24 | May 05 01:23:52 PM PDT 24 | 48657933 ps | ||
| T553 | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1606121184 | May 05 01:23:49 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 73130501 ps | ||
| T554 | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3196312911 | May 05 01:23:51 PM PDT 24 | May 05 01:23:52 PM PDT 24 | 11420142 ps | ||
| T555 | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1405795516 | May 05 01:23:44 PM PDT 24 | May 05 01:23:45 PM PDT 24 | 19146970 ps | ||
| T556 | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2287113354 | May 05 01:23:45 PM PDT 24 | May 05 01:23:48 PM PDT 24 | 248436531 ps | ||
| T557 | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1302882013 | May 05 01:23:28 PM PDT 24 | May 05 01:23:29 PM PDT 24 | 20953451 ps | ||
| T85 | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.362072031 | May 05 01:23:45 PM PDT 24 | May 05 01:23:46 PM PDT 24 | 18039280 ps | ||
| T558 | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3931977218 | May 05 01:23:28 PM PDT 24 | May 05 01:23:30 PM PDT 24 | 410427256 ps | ||
| T559 | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2834705868 | May 05 01:23:45 PM PDT 24 | May 05 01:23:46 PM PDT 24 | 44136396 ps | ||
| T560 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1506174359 | May 05 01:23:40 PM PDT 24 | May 05 01:23:41 PM PDT 24 | 76456310 ps | ||
| T561 | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.163021607 | May 05 01:23:47 PM PDT 24 | May 05 01:23:48 PM PDT 24 | 42989348 ps | ||
| T562 | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3400952099 | May 05 01:23:39 PM PDT 24 | May 05 01:23:40 PM PDT 24 | 50903396 ps | ||
| T563 | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1322821663 | May 05 01:23:51 PM PDT 24 | May 05 01:23:52 PM PDT 24 | 14888170 ps | ||
| T564 | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.348198856 | May 05 01:23:54 PM PDT 24 | May 05 01:23:55 PM PDT 24 | 53960660 ps | ||
| T565 | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.28177661 | May 05 01:23:47 PM PDT 24 | May 05 01:23:48 PM PDT 24 | 60820279 ps | ||
| T566 | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.423998606 | May 05 01:23:50 PM PDT 24 | May 05 01:23:51 PM PDT 24 | 23333777 ps | ||
| T567 | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4270851041 | May 05 01:23:41 PM PDT 24 | May 05 01:23:45 PM PDT 24 | 313141329 ps | ||
| T568 | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.187749558 | May 05 01:23:43 PM PDT 24 | May 05 01:23:45 PM PDT 24 | 127760774 ps | ||
| T569 | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2535728458 | May 05 01:23:44 PM PDT 24 | May 05 01:23:45 PM PDT 24 | 70357020 ps | ||
| T570 | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.4156140553 | May 05 01:23:35 PM PDT 24 | May 05 01:23:36 PM PDT 24 | 33606264 ps | ||
| T571 | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1894470209 | May 05 01:23:49 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 336717992 ps | ||
| T572 | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1522003688 | May 05 01:23:46 PM PDT 24 | May 05 01:23:49 PM PDT 24 | 125479326 ps | ||
| T573 | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4171763618 | May 05 01:23:54 PM PDT 24 | May 05 01:23:55 PM PDT 24 | 66286211 ps | ||
| T574 | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.467704210 | May 05 01:23:37 PM PDT 24 | May 05 01:23:38 PM PDT 24 | 73975133 ps | ||
| T575 | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.662480384 | May 05 01:23:48 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 101590908 ps | ||
| T576 | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.286963606 | May 05 01:23:39 PM PDT 24 | May 05 01:23:40 PM PDT 24 | 78213331 ps | ||
| T577 | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1453403505 | May 05 01:23:46 PM PDT 24 | May 05 01:23:50 PM PDT 24 | 128653774 ps |
| Test location | /workspace/coverage/default/37.rv_timer_random.1447847116 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 130219899711 ps |
| CPU time | 753.23 seconds |
| Started | May 05 01:25:11 PM PDT 24 |
| Finished | May 05 01:37:45 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-7add23a3-bfdf-4d18-a0c1-bbb848258cca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447847116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1447847116 |
| Directory | /workspace/37.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.4047120617 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 36933958396 ps |
| CPU time | 155.29 seconds |
| Started | May 05 01:24:40 PM PDT 24 |
| Finished | May 05 01:27:16 PM PDT 24 |
| Peak memory | 197548 kb |
| Host | smart-c5c3afa3-3a55-4af8-b1d6-58e0240815e5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047120617 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.4047120617 |
| Directory | /workspace/14.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all.3221432484 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2959804243827 ps |
| CPU time | 2024 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:58:51 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-a4d9dc7c-7ae0-4c85-aa8b-b282423faeda |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221432484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all .3221432484 |
| Directory | /workspace/34.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all.1358344751 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1458238316545 ps |
| CPU time | 1888.15 seconds |
| Started | May 05 01:24:50 PM PDT 24 |
| Finished | May 05 01:56:18 PM PDT 24 |
| Peak memory | 196268 kb |
| Host | smart-63150a2b-7468-4b23-b2b2-98ed7f6dda51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358344751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all .1358344751 |
| Directory | /workspace/18.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4167866930 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 361462428 ps |
| CPU time | 1.32 seconds |
| Started | May 05 01:23:35 PM PDT 24 |
| Finished | May 05 01:23:37 PM PDT 24 |
| Peak memory | 195400 kb |
| Host | smart-7641fc24-4024-49bf-a094-f170ff3473e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167866930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.4167866930 |
| Directory | /workspace/4.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all.1127061547 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1081496512557 ps |
| CPU time | 5783.73 seconds |
| Started | May 05 01:24:52 PM PDT 24 |
| Finished | May 05 03:01:17 PM PDT 24 |
| Peak memory | 191104 kb |
| Host | smart-57f8ab62-dfda-4260-8fb1-f731a731d103 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127061547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all .1127061547 |
| Directory | /workspace/22.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all.1476159524 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1004249602220 ps |
| CPU time | 1527.22 seconds |
| Started | May 05 01:26:01 PM PDT 24 |
| Finished | May 05 01:51:29 PM PDT 24 |
| Peak memory | 191424 kb |
| Host | smart-9c3456ba-e4d6-45fb-a037-8fa6b2e8b1da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476159524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all .1476159524 |
| Directory | /workspace/49.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all.3892402836 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1062710020187 ps |
| CPU time | 2819.83 seconds |
| Started | May 05 01:25:07 PM PDT 24 |
| Finished | May 05 02:12:07 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-3b628cfd-15de-4f93-a785-2366aa506c71 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892402836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all .3892402836 |
| Directory | /workspace/33.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all.1109121037 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1141396621484 ps |
| CPU time | 2155.06 seconds |
| Started | May 05 01:24:42 PM PDT 24 |
| Finished | May 05 02:00:38 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-b20a4e2d-54c1-4769-af8b-ad25c2876f53 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109121037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all .1109121037 |
| Directory | /workspace/13.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2235215584 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 138191660305 ps |
| CPU time | 1658.85 seconds |
| Started | May 05 01:25:12 PM PDT 24 |
| Finished | May 05 01:52:52 PM PDT 24 |
| Peak memory | 211268 kb |
| Host | smart-cf225006-884b-4973-94c4-c209781f2821 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235215584 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2235215584 |
| Directory | /workspace/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all.3100050937 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 340041803506 ps |
| CPU time | 1335.49 seconds |
| Started | May 05 01:25:07 PM PDT 24 |
| Finished | May 05 01:47:23 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-6cc7a3b8-f781-45e1-a84a-1eb48be7e54f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100050937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all .3100050937 |
| Directory | /workspace/32.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all.4100554137 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 354177329391 ps |
| CPU time | 1207.13 seconds |
| Started | May 05 01:24:44 PM PDT 24 |
| Finished | May 05 01:44:52 PM PDT 24 |
| Peak memory | 195616 kb |
| Host | smart-1611a15f-995f-4803-8e81-3ff9881de886 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100554137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all .4100554137 |
| Directory | /workspace/16.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_timer_sec_cm.1514930419 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 126678581 ps |
| CPU time | 0.72 seconds |
| Started | May 05 01:24:27 PM PDT 24 |
| Finished | May 05 01:24:28 PM PDT 24 |
| Peak memory | 213304 kb |
| Host | smart-d4d948f6-9123-41c6-868d-f259ad3307b0 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514930419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1514930419 |
| Directory | /workspace/0.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all.2843805236 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 324388208207 ps |
| CPU time | 1022.39 seconds |
| Started | May 05 01:25:56 PM PDT 24 |
| Finished | May 05 01:42:59 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-5f9373ad-6b78-46c4-800d-cde186d8d15c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843805236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all .2843805236 |
| Directory | /workspace/47.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all.4258034429 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 401774852089 ps |
| CPU time | 1317.16 seconds |
| Started | May 05 01:25:56 PM PDT 24 |
| Finished | May 05 01:47:54 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-5dfd6282-247a-4690-9dd6-571d3597432d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258034429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all .4258034429 |
| Directory | /workspace/48.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all.734068909 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 251649150550 ps |
| CPU time | 781.52 seconds |
| Started | May 05 01:24:57 PM PDT 24 |
| Finished | May 05 01:37:59 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-1de80ec5-8a4c-47a9-a138-cd72d57e4a77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734068909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all. 734068909 |
| Directory | /workspace/26.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all.2395169528 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 405829178957 ps |
| CPU time | 2381.43 seconds |
| Started | May 05 01:24:45 PM PDT 24 |
| Finished | May 05 02:04:28 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-5c4cccd7-a675-431d-afb7-0db8a62115f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395169528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all .2395169528 |
| Directory | /workspace/19.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all.293815711 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2060790617949 ps |
| CPU time | 1174.17 seconds |
| Started | May 05 01:25:07 PM PDT 24 |
| Finished | May 05 01:44:42 PM PDT 24 |
| Peak memory | 191424 kb |
| Host | smart-ac5c590a-18c9-4718-b6e5-ce7037b6d952 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293815711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all. 293815711 |
| Directory | /workspace/35.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/173.rv_timer_random.2001614274 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 175355147054 ps |
| CPU time | 592.47 seconds |
| Started | May 05 01:27:47 PM PDT 24 |
| Finished | May 05 01:37:40 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-39b7914d-04e3-4fe1-8ca6-677c7583b2a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001614274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2001614274 |
| Directory | /workspace/173.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all.3309750335 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1021942303545 ps |
| CPU time | 1330.12 seconds |
| Started | May 05 01:24:32 PM PDT 24 |
| Finished | May 05 01:46:43 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-9dc7de57-ccad-4089-a911-7a119ae98a6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309750335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 3309750335 |
| Directory | /workspace/8.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/118.rv_timer_random.1147991530 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1037487691935 ps |
| CPU time | 409.33 seconds |
| Started | May 05 01:26:58 PM PDT 24 |
| Finished | May 05 01:33:48 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-bbb5007e-2878-4e27-8e31-0b4b6f7b7c12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147991530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1147991530 |
| Directory | /workspace/118.rv_timer_random/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random.1606203305 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 225671854829 ps |
| CPU time | 272.33 seconds |
| Started | May 05 01:24:26 PM PDT 24 |
| Finished | May 05 01:28:59 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-d93c17df-7aca-4b63-bec4-e1b83d88674d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606203305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1606203305 |
| Directory | /workspace/5.rv_timer_random/latest |
| Test location | /workspace/coverage/default/177.rv_timer_random.561534510 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 99664932566 ps |
| CPU time | 174.94 seconds |
| Started | May 05 01:27:52 PM PDT 24 |
| Finished | May 05 01:30:48 PM PDT 24 |
| Peak memory | 191088 kb |
| Host | smart-d9202dc6-66c2-4b7f-b1df-10c044e8b31e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561534510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.561534510 |
| Directory | /workspace/177.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all.844838275 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 943335600646 ps |
| CPU time | 1212.58 seconds |
| Started | May 05 01:24:59 PM PDT 24 |
| Finished | May 05 01:45:13 PM PDT 24 |
| Peak memory | 191136 kb |
| Host | smart-f5f3eb81-dab9-4eab-bbd0-0636d7e228fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844838275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all. 844838275 |
| Directory | /workspace/28.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all.4081858878 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 615831764307 ps |
| CPU time | 953.09 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:40:24 PM PDT 24 |
| Peak memory | 191136 kb |
| Host | smart-cd320f54-8bc2-4e0c-8d7f-0997ae3e84f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081858878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 4081858878 |
| Directory | /workspace/4.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random.1809388531 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 205949454668 ps |
| CPU time | 563.56 seconds |
| Started | May 05 01:24:38 PM PDT 24 |
| Finished | May 05 01:34:02 PM PDT 24 |
| Peak memory | 191096 kb |
| Host | smart-156ae8c1-52ee-4a44-a14c-11ace3a43000 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809388531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1809388531 |
| Directory | /workspace/10.rv_timer_random/latest |
| Test location | /workspace/coverage/default/145.rv_timer_random.371721124 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 269747417067 ps |
| CPU time | 262.46 seconds |
| Started | May 05 01:27:26 PM PDT 24 |
| Finished | May 05 01:31:49 PM PDT 24 |
| Peak memory | 191132 kb |
| Host | smart-493c7a2c-390c-4ccb-a682-e9c478dd9a4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371721124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.371721124 |
| Directory | /workspace/145.rv_timer_random/latest |
| Test location | /workspace/coverage/default/166.rv_timer_random.198828288 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 356368610980 ps |
| CPU time | 315.91 seconds |
| Started | May 05 01:27:37 PM PDT 24 |
| Finished | May 05 01:32:54 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-373ac405-a27d-47fa-ae37-0cccf525c3e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198828288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.198828288 |
| Directory | /workspace/166.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random.2720718342 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 577639148663 ps |
| CPU time | 496.16 seconds |
| Started | May 05 01:25:16 PM PDT 24 |
| Finished | May 05 01:33:33 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-8fd354ba-1f18-4187-99d3-282797f2b8ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720718342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2720718342 |
| Directory | /workspace/39.rv_timer_random/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random.2815259693 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 312550622651 ps |
| CPU time | 530.49 seconds |
| Started | May 05 01:25:46 PM PDT 24 |
| Finished | May 05 01:34:37 PM PDT 24 |
| Peak memory | 191208 kb |
| Host | smart-44f3cc9a-b8a7-4026-9702-d82c56d36be8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815259693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2815259693 |
| Directory | /workspace/46.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2948771372 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 14767482 ps |
| CPU time | 0.64 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:43 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-0e348734-0e25-42ab-bfad-0cd5c546bcd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948771372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2948771372 |
| Directory | /workspace/14.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2320027957 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 66664209706 ps |
| CPU time | 109.69 seconds |
| Started | May 05 01:24:39 PM PDT 24 |
| Finished | May 05 01:26:30 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-61bea489-65a4-4909-8f4d-9c91148fbc95 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320027957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.2320027957 |
| Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/156.rv_timer_random.2951324362 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 497220567409 ps |
| CPU time | 271.8 seconds |
| Started | May 05 01:27:35 PM PDT 24 |
| Finished | May 05 01:32:07 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-9d87d068-0fca-4b6c-a405-a7c55f6fff25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951324362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2951324362 |
| Directory | /workspace/156.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random.1767425258 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 190711071467 ps |
| CPU time | 595.99 seconds |
| Started | May 05 01:25:02 PM PDT 24 |
| Finished | May 05 01:34:59 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-6cfa55e3-247b-42c4-8730-685bc3b555a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767425258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1767425258 |
| Directory | /workspace/28.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random.682210339 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 19874165496 ps |
| CPU time | 39.39 seconds |
| Started | May 05 01:25:12 PM PDT 24 |
| Finished | May 05 01:25:52 PM PDT 24 |
| Peak memory | 191412 kb |
| Host | smart-84b90810-0c57-4b28-9e73-5098ef681fca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682210339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.682210339 |
| Directory | /workspace/38.rv_timer_random/latest |
| Test location | /workspace/coverage/default/97.rv_timer_random.234213883 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 915412925456 ps |
| CPU time | 610.56 seconds |
| Started | May 05 01:26:36 PM PDT 24 |
| Finished | May 05 01:36:47 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-83229adb-309d-4ac6-ad6f-6186a7c1903d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234213883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.234213883 |
| Directory | /workspace/97.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random.4077032498 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 502983736947 ps |
| CPU time | 305.38 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:29:36 PM PDT 24 |
| Peak memory | 191128 kb |
| Host | smart-f29ad9d8-50bc-4c54-8c99-81087da8bb04 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077032498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.4077032498 |
| Directory | /workspace/0.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all.3808170630 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 555803216485 ps |
| CPU time | 1411.42 seconds |
| Started | May 05 01:24:28 PM PDT 24 |
| Finished | May 05 01:48:00 PM PDT 24 |
| Peak memory | 193480 kb |
| Host | smart-b284759f-2d44-4fd6-b305-43b24e55b8c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808170630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 3808170630 |
| Directory | /workspace/1.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/119.rv_timer_random.3364504076 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 53349834317 ps |
| CPU time | 146.89 seconds |
| Started | May 05 01:27:00 PM PDT 24 |
| Finished | May 05 01:29:27 PM PDT 24 |
| Peak memory | 191420 kb |
| Host | smart-8d0fc70c-a009-4811-bd09-6a5d0ac2dc35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364504076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3364504076 |
| Directory | /workspace/119.rv_timer_random/latest |
| Test location | /workspace/coverage/default/154.rv_timer_random.3770757542 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 114318132256 ps |
| CPU time | 175.01 seconds |
| Started | May 05 01:27:33 PM PDT 24 |
| Finished | May 05 01:30:29 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-8ff6cc74-94bb-46c0-b8d2-6d463dfadbd8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770757542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3770757542 |
| Directory | /workspace/154.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all.3057876269 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 151584653688 ps |
| CPU time | 289.5 seconds |
| Started | May 05 01:25:13 PM PDT 24 |
| Finished | May 05 01:30:03 PM PDT 24 |
| Peak memory | 195568 kb |
| Host | smart-b99231b7-0d37-47dd-b8cc-02a3c12125b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057876269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .3057876269 |
| Directory | /workspace/37.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/101.rv_timer_random.2655427133 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 158345076206 ps |
| CPU time | 156.24 seconds |
| Started | May 05 01:26:41 PM PDT 24 |
| Finished | May 05 01:29:18 PM PDT 24 |
| Peak memory | 191132 kb |
| Host | smart-45e7a486-2fac-4801-86c8-a6caf2b853b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655427133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2655427133 |
| Directory | /workspace/101.rv_timer_random/latest |
| Test location | /workspace/coverage/default/105.rv_timer_random.1992545205 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 479246315675 ps |
| CPU time | 199.93 seconds |
| Started | May 05 01:26:44 PM PDT 24 |
| Finished | May 05 01:30:04 PM PDT 24 |
| Peak memory | 191140 kb |
| Host | smart-34917741-1ca1-4368-912a-c17bd58d0436 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992545205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1992545205 |
| Directory | /workspace/105.rv_timer_random/latest |
| Test location | /workspace/coverage/default/106.rv_timer_random.3814191726 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 171408448941 ps |
| CPU time | 875.15 seconds |
| Started | May 05 01:26:45 PM PDT 24 |
| Finished | May 05 01:41:21 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-38dcaf92-d849-477f-97e2-1c1c49f46846 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814191726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3814191726 |
| Directory | /workspace/106.rv_timer_random/latest |
| Test location | /workspace/coverage/default/110.rv_timer_random.1897118901 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1307477360271 ps |
| CPU time | 486.5 seconds |
| Started | May 05 01:26:54 PM PDT 24 |
| Finished | May 05 01:35:01 PM PDT 24 |
| Peak memory | 191108 kb |
| Host | smart-d8a98f73-4634-4a38-b7f5-4ba08a98b6ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897118901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1897118901 |
| Directory | /workspace/110.rv_timer_random/latest |
| Test location | /workspace/coverage/default/143.rv_timer_random.1983873700 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 121608556582 ps |
| CPU time | 106.58 seconds |
| Started | May 05 01:27:19 PM PDT 24 |
| Finished | May 05 01:29:05 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-bde061d5-886a-4fcf-bf04-d2ed20e172d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983873700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1983873700 |
| Directory | /workspace/143.rv_timer_random/latest |
| Test location | /workspace/coverage/default/169.rv_timer_random.1670926623 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 134429625925 ps |
| CPU time | 184.35 seconds |
| Started | May 05 01:27:42 PM PDT 24 |
| Finished | May 05 01:30:47 PM PDT 24 |
| Peak memory | 193684 kb |
| Host | smart-0bf1a68d-1862-4bd6-bbdb-1951163b774c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670926623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1670926623 |
| Directory | /workspace/169.rv_timer_random/latest |
| Test location | /workspace/coverage/default/195.rv_timer_random.19240058 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2320283841681 ps |
| CPU time | 690.08 seconds |
| Started | May 05 01:28:11 PM PDT 24 |
| Finished | May 05 01:39:42 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-5371d010-6709-4c42-b768-5dacf0087b53 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19240058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.19240058 |
| Directory | /workspace/195.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2347857257 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 958125321358 ps |
| CPU time | 861.16 seconds |
| Started | May 05 01:24:53 PM PDT 24 |
| Finished | May 05 01:39:14 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-f0e90a61-ca2c-4cb7-a755-b0f8f3bb426a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347857257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.2347857257 |
| Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random.3548411595 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 512246849224 ps |
| CPU time | 586.12 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:34:53 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-a9bb759a-ce56-48c5-b0f9-5c06b36ad7d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548411595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3548411595 |
| Directory | /workspace/36.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random_reset.3782007198 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 61015460688 ps |
| CPU time | 132.47 seconds |
| Started | May 05 01:25:13 PM PDT 24 |
| Finished | May 05 01:27:26 PM PDT 24 |
| Peak memory | 182956 kb |
| Host | smart-94bbc7f3-f74c-4982-84cf-3e8fe0ee8a57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782007198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3782007198 |
| Directory | /workspace/37.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/53.rv_timer_random.1605721941 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 48388149079 ps |
| CPU time | 445.05 seconds |
| Started | May 05 01:26:02 PM PDT 24 |
| Finished | May 05 01:33:27 PM PDT 24 |
| Peak memory | 194860 kb |
| Host | smart-1b3e9112-6456-4a2c-8450-ba7ab9a9a67d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605721941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1605721941 |
| Directory | /workspace/53.rv_timer_random/latest |
| Test location | /workspace/coverage/default/90.rv_timer_random.504308126 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 95387640637 ps |
| CPU time | 207.06 seconds |
| Started | May 05 01:26:31 PM PDT 24 |
| Finished | May 05 01:29:58 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-3eea498e-ab8e-49e1-8b48-3e9a3a70c4e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504308126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.504308126 |
| Directory | /workspace/90.rv_timer_random/latest |
| Test location | /workspace/coverage/default/92.rv_timer_random.2707434785 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 631445206901 ps |
| CPU time | 662.54 seconds |
| Started | May 05 01:26:36 PM PDT 24 |
| Finished | May 05 01:37:39 PM PDT 24 |
| Peak memory | 193244 kb |
| Host | smart-3450458b-cc9c-413d-affb-1e65ce19ecee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707434785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2707434785 |
| Directory | /workspace/92.rv_timer_random/latest |
| Test location | /workspace/coverage/default/111.rv_timer_random.3373866476 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 319300326534 ps |
| CPU time | 1366.08 seconds |
| Started | May 05 01:26:55 PM PDT 24 |
| Finished | May 05 01:49:42 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-93e17491-72d7-4db5-987e-9d98f2ca30db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373866476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3373866476 |
| Directory | /workspace/111.rv_timer_random/latest |
| Test location | /workspace/coverage/default/126.rv_timer_random.3061217270 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 62754311328 ps |
| CPU time | 116.89 seconds |
| Started | May 05 01:27:04 PM PDT 24 |
| Finished | May 05 01:29:02 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-3325a718-96da-4ca2-a33d-024627727fee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061217270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3061217270 |
| Directory | /workspace/126.rv_timer_random/latest |
| Test location | /workspace/coverage/default/144.rv_timer_random.3617063706 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 273790457210 ps |
| CPU time | 288.28 seconds |
| Started | May 05 01:27:21 PM PDT 24 |
| Finished | May 05 01:32:10 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-c318f97c-126d-483b-b146-d2c0546d20e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617063706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3617063706 |
| Directory | /workspace/144.rv_timer_random/latest |
| Test location | /workspace/coverage/default/150.rv_timer_random.3971846013 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 96069339930 ps |
| CPU time | 123.01 seconds |
| Started | May 05 01:27:24 PM PDT 24 |
| Finished | May 05 01:29:27 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-43e15ce5-dece-4958-8e58-1c9ce84d6e06 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971846013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3971846013 |
| Directory | /workspace/150.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random_reset.1252232303 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 198110020730 ps |
| CPU time | 79.26 seconds |
| Started | May 05 01:24:49 PM PDT 24 |
| Finished | May 05 01:26:08 PM PDT 24 |
| Peak memory | 194428 kb |
| Host | smart-1d123ba3-a45d-4580-8113-2cd11bb7419b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252232303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1252232303 |
| Directory | /workspace/17.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/186.rv_timer_random.3346766983 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 374954004119 ps |
| CPU time | 353.41 seconds |
| Started | May 05 01:28:05 PM PDT 24 |
| Finished | May 05 01:33:58 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-ad6f29af-3255-4f7f-8e42-8577e9cb4fd4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346766983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3346766983 |
| Directory | /workspace/186.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random_reset.4059939117 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 140369376263 ps |
| CPU time | 79.73 seconds |
| Started | May 05 01:24:58 PM PDT 24 |
| Finished | May 05 01:26:18 PM PDT 24 |
| Peak memory | 193328 kb |
| Host | smart-4cf036c7-cd18-443d-bd42-f4989ebd2a74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059939117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4059939117 |
| Directory | /workspace/24.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random.3282725841 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 348952506820 ps |
| CPU time | 1482.92 seconds |
| Started | May 05 01:24:59 PM PDT 24 |
| Finished | May 05 01:49:43 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-f7e5c1ba-c494-4d54-a9e2-cd2affe5f9a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282725841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3282725841 |
| Directory | /workspace/25.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all.344778209 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 340620908819 ps |
| CPU time | 787.17 seconds |
| Started | May 05 01:25:07 PM PDT 24 |
| Finished | May 05 01:38:15 PM PDT 24 |
| Peak memory | 191104 kb |
| Host | smart-cc411f58-7383-4b92-9f99-1bdccdb16324 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344778209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all. 344778209 |
| Directory | /workspace/31.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random.2260631649 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 237744389238 ps |
| CPU time | 280.5 seconds |
| Started | May 05 01:25:04 PM PDT 24 |
| Finished | May 05 01:29:45 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-4a9b1ff3-41f2-4d22-91f0-c4c753ce477a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260631649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2260631649 |
| Directory | /workspace/35.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2035017215 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 108722263670 ps |
| CPU time | 108.92 seconds |
| Started | May 05 01:25:12 PM PDT 24 |
| Finished | May 05 01:27:02 PM PDT 24 |
| Peak memory | 183004 kb |
| Host | smart-001bc5dd-7ab6-4509-afa5-382aaeafeb94 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035017215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2035017215 |
| Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random.4110528644 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 227426777244 ps |
| CPU time | 125.5 seconds |
| Started | May 05 01:25:35 PM PDT 24 |
| Finished | May 05 01:27:40 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-2cf70179-3eb0-439f-b0f1-7500c6d923ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110528644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4110528644 |
| Directory | /workspace/43.rv_timer_random/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random_reset.2317678904 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 188029587466 ps |
| CPU time | 500.31 seconds |
| Started | May 05 01:26:01 PM PDT 24 |
| Finished | May 05 01:34:22 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-fbf7ffea-7506-4a0e-920d-d9f548b2abce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317678904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2317678904 |
| Directory | /workspace/49.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all.2226583187 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 549834400504 ps |
| CPU time | 754.24 seconds |
| Started | May 05 01:24:26 PM PDT 24 |
| Finished | May 05 01:37:01 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-e8e97d7f-8756-489b-81bb-2b17a39226bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226583187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 2226583187 |
| Directory | /workspace/5.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/96.rv_timer_random.4113519990 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 193437871242 ps |
| CPU time | 309.54 seconds |
| Started | May 05 01:26:36 PM PDT 24 |
| Finished | May 05 01:31:46 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-02c91523-9e84-484e-8bc5-842bd01052d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113519990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.4113519990 |
| Directory | /workspace/96.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2812804438 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 261745137223 ps |
| CPU time | 426.07 seconds |
| Started | May 05 01:24:27 PM PDT 24 |
| Finished | May 05 01:31:34 PM PDT 24 |
| Peak memory | 182956 kb |
| Host | smart-80eaebd5-4be1-41bb-ae7c-0a08574a7f0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812804438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.2812804438 |
| Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/102.rv_timer_random.3990643739 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 232762219541 ps |
| CPU time | 2445.48 seconds |
| Started | May 05 01:26:40 PM PDT 24 |
| Finished | May 05 02:07:26 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-1aeedacb-ef67-423c-82aa-15ac1e3ed519 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990643739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3990643739 |
| Directory | /workspace/102.rv_timer_random/latest |
| Test location | /workspace/coverage/default/103.rv_timer_random.1501510687 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 60841360050 ps |
| CPU time | 91.3 seconds |
| Started | May 05 01:26:45 PM PDT 24 |
| Finished | May 05 01:28:16 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-f570ce0a-7ac4-4ee7-937e-3b2620411b6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501510687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1501510687 |
| Directory | /workspace/103.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all.2696784158 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 159812393283 ps |
| CPU time | 230.86 seconds |
| Started | May 05 01:24:36 PM PDT 24 |
| Finished | May 05 01:28:28 PM PDT 24 |
| Peak memory | 194544 kb |
| Host | smart-27392a43-1ebb-4968-acf1-67ce65f06d0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696784158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .2696784158 |
| Directory | /workspace/11.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/113.rv_timer_random.1725386026 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 23885151485 ps |
| CPU time | 290.87 seconds |
| Started | May 05 01:26:54 PM PDT 24 |
| Finished | May 05 01:31:45 PM PDT 24 |
| Peak memory | 182940 kb |
| Host | smart-eac4c2eb-3913-4196-afc7-54cf8c14e601 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725386026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1725386026 |
| Directory | /workspace/113.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random_reset.4129190543 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 12251864602 ps |
| CPU time | 11.35 seconds |
| Started | May 05 01:24:39 PM PDT 24 |
| Finished | May 05 01:24:52 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-3ff8bd3b-a022-4ece-b2c3-40612fcbb922 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129190543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4129190543 |
| Directory | /workspace/12.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/131.rv_timer_random.120833397 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 84672851901 ps |
| CPU time | 331.84 seconds |
| Started | May 05 01:27:12 PM PDT 24 |
| Finished | May 05 01:32:44 PM PDT 24 |
| Peak memory | 191104 kb |
| Host | smart-031b5fe9-dc69-47cc-8c6d-4ac0745fbdee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120833397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.120833397 |
| Directory | /workspace/131.rv_timer_random/latest |
| Test location | /workspace/coverage/default/136.rv_timer_random.1205845894 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 634589410784 ps |
| CPU time | 656.5 seconds |
| Started | May 05 01:27:15 PM PDT 24 |
| Finished | May 05 01:38:12 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-33de6d6f-d527-4afd-bb25-91b0699dacf1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205845894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1205845894 |
| Directory | /workspace/136.rv_timer_random/latest |
| Test location | /workspace/coverage/default/146.rv_timer_random.159248975 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 175320491364 ps |
| CPU time | 156.88 seconds |
| Started | May 05 01:27:26 PM PDT 24 |
| Finished | May 05 01:30:03 PM PDT 24 |
| Peak memory | 191140 kb |
| Host | smart-6cfa1aa4-ff26-4a3d-9eda-74c0425dec2b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159248975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.159248975 |
| Directory | /workspace/146.rv_timer_random/latest |
| Test location | /workspace/coverage/default/159.rv_timer_random.2464412863 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 63008519952 ps |
| CPU time | 25.18 seconds |
| Started | May 05 01:27:35 PM PDT 24 |
| Finished | May 05 01:28:01 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-40838104-7de0-45c3-9ed6-33f35b477ad1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464412863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2464412863 |
| Directory | /workspace/159.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4008365618 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 695245890573 ps |
| CPU time | 345.22 seconds |
| Started | May 05 01:24:44 PM PDT 24 |
| Finished | May 05 01:30:30 PM PDT 24 |
| Peak memory | 183008 kb |
| Host | smart-bfc93ac7-5358-4d78-9672-e0bd3bbedd84 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008365618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.4008365618 |
| Directory | /workspace/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/165.rv_timer_random.4008321509 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 473544438321 ps |
| CPU time | 1024.63 seconds |
| Started | May 05 01:27:38 PM PDT 24 |
| Finished | May 05 01:44:43 PM PDT 24 |
| Peak memory | 191208 kb |
| Host | smart-b684a418-81e7-451c-aee0-f5e6fa2e4d04 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008321509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4008321509 |
| Directory | /workspace/165.rv_timer_random/latest |
| Test location | /workspace/coverage/default/176.rv_timer_random.2683213212 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 363779066424 ps |
| CPU time | 1229.01 seconds |
| Started | May 05 01:27:53 PM PDT 24 |
| Finished | May 05 01:48:23 PM PDT 24 |
| Peak memory | 191204 kb |
| Host | smart-17e514bd-6f2b-4026-a63a-c2a5ef9d05f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683213212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2683213212 |
| Directory | /workspace/176.rv_timer_random/latest |
| Test location | /workspace/coverage/default/182.rv_timer_random.1989519835 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 264392724706 ps |
| CPU time | 235.42 seconds |
| Started | May 05 01:28:04 PM PDT 24 |
| Finished | May 05 01:32:00 PM PDT 24 |
| Peak memory | 195380 kb |
| Host | smart-eb5609cb-0ef5-469c-8f23-b79ee70d5b23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989519835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1989519835 |
| Directory | /workspace/182.rv_timer_random/latest |
| Test location | /workspace/coverage/default/183.rv_timer_random.793549977 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1113495661563 ps |
| CPU time | 570.14 seconds |
| Started | May 05 01:27:57 PM PDT 24 |
| Finished | May 05 01:37:27 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-0564a825-3ef3-4d12-972a-73c47aed1955 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793549977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.793549977 |
| Directory | /workspace/183.rv_timer_random/latest |
| Test location | /workspace/coverage/default/189.rv_timer_random.1327590580 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 142440316319 ps |
| CPU time | 324.3 seconds |
| Started | May 05 01:28:02 PM PDT 24 |
| Finished | May 05 01:33:27 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-e6d1264d-990a-4b1f-905c-872da15651a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327590580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1327590580 |
| Directory | /workspace/189.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.843286740 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8124129013 ps |
| CPU time | 14.23 seconds |
| Started | May 05 01:24:47 PM PDT 24 |
| Finished | May 05 01:25:02 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-d6246abc-aae7-434e-a303-14f1e70c7757 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843286740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.rv_timer_cfg_update_on_fly.843286740 |
| Directory | /workspace/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/56.rv_timer_random.2047361998 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 106155026057 ps |
| CPU time | 165.56 seconds |
| Started | May 05 01:26:05 PM PDT 24 |
| Finished | May 05 01:28:51 PM PDT 24 |
| Peak memory | 191096 kb |
| Host | smart-411f1603-6900-4b98-9126-c59cb611b9d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047361998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2047361998 |
| Directory | /workspace/56.rv_timer_random/latest |
| Test location | /workspace/coverage/default/63.rv_timer_random.2441846505 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336559787319 ps |
| CPU time | 138.08 seconds |
| Started | May 05 01:26:11 PM PDT 24 |
| Finished | May 05 01:28:30 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-71acdc08-b0bd-4528-b87b-4ab10935ea6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441846505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2441846505 |
| Directory | /workspace/63.rv_timer_random/latest |
| Test location | /workspace/coverage/default/64.rv_timer_random.3394850328 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 145327636351 ps |
| CPU time | 220.57 seconds |
| Started | May 05 01:26:11 PM PDT 24 |
| Finished | May 05 01:29:52 PM PDT 24 |
| Peak memory | 191208 kb |
| Host | smart-0254da63-a5ff-466a-975b-4974b3bf30a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394850328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3394850328 |
| Directory | /workspace/64.rv_timer_random/latest |
| Test location | /workspace/coverage/default/84.rv_timer_random.3354298879 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 879083723256 ps |
| CPU time | 722.42 seconds |
| Started | May 05 01:26:31 PM PDT 24 |
| Finished | May 05 01:38:34 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-a937bb72-ea9c-4480-b403-bce12ff27b66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354298879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3354298879 |
| Directory | /workspace/84.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.400990022 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 25907805 ps |
| CPU time | 0.69 seconds |
| Started | May 05 01:23:25 PM PDT 24 |
| Finished | May 05 01:23:27 PM PDT 24 |
| Peak memory | 182756 kb |
| Host | smart-6ff40607-6bef-4aca-9132-23f3aefb7e8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400990022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias ing.400990022 |
| Directory | /workspace/0.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2289843053 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 979222282 ps |
| CPU time | 2.33 seconds |
| Started | May 05 01:23:29 PM PDT 24 |
| Finished | May 05 01:23:31 PM PDT 24 |
| Peak memory | 192404 kb |
| Host | smart-b051ab73-b8b4-4d0b-a0ea-ef96b1fefb68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289843053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ bash.2289843053 |
| Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3832569002 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 19525926 ps |
| CPU time | 0.59 seconds |
| Started | May 05 01:23:27 PM PDT 24 |
| Finished | May 05 01:23:28 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-d87e7666-ed44-4b8e-8d4b-8b02ccde08a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832569002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.3832569002 |
| Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4001148642 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 28314125 ps |
| CPU time | 0.68 seconds |
| Started | May 05 01:23:24 PM PDT 24 |
| Finished | May 05 01:23:25 PM PDT 24 |
| Peak memory | 194948 kb |
| Host | smart-c2530703-7313-4308-9bd6-515acd397e8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001148642 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.4001148642 |
| Directory | /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.689439897 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 16177391 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:25 PM PDT 24 |
| Finished | May 05 01:23:26 PM PDT 24 |
| Peak memory | 182672 kb |
| Host | smart-4c165cd5-8c76-4521-8f0d-9c4012135703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689439897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.689439897 |
| Directory | /workspace/0.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1609944566 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 15639207 ps |
| CPU time | 0.61 seconds |
| Started | May 05 01:23:29 PM PDT 24 |
| Finished | May 05 01:23:30 PM PDT 24 |
| Peak memory | 182600 kb |
| Host | smart-394a02ec-e6ec-4e18-a1dd-41c4e834b646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609944566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1609944566 |
| Directory | /workspace/0.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.157978744 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 26211556 ps |
| CPU time | 0.7 seconds |
| Started | May 05 01:23:27 PM PDT 24 |
| Finished | May 05 01:23:28 PM PDT 24 |
| Peak memory | 192112 kb |
| Host | smart-5588be0e-8cf5-44f4-9af1-b0187b23c103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157978744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim er_same_csr_outstanding.157978744 |
| Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2774110466 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 49346195 ps |
| CPU time | 2.58 seconds |
| Started | May 05 01:23:34 PM PDT 24 |
| Finished | May 05 01:23:37 PM PDT 24 |
| Peak memory | 197664 kb |
| Host | smart-19b0d8e4-b344-4e8c-b779-ccb454ec1db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774110466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2774110466 |
| Directory | /workspace/0.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2646864319 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 82104753 ps |
| CPU time | 0.86 seconds |
| Started | May 05 01:23:24 PM PDT 24 |
| Finished | May 05 01:23:26 PM PDT 24 |
| Peak memory | 194076 kb |
| Host | smart-cb07b491-c94f-4838-aa5e-94b87b2111ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646864319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in tg_err.2646864319 |
| Directory | /workspace/0.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3297828452 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 25856768 ps |
| CPU time | 0.75 seconds |
| Started | May 05 01:23:26 PM PDT 24 |
| Finished | May 05 01:23:27 PM PDT 24 |
| Peak memory | 192208 kb |
| Host | smart-ce4e692e-9fcf-44d3-8fd4-23e779149bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297828452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia sing.3297828452 |
| Directory | /workspace/1.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1678914695 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 196791772 ps |
| CPU time | 2.73 seconds |
| Started | May 05 01:23:24 PM PDT 24 |
| Finished | May 05 01:23:27 PM PDT 24 |
| Peak memory | 193580 kb |
| Host | smart-1f72aed3-d08d-4114-9a40-114fc06f9a41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678914695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ bash.1678914695 |
| Directory | /workspace/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2144104353 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 195516191 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:25 PM PDT 24 |
| Finished | May 05 01:23:26 PM PDT 24 |
| Peak memory | 182716 kb |
| Host | smart-442fb55f-4a0e-47a1-92e9-6fd182b00f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144104353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r eset.2144104353 |
| Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.977081984 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 128414188 ps |
| CPU time | 0.87 seconds |
| Started | May 05 01:23:32 PM PDT 24 |
| Finished | May 05 01:23:33 PM PDT 24 |
| Peak memory | 196912 kb |
| Host | smart-da088a46-afa1-4237-bd89-d06ee39d7f71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977081984 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.977081984 |
| Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3339766783 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 46768254 ps |
| CPU time | 0.58 seconds |
| Started | May 05 01:23:27 PM PDT 24 |
| Finished | May 05 01:23:28 PM PDT 24 |
| Peak memory | 182696 kb |
| Host | smart-05bb6f7f-333f-41d4-b549-548eb3d0019b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339766783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3339766783 |
| Directory | /workspace/1.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2331232179 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 69727707 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:24 PM PDT 24 |
| Finished | May 05 01:23:25 PM PDT 24 |
| Peak memory | 182620 kb |
| Host | smart-35d3ec89-bc37-48d3-821d-2e9bb6e3110c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331232179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2331232179 |
| Directory | /workspace/1.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1302882013 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 20953451 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:28 PM PDT 24 |
| Finished | May 05 01:23:29 PM PDT 24 |
| Peak memory | 191536 kb |
| Host | smart-5f2b36b8-b60b-49be-9097-6bd2ac924a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302882013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.1302882013 |
| Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.233851236 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 287824877 ps |
| CPU time | 1.48 seconds |
| Started | May 05 01:23:34 PM PDT 24 |
| Finished | May 05 01:23:36 PM PDT 24 |
| Peak memory | 197636 kb |
| Host | smart-182e10dc-a79c-462d-bc78-d06f62e835c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233851236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.233851236 |
| Directory | /workspace/1.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.833473178 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 134953011 ps |
| CPU time | 1.47 seconds |
| Started | May 05 01:23:34 PM PDT 24 |
| Finished | May 05 01:23:35 PM PDT 24 |
| Peak memory | 195524 kb |
| Host | smart-547560e1-8250-4cb5-b22d-efeb6d09b711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833473178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int g_err.833473178 |
| Directory | /workspace/1.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2635576493 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 62908978 ps |
| CPU time | 1.04 seconds |
| Started | May 05 01:23:41 PM PDT 24 |
| Finished | May 05 01:23:43 PM PDT 24 |
| Peak memory | 197444 kb |
| Host | smart-e014456a-763a-4c6e-893e-19cdd26586d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635576493 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2635576493 |
| Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2834705868 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 44136396 ps |
| CPU time | 0.58 seconds |
| Started | May 05 01:23:45 PM PDT 24 |
| Finished | May 05 01:23:46 PM PDT 24 |
| Peak memory | 182732 kb |
| Host | smart-abd31633-179f-44c5-9a3d-a5a25b3f6eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834705868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2834705868 |
| Directory | /workspace/10.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1442053967 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 63567950 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:43 PM PDT 24 |
| Peak memory | 182592 kb |
| Host | smart-c59da2e8-1ce8-439f-9783-b6fdf17b05f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442053967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1442053967 |
| Directory | /workspace/10.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.264266940 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 19004128 ps |
| CPU time | 0.78 seconds |
| Started | May 05 01:23:40 PM PDT 24 |
| Finished | May 05 01:23:42 PM PDT 24 |
| Peak memory | 191764 kb |
| Host | smart-a66ad585-8fe9-4ee6-ac9b-9813cc6af6f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264266940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti mer_same_csr_outstanding.264266940 |
| Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3861904933 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 519467940 ps |
| CPU time | 2.18 seconds |
| Started | May 05 01:23:46 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 197656 kb |
| Host | smart-3442609f-8f66-42ce-8ca3-ffa95e0e6982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861904933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3861904933 |
| Directory | /workspace/10.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.479509895 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 496738586 ps |
| CPU time | 1.29 seconds |
| Started | May 05 01:23:45 PM PDT 24 |
| Finished | May 05 01:23:47 PM PDT 24 |
| Peak memory | 195416 kb |
| Host | smart-7cadfb7a-8211-451c-b2b3-3cfe36706caf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479509895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in tg_err.479509895 |
| Directory | /workspace/10.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.286963606 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 78213331 ps |
| CPU time | 1.03 seconds |
| Started | May 05 01:23:39 PM PDT 24 |
| Finished | May 05 01:23:40 PM PDT 24 |
| Peak memory | 197484 kb |
| Host | smart-1632d282-8d78-41ce-82fa-1daa304dbdd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286963606 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.286963606 |
| Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.362072031 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 18039280 ps |
| CPU time | 0.61 seconds |
| Started | May 05 01:23:45 PM PDT 24 |
| Finished | May 05 01:23:46 PM PDT 24 |
| Peak memory | 182696 kb |
| Host | smart-e336c2e8-7017-481b-b378-8a788c884ac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362072031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.362072031 |
| Directory | /workspace/11.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2429256995 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 13858773 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:52 PM PDT 24 |
| Finished | May 05 01:23:54 PM PDT 24 |
| Peak memory | 182048 kb |
| Host | smart-40436755-f14a-4fb0-9301-1823cf0613a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429256995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2429256995 |
| Directory | /workspace/11.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1693138851 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 26831697 ps |
| CPU time | 0.72 seconds |
| Started | May 05 01:23:41 PM PDT 24 |
| Finished | May 05 01:23:42 PM PDT 24 |
| Peak memory | 193164 kb |
| Host | smart-c6421522-cc90-499d-954b-fc1136451047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693138851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.1693138851 |
| Directory | /workspace/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.723790773 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 180185118 ps |
| CPU time | 1.21 seconds |
| Started | May 05 01:23:45 PM PDT 24 |
| Finished | May 05 01:23:47 PM PDT 24 |
| Peak memory | 196924 kb |
| Host | smart-5130d220-25d9-4afa-8627-c7478a7b3aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723790773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.723790773 |
| Directory | /workspace/11.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3587799768 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 57630222 ps |
| CPU time | 0.84 seconds |
| Started | May 05 01:23:41 PM PDT 24 |
| Finished | May 05 01:23:43 PM PDT 24 |
| Peak memory | 183244 kb |
| Host | smart-19341ee2-61ce-41a0-9d2d-2dccef7c89b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587799768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i ntg_err.3587799768 |
| Directory | /workspace/11.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3087964874 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 466843896 ps |
| CPU time | 0.95 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:44 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-8f8b9fa9-f8da-44b6-bbe1-409791320bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087964874 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3087964874 |
| Directory | /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1265829177 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 13164706 ps |
| CPU time | 0.6 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:43 PM PDT 24 |
| Peak memory | 182768 kb |
| Host | smart-3b683add-5b77-468c-9294-7f8d807c53dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265829177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1265829177 |
| Directory | /workspace/12.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1376049368 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 42821995 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:41 PM PDT 24 |
| Finished | May 05 01:23:42 PM PDT 24 |
| Peak memory | 182704 kb |
| Host | smart-71436aa7-1924-4e3c-81f9-23cf95f08f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376049368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1376049368 |
| Directory | /workspace/12.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.646795289 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 97899140 ps |
| CPU time | 0.71 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 193124 kb |
| Host | smart-4c9d13f8-88a1-4d92-993b-39a14b5d3f41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646795289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti mer_same_csr_outstanding.646795289 |
| Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1522003688 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 125479326 ps |
| CPU time | 2.04 seconds |
| Started | May 05 01:23:46 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 197652 kb |
| Host | smart-9b76c650-60d3-4dd1-a3c8-e5b2b477e693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522003688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1522003688 |
| Directory | /workspace/12.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.167069434 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 249661774 ps |
| CPU time | 1.31 seconds |
| Started | May 05 01:23:46 PM PDT 24 |
| Finished | May 05 01:23:48 PM PDT 24 |
| Peak memory | 194548 kb |
| Host | smart-9c2d1aa8-f366-449f-8511-982406cb8c02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167069434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in tg_err.167069434 |
| Directory | /workspace/12.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.871242610 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 22339922 ps |
| CPU time | 0.7 seconds |
| Started | May 05 01:23:43 PM PDT 24 |
| Finished | May 05 01:23:44 PM PDT 24 |
| Peak memory | 194164 kb |
| Host | smart-4e640335-7f65-4cd9-8fb5-8cdfd664cadf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871242610 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.871242610 |
| Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.444309664 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 13771520 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:45 PM PDT 24 |
| Finished | May 05 01:23:46 PM PDT 24 |
| Peak memory | 182668 kb |
| Host | smart-0025a685-f025-4321-884f-9f76f733c093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444309664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.444309664 |
| Directory | /workspace/13.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4142949554 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 28104406 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:41 PM PDT 24 |
| Finished | May 05 01:23:42 PM PDT 24 |
| Peak memory | 182116 kb |
| Host | smart-7076a2c6-e06b-4b23-ab68-b4e48b4a2a63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142949554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.4142949554 |
| Directory | /workspace/13.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1894470209 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 336717992 ps |
| CPU time | 0.67 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 191232 kb |
| Host | smart-2b6782a9-0eda-4a0b-a988-8ff3d1891689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894470209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t imer_same_csr_outstanding.1894470209 |
| Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1202663539 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 171265258 ps |
| CPU time | 3.3 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:45 PM PDT 24 |
| Peak memory | 197600 kb |
| Host | smart-e13149f1-4d31-471f-a713-a891caf0d9b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202663539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1202663539 |
| Directory | /workspace/13.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.214320201 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1229325984 ps |
| CPU time | 1.07 seconds |
| Started | May 05 01:23:40 PM PDT 24 |
| Finished | May 05 01:23:42 PM PDT 24 |
| Peak memory | 195132 kb |
| Host | smart-b6e8bc9b-899a-4a91-9f21-7980cfdb9715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214320201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in tg_err.214320201 |
| Directory | /workspace/13.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1698803572 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 226712318 ps |
| CPU time | 0.67 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 193952 kb |
| Host | smart-dd4aee3c-a80b-4af7-8770-5cb752ea803c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698803572 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1698803572 |
| Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2104655717 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 11097265 ps |
| CPU time | 0.6 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 182168 kb |
| Host | smart-89b29d95-506f-4e49-9038-c68325778ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104655717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2104655717 |
| Directory | /workspace/14.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1606121184 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 73130501 ps |
| CPU time | 0.81 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 193376 kb |
| Host | smart-e6b6a0e7-77d3-45e3-a1ad-c5e7024da823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606121184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.1606121184 |
| Directory | /workspace/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2287113354 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 248436531 ps |
| CPU time | 2.3 seconds |
| Started | May 05 01:23:45 PM PDT 24 |
| Finished | May 05 01:23:48 PM PDT 24 |
| Peak memory | 197612 kb |
| Host | smart-8c7a6ba5-0153-4e1d-95de-1cf86db78ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287113354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2287113354 |
| Directory | /workspace/14.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4279045713 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 307538568 ps |
| CPU time | 1.14 seconds |
| Started | May 05 01:23:48 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 195376 kb |
| Host | smart-47594cf3-63a9-4dc2-a7a8-1ed9bce93854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279045713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.4279045713 |
| Directory | /workspace/14.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3374972617 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 19189270 ps |
| CPU time | 0.66 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:51 PM PDT 24 |
| Peak memory | 193536 kb |
| Host | smart-3b06e8c5-b10a-4852-a954-94634f378679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374972617 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3374972617 |
| Directory | /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1668169122 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 57120485 ps |
| CPU time | 0.59 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 182760 kb |
| Host | smart-a5025075-b8f3-4bd1-abdd-c3961e5fa84b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668169122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1668169122 |
| Directory | /workspace/15.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.163021607 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 42989348 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:48 PM PDT 24 |
| Peak memory | 182100 kb |
| Host | smart-9597e528-a344-4ec0-9872-deb9815348eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163021607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.163021607 |
| Directory | /workspace/15.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.348198856 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 53960660 ps |
| CPU time | 0.69 seconds |
| Started | May 05 01:23:54 PM PDT 24 |
| Finished | May 05 01:23:55 PM PDT 24 |
| Peak memory | 191660 kb |
| Host | smart-98f24e25-cc8c-4af0-aa7d-6c0e68a8e7ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348198856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti mer_same_csr_outstanding.348198856 |
| Directory | /workspace/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3124114671 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 559759474 ps |
| CPU time | 2.66 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 197596 kb |
| Host | smart-f9559d30-d78c-448e-8aaa-52439ffaf152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124114671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3124114671 |
| Directory | /workspace/15.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1950413647 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 195391412 ps |
| CPU time | 1.31 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 183364 kb |
| Host | smart-440300f5-d8b8-44fc-8cb1-edbaea14281d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950413647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i ntg_err.1950413647 |
| Directory | /workspace/15.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.998680062 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 32857306 ps |
| CPU time | 1.38 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 197652 kb |
| Host | smart-80c6c5f4-3b59-4d03-8f79-19a5cfbde25e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998680062 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.998680062 |
| Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2113208285 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 13992799 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:51 PM PDT 24 |
| Peak memory | 182440 kb |
| Host | smart-6a959c09-b968-4f28-9903-b4210fb53e97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113208285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2113208285 |
| Directory | /workspace/16.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.208795027 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 15038532 ps |
| CPU time | 0.59 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 182648 kb |
| Host | smart-4b898d67-e327-4c1f-8884-e814639b8147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208795027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.208795027 |
| Directory | /workspace/16.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.900447218 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 128316808 ps |
| CPU time | 0.83 seconds |
| Started | May 05 01:23:45 PM PDT 24 |
| Finished | May 05 01:23:47 PM PDT 24 |
| Peak memory | 193484 kb |
| Host | smart-107ad348-3235-4624-9a4b-63bf665b870a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900447218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti mer_same_csr_outstanding.900447218 |
| Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1392561401 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 180196671 ps |
| CPU time | 1.51 seconds |
| Started | May 05 01:23:46 PM PDT 24 |
| Finished | May 05 01:23:48 PM PDT 24 |
| Peak memory | 197504 kb |
| Host | smart-d2994200-fe18-4432-b43b-17f7791b11ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392561401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1392561401 |
| Directory | /workspace/16.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2960288818 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 638159701 ps |
| CPU time | 1.46 seconds |
| Started | May 05 01:23:48 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 183476 kb |
| Host | smart-f1b12af8-00b2-448d-a483-3fa3ce7c22ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960288818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i ntg_err.2960288818 |
| Directory | /workspace/16.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1374573621 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 29963614 ps |
| CPU time | 1.3 seconds |
| Started | May 05 01:23:50 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 197672 kb |
| Host | smart-4eff924f-6cd3-4f8a-9ac9-9db901e033e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374573621 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1374573621 |
| Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2977115034 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 12117078 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:48 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 182704 kb |
| Host | smart-ad8ce3f1-418d-4c92-a9a5-da6cd7178437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977115034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2977115034 |
| Directory | /workspace/17.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2688159744 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 22611695 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:46 PM PDT 24 |
| Finished | May 05 01:23:47 PM PDT 24 |
| Peak memory | 182300 kb |
| Host | smart-9c099411-1b7b-440a-bf13-3217e6b10944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688159744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2688159744 |
| Directory | /workspace/17.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.28177661 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 60820279 ps |
| CPU time | 0.61 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:48 PM PDT 24 |
| Peak memory | 191348 kb |
| Host | smart-a060e7ba-d1b6-424a-8e0e-b18f49671006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28177661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_tim er_same_csr_outstanding.28177661 |
| Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.279156997 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 56486788 ps |
| CPU time | 1.22 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 197572 kb |
| Host | smart-14686a26-6625-48f7-8b40-d1fda6df94f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279156997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.279156997 |
| Directory | /workspace/17.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1569188643 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 597389931 ps |
| CPU time | 1.08 seconds |
| Started | May 05 01:23:46 PM PDT 24 |
| Finished | May 05 01:23:48 PM PDT 24 |
| Peak memory | 195188 kb |
| Host | smart-a9b15570-d3c6-413a-9eb6-4465656f4653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569188643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i ntg_err.1569188643 |
| Directory | /workspace/17.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4171763618 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 66286211 ps |
| CPU time | 0.81 seconds |
| Started | May 05 01:23:54 PM PDT 24 |
| Finished | May 05 01:23:55 PM PDT 24 |
| Peak memory | 196856 kb |
| Host | smart-4085fc05-f3f4-47b8-b838-0e42067c67b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171763618 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4171763618 |
| Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.120563258 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 54199842 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 182624 kb |
| Host | smart-52d13013-3005-4345-903b-6e77b8e6833f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120563258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.120563258 |
| Directory | /workspace/18.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3538302734 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 11533359 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:48 PM PDT 24 |
| Peak memory | 182700 kb |
| Host | smart-1e8789f8-2088-4f5c-a8e7-b2a32cb27c94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538302734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3538302734 |
| Directory | /workspace/18.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.510164884 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 38616103 ps |
| CPU time | 0.81 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 193368 kb |
| Host | smart-cbc253e1-cee5-4ce6-8cb0-2f89a79adcc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510164884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti mer_same_csr_outstanding.510164884 |
| Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.662480384 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 101590908 ps |
| CPU time | 1.98 seconds |
| Started | May 05 01:23:48 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 197656 kb |
| Host | smart-0e85b36a-941f-418e-b7bd-6c44556942b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662480384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.662480384 |
| Directory | /workspace/18.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.682715703 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 87973639 ps |
| CPU time | 1.1 seconds |
| Started | May 05 01:23:48 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 195072 kb |
| Host | smart-7997233c-8b9a-47c4-85d1-151fc6eaa7e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682715703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in tg_err.682715703 |
| Directory | /workspace/18.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3409087378 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 33368153 ps |
| CPU time | 0.61 seconds |
| Started | May 05 01:23:53 PM PDT 24 |
| Finished | May 05 01:23:54 PM PDT 24 |
| Peak memory | 193020 kb |
| Host | smart-045a83b9-abee-4af0-a461-a228255557a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409087378 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3409087378 |
| Directory | /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2890772010 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 18728378 ps |
| CPU time | 0.52 seconds |
| Started | May 05 01:23:52 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 182756 kb |
| Host | smart-0b1207fb-1bd7-418b-a637-f863e8833318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890772010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2890772010 |
| Directory | /workspace/19.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.892671796 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 45678117 ps |
| CPU time | 0.56 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:48 PM PDT 24 |
| Peak memory | 182708 kb |
| Host | smart-5b0b2378-cdc0-4f53-a9ea-07871ccf9e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892671796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.892671796 |
| Directory | /workspace/19.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2235268345 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 100454674 ps |
| CPU time | 0.73 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-a867fe68-f2ce-4f45-a313-972c3fd29ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235268345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.2235268345 |
| Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1453403505 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 128653774 ps |
| CPU time | 3.1 seconds |
| Started | May 05 01:23:46 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 197640 kb |
| Host | smart-d73bc4b6-232c-454c-bf73-72de6bd7e1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453403505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1453403505 |
| Directory | /workspace/19.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2196850145 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 196340267 ps |
| CPU time | 1.09 seconds |
| Started | May 05 01:23:48 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 195288 kb |
| Host | smart-8a5b0a0a-a77f-4a56-866a-6a3ad1bf410a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196850145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i ntg_err.2196850145 |
| Directory | /workspace/19.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2806675396 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 435980626 ps |
| CPU time | 0.79 seconds |
| Started | May 05 01:23:28 PM PDT 24 |
| Finished | May 05 01:23:30 PM PDT 24 |
| Peak memory | 190952 kb |
| Host | smart-7b924c61-b20d-48c2-8c3c-e5146a9321bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806675396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia sing.2806675396 |
| Directory | /workspace/2.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.204517832 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 416414090 ps |
| CPU time | 3.7 seconds |
| Started | May 05 01:23:29 PM PDT 24 |
| Finished | May 05 01:23:33 PM PDT 24 |
| Peak memory | 192812 kb |
| Host | smart-369db30a-1981-47b9-93f0-abac0dd8e0f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204517832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b ash.204517832 |
| Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4078659909 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 36457133 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:28 PM PDT 24 |
| Finished | May 05 01:23:29 PM PDT 24 |
| Peak memory | 182768 kb |
| Host | smart-e7f20bd4-2778-4dc2-a331-06429be841bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078659909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r eset.4078659909 |
| Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1264013329 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 33055529 ps |
| CPU time | 0.82 seconds |
| Started | May 05 01:23:32 PM PDT 24 |
| Finished | May 05 01:23:33 PM PDT 24 |
| Peak memory | 195892 kb |
| Host | smart-bbea1e02-24c3-4f7c-9d06-15cca34cf902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264013329 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1264013329 |
| Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1809546884 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13730392 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:29 PM PDT 24 |
| Finished | May 05 01:23:30 PM PDT 24 |
| Peak memory | 182728 kb |
| Host | smart-5d940ba1-49aa-43eb-89df-8d2653dccf99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809546884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1809546884 |
| Directory | /workspace/2.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3218580138 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 48356795 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:32 PM PDT 24 |
| Finished | May 05 01:23:33 PM PDT 24 |
| Peak memory | 182644 kb |
| Host | smart-ef288990-ed4a-4d47-8119-cbb3e577aec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218580138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3218580138 |
| Directory | /workspace/2.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4108954982 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 16675209 ps |
| CPU time | 0.68 seconds |
| Started | May 05 01:23:28 PM PDT 24 |
| Finished | May 05 01:23:30 PM PDT 24 |
| Peak memory | 191532 kb |
| Host | smart-4cecd4a3-309f-4ef6-95df-077a19d3f0a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108954982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti mer_same_csr_outstanding.4108954982 |
| Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3209491661 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 38481348 ps |
| CPU time | 1.88 seconds |
| Started | May 05 01:23:27 PM PDT 24 |
| Finished | May 05 01:23:29 PM PDT 24 |
| Peak memory | 197660 kb |
| Host | smart-f6fa4fa6-7f8a-44f6-9883-201f054dc736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209491661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3209491661 |
| Directory | /workspace/2.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3931977218 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 410427256 ps |
| CPU time | 1.3 seconds |
| Started | May 05 01:23:28 PM PDT 24 |
| Finished | May 05 01:23:30 PM PDT 24 |
| Peak memory | 195452 kb |
| Host | smart-163b313a-ba54-457f-8396-0cd4354d7edb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931977218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in tg_err.3931977218 |
| Directory | /workspace/2.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.843081256 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 35983762 ps |
| CPU time | 0.56 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 182596 kb |
| Host | smart-628bfbb1-78d7-461d-99d8-029d600828be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843081256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.843081256 |
| Directory | /workspace/20.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1360888171 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 52046628 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 182604 kb |
| Host | smart-6399601c-919e-47d4-9e29-3a2fa0f83b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360888171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1360888171 |
| Directory | /workspace/21.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.350010454 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 16042381 ps |
| CPU time | 0.58 seconds |
| Started | May 05 01:23:50 PM PDT 24 |
| Finished | May 05 01:23:51 PM PDT 24 |
| Peak memory | 182556 kb |
| Host | smart-35ecba97-dd67-4869-b9f0-52ddc0b5651b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350010454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.350010454 |
| Directory | /workspace/22.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2303240993 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 13350828 ps |
| CPU time | 0.59 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 182588 kb |
| Host | smart-14ef4fa7-3191-4751-84bd-6ffcc8f91e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303240993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2303240993 |
| Directory | /workspace/23.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2706664069 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 43182399 ps |
| CPU time | 0.52 seconds |
| Started | May 05 01:23:55 PM PDT 24 |
| Finished | May 05 01:23:56 PM PDT 24 |
| Peak memory | 182088 kb |
| Host | smart-c57b6d71-a46f-439f-8588-d88f668df968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706664069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2706664069 |
| Directory | /workspace/24.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2859252155 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 80226210 ps |
| CPU time | 0.51 seconds |
| Started | May 05 01:23:52 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 182720 kb |
| Host | smart-20ebeb5c-ddee-4534-867c-9323a74511f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859252155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2859252155 |
| Directory | /workspace/25.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1023376848 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 20407346 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:56 PM PDT 24 |
| Finished | May 05 01:23:57 PM PDT 24 |
| Peak memory | 182048 kb |
| Host | smart-63625e49-1f38-4eee-b675-aee7ba70b885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023376848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1023376848 |
| Directory | /workspace/26.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1322821663 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 14888170 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 182660 kb |
| Host | smart-9a2a5253-610b-47d0-bd36-fd35a090289f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322821663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1322821663 |
| Directory | /workspace/27.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1527063972 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 39411629 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:56 PM PDT 24 |
| Finished | May 05 01:23:57 PM PDT 24 |
| Peak memory | 182580 kb |
| Host | smart-33245c48-969d-4bf3-aaef-910b490732ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527063972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1527063972 |
| Directory | /workspace/28.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.942943882 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 14153250 ps |
| CPU time | 0.52 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 182608 kb |
| Host | smart-1ea3cefa-d0e4-4fb0-8e1d-da99463efd03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942943882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.942943882 |
| Directory | /workspace/29.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2496431661 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 46248799 ps |
| CPU time | 0.61 seconds |
| Started | May 05 01:23:31 PM PDT 24 |
| Finished | May 05 01:23:32 PM PDT 24 |
| Peak memory | 182696 kb |
| Host | smart-d897887e-4f3b-4dfe-a2f7-1b47ff8f2ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496431661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.2496431661 |
| Directory | /workspace/3.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.59179395 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 151531735 ps |
| CPU time | 3.26 seconds |
| Started | May 05 01:23:31 PM PDT 24 |
| Finished | May 05 01:23:35 PM PDT 24 |
| Peak memory | 193928 kb |
| Host | smart-a88cff27-c3b2-432c-865a-25c3cefa16e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59179395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ba sh.59179395 |
| Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2217691971 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 29382980 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:32 PM PDT 24 |
| Finished | May 05 01:23:33 PM PDT 24 |
| Peak memory | 182696 kb |
| Host | smart-777b8126-f4fe-46b4-bf27-6dac0c87ddb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217691971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.2217691971 |
| Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4015270424 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 40459137 ps |
| CPU time | 1.04 seconds |
| Started | May 05 01:23:37 PM PDT 24 |
| Finished | May 05 01:23:38 PM PDT 24 |
| Peak memory | 197260 kb |
| Host | smart-a529417b-20dc-4c8a-87bb-8ef981fb5fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015270424 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4015270424 |
| Directory | /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2992054144 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 93039805 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:28 PM PDT 24 |
| Finished | May 05 01:23:29 PM PDT 24 |
| Peak memory | 182744 kb |
| Host | smart-c6dbe9b5-07ce-4064-81f8-86bbc9f2c3f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992054144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2992054144 |
| Directory | /workspace/3.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.749692876 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 14493011 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:31 PM PDT 24 |
| Finished | May 05 01:23:32 PM PDT 24 |
| Peak memory | 182596 kb |
| Host | smart-1eff7ee0-59e6-4999-bc77-3458869b1a64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749692876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.749692876 |
| Directory | /workspace/3.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4138509548 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 17653041 ps |
| CPU time | 0.62 seconds |
| Started | May 05 01:23:38 PM PDT 24 |
| Finished | May 05 01:23:39 PM PDT 24 |
| Peak memory | 191500 kb |
| Host | smart-12159c24-4d40-470e-91bf-c7c46f3d69f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138509548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti mer_same_csr_outstanding.4138509548 |
| Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1722197938 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 164524471 ps |
| CPU time | 2.18 seconds |
| Started | May 05 01:23:30 PM PDT 24 |
| Finished | May 05 01:23:33 PM PDT 24 |
| Peak memory | 197648 kb |
| Host | smart-f5781052-204b-41d1-8a1c-29516866c619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722197938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1722197938 |
| Directory | /workspace/3.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.56807841 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 45321535 ps |
| CPU time | 0.86 seconds |
| Started | May 05 01:23:31 PM PDT 24 |
| Finished | May 05 01:23:32 PM PDT 24 |
| Peak memory | 193556 kb |
| Host | smart-aba22fd7-324a-47ce-846e-b3f89540c24b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56807841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg _err.56807841 |
| Directory | /workspace/3.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2283441782 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 12244171 ps |
| CPU time | 0.52 seconds |
| Started | May 05 01:23:52 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 182588 kb |
| Host | smart-9087a634-c723-4db2-80c4-2c96ead093b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283441782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2283441782 |
| Directory | /workspace/30.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.265273512 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 18302038 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 182676 kb |
| Host | smart-d027b1f9-35c7-4046-9d51-14702f69facc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265273512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.265273512 |
| Directory | /workspace/31.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2200764503 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 12543592 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:50 PM PDT 24 |
| Finished | May 05 01:23:51 PM PDT 24 |
| Peak memory | 182092 kb |
| Host | smart-422670b8-4b85-4b9c-a6e5-2ac59b422cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200764503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2200764503 |
| Directory | /workspace/32.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4059957223 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 25799433 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:55 PM PDT 24 |
| Finished | May 05 01:23:56 PM PDT 24 |
| Peak memory | 182556 kb |
| Host | smart-53ef2831-74d8-4820-8ba7-98c6fbe7ccba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059957223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.4059957223 |
| Directory | /workspace/33.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2389979803 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 48657933 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 182328 kb |
| Host | smart-b227e93f-1334-4d19-88c5-278bb54b42e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389979803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2389979803 |
| Directory | /workspace/34.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2541971400 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 15082042 ps |
| CPU time | 0.56 seconds |
| Started | May 05 01:23:56 PM PDT 24 |
| Finished | May 05 01:23:57 PM PDT 24 |
| Peak memory | 182532 kb |
| Host | smart-4989d273-c684-4a6e-8099-c3a00c5b1b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541971400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2541971400 |
| Directory | /workspace/35.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2730603660 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 57527611 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:53 PM PDT 24 |
| Finished | May 05 01:23:54 PM PDT 24 |
| Peak memory | 182612 kb |
| Host | smart-be3f5ee8-f7bb-4031-aab6-022aefaa8f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730603660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2730603660 |
| Directory | /workspace/36.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1293382765 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 30962351 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:50 PM PDT 24 |
| Finished | May 05 01:23:51 PM PDT 24 |
| Peak memory | 182636 kb |
| Host | smart-7f32ad5d-10b4-430b-94d3-6031462dccd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293382765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1293382765 |
| Directory | /workspace/37.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.915885140 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 24389295 ps |
| CPU time | 0.56 seconds |
| Started | May 05 01:23:56 PM PDT 24 |
| Finished | May 05 01:23:57 PM PDT 24 |
| Peak memory | 182108 kb |
| Host | smart-5504f181-5fae-44a9-a01b-edae42c29827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915885140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.915885140 |
| Directory | /workspace/38.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.423998606 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 23333777 ps |
| CPU time | 0.58 seconds |
| Started | May 05 01:23:50 PM PDT 24 |
| Finished | May 05 01:23:51 PM PDT 24 |
| Peak memory | 182616 kb |
| Host | smart-8086562c-53d0-4ca2-9065-1b628fed50cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423998606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.423998606 |
| Directory | /workspace/39.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4260009116 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 98871629 ps |
| CPU time | 0.71 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:43 PM PDT 24 |
| Peak memory | 192352 kb |
| Host | smart-755c8d5c-8734-4ba7-a68e-bad0036fc218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260009116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.4260009116 |
| Directory | /workspace/4.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4176593827 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 440547073 ps |
| CPU time | 1.5 seconds |
| Started | May 05 01:23:36 PM PDT 24 |
| Finished | May 05 01:23:38 PM PDT 24 |
| Peak memory | 193520 kb |
| Host | smart-d17acf33-4abc-4081-b51b-eec9c43b42d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176593827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.4176593827 |
| Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1506174359 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 76456310 ps |
| CPU time | 0.6 seconds |
| Started | May 05 01:23:40 PM PDT 24 |
| Finished | May 05 01:23:41 PM PDT 24 |
| Peak memory | 182732 kb |
| Host | smart-728ce26d-068d-40d2-8038-aa69588a8d0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506174359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.1506174359 |
| Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2958770230 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 31386804 ps |
| CPU time | 0.61 seconds |
| Started | May 05 01:23:33 PM PDT 24 |
| Finished | May 05 01:23:34 PM PDT 24 |
| Peak memory | 193644 kb |
| Host | smart-2a81c8c0-1594-4215-99cb-495ca6c2faa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958770230 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2958770230 |
| Directory | /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3499141428 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 12592151 ps |
| CPU time | 0.61 seconds |
| Started | May 05 01:23:43 PM PDT 24 |
| Finished | May 05 01:23:44 PM PDT 24 |
| Peak memory | 182708 kb |
| Host | smart-cbdefb3b-24d2-4312-9022-91cfc24e7ad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499141428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3499141428 |
| Directory | /workspace/4.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1159983308 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 41040273 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:35 PM PDT 24 |
| Finished | May 05 01:23:36 PM PDT 24 |
| Peak memory | 182596 kb |
| Host | smart-8f73a53a-8f76-482b-bc1b-da999b736bc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159983308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1159983308 |
| Directory | /workspace/4.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2355796687 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 156378975 ps |
| CPU time | 0.76 seconds |
| Started | May 05 01:23:35 PM PDT 24 |
| Finished | May 05 01:23:36 PM PDT 24 |
| Peak memory | 191780 kb |
| Host | smart-53aa3400-3e72-4d2a-bb25-91ae7548068d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355796687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.2355796687 |
| Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1761981707 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1747877061 ps |
| CPU time | 2.47 seconds |
| Started | May 05 01:23:39 PM PDT 24 |
| Finished | May 05 01:23:42 PM PDT 24 |
| Peak memory | 197648 kb |
| Host | smart-36568b5a-9927-46f9-874a-a5f5d65d851b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761981707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1761981707 |
| Directory | /workspace/4.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1353863494 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 17108802 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 182608 kb |
| Host | smart-06421f10-df55-4dc1-87d2-c6800e883b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353863494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1353863494 |
| Directory | /workspace/40.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2370873695 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 25594061 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 182564 kb |
| Host | smart-9cfa8138-f747-4684-a528-7e0ba095594d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370873695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2370873695 |
| Directory | /workspace/41.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3196312911 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 11420142 ps |
| CPU time | 0.5 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 182064 kb |
| Host | smart-8d4f0d31-6ee0-453d-849f-998e4f403711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196312911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3196312911 |
| Directory | /workspace/42.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2857289470 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 33300741 ps |
| CPU time | 0.51 seconds |
| Started | May 05 01:23:49 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 182596 kb |
| Host | smart-3c9a58a3-d039-4de9-b100-fdc53b90ae42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857289470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2857289470 |
| Directory | /workspace/43.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3076535731 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 29517024 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:58 PM PDT 24 |
| Finished | May 05 01:24:00 PM PDT 24 |
| Peak memory | 182688 kb |
| Host | smart-d80c9139-4785-47fc-8407-5e7062e19083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076535731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3076535731 |
| Directory | /workspace/44.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3994697938 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 69430495 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 182628 kb |
| Host | smart-1a810c69-aca1-471f-a62f-3af7d7fc8171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994697938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3994697938 |
| Directory | /workspace/45.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3818224547 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 12783724 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:52 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 182580 kb |
| Host | smart-c9266ae7-07da-41ed-8933-3b47fc68b92d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818224547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3818224547 |
| Directory | /workspace/46.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1694830781 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 11476984 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:54 PM PDT 24 |
| Finished | May 05 01:23:55 PM PDT 24 |
| Peak memory | 182656 kb |
| Host | smart-64f88cf7-b1e3-4b1b-8cda-e67cbe3a93b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694830781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1694830781 |
| Directory | /workspace/47.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1346331071 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 149097559 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:51 PM PDT 24 |
| Finished | May 05 01:23:52 PM PDT 24 |
| Peak memory | 182120 kb |
| Host | smart-2620ade8-848c-4e3f-a824-7878447c94f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346331071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1346331071 |
| Directory | /workspace/48.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3655084371 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 18843805 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:52 PM PDT 24 |
| Finished | May 05 01:23:53 PM PDT 24 |
| Peak memory | 182584 kb |
| Host | smart-27504c98-acc3-49ee-849a-bc3122473a23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655084371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3655084371 |
| Directory | /workspace/49.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3400952099 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 50903396 ps |
| CPU time | 1.27 seconds |
| Started | May 05 01:23:39 PM PDT 24 |
| Finished | May 05 01:23:40 PM PDT 24 |
| Peak memory | 197656 kb |
| Host | smart-384a63b9-9da5-4746-84fb-04e95f94f7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400952099 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3400952099 |
| Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.925966782 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 10932470 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:41 PM PDT 24 |
| Finished | May 05 01:23:42 PM PDT 24 |
| Peak memory | 182388 kb |
| Host | smart-a7981136-ab6a-4572-9ce9-49b797bf3ac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925966782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.925966782 |
| Directory | /workspace/5.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1538901251 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 16802729 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:44 PM PDT 24 |
| Peak memory | 182716 kb |
| Host | smart-e1e2b499-7ef0-4281-b8bf-32e0d96c89db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538901251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1538901251 |
| Directory | /workspace/5.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1544499633 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 168675661 ps |
| CPU time | 0.71 seconds |
| Started | May 05 01:23:37 PM PDT 24 |
| Finished | May 05 01:23:38 PM PDT 24 |
| Peak memory | 191676 kb |
| Host | smart-04aea70a-3c2e-493d-8163-04032b97031d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544499633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.1544499633 |
| Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.394312825 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 96753675 ps |
| CPU time | 1.88 seconds |
| Started | May 05 01:23:36 PM PDT 24 |
| Finished | May 05 01:23:39 PM PDT 24 |
| Peak memory | 197624 kb |
| Host | smart-7193eceb-6bfe-4b84-8732-a19d1256e070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394312825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.394312825 |
| Directory | /workspace/5.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.304808274 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 41134763 ps |
| CPU time | 0.77 seconds |
| Started | May 05 01:23:35 PM PDT 24 |
| Finished | May 05 01:23:37 PM PDT 24 |
| Peak memory | 193312 kb |
| Host | smart-a31d36db-004f-41c5-89d0-a31bf22e6c3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304808274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int g_err.304808274 |
| Directory | /workspace/5.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.466720786 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 25337469 ps |
| CPU time | 1.22 seconds |
| Started | May 05 01:23:41 PM PDT 24 |
| Finished | May 05 01:23:43 PM PDT 24 |
| Peak memory | 197668 kb |
| Host | smart-bd81a93d-aff5-4193-a01b-4bb8d6f39f3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466720786 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.466720786 |
| Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3011075500 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 24267686 ps |
| CPU time | 0.59 seconds |
| Started | May 05 01:23:35 PM PDT 24 |
| Finished | May 05 01:23:36 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-a7222b7e-9ec9-48d3-b1b1-e8b3ab5aae24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011075500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3011075500 |
| Directory | /workspace/6.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1962937654 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 154125769 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:36 PM PDT 24 |
| Finished | May 05 01:23:37 PM PDT 24 |
| Peak memory | 182628 kb |
| Host | smart-8faf37c7-9b46-4559-9cae-2efb4b451a54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962937654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1962937654 |
| Directory | /workspace/6.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2535728458 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 70357020 ps |
| CPU time | 0.78 seconds |
| Started | May 05 01:23:44 PM PDT 24 |
| Finished | May 05 01:23:45 PM PDT 24 |
| Peak memory | 191744 kb |
| Host | smart-e27b6f3f-421a-429b-85c9-63cb4cdc1a59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535728458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.2535728458 |
| Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4270851041 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 313141329 ps |
| CPU time | 3.22 seconds |
| Started | May 05 01:23:41 PM PDT 24 |
| Finished | May 05 01:23:45 PM PDT 24 |
| Peak memory | 197660 kb |
| Host | smart-3229cbaa-a578-4f98-aa23-91634f0b0bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270851041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4270851041 |
| Directory | /workspace/6.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.467704210 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 73975133 ps |
| CPU time | 0.81 seconds |
| Started | May 05 01:23:37 PM PDT 24 |
| Finished | May 05 01:23:38 PM PDT 24 |
| Peak memory | 193364 kb |
| Host | smart-41396904-a10f-437f-aa94-66fdf65614a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467704210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int g_err.467704210 |
| Directory | /workspace/6.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2392031299 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 130104792 ps |
| CPU time | 0.69 seconds |
| Started | May 05 01:23:40 PM PDT 24 |
| Finished | May 05 01:23:42 PM PDT 24 |
| Peak memory | 195096 kb |
| Host | smart-809150f3-7a66-4978-a3e1-05b9d2c42971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392031299 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2392031299 |
| Directory | /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2648355242 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 93381430 ps |
| CPU time | 0.57 seconds |
| Started | May 05 01:23:43 PM PDT 24 |
| Finished | May 05 01:23:44 PM PDT 24 |
| Peak memory | 182816 kb |
| Host | smart-eecaa9a6-8771-41fe-b583-e95c3ffe56c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648355242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2648355242 |
| Directory | /workspace/7.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.4156140553 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 33606264 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:35 PM PDT 24 |
| Finished | May 05 01:23:36 PM PDT 24 |
| Peak memory | 182708 kb |
| Host | smart-dc04fb60-0764-4dcb-a440-987411f5339e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156140553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.4156140553 |
| Directory | /workspace/7.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1793390194 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 42744849 ps |
| CPU time | 0.72 seconds |
| Started | May 05 01:23:39 PM PDT 24 |
| Finished | May 05 01:23:40 PM PDT 24 |
| Peak memory | 192092 kb |
| Host | smart-48aa0133-f92b-4fc5-a922-9a8d767681fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793390194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti mer_same_csr_outstanding.1793390194 |
| Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.637059210 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 21842730 ps |
| CPU time | 1.06 seconds |
| Started | May 05 01:23:35 PM PDT 24 |
| Finished | May 05 01:23:37 PM PDT 24 |
| Peak memory | 197340 kb |
| Host | smart-65f248a9-4497-4e15-b735-7183ab7eea40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637059210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.637059210 |
| Directory | /workspace/7.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2070152077 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 524906514 ps |
| CPU time | 1.3 seconds |
| Started | May 05 01:23:37 PM PDT 24 |
| Finished | May 05 01:23:39 PM PDT 24 |
| Peak memory | 183424 kb |
| Host | smart-9ed652bd-15a5-4026-987a-aae43e11aa33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070152077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in tg_err.2070152077 |
| Directory | /workspace/7.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1801549402 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 17574005 ps |
| CPU time | 0.62 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:43 PM PDT 24 |
| Peak memory | 193828 kb |
| Host | smart-af3dedb7-b5cb-4d27-8f99-02f930f56af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801549402 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1801549402 |
| Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.592818680 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 15557375 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:40 PM PDT 24 |
| Finished | May 05 01:23:41 PM PDT 24 |
| Peak memory | 182736 kb |
| Host | smart-e92f7c62-e504-493e-9758-7476b2d41a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592818680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.592818680 |
| Directory | /workspace/8.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2719075404 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 23250298 ps |
| CPU time | 0.54 seconds |
| Started | May 05 01:23:42 PM PDT 24 |
| Finished | May 05 01:23:44 PM PDT 24 |
| Peak memory | 182156 kb |
| Host | smart-a3d8e33a-3479-4717-8eb6-17596d22d65c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719075404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2719075404 |
| Directory | /workspace/8.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4198123442 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 174882344 ps |
| CPU time | 0.66 seconds |
| Started | May 05 01:23:39 PM PDT 24 |
| Finished | May 05 01:23:40 PM PDT 24 |
| Peak memory | 193256 kb |
| Host | smart-f265b947-7573-4242-ade8-f36c4a92bcd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198123442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti mer_same_csr_outstanding.4198123442 |
| Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.187749558 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 127760774 ps |
| CPU time | 2.13 seconds |
| Started | May 05 01:23:43 PM PDT 24 |
| Finished | May 05 01:23:45 PM PDT 24 |
| Peak memory | 197668 kb |
| Host | smart-eda81691-84b2-4e98-b9d8-a711366cf851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187749558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.187749558 |
| Directory | /workspace/8.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2479879371 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 599315190 ps |
| CPU time | 1.19 seconds |
| Started | May 05 01:23:36 PM PDT 24 |
| Finished | May 05 01:23:38 PM PDT 24 |
| Peak memory | 183428 kb |
| Host | smart-ce612c2f-7e4b-40c8-b89a-44a2438b96f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479879371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in tg_err.2479879371 |
| Directory | /workspace/8.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1061634473 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 66078033 ps |
| CPU time | 0.91 seconds |
| Started | May 05 01:23:48 PM PDT 24 |
| Finished | May 05 01:23:50 PM PDT 24 |
| Peak memory | 197020 kb |
| Host | smart-5ebd990c-c22c-4a20-ac22-b123ed73ab12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061634473 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1061634473 |
| Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1405795516 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 19146970 ps |
| CPU time | 0.53 seconds |
| Started | May 05 01:23:44 PM PDT 24 |
| Finished | May 05 01:23:45 PM PDT 24 |
| Peak memory | 182348 kb |
| Host | smart-24881b0b-8e35-4f95-ab4c-a0057ae80944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405795516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1405795516 |
| Directory | /workspace/9.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2415359063 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 17028692 ps |
| CPU time | 0.55 seconds |
| Started | May 05 01:23:46 PM PDT 24 |
| Finished | May 05 01:23:47 PM PDT 24 |
| Peak memory | 182736 kb |
| Host | smart-6a38d8dc-bfe9-4c43-be79-217d27097c06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415359063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2415359063 |
| Directory | /workspace/9.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3106150882 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 17444019 ps |
| CPU time | 0.66 seconds |
| Started | May 05 01:23:40 PM PDT 24 |
| Finished | May 05 01:23:41 PM PDT 24 |
| Peak memory | 193044 kb |
| Host | smart-5ff55518-fe0e-4eb3-9640-ad0057017e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106150882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.3106150882 |
| Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2430895664 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 196846769 ps |
| CPU time | 3.15 seconds |
| Started | May 05 01:23:45 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 197556 kb |
| Host | smart-b713d602-a420-4aba-977f-7e7707db6398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430895664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2430895664 |
| Directory | /workspace/9.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2590193527 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 184528429 ps |
| CPU time | 1.31 seconds |
| Started | May 05 01:23:47 PM PDT 24 |
| Finished | May 05 01:23:49 PM PDT 24 |
| Peak memory | 195476 kb |
| Host | smart-a224160f-21d5-415e-92d6-8a3bd5392c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590193527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.2590193527 |
| Directory | /workspace/9.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_disabled.3521896028 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 58949957422 ps |
| CPU time | 50.67 seconds |
| Started | May 05 01:24:31 PM PDT 24 |
| Finished | May 05 01:25:23 PM PDT 24 |
| Peak memory | 182928 kb |
| Host | smart-31407ec8-0c0e-415f-8d6e-f9a76627f78a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521896028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3521896028 |
| Directory | /workspace/0.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random_reset.736030966 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 24332032392 ps |
| CPU time | 113.58 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:26:24 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-125a0a34-ec4b-49b0-984a-bb005b202e08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736030966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.736030966 |
| Directory | /workspace/0.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all.2250907256 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 143171317302 ps |
| CPU time | 521.77 seconds |
| Started | May 05 01:24:29 PM PDT 24 |
| Finished | May 05 01:33:11 PM PDT 24 |
| Peak memory | 191136 kb |
| Host | smart-072e4f68-adc7-4f44-b00b-2a1e940bba3c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250907256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 2250907256 |
| Directory | /workspace/0.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.565692688 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 351242929538 ps |
| CPU time | 118.39 seconds |
| Started | May 05 01:24:31 PM PDT 24 |
| Finished | May 05 01:26:30 PM PDT 24 |
| Peak memory | 183000 kb |
| Host | smart-674a572d-1b84-40c2-8efb-7ba492b3470f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565692688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rv_timer_cfg_update_on_fly.565692688 |
| Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/1.rv_timer_disabled.702673610 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 131736701548 ps |
| CPU time | 176.87 seconds |
| Started | May 05 01:24:29 PM PDT 24 |
| Finished | May 05 01:27:27 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-964483a3-1b5a-44a5-8aa2-ec4f578a23b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=702673610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.702673610 |
| Directory | /workspace/1.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random.4279555433 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 449486564900 ps |
| CPU time | 267.39 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:28:59 PM PDT 24 |
| Peak memory | 191224 kb |
| Host | smart-4462698b-9b99-47e5-b95b-11aca09fafdf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279555433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.4279555433 |
| Directory | /workspace/1.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random_reset.142664859 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 40999548385 ps |
| CPU time | 55.1 seconds |
| Started | May 05 01:24:27 PM PDT 24 |
| Finished | May 05 01:25:23 PM PDT 24 |
| Peak memory | 182956 kb |
| Host | smart-c5ce8f06-58b5-4999-b97b-61e394d710c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142664859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.142664859 |
| Directory | /workspace/1.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_sec_cm.1234661534 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 260226471 ps |
| CPU time | 0.85 seconds |
| Started | May 05 01:24:33 PM PDT 24 |
| Finished | May 05 01:24:35 PM PDT 24 |
| Peak memory | 213308 kb |
| Host | smart-83878e07-488a-44ce-a4d0-19ffc8f9f3df |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234661534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1234661534 |
| Directory | /workspace/1.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1602589420 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13408453418 ps |
| CPU time | 103.95 seconds |
| Started | May 05 01:24:29 PM PDT 24 |
| Finished | May 05 01:26:13 PM PDT 24 |
| Peak memory | 197644 kb |
| Host | smart-a55ce236-121c-4afa-bd47-a693a3b564a4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602589420 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1602589420 |
| Directory | /workspace/1.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3953007760 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 299086204103 ps |
| CPU time | 323.97 seconds |
| Started | May 05 01:24:39 PM PDT 24 |
| Finished | May 05 01:30:03 PM PDT 24 |
| Peak memory | 183020 kb |
| Host | smart-266d4a06-6c4f-44bd-b55e-cc045b7b2fa6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953007760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.3953007760 |
| Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_disabled.131783669 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 118423508509 ps |
| CPU time | 125.44 seconds |
| Started | May 05 01:24:38 PM PDT 24 |
| Finished | May 05 01:26:44 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-56641acf-4b56-4ebe-ae6d-4f2d354aa1a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131783669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.131783669 |
| Directory | /workspace/10.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random_reset.3299712187 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 27424714091 ps |
| CPU time | 45.23 seconds |
| Started | May 05 01:24:41 PM PDT 24 |
| Finished | May 05 01:25:27 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-15dbda0c-3789-47bc-9b2d-1de964f3282c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299712187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3299712187 |
| Directory | /workspace/10.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all.2005674670 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 33818890867 ps |
| CPU time | 645.56 seconds |
| Started | May 05 01:24:37 PM PDT 24 |
| Finished | May 05 01:35:23 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-92e9b81b-c105-4c52-8c87-b50c1a70c248 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005674670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all .2005674670 |
| Directory | /workspace/10.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/100.rv_timer_random.3012902197 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 49869699671 ps |
| CPU time | 18.18 seconds |
| Started | May 05 01:26:40 PM PDT 24 |
| Finished | May 05 01:26:59 PM PDT 24 |
| Peak memory | 183000 kb |
| Host | smart-518e8c77-1bc6-47c0-bc53-790ed98d6538 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012902197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3012902197 |
| Directory | /workspace/100.rv_timer_random/latest |
| Test location | /workspace/coverage/default/104.rv_timer_random.996918296 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 256253237792 ps |
| CPU time | 1894.95 seconds |
| Started | May 05 01:26:46 PM PDT 24 |
| Finished | May 05 01:58:22 PM PDT 24 |
| Peak memory | 191200 kb |
| Host | smart-c57cb1df-90fc-4285-b051-29124b4d798f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996918296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.996918296 |
| Directory | /workspace/104.rv_timer_random/latest |
| Test location | /workspace/coverage/default/107.rv_timer_random.2577890239 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 93900442699 ps |
| CPU time | 69.2 seconds |
| Started | May 05 01:26:45 PM PDT 24 |
| Finished | May 05 01:27:55 PM PDT 24 |
| Peak memory | 182956 kb |
| Host | smart-6b42b537-2618-440c-a336-a02e78c0c1db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577890239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2577890239 |
| Directory | /workspace/107.rv_timer_random/latest |
| Test location | /workspace/coverage/default/108.rv_timer_random.935512527 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 468266248445 ps |
| CPU time | 214.82 seconds |
| Started | May 05 01:26:52 PM PDT 24 |
| Finished | May 05 01:30:27 PM PDT 24 |
| Peak memory | 191232 kb |
| Host | smart-4dc0814f-7166-4119-9c1f-cc5e880a60bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935512527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.935512527 |
| Directory | /workspace/108.rv_timer_random/latest |
| Test location | /workspace/coverage/default/109.rv_timer_random.700002429 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 167062680651 ps |
| CPU time | 1035.19 seconds |
| Started | May 05 01:26:54 PM PDT 24 |
| Finished | May 05 01:44:09 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-a1e4e3b0-595b-401c-b601-b29f2a6772bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700002429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.700002429 |
| Directory | /workspace/109.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1208937075 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 45877712911 ps |
| CPU time | 39.78 seconds |
| Started | May 05 01:24:38 PM PDT 24 |
| Finished | May 05 01:25:18 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-9b669efa-c381-4a47-aeeb-d242714c7f29 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208937075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.1208937075 |
| Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/11.rv_timer_disabled.931262797 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 44643092405 ps |
| CPU time | 62.43 seconds |
| Started | May 05 01:24:41 PM PDT 24 |
| Finished | May 05 01:25:45 PM PDT 24 |
| Peak memory | 183012 kb |
| Host | smart-0fdd6716-a399-44fd-a9a2-4e698e0a0946 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931262797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.931262797 |
| Directory | /workspace/11.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random.2194261542 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 170081031219 ps |
| CPU time | 535.08 seconds |
| Started | May 05 01:24:36 PM PDT 24 |
| Finished | May 05 01:33:31 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-a783ceab-2b37-44e2-8ce7-4c2fb2b2139a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194261542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2194261542 |
| Directory | /workspace/11.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random_reset.283346443 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4040058682 ps |
| CPU time | 6.99 seconds |
| Started | May 05 01:24:40 PM PDT 24 |
| Finished | May 05 01:24:48 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-a02c284d-92e7-4ee4-8c5c-d819c389b6b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283346443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.283346443 |
| Directory | /workspace/11.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/112.rv_timer_random.2670941114 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 327267524051 ps |
| CPU time | 163.14 seconds |
| Started | May 05 01:26:55 PM PDT 24 |
| Finished | May 05 01:29:38 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-911d6624-edb3-4485-ae91-5bc6c2afe8bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670941114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2670941114 |
| Directory | /workspace/112.rv_timer_random/latest |
| Test location | /workspace/coverage/default/114.rv_timer_random.2079114437 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 93013197072 ps |
| CPU time | 149.01 seconds |
| Started | May 05 01:26:54 PM PDT 24 |
| Finished | May 05 01:29:24 PM PDT 24 |
| Peak memory | 191216 kb |
| Host | smart-1e7fcfad-8d97-429f-86c8-b3fa512e46f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079114437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2079114437 |
| Directory | /workspace/114.rv_timer_random/latest |
| Test location | /workspace/coverage/default/115.rv_timer_random.1129306506 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 59480579052 ps |
| CPU time | 76.35 seconds |
| Started | May 05 01:26:54 PM PDT 24 |
| Finished | May 05 01:28:11 PM PDT 24 |
| Peak memory | 183004 kb |
| Host | smart-64ed51ea-20e8-440c-823e-4c963b2cef42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129306506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1129306506 |
| Directory | /workspace/115.rv_timer_random/latest |
| Test location | /workspace/coverage/default/116.rv_timer_random.3206595937 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 174082560821 ps |
| CPU time | 1144.89 seconds |
| Started | May 05 01:26:56 PM PDT 24 |
| Finished | May 05 01:46:01 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-791e0100-42b5-4c6b-8bf8-e40e73a8e801 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206595937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3206595937 |
| Directory | /workspace/116.rv_timer_random/latest |
| Test location | /workspace/coverage/default/117.rv_timer_random.831209030 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1500684513256 ps |
| CPU time | 1570.81 seconds |
| Started | May 05 01:26:59 PM PDT 24 |
| Finished | May 05 01:53:10 PM PDT 24 |
| Peak memory | 194028 kb |
| Host | smart-6b24882c-6cc5-42a4-ac49-78da611b9c38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831209030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.831209030 |
| Directory | /workspace/117.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_disabled.1401327436 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 173552585216 ps |
| CPU time | 129.68 seconds |
| Started | May 05 01:24:41 PM PDT 24 |
| Finished | May 05 01:26:51 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-bc3e4ffe-4904-49d9-8b12-ca4c28fe0569 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401327436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1401327436 |
| Directory | /workspace/12.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random.482023091 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 270363606643 ps |
| CPU time | 101.18 seconds |
| Started | May 05 01:24:39 PM PDT 24 |
| Finished | May 05 01:26:20 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-5feb7b47-7337-40b8-bda7-ed374cb9f039 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482023091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.482023091 |
| Directory | /workspace/12.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all.2282278308 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 598671992255 ps |
| CPU time | 581.49 seconds |
| Started | May 05 01:24:37 PM PDT 24 |
| Finished | May 05 01:34:19 PM PDT 24 |
| Peak memory | 191208 kb |
| Host | smart-2ddb9f02-b1f6-44b8-85a1-9516a94b7981 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282278308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .2282278308 |
| Directory | /workspace/12.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/120.rv_timer_random.1122437579 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 69950736491 ps |
| CPU time | 729.7 seconds |
| Started | May 05 01:27:03 PM PDT 24 |
| Finished | May 05 01:39:13 PM PDT 24 |
| Peak memory | 192972 kb |
| Host | smart-079e1e47-47a0-48de-9719-6ae7c5dc212e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122437579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1122437579 |
| Directory | /workspace/120.rv_timer_random/latest |
| Test location | /workspace/coverage/default/121.rv_timer_random.1184917910 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 21039220847 ps |
| CPU time | 53.35 seconds |
| Started | May 05 01:27:04 PM PDT 24 |
| Finished | May 05 01:27:57 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-696b9ccb-0a04-44c8-98cf-b0898eaf9297 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184917910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1184917910 |
| Directory | /workspace/121.rv_timer_random/latest |
| Test location | /workspace/coverage/default/122.rv_timer_random.3873916300 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 10610698342 ps |
| CPU time | 29.05 seconds |
| Started | May 05 01:27:03 PM PDT 24 |
| Finished | May 05 01:27:33 PM PDT 24 |
| Peak memory | 191140 kb |
| Host | smart-67d84e8f-dd25-4587-b7bd-261933647a3f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873916300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3873916300 |
| Directory | /workspace/122.rv_timer_random/latest |
| Test location | /workspace/coverage/default/123.rv_timer_random.3744442307 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 183089928185 ps |
| CPU time | 488.24 seconds |
| Started | May 05 01:27:07 PM PDT 24 |
| Finished | May 05 01:35:15 PM PDT 24 |
| Peak memory | 193788 kb |
| Host | smart-1c33ed64-0dcd-4960-8cce-1563333589e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744442307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3744442307 |
| Directory | /workspace/123.rv_timer_random/latest |
| Test location | /workspace/coverage/default/124.rv_timer_random.4249880369 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1733072311615 ps |
| CPU time | 1408.85 seconds |
| Started | May 05 01:27:07 PM PDT 24 |
| Finished | May 05 01:50:37 PM PDT 24 |
| Peak memory | 191412 kb |
| Host | smart-85babf69-70dd-4036-bc1a-2f24710c1259 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249880369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.4249880369 |
| Directory | /workspace/124.rv_timer_random/latest |
| Test location | /workspace/coverage/default/125.rv_timer_random.3553812860 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1603643399039 ps |
| CPU time | 402.13 seconds |
| Started | May 05 01:27:08 PM PDT 24 |
| Finished | May 05 01:33:50 PM PDT 24 |
| Peak memory | 191216 kb |
| Host | smart-56dba788-a52e-412c-99a5-57bf2b32e2b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553812860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3553812860 |
| Directory | /workspace/125.rv_timer_random/latest |
| Test location | /workspace/coverage/default/127.rv_timer_random.3950677233 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 423498124424 ps |
| CPU time | 190.52 seconds |
| Started | May 05 01:27:09 PM PDT 24 |
| Finished | May 05 01:30:20 PM PDT 24 |
| Peak memory | 191216 kb |
| Host | smart-96cf604b-522c-4834-a206-33a1aeadbdfc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950677233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3950677233 |
| Directory | /workspace/127.rv_timer_random/latest |
| Test location | /workspace/coverage/default/128.rv_timer_random.389896571 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 598740406521 ps |
| CPU time | 230.59 seconds |
| Started | May 05 01:27:09 PM PDT 24 |
| Finished | May 05 01:31:00 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-4c5988d1-f78b-4341-b372-a84e6134ab6a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389896571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.389896571 |
| Directory | /workspace/128.rv_timer_random/latest |
| Test location | /workspace/coverage/default/129.rv_timer_random.2839693887 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 440262179016 ps |
| CPU time | 499.93 seconds |
| Started | May 05 01:27:12 PM PDT 24 |
| Finished | May 05 01:35:32 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-66b2e5f2-986e-4954-ab89-49ce78037e69 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839693887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2839693887 |
| Directory | /workspace/129.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.189487130 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 133805433227 ps |
| CPU time | 113.97 seconds |
| Started | May 05 01:24:45 PM PDT 24 |
| Finished | May 05 01:26:40 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-05170a15-ed1b-4a52-b1f3-294932d6d16b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189487130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.rv_timer_cfg_update_on_fly.189487130 |
| Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/13.rv_timer_disabled.1848625076 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 192742780047 ps |
| CPU time | 143.56 seconds |
| Started | May 05 01:24:36 PM PDT 24 |
| Finished | May 05 01:27:00 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-2a55c53a-dafd-472c-bd5a-493c70d65957 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848625076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1848625076 |
| Directory | /workspace/13.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random.854730287 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 592868424269 ps |
| CPU time | 687.97 seconds |
| Started | May 05 01:24:37 PM PDT 24 |
| Finished | May 05 01:36:06 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-98176c71-e652-4c44-9bff-5dc9c0f2a604 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854730287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.854730287 |
| Directory | /workspace/13.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random_reset.2192935645 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 611353112 ps |
| CPU time | 1.34 seconds |
| Started | May 05 01:24:41 PM PDT 24 |
| Finished | May 05 01:24:43 PM PDT 24 |
| Peak memory | 182788 kb |
| Host | smart-847015ae-0251-4760-9fde-5e70e6d63488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2192935645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2192935645 |
| Directory | /workspace/13.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/130.rv_timer_random.4089794828 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 515819361449 ps |
| CPU time | 146.28 seconds |
| Started | May 05 01:27:09 PM PDT 24 |
| Finished | May 05 01:29:36 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-853497b3-0659-43d9-bf16-d1dd8f6cea4e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089794828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.4089794828 |
| Directory | /workspace/130.rv_timer_random/latest |
| Test location | /workspace/coverage/default/132.rv_timer_random.3892562569 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 66213682076 ps |
| CPU time | 107.75 seconds |
| Started | May 05 01:27:16 PM PDT 24 |
| Finished | May 05 01:29:04 PM PDT 24 |
| Peak memory | 191232 kb |
| Host | smart-adf95ecf-722e-4452-bc85-9e13d7337961 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892562569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3892562569 |
| Directory | /workspace/132.rv_timer_random/latest |
| Test location | /workspace/coverage/default/133.rv_timer_random.2792307817 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 714769286902 ps |
| CPU time | 1262.06 seconds |
| Started | May 05 01:27:13 PM PDT 24 |
| Finished | May 05 01:48:15 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-a4330d73-9608-4a85-b7a1-9f902c2ae7b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792307817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2792307817 |
| Directory | /workspace/133.rv_timer_random/latest |
| Test location | /workspace/coverage/default/134.rv_timer_random.2841377561 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 176591924819 ps |
| CPU time | 467.36 seconds |
| Started | May 05 01:27:16 PM PDT 24 |
| Finished | May 05 01:35:04 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-085bd2a9-7b3a-46c1-a584-74b5b9a79759 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841377561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2841377561 |
| Directory | /workspace/134.rv_timer_random/latest |
| Test location | /workspace/coverage/default/135.rv_timer_random.3547689829 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 192469808996 ps |
| CPU time | 305.97 seconds |
| Started | May 05 01:27:16 PM PDT 24 |
| Finished | May 05 01:32:23 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-2928b42f-6074-4748-aa45-2bcd785ebce8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547689829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3547689829 |
| Directory | /workspace/135.rv_timer_random/latest |
| Test location | /workspace/coverage/default/137.rv_timer_random.3092862774 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 96746265997 ps |
| CPU time | 88 seconds |
| Started | May 05 01:27:16 PM PDT 24 |
| Finished | May 05 01:28:44 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-7858b9b8-a435-48c7-9879-8f1e260bed04 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092862774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3092862774 |
| Directory | /workspace/137.rv_timer_random/latest |
| Test location | /workspace/coverage/default/138.rv_timer_random.3814139814 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 33650716029 ps |
| CPU time | 49.5 seconds |
| Started | May 05 01:27:13 PM PDT 24 |
| Finished | May 05 01:28:03 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-078d36a8-2e2a-470d-a343-db230e2a74a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814139814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3814139814 |
| Directory | /workspace/138.rv_timer_random/latest |
| Test location | /workspace/coverage/default/139.rv_timer_random.2928532785 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 176919053987 ps |
| CPU time | 111.5 seconds |
| Started | May 05 01:27:18 PM PDT 24 |
| Finished | May 05 01:29:10 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-e4362dd3-5bb8-4797-b092-e2aa968f838c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928532785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2928532785 |
| Directory | /workspace/139.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3666834621 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 193739094633 ps |
| CPU time | 318.33 seconds |
| Started | May 05 01:24:41 PM PDT 24 |
| Finished | May 05 01:30:00 PM PDT 24 |
| Peak memory | 183024 kb |
| Host | smart-923c2a7c-1a7f-428d-84e5-a89e04e08452 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666834621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.3666834621 |
| Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/14.rv_timer_disabled.1517447745 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 334046489996 ps |
| CPU time | 271.96 seconds |
| Started | May 05 01:24:41 PM PDT 24 |
| Finished | May 05 01:29:13 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-712aeede-3e7e-4705-b800-7009d3fe3a1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517447745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1517447745 |
| Directory | /workspace/14.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random.1147787915 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 100632646837 ps |
| CPU time | 106.64 seconds |
| Started | May 05 01:24:42 PM PDT 24 |
| Finished | May 05 01:26:30 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-8e378309-feb1-4177-8c31-7f4d69dd7129 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147787915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1147787915 |
| Directory | /workspace/14.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random_reset.3411537010 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 213694173227 ps |
| CPU time | 180.82 seconds |
| Started | May 05 01:24:45 PM PDT 24 |
| Finished | May 05 01:27:47 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-38a9630b-492d-48b6-b983-c15591024728 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411537010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3411537010 |
| Directory | /workspace/14.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all.739279882 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 291865664014 ps |
| CPU time | 1184.48 seconds |
| Started | May 05 01:24:41 PM PDT 24 |
| Finished | May 05 01:44:26 PM PDT 24 |
| Peak memory | 196148 kb |
| Host | smart-2335251a-151c-4c66-ade4-de42fd918d6b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739279882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all. 739279882 |
| Directory | /workspace/14.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/140.rv_timer_random.3284822926 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 55849233388 ps |
| CPU time | 82.67 seconds |
| Started | May 05 01:27:22 PM PDT 24 |
| Finished | May 05 01:28:45 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-aab47e8e-f091-4815-afc9-d4f943785422 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284822926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3284822926 |
| Directory | /workspace/140.rv_timer_random/latest |
| Test location | /workspace/coverage/default/141.rv_timer_random.2296875123 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 340434241577 ps |
| CPU time | 569.51 seconds |
| Started | May 05 01:27:20 PM PDT 24 |
| Finished | May 05 01:36:50 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-66c748a4-9a90-4d5e-8919-6b6af3c37bf0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296875123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2296875123 |
| Directory | /workspace/141.rv_timer_random/latest |
| Test location | /workspace/coverage/default/142.rv_timer_random.1545992948 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 174954607744 ps |
| CPU time | 1799.74 seconds |
| Started | May 05 01:27:18 PM PDT 24 |
| Finished | May 05 01:57:18 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-4520c5cf-cd99-41c4-b036-e0d98bfea660 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545992948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1545992948 |
| Directory | /workspace/142.rv_timer_random/latest |
| Test location | /workspace/coverage/default/147.rv_timer_random.1997418933 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 42039098925 ps |
| CPU time | 246.93 seconds |
| Started | May 05 01:27:24 PM PDT 24 |
| Finished | May 05 01:31:32 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-af9a5cbc-23ac-4df3-9175-0dfa1eadc5f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997418933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1997418933 |
| Directory | /workspace/147.rv_timer_random/latest |
| Test location | /workspace/coverage/default/148.rv_timer_random.2863576244 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 89751471217 ps |
| CPU time | 168 seconds |
| Started | May 05 01:27:24 PM PDT 24 |
| Finished | May 05 01:30:12 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-573e46c1-13a2-498b-83de-87dc337d8ab5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863576244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2863576244 |
| Directory | /workspace/148.rv_timer_random/latest |
| Test location | /workspace/coverage/default/149.rv_timer_random.1805839833 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 18754253134 ps |
| CPU time | 36.76 seconds |
| Started | May 05 01:27:24 PM PDT 24 |
| Finished | May 05 01:28:01 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-80d8c526-d9b1-4bdc-b387-e0b981a0e1ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805839833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1805839833 |
| Directory | /workspace/149.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1581159033 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 306533848154 ps |
| CPU time | 525.67 seconds |
| Started | May 05 01:24:49 PM PDT 24 |
| Finished | May 05 01:33:35 PM PDT 24 |
| Peak memory | 182452 kb |
| Host | smart-e3e4f601-9919-46c2-b445-35d443059ece |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581159033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1581159033 |
| Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/15.rv_timer_disabled.2758546553 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 158227229033 ps |
| CPU time | 236.01 seconds |
| Started | May 05 01:24:42 PM PDT 24 |
| Finished | May 05 01:28:39 PM PDT 24 |
| Peak memory | 182936 kb |
| Host | smart-95f06c88-dd17-4f21-a98c-78f3bdc293da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758546553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2758546553 |
| Directory | /workspace/15.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random.929604894 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 230596470066 ps |
| CPU time | 574.3 seconds |
| Started | May 05 01:24:42 PM PDT 24 |
| Finished | May 05 01:34:17 PM PDT 24 |
| Peak memory | 191412 kb |
| Host | smart-68e29fa2-5d72-469b-9c5e-67b4f172a49e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929604894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.929604894 |
| Directory | /workspace/15.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random_reset.1069292446 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 111651073086 ps |
| CPU time | 52.3 seconds |
| Started | May 05 01:24:40 PM PDT 24 |
| Finished | May 05 01:25:33 PM PDT 24 |
| Peak memory | 194976 kb |
| Host | smart-593b280f-c86a-4137-8e13-8e4b035dec5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069292446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1069292446 |
| Directory | /workspace/15.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all.4228372859 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2406128450650 ps |
| CPU time | 452.83 seconds |
| Started | May 05 01:24:49 PM PDT 24 |
| Finished | May 05 01:32:22 PM PDT 24 |
| Peak memory | 191100 kb |
| Host | smart-68307aaf-539d-4d38-9463-ae27f52d7e82 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228372859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .4228372859 |
| Directory | /workspace/15.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2732610427 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 26964026243 ps |
| CPU time | 262.84 seconds |
| Started | May 05 01:24:45 PM PDT 24 |
| Finished | May 05 01:29:09 PM PDT 24 |
| Peak memory | 205860 kb |
| Host | smart-bdee6a66-daec-4037-8446-0f548c98dee2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732610427 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.2732610427 |
| Directory | /workspace/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/151.rv_timer_random.679846835 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 226899085394 ps |
| CPU time | 230.51 seconds |
| Started | May 05 01:27:28 PM PDT 24 |
| Finished | May 05 01:31:19 PM PDT 24 |
| Peak memory | 191140 kb |
| Host | smart-13734711-1dcd-4016-b205-1f77b024c12c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679846835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.679846835 |
| Directory | /workspace/151.rv_timer_random/latest |
| Test location | /workspace/coverage/default/152.rv_timer_random.3681303025 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 231688918713 ps |
| CPU time | 157.16 seconds |
| Started | May 05 01:27:28 PM PDT 24 |
| Finished | May 05 01:30:05 PM PDT 24 |
| Peak memory | 193504 kb |
| Host | smart-9f092243-3d68-441d-96e3-c478530f675d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681303025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3681303025 |
| Directory | /workspace/152.rv_timer_random/latest |
| Test location | /workspace/coverage/default/153.rv_timer_random.1173083062 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 620109618846 ps |
| CPU time | 302.38 seconds |
| Started | May 05 01:27:28 PM PDT 24 |
| Finished | May 05 01:32:31 PM PDT 24 |
| Peak memory | 191092 kb |
| Host | smart-74f6c638-695c-4f6b-b3cd-30544593e402 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173083062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1173083062 |
| Directory | /workspace/153.rv_timer_random/latest |
| Test location | /workspace/coverage/default/155.rv_timer_random.2317625633 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 128060676929 ps |
| CPU time | 92.45 seconds |
| Started | May 05 01:27:33 PM PDT 24 |
| Finished | May 05 01:29:06 PM PDT 24 |
| Peak memory | 194600 kb |
| Host | smart-1ab7bf7f-5d5a-4f3d-a4da-6517a5caa1c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317625633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2317625633 |
| Directory | /workspace/155.rv_timer_random/latest |
| Test location | /workspace/coverage/default/157.rv_timer_random.3145995823 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 322101911241 ps |
| CPU time | 1639.44 seconds |
| Started | May 05 01:27:34 PM PDT 24 |
| Finished | May 05 01:54:54 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-be846bac-7ae9-4025-a3c2-f965b99d10a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145995823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3145995823 |
| Directory | /workspace/157.rv_timer_random/latest |
| Test location | /workspace/coverage/default/158.rv_timer_random.3699480049 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 164699335003 ps |
| CPU time | 81.64 seconds |
| Started | May 05 01:27:34 PM PDT 24 |
| Finished | May 05 01:28:56 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-fafecdbf-774a-4bde-83a7-5829cd2419ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699480049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3699480049 |
| Directory | /workspace/158.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_disabled.1587121217 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 97336008896 ps |
| CPU time | 42.49 seconds |
| Started | May 05 01:24:50 PM PDT 24 |
| Finished | May 05 01:25:33 PM PDT 24 |
| Peak memory | 182916 kb |
| Host | smart-734b6546-133f-42d4-b4b5-d2ac9a8ec5fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587121217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1587121217 |
| Directory | /workspace/16.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random.151439256 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 51785276094 ps |
| CPU time | 77.65 seconds |
| Started | May 05 01:24:44 PM PDT 24 |
| Finished | May 05 01:26:02 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-ddb08cbf-5398-4466-8de7-3e47f5809fa8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151439256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.151439256 |
| Directory | /workspace/16.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random_reset.1505621431 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 27676312888 ps |
| CPU time | 42.62 seconds |
| Started | May 05 01:24:43 PM PDT 24 |
| Finished | May 05 01:25:26 PM PDT 24 |
| Peak memory | 182848 kb |
| Host | smart-990424bb-e6a4-4660-9c37-16b7e9c16761 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505621431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1505621431 |
| Directory | /workspace/16.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.213337772 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13562074807 ps |
| CPU time | 219.44 seconds |
| Started | May 05 01:24:46 PM PDT 24 |
| Finished | May 05 01:28:26 PM PDT 24 |
| Peak memory | 197628 kb |
| Host | smart-88bdb9a3-5654-46eb-aa91-27432abe3c77 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213337772 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.213337772 |
| Directory | /workspace/16.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/160.rv_timer_random.809275431 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 272967303725 ps |
| CPU time | 2222.19 seconds |
| Started | May 05 01:27:35 PM PDT 24 |
| Finished | May 05 02:04:37 PM PDT 24 |
| Peak memory | 191132 kb |
| Host | smart-ad56ded8-7867-4e34-b188-91447b21ccd1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809275431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.809275431 |
| Directory | /workspace/160.rv_timer_random/latest |
| Test location | /workspace/coverage/default/161.rv_timer_random.3480750553 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 96396779739 ps |
| CPU time | 149.03 seconds |
| Started | May 05 01:27:34 PM PDT 24 |
| Finished | May 05 01:30:03 PM PDT 24 |
| Peak memory | 194788 kb |
| Host | smart-793954ea-0e86-46cf-99d6-a61daedbc8ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480750553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3480750553 |
| Directory | /workspace/161.rv_timer_random/latest |
| Test location | /workspace/coverage/default/162.rv_timer_random.4241722208 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 221798505523 ps |
| CPU time | 543.43 seconds |
| Started | May 05 01:27:36 PM PDT 24 |
| Finished | May 05 01:36:40 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-1bb3ef6d-1a8d-4ceb-be71-8bd5ca0e97e8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241722208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4241722208 |
| Directory | /workspace/162.rv_timer_random/latest |
| Test location | /workspace/coverage/default/163.rv_timer_random.923348891 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 819606612838 ps |
| CPU time | 892.38 seconds |
| Started | May 05 01:27:39 PM PDT 24 |
| Finished | May 05 01:42:31 PM PDT 24 |
| Peak memory | 191204 kb |
| Host | smart-becad0ca-3a26-4e03-b0c3-d6c5a9e844d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923348891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.923348891 |
| Directory | /workspace/163.rv_timer_random/latest |
| Test location | /workspace/coverage/default/164.rv_timer_random.3676219216 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 113985081218 ps |
| CPU time | 142.44 seconds |
| Started | May 05 01:27:40 PM PDT 24 |
| Finished | May 05 01:30:03 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-aa219240-8a44-406b-9178-c273e545e49e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676219216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3676219216 |
| Directory | /workspace/164.rv_timer_random/latest |
| Test location | /workspace/coverage/default/167.rv_timer_random.734301402 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 166111883011 ps |
| CPU time | 444.5 seconds |
| Started | May 05 01:27:41 PM PDT 24 |
| Finished | May 05 01:35:06 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-68fff437-252b-4f5b-9cde-1591177b7ed8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734301402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.734301402 |
| Directory | /workspace/167.rv_timer_random/latest |
| Test location | /workspace/coverage/default/168.rv_timer_random.3480466215 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 270308900980 ps |
| CPU time | 155.27 seconds |
| Started | May 05 01:27:42 PM PDT 24 |
| Finished | May 05 01:30:18 PM PDT 24 |
| Peak memory | 191200 kb |
| Host | smart-4885c1b4-4eb6-4b2d-9a25-14a1251915c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480466215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3480466215 |
| Directory | /workspace/168.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2910761797 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1707912090419 ps |
| CPU time | 919.41 seconds |
| Started | May 05 01:24:45 PM PDT 24 |
| Finished | May 05 01:40:06 PM PDT 24 |
| Peak memory | 182972 kb |
| Host | smart-61e735b4-e66d-4c03-b26c-f25a66801a58 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910761797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.2910761797 |
| Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/17.rv_timer_disabled.1345944956 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 307546368699 ps |
| CPU time | 137.56 seconds |
| Started | May 05 01:24:42 PM PDT 24 |
| Finished | May 05 01:27:00 PM PDT 24 |
| Peak memory | 183008 kb |
| Host | smart-c05ba044-5755-4a08-9716-ac6829489d45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345944956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1345944956 |
| Directory | /workspace/17.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random.4283682270 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3509328309 ps |
| CPU time | 6.06 seconds |
| Started | May 05 01:24:42 PM PDT 24 |
| Finished | May 05 01:24:49 PM PDT 24 |
| Peak memory | 182848 kb |
| Host | smart-f138b9d3-0d61-40c9-8098-d60eba227d69 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283682270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4283682270 |
| Directory | /workspace/17.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all.721490127 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 212410879474 ps |
| CPU time | 420.3 seconds |
| Started | May 05 01:24:47 PM PDT 24 |
| Finished | May 05 01:31:48 PM PDT 24 |
| Peak memory | 194968 kb |
| Host | smart-547d4997-a7d4-4a8e-933a-bc59d46c52db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721490127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all. 721490127 |
| Directory | /workspace/17.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/170.rv_timer_random.2215903584 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 43373490474 ps |
| CPU time | 80.1 seconds |
| Started | May 05 01:27:48 PM PDT 24 |
| Finished | May 05 01:29:09 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-24a65036-20f3-4e16-8aa8-a4e164443fe1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215903584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2215903584 |
| Directory | /workspace/170.rv_timer_random/latest |
| Test location | /workspace/coverage/default/171.rv_timer_random.4285723949 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 211444837872 ps |
| CPU time | 1312.8 seconds |
| Started | May 05 01:27:47 PM PDT 24 |
| Finished | May 05 01:49:40 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-25cfb6eb-68b3-4d9e-8c1c-bb5e09ac107d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285723949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4285723949 |
| Directory | /workspace/171.rv_timer_random/latest |
| Test location | /workspace/coverage/default/172.rv_timer_random.532895358 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 34219793189 ps |
| CPU time | 50.36 seconds |
| Started | May 05 01:27:46 PM PDT 24 |
| Finished | May 05 01:28:37 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-39bb340e-8d99-4dc7-a47c-18c13cbcf494 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532895358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.532895358 |
| Directory | /workspace/172.rv_timer_random/latest |
| Test location | /workspace/coverage/default/174.rv_timer_random.2236305418 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 90940966900 ps |
| CPU time | 456.05 seconds |
| Started | May 05 01:27:48 PM PDT 24 |
| Finished | May 05 01:35:25 PM PDT 24 |
| Peak memory | 191088 kb |
| Host | smart-a5c1ca62-ad57-4ec7-87e7-268213d4c7e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236305418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2236305418 |
| Directory | /workspace/174.rv_timer_random/latest |
| Test location | /workspace/coverage/default/175.rv_timer_random.1414009594 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 160878949740 ps |
| CPU time | 245.57 seconds |
| Started | May 05 01:27:52 PM PDT 24 |
| Finished | May 05 01:31:58 PM PDT 24 |
| Peak memory | 191404 kb |
| Host | smart-2e84cd95-e729-4dde-854d-6a72e2b0ca03 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414009594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1414009594 |
| Directory | /workspace/175.rv_timer_random/latest |
| Test location | /workspace/coverage/default/178.rv_timer_random.1941883087 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 41433388177 ps |
| CPU time | 34.09 seconds |
| Started | May 05 01:27:53 PM PDT 24 |
| Finished | May 05 01:28:27 PM PDT 24 |
| Peak memory | 191204 kb |
| Host | smart-e18a01e0-31a3-46fe-9659-43fbe351f968 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941883087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1941883087 |
| Directory | /workspace/178.rv_timer_random/latest |
| Test location | /workspace/coverage/default/179.rv_timer_random.1294761148 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 102853397069 ps |
| CPU time | 50.48 seconds |
| Started | May 05 01:27:58 PM PDT 24 |
| Finished | May 05 01:28:49 PM PDT 24 |
| Peak memory | 182892 kb |
| Host | smart-7ced9011-4490-49f9-b4d6-3b1be430f66d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294761148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1294761148 |
| Directory | /workspace/179.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.17314914 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3794426691 ps |
| CPU time | 6.76 seconds |
| Started | May 05 01:24:46 PM PDT 24 |
| Finished | May 05 01:24:54 PM PDT 24 |
| Peak memory | 183000 kb |
| Host | smart-30385f96-785a-458f-ae2d-1b23c6c28096 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17314914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .rv_timer_cfg_update_on_fly.17314914 |
| Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/18.rv_timer_disabled.2302199473 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 176058908242 ps |
| CPU time | 196.22 seconds |
| Started | May 05 01:24:48 PM PDT 24 |
| Finished | May 05 01:28:04 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-b5591b73-5a98-4f54-b279-47b707932064 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302199473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2302199473 |
| Directory | /workspace/18.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random.711971939 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 124639565483 ps |
| CPU time | 393.29 seconds |
| Started | May 05 01:24:46 PM PDT 24 |
| Finished | May 05 01:31:20 PM PDT 24 |
| Peak memory | 194796 kb |
| Host | smart-fe8692d5-6eb3-492e-898b-b4164bc2380c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711971939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.711971939 |
| Directory | /workspace/18.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random_reset.2072373536 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 28788881990 ps |
| CPU time | 170.25 seconds |
| Started | May 05 01:24:47 PM PDT 24 |
| Finished | May 05 01:27:38 PM PDT 24 |
| Peak memory | 194116 kb |
| Host | smart-5fe3d1db-4993-4c02-b186-e899b3d94b29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072373536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2072373536 |
| Directory | /workspace/18.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2881482008 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 61155046334 ps |
| CPU time | 438.72 seconds |
| Started | May 05 01:24:47 PM PDT 24 |
| Finished | May 05 01:32:06 PM PDT 24 |
| Peak memory | 207352 kb |
| Host | smart-712f1c9b-3f2d-4129-b7d2-07c4a72a8abb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881482008 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2881482008 |
| Directory | /workspace/18.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/180.rv_timer_random.1001339112 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 8083545813 ps |
| CPU time | 11.98 seconds |
| Started | May 05 01:28:05 PM PDT 24 |
| Finished | May 05 01:28:17 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-2c6e1ca2-387a-43b4-b918-5fdc864fc261 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001339112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1001339112 |
| Directory | /workspace/180.rv_timer_random/latest |
| Test location | /workspace/coverage/default/181.rv_timer_random.3060852185 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 16365108357 ps |
| CPU time | 26.62 seconds |
| Started | May 05 01:27:57 PM PDT 24 |
| Finished | May 05 01:28:24 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-9ac77eba-3a67-4915-8d72-f4b1fcdba8a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060852185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3060852185 |
| Directory | /workspace/181.rv_timer_random/latest |
| Test location | /workspace/coverage/default/184.rv_timer_random.2789157511 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 15981516895 ps |
| CPU time | 78.6 seconds |
| Started | May 05 01:28:05 PM PDT 24 |
| Finished | May 05 01:29:24 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-83a9e013-60a4-43a5-8927-d70c6193496f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789157511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2789157511 |
| Directory | /workspace/184.rv_timer_random/latest |
| Test location | /workspace/coverage/default/185.rv_timer_random.1897748088 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 100737001212 ps |
| CPU time | 181.24 seconds |
| Started | May 05 01:28:05 PM PDT 24 |
| Finished | May 05 01:31:07 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-9fadea26-87d4-47c0-b5d4-5e3ff52e1320 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897748088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1897748088 |
| Directory | /workspace/185.rv_timer_random/latest |
| Test location | /workspace/coverage/default/187.rv_timer_random.3480929241 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 153391487075 ps |
| CPU time | 282.69 seconds |
| Started | May 05 01:28:04 PM PDT 24 |
| Finished | May 05 01:32:47 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-ed638b35-bd38-4fa0-abf9-ec08a578cb30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480929241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3480929241 |
| Directory | /workspace/187.rv_timer_random/latest |
| Test location | /workspace/coverage/default/188.rv_timer_random.2510597692 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 56582835573 ps |
| CPU time | 87.9 seconds |
| Started | May 05 01:28:04 PM PDT 24 |
| Finished | May 05 01:29:32 PM PDT 24 |
| Peak memory | 191092 kb |
| Host | smart-6f47c386-cfb8-4315-ba0b-f0cf06520c79 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510597692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2510597692 |
| Directory | /workspace/188.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1727059627 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 22239655055 ps |
| CPU time | 15.44 seconds |
| Started | May 05 01:24:47 PM PDT 24 |
| Finished | May 05 01:25:03 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-4b701c88-c1e5-4a4c-919c-9902554d463d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727059627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.1727059627 |
| Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/19.rv_timer_disabled.2195637559 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 102486071632 ps |
| CPU time | 158.28 seconds |
| Started | May 05 01:24:48 PM PDT 24 |
| Finished | May 05 01:27:27 PM PDT 24 |
| Peak memory | 182972 kb |
| Host | smart-87399332-358e-449c-b89d-af8d38be2dd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195637559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2195637559 |
| Directory | /workspace/19.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random.3107325197 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 38064554987 ps |
| CPU time | 229.08 seconds |
| Started | May 05 01:24:46 PM PDT 24 |
| Finished | May 05 01:28:36 PM PDT 24 |
| Peak memory | 191208 kb |
| Host | smart-514a8eae-6951-4317-99d6-519c1e915569 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107325197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3107325197 |
| Directory | /workspace/19.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random_reset.1079167503 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 65738601028 ps |
| CPU time | 422.19 seconds |
| Started | May 05 01:24:45 PM PDT 24 |
| Finished | May 05 01:31:49 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-dc7c92ea-6670-437a-8401-e1d5a5c8550c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079167503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1079167503 |
| Directory | /workspace/19.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/190.rv_timer_random.1092267969 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 113903122234 ps |
| CPU time | 186.22 seconds |
| Started | May 05 01:28:04 PM PDT 24 |
| Finished | May 05 01:31:10 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-f2aafa89-668c-4914-ba92-dfce89969d05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092267969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1092267969 |
| Directory | /workspace/190.rv_timer_random/latest |
| Test location | /workspace/coverage/default/191.rv_timer_random.524158536 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 227280016106 ps |
| CPU time | 608.42 seconds |
| Started | May 05 01:28:03 PM PDT 24 |
| Finished | May 05 01:38:12 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-aa5913ca-ff2d-424b-9776-ce96ff74747d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524158536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.524158536 |
| Directory | /workspace/191.rv_timer_random/latest |
| Test location | /workspace/coverage/default/192.rv_timer_random.1915592012 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 180782428017 ps |
| CPU time | 294.19 seconds |
| Started | May 05 01:28:01 PM PDT 24 |
| Finished | May 05 01:32:56 PM PDT 24 |
| Peak memory | 194632 kb |
| Host | smart-ea6281b7-d45e-4a50-89ab-cd22b69e2611 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915592012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1915592012 |
| Directory | /workspace/192.rv_timer_random/latest |
| Test location | /workspace/coverage/default/193.rv_timer_random.2030226733 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 81822968276 ps |
| CPU time | 134.8 seconds |
| Started | May 05 01:28:12 PM PDT 24 |
| Finished | May 05 01:30:27 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-c0e5b6f3-fc05-4135-899f-274b95363282 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030226733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2030226733 |
| Directory | /workspace/193.rv_timer_random/latest |
| Test location | /workspace/coverage/default/194.rv_timer_random.501099666 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 468729099935 ps |
| CPU time | 357.85 seconds |
| Started | May 05 01:28:12 PM PDT 24 |
| Finished | May 05 01:34:10 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-05ec4b36-c593-4571-a6a5-61b789891257 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501099666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.501099666 |
| Directory | /workspace/194.rv_timer_random/latest |
| Test location | /workspace/coverage/default/196.rv_timer_random.577412629 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 470898981775 ps |
| CPU time | 427.51 seconds |
| Started | May 05 01:28:12 PM PDT 24 |
| Finished | May 05 01:35:20 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-59e509b0-bd8e-44df-809e-3817c2262cb4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577412629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.577412629 |
| Directory | /workspace/196.rv_timer_random/latest |
| Test location | /workspace/coverage/default/197.rv_timer_random.3970841137 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 45340603023 ps |
| CPU time | 81.03 seconds |
| Started | May 05 01:28:13 PM PDT 24 |
| Finished | May 05 01:29:34 PM PDT 24 |
| Peak memory | 182952 kb |
| Host | smart-cde42cf4-5a32-430f-b97f-0196b083fe55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970841137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3970841137 |
| Directory | /workspace/197.rv_timer_random/latest |
| Test location | /workspace/coverage/default/198.rv_timer_random.2718564360 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 165171351243 ps |
| CPU time | 34.39 seconds |
| Started | May 05 01:28:12 PM PDT 24 |
| Finished | May 05 01:28:47 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-be2931f9-cfe6-4653-abe0-bf3928461d0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718564360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2718564360 |
| Directory | /workspace/198.rv_timer_random/latest |
| Test location | /workspace/coverage/default/199.rv_timer_random.2401787961 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 137256811707 ps |
| CPU time | 292.53 seconds |
| Started | May 05 01:28:11 PM PDT 24 |
| Finished | May 05 01:33:04 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-1087abcd-07c2-413d-a7d8-d20d1bc180e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401787961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2401787961 |
| Directory | /workspace/199.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.227558264 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 112212481874 ps |
| CPU time | 193.18 seconds |
| Started | May 05 01:24:28 PM PDT 24 |
| Finished | May 05 01:27:42 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-417d6b2f-afb8-4631-9498-378370f8c0c5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227558264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rv_timer_cfg_update_on_fly.227558264 |
| Directory | /workspace/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/2.rv_timer_disabled.3250665727 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 116513219346 ps |
| CPU time | 154.7 seconds |
| Started | May 05 01:24:34 PM PDT 24 |
| Finished | May 05 01:27:09 PM PDT 24 |
| Peak memory | 182908 kb |
| Host | smart-f6c050df-04a7-4445-9157-8aa589a61e7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250665727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3250665727 |
| Directory | /workspace/2.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random.2001966867 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2509518228953 ps |
| CPU time | 1679.1 seconds |
| Started | May 05 01:24:31 PM PDT 24 |
| Finished | May 05 01:52:31 PM PDT 24 |
| Peak memory | 191136 kb |
| Host | smart-b894a647-7cda-4fea-9c27-70605baf22b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001966867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2001966867 |
| Directory | /workspace/2.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random_reset.516041023 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 406831648 ps |
| CPU time | 0.71 seconds |
| Started | May 05 01:24:25 PM PDT 24 |
| Finished | May 05 01:24:26 PM PDT 24 |
| Peak memory | 182732 kb |
| Host | smart-84801ddb-e3e8-49cc-8b37-02d17e7307af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516041023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.516041023 |
| Directory | /workspace/2.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_sec_cm.1666978116 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 205749674 ps |
| CPU time | 0.8 seconds |
| Started | May 05 01:24:28 PM PDT 24 |
| Finished | May 05 01:24:29 PM PDT 24 |
| Peak memory | 213424 kb |
| Host | smart-fb8ec790-e83b-4fa7-ad57-fc2a59cf43e5 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666978116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1666978116 |
| Directory | /workspace/2.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all.1536314035 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 914867205434 ps |
| CPU time | 639.77 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:35:10 PM PDT 24 |
| Peak memory | 191132 kb |
| Host | smart-72213320-06d7-4b9d-80b4-63bd9e564710 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536314035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 1536314035 |
| Directory | /workspace/2.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.rv_timer_disabled.3386219066 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 376002078079 ps |
| CPU time | 167.2 seconds |
| Started | May 05 01:24:48 PM PDT 24 |
| Finished | May 05 01:27:36 PM PDT 24 |
| Peak memory | 182972 kb |
| Host | smart-8a2bcf8b-5ea0-4344-8b53-2831c3a9419f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386219066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3386219066 |
| Directory | /workspace/20.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random.3926693850 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 829041409054 ps |
| CPU time | 652.81 seconds |
| Started | May 05 01:24:48 PM PDT 24 |
| Finished | May 05 01:35:41 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-15fc6227-b304-4229-acc5-f1b79a6dd5a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926693850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3926693850 |
| Directory | /workspace/20.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random_reset.3302074394 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 52783404121 ps |
| CPU time | 226.1 seconds |
| Started | May 05 01:24:45 PM PDT 24 |
| Finished | May 05 01:28:32 PM PDT 24 |
| Peak memory | 191204 kb |
| Host | smart-e8b3ffc9-1bdb-4d5b-8d9b-083b2c66162c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302074394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3302074394 |
| Directory | /workspace/20.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all.1241744968 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2385169168001 ps |
| CPU time | 1531.84 seconds |
| Started | May 05 01:24:49 PM PDT 24 |
| Finished | May 05 01:50:21 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-a5c7dda8-8ab8-4201-a7f5-aaa85b34b934 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241744968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all .1241744968 |
| Directory | /workspace/20.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.922480176 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 198043871344 ps |
| CPU time | 277.06 seconds |
| Started | May 05 01:24:47 PM PDT 24 |
| Finished | May 05 01:29:24 PM PDT 24 |
| Peak memory | 205796 kb |
| Host | smart-c9eddd67-c0d5-4908-a959-4348ca7e91c6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922480176 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.922480176 |
| Directory | /workspace/20.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.348034841 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 102780146989 ps |
| CPU time | 56.12 seconds |
| Started | May 05 01:24:54 PM PDT 24 |
| Finished | May 05 01:25:50 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-07314a5d-0f81-4b3f-8a3a-7446e4837cfa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348034841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.rv_timer_cfg_update_on_fly.348034841 |
| Directory | /workspace/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/21.rv_timer_disabled.27151095 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 214313065668 ps |
| CPU time | 81.68 seconds |
| Started | May 05 01:24:47 PM PDT 24 |
| Finished | May 05 01:26:09 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-8bae1745-cb67-44b3-80a2-ca9b52465cdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27151095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.27151095 |
| Directory | /workspace/21.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random.3534058471 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 18544885513 ps |
| CPU time | 10.13 seconds |
| Started | May 05 01:24:50 PM PDT 24 |
| Finished | May 05 01:25:00 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-0784d03f-9fe6-4760-8e64-9441c837047f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534058471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3534058471 |
| Directory | /workspace/21.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random_reset.3005270563 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 166621395 ps |
| CPU time | 0.86 seconds |
| Started | May 05 01:24:51 PM PDT 24 |
| Finished | May 05 01:24:52 PM PDT 24 |
| Peak memory | 182784 kb |
| Host | smart-01578b60-d412-4dba-9b68-9dee0264311e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005270563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3005270563 |
| Directory | /workspace/21.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all.1631131810 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2526652501303 ps |
| CPU time | 1616.92 seconds |
| Started | May 05 01:24:53 PM PDT 24 |
| Finished | May 05 01:51:50 PM PDT 24 |
| Peak memory | 191200 kb |
| Host | smart-2673f548-9f2c-4351-a731-d290dee5b66d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631131810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all .1631131810 |
| Directory | /workspace/21.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.697657874 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 874443196674 ps |
| CPU time | 493.52 seconds |
| Started | May 05 01:24:52 PM PDT 24 |
| Finished | May 05 01:33:05 PM PDT 24 |
| Peak memory | 182924 kb |
| Host | smart-884a2519-0bad-4e86-ae87-380dd28ccd5f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697657874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.rv_timer_cfg_update_on_fly.697657874 |
| Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/22.rv_timer_disabled.3963135283 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 233649300894 ps |
| CPU time | 192.78 seconds |
| Started | May 05 01:24:53 PM PDT 24 |
| Finished | May 05 01:28:06 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-df760d68-6695-4f86-bbe5-120c9cfd1a71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963135283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3963135283 |
| Directory | /workspace/22.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random.837140954 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 35668694855 ps |
| CPU time | 38.55 seconds |
| Started | May 05 01:24:55 PM PDT 24 |
| Finished | May 05 01:25:33 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-7c427287-1c86-482c-ad60-6daa29265f41 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837140954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.837140954 |
| Directory | /workspace/22.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random_reset.1617418884 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 731398349405 ps |
| CPU time | 417.97 seconds |
| Started | May 05 01:24:50 PM PDT 24 |
| Finished | May 05 01:31:49 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-e6365128-006d-4788-bf35-ebd1acd2340b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1617418884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1617418884 |
| Directory | /workspace/22.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_disabled.3507914680 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 50371291621 ps |
| CPU time | 20.82 seconds |
| Started | May 05 01:24:52 PM PDT 24 |
| Finished | May 05 01:25:13 PM PDT 24 |
| Peak memory | 183032 kb |
| Host | smart-227276a6-331d-424d-b1c5-6b9da488ee26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507914680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3507914680 |
| Directory | /workspace/23.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random.489701375 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1696780607165 ps |
| CPU time | 327.68 seconds |
| Started | May 05 01:24:50 PM PDT 24 |
| Finished | May 05 01:30:18 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-8c829930-7974-445c-a140-ec5a24c8847e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489701375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.489701375 |
| Directory | /workspace/23.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random_reset.752684540 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 64461090919 ps |
| CPU time | 51.64 seconds |
| Started | May 05 01:24:53 PM PDT 24 |
| Finished | May 05 01:25:45 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-0b9df078-3cb3-40f0-bc61-ed6d1657713d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752684540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.752684540 |
| Directory | /workspace/23.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all.1254553758 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 360562222525 ps |
| CPU time | 580.5 seconds |
| Started | May 05 01:24:56 PM PDT 24 |
| Finished | May 05 01:34:37 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-46f6a32f-cf1c-44bb-a7d7-46b99800c0dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254553758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .1254553758 |
| Directory | /workspace/23.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.48372062 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 366311836601 ps |
| CPU time | 656.51 seconds |
| Started | May 05 01:24:59 PM PDT 24 |
| Finished | May 05 01:35:56 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-7dfbbffa-0591-4ddf-b276-b6d0137913c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48372062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .rv_timer_cfg_update_on_fly.48372062 |
| Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_disabled.4223191913 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 255218888370 ps |
| CPU time | 100.7 seconds |
| Started | May 05 01:24:56 PM PDT 24 |
| Finished | May 05 01:26:38 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-26e5edd2-6888-496e-87fa-33171e82a9ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223191913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4223191913 |
| Directory | /workspace/24.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random.2412440775 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 530155921937 ps |
| CPU time | 666.3 seconds |
| Started | May 05 01:24:58 PM PDT 24 |
| Finished | May 05 01:36:04 PM PDT 24 |
| Peak memory | 191076 kb |
| Host | smart-cbff2cd4-e8b6-4f53-8f0d-0e25eb340205 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412440775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2412440775 |
| Directory | /workspace/24.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all.1273741794 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2751376939245 ps |
| CPU time | 1131.31 seconds |
| Started | May 05 01:24:58 PM PDT 24 |
| Finished | May 05 01:43:51 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-24aaa89c-b275-44ba-824b-0e67eec018bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273741794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all .1273741794 |
| Directory | /workspace/24.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.287263030 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 34747765899 ps |
| CPU time | 159.24 seconds |
| Started | May 05 01:24:58 PM PDT 24 |
| Finished | May 05 01:27:39 PM PDT 24 |
| Peak memory | 197636 kb |
| Host | smart-3e5ba637-2624-494f-af40-625769e66cb2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287263030 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.287263030 |
| Directory | /workspace/24.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2590142330 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9049276139 ps |
| CPU time | 15.97 seconds |
| Started | May 05 01:24:58 PM PDT 24 |
| Finished | May 05 01:25:14 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-65a8ab97-2381-4a8f-ac65-1ca2f3106508 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590142330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2590142330 |
| Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/25.rv_timer_disabled.3525583336 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 122497137875 ps |
| CPU time | 192.94 seconds |
| Started | May 05 01:24:58 PM PDT 24 |
| Finished | May 05 01:28:11 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-a262a99c-3ce7-49fe-810a-29101d6d4637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3525583336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3525583336 |
| Directory | /workspace/25.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random_reset.352107012 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 340600111 ps |
| CPU time | 0.78 seconds |
| Started | May 05 01:24:58 PM PDT 24 |
| Finished | May 05 01:24:59 PM PDT 24 |
| Peak memory | 192428 kb |
| Host | smart-11d7815a-3e8c-41cd-b957-560bdb72d881 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352107012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.352107012 |
| Directory | /workspace/25.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all.2762834028 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 414232887031 ps |
| CPU time | 327.06 seconds |
| Started | May 05 01:24:57 PM PDT 24 |
| Finished | May 05 01:30:24 PM PDT 24 |
| Peak memory | 193352 kb |
| Host | smart-e34574f3-9f5d-4ee3-b20a-216c15820c90 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762834028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all .2762834028 |
| Directory | /workspace/25.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3010636707 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 192494926414 ps |
| CPU time | 332.17 seconds |
| Started | May 05 01:24:58 PM PDT 24 |
| Finished | May 05 01:30:30 PM PDT 24 |
| Peak memory | 182908 kb |
| Host | smart-37d56371-b165-4f15-8a06-7dec03d82413 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010636707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3010636707 |
| Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/26.rv_timer_disabled.988105123 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 379514279421 ps |
| CPU time | 165.66 seconds |
| Started | May 05 01:24:56 PM PDT 24 |
| Finished | May 05 01:27:42 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-c9293820-0b7f-4d4e-a75c-eda129463000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988105123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.988105123 |
| Directory | /workspace/26.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random.1405084378 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 76304690023 ps |
| CPU time | 68.03 seconds |
| Started | May 05 01:24:57 PM PDT 24 |
| Finished | May 05 01:26:05 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-a2e36fe0-7563-408f-8a2c-8231d77e061c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405084378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1405084378 |
| Directory | /workspace/26.rv_timer_random/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random_reset.2099970297 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 763066058 ps |
| CPU time | 1.63 seconds |
| Started | May 05 01:24:57 PM PDT 24 |
| Finished | May 05 01:24:59 PM PDT 24 |
| Peak memory | 182772 kb |
| Host | smart-8a4508f8-9f0d-4973-b02d-5c709ed2782b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099970297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2099970297 |
| Directory | /workspace/26.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.257062742 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2436791702058 ps |
| CPU time | 936.57 seconds |
| Started | May 05 01:24:59 PM PDT 24 |
| Finished | May 05 01:40:36 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-dec837b1-2f50-4a40-bde7-82cc52e320fc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257062742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.rv_timer_cfg_update_on_fly.257062742 |
| Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/27.rv_timer_disabled.3943675096 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 30740240392 ps |
| CPU time | 41.11 seconds |
| Started | May 05 01:24:56 PM PDT 24 |
| Finished | May 05 01:25:38 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-5b8f63fe-de12-48f6-8b3d-7c1d61928e40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943675096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3943675096 |
| Directory | /workspace/27.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random.4202222612 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 769197305535 ps |
| CPU time | 993.07 seconds |
| Started | May 05 01:24:59 PM PDT 24 |
| Finished | May 05 01:41:33 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-d3999156-9dc0-4b17-82f5-65b5ded5f22e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202222612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.4202222612 |
| Directory | /workspace/27.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random_reset.3701202043 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5995172521 ps |
| CPU time | 2.95 seconds |
| Started | May 05 01:24:59 PM PDT 24 |
| Finished | May 05 01:25:03 PM PDT 24 |
| Peak memory | 194500 kb |
| Host | smart-77348d66-13eb-48ea-8e90-cd4561f8a698 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701202043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3701202043 |
| Directory | /workspace/27.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all.1127000586 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 148888744590 ps |
| CPU time | 54.51 seconds |
| Started | May 05 01:25:01 PM PDT 24 |
| Finished | May 05 01:25:56 PM PDT 24 |
| Peak memory | 194576 kb |
| Host | smart-f28ed5b1-0d04-49c5-84c0-8a414fcf46c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127000586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .1127000586 |
| Directory | /workspace/27.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3732335501 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6995142643902 ps |
| CPU time | 1882.89 seconds |
| Started | May 05 01:25:00 PM PDT 24 |
| Finished | May 05 01:56:23 PM PDT 24 |
| Peak memory | 182892 kb |
| Host | smart-9ac5b23d-b9c0-4f86-ba66-8fe43fdfbb95 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732335501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.3732335501 |
| Directory | /workspace/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/28.rv_timer_disabled.4055324819 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 778016378209 ps |
| CPU time | 152.37 seconds |
| Started | May 05 01:25:02 PM PDT 24 |
| Finished | May 05 01:27:35 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-a1fc94d2-ea48-48d1-9f12-582a33c07764 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055324819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.4055324819 |
| Directory | /workspace/28.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random_reset.3682625593 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 845963946410 ps |
| CPU time | 472.33 seconds |
| Started | May 05 01:25:01 PM PDT 24 |
| Finished | May 05 01:32:54 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-994d6f81-13f3-455d-baa0-14a1177d6767 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682625593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3682625593 |
| Directory | /workspace/28.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.837643885 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 302658944921 ps |
| CPU time | 515.45 seconds |
| Started | May 05 01:25:01 PM PDT 24 |
| Finished | May 05 01:33:37 PM PDT 24 |
| Peak memory | 183000 kb |
| Host | smart-79399949-d3ba-48ed-b130-43dc53d5cf6f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837643885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.rv_timer_cfg_update_on_fly.837643885 |
| Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/29.rv_timer_disabled.2898913610 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 108041103080 ps |
| CPU time | 159.45 seconds |
| Started | May 05 01:25:02 PM PDT 24 |
| Finished | May 05 01:27:42 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-62c2c6b7-a520-4c0e-b2e1-30e9dab7549c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898913610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2898913610 |
| Directory | /workspace/29.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random.851106542 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 126865632485 ps |
| CPU time | 100.07 seconds |
| Started | May 05 01:25:05 PM PDT 24 |
| Finished | May 05 01:26:46 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-432e4af1-3a42-47e4-82cf-79adb73de458 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851106542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.851106542 |
| Directory | /workspace/29.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random_reset.1775457237 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 36911212978 ps |
| CPU time | 64.02 seconds |
| Started | May 05 01:25:02 PM PDT 24 |
| Finished | May 05 01:26:07 PM PDT 24 |
| Peak memory | 183004 kb |
| Host | smart-0057bea7-0018-4941-8e08-6574b81adbbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775457237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1775457237 |
| Directory | /workspace/29.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all.264813161 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1925997671020 ps |
| CPU time | 379.82 seconds |
| Started | May 05 01:25:02 PM PDT 24 |
| Finished | May 05 01:31:23 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-2c444119-497d-41f1-9fc7-d26c151003fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264813161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all. 264813161 |
| Directory | /workspace/29.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2626364057 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 6630248209 ps |
| CPU time | 10.58 seconds |
| Started | May 05 01:24:32 PM PDT 24 |
| Finished | May 05 01:24:43 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-09a1f1c0-38bc-4053-8ec0-90ef33cdec85 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626364057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.2626364057 |
| Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/3.rv_timer_disabled.2363444602 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 157029598224 ps |
| CPU time | 236.88 seconds |
| Started | May 05 01:24:26 PM PDT 24 |
| Finished | May 05 01:28:24 PM PDT 24 |
| Peak memory | 182952 kb |
| Host | smart-a833c4f1-813f-455b-a399-8c09f8f698b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363444602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2363444602 |
| Directory | /workspace/3.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random.2746142361 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 298544370558 ps |
| CPU time | 179.17 seconds |
| Started | May 05 01:24:27 PM PDT 24 |
| Finished | May 05 01:27:27 PM PDT 24 |
| Peak memory | 194344 kb |
| Host | smart-a7c7de31-41e0-41bd-a30b-f0d3e86e277c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746142361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2746142361 |
| Directory | /workspace/3.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random_reset.3982830845 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 25827673845 ps |
| CPU time | 84.96 seconds |
| Started | May 05 01:24:29 PM PDT 24 |
| Finished | May 05 01:25:55 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-4f0e62c0-0b4b-4c5d-bcc1-1c655d90b3dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982830845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3982830845 |
| Directory | /workspace/3.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_sec_cm.1171622820 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 34109116 ps |
| CPU time | 0.75 seconds |
| Started | May 05 01:24:28 PM PDT 24 |
| Finished | May 05 01:24:29 PM PDT 24 |
| Peak memory | 213384 kb |
| Host | smart-5940c023-394f-4de7-af10-437c8786b1b6 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171622820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1171622820 |
| Directory | /workspace/3.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all.3116428411 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 63779785740 ps |
| CPU time | 77.81 seconds |
| Started | May 05 01:24:34 PM PDT 24 |
| Finished | May 05 01:25:52 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-fa24d5dc-11c0-4114-adc0-93254303aa09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116428411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 3116428411 |
| Directory | /workspace/3.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4183153156 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 126969987058 ps |
| CPU time | 205.33 seconds |
| Started | May 05 01:25:02 PM PDT 24 |
| Finished | May 05 01:28:28 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-e9829f05-3f10-4491-b948-f5f74725c044 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183153156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.4183153156 |
| Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_disabled.3468752080 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 118628439769 ps |
| CPU time | 85.7 seconds |
| Started | May 05 01:25:02 PM PDT 24 |
| Finished | May 05 01:26:28 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-6ed94ab2-a57d-40e0-a85c-ce84dedfed58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468752080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3468752080 |
| Directory | /workspace/30.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random.2140451862 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 241787268397 ps |
| CPU time | 744.16 seconds |
| Started | May 05 01:25:05 PM PDT 24 |
| Finished | May 05 01:37:29 PM PDT 24 |
| Peak memory | 193484 kb |
| Host | smart-d200dc8c-1a07-4b38-a11b-20b2e6351468 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140451862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2140451862 |
| Directory | /workspace/30.rv_timer_random/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random_reset.3039595330 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 154460918595 ps |
| CPU time | 433.42 seconds |
| Started | May 05 01:25:04 PM PDT 24 |
| Finished | May 05 01:32:18 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-9c47e2b3-0cfc-41c0-bf9d-2f30ce7e40f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039595330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3039595330 |
| Directory | /workspace/30.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all.2373223737 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 120128346272 ps |
| CPU time | 184.72 seconds |
| Started | May 05 01:25:01 PM PDT 24 |
| Finished | May 05 01:28:07 PM PDT 24 |
| Peak memory | 194516 kb |
| Host | smart-fb4d889c-a672-4eef-b058-b1a228d7e870 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373223737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .2373223737 |
| Directory | /workspace/30.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1541207937 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2747899041948 ps |
| CPU time | 975.29 seconds |
| Started | May 05 01:25:04 PM PDT 24 |
| Finished | May 05 01:41:20 PM PDT 24 |
| Peak memory | 182940 kb |
| Host | smart-ce8a3275-a584-4880-b604-fbb43d0e1344 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541207937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.1541207937 |
| Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/31.rv_timer_disabled.2068910064 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 104825096215 ps |
| CPU time | 140.02 seconds |
| Started | May 05 01:25:07 PM PDT 24 |
| Finished | May 05 01:27:28 PM PDT 24 |
| Peak memory | 182908 kb |
| Host | smart-30500e9e-3440-4011-a79c-39ba44788d6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068910064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2068910064 |
| Directory | /workspace/31.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random.1764397332 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 159326073311 ps |
| CPU time | 129.33 seconds |
| Started | May 05 01:25:00 PM PDT 24 |
| Finished | May 05 01:27:10 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-4e95274d-bbf2-411e-b388-cdeaf844ad86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764397332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1764397332 |
| Directory | /workspace/31.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random_reset.2221766754 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 41104411995 ps |
| CPU time | 107.07 seconds |
| Started | May 05 01:25:07 PM PDT 24 |
| Finished | May 05 01:26:55 PM PDT 24 |
| Peak memory | 191104 kb |
| Host | smart-fe1e3c13-f2eb-46d7-a7ba-8bd7ce6bca9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221766754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2221766754 |
| Directory | /workspace/31.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.4291962574 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 229191524887 ps |
| CPU time | 390.83 seconds |
| Started | May 05 01:25:04 PM PDT 24 |
| Finished | May 05 01:31:36 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-534d6de1-7e05-40e4-b6e4-e15c4ce1867d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291962574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.4291962574 |
| Directory | /workspace/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/32.rv_timer_disabled.1892956367 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 109307632193 ps |
| CPU time | 172.89 seconds |
| Started | May 05 01:25:05 PM PDT 24 |
| Finished | May 05 01:27:59 PM PDT 24 |
| Peak memory | 182940 kb |
| Host | smart-248ff609-c67f-4376-9117-9723d0ac7f8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892956367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1892956367 |
| Directory | /workspace/32.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random.1468089125 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 68445526783 ps |
| CPU time | 292.62 seconds |
| Started | May 05 01:25:07 PM PDT 24 |
| Finished | May 05 01:30:01 PM PDT 24 |
| Peak memory | 191088 kb |
| Host | smart-2ba3c1a1-e3eb-4566-b5cb-25c1a9a6458e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468089125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1468089125 |
| Directory | /workspace/32.rv_timer_random/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random_reset.279473575 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 61791326 ps |
| CPU time | 0.6 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:25:07 PM PDT 24 |
| Peak memory | 182720 kb |
| Host | smart-53f9559a-cdd2-4b7f-88c0-c147c220e759 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279473575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.279473575 |
| Directory | /workspace/32.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3401323063 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 86096838165 ps |
| CPU time | 91.97 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:26:39 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-21af1d67-892b-4f01-8b48-1e91da049808 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401323063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.3401323063 |
| Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/33.rv_timer_disabled.501436788 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 312078725197 ps |
| CPU time | 143.97 seconds |
| Started | May 05 01:25:10 PM PDT 24 |
| Finished | May 05 01:27:35 PM PDT 24 |
| Peak memory | 182908 kb |
| Host | smart-3904ee52-2d4d-4e44-9fff-3e0b53ebbe0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501436788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.501436788 |
| Directory | /workspace/33.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random.2754383973 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 49741248445 ps |
| CPU time | 85.23 seconds |
| Started | May 05 01:25:07 PM PDT 24 |
| Finished | May 05 01:26:33 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-031fc5e4-3d7c-430e-a0a2-c5358b771cfe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754383973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2754383973 |
| Directory | /workspace/33.rv_timer_random/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random_reset.2362217720 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 121975424091 ps |
| CPU time | 47.71 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:25:54 PM PDT 24 |
| Peak memory | 194244 kb |
| Host | smart-ff9bc20c-8183-4158-a2b7-0d3852b3eccb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362217720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2362217720 |
| Directory | /workspace/33.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.4188291525 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 60025117537 ps |
| CPU time | 87.7 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:26:34 PM PDT 24 |
| Peak memory | 182920 kb |
| Host | smart-bca52800-1ca8-432b-91f4-19d71e0445e5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188291525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.4188291525 |
| Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/34.rv_timer_disabled.3518568373 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 614303159511 ps |
| CPU time | 160.66 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:27:47 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-c0845c5c-f82e-4f30-98d4-137b6baa2273 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3518568373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3518568373 |
| Directory | /workspace/34.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random.3771849983 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 174730971519 ps |
| CPU time | 981.62 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:41:28 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-fd4b7793-9de8-4062-b086-430b75fc32e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771849983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3771849983 |
| Directory | /workspace/34.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random_reset.4243673693 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 310436143745 ps |
| CPU time | 164.85 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:27:51 PM PDT 24 |
| Peak memory | 194620 kb |
| Host | smart-cd811ebd-a2ea-4cc1-bcf0-26680fadcbe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243673693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.4243673693 |
| Directory | /workspace/34.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2426118133 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 946202775386 ps |
| CPU time | 868.09 seconds |
| Started | May 05 01:25:04 PM PDT 24 |
| Finished | May 05 01:39:33 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-3e416b42-ae05-404d-a47d-1cf43d84d109 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426118133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.2426118133 |
| Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/35.rv_timer_disabled.2142363840 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 109478625659 ps |
| CPU time | 128.81 seconds |
| Started | May 05 01:25:12 PM PDT 24 |
| Finished | May 05 01:27:21 PM PDT 24 |
| Peak memory | 182908 kb |
| Host | smart-64ffecc3-7243-4e69-b696-20287059c224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142363840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2142363840 |
| Directory | /workspace/35.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random_reset.2861736505 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 226414261 ps |
| CPU time | 0.98 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:25:08 PM PDT 24 |
| Peak memory | 182672 kb |
| Host | smart-7caf69fb-e11f-4ff2-b125-849e4634cd29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2861736505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2861736505 |
| Directory | /workspace/35.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.120763705 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 39055269828 ps |
| CPU time | 415.27 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:32:02 PM PDT 24 |
| Peak memory | 205768 kb |
| Host | smart-9980156d-9f71-4b82-913e-1d46a5fea1aa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120763705 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.120763705 |
| Directory | /workspace/35.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2407461625 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 62182190285 ps |
| CPU time | 106.64 seconds |
| Started | May 05 01:25:06 PM PDT 24 |
| Finished | May 05 01:26:53 PM PDT 24 |
| Peak memory | 183012 kb |
| Host | smart-4d33a053-3ce5-456d-a939-b8293d19d468 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407461625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.2407461625 |
| Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/36.rv_timer_disabled.1701829688 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3000715429 ps |
| CPU time | 2.41 seconds |
| Started | May 05 01:25:05 PM PDT 24 |
| Finished | May 05 01:25:08 PM PDT 24 |
| Peak memory | 182896 kb |
| Host | smart-e4213303-b389-400e-944d-32d3c53865a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701829688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1701829688 |
| Directory | /workspace/36.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random_reset.3023125756 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 171124249068 ps |
| CPU time | 658.45 seconds |
| Started | May 05 01:25:04 PM PDT 24 |
| Finished | May 05 01:36:03 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-a6385a32-2558-445b-8012-fc9dc2f57645 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023125756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3023125756 |
| Directory | /workspace/36.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all.1333218221 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 148581574400 ps |
| CPU time | 207.72 seconds |
| Started | May 05 01:25:11 PM PDT 24 |
| Finished | May 05 01:28:39 PM PDT 24 |
| Peak memory | 182932 kb |
| Host | smart-ac37e9ba-81b7-425f-a3e4-24ee1468557b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333218221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .1333218221 |
| Directory | /workspace/36.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.rv_timer_disabled.1540991852 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 141851806987 ps |
| CPU time | 108.31 seconds |
| Started | May 05 01:25:14 PM PDT 24 |
| Finished | May 05 01:27:02 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-06ef9eaa-3bba-41a7-8c4d-5ca5ee378945 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540991852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1540991852 |
| Directory | /workspace/37.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.4113423193 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 19281165896 ps |
| CPU time | 112.17 seconds |
| Started | May 05 01:25:12 PM PDT 24 |
| Finished | May 05 01:27:05 PM PDT 24 |
| Peak memory | 197676 kb |
| Host | smart-1e44b2f1-de83-40e7-8876-dbeec8308a5a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113423193 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.4113423193 |
| Directory | /workspace/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2947072376 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 14427209509 ps |
| CPU time | 25.17 seconds |
| Started | May 05 01:25:11 PM PDT 24 |
| Finished | May 05 01:25:36 PM PDT 24 |
| Peak memory | 182932 kb |
| Host | smart-566939b2-d551-4994-a41a-0c6660efcdce |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947072376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.2947072376 |
| Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/38.rv_timer_disabled.1605850385 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 430426292411 ps |
| CPU time | 143.8 seconds |
| Started | May 05 01:25:13 PM PDT 24 |
| Finished | May 05 01:27:38 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-5c74678e-436f-4aad-933d-1921874e8a73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605850385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1605850385 |
| Directory | /workspace/38.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random_reset.2131122575 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 74680995049 ps |
| CPU time | 227.34 seconds |
| Started | May 05 01:25:12 PM PDT 24 |
| Finished | May 05 01:29:00 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-07dea662-ab0c-404a-b5a1-c352fcede878 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131122575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2131122575 |
| Directory | /workspace/38.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all.1250991069 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 54532712 ps |
| CPU time | 0.52 seconds |
| Started | May 05 01:25:16 PM PDT 24 |
| Finished | May 05 01:25:16 PM PDT 24 |
| Peak memory | 182768 kb |
| Host | smart-05ce21a2-55a3-4626-a0eb-50f357ccfda3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250991069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .1250991069 |
| Directory | /workspace/38.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3887358908 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2721643535 ps |
| CPU time | 5.07 seconds |
| Started | May 05 01:25:15 PM PDT 24 |
| Finished | May 05 01:25:20 PM PDT 24 |
| Peak memory | 183016 kb |
| Host | smart-881acf67-5470-4272-a2e3-5159a0ad3b74 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887358908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.3887358908 |
| Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/39.rv_timer_disabled.3337037364 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 438454313133 ps |
| CPU time | 258.19 seconds |
| Started | May 05 01:25:16 PM PDT 24 |
| Finished | May 05 01:29:35 PM PDT 24 |
| Peak memory | 182940 kb |
| Host | smart-050d836f-cea2-4f55-9280-6affad57fb02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337037364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3337037364 |
| Directory | /workspace/39.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random_reset.2805145645 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 202947964 ps |
| CPU time | 0.8 seconds |
| Started | May 05 01:25:15 PM PDT 24 |
| Finished | May 05 01:25:16 PM PDT 24 |
| Peak memory | 182760 kb |
| Host | smart-f4ea8c1e-3321-42b2-9009-e411b1614181 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805145645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2805145645 |
| Directory | /workspace/39.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all.474219123 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1063498312837 ps |
| CPU time | 714.76 seconds |
| Started | May 05 01:25:16 PM PDT 24 |
| Finished | May 05 01:37:11 PM PDT 24 |
| Peak memory | 191096 kb |
| Host | smart-b167387c-0f18-4fdb-9789-3c481c8df746 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474219123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all. 474219123 |
| Directory | /workspace/39.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.836606705 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 320486598424 ps |
| CPU time | 185.31 seconds |
| Started | May 05 01:24:27 PM PDT 24 |
| Finished | May 05 01:27:33 PM PDT 24 |
| Peak memory | 183000 kb |
| Host | smart-a5a1ae3a-8357-4c27-8041-3d22a83bb108 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836606705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .rv_timer_cfg_update_on_fly.836606705 |
| Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/4.rv_timer_disabled.1186763632 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 13397548190 ps |
| CPU time | 22.17 seconds |
| Started | May 05 01:24:28 PM PDT 24 |
| Finished | May 05 01:24:51 PM PDT 24 |
| Peak memory | 182972 kb |
| Host | smart-903009ec-30fc-4d3f-a140-5e97cae84328 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186763632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1186763632 |
| Directory | /workspace/4.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random.287057292 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 204881665636 ps |
| CPU time | 244.68 seconds |
| Started | May 05 01:24:41 PM PDT 24 |
| Finished | May 05 01:28:47 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-04a642f2-e0e7-4cb1-9ee9-f4d9ee4ff43a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287057292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.287057292 |
| Directory | /workspace/4.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random_reset.1517894110 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 464196323448 ps |
| CPU time | 150.61 seconds |
| Started | May 05 01:24:27 PM PDT 24 |
| Finished | May 05 01:26:58 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-7f06d433-ebbb-402d-ad6c-5cf5061bf6bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517894110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1517894110 |
| Directory | /workspace/4.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_sec_cm.2293926966 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 224435356 ps |
| CPU time | 0.79 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:24:32 PM PDT 24 |
| Peak memory | 213400 kb |
| Host | smart-65b4886a-d760-4e39-860d-226419742c6a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293926966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2293926966 |
| Directory | /workspace/4.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3911511477 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2184332549768 ps |
| CPU time | 727.22 seconds |
| Started | May 05 01:25:28 PM PDT 24 |
| Finished | May 05 01:37:36 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-345bf244-b5c3-42d9-9020-9612ffd23478 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911511477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.3911511477 |
| Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/40.rv_timer_disabled.2926393605 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 680347771191 ps |
| CPU time | 260.91 seconds |
| Started | May 05 01:25:15 PM PDT 24 |
| Finished | May 05 01:29:36 PM PDT 24 |
| Peak memory | 182900 kb |
| Host | smart-e33dc0c0-e7c4-4e47-af9b-3a1548326565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926393605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2926393605 |
| Directory | /workspace/40.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random.3359948570 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 254680743017 ps |
| CPU time | 669.98 seconds |
| Started | May 05 01:25:14 PM PDT 24 |
| Finished | May 05 01:36:25 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-80002fa4-e3bc-4d7e-8ea5-f133e2726bc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359948570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3359948570 |
| Directory | /workspace/40.rv_timer_random/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random_reset.866277480 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 29034171804 ps |
| CPU time | 45.46 seconds |
| Started | May 05 01:25:28 PM PDT 24 |
| Finished | May 05 01:26:14 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-ef958387-0ae8-495d-b299-4f22a5a2584b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866277480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.866277480 |
| Directory | /workspace/40.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all.4151001210 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 393961690581 ps |
| CPU time | 1818.13 seconds |
| Started | May 05 01:25:29 PM PDT 24 |
| Finished | May 05 01:55:47 PM PDT 24 |
| Peak memory | 195736 kb |
| Host | smart-84389913-65c1-478c-b201-ed098620720b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151001210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all .4151001210 |
| Directory | /workspace/40.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3396040975 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 93381168060 ps |
| CPU time | 597.17 seconds |
| Started | May 05 01:25:28 PM PDT 24 |
| Finished | May 05 01:35:25 PM PDT 24 |
| Peak memory | 205848 kb |
| Host | smart-567ffaa1-07c4-4153-bca2-3e4404f05b97 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396040975 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3396040975 |
| Directory | /workspace/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2600571484 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 392835914208 ps |
| CPU time | 334.78 seconds |
| Started | May 05 01:25:28 PM PDT 24 |
| Finished | May 05 01:31:03 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-4ce4a2f4-f3d3-4898-a4d2-b9263f910623 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600571484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.2600571484 |
| Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/41.rv_timer_disabled.1849935223 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 29976608697 ps |
| CPU time | 45.79 seconds |
| Started | May 05 01:25:29 PM PDT 24 |
| Finished | May 05 01:26:15 PM PDT 24 |
| Peak memory | 183016 kb |
| Host | smart-3cb819a4-b8d9-4792-8c91-047f27f27ce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849935223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1849935223 |
| Directory | /workspace/41.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random.3400002231 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 41053215353 ps |
| CPU time | 55.61 seconds |
| Started | May 05 01:25:27 PM PDT 24 |
| Finished | May 05 01:26:23 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-b21c6ed9-025c-4ddc-805f-c8cd726c55d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400002231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3400002231 |
| Directory | /workspace/41.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random_reset.1053799287 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 166658911907 ps |
| CPU time | 67.32 seconds |
| Started | May 05 01:25:28 PM PDT 24 |
| Finished | May 05 01:26:35 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-c08c83c4-5683-4c81-9c93-afa57106eb7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053799287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1053799287 |
| Directory | /workspace/41.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all.3787411911 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 232672178722 ps |
| CPU time | 441.66 seconds |
| Started | May 05 01:25:27 PM PDT 24 |
| Finished | May 05 01:32:49 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-2c091ff7-9a15-48a5-93b0-7e31fb39d6bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787411911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all .3787411911 |
| Directory | /workspace/41.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3352135389 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2752136708575 ps |
| CPU time | 990.64 seconds |
| Started | May 05 01:25:30 PM PDT 24 |
| Finished | May 05 01:42:01 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-41d7efb0-729d-40d3-b3ae-8469e0fe98f2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352135389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.3352135389 |
| Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random.2426310862 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 126294041644 ps |
| CPU time | 239.97 seconds |
| Started | May 05 01:25:30 PM PDT 24 |
| Finished | May 05 01:29:30 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-290c6110-e003-4a4d-a9a8-6705286d87fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426310862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2426310862 |
| Directory | /workspace/42.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random_reset.2284057285 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 188928451422 ps |
| CPU time | 931.24 seconds |
| Started | May 05 01:25:31 PM PDT 24 |
| Finished | May 05 01:41:03 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-bb7d04f8-bbef-43ad-b0b0-8e0a69fb52e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2284057285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2284057285 |
| Directory | /workspace/42.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all.3982756783 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 52423162 ps |
| CPU time | 0.68 seconds |
| Started | May 05 01:25:35 PM PDT 24 |
| Finished | May 05 01:25:36 PM PDT 24 |
| Peak memory | 182784 kb |
| Host | smart-ab4e7cbe-559a-4353-9d28-03902c516815 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982756783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all .3982756783 |
| Directory | /workspace/42.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3509921368 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 232447294333 ps |
| CPU time | 377.91 seconds |
| Started | May 05 01:25:35 PM PDT 24 |
| Finished | May 05 01:31:54 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-e8d7f53b-4df9-4da5-a10d-e831536ba810 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509921368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3509921368 |
| Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_disabled.1020355860 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 54060899485 ps |
| CPU time | 23.72 seconds |
| Started | May 05 01:25:34 PM PDT 24 |
| Finished | May 05 01:25:58 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-5a01bfba-ee7f-4768-8e83-28d34f82441a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020355860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1020355860 |
| Directory | /workspace/43.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random_reset.3507195341 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 787363971 ps |
| CPU time | 1 seconds |
| Started | May 05 01:25:35 PM PDT 24 |
| Finished | May 05 01:25:36 PM PDT 24 |
| Peak memory | 182796 kb |
| Host | smart-911df608-9f01-40b4-afe1-dc9251e9fdb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507195341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3507195341 |
| Directory | /workspace/43.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all.1029873423 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 143823292303 ps |
| CPU time | 479.29 seconds |
| Started | May 05 01:25:36 PM PDT 24 |
| Finished | May 05 01:33:36 PM PDT 24 |
| Peak memory | 191200 kb |
| Host | smart-5070c7a8-73e3-4eba-9410-924bd900247a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029873423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all .1029873423 |
| Directory | /workspace/43.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.587893934 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 843920458334 ps |
| CPU time | 809.92 seconds |
| Started | May 05 01:25:41 PM PDT 24 |
| Finished | May 05 01:39:11 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-b1146c87-c2e3-41cd-913a-327fce4688cd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587893934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.rv_timer_cfg_update_on_fly.587893934 |
| Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_disabled.322724142 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 109492088198 ps |
| CPU time | 172.63 seconds |
| Started | May 05 01:25:40 PM PDT 24 |
| Finished | May 05 01:28:33 PM PDT 24 |
| Peak memory | 183012 kb |
| Host | smart-ae211fdc-c13c-44f4-bcbc-ecb77da2de87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322724142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.322724142 |
| Directory | /workspace/44.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random.1391764167 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 44652770977 ps |
| CPU time | 102.76 seconds |
| Started | May 05 01:25:35 PM PDT 24 |
| Finished | May 05 01:27:18 PM PDT 24 |
| Peak memory | 182948 kb |
| Host | smart-6cb3a3f1-2097-4d0c-81fb-45e982992043 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391764167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1391764167 |
| Directory | /workspace/44.rv_timer_random/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random_reset.2256947326 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 620704484 ps |
| CPU time | 0.75 seconds |
| Started | May 05 01:25:38 PM PDT 24 |
| Finished | May 05 01:25:39 PM PDT 24 |
| Peak memory | 182756 kb |
| Host | smart-c121ab47-0ca1-4883-8d0d-8f74cb0fa743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256947326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2256947326 |
| Directory | /workspace/44.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all.2952429658 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 465305188751 ps |
| CPU time | 1013.61 seconds |
| Started | May 05 01:25:39 PM PDT 24 |
| Finished | May 05 01:42:33 PM PDT 24 |
| Peak memory | 191140 kb |
| Host | smart-921bfd46-474f-4a05-a73b-2be0e520339f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952429658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all .2952429658 |
| Directory | /workspace/44.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3141133198 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 556967004790 ps |
| CPU time | 279.54 seconds |
| Started | May 05 01:25:48 PM PDT 24 |
| Finished | May 05 01:30:28 PM PDT 24 |
| Peak memory | 183000 kb |
| Host | smart-74b0a85e-d102-443b-a84b-19c506f519bd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141133198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.3141133198 |
| Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random.185410552 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 106725104425 ps |
| CPU time | 121.67 seconds |
| Started | May 05 01:25:48 PM PDT 24 |
| Finished | May 05 01:27:50 PM PDT 24 |
| Peak memory | 191200 kb |
| Host | smart-b9d0fb38-6de0-45f0-88b9-a9a394349739 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185410552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.185410552 |
| Directory | /workspace/45.rv_timer_random/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random_reset.41031737 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 13734231865 ps |
| CPU time | 14.49 seconds |
| Started | May 05 01:25:48 PM PDT 24 |
| Finished | May 05 01:26:03 PM PDT 24 |
| Peak memory | 191204 kb |
| Host | smart-18fad960-5000-42df-9ee4-f066270582bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41031737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.41031737 |
| Directory | /workspace/45.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all.1914171194 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 575829794925 ps |
| CPU time | 1714.52 seconds |
| Started | May 05 01:25:46 PM PDT 24 |
| Finished | May 05 01:54:21 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-34fcb136-a05a-4af6-ae95-fd5801fd429d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914171194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all .1914171194 |
| Directory | /workspace/45.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1340181695 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 215758028715 ps |
| CPU time | 354.82 seconds |
| Started | May 05 01:25:44 PM PDT 24 |
| Finished | May 05 01:31:40 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-0e3738e5-61f6-49a0-8820-4b93f282fd44 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340181695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.1340181695 |
| Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random_reset.764708172 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 713322580 ps |
| CPU time | 0.8 seconds |
| Started | May 05 01:25:48 PM PDT 24 |
| Finished | May 05 01:25:50 PM PDT 24 |
| Peak memory | 182756 kb |
| Host | smart-50b4f25a-69f6-4d1e-84c0-6c2cb2022606 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764708172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.764708172 |
| Directory | /workspace/46.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all.441581659 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 458075565060 ps |
| CPU time | 346.59 seconds |
| Started | May 05 01:25:50 PM PDT 24 |
| Finished | May 05 01:31:37 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-4c69a9f7-deb8-43dd-ab43-cca6798f0de9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441581659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all. 441581659 |
| Directory | /workspace/46.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3030498846 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 209028685088 ps |
| CPU time | 373.09 seconds |
| Started | May 05 01:25:49 PM PDT 24 |
| Finished | May 05 01:32:03 PM PDT 24 |
| Peak memory | 183024 kb |
| Host | smart-cc02dd2c-4565-4481-9c54-f27163e9cfc7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030498846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.3030498846 |
| Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/47.rv_timer_disabled.2336565753 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 28525546386 ps |
| CPU time | 10.89 seconds |
| Started | May 05 01:25:51 PM PDT 24 |
| Finished | May 05 01:26:02 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-070fea9b-fe99-4571-afc4-ad03f1a6b19c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336565753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2336565753 |
| Directory | /workspace/47.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random.4134583475 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 289898302178 ps |
| CPU time | 118.26 seconds |
| Started | May 05 01:25:47 PM PDT 24 |
| Finished | May 05 01:27:46 PM PDT 24 |
| Peak memory | 191200 kb |
| Host | smart-706ed125-d02a-4e98-a336-1eb60f830a93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134583475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4134583475 |
| Directory | /workspace/47.rv_timer_random/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random_reset.1744325906 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 50852154478 ps |
| CPU time | 75.9 seconds |
| Started | May 05 01:25:51 PM PDT 24 |
| Finished | May 05 01:27:07 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-ac941575-dbdd-407e-9a51-36943a7c33b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744325906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1744325906 |
| Directory | /workspace/47.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.640210726 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 327736214195 ps |
| CPU time | 538.57 seconds |
| Started | May 05 01:25:57 PM PDT 24 |
| Finished | May 05 01:34:56 PM PDT 24 |
| Peak memory | 182932 kb |
| Host | smart-d6315b8d-ff5b-4f83-8b2e-f6d02d52eab3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640210726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.rv_timer_cfg_update_on_fly.640210726 |
| Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/48.rv_timer_disabled.808319708 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 505249477559 ps |
| CPU time | 255.79 seconds |
| Started | May 05 01:25:55 PM PDT 24 |
| Finished | May 05 01:30:11 PM PDT 24 |
| Peak memory | 183004 kb |
| Host | smart-a281c730-a962-422b-b834-29c7de01310d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808319708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.808319708 |
| Directory | /workspace/48.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random.1391608254 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 31607436035 ps |
| CPU time | 49.49 seconds |
| Started | May 05 01:25:58 PM PDT 24 |
| Finished | May 05 01:26:47 PM PDT 24 |
| Peak memory | 194892 kb |
| Host | smart-45ca3c14-eca4-4eb5-9405-fb469c288e05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391608254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1391608254 |
| Directory | /workspace/48.rv_timer_random/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random_reset.969685212 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 397189325 ps |
| CPU time | 0.9 seconds |
| Started | May 05 01:25:57 PM PDT 24 |
| Finished | May 05 01:25:58 PM PDT 24 |
| Peak memory | 191468 kb |
| Host | smart-f57c69a9-0144-46a3-8272-8fde9f0c90f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=969685212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.969685212 |
| Directory | /workspace/48.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3981892518 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 54409691323 ps |
| CPU time | 83.73 seconds |
| Started | May 05 01:25:56 PM PDT 24 |
| Finished | May 05 01:27:20 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-617a0234-244a-4cc2-8fa4-dbf7ca10dc62 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981892518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3981892518 |
| Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/49.rv_timer_disabled.1915010511 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 65665707063 ps |
| CPU time | 103.85 seconds |
| Started | May 05 01:25:57 PM PDT 24 |
| Finished | May 05 01:27:41 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-8f59a0b5-1321-4328-a4f4-fdf992f054ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915010511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1915010511 |
| Directory | /workspace/49.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random.3406700034 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 27257219855 ps |
| CPU time | 41.2 seconds |
| Started | May 05 01:25:56 PM PDT 24 |
| Finished | May 05 01:26:38 PM PDT 24 |
| Peak memory | 182844 kb |
| Host | smart-3b8a8202-40f6-4276-9292-62db588b4e32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406700034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3406700034 |
| Directory | /workspace/49.rv_timer_random/latest |
| Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.136084289 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 563160767437 ps |
| CPU time | 468.24 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:32:19 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-16ad5fe5-574b-414d-8063-f0f8320555e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136084289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .rv_timer_cfg_update_on_fly.136084289 |
| Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/5.rv_timer_disabled.3455523954 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 448034714909 ps |
| CPU time | 114.88 seconds |
| Started | May 05 01:24:33 PM PDT 24 |
| Finished | May 05 01:26:28 PM PDT 24 |
| Peak memory | 182972 kb |
| Host | smart-2496d5f5-45ac-4f46-9c64-31126c6d19e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455523954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3455523954 |
| Directory | /workspace/5.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random_reset.3249181285 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 27767557367 ps |
| CPU time | 53.32 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:25:24 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-0e170af9-2974-4a66-9c7e-7eae61c097c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249181285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3249181285 |
| Directory | /workspace/5.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/50.rv_timer_random.1467529171 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 150444937124 ps |
| CPU time | 145.33 seconds |
| Started | May 05 01:26:02 PM PDT 24 |
| Finished | May 05 01:28:27 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-16fb6657-6f95-4fad-a31c-74925164fde3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467529171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1467529171 |
| Directory | /workspace/50.rv_timer_random/latest |
| Test location | /workspace/coverage/default/51.rv_timer_random.4036792234 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 352787362310 ps |
| CPU time | 222.56 seconds |
| Started | May 05 01:26:02 PM PDT 24 |
| Finished | May 05 01:29:45 PM PDT 24 |
| Peak memory | 191104 kb |
| Host | smart-51f7b287-8022-41b9-bc8a-dcde208c83cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036792234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4036792234 |
| Directory | /workspace/51.rv_timer_random/latest |
| Test location | /workspace/coverage/default/52.rv_timer_random.23766168 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 896742609836 ps |
| CPU time | 537.53 seconds |
| Started | May 05 01:26:03 PM PDT 24 |
| Finished | May 05 01:35:01 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-a89f8fb7-73a5-41a7-98ec-30265eb80544 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23766168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.23766168 |
| Directory | /workspace/52.rv_timer_random/latest |
| Test location | /workspace/coverage/default/54.rv_timer_random.1309466637 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 59026690073 ps |
| CPU time | 163.75 seconds |
| Started | May 05 01:26:05 PM PDT 24 |
| Finished | May 05 01:28:49 PM PDT 24 |
| Peak memory | 192160 kb |
| Host | smart-c08e6946-c9dc-434b-a1f6-21729b7e41aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309466637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1309466637 |
| Directory | /workspace/54.rv_timer_random/latest |
| Test location | /workspace/coverage/default/55.rv_timer_random.4013491615 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 129352535848 ps |
| CPU time | 312.79 seconds |
| Started | May 05 01:26:06 PM PDT 24 |
| Finished | May 05 01:31:19 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-099d3847-8c0a-4164-ac75-c569605e34bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013491615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4013491615 |
| Directory | /workspace/55.rv_timer_random/latest |
| Test location | /workspace/coverage/default/57.rv_timer_random.37871733 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 18588187432 ps |
| CPU time | 35.17 seconds |
| Started | May 05 01:26:06 PM PDT 24 |
| Finished | May 05 01:26:42 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-fbf4aab5-9520-4b7a-8093-44e7f9c4b0de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37871733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.37871733 |
| Directory | /workspace/57.rv_timer_random/latest |
| Test location | /workspace/coverage/default/58.rv_timer_random.645704208 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 246714740887 ps |
| CPU time | 223.59 seconds |
| Started | May 05 01:26:07 PM PDT 24 |
| Finished | May 05 01:29:51 PM PDT 24 |
| Peak memory | 193984 kb |
| Host | smart-31b83ccf-3bba-4117-ab60-ab50a519ae99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645704208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.645704208 |
| Directory | /workspace/58.rv_timer_random/latest |
| Test location | /workspace/coverage/default/59.rv_timer_random.1068031646 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 422309099594 ps |
| CPU time | 736.54 seconds |
| Started | May 05 01:26:06 PM PDT 24 |
| Finished | May 05 01:38:23 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-8b3c5cf6-301c-4eee-a0a3-a73f030200f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068031646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1068031646 |
| Directory | /workspace/59.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3783157593 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 481450367023 ps |
| CPU time | 238.64 seconds |
| Started | May 05 01:24:28 PM PDT 24 |
| Finished | May 05 01:28:27 PM PDT 24 |
| Peak memory | 182936 kb |
| Host | smart-563a8c45-d192-4bb2-8c3a-560071154f1f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783157593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.3783157593 |
| Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/6.rv_timer_disabled.3993350962 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 859911306186 ps |
| CPU time | 358.24 seconds |
| Started | May 05 01:24:28 PM PDT 24 |
| Finished | May 05 01:30:27 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-bfd6dcb3-ec0c-4457-b835-ed41dc4c89ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993350962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3993350962 |
| Directory | /workspace/6.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random.1006806636 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1304169671645 ps |
| CPU time | 643.29 seconds |
| Started | May 05 01:24:32 PM PDT 24 |
| Finished | May 05 01:35:16 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-f6959b5c-e1f0-49cd-aae6-c8614041a4f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006806636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1006806636 |
| Directory | /workspace/6.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random_reset.4243593037 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 252287465 ps |
| CPU time | 0.88 seconds |
| Started | May 05 01:24:28 PM PDT 24 |
| Finished | May 05 01:24:29 PM PDT 24 |
| Peak memory | 182764 kb |
| Host | smart-25c87ab0-760d-49c4-bb45-30839b3967fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243593037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4243593037 |
| Directory | /workspace/6.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all.121295849 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 51062640 ps |
| CPU time | 0.56 seconds |
| Started | May 05 01:24:34 PM PDT 24 |
| Finished | May 05 01:24:35 PM PDT 24 |
| Peak memory | 182776 kb |
| Host | smart-215546d6-923c-4eb2-beba-937e7f0e6ea7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121295849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.121295849 |
| Directory | /workspace/6.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/60.rv_timer_random.2987235057 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 605068490576 ps |
| CPU time | 225.91 seconds |
| Started | May 05 01:26:11 PM PDT 24 |
| Finished | May 05 01:29:57 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-bb916e95-b0f0-4019-a4b9-5ed6e0f1ce01 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987235057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2987235057 |
| Directory | /workspace/60.rv_timer_random/latest |
| Test location | /workspace/coverage/default/62.rv_timer_random.3899592233 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 591658327098 ps |
| CPU time | 275.84 seconds |
| Started | May 05 01:26:10 PM PDT 24 |
| Finished | May 05 01:30:46 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-b5d1cf9f-0bd0-4cd1-8ed7-c91496d7131e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899592233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3899592233 |
| Directory | /workspace/62.rv_timer_random/latest |
| Test location | /workspace/coverage/default/65.rv_timer_random.404519948 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 167479680026 ps |
| CPU time | 312.2 seconds |
| Started | May 05 01:26:13 PM PDT 24 |
| Finished | May 05 01:31:26 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-69e48d97-3086-4ce8-a41a-496ae0f1e4f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404519948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.404519948 |
| Directory | /workspace/65.rv_timer_random/latest |
| Test location | /workspace/coverage/default/66.rv_timer_random.247830747 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 173240888215 ps |
| CPU time | 284.75 seconds |
| Started | May 05 01:26:11 PM PDT 24 |
| Finished | May 05 01:30:56 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-3ca8030d-425b-4d14-bd8d-ba9ad4707107 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247830747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.247830747 |
| Directory | /workspace/66.rv_timer_random/latest |
| Test location | /workspace/coverage/default/67.rv_timer_random.3236205201 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 103290587878 ps |
| CPU time | 156.78 seconds |
| Started | May 05 01:26:12 PM PDT 24 |
| Finished | May 05 01:28:49 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-183511af-c462-4070-8196-c41abf2082c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236205201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3236205201 |
| Directory | /workspace/67.rv_timer_random/latest |
| Test location | /workspace/coverage/default/68.rv_timer_random.4038530244 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 152441893197 ps |
| CPU time | 186.99 seconds |
| Started | May 05 01:26:13 PM PDT 24 |
| Finished | May 05 01:29:20 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-17afc3e5-f835-48ad-b3f1-1b24509b9fc8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038530244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4038530244 |
| Directory | /workspace/68.rv_timer_random/latest |
| Test location | /workspace/coverage/default/69.rv_timer_random.635030354 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 157813371113 ps |
| CPU time | 57.77 seconds |
| Started | May 05 01:26:18 PM PDT 24 |
| Finished | May 05 01:27:16 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-5325ea09-008b-4e0a-88ca-bbf6700de14b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635030354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.635030354 |
| Directory | /workspace/69.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1441477425 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1321713586294 ps |
| CPU time | 508.67 seconds |
| Started | May 05 01:24:37 PM PDT 24 |
| Finished | May 05 01:33:06 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-de2390cf-9234-4b61-afb6-384400a5658a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441477425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.1441477425 |
| Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_disabled.2208513035 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 36643635215 ps |
| CPU time | 59.63 seconds |
| Started | May 05 01:24:29 PM PDT 24 |
| Finished | May 05 01:25:30 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-586d3333-ffc4-4ffc-81b3-fb3fbd1d9ffb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2208513035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2208513035 |
| Directory | /workspace/7.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random.2802299788 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 475649559685 ps |
| CPU time | 318.55 seconds |
| Started | May 05 01:24:29 PM PDT 24 |
| Finished | May 05 01:29:49 PM PDT 24 |
| Peak memory | 191212 kb |
| Host | smart-4ed23875-4b53-44d0-9d29-7c146a456065 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802299788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2802299788 |
| Directory | /workspace/7.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random_reset.1898995823 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 38203660867 ps |
| CPU time | 85.87 seconds |
| Started | May 05 01:24:35 PM PDT 24 |
| Finished | May 05 01:26:01 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-d5190060-bc50-444e-b422-cd68f046dd5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898995823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1898995823 |
| Directory | /workspace/7.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all.2675473357 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 202474263935 ps |
| CPU time | 963.24 seconds |
| Started | May 05 01:24:30 PM PDT 24 |
| Finished | May 05 01:40:34 PM PDT 24 |
| Peak memory | 191188 kb |
| Host | smart-9568b05a-7489-43ce-878f-6ea18dd3b5db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675473357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all. 2675473357 |
| Directory | /workspace/7.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/70.rv_timer_random.3753800141 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 487881419640 ps |
| CPU time | 1604.24 seconds |
| Started | May 05 01:26:16 PM PDT 24 |
| Finished | May 05 01:53:01 PM PDT 24 |
| Peak memory | 191240 kb |
| Host | smart-1efaa5cd-140b-4ca2-a549-c8d64b98a9cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753800141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3753800141 |
| Directory | /workspace/70.rv_timer_random/latest |
| Test location | /workspace/coverage/default/71.rv_timer_random.2670080093 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 206715173445 ps |
| CPU time | 55.3 seconds |
| Started | May 05 01:26:18 PM PDT 24 |
| Finished | May 05 01:27:14 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-80c51130-2f6d-4796-b131-49072bc41d02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670080093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2670080093 |
| Directory | /workspace/71.rv_timer_random/latest |
| Test location | /workspace/coverage/default/72.rv_timer_random.1058648433 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 62263356936 ps |
| CPU time | 190.74 seconds |
| Started | May 05 01:26:16 PM PDT 24 |
| Finished | May 05 01:29:27 PM PDT 24 |
| Peak memory | 182904 kb |
| Host | smart-df1b7b0e-f6bb-4355-933f-a954ba5aaf43 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058648433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1058648433 |
| Directory | /workspace/72.rv_timer_random/latest |
| Test location | /workspace/coverage/default/73.rv_timer_random.1663340960 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 128215926219 ps |
| CPU time | 48.76 seconds |
| Started | May 05 01:26:23 PM PDT 24 |
| Finished | May 05 01:27:12 PM PDT 24 |
| Peak memory | 191200 kb |
| Host | smart-5055bc84-1ca2-4abf-949c-8caacfe1e3ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663340960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1663340960 |
| Directory | /workspace/73.rv_timer_random/latest |
| Test location | /workspace/coverage/default/74.rv_timer_random.204144138 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 152137627617 ps |
| CPU time | 70.27 seconds |
| Started | May 05 01:26:22 PM PDT 24 |
| Finished | May 05 01:27:32 PM PDT 24 |
| Peak memory | 194792 kb |
| Host | smart-2ca86b68-5100-4825-8223-a87ed3ce6a6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204144138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.204144138 |
| Directory | /workspace/74.rv_timer_random/latest |
| Test location | /workspace/coverage/default/75.rv_timer_random.180428791 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 59340203634 ps |
| CPU time | 343.5 seconds |
| Started | May 05 01:26:23 PM PDT 24 |
| Finished | May 05 01:32:07 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-eeebf25e-7cff-4c0d-8195-55b460de505f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180428791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.180428791 |
| Directory | /workspace/75.rv_timer_random/latest |
| Test location | /workspace/coverage/default/76.rv_timer_random.136942472 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 716339415827 ps |
| CPU time | 636.38 seconds |
| Started | May 05 01:26:25 PM PDT 24 |
| Finished | May 05 01:37:02 PM PDT 24 |
| Peak memory | 191128 kb |
| Host | smart-b8efab46-e7fe-429f-aba6-b949d6a6a5b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136942472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.136942472 |
| Directory | /workspace/76.rv_timer_random/latest |
| Test location | /workspace/coverage/default/77.rv_timer_random.1522673898 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 744924591580 ps |
| CPU time | 503 seconds |
| Started | May 05 01:26:26 PM PDT 24 |
| Finished | May 05 01:34:49 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-6805818e-e296-4b15-8d44-7807f23184db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522673898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1522673898 |
| Directory | /workspace/77.rv_timer_random/latest |
| Test location | /workspace/coverage/default/78.rv_timer_random.3128382761 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 124895460512 ps |
| CPU time | 604.38 seconds |
| Started | May 05 01:26:25 PM PDT 24 |
| Finished | May 05 01:36:30 PM PDT 24 |
| Peak memory | 191408 kb |
| Host | smart-e4ae1c88-5351-49b0-94c1-bf63e46f3c0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128382761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3128382761 |
| Directory | /workspace/78.rv_timer_random/latest |
| Test location | /workspace/coverage/default/79.rv_timer_random.984776601 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 151434037537 ps |
| CPU time | 414.37 seconds |
| Started | May 05 01:26:25 PM PDT 24 |
| Finished | May 05 01:33:20 PM PDT 24 |
| Peak memory | 191132 kb |
| Host | smart-ca57a04e-f312-462b-afe3-7e4234c998b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984776601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.984776601 |
| Directory | /workspace/79.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.416685512 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 21057787214 ps |
| CPU time | 36.56 seconds |
| Started | May 05 01:24:38 PM PDT 24 |
| Finished | May 05 01:25:15 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-267fed45-8050-450d-885a-f1526799b4bd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416685512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .rv_timer_cfg_update_on_fly.416685512 |
| Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/8.rv_timer_disabled.2090462899 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 346968952873 ps |
| CPU time | 114.45 seconds |
| Started | May 05 01:24:37 PM PDT 24 |
| Finished | May 05 01:26:32 PM PDT 24 |
| Peak memory | 183000 kb |
| Host | smart-c78ac9ad-4be3-4f97-a4d8-933dd4d17302 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2090462899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2090462899 |
| Directory | /workspace/8.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random.2691689416 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 432411070322 ps |
| CPU time | 1616.49 seconds |
| Started | May 05 01:24:33 PM PDT 24 |
| Finished | May 05 01:51:30 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-31d09319-34be-45e9-a71b-22c1ebc48530 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691689416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2691689416 |
| Directory | /workspace/8.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random_reset.1282171129 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 306968347 ps |
| CPU time | 0.66 seconds |
| Started | May 05 01:24:34 PM PDT 24 |
| Finished | May 05 01:24:35 PM PDT 24 |
| Peak memory | 182772 kb |
| Host | smart-fcec6034-6a6a-487b-885a-709ad2b6379f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1282171129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1282171129 |
| Directory | /workspace/8.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/80.rv_timer_random.2643603298 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1197561956114 ps |
| CPU time | 516.55 seconds |
| Started | May 05 01:26:25 PM PDT 24 |
| Finished | May 05 01:35:02 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-dc5cd951-2986-48f2-b6a1-c1515b4f685a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643603298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2643603298 |
| Directory | /workspace/80.rv_timer_random/latest |
| Test location | /workspace/coverage/default/81.rv_timer_random.182076754 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 105920736864 ps |
| CPU time | 202.17 seconds |
| Started | May 05 01:26:25 PM PDT 24 |
| Finished | May 05 01:29:48 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-3d1799ca-2cd1-4470-9ef6-f0b47dad2231 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182076754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.182076754 |
| Directory | /workspace/81.rv_timer_random/latest |
| Test location | /workspace/coverage/default/82.rv_timer_random.2217870604 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 136627269607 ps |
| CPU time | 261.15 seconds |
| Started | May 05 01:26:26 PM PDT 24 |
| Finished | May 05 01:30:47 PM PDT 24 |
| Peak memory | 191196 kb |
| Host | smart-9abc938f-0f58-4f3d-b91d-e7de3a6e6e3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217870604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2217870604 |
| Directory | /workspace/82.rv_timer_random/latest |
| Test location | /workspace/coverage/default/83.rv_timer_random.582434522 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 652752990172 ps |
| CPU time | 484.28 seconds |
| Started | May 05 01:26:25 PM PDT 24 |
| Finished | May 05 01:34:30 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-b5888d63-042e-4452-9068-75caeac576e7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582434522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.582434522 |
| Directory | /workspace/83.rv_timer_random/latest |
| Test location | /workspace/coverage/default/85.rv_timer_random.1904696722 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 648395085868 ps |
| CPU time | 168.38 seconds |
| Started | May 05 01:26:34 PM PDT 24 |
| Finished | May 05 01:29:23 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-44910140-983e-4534-bd56-f512e38be26c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904696722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1904696722 |
| Directory | /workspace/85.rv_timer_random/latest |
| Test location | /workspace/coverage/default/86.rv_timer_random.3563013579 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 140508868021 ps |
| CPU time | 651.51 seconds |
| Started | May 05 01:26:33 PM PDT 24 |
| Finished | May 05 01:37:25 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-8dba6e79-d95c-4d0b-ab4d-418b811ea0b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563013579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3563013579 |
| Directory | /workspace/86.rv_timer_random/latest |
| Test location | /workspace/coverage/default/87.rv_timer_random.2024748599 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 523804396390 ps |
| CPU time | 580.16 seconds |
| Started | May 05 01:26:31 PM PDT 24 |
| Finished | May 05 01:36:12 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-359d308a-d8de-4b14-ba9d-6235cc1cf576 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024748599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2024748599 |
| Directory | /workspace/87.rv_timer_random/latest |
| Test location | /workspace/coverage/default/88.rv_timer_random.366918663 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 67817580599 ps |
| CPU time | 119.99 seconds |
| Started | May 05 01:26:32 PM PDT 24 |
| Finished | May 05 01:28:32 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-19f1a494-ba90-441b-a304-645d66ba9b80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366918663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.366918663 |
| Directory | /workspace/88.rv_timer_random/latest |
| Test location | /workspace/coverage/default/89.rv_timer_random.72365101 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 21907596940 ps |
| CPU time | 220.23 seconds |
| Started | May 05 01:26:31 PM PDT 24 |
| Finished | May 05 01:30:12 PM PDT 24 |
| Peak memory | 182936 kb |
| Host | smart-c653c5cb-4c3f-4c04-a705-c768187dc55b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72365101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.72365101 |
| Directory | /workspace/89.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.390405283 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 303456037132 ps |
| CPU time | 309.24 seconds |
| Started | May 05 01:24:34 PM PDT 24 |
| Finished | May 05 01:29:44 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-8f40adac-507c-4884-a708-bb9fa9775c79 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390405283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .rv_timer_cfg_update_on_fly.390405283 |
| Directory | /workspace/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/9.rv_timer_disabled.2640633050 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 82104901480 ps |
| CPU time | 36.49 seconds |
| Started | May 05 01:24:35 PM PDT 24 |
| Finished | May 05 01:25:12 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-b42e5531-fcc2-423c-87f3-b538911742e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640633050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2640633050 |
| Directory | /workspace/9.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random.718695020 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 44945840289 ps |
| CPU time | 40.15 seconds |
| Started | May 05 01:24:33 PM PDT 24 |
| Finished | May 05 01:25:14 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-7446885d-4535-4b03-84d1-64e7197359ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718695020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.718695020 |
| Directory | /workspace/9.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random_reset.839458727 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 99668138 ps |
| CPU time | 1.58 seconds |
| Started | May 05 01:24:39 PM PDT 24 |
| Finished | May 05 01:24:41 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-140591c6-55b2-427b-8d30-b9181ea8cbe3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839458727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.839458727 |
| Directory | /workspace/9.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all.1320590490 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 282885743351 ps |
| CPU time | 192.02 seconds |
| Started | May 05 01:24:36 PM PDT 24 |
| Finished | May 05 01:27:48 PM PDT 24 |
| Peak memory | 191104 kb |
| Host | smart-5f40013c-971b-441f-9404-883cda8eb37c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320590490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 1320590490 |
| Directory | /workspace/9.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/91.rv_timer_random.1430265743 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 123025117830 ps |
| CPU time | 238.26 seconds |
| Started | May 05 01:26:35 PM PDT 24 |
| Finished | May 05 01:30:34 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-f6bb08c8-b3b2-480b-8fcc-303e24a29bcc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430265743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1430265743 |
| Directory | /workspace/91.rv_timer_random/latest |
| Test location | /workspace/coverage/default/93.rv_timer_random.2732842074 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1172610669610 ps |
| CPU time | 1507.49 seconds |
| Started | May 05 01:26:37 PM PDT 24 |
| Finished | May 05 01:51:45 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-fb9e78cd-bdc1-4751-902c-3e5738d91315 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732842074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2732842074 |
| Directory | /workspace/93.rv_timer_random/latest |
| Test location | /workspace/coverage/default/94.rv_timer_random.2854504123 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 135498095975 ps |
| CPU time | 501.22 seconds |
| Started | May 05 01:26:35 PM PDT 24 |
| Finished | May 05 01:34:57 PM PDT 24 |
| Peak memory | 191204 kb |
| Host | smart-5cead5d9-f54c-4307-8271-c16e27478448 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854504123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2854504123 |
| Directory | /workspace/94.rv_timer_random/latest |
| Test location | /workspace/coverage/default/95.rv_timer_random.1745118232 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 46263943335 ps |
| CPU time | 20.56 seconds |
| Started | May 05 01:26:36 PM PDT 24 |
| Finished | May 05 01:26:57 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-202b2cd0-2c49-4cd4-a534-5473a29079ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745118232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1745118232 |
| Directory | /workspace/95.rv_timer_random/latest |
| Test location | /workspace/coverage/default/98.rv_timer_random.3412273202 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 165314970352 ps |
| CPU time | 435.2 seconds |
| Started | May 05 01:26:36 PM PDT 24 |
| Finished | May 05 01:33:51 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-bb1fd583-6273-4081-806b-d1a5f84cb5fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412273202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3412273202 |
| Directory | /workspace/98.rv_timer_random/latest |
| Test location | /workspace/coverage/default/99.rv_timer_random.1730786994 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 10625487613 ps |
| CPU time | 50.69 seconds |
| Started | May 05 01:26:34 PM PDT 24 |
| Finished | May 05 01:27:25 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-160ba28a-9b49-40a1-b9f0-883520dd6322 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730786994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1730786994 |
| Directory | /workspace/99.rv_timer_random/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |