Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
118897067 |
1 |
|
T1 |
3001 |
|
T2 |
213822 |
|
T3 |
123419 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
66283992 |
1 |
|
T1 |
2653 |
|
T2 |
204836 |
|
T3 |
123419 |
auto[1] |
52613075 |
1 |
|
T1 |
348 |
|
T2 |
89858 |
|
T4 |
34603 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
118890884 |
1 |
|
T1 |
2997 |
|
T2 |
213821 |
|
T3 |
123411 |
auto[1] |
6183 |
1 |
|
T1 |
4 |
|
T2 |
9 |
|
T3 |
8 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
66280893 |
1 |
|
T1 |
2651 |
|
T2 |
204836 |
|
T3 |
123411 |
all_values[0] |
auto[0] |
auto[1] |
3099 |
1 |
|
T1 |
2 |
|
T2 |
5 |
|
T3 |
8 |
all_values[0] |
auto[1] |
auto[0] |
52609991 |
1 |
|
T1 |
346 |
|
T2 |
89854 |
|
T4 |
34598 |
all_values[0] |
auto[1] |
auto[1] |
3084 |
1 |
|
T1 |
2 |
|
T2 |
4 |
|
T4 |
5 |