Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 586
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2742531057 May 07 03:01:57 PM PDT 24 May 07 03:02:00 PM PDT 24 103344991 ps
T510 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.443131213 May 07 03:01:53 PM PDT 24 May 07 03:01:56 PM PDT 24 159229216 ps
T511 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4167376239 May 07 03:01:44 PM PDT 24 May 07 03:01:48 PM PDT 24 142391631 ps
T512 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3606782045 May 07 03:01:50 PM PDT 24 May 07 03:01:52 PM PDT 24 203674856 ps
T513 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4167621074 May 07 03:02:11 PM PDT 24 May 07 03:02:13 PM PDT 24 21443243 ps
T514 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1513435055 May 07 03:02:02 PM PDT 24 May 07 03:02:05 PM PDT 24 28398852 ps
T99 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3882852710 May 07 03:01:48 PM PDT 24 May 07 03:01:50 PM PDT 24 34406814 ps
T515 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2802080075 May 07 03:02:06 PM PDT 24 May 07 03:02:10 PM PDT 24 610741265 ps
T516 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.903999243 May 07 03:02:12 PM PDT 24 May 07 03:02:14 PM PDT 24 12629365 ps
T517 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3584078572 May 07 03:01:54 PM PDT 24 May 07 03:01:57 PM PDT 24 113084753 ps
T100 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1406838443 May 07 03:01:46 PM PDT 24 May 07 03:01:49 PM PDT 24 19417465 ps
T518 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4218556607 May 07 03:02:01 PM PDT 24 May 07 03:02:04 PM PDT 24 27594595 ps
T519 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3706791650 May 07 03:01:56 PM PDT 24 May 07 03:02:01 PM PDT 24 115438903 ps
T520 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1099117306 May 07 03:01:49 PM PDT 24 May 07 03:01:52 PM PDT 24 106375969 ps
T101 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1952635687 May 07 03:01:55 PM PDT 24 May 07 03:01:58 PM PDT 24 16782533 ps
T521 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3650892125 May 07 03:02:13 PM PDT 24 May 07 03:02:16 PM PDT 24 18076076 ps
T522 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.567412838 May 07 03:02:09 PM PDT 24 May 07 03:02:12 PM PDT 24 158493190 ps
T523 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1589192070 May 07 03:02:10 PM PDT 24 May 07 03:02:12 PM PDT 24 158430494 ps
T524 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3834964790 May 07 03:02:00 PM PDT 24 May 07 03:02:03 PM PDT 24 49253611 ps
T525 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.616986173 May 07 03:01:54 PM PDT 24 May 07 03:01:56 PM PDT 24 81445744 ps
T526 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1347215744 May 07 03:01:47 PM PDT 24 May 07 03:01:49 PM PDT 24 19393073 ps
T527 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.457832897 May 07 03:01:45 PM PDT 24 May 07 03:01:48 PM PDT 24 11923307 ps
T111 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3062477569 May 07 03:01:41 PM PDT 24 May 07 03:01:46 PM PDT 24 344766004 ps
T127 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2381912792 May 07 03:02:00 PM PDT 24 May 07 03:02:03 PM PDT 24 189789282 ps
T528 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3626233454 May 07 03:01:47 PM PDT 24 May 07 03:01:49 PM PDT 24 91520242 ps
T529 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3353336862 May 07 03:01:50 PM PDT 24 May 07 03:01:52 PM PDT 24 69550483 ps
T530 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3765716037 May 07 03:01:53 PM PDT 24 May 07 03:01:55 PM PDT 24 14211739 ps
T531 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1578464416 May 07 03:01:52 PM PDT 24 May 07 03:01:54 PM PDT 24 62509181 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.728450989 May 07 03:01:51 PM PDT 24 May 07 03:01:53 PM PDT 24 127657804 ps
T533 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1955129598 May 07 03:01:55 PM PDT 24 May 07 03:01:58 PM PDT 24 18258195 ps
T534 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2711909736 May 07 03:01:43 PM PDT 24 May 07 03:01:45 PM PDT 24 26324976 ps
T535 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3770533963 May 07 03:01:53 PM PDT 24 May 07 03:01:55 PM PDT 24 23330656 ps
T536 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1220297977 May 07 03:02:02 PM PDT 24 May 07 03:02:04 PM PDT 24 22437320 ps
T537 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2395853057 May 07 03:02:06 PM PDT 24 May 07 03:02:08 PM PDT 24 115796427 ps
T538 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1132979832 May 07 03:02:13 PM PDT 24 May 07 03:02:15 PM PDT 24 18177339 ps
T539 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1082581213 May 07 03:02:07 PM PDT 24 May 07 03:02:09 PM PDT 24 35938504 ps
T540 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4123300437 May 07 03:02:03 PM PDT 24 May 07 03:02:05 PM PDT 24 56736913 ps
T541 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1690179512 May 07 03:01:51 PM PDT 24 May 07 03:01:56 PM PDT 24 358116401 ps
T542 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3825682934 May 07 03:02:06 PM PDT 24 May 07 03:02:08 PM PDT 24 13114680 ps
T543 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3330969142 May 07 03:02:08 PM PDT 24 May 07 03:02:11 PM PDT 24 12233809 ps
T544 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1111844685 May 07 03:01:51 PM PDT 24 May 07 03:01:55 PM PDT 24 468634588 ps
T545 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3807178126 May 07 03:01:45 PM PDT 24 May 07 03:01:48 PM PDT 24 189676533 ps
T546 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3792937280 May 07 03:02:17 PM PDT 24 May 07 03:02:19 PM PDT 24 39358159 ps
T547 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1987022567 May 07 03:01:46 PM PDT 24 May 07 03:01:50 PM PDT 24 194322423 ps
T112 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.543541905 May 07 03:01:54 PM PDT 24 May 07 03:01:57 PM PDT 24 12774007 ps
T548 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2572200259 May 07 03:02:10 PM PDT 24 May 07 03:02:12 PM PDT 24 85235711 ps
T549 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.810816268 May 07 03:02:15 PM PDT 24 May 07 03:02:18 PM PDT 24 16304975 ps
T550 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2189631465 May 07 03:01:56 PM PDT 24 May 07 03:02:00 PM PDT 24 73708755 ps
T551 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.861303913 May 07 03:02:12 PM PDT 24 May 07 03:02:14 PM PDT 24 32257590 ps
T552 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2898335296 May 07 03:02:14 PM PDT 24 May 07 03:02:16 PM PDT 24 101246581 ps
T553 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1798658231 May 07 03:02:15 PM PDT 24 May 07 03:02:17 PM PDT 24 31108139 ps
T554 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2864662468 May 07 03:02:14 PM PDT 24 May 07 03:02:16 PM PDT 24 25512141 ps
T555 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1552788434 May 07 03:02:09 PM PDT 24 May 07 03:02:11 PM PDT 24 23287164 ps
T556 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1703700175 May 07 03:01:50 PM PDT 24 May 07 03:01:52 PM PDT 24 13622594 ps
T557 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.192072735 May 07 03:01:53 PM PDT 24 May 07 03:01:55 PM PDT 24 95005094 ps
T558 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3534454021 May 07 03:01:53 PM PDT 24 May 07 03:01:55 PM PDT 24 46179813 ps
T559 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2328865761 May 07 03:02:08 PM PDT 24 May 07 03:02:12 PM PDT 24 335665898 ps
T560 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3942303519 May 07 03:01:51 PM PDT 24 May 07 03:01:54 PM PDT 24 104412209 ps
T561 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2201423760 May 07 03:01:56 PM PDT 24 May 07 03:01:59 PM PDT 24 43453816 ps
T562 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.80021591 May 07 03:01:49 PM PDT 24 May 07 03:01:52 PM PDT 24 167733655 ps
T563 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2032603956 May 07 03:02:13 PM PDT 24 May 07 03:02:15 PM PDT 24 16254222 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2238430728 May 07 03:01:49 PM PDT 24 May 07 03:01:50 PM PDT 24 23192740 ps
T565 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.736340674 May 07 03:02:15 PM PDT 24 May 07 03:02:17 PM PDT 24 13361692 ps
T566 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1369478907 May 07 03:02:14 PM PDT 24 May 07 03:02:17 PM PDT 24 24546775 ps
T567 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1795229693 May 07 03:01:56 PM PDT 24 May 07 03:02:00 PM PDT 24 132882946 ps
T568 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1653461603 May 07 03:01:51 PM PDT 24 May 07 03:01:53 PM PDT 24 18177547 ps
T569 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.477559609 May 07 03:01:54 PM PDT 24 May 07 03:01:56 PM PDT 24 51317453 ps
T570 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4224639561 May 07 03:01:54 PM PDT 24 May 07 03:01:56 PM PDT 24 14176292 ps
T571 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1062068807 May 07 03:01:52 PM PDT 24 May 07 03:01:54 PM PDT 24 24775856 ps
T572 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2800515306 May 07 03:01:44 PM PDT 24 May 07 03:01:46 PM PDT 24 13240347 ps
T573 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4138451472 May 07 03:01:51 PM PDT 24 May 07 03:01:54 PM PDT 24 101074913 ps
T574 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.501127410 May 07 03:01:55 PM PDT 24 May 07 03:02:00 PM PDT 24 1164528620 ps
T575 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.902005292 May 07 03:01:48 PM PDT 24 May 07 03:01:51 PM PDT 24 79940376 ps
T576 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3710997167 May 07 03:02:14 PM PDT 24 May 07 03:02:17 PM PDT 24 141402442 ps
T577 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4052089256 May 07 03:02:13 PM PDT 24 May 07 03:02:15 PM PDT 24 119882232 ps
T578 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3394512121 May 07 03:01:59 PM PDT 24 May 07 03:02:03 PM PDT 24 77202033 ps
T113 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3118277156 May 07 03:01:41 PM PDT 24 May 07 03:01:43 PM PDT 24 83501221 ps
T579 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2418946531 May 07 03:01:56 PM PDT 24 May 07 03:02:00 PM PDT 24 60523255 ps
T580 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3522888677 May 07 03:01:49 PM PDT 24 May 07 03:01:51 PM PDT 24 44756335 ps
T581 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3364905063 May 07 03:01:54 PM PDT 24 May 07 03:01:56 PM PDT 24 15225703 ps
T582 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3696294275 May 07 03:01:46 PM PDT 24 May 07 03:01:48 PM PDT 24 102033295 ps
T583 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.96120325 May 07 03:02:08 PM PDT 24 May 07 03:02:10 PM PDT 24 141766429 ps
T114 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4065043622 May 07 03:01:53 PM PDT 24 May 07 03:01:55 PM PDT 24 688298372 ps
T584 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2902784066 May 07 03:02:08 PM PDT 24 May 07 03:02:10 PM PDT 24 19428133 ps
T585 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.514213114 May 07 03:01:46 PM PDT 24 May 07 03:01:48 PM PDT 24 20888432 ps
T586 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2752444410 May 07 03:02:09 PM PDT 24 May 07 03:02:11 PM PDT 24 37383841 ps

Test location /workspace/coverage/default/58.rv_timer_random.2416335306
Short name T1
Test name
Test status
Simulation time 10425245659 ps
CPU time 12.09 seconds
Started May 07 01:08:37 PM PDT 24
Finished May 07 01:08:50 PM PDT 24
Peak memory 191252 kb
Host smart-638b60de-c998-461b-a54c-7b27a29385ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416335306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2416335306
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3423136568
Short name T13
Test name
Test status
Simulation time 53950215725 ps
CPU time 508.36 seconds
Started May 07 01:07:43 PM PDT 24
Finished May 07 01:16:12 PM PDT 24
Peak memory 197688 kb
Host smart-60ef72af-807c-4ea7-b9e9-70d729b5f3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423136568 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3423136568
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.470701435
Short name T61
Test name
Test status
Simulation time 725151176836 ps
CPU time 2186.37 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:44:44 PM PDT 24
Peak memory 196920 kb
Host smart-414e65f6-e567-40ca-aa18-6257daf823b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470701435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
470701435
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4204880229
Short name T21
Test name
Test status
Simulation time 240653916 ps
CPU time 1.35 seconds
Started May 07 03:01:47 PM PDT 24
Finished May 07 03:01:50 PM PDT 24
Peak memory 195408 kb
Host smart-b9c6f5c9-04ce-4479-baf3-59cf285bfb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204880229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.4204880229
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2793678705
Short name T11
Test name
Test status
Simulation time 211065653375 ps
CPU time 1067.77 seconds
Started May 07 01:08:06 PM PDT 24
Finished May 07 01:25:55 PM PDT 24
Peak memory 191256 kb
Host smart-d7cf314f-4094-45a0-8958-b3f7beb66455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793678705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2793678705
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1970169039
Short name T64
Test name
Test status
Simulation time 4579316485908 ps
CPU time 1828.26 seconds
Started May 07 01:07:38 PM PDT 24
Finished May 07 01:38:07 PM PDT 24
Peak memory 191232 kb
Host smart-ed7383f7-fc4c-493c-80b1-744dc9d6a845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970169039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1970169039
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2018794697
Short name T146
Test name
Test status
Simulation time 1628358597656 ps
CPU time 845.47 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:21:38 PM PDT 24
Peak memory 191224 kb
Host smart-869b71b8-5b31-4cc8-bb19-814d9b614402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018794697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2018794697
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3102852639
Short name T193
Test name
Test status
Simulation time 388386585886 ps
CPU time 1115.56 seconds
Started May 07 01:07:24 PM PDT 24
Finished May 07 01:26:01 PM PDT 24
Peak memory 196044 kb
Host smart-87f29e35-bcfc-4354-98bc-d504cc4f52e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102852639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3102852639
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.923882161
Short name T92
Test name
Test status
Simulation time 1776603939275 ps
CPU time 2226.58 seconds
Started May 07 01:07:52 PM PDT 24
Finished May 07 01:44:59 PM PDT 24
Peak memory 191264 kb
Host smart-fc992430-30e2-4bc4-9997-2ea457393f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923882161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
923882161
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/144.rv_timer_random.1233199103
Short name T6
Test name
Test status
Simulation time 322802019424 ps
CPU time 290.56 seconds
Started May 07 01:09:30 PM PDT 24
Finished May 07 01:14:22 PM PDT 24
Peak memory 191336 kb
Host smart-6977dc14-3d7f-4624-ba5d-9023fbea354a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233199103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1233199103
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2550317232
Short name T46
Test name
Test status
Simulation time 51417481 ps
CPU time 0.55 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:51 PM PDT 24
Peak memory 182752 kb
Host smart-afe15c3d-5adf-429d-b0b1-c1a6c662b67a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550317232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2550317232
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.476605928
Short name T194
Test name
Test status
Simulation time 1950073059676 ps
CPU time 1001.58 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:24:38 PM PDT 24
Peak memory 191428 kb
Host smart-e4304901-c465-4c7b-9d6d-209e94c6d409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476605928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
476605928
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3641869490
Short name T257
Test name
Test status
Simulation time 527689699131 ps
CPU time 1298.16 seconds
Started May 07 01:07:30 PM PDT 24
Finished May 07 01:29:09 PM PDT 24
Peak memory 191224 kb
Host smart-cf32f5c5-90ae-4b95-a8e4-2d908ec0ea7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641869490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3641869490
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.763952669
Short name T18
Test name
Test status
Simulation time 40448069 ps
CPU time 0.77 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:07:24 PM PDT 24
Peak memory 213264 kb
Host smart-8de9bfdc-d0b5-48dd-a2dc-8031f22b9494
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763952669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.763952669
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2597983942
Short name T62
Test name
Test status
Simulation time 1481451418389 ps
CPU time 723.31 seconds
Started May 07 01:07:42 PM PDT 24
Finished May 07 01:19:46 PM PDT 24
Peak memory 191196 kb
Host smart-70f0a35b-1e5b-4e73-9cde-6fae57d0db50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597983942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2597983942
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.1067698020
Short name T283
Test name
Test status
Simulation time 154221916386 ps
CPU time 1306.83 seconds
Started May 07 01:09:59 PM PDT 24
Finished May 07 01:31:46 PM PDT 24
Peak memory 194236 kb
Host smart-96e17c33-dbe8-4a54-b8f7-3e4bc0d3cb53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067698020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1067698020
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2478273145
Short name T59
Test name
Test status
Simulation time 258668334552 ps
CPU time 525.69 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:16:42 PM PDT 24
Peak memory 196772 kb
Host smart-c0f12399-ab44-4688-90b1-d9bbffdc88d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478273145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2478273145
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3477616081
Short name T195
Test name
Test status
Simulation time 310071911374 ps
CPU time 255.04 seconds
Started May 07 01:08:32 PM PDT 24
Finished May 07 01:12:48 PM PDT 24
Peak memory 191276 kb
Host smart-83fc16df-81b7-4f3d-b22d-ab8ac09eec72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477616081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3477616081
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/104.rv_timer_random.178659871
Short name T312
Test name
Test status
Simulation time 164563218554 ps
CPU time 276.63 seconds
Started May 07 01:09:06 PM PDT 24
Finished May 07 01:13:44 PM PDT 24
Peak memory 193468 kb
Host smart-dfc01ecc-9caf-4b95-bf46-9f170222359c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178659871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.178659871
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.4066400156
Short name T102
Test name
Test status
Simulation time 852554426208 ps
CPU time 842.74 seconds
Started May 07 01:09:29 PM PDT 24
Finished May 07 01:23:33 PM PDT 24
Peak memory 192520 kb
Host smart-f0edd472-d5f8-4c28-bcad-1513e9a8d2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066400156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.4066400156
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.2705223408
Short name T199
Test name
Test status
Simulation time 201381436162 ps
CPU time 1207.94 seconds
Started May 07 01:08:53 PM PDT 24
Finished May 07 01:29:01 PM PDT 24
Peak memory 191100 kb
Host smart-4b48b9f4-5c55-45cc-b760-43ca495d0cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705223408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2705223408
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.965429081
Short name T185
Test name
Test status
Simulation time 960454697486 ps
CPU time 580.34 seconds
Started May 07 01:09:34 PM PDT 24
Finished May 07 01:19:16 PM PDT 24
Peak memory 191100 kb
Host smart-af3e8b68-1bc4-4169-bb0e-9a0485101d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965429081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.965429081
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3190333320
Short name T290
Test name
Test status
Simulation time 230163430558 ps
CPU time 307.82 seconds
Started May 07 01:09:43 PM PDT 24
Finished May 07 01:14:51 PM PDT 24
Peak memory 191168 kb
Host smart-85c0d80c-1317-4ca7-ba33-40f8ce002996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190333320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3190333320
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1419457920
Short name T178
Test name
Test status
Simulation time 206970989155 ps
CPU time 440.03 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:15:06 PM PDT 24
Peak memory 195920 kb
Host smart-c81cb5bc-e8fe-4f21-b0df-5ac9a65616fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419457920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1419457920
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3784314584
Short name T52
Test name
Test status
Simulation time 276198777614 ps
CPU time 577.07 seconds
Started May 07 01:08:46 PM PDT 24
Finished May 07 01:18:24 PM PDT 24
Peak memory 191268 kb
Host smart-14c15296-a371-4a3d-8247-cf7a559884d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784314584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3784314584
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2099706780
Short name T217
Test name
Test status
Simulation time 159857195731 ps
CPU time 284.49 seconds
Started May 07 01:09:05 PM PDT 24
Finished May 07 01:13:50 PM PDT 24
Peak memory 191260 kb
Host smart-a570fb65-ec53-4d22-82a1-2fb82a4a44c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099706780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2099706780
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3693212434
Short name T333
Test name
Test status
Simulation time 806732890926 ps
CPU time 1633.86 seconds
Started May 07 01:07:48 PM PDT 24
Finished May 07 01:35:03 PM PDT 24
Peak memory 191252 kb
Host smart-048744c4-df87-4fb5-b096-de53912dbdde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693212434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3693212434
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/152.rv_timer_random.491739452
Short name T173
Test name
Test status
Simulation time 126532715589 ps
CPU time 348.21 seconds
Started May 07 01:09:35 PM PDT 24
Finished May 07 01:15:24 PM PDT 24
Peak memory 191260 kb
Host smart-0cd9dbc3-b70d-447b-bb8c-3da4d239f5d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491739452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.491739452
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1315392671
Short name T292
Test name
Test status
Simulation time 174106576062 ps
CPU time 303.72 seconds
Started May 07 01:09:59 PM PDT 24
Finished May 07 01:15:04 PM PDT 24
Peak memory 191260 kb
Host smart-54747d79-ad4f-499c-b6f6-0acf01f07121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315392671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1315392671
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1620392954
Short name T145
Test name
Test status
Simulation time 4577873822981 ps
CPU time 2393.71 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:47:18 PM PDT 24
Peak memory 194936 kb
Host smart-b62149e6-fda6-475b-9cfd-e33b99b2f76f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620392954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1620392954
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random.3366962959
Short name T349
Test name
Test status
Simulation time 538437560928 ps
CPU time 279.71 seconds
Started May 07 01:07:30 PM PDT 24
Finished May 07 01:12:11 PM PDT 24
Peak memory 191264 kb
Host smart-c8475a75-36db-422f-bb49-40078ec529a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366962959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3366962959
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.46522267
Short name T164
Test name
Test status
Simulation time 82600781341 ps
CPU time 604.36 seconds
Started May 07 01:09:52 PM PDT 24
Finished May 07 01:19:57 PM PDT 24
Peak memory 191200 kb
Host smart-d5a060b5-d4ff-496f-933e-2d0e24767cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46522267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.46522267
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.23544508
Short name T170
Test name
Test status
Simulation time 133293282700 ps
CPU time 1534.11 seconds
Started May 07 01:09:59 PM PDT 24
Finished May 07 01:35:33 PM PDT 24
Peak memory 191244 kb
Host smart-291b9f8a-f58a-4328-8de4-e5f78ac8c5d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23544508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.23544508
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1358045293
Short name T346
Test name
Test status
Simulation time 1596932907854 ps
CPU time 589.53 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:17:36 PM PDT 24
Peak memory 183088 kb
Host smart-9f893d93-7286-4fa6-b463-29600212aaae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358045293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1358045293
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.995070652
Short name T133
Test name
Test status
Simulation time 223561818909 ps
CPU time 258.85 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:12:06 PM PDT 24
Peak memory 191168 kb
Host smart-df0d193f-1c6f-4fbf-99e9-a13aa1896aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995070652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.995070652
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1781075043
Short name T188
Test name
Test status
Simulation time 278816621029 ps
CPU time 1292.31 seconds
Started May 07 01:07:53 PM PDT 24
Finished May 07 01:29:26 PM PDT 24
Peak memory 191260 kb
Host smart-e83eeec7-7ff6-4c64-9f09-6b51c825fe2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781075043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1781075043
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3170197058
Short name T141
Test name
Test status
Simulation time 1409452142406 ps
CPU time 737.15 seconds
Started May 07 01:08:04 PM PDT 24
Finished May 07 01:20:23 PM PDT 24
Peak memory 183060 kb
Host smart-8c4c70a0-276e-4397-8632-55e966698c73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170197058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3170197058
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/118.rv_timer_random.215188896
Short name T220
Test name
Test status
Simulation time 111865519912 ps
CPU time 212.03 seconds
Started May 07 01:09:21 PM PDT 24
Finished May 07 01:12:55 PM PDT 24
Peak memory 191224 kb
Host smart-4dc38000-d4ac-4f9a-b91e-2a4d1dc20aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215188896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.215188896
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.577302964
Short name T227
Test name
Test status
Simulation time 273333348928 ps
CPU time 299.23 seconds
Started May 07 01:09:28 PM PDT 24
Finished May 07 01:14:28 PM PDT 24
Peak memory 191252 kb
Host smart-805026cc-f01e-444e-b313-3f40f0d529b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577302964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.577302964
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.3293161004
Short name T79
Test name
Test status
Simulation time 257605609283 ps
CPU time 151.43 seconds
Started May 07 01:08:10 PM PDT 24
Finished May 07 01:10:43 PM PDT 24
Peak memory 191236 kb
Host smart-d7ceb68f-9b4a-4c3a-ab17-8c51de4ef9f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293161004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3293161004
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1993715017
Short name T198
Test name
Test status
Simulation time 304031452842 ps
CPU time 352.82 seconds
Started May 07 01:08:37 PM PDT 24
Finished May 07 01:14:31 PM PDT 24
Peak memory 191348 kb
Host smart-326d3f81-833f-40b4-b710-9dcb4a0b2d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993715017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1993715017
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.777377628
Short name T250
Test name
Test status
Simulation time 1772955490363 ps
CPU time 974.57 seconds
Started May 07 01:07:26 PM PDT 24
Finished May 07 01:23:41 PM PDT 24
Peak memory 183064 kb
Host smart-0947654c-37f1-4520-a82c-d6d333be2f5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777377628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.777377628
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_random.3412343094
Short name T229
Test name
Test status
Simulation time 172032311038 ps
CPU time 471.86 seconds
Started May 07 01:07:33 PM PDT 24
Finished May 07 01:15:26 PM PDT 24
Peak memory 191200 kb
Host smart-f958144e-d878-40c1-afea-b5e8526a8797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412343094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3412343094
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.4264136734
Short name T204
Test name
Test status
Simulation time 306020653443 ps
CPU time 1120.05 seconds
Started May 07 01:09:20 PM PDT 24
Finished May 07 01:28:02 PM PDT 24
Peak memory 191256 kb
Host smart-3c42aada-c842-46da-b82a-77f125776273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264136734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4264136734
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1587719290
Short name T50
Test name
Test status
Simulation time 436844263642 ps
CPU time 489.95 seconds
Started May 07 01:09:28 PM PDT 24
Finished May 07 01:17:39 PM PDT 24
Peak memory 191260 kb
Host smart-e2e20876-a804-4880-8fe0-5ab3d01c4c58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587719290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1587719290
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.963902602
Short name T418
Test name
Test status
Simulation time 154541552950 ps
CPU time 401.99 seconds
Started May 07 01:09:29 PM PDT 24
Finished May 07 01:16:12 PM PDT 24
Peak memory 191260 kb
Host smart-e6ccabf4-6629-445a-a9c8-ad3b143194ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963902602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.963902602
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1210948127
Short name T197
Test name
Test status
Simulation time 621597568234 ps
CPU time 1653.86 seconds
Started May 07 01:09:49 PM PDT 24
Finished May 07 01:37:24 PM PDT 24
Peak memory 191268 kb
Host smart-206a6324-4a0e-4706-8a4d-229b26c1d654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210948127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1210948127
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.1168663016
Short name T265
Test name
Test status
Simulation time 918008379528 ps
CPU time 272.98 seconds
Started May 07 01:07:21 PM PDT 24
Finished May 07 01:11:55 PM PDT 24
Peak memory 191332 kb
Host smart-a5fdf6ef-e06c-4709-96a3-77256862f6f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168663016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1168663016
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3523631203
Short name T189
Test name
Test status
Simulation time 200120001052 ps
CPU time 207.41 seconds
Started May 07 01:09:03 PM PDT 24
Finished May 07 01:12:31 PM PDT 24
Peak memory 191244 kb
Host smart-cbcba217-d00f-4ba3-8f84-7291cccbcb08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523631203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3523631203
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3517456742
Short name T223
Test name
Test status
Simulation time 571636202654 ps
CPU time 330.07 seconds
Started May 07 01:09:21 PM PDT 24
Finished May 07 01:14:53 PM PDT 24
Peak memory 191244 kb
Host smart-60e5d278-8b78-4cdc-8d35-0ae3ae82a4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517456742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3517456742
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.4193986285
Short name T215
Test name
Test status
Simulation time 171610483891 ps
CPU time 217.48 seconds
Started May 07 01:09:22 PM PDT 24
Finished May 07 01:13:02 PM PDT 24
Peak memory 193476 kb
Host smart-5592d6a5-5a4a-4614-94ae-abaa30813a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193986285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4193986285
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.170330587
Short name T249
Test name
Test status
Simulation time 155595405256 ps
CPU time 232.09 seconds
Started May 07 01:07:48 PM PDT 24
Finished May 07 01:11:41 PM PDT 24
Peak memory 191248 kb
Host smart-60f2a496-2901-4080-ad42-7f81b0b9eea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170330587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.170330587
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2901686873
Short name T240
Test name
Test status
Simulation time 66084997212 ps
CPU time 297.42 seconds
Started May 07 01:09:29 PM PDT 24
Finished May 07 01:14:28 PM PDT 24
Peak memory 191240 kb
Host smart-ac065cd6-ba2a-4279-a062-3dc3da0d8ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901686873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2901686873
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3967630805
Short name T343
Test name
Test status
Simulation time 869882775324 ps
CPU time 416.94 seconds
Started May 07 01:07:39 PM PDT 24
Finished May 07 01:14:37 PM PDT 24
Peak memory 191252 kb
Host smart-88a43627-847e-49e4-8176-9fb9b9886f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967630805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3967630805
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.782988801
Short name T307
Test name
Test status
Simulation time 435550880692 ps
CPU time 292.51 seconds
Started May 07 01:09:42 PM PDT 24
Finished May 07 01:14:35 PM PDT 24
Peak memory 191240 kb
Host smart-bbe74658-cd84-4946-bdaf-83ca7756901d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782988801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.782988801
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1528435379
Short name T245
Test name
Test status
Simulation time 100371058698 ps
CPU time 149.83 seconds
Started May 07 01:09:43 PM PDT 24
Finished May 07 01:12:13 PM PDT 24
Peak memory 191416 kb
Host smart-30b786f7-8190-42f0-9be9-45c127ce0112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528435379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1528435379
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2536998833
Short name T208
Test name
Test status
Simulation time 173660030177 ps
CPU time 2530.33 seconds
Started May 07 01:08:02 PM PDT 24
Finished May 07 01:50:14 PM PDT 24
Peak memory 196544 kb
Host smart-640228be-a290-4b96-862e-b08c7d9c6b54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536998833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2536998833
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.2066196073
Short name T162
Test name
Test status
Simulation time 245578935891 ps
CPU time 115.61 seconds
Started May 07 01:08:05 PM PDT 24
Finished May 07 01:10:02 PM PDT 24
Peak memory 191244 kb
Host smart-dc82e7b1-fb60-4777-92e7-802a9e7b1077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066196073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2066196073
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.2060823328
Short name T182
Test name
Test status
Simulation time 128670489880 ps
CPU time 574.76 seconds
Started May 07 01:07:29 PM PDT 24
Finished May 07 01:17:04 PM PDT 24
Peak memory 191232 kb
Host smart-7686e5c2-209f-4e8d-b665-534e75402259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060823328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2060823328
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1561592525
Short name T24
Test name
Test status
Simulation time 81391274 ps
CPU time 0.63 seconds
Started May 07 03:01:43 PM PDT 24
Finished May 07 03:01:45 PM PDT 24
Peak memory 192028 kb
Host smart-54c8d8d7-4ad1-41aa-a947-d1801692d0e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561592525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1561592525
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2381912792
Short name T127
Test name
Test status
Simulation time 189789282 ps
CPU time 1.49 seconds
Started May 07 03:02:00 PM PDT 24
Finished May 07 03:02:03 PM PDT 24
Peak memory 183372 kb
Host smart-8aafef8f-c6c0-4ddb-be6a-bf81d55c658c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381912792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2381912792
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2248156238
Short name T315
Test name
Test status
Simulation time 399793818482 ps
CPU time 333.77 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:13:06 PM PDT 24
Peak memory 191252 kb
Host smart-8e543c31-a0a3-42d8-8f45-4aa439691022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248156238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2248156238
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.772954129
Short name T44
Test name
Test status
Simulation time 72920775172 ps
CPU time 527.04 seconds
Started May 07 01:07:30 PM PDT 24
Finished May 07 01:16:18 PM PDT 24
Peak memory 205932 kb
Host smart-b31e07fd-1742-4df3-a3a3-64cd420c2a2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772954129 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.772954129
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.888465945
Short name T452
Test name
Test status
Simulation time 143565392921 ps
CPU time 241.43 seconds
Started May 07 01:09:06 PM PDT 24
Finished May 07 01:13:08 PM PDT 24
Peak memory 191260 kb
Host smart-13d4612c-f9cf-4825-aa7e-4f98439c3f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888465945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.888465945
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3608971758
Short name T75
Test name
Test status
Simulation time 131589202711 ps
CPU time 462.31 seconds
Started May 07 01:09:21 PM PDT 24
Finished May 07 01:17:04 PM PDT 24
Peak memory 191252 kb
Host smart-66e8364e-7076-4328-ada2-930f6fb4c6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608971758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3608971758
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.557808053
Short name T300
Test name
Test status
Simulation time 295067397614 ps
CPU time 546.74 seconds
Started May 07 01:09:29 PM PDT 24
Finished May 07 01:18:37 PM PDT 24
Peak memory 191236 kb
Host smart-fb02edb6-e199-4ed6-80b7-6e41540e5b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557808053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.557808053
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1633647875
Short name T331
Test name
Test status
Simulation time 476752298264 ps
CPU time 1970.82 seconds
Started May 07 01:09:41 PM PDT 24
Finished May 07 01:42:33 PM PDT 24
Peak memory 191224 kb
Host smart-bb466062-1341-45dc-baa7-7a3038175769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633647875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1633647875
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3967408274
Short name T228
Test name
Test status
Simulation time 580754628472 ps
CPU time 522.15 seconds
Started May 07 01:09:42 PM PDT 24
Finished May 07 01:18:25 PM PDT 24
Peak memory 191236 kb
Host smart-5e620fc1-4ad4-47d5-b576-1c8ace038698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967408274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3967408274
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3669185485
Short name T154
Test name
Test status
Simulation time 100549654518 ps
CPU time 281.87 seconds
Started May 07 01:10:00 PM PDT 24
Finished May 07 01:14:42 PM PDT 24
Peak memory 191224 kb
Host smart-d174e067-2134-4258-a0e7-04ff724afc38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669185485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3669185485
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1719089432
Short name T211
Test name
Test status
Simulation time 340715492065 ps
CPU time 484.13 seconds
Started May 07 01:07:25 PM PDT 24
Finished May 07 01:15:30 PM PDT 24
Peak memory 183044 kb
Host smart-9960c2a5-ddbc-404b-84f1-578436cceab1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719089432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1719089432
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2665332154
Short name T222
Test name
Test status
Simulation time 1152931979941 ps
CPU time 261 seconds
Started May 07 01:07:54 PM PDT 24
Finished May 07 01:12:16 PM PDT 24
Peak memory 183088 kb
Host smart-e844a5ac-043c-4d14-b990-6ab1f87971c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665332154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2665332154
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_random.3681670048
Short name T297
Test name
Test status
Simulation time 164082266757 ps
CPU time 974.51 seconds
Started May 07 01:07:56 PM PDT 24
Finished May 07 01:24:12 PM PDT 24
Peak memory 191260 kb
Host smart-4eb45b13-7f90-41d2-8fa2-c9d22f0d3a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681670048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3681670048
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2968804796
Short name T295
Test name
Test status
Simulation time 1674912498460 ps
CPU time 1433.42 seconds
Started May 07 01:08:04 PM PDT 24
Finished May 07 01:31:59 PM PDT 24
Peak memory 194964 kb
Host smart-c08b5cdf-8d9e-478c-a0ea-8d3b92b710ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968804796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2968804796
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_random.651058764
Short name T135
Test name
Test status
Simulation time 586103980634 ps
CPU time 1434.53 seconds
Started May 07 01:08:08 PM PDT 24
Finished May 07 01:32:04 PM PDT 24
Peak memory 195108 kb
Host smart-06a85122-79f0-4703-91d7-9aaaaae4f03f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651058764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.651058764
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.1522891537
Short name T122
Test name
Test status
Simulation time 688837003138 ps
CPU time 376.66 seconds
Started May 07 01:08:44 PM PDT 24
Finished May 07 01:15:02 PM PDT 24
Peak memory 191120 kb
Host smart-a8c3ffed-8c8b-4683-9745-6e1a0e528b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522891537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1522891537
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.233174009
Short name T74
Test name
Test status
Simulation time 300319895994 ps
CPU time 91.22 seconds
Started May 07 01:07:21 PM PDT 24
Finished May 07 01:08:54 PM PDT 24
Peak memory 183044 kb
Host smart-87bcf969-f2c9-42be-9829-9cf70801b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233174009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.233174009
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/72.rv_timer_random.416580245
Short name T262
Test name
Test status
Simulation time 509127708605 ps
CPU time 165.26 seconds
Started May 07 01:08:46 PM PDT 24
Finished May 07 01:11:32 PM PDT 24
Peak memory 191208 kb
Host smart-80bf758e-2062-44c3-be3d-aa322443a16b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416580245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.416580245
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.621223269
Short name T172
Test name
Test status
Simulation time 26369696796 ps
CPU time 64.05 seconds
Started May 07 01:08:58 PM PDT 24
Finished May 07 01:10:03 PM PDT 24
Peak memory 191252 kb
Host smart-2b48084a-7bac-4e2d-aa48-aee8e736eda8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621223269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.621223269
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4177577073
Short name T338
Test name
Test status
Simulation time 668012769694 ps
CPU time 381.68 seconds
Started May 07 01:09:00 PM PDT 24
Finished May 07 01:15:23 PM PDT 24
Peak memory 191208 kb
Host smart-a9dc95cb-7e87-45cc-934a-12ddbb33883f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177577073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4177577073
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.4038344726
Short name T219
Test name
Test status
Simulation time 84004240475 ps
CPU time 193.89 seconds
Started May 07 01:09:15 PM PDT 24
Finished May 07 01:12:30 PM PDT 24
Peak memory 191264 kb
Host smart-59991484-8b55-4e48-b1c3-5967473a5255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038344726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.4038344726
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2927623566
Short name T232
Test name
Test status
Simulation time 391454923186 ps
CPU time 150.19 seconds
Started May 07 01:09:12 PM PDT 24
Finished May 07 01:11:43 PM PDT 24
Peak memory 191256 kb
Host smart-87d0094a-624a-488d-abf3-e4e379348161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927623566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2927623566
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.4046982485
Short name T183
Test name
Test status
Simulation time 547485676900 ps
CPU time 621.92 seconds
Started May 07 01:09:21 PM PDT 24
Finished May 07 01:19:44 PM PDT 24
Peak memory 191232 kb
Host smart-9e8acc1a-ef5b-441d-a63a-f3c6605b3d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046982485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.4046982485
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.822302885
Short name T327
Test name
Test status
Simulation time 465620144335 ps
CPU time 422.5 seconds
Started May 07 01:09:21 PM PDT 24
Finished May 07 01:16:25 PM PDT 24
Peak memory 191260 kb
Host smart-24945e46-9291-4b35-801c-2929cd32f1c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822302885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.822302885
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3045510439
Short name T348
Test name
Test status
Simulation time 252870181207 ps
CPU time 323.55 seconds
Started May 07 01:09:28 PM PDT 24
Finished May 07 01:14:52 PM PDT 24
Peak memory 194772 kb
Host smart-b965a4a3-b0ce-4d44-b82e-e948c4b389a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045510439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3045510439
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.4118101166
Short name T186
Test name
Test status
Simulation time 3897779113741 ps
CPU time 1051.57 seconds
Started May 07 01:07:37 PM PDT 24
Finished May 07 01:25:09 PM PDT 24
Peak memory 182968 kb
Host smart-d28958dc-cf70-494a-869e-e704f15e1b62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118101166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.4118101166
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/140.rv_timer_random.213470285
Short name T134
Test name
Test status
Simulation time 16299556469 ps
CPU time 69.09 seconds
Started May 07 01:09:30 PM PDT 24
Finished May 07 01:10:40 PM PDT 24
Peak memory 193292 kb
Host smart-0bcb276d-1bcb-4799-b151-75a16b92b3b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213470285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.213470285
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3740623448
Short name T168
Test name
Test status
Simulation time 72380960645 ps
CPU time 88.1 seconds
Started May 07 01:09:35 PM PDT 24
Finished May 07 01:11:04 PM PDT 24
Peak memory 191236 kb
Host smart-24fdcc7c-a673-4110-a15e-2f2f01968a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740623448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3740623448
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1299882348
Short name T176
Test name
Test status
Simulation time 40836668466 ps
CPU time 187.45 seconds
Started May 07 01:07:38 PM PDT 24
Finished May 07 01:10:47 PM PDT 24
Peak memory 183076 kb
Host smart-db4a3341-6fd9-495b-b84d-a6ed1d4d3ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299882348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1299882348
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/164.rv_timer_random.386392610
Short name T155
Test name
Test status
Simulation time 83433053628 ps
CPU time 144.39 seconds
Started May 07 01:09:41 PM PDT 24
Finished May 07 01:12:06 PM PDT 24
Peak memory 183012 kb
Host smart-b7469515-35bf-42d7-ac88-e15eb85c99a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386392610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.386392610
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3997962743
Short name T269
Test name
Test status
Simulation time 337352787351 ps
CPU time 1848.23 seconds
Started May 07 01:09:42 PM PDT 24
Finished May 07 01:40:31 PM PDT 24
Peak memory 192188 kb
Host smart-c5e9d96d-e1de-479d-afc8-c21e1941c37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997962743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3997962743
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.384195106
Short name T2
Test name
Test status
Simulation time 147777065584 ps
CPU time 1700.34 seconds
Started May 07 01:09:48 PM PDT 24
Finished May 07 01:38:09 PM PDT 24
Peak memory 194108 kb
Host smart-b8d410cb-bc3e-4ced-975e-2c9e61cf60ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384195106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.384195106
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3251445731
Short name T108
Test name
Test status
Simulation time 277373086541 ps
CPU time 230.91 seconds
Started May 07 01:09:49 PM PDT 24
Finished May 07 01:13:41 PM PDT 24
Peak memory 191248 kb
Host smart-3ebc5645-bd3b-4878-8f06-31bf4e70369d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251445731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3251445731
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.370255137
Short name T282
Test name
Test status
Simulation time 81205247599 ps
CPU time 157.76 seconds
Started May 07 01:09:49 PM PDT 24
Finished May 07 01:12:27 PM PDT 24
Peak memory 191264 kb
Host smart-c8f51598-296b-4db0-88ad-b6582c45ce99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370255137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.370255137
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1057519456
Short name T81
Test name
Test status
Simulation time 1688712477192 ps
CPU time 1014.06 seconds
Started May 07 01:07:24 PM PDT 24
Finished May 07 01:24:19 PM PDT 24
Peak memory 191188 kb
Host smart-c0cad6d1-b01a-4788-b11d-35c81e3f9618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057519456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1057519456
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2910210712
Short name T132
Test name
Test status
Simulation time 153433447901 ps
CPU time 102.09 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:09:27 PM PDT 24
Peak memory 183048 kb
Host smart-425de117-3faf-46dc-8acb-fe4309dbf4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910210712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2910210712
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_random.572461231
Short name T180
Test name
Test status
Simulation time 906996600015 ps
CPU time 424.98 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:14:51 PM PDT 24
Peak memory 191252 kb
Host smart-101327a6-97d1-449c-ba26-b18cdc062ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572461231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.572461231
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.294047123
Short name T103
Test name
Test status
Simulation time 545562332136 ps
CPU time 514.25 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:16:30 PM PDT 24
Peak memory 183076 kb
Host smart-d74dce63-aa65-4e41-b0eb-99d6d85b89f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294047123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.294047123
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.147160824
Short name T254
Test name
Test status
Simulation time 65944224757 ps
CPU time 64.52 seconds
Started May 07 01:07:53 PM PDT 24
Finished May 07 01:08:59 PM PDT 24
Peak memory 191264 kb
Host smart-b93b930b-4239-4407-98c4-c92bde6700f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147160824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
147160824
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2440838185
Short name T83
Test name
Test status
Simulation time 60342525210 ps
CPU time 567.38 seconds
Started May 07 01:08:01 PM PDT 24
Finished May 07 01:17:30 PM PDT 24
Peak memory 205908 kb
Host smart-cc289baa-d6d5-4539-bf22-55cace1cad42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440838185 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.2440838185
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_random.1601265360
Short name T71
Test name
Test status
Simulation time 802168225479 ps
CPU time 523.62 seconds
Started May 07 01:08:16 PM PDT 24
Finished May 07 01:17:00 PM PDT 24
Peak memory 191152 kb
Host smart-9442d3a5-b47a-4297-9975-7500f5e86274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601265360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1601265360
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.4280771857
Short name T272
Test name
Test status
Simulation time 510574392699 ps
CPU time 558.63 seconds
Started May 07 01:07:28 PM PDT 24
Finished May 07 01:16:47 PM PDT 24
Peak memory 191244 kb
Host smart-046c362a-e12c-4764-ac66-63ffcae1a8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280771857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.4280771857
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3118277156
Short name T113
Test name
Test status
Simulation time 83501221 ps
CPU time 0.73 seconds
Started May 07 03:01:41 PM PDT 24
Finished May 07 03:01:43 PM PDT 24
Peak memory 191980 kb
Host smart-bff480e5-690c-440f-94da-f5e9b2331a70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118277156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3118277156
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3062477569
Short name T111
Test name
Test status
Simulation time 344766004 ps
CPU time 3.24 seconds
Started May 07 03:01:41 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 192844 kb
Host smart-42113156-e2ec-4e1d-ba17-e5a9364ee0b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062477569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3062477569
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2711909736
Short name T534
Test name
Test status
Simulation time 26324976 ps
CPU time 0.53 seconds
Started May 07 03:01:43 PM PDT 24
Finished May 07 03:01:45 PM PDT 24
Peak memory 182332 kb
Host smart-bc2e9a55-059c-4af3-9fed-181cb2f4e36e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711909736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2711909736
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3696294275
Short name T582
Test name
Test status
Simulation time 102033295 ps
CPU time 0.74 seconds
Started May 07 03:01:46 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 195384 kb
Host smart-85383667-526e-498f-95fc-a0623b77d702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696294275 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3696294275
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1947658453
Short name T485
Test name
Test status
Simulation time 12657676 ps
CPU time 0.58 seconds
Started May 07 03:01:45 PM PDT 24
Finished May 07 03:01:47 PM PDT 24
Peak memory 182776 kb
Host smart-c4172d1a-6021-4d4e-ac30-786469f9741c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947658453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1947658453
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.457832897
Short name T527
Test name
Test status
Simulation time 11923307 ps
CPU time 0.54 seconds
Started May 07 03:01:45 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 182668 kb
Host smart-da7fe082-611a-447a-b3cf-e2a48b895454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457832897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.457832897
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2996553629
Short name T493
Test name
Test status
Simulation time 168689636 ps
CPU time 2.1 seconds
Started May 07 03:01:43 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 191364 kb
Host smart-b732e15c-7f97-4ebf-a870-11f103f702de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996553629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2996553629
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1406838443
Short name T100
Test name
Test status
Simulation time 19417465 ps
CPU time 0.82 seconds
Started May 07 03:01:46 PM PDT 24
Finished May 07 03:01:49 PM PDT 24
Peak memory 191924 kb
Host smart-170e2c46-257b-4655-ad83-45f3e0fa906f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406838443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1406838443
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3791100887
Short name T124
Test name
Test status
Simulation time 65542482 ps
CPU time 2.32 seconds
Started May 07 03:01:45 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 191180 kb
Host smart-83e03949-b70f-4635-bd5e-db62c7c93612
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791100887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3791100887
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1865962369
Short name T84
Test name
Test status
Simulation time 53808177 ps
CPU time 0.57 seconds
Started May 07 03:01:43 PM PDT 24
Finished May 07 03:01:45 PM PDT 24
Peak memory 182796 kb
Host smart-b0110b69-3823-4264-8d99-85e07ce4ce7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865962369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1865962369
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3626233454
Short name T528
Test name
Test status
Simulation time 91520242 ps
CPU time 0.75 seconds
Started May 07 03:01:47 PM PDT 24
Finished May 07 03:01:49 PM PDT 24
Peak memory 195612 kb
Host smart-ae182cab-2c46-4400-a65c-1858a2c09464
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626233454 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3626233454
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2800515306
Short name T572
Test name
Test status
Simulation time 13240347 ps
CPU time 0.59 seconds
Started May 07 03:01:44 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 182592 kb
Host smart-2df9de3f-b4b5-43f2-8c12-531be4cdb20d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800515306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2800515306
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4281883237
Short name T462
Test name
Test status
Simulation time 30991957 ps
CPU time 0.52 seconds
Started May 07 03:01:43 PM PDT 24
Finished May 07 03:01:44 PM PDT 24
Peak memory 182304 kb
Host smart-9dab3fe8-0098-40d3-8ec4-de1b8c84d1c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281883237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4281883237
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1347215744
Short name T526
Test name
Test status
Simulation time 19393073 ps
CPU time 0.68 seconds
Started May 07 03:01:47 PM PDT 24
Finished May 07 03:01:49 PM PDT 24
Peak memory 191700 kb
Host smart-f9b56529-6383-4d4f-a30d-7cdf8d2b3d9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347215744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1347215744
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1987022567
Short name T547
Test name
Test status
Simulation time 194322423 ps
CPU time 2.8 seconds
Started May 07 03:01:46 PM PDT 24
Finished May 07 03:01:50 PM PDT 24
Peak memory 197624 kb
Host smart-85f3fda7-c731-432c-a333-8bb9d49a296d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987022567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1987022567
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3321094784
Short name T464
Test name
Test status
Simulation time 1521044762 ps
CPU time 1.3 seconds
Started May 07 03:01:45 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 183232 kb
Host smart-9b2168d8-f400-49c3-b97e-a48feaa0c78c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321094784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3321094784
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.548205779
Short name T477
Test name
Test status
Simulation time 36587415 ps
CPU time 0.62 seconds
Started May 07 03:01:55 PM PDT 24
Finished May 07 03:01:59 PM PDT 24
Peak memory 193924 kb
Host smart-bf2973d5-5776-4a32-80e4-297ee8bfa6d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548205779 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.548205779
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.543541905
Short name T112
Test name
Test status
Simulation time 12774007 ps
CPU time 0.58 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:57 PM PDT 24
Peak memory 182752 kb
Host smart-aa6cf274-3a83-4503-aa3d-be57d9da007d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543541905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.543541905
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1333156448
Short name T487
Test name
Test status
Simulation time 90329475 ps
CPU time 0.52 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:57 PM PDT 24
Peak memory 182116 kb
Host smart-5b806320-2f3b-4982-93aa-4130cbbb19b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333156448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1333156448
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4163647478
Short name T25
Test name
Test status
Simulation time 36244642 ps
CPU time 0.84 seconds
Started May 07 03:01:57 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 193436 kb
Host smart-1815a55e-4786-4690-b318-4a599b6c843d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163647478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4163647478
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1589163289
Short name T497
Test name
Test status
Simulation time 214812349 ps
CPU time 1.92 seconds
Started May 07 03:02:01 PM PDT 24
Finished May 07 03:02:05 PM PDT 24
Peak memory 197736 kb
Host smart-c51fd6bb-bb2d-455f-9441-e869c81b3537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589163289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1589163289
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2579334015
Short name T470
Test name
Test status
Simulation time 166789548 ps
CPU time 0.86 seconds
Started May 07 03:01:57 PM PDT 24
Finished May 07 03:02:01 PM PDT 24
Peak memory 193888 kb
Host smart-b1437dfe-94a4-45c3-8675-2c851fc5f484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579334015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2579334015
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2742531057
Short name T509
Test name
Test status
Simulation time 103344991 ps
CPU time 0.78 seconds
Started May 07 03:01:57 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 195600 kb
Host smart-a325d8fb-aa3a-4ba6-98a6-c6c45804d05b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742531057 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2742531057
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2418946531
Short name T579
Test name
Test status
Simulation time 60523255 ps
CPU time 0.58 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 192012 kb
Host smart-5ca170b1-e69b-4d3f-83c2-e4fffc3c57a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418946531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2418946531
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2994288299
Short name T508
Test name
Test status
Simulation time 69299522 ps
CPU time 0.53 seconds
Started May 07 03:01:57 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 182136 kb
Host smart-f43bfd9e-2d8e-48b2-9736-48feeef67262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994288299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2994288299
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2097115365
Short name T85
Test name
Test status
Simulation time 18315422 ps
CPU time 0.76 seconds
Started May 07 03:01:57 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 193428 kb
Host smart-7fa260f5-935a-4472-aace-b9c2789e2471
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097115365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2097115365
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.659960311
Short name T465
Test name
Test status
Simulation time 383648660 ps
CPU time 1.73 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:02:01 PM PDT 24
Peak memory 197668 kb
Host smart-f3111d6e-f3a9-4b09-b13c-d1861b154208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659960311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.659960311
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1732810994
Short name T125
Test name
Test status
Simulation time 172029626 ps
CPU time 1.3 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:01:59 PM PDT 24
Peak memory 183296 kb
Host smart-52b6937a-cd60-4ae9-acee-6cd79a0a366d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732810994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1732810994
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2432778050
Short name T479
Test name
Test status
Simulation time 108603796 ps
CPU time 1.27 seconds
Started May 07 03:02:03 PM PDT 24
Finished May 07 03:02:06 PM PDT 24
Peak memory 197632 kb
Host smart-9a445ccf-70e6-41b6-b828-2e0109782b9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432778050 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2432778050
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.470577028
Short name T475
Test name
Test status
Simulation time 25673985 ps
CPU time 0.59 seconds
Started May 07 03:02:00 PM PDT 24
Finished May 07 03:02:03 PM PDT 24
Peak memory 182776 kb
Host smart-9783b3ab-2f1b-4697-bde4-f01b4b51a195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470577028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.470577028
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.616986173
Short name T525
Test name
Test status
Simulation time 81445744 ps
CPU time 0.55 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:56 PM PDT 24
Peak memory 182700 kb
Host smart-4e002abc-fe4a-401c-9bce-3e1e5637c40e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616986173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.616986173
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4218556607
Short name T518
Test name
Test status
Simulation time 27594595 ps
CPU time 0.74 seconds
Started May 07 03:02:01 PM PDT 24
Finished May 07 03:02:04 PM PDT 24
Peak memory 192356 kb
Host smart-af13fcdb-d6fa-4934-a30a-dced238131e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218556607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4218556607
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2592507956
Short name T58
Test name
Test status
Simulation time 547066585 ps
CPU time 2.33 seconds
Started May 07 03:02:02 PM PDT 24
Finished May 07 03:02:06 PM PDT 24
Peak memory 197760 kb
Host smart-ab99fe46-8c19-4f59-babf-723bc6c52adc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592507956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2592507956
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4194574258
Short name T129
Test name
Test status
Simulation time 76403189 ps
CPU time 1.08 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 183236 kb
Host smart-c799b794-2040-4a1d-89b9-4726db9781b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194574258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4194574258
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3834964790
Short name T524
Test name
Test status
Simulation time 49253611 ps
CPU time 0.96 seconds
Started May 07 03:02:00 PM PDT 24
Finished May 07 03:02:03 PM PDT 24
Peak memory 197472 kb
Host smart-34aec134-77b0-4443-9c8b-ffec57d0c77a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834964790 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3834964790
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3745474896
Short name T96
Test name
Test status
Simulation time 90645634 ps
CPU time 0.56 seconds
Started May 07 03:01:59 PM PDT 24
Finished May 07 03:02:02 PM PDT 24
Peak memory 182772 kb
Host smart-b0e79fe6-aa77-455f-b02c-494e56e6d7eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745474896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3745474896
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1904875302
Short name T461
Test name
Test status
Simulation time 32064735 ps
CPU time 0.52 seconds
Started May 07 03:02:04 PM PDT 24
Finished May 07 03:02:06 PM PDT 24
Peak memory 182136 kb
Host smart-946fa237-0d0e-44ef-a9f6-de08b6f1984b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904875302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1904875302
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3546896171
Short name T119
Test name
Test status
Simulation time 74192054 ps
CPU time 0.85 seconds
Started May 07 03:02:00 PM PDT 24
Finished May 07 03:02:03 PM PDT 24
Peak memory 193600 kb
Host smart-60803f89-4b00-4f3c-9a1a-d7c22ba6a4bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546896171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3546896171
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3394512121
Short name T578
Test name
Test status
Simulation time 77202033 ps
CPU time 1.53 seconds
Started May 07 03:01:59 PM PDT 24
Finished May 07 03:02:03 PM PDT 24
Peak memory 197640 kb
Host smart-5c3c64ef-d688-405d-ae60-7d8db30b46f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394512121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3394512121
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1780442657
Short name T126
Test name
Test status
Simulation time 570871615 ps
CPU time 1.41 seconds
Started May 07 03:02:03 PM PDT 24
Finished May 07 03:02:06 PM PDT 24
Peak memory 183580 kb
Host smart-9b15a970-4840-4835-822f-f435640477b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780442657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1780442657
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.406477368
Short name T460
Test name
Test status
Simulation time 44411752 ps
CPU time 0.66 seconds
Started May 07 03:02:00 PM PDT 24
Finished May 07 03:02:03 PM PDT 24
Peak memory 194880 kb
Host smart-12460e9e-a95c-48b3-b699-44dc131c5ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406477368 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.406477368
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1978672184
Short name T500
Test name
Test status
Simulation time 14049162 ps
CPU time 0.59 seconds
Started May 07 03:02:00 PM PDT 24
Finished May 07 03:02:03 PM PDT 24
Peak memory 192012 kb
Host smart-07585e33-b39f-43d0-90ea-9a42efc98326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978672184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1978672184
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2521922976
Short name T458
Test name
Test status
Simulation time 14986529 ps
CPU time 0.56 seconds
Started May 07 03:02:02 PM PDT 24
Finished May 07 03:02:05 PM PDT 24
Peak memory 182660 kb
Host smart-103b735f-2565-4b56-b499-2a10ccc52e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521922976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2521922976
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1513435055
Short name T514
Test name
Test status
Simulation time 28398852 ps
CPU time 0.7 seconds
Started May 07 03:02:02 PM PDT 24
Finished May 07 03:02:05 PM PDT 24
Peak memory 191768 kb
Host smart-e1b461dd-3681-4dce-ab04-964026507825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513435055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1513435055
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2496389015
Short name T505
Test name
Test status
Simulation time 193248563 ps
CPU time 1.5 seconds
Started May 07 03:02:04 PM PDT 24
Finished May 07 03:02:07 PM PDT 24
Peak memory 197652 kb
Host smart-ef6887b5-1c9f-451f-883c-feacbc0dd085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496389015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2496389015
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1552788434
Short name T555
Test name
Test status
Simulation time 23287164 ps
CPU time 0.63 seconds
Started May 07 03:02:09 PM PDT 24
Finished May 07 03:02:11 PM PDT 24
Peak memory 194272 kb
Host smart-14b92d0e-63df-441a-b553-0290e36449ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552788434 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1552788434
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1220297977
Short name T536
Test name
Test status
Simulation time 22437320 ps
CPU time 0.53 seconds
Started May 07 03:02:02 PM PDT 24
Finished May 07 03:02:04 PM PDT 24
Peak memory 182488 kb
Host smart-3b0f07d1-fe7d-446c-af29-e9b9593ebbaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220297977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1220297977
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4123300437
Short name T540
Test name
Test status
Simulation time 56736913 ps
CPU time 0.6 seconds
Started May 07 03:02:03 PM PDT 24
Finished May 07 03:02:05 PM PDT 24
Peak memory 182564 kb
Host smart-bbd02fea-0aba-441b-95bb-136f744dde93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123300437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4123300437
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4167621074
Short name T513
Test name
Test status
Simulation time 21443243 ps
CPU time 0.75 seconds
Started May 07 03:02:11 PM PDT 24
Finished May 07 03:02:13 PM PDT 24
Peak memory 193292 kb
Host smart-24fbbad9-8e0c-440b-aed5-0ad94e31ea23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167621074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4167621074
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.247533226
Short name T484
Test name
Test status
Simulation time 145679282 ps
CPU time 2.84 seconds
Started May 07 03:02:01 PM PDT 24
Finished May 07 03:02:06 PM PDT 24
Peak memory 197640 kb
Host smart-3a0340ce-15ab-45b7-8896-7fe3a04b1b47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247533226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.247533226
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1663854343
Short name T466
Test name
Test status
Simulation time 72891281 ps
CPU time 1.08 seconds
Started May 07 03:02:02 PM PDT 24
Finished May 07 03:02:05 PM PDT 24
Peak memory 183272 kb
Host smart-3bc42c31-bc53-4e56-b463-8e491a96ec9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663854343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1663854343
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.556996745
Short name T469
Test name
Test status
Simulation time 66540190 ps
CPU time 1.53 seconds
Started May 07 03:02:06 PM PDT 24
Finished May 07 03:02:09 PM PDT 24
Peak memory 197712 kb
Host smart-ca6d024c-b7b4-42e3-acda-8e4520589084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556996745 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.556996745
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3873892869
Short name T98
Test name
Test status
Simulation time 64841702 ps
CPU time 0.59 seconds
Started May 07 03:02:07 PM PDT 24
Finished May 07 03:02:08 PM PDT 24
Peak memory 182788 kb
Host smart-54e75b48-53f2-40ce-afc2-008b96e57bae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873892869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3873892869
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3825682934
Short name T542
Test name
Test status
Simulation time 13114680 ps
CPU time 0.55 seconds
Started May 07 03:02:06 PM PDT 24
Finished May 07 03:02:08 PM PDT 24
Peak memory 182588 kb
Host smart-70fdc6b7-0d93-45e9-b1eb-150b631d32d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825682934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3825682934
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2032716273
Short name T116
Test name
Test status
Simulation time 90284138 ps
CPU time 0.7 seconds
Started May 07 03:02:08 PM PDT 24
Finished May 07 03:02:11 PM PDT 24
Peak memory 192388 kb
Host smart-8bf6f2db-d42c-4ec7-8c5f-d248462a3821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032716273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2032716273
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.20905742
Short name T504
Test name
Test status
Simulation time 159388228 ps
CPU time 1.76 seconds
Started May 07 03:02:07 PM PDT 24
Finished May 07 03:02:10 PM PDT 24
Peak memory 197696 kb
Host smart-66eb9223-0120-495c-ba35-1e1fd6604fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20905742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.20905742
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3591910614
Short name T23
Test name
Test status
Simulation time 84394205 ps
CPU time 1.15 seconds
Started May 07 03:02:08 PM PDT 24
Finished May 07 03:02:10 PM PDT 24
Peak memory 195232 kb
Host smart-f9ad4e74-9c8f-4363-84f1-3cefbafee0ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591910614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3591910614
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.201259304
Short name T482
Test name
Test status
Simulation time 96312737 ps
CPU time 0.72 seconds
Started May 07 03:02:05 PM PDT 24
Finished May 07 03:02:07 PM PDT 24
Peak memory 194268 kb
Host smart-f602b94b-b7d3-4aa3-bbc2-986323a7efab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201259304 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.201259304
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.146648468
Short name T86
Test name
Test status
Simulation time 61618640 ps
CPU time 0.54 seconds
Started May 07 03:02:06 PM PDT 24
Finished May 07 03:02:08 PM PDT 24
Peak memory 182756 kb
Host smart-5b9213c8-92b7-4b41-b7eb-3cbb9baf28b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146648468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.146648468
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3531525842
Short name T501
Test name
Test status
Simulation time 15488306 ps
CPU time 0.55 seconds
Started May 07 03:02:07 PM PDT 24
Finished May 07 03:02:09 PM PDT 24
Peak memory 182720 kb
Host smart-1e77e49d-ac22-404d-b081-5bfac9154752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531525842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3531525842
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3330969142
Short name T543
Test name
Test status
Simulation time 12233809 ps
CPU time 0.59 seconds
Started May 07 03:02:08 PM PDT 24
Finished May 07 03:02:11 PM PDT 24
Peak memory 191192 kb
Host smart-46954bfc-2ebc-4182-8adb-1487fd17c5be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330969142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3330969142
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.567412838
Short name T522
Test name
Test status
Simulation time 158493190 ps
CPU time 1.52 seconds
Started May 07 03:02:09 PM PDT 24
Finished May 07 03:02:12 PM PDT 24
Peak memory 197720 kb
Host smart-9e5063d3-456e-438f-9cc5-7a29331ebf9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567412838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.567412838
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1221067202
Short name T22
Test name
Test status
Simulation time 68295163 ps
CPU time 1.06 seconds
Started May 07 03:02:08 PM PDT 24
Finished May 07 03:02:10 PM PDT 24
Peak memory 183272 kb
Host smart-98909d21-3de0-463e-8b67-c1de68320e12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221067202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1221067202
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.96120325
Short name T583
Test name
Test status
Simulation time 141766429 ps
CPU time 1.11 seconds
Started May 07 03:02:08 PM PDT 24
Finished May 07 03:02:10 PM PDT 24
Peak memory 197604 kb
Host smart-d1a09bc1-2add-4f65-bbbb-eff5755ada8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96120325 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.96120325
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1412309728
Short name T506
Test name
Test status
Simulation time 40028370 ps
CPU time 0.56 seconds
Started May 07 03:02:06 PM PDT 24
Finished May 07 03:02:07 PM PDT 24
Peak memory 182776 kb
Host smart-c1933884-36b8-4ab9-bf05-5f7599e1f8a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412309728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1412309728
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.242937266
Short name T502
Test name
Test status
Simulation time 23407299 ps
CPU time 0.55 seconds
Started May 07 03:02:06 PM PDT 24
Finished May 07 03:02:08 PM PDT 24
Peak memory 182344 kb
Host smart-72c595a8-fb60-429c-bbff-cbbfd2cb131f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242937266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.242937266
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2752444410
Short name T586
Test name
Test status
Simulation time 37383841 ps
CPU time 0.78 seconds
Started May 07 03:02:09 PM PDT 24
Finished May 07 03:02:11 PM PDT 24
Peak memory 193632 kb
Host smart-1b4340ab-6bd0-4db5-94b2-eb1de8f202b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752444410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2752444410
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2802080075
Short name T515
Test name
Test status
Simulation time 610741265 ps
CPU time 2.41 seconds
Started May 07 03:02:06 PM PDT 24
Finished May 07 03:02:10 PM PDT 24
Peak memory 197596 kb
Host smart-ba3c121f-1c5a-4e8a-bedf-c20ec1cb4896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802080075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2802080075
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.245890902
Short name T478
Test name
Test status
Simulation time 74141362 ps
CPU time 0.79 seconds
Started May 07 03:02:09 PM PDT 24
Finished May 07 03:02:11 PM PDT 24
Peak memory 193540 kb
Host smart-ef1e4ef9-b84d-45ba-b1c1-0d1881e40354
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245890902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.245890902
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2395853057
Short name T537
Test name
Test status
Simulation time 115796427 ps
CPU time 0.84 seconds
Started May 07 03:02:06 PM PDT 24
Finished May 07 03:02:08 PM PDT 24
Peak memory 196660 kb
Host smart-356e3a54-a583-4837-a316-289b3d999b17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395853057 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2395853057
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.917712262
Short name T117
Test name
Test status
Simulation time 14521404 ps
CPU time 0.56 seconds
Started May 07 03:02:05 PM PDT 24
Finished May 07 03:02:07 PM PDT 24
Peak memory 182580 kb
Host smart-e4a88b40-fb1a-4e30-87bb-bd50713657b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917712262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.917712262
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2572200259
Short name T548
Test name
Test status
Simulation time 85235711 ps
CPU time 0.53 seconds
Started May 07 03:02:10 PM PDT 24
Finished May 07 03:02:12 PM PDT 24
Peak memory 182612 kb
Host smart-8e1bf029-13e7-4416-854e-211ff5e58270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572200259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2572200259
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1611438843
Short name T118
Test name
Test status
Simulation time 23320766 ps
CPU time 0.64 seconds
Started May 07 03:02:07 PM PDT 24
Finished May 07 03:02:09 PM PDT 24
Peak memory 192032 kb
Host smart-d2d94fc7-efd7-47c5-b25b-bfc430f2c88f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611438843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1611438843
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2328865761
Short name T559
Test name
Test status
Simulation time 335665898 ps
CPU time 1.82 seconds
Started May 07 03:02:08 PM PDT 24
Finished May 07 03:02:12 PM PDT 24
Peak memory 197632 kb
Host smart-1e84892d-21b8-4bca-a180-4f0cb4de768b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328865761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2328865761
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1589192070
Short name T523
Test name
Test status
Simulation time 158430494 ps
CPU time 0.84 seconds
Started May 07 03:02:10 PM PDT 24
Finished May 07 03:02:12 PM PDT 24
Peak memory 183292 kb
Host smart-eec54000-4938-4976-b9e1-22a98ce8d759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589192070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1589192070
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3353336862
Short name T529
Test name
Test status
Simulation time 69550483 ps
CPU time 0.62 seconds
Started May 07 03:01:50 PM PDT 24
Finished May 07 03:01:52 PM PDT 24
Peak memory 182784 kb
Host smart-a37085d8-a96e-4701-84a7-a72f551e86d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353336862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3353336862
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1099117306
Short name T520
Test name
Test status
Simulation time 106375969 ps
CPU time 1.48 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:52 PM PDT 24
Peak memory 182956 kb
Host smart-36d7d034-18c5-4d9d-b12a-64834622188e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099117306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1099117306
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.16659862
Short name T468
Test name
Test status
Simulation time 26749293 ps
CPU time 0.62 seconds
Started May 07 03:01:46 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 182780 kb
Host smart-cd1e8c8f-3ba9-4737-b1c2-ee065280ddbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_res
et.16659862
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1441707091
Short name T476
Test name
Test status
Simulation time 55330944 ps
CPU time 0.96 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:54 PM PDT 24
Peak memory 197496 kb
Host smart-7c823b3c-6cf2-4e5c-8587-5111e464d92a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441707091 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1441707091
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.840754098
Short name T26
Test name
Test status
Simulation time 32588386 ps
CPU time 0.6 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:50 PM PDT 24
Peak memory 182608 kb
Host smart-03a3a1d6-24f8-412a-9199-a40661990d2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840754098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.840754098
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.514213114
Short name T585
Test name
Test status
Simulation time 20888432 ps
CPU time 0.55 seconds
Started May 07 03:01:46 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 182720 kb
Host smart-cefa91d8-936a-41e4-96ec-32a395049c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514213114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.514213114
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3606782045
Short name T512
Test name
Test status
Simulation time 203674856 ps
CPU time 0.86 seconds
Started May 07 03:01:50 PM PDT 24
Finished May 07 03:01:52 PM PDT 24
Peak memory 193544 kb
Host smart-636538dc-7065-4775-a631-97f551e833f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606782045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3606782045
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4167376239
Short name T511
Test name
Test status
Simulation time 142391631 ps
CPU time 1.97 seconds
Started May 07 03:01:44 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 197656 kb
Host smart-12f5de48-cbb9-4fbb-b533-d42914e6bd68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167376239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4167376239
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3807178126
Short name T545
Test name
Test status
Simulation time 189676533 ps
CPU time 0.89 seconds
Started May 07 03:01:45 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 193648 kb
Host smart-a5cb9731-6218-4c34-a560-c377c0c6b908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807178126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3807178126
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2902784066
Short name T584
Test name
Test status
Simulation time 19428133 ps
CPU time 0.51 seconds
Started May 07 03:02:08 PM PDT 24
Finished May 07 03:02:10 PM PDT 24
Peak memory 182124 kb
Host smart-8491e307-b8ee-47e9-8d84-79baac305708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902784066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2902784066
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3407912836
Short name T495
Test name
Test status
Simulation time 31138464 ps
CPU time 0.57 seconds
Started May 07 03:02:07 PM PDT 24
Finished May 07 03:02:09 PM PDT 24
Peak memory 182688 kb
Host smart-2bdaca74-7fb1-420b-b483-a631212f8df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407912836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3407912836
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1082581213
Short name T539
Test name
Test status
Simulation time 35938504 ps
CPU time 0.51 seconds
Started May 07 03:02:07 PM PDT 24
Finished May 07 03:02:09 PM PDT 24
Peak memory 182136 kb
Host smart-0f7da33c-f62b-47b3-8528-8c20a78c396e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082581213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1082581213
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3727456960
Short name T489
Test name
Test status
Simulation time 11769902 ps
CPU time 0.53 seconds
Started May 07 03:02:08 PM PDT 24
Finished May 07 03:02:10 PM PDT 24
Peak memory 182632 kb
Host smart-bda7a758-6757-48a8-8767-9583ecd2d038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727456960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3727456960
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1443943269
Short name T483
Test name
Test status
Simulation time 14885760 ps
CPU time 0.55 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:16 PM PDT 24
Peak memory 182720 kb
Host smart-4e9f4a92-d722-406e-a3a6-0c701f7a6484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443943269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1443943269
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.810816268
Short name T549
Test name
Test status
Simulation time 16304975 ps
CPU time 0.56 seconds
Started May 07 03:02:15 PM PDT 24
Finished May 07 03:02:18 PM PDT 24
Peak memory 182112 kb
Host smart-325db632-2f95-4ce1-82d9-b2f7901dd6bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810816268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.810816268
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4052089256
Short name T577
Test name
Test status
Simulation time 119882232 ps
CPU time 0.55 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:15 PM PDT 24
Peak memory 182624 kb
Host smart-82c43e55-dd73-427e-9d15-52e2260fba67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052089256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.4052089256
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1798658231
Short name T553
Test name
Test status
Simulation time 31108139 ps
CPU time 0.53 seconds
Started May 07 03:02:15 PM PDT 24
Finished May 07 03:02:17 PM PDT 24
Peak memory 182104 kb
Host smart-f80efe0a-d33b-4a5e-afb1-99949febbef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798658231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1798658231
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3710997167
Short name T576
Test name
Test status
Simulation time 141402442 ps
CPU time 0.57 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:17 PM PDT 24
Peak memory 182624 kb
Host smart-9accb6a1-6f8f-4f59-99ae-0fa727a89500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710997167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3710997167
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1082081926
Short name T503
Test name
Test status
Simulation time 43765141 ps
CPU time 0.53 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:17 PM PDT 24
Peak memory 182736 kb
Host smart-b65b2dee-66a8-4c12-8963-111c2860cee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082081926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1082081926
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4065043622
Short name T114
Test name
Test status
Simulation time 688298372 ps
CPU time 0.85 seconds
Started May 07 03:01:53 PM PDT 24
Finished May 07 03:01:55 PM PDT 24
Peak memory 192240 kb
Host smart-2804e2ae-ab73-48b4-a625-ecb409ddda79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065043622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.4065043622
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1227518776
Short name T488
Test name
Test status
Simulation time 222168683 ps
CPU time 2.33 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:55 PM PDT 24
Peak memory 191196 kb
Host smart-9d3e3751-74a6-4a33-ae74-d00909598a71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227518776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1227518776
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.512510708
Short name T97
Test name
Test status
Simulation time 15083151 ps
CPU time 0.54 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:50 PM PDT 24
Peak memory 182784 kb
Host smart-4bfca7d3-57f4-4adc-9cf1-3f9ec2adc578
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512510708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.512510708
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.728450989
Short name T532
Test name
Test status
Simulation time 127657804 ps
CPU time 0.94 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:53 PM PDT 24
Peak memory 196724 kb
Host smart-6d407457-6513-4a9e-9bec-77174aa246c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728450989 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.728450989
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3770533963
Short name T535
Test name
Test status
Simulation time 23330656 ps
CPU time 0.57 seconds
Started May 07 03:01:53 PM PDT 24
Finished May 07 03:01:55 PM PDT 24
Peak memory 182644 kb
Host smart-b32f42c6-cc96-4f5f-8686-994aaa9a2544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770533963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3770533963
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1578464416
Short name T531
Test name
Test status
Simulation time 62509181 ps
CPU time 0.61 seconds
Started May 07 03:01:52 PM PDT 24
Finished May 07 03:01:54 PM PDT 24
Peak memory 192044 kb
Host smart-359de2ea-9484-451e-b56a-b0b7699f2d15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578464416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1578464416
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3942303519
Short name T560
Test name
Test status
Simulation time 104412209 ps
CPU time 2.15 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:54 PM PDT 24
Peak memory 197692 kb
Host smart-620becc2-8785-4231-a942-18e477676119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942303519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3942303519
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.78581635
Short name T507
Test name
Test status
Simulation time 299969858 ps
CPU time 1.09 seconds
Started May 07 03:01:48 PM PDT 24
Finished May 07 03:01:51 PM PDT 24
Peak memory 195344 kb
Host smart-af6cd54a-61ad-45a2-8bb1-5b06112a89fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78581635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg
_err.78581635
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2021641856
Short name T463
Test name
Test status
Simulation time 111319168 ps
CPU time 0.54 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:15 PM PDT 24
Peak memory 182604 kb
Host smart-6c2d87e4-ca58-449d-ac76-5a545a10cef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021641856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2021641856
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1436979896
Short name T498
Test name
Test status
Simulation time 14313847 ps
CPU time 0.57 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:16 PM PDT 24
Peak memory 182648 kb
Host smart-b4d1ec9b-d2f2-4b0e-aefe-848360a87f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436979896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1436979896
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4038946562
Short name T472
Test name
Test status
Simulation time 64016992 ps
CPU time 0.51 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:15 PM PDT 24
Peak memory 182116 kb
Host smart-274fc496-aa95-4944-b566-40736c39ce3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038946562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4038946562
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4176912840
Short name T486
Test name
Test status
Simulation time 39794916 ps
CPU time 0.63 seconds
Started May 07 03:02:12 PM PDT 24
Finished May 07 03:02:14 PM PDT 24
Peak memory 182144 kb
Host smart-f2e003e7-4380-412b-9eba-e3040d94af9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176912840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.4176912840
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1369478907
Short name T566
Test name
Test status
Simulation time 24546775 ps
CPU time 0.59 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:17 PM PDT 24
Peak memory 182640 kb
Host smart-43c9a021-1a49-4069-a9b0-013c5dc7852f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369478907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1369478907
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3200480201
Short name T456
Test name
Test status
Simulation time 15124677 ps
CPU time 0.54 seconds
Started May 07 03:02:15 PM PDT 24
Finished May 07 03:02:18 PM PDT 24
Peak memory 182128 kb
Host smart-f506caff-9023-4a26-a248-2d8264c00a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200480201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3200480201
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3650892125
Short name T521
Test name
Test status
Simulation time 18076076 ps
CPU time 0.56 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:16 PM PDT 24
Peak memory 182660 kb
Host smart-06366cb7-60b0-48df-8564-077f3445fb62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650892125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3650892125
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3792937280
Short name T546
Test name
Test status
Simulation time 39358159 ps
CPU time 0.56 seconds
Started May 07 03:02:17 PM PDT 24
Finished May 07 03:02:19 PM PDT 24
Peak memory 182160 kb
Host smart-e5c67ba3-ab31-48e0-819b-ada0fd878aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792937280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3792937280
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4146711777
Short name T471
Test name
Test status
Simulation time 15708759 ps
CPU time 0.57 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:17 PM PDT 24
Peak memory 182744 kb
Host smart-a6206a4c-edf9-4e13-92cd-6d8813961e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146711777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4146711777
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2032603956
Short name T563
Test name
Test status
Simulation time 16254222 ps
CPU time 0.56 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:15 PM PDT 24
Peak memory 182692 kb
Host smart-b238b0d2-2751-44fe-bc4a-d3e3a1bcc3b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032603956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2032603956
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3882852710
Short name T99
Test name
Test status
Simulation time 34406814 ps
CPU time 0.73 seconds
Started May 07 03:01:48 PM PDT 24
Finished May 07 03:01:50 PM PDT 24
Peak memory 192488 kb
Host smart-a93c8cfa-cb25-4c82-abc7-3e61e90ca656
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882852710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3882852710
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3960288290
Short name T473
Test name
Test status
Simulation time 106261586 ps
CPU time 1.51 seconds
Started May 07 03:01:53 PM PDT 24
Finished May 07 03:01:56 PM PDT 24
Peak memory 192984 kb
Host smart-d39a2290-56fa-4156-afec-f8d651b8ad7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960288290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3960288290
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2238430728
Short name T564
Test name
Test status
Simulation time 23192740 ps
CPU time 0.56 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:50 PM PDT 24
Peak memory 182768 kb
Host smart-454a1e26-0520-4655-a218-7954c7bf653e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238430728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2238430728
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1716741179
Short name T492
Test name
Test status
Simulation time 112115249 ps
CPU time 1.48 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:52 PM PDT 24
Peak memory 197720 kb
Host smart-14725546-9c0a-4b8c-aa1a-e921d5877a32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716741179 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1716741179
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3522888677
Short name T580
Test name
Test status
Simulation time 44756335 ps
CPU time 0.58 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:51 PM PDT 24
Peak memory 182768 kb
Host smart-c04bf55b-f702-4ac6-82de-26fe48fb8fcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522888677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3522888677
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1653461603
Short name T568
Test name
Test status
Simulation time 18177547 ps
CPU time 0.53 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:53 PM PDT 24
Peak memory 182144 kb
Host smart-02a3b078-982a-4174-9f5d-dd5e6b3aa288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653461603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1653461603
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.902005292
Short name T575
Test name
Test status
Simulation time 79940376 ps
CPU time 0.68 seconds
Started May 07 03:01:48 PM PDT 24
Finished May 07 03:01:51 PM PDT 24
Peak memory 191800 kb
Host smart-0c065d89-b491-404d-b151-f78f42b7a150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902005292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.902005292
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1111844685
Short name T544
Test name
Test status
Simulation time 468634588 ps
CPU time 1.67 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:55 PM PDT 24
Peak memory 197628 kb
Host smart-ed5c08b2-5605-4a98-b7f0-f0d6dd2f02f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111844685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1111844685
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.13069887
Short name T128
Test name
Test status
Simulation time 246542663 ps
CPU time 0.92 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:57 PM PDT 24
Peak memory 193532 kb
Host smart-034041b5-d88b-43d7-acc5-3ace3c7b0c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13069887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg
_err.13069887
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4196392790
Short name T467
Test name
Test status
Simulation time 50484344 ps
CPU time 0.54 seconds
Started May 07 03:02:15 PM PDT 24
Finished May 07 03:02:17 PM PDT 24
Peak memory 182592 kb
Host smart-4af87518-14b7-4512-997b-76981f42b465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196392790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4196392790
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2864662468
Short name T554
Test name
Test status
Simulation time 25512141 ps
CPU time 0.55 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:16 PM PDT 24
Peak memory 182700 kb
Host smart-3d7c9707-f22a-44c7-9c4c-58965273e8ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864662468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2864662468
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3200778219
Short name T474
Test name
Test status
Simulation time 16319797 ps
CPU time 0.56 seconds
Started May 07 03:02:15 PM PDT 24
Finished May 07 03:02:18 PM PDT 24
Peak memory 182676 kb
Host smart-b9cd8ea4-5bd6-425f-b4ff-9388cf7eca11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200778219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3200778219
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1073800955
Short name T481
Test name
Test status
Simulation time 11052383 ps
CPU time 0.56 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:16 PM PDT 24
Peak memory 182648 kb
Host smart-fcce4806-edaf-48ad-9a6c-bd352f2335c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073800955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1073800955
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3026179868
Short name T459
Test name
Test status
Simulation time 13207928 ps
CPU time 0.62 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:16 PM PDT 24
Peak memory 182708 kb
Host smart-96b2f25f-b7a6-423e-ba7e-29d140d52779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026179868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3026179868
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2898335296
Short name T552
Test name
Test status
Simulation time 101246581 ps
CPU time 0.55 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:16 PM PDT 24
Peak memory 182496 kb
Host smart-db324e61-628c-4629-a644-55ee14d02a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898335296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2898335296
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.736340674
Short name T565
Test name
Test status
Simulation time 13361692 ps
CPU time 0.6 seconds
Started May 07 03:02:15 PM PDT 24
Finished May 07 03:02:17 PM PDT 24
Peak memory 182692 kb
Host smart-ac983c10-1352-431a-9edf-89b03e8b6514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736340674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.736340674
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.903999243
Short name T516
Test name
Test status
Simulation time 12629365 ps
CPU time 0.56 seconds
Started May 07 03:02:12 PM PDT 24
Finished May 07 03:02:14 PM PDT 24
Peak memory 182688 kb
Host smart-d1d32285-1afd-4227-af04-c956bf5a2bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903999243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.903999243
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1132979832
Short name T538
Test name
Test status
Simulation time 18177339 ps
CPU time 0.58 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:15 PM PDT 24
Peak memory 182668 kb
Host smart-84c5f365-dc16-4618-99c3-db2776b812be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132979832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1132979832
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.861303913
Short name T551
Test name
Test status
Simulation time 32257590 ps
CPU time 0.53 seconds
Started May 07 03:02:12 PM PDT 24
Finished May 07 03:02:14 PM PDT 24
Peak memory 182660 kb
Host smart-db73d535-a6e1-4c80-bdfa-e5da2c89bb0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861303913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.861303913
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4138451472
Short name T573
Test name
Test status
Simulation time 101074913 ps
CPU time 0.88 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:54 PM PDT 24
Peak memory 197412 kb
Host smart-9d77840f-4cfd-42c4-90dc-007ae2345875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138451472 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.4138451472
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1703700175
Short name T556
Test name
Test status
Simulation time 13622594 ps
CPU time 0.54 seconds
Started May 07 03:01:50 PM PDT 24
Finished May 07 03:01:52 PM PDT 24
Peak memory 182748 kb
Host smart-9fa10142-e90c-4249-ba88-8ad0f5cb46c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703700175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1703700175
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1408642973
Short name T457
Test name
Test status
Simulation time 11706940 ps
CPU time 0.51 seconds
Started May 07 03:01:48 PM PDT 24
Finished May 07 03:01:50 PM PDT 24
Peak memory 182136 kb
Host smart-8bf12461-40e0-472b-a7c1-61f9a4567178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408642973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1408642973
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2528722386
Short name T57
Test name
Test status
Simulation time 65242949 ps
CPU time 0.64 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:53 PM PDT 24
Peak memory 191712 kb
Host smart-f8d5398a-94a3-4b38-9d01-ee3b6b011ea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528722386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2528722386
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.80021591
Short name T562
Test name
Test status
Simulation time 167733655 ps
CPU time 1.71 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:52 PM PDT 24
Peak memory 197600 kb
Host smart-4313f3bc-b192-4455-97f9-6f2a29af74f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80021591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.80021591
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3069842098
Short name T496
Test name
Test status
Simulation time 124408641 ps
CPU time 0.83 seconds
Started May 07 03:01:49 PM PDT 24
Finished May 07 03:01:52 PM PDT 24
Peak memory 193848 kb
Host smart-a79180e0-1a61-4d44-ba50-3613dc5ad805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069842098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3069842098
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3534454021
Short name T558
Test name
Test status
Simulation time 46179813 ps
CPU time 0.81 seconds
Started May 07 03:01:53 PM PDT 24
Finished May 07 03:01:55 PM PDT 24
Peak memory 195520 kb
Host smart-abc0f44f-adff-499f-ae35-5ac7f9c989ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534454021 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3534454021
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3765716037
Short name T530
Test name
Test status
Simulation time 14211739 ps
CPU time 0.59 seconds
Started May 07 03:01:53 PM PDT 24
Finished May 07 03:01:55 PM PDT 24
Peak memory 191864 kb
Host smart-bd92ba6c-a751-4d5a-ae23-b441140650c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765716037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3765716037
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1062068807
Short name T571
Test name
Test status
Simulation time 24775856 ps
CPU time 0.56 seconds
Started May 07 03:01:52 PM PDT 24
Finished May 07 03:01:54 PM PDT 24
Peak memory 182736 kb
Host smart-f915ea88-d619-4a45-ba39-cb5302fb9c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062068807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1062068807
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.192072735
Short name T557
Test name
Test status
Simulation time 95005094 ps
CPU time 0.77 seconds
Started May 07 03:01:53 PM PDT 24
Finished May 07 03:01:55 PM PDT 24
Peak memory 191676 kb
Host smart-024f1de1-85dc-4459-9641-ea2436df3484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192072735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.192072735
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1690179512
Short name T541
Test name
Test status
Simulation time 358116401 ps
CPU time 3.54 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:56 PM PDT 24
Peak memory 197696 kb
Host smart-a065eba9-8099-4197-8df9-b6454e1863bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690179512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1690179512
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1190934034
Short name T480
Test name
Test status
Simulation time 365144646 ps
CPU time 0.81 seconds
Started May 07 03:01:51 PM PDT 24
Finished May 07 03:01:54 PM PDT 24
Peak memory 192764 kb
Host smart-91d2c368-021b-4a08-9316-3dd080265794
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190934034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1190934034
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1991417902
Short name T491
Test name
Test status
Simulation time 91733745 ps
CPU time 1.17 seconds
Started May 07 03:01:57 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 197680 kb
Host smart-43e0afb4-b667-4ba2-8fb2-e8b289d7799a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991417902 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1991417902
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1952635687
Short name T101
Test name
Test status
Simulation time 16782533 ps
CPU time 0.57 seconds
Started May 07 03:01:55 PM PDT 24
Finished May 07 03:01:58 PM PDT 24
Peak memory 182592 kb
Host smart-b8367ca0-95b7-4ab1-a69e-bbf52c0bd8bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952635687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1952635687
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1955129598
Short name T533
Test name
Test status
Simulation time 18258195 ps
CPU time 0.56 seconds
Started May 07 03:01:55 PM PDT 24
Finished May 07 03:01:58 PM PDT 24
Peak memory 182664 kb
Host smart-fc3b00d3-045e-48c3-afd5-801206cf0bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955129598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1955129598
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3584078572
Short name T517
Test name
Test status
Simulation time 113084753 ps
CPU time 0.69 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:57 PM PDT 24
Peak memory 192232 kb
Host smart-f3a9fa81-4a3d-41f8-9361-9c243ace5e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584078572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3584078572
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2337200712
Short name T47
Test name
Test status
Simulation time 57657395 ps
CPU time 1.2 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:58 PM PDT 24
Peak memory 197656 kb
Host smart-4722c05b-be72-49f7-bfc3-ad71d8446c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337200712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2337200712
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2201423760
Short name T561
Test name
Test status
Simulation time 43453816 ps
CPU time 0.83 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:01:59 PM PDT 24
Peak memory 193516 kb
Host smart-b3f48718-4274-4360-ae33-9244da2b1c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201423760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2201423760
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1795229693
Short name T567
Test name
Test status
Simulation time 132882946 ps
CPU time 0.78 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 195432 kb
Host smart-f6e4bc06-d9ea-410a-8c1a-011754c125d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795229693 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1795229693
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3364905063
Short name T581
Test name
Test status
Simulation time 15225703 ps
CPU time 0.53 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:56 PM PDT 24
Peak memory 182776 kb
Host smart-8260d1a2-b95b-4c9b-9853-c060c1417034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364905063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3364905063
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4224639561
Short name T570
Test name
Test status
Simulation time 14176292 ps
CPU time 0.59 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:56 PM PDT 24
Peak memory 182604 kb
Host smart-64333eda-729e-4db5-adc7-f8c5b24a575b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224639561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4224639561
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.477559609
Short name T569
Test name
Test status
Simulation time 51317453 ps
CPU time 0.71 seconds
Started May 07 03:01:54 PM PDT 24
Finished May 07 03:01:56 PM PDT 24
Peak memory 191700 kb
Host smart-6d7b5859-a25b-4e84-8990-e73177db2e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477559609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.477559609
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3706791650
Short name T519
Test name
Test status
Simulation time 115438903 ps
CPU time 2.39 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:02:01 PM PDT 24
Peak memory 197564 kb
Host smart-47765cf7-d1a0-442b-9f0c-d7e7a499df5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706791650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3706791650
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2863229788
Short name T499
Test name
Test status
Simulation time 225326335 ps
CPU time 1.37 seconds
Started May 07 03:01:57 PM PDT 24
Finished May 07 03:02:01 PM PDT 24
Peak memory 195452 kb
Host smart-3be565f5-f556-40fc-b63b-54377eeec1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863229788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2863229788
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2189631465
Short name T550
Test name
Test status
Simulation time 73708755 ps
CPU time 1.08 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 197508 kb
Host smart-57120339-ff74-48f8-9ef1-7bc60dcaa99e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189631465 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2189631465
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.294825478
Short name T494
Test name
Test status
Simulation time 14694462 ps
CPU time 0.59 seconds
Started May 07 03:01:55 PM PDT 24
Finished May 07 03:01:59 PM PDT 24
Peak memory 182756 kb
Host smart-12744775-7f63-42fe-b371-163b266b877d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294825478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.294825478
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1458902421
Short name T490
Test name
Test status
Simulation time 76512911 ps
CPU time 0.55 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:01:59 PM PDT 24
Peak memory 182724 kb
Host smart-ae6f22a1-5e8d-496a-a131-713962f011da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458902421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1458902421
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3720459601
Short name T115
Test name
Test status
Simulation time 32825394 ps
CPU time 0.7 seconds
Started May 07 03:01:56 PM PDT 24
Finished May 07 03:01:59 PM PDT 24
Peak memory 193304 kb
Host smart-e0d54ed5-a918-4b87-8be0-1c8d64c8b74d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720459601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3720459601
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.501127410
Short name T574
Test name
Test status
Simulation time 1164528620 ps
CPU time 2.03 seconds
Started May 07 03:01:55 PM PDT 24
Finished May 07 03:02:00 PM PDT 24
Peak memory 197640 kb
Host smart-975cc09b-410a-40f8-8529-026922222bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501127410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.501127410
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.443131213
Short name T510
Test name
Test status
Simulation time 159229216 ps
CPU time 0.85 seconds
Started May 07 03:01:53 PM PDT 24
Finished May 07 03:01:56 PM PDT 24
Peak memory 193560 kb
Host smart-16d38704-1db4-4e26-a032-e74ead573fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443131213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.443131213
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.746207376
Short name T413
Test name
Test status
Simulation time 17271052195 ps
CPU time 28.48 seconds
Started May 07 01:07:21 PM PDT 24
Finished May 07 01:07:50 PM PDT 24
Peak memory 183060 kb
Host smart-aabf9b33-7edc-4d98-b533-cddf19658db6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746207376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.746207376
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3059008163
Short name T42
Test name
Test status
Simulation time 86194946686 ps
CPU time 79.51 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:08:42 PM PDT 24
Peak memory 183064 kb
Host smart-97cf4e1c-c789-4f33-9c1c-29e17919d2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059008163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3059008163
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1796598712
Short name T309
Test name
Test status
Simulation time 9823369875 ps
CPU time 16.84 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:07:41 PM PDT 24
Peak memory 191220 kb
Host smart-ef4bec39-36b5-4cbd-9a89-cc8bb7eb95a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796598712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1796598712
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2865679320
Short name T391
Test name
Test status
Simulation time 723816515787 ps
CPU time 493.65 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:15:37 PM PDT 24
Peak memory 191244 kb
Host smart-d20fcbe1-8804-4a64-a1c1-dbd4ff026440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865679320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2865679320
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1441351541
Short name T137
Test name
Test status
Simulation time 719641258155 ps
CPU time 1047.54 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:24:52 PM PDT 24
Peak memory 183032 kb
Host smart-8939021e-33b3-48bc-a3ab-83a511f92722
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441351541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1441351541
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3530752925
Short name T335
Test name
Test status
Simulation time 28674573304 ps
CPU time 43.03 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:08:06 PM PDT 24
Peak memory 183036 kb
Host smart-66d76b35-73a5-4f36-80bd-6700d8f5ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530752925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3530752925
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.69545985
Short name T16
Test name
Test status
Simulation time 84534485 ps
CPU time 0.9 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:07:25 PM PDT 24
Peak memory 214596 kb
Host smart-a2aabda5-c360-49cd-a2e7-e8ad07ce1e99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69545985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.69545985
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3459773585
Short name T230
Test name
Test status
Simulation time 33907545698 ps
CPU time 21.21 seconds
Started May 07 01:07:35 PM PDT 24
Finished May 07 01:07:57 PM PDT 24
Peak memory 183084 kb
Host smart-2e95f2ca-34ec-49da-a3f3-4cc6feeb94c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459773585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3459773585
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.690482700
Short name T415
Test name
Test status
Simulation time 201430197965 ps
CPU time 30.96 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:08:03 PM PDT 24
Peak memory 183060 kb
Host smart-6d74abc9-fbf2-4bf5-b322-f840c2463446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690482700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.690482700
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3129785293
Short name T255
Test name
Test status
Simulation time 307504658195 ps
CPU time 243.33 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:11:36 PM PDT 24
Peak memory 191260 kb
Host smart-d65c32fb-7a89-43e2-826f-d6377ed13ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129785293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3129785293
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2344885584
Short name T323
Test name
Test status
Simulation time 49608127155 ps
CPU time 77.7 seconds
Started May 07 01:07:30 PM PDT 24
Finished May 07 01:08:49 PM PDT 24
Peak memory 191244 kb
Host smart-62f9600b-0644-4674-b440-c96415c39439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344885584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2344885584
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/103.rv_timer_random.1815821053
Short name T175
Test name
Test status
Simulation time 94413945986 ps
CPU time 164.36 seconds
Started May 07 01:09:05 PM PDT 24
Finished May 07 01:11:50 PM PDT 24
Peak memory 191192 kb
Host smart-095ba926-a919-4c25-a49a-cb89e1dd4e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815821053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1815821053
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.672423948
Short name T449
Test name
Test status
Simulation time 80803710121 ps
CPU time 161.64 seconds
Started May 07 01:09:06 PM PDT 24
Finished May 07 01:11:48 PM PDT 24
Peak memory 191228 kb
Host smart-d0095ef9-ff9f-4bb0-bf1c-a27eb2489f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672423948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.672423948
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1800789455
Short name T41
Test name
Test status
Simulation time 294659137741 ps
CPU time 115.16 seconds
Started May 07 01:09:05 PM PDT 24
Finished May 07 01:11:01 PM PDT 24
Peak memory 191256 kb
Host smart-497439f3-6a3e-4502-bb58-f41ab18d2a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800789455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1800789455
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1398020702
Short name T89
Test name
Test status
Simulation time 59461625942 ps
CPU time 349.32 seconds
Started May 07 01:09:06 PM PDT 24
Finished May 07 01:14:56 PM PDT 24
Peak memory 191264 kb
Host smart-3eb9479d-d940-44c2-bdb2-bb2010485c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398020702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1398020702
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.4249144690
Short name T448
Test name
Test status
Simulation time 74242973563 ps
CPU time 81.56 seconds
Started May 07 01:09:12 PM PDT 24
Finished May 07 01:10:34 PM PDT 24
Peak memory 183108 kb
Host smart-4d69694c-1590-44e6-9bd7-e1b755a4f838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249144690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.4249144690
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3072267670
Short name T437
Test name
Test status
Simulation time 88430152271 ps
CPU time 146.81 seconds
Started May 07 01:09:14 PM PDT 24
Finished May 07 01:11:42 PM PDT 24
Peak memory 191240 kb
Host smart-a7413df1-3a1e-45c8-9282-bf727534b5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072267670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3072267670
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.229986044
Short name T442
Test name
Test status
Simulation time 370204747411 ps
CPU time 174.68 seconds
Started May 07 01:07:33 PM PDT 24
Finished May 07 01:10:29 PM PDT 24
Peak memory 183068 kb
Host smart-d96c97c4-fcd0-4d20-b434-e51ee8510fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229986044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.229986044
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.4176746304
Short name T325
Test name
Test status
Simulation time 213038926485 ps
CPU time 552.35 seconds
Started May 07 01:07:32 PM PDT 24
Finished May 07 01:16:45 PM PDT 24
Peak memory 191244 kb
Host smart-39da7a22-dbc0-4a5b-a8e9-b7a243c98ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176746304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4176746304
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2732122191
Short name T93
Test name
Test status
Simulation time 571933863514 ps
CPU time 220.4 seconds
Started May 07 01:07:32 PM PDT 24
Finished May 07 01:11:14 PM PDT 24
Peak memory 183064 kb
Host smart-f6e4db11-b3de-44b9-9b25-b613668caa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732122191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2732122191
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4040003586
Short name T142
Test name
Test status
Simulation time 370515196381 ps
CPU time 582.17 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:17:14 PM PDT 24
Peak memory 191216 kb
Host smart-c488a8ad-9fc7-4f13-a040-427192000856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040003586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4040003586
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.2614405573
Short name T296
Test name
Test status
Simulation time 356508134863 ps
CPU time 182.19 seconds
Started May 07 01:09:18 PM PDT 24
Finished May 07 01:12:21 PM PDT 24
Peak memory 191264 kb
Host smart-33a5a93f-a697-4b83-a5bb-59ddc1881689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614405573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2614405573
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1609121708
Short name T288
Test name
Test status
Simulation time 30539036593 ps
CPU time 13.83 seconds
Started May 07 01:09:16 PM PDT 24
Finished May 07 01:09:30 PM PDT 24
Peak memory 183056 kb
Host smart-4084bb53-229b-4c14-a8a9-f88ee601e7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609121708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1609121708
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3946077969
Short name T293
Test name
Test status
Simulation time 43676106440 ps
CPU time 78.63 seconds
Started May 07 01:09:12 PM PDT 24
Finished May 07 01:10:31 PM PDT 24
Peak memory 183052 kb
Host smart-7191e575-c6be-4613-9e53-e56244d22d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946077969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3946077969
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3625899060
Short name T139
Test name
Test status
Simulation time 141079577397 ps
CPU time 131.64 seconds
Started May 07 01:09:11 PM PDT 24
Finished May 07 01:11:23 PM PDT 24
Peak memory 193480 kb
Host smart-4b82e83c-56d2-4168-b2dc-b9687068e497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625899060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3625899060
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.4163623628
Short name T444
Test name
Test status
Simulation time 10790996071 ps
CPU time 8.74 seconds
Started May 07 01:09:20 PM PDT 24
Finished May 07 01:09:30 PM PDT 24
Peak memory 183036 kb
Host smart-03db19e2-b249-453b-923b-5be4f538a9db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163623628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4163623628
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2991228162
Short name T246
Test name
Test status
Simulation time 259347826809 ps
CPU time 299.06 seconds
Started May 07 01:09:22 PM PDT 24
Finished May 07 01:14:22 PM PDT 24
Peak memory 191088 kb
Host smart-23ffee1c-8ae7-40e9-bf1d-f39825d40118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991228162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2991228162
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.17027906
Short name T19
Test name
Test status
Simulation time 164838475732 ps
CPU time 311.65 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:12:44 PM PDT 24
Peak memory 183048 kb
Host smart-baee029e-b6cf-4c8d-bdd9-9df41f0f48b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17027906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.rv_timer_cfg_update_on_fly.17027906
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2278985310
Short name T361
Test name
Test status
Simulation time 300686723690 ps
CPU time 121.16 seconds
Started May 07 01:07:30 PM PDT 24
Finished May 07 01:09:32 PM PDT 24
Peak memory 183064 kb
Host smart-20c128f7-abc2-4995-9daa-dce0a2d8acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278985310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2278985310
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3950960587
Short name T356
Test name
Test status
Simulation time 62099143717 ps
CPU time 120.08 seconds
Started May 07 01:07:42 PM PDT 24
Finished May 07 01:09:43 PM PDT 24
Peak memory 191260 kb
Host smart-9eb6bc25-8403-4449-99fd-8476d55f36f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950960587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3950960587
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3115321565
Short name T298
Test name
Test status
Simulation time 172197653451 ps
CPU time 407.31 seconds
Started May 07 01:07:43 PM PDT 24
Finished May 07 01:14:31 PM PDT 24
Peak memory 183044 kb
Host smart-a5723afc-42ae-4e9f-9f64-b03787c1ffd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115321565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3115321565
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.2862887688
Short name T56
Test name
Test status
Simulation time 200253100616 ps
CPU time 561.15 seconds
Started May 07 01:09:21 PM PDT 24
Finished May 07 01:18:44 PM PDT 24
Peak memory 191140 kb
Host smart-23fca6fa-8d75-4607-bae5-5c5396f54173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862887688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2862887688
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.4140902491
Short name T187
Test name
Test status
Simulation time 57054127933 ps
CPU time 112.49 seconds
Started May 07 01:09:20 PM PDT 24
Finished May 07 01:11:14 PM PDT 24
Peak memory 191208 kb
Host smart-d8441bcd-ffc7-48fb-9e8e-85eb34bf1340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140902491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.4140902491
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3500282362
Short name T284
Test name
Test status
Simulation time 128540487339 ps
CPU time 392.27 seconds
Started May 07 01:09:21 PM PDT 24
Finished May 07 01:15:54 PM PDT 24
Peak memory 191244 kb
Host smart-4463f098-31c6-4896-95b8-1910a1f07044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500282362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3500282362
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.359287191
Short name T191
Test name
Test status
Simulation time 396844983352 ps
CPU time 532.58 seconds
Started May 07 01:09:23 PM PDT 24
Finished May 07 01:18:17 PM PDT 24
Peak memory 191244 kb
Host smart-65c9a516-88ed-4c76-b0d0-c3980f349aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359287191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.359287191
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.469472189
Short name T174
Test name
Test status
Simulation time 54916881023 ps
CPU time 142.01 seconds
Started May 07 01:09:20 PM PDT 24
Finished May 07 01:11:44 PM PDT 24
Peak memory 191228 kb
Host smart-eee0bb7a-edc7-41f1-bb46-244765e509c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469472189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.469472189
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1186909060
Short name T261
Test name
Test status
Simulation time 1377310667137 ps
CPU time 727.59 seconds
Started May 07 01:07:37 PM PDT 24
Finished May 07 01:19:45 PM PDT 24
Peak memory 183020 kb
Host smart-fe5c479f-87f9-415e-b486-bc590d574f7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186909060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1186909060
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.4267964654
Short name T429
Test name
Test status
Simulation time 133626485510 ps
CPU time 208.82 seconds
Started May 07 01:07:37 PM PDT 24
Finished May 07 01:11:07 PM PDT 24
Peak memory 183012 kb
Host smart-779a7d23-0b0a-4f81-831c-ac1ff43700c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267964654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.4267964654
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3235816721
Short name T440
Test name
Test status
Simulation time 40526594087 ps
CPU time 55.34 seconds
Started May 07 01:07:48 PM PDT 24
Finished May 07 01:08:44 PM PDT 24
Peak memory 191248 kb
Host smart-29d750ef-0f59-49dc-86f6-cef367a9b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235816721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3235816721
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3026179236
Short name T28
Test name
Test status
Simulation time 1013086701822 ps
CPU time 2136.36 seconds
Started May 07 01:07:37 PM PDT 24
Finished May 07 01:43:14 PM PDT 24
Peak memory 191340 kb
Host smart-dac1bccc-691e-4baf-96c8-989ec4930b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026179236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3026179236
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.3867215666
Short name T405
Test name
Test status
Simulation time 250594016913 ps
CPU time 92.3 seconds
Started May 07 01:09:21 PM PDT 24
Finished May 07 01:10:55 PM PDT 24
Peak memory 192248 kb
Host smart-57a5221b-517c-4377-a26c-40b2bf9cec74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867215666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3867215666
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3973308227
Short name T251
Test name
Test status
Simulation time 93457393108 ps
CPU time 102.9 seconds
Started May 07 01:09:29 PM PDT 24
Finished May 07 01:11:13 PM PDT 24
Peak memory 183040 kb
Host smart-e09030bd-aab7-4926-9712-db2642180366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973308227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3973308227
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.145438882
Short name T276
Test name
Test status
Simulation time 86030929601 ps
CPU time 147.17 seconds
Started May 07 01:09:31 PM PDT 24
Finished May 07 01:11:59 PM PDT 24
Peak memory 193620 kb
Host smart-3a3b2aa4-4652-4915-af6d-d305230cda98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145438882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.145438882
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3065789720
Short name T151
Test name
Test status
Simulation time 191904363092 ps
CPU time 125.68 seconds
Started May 07 01:09:28 PM PDT 24
Finished May 07 01:11:35 PM PDT 24
Peak memory 191244 kb
Host smart-ed10c2fe-851d-4a6e-8aa3-ec81167cc7c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065789720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3065789720
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2037449681
Short name T370
Test name
Test status
Simulation time 2044364489 ps
CPU time 1.43 seconds
Started May 07 01:07:41 PM PDT 24
Finished May 07 01:07:43 PM PDT 24
Peak memory 182712 kb
Host smart-ab7a6f43-4539-424a-8c2a-4f1e50b81307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037449681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2037449681
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1329840353
Short name T110
Test name
Test status
Simulation time 379107536544 ps
CPU time 355.82 seconds
Started May 07 01:07:40 PM PDT 24
Finished May 07 01:13:37 PM PDT 24
Peak memory 191252 kb
Host smart-27d0e838-4dbd-48a9-b684-d0cc8a680bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329840353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1329840353
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.116377523
Short name T408
Test name
Test status
Simulation time 10622376603 ps
CPU time 96.88 seconds
Started May 07 01:07:40 PM PDT 24
Finished May 07 01:09:18 PM PDT 24
Peak memory 193600 kb
Host smart-bcc5f104-635e-47c2-a114-384cbc5cdeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116377523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.116377523
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.1548807468
Short name T350
Test name
Test status
Simulation time 933918413908 ps
CPU time 1107.46 seconds
Started May 07 01:09:29 PM PDT 24
Finished May 07 01:27:57 PM PDT 24
Peak memory 191260 kb
Host smart-5cae0bf8-0da8-47cc-b8a9-d9e38474f8c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548807468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1548807468
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2709205230
Short name T153
Test name
Test status
Simulation time 1082499837108 ps
CPU time 479.89 seconds
Started May 07 01:09:27 PM PDT 24
Finished May 07 01:17:28 PM PDT 24
Peak memory 191176 kb
Host smart-ff00da9e-583c-461a-bf0e-434dc10bf921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709205230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2709205230
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1950703381
Short name T400
Test name
Test status
Simulation time 59369339767 ps
CPU time 57.48 seconds
Started May 07 01:09:31 PM PDT 24
Finished May 07 01:10:29 PM PDT 24
Peak memory 182916 kb
Host smart-f5f72d13-cbbd-47c3-a052-c4f632acb4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950703381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1950703381
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1512932250
Short name T438
Test name
Test status
Simulation time 100276947799 ps
CPU time 161.83 seconds
Started May 07 01:09:29 PM PDT 24
Finished May 07 01:12:12 PM PDT 24
Peak memory 191256 kb
Host smart-b6777d13-4a1f-422b-b7ef-b6ceb0ab667e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512932250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1512932250
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2723274338
Short name T9
Test name
Test status
Simulation time 38272889723 ps
CPU time 63.61 seconds
Started May 07 01:09:28 PM PDT 24
Finished May 07 01:10:32 PM PDT 24
Peak memory 183024 kb
Host smart-aaec9cd4-5301-4745-a3e3-4528b8d676b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723274338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2723274338
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.648397436
Short name T67
Test name
Test status
Simulation time 211458138165 ps
CPU time 281.6 seconds
Started May 07 01:09:29 PM PDT 24
Finished May 07 01:14:12 PM PDT 24
Peak memory 191244 kb
Host smart-bdd62a99-b8ae-417d-8b64-f30efda37801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648397436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.648397436
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2168709245
Short name T82
Test name
Test status
Simulation time 258356757187 ps
CPU time 728.55 seconds
Started May 07 01:09:38 PM PDT 24
Finished May 07 01:21:47 PM PDT 24
Peak memory 191244 kb
Host smart-4672cd8e-7c03-4989-9ec0-f6b0d574c210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168709245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2168709245
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1181294248
Short name T40
Test name
Test status
Simulation time 284796732116 ps
CPU time 541.66 seconds
Started May 07 01:07:48 PM PDT 24
Finished May 07 01:16:50 PM PDT 24
Peak memory 183064 kb
Host smart-23455989-307c-4c44-bbd5-88316269e81f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181294248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1181294248
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.706893688
Short name T369
Test name
Test status
Simulation time 244306806771 ps
CPU time 101.44 seconds
Started May 07 01:07:41 PM PDT 24
Finished May 07 01:09:23 PM PDT 24
Peak memory 183048 kb
Host smart-73a8c05c-e886-4a09-b1b1-66354b9350e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706893688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.706893688
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2496424982
Short name T359
Test name
Test status
Simulation time 655400000741 ps
CPU time 304.56 seconds
Started May 07 01:07:35 PM PDT 24
Finished May 07 01:12:41 PM PDT 24
Peak memory 191228 kb
Host smart-abbdaa67-e938-4aae-8320-075fe2a258e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496424982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2496424982
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3620977987
Short name T318
Test name
Test status
Simulation time 187330761028 ps
CPU time 317.58 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:13:03 PM PDT 24
Peak memory 183068 kb
Host smart-96aa1750-2bcd-4724-9e04-6265a20a42f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620977987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3620977987
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3431641539
Short name T279
Test name
Test status
Simulation time 1478084009226 ps
CPU time 1162.2 seconds
Started May 07 01:07:36 PM PDT 24
Finished May 07 01:26:59 PM PDT 24
Peak memory 191232 kb
Host smart-d1c2ffef-ca9c-488c-bcd1-b467400f7940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431641539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3431641539
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.829211234
Short name T31
Test name
Test status
Simulation time 103337205559 ps
CPU time 855.69 seconds
Started May 07 01:07:37 PM PDT 24
Finished May 07 01:21:53 PM PDT 24
Peak memory 207072 kb
Host smart-3ffc85bb-34e1-48fa-be64-54de7f5774f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829211234 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.829211234
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.1890250380
Short name T355
Test name
Test status
Simulation time 433900694124 ps
CPU time 517.81 seconds
Started May 07 01:09:36 PM PDT 24
Finished May 07 01:18:15 PM PDT 24
Peak memory 191460 kb
Host smart-38a0fa29-53c7-4166-b71a-9f0ba4732370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890250380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1890250380
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2252905045
Short name T275
Test name
Test status
Simulation time 6157939637 ps
CPU time 58.71 seconds
Started May 07 01:09:33 PM PDT 24
Finished May 07 01:10:33 PM PDT 24
Peak memory 183048 kb
Host smart-81a2bb3a-9b6d-4ac3-b99b-02d6c2d78838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252905045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2252905045
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1860167975
Short name T263
Test name
Test status
Simulation time 639517999925 ps
CPU time 382.24 seconds
Started May 07 01:09:38 PM PDT 24
Finished May 07 01:16:01 PM PDT 24
Peak memory 194848 kb
Host smart-d6c34891-250b-47d1-865d-1209788549b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860167975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1860167975
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2626306641
Short name T163
Test name
Test status
Simulation time 298935785583 ps
CPU time 160.31 seconds
Started May 07 01:09:34 PM PDT 24
Finished May 07 01:12:15 PM PDT 24
Peak memory 192268 kb
Host smart-ee93990b-10bc-45e0-8f1b-2b82bf760281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626306641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2626306641
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3315273760
Short name T322
Test name
Test status
Simulation time 3225338765082 ps
CPU time 884.45 seconds
Started May 07 01:09:33 PM PDT 24
Finished May 07 01:24:18 PM PDT 24
Peak memory 193220 kb
Host smart-fbbbae90-36da-4296-aa53-5ccf1ef0c0c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315273760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3315273760
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2972757155
Short name T301
Test name
Test status
Simulation time 394364594459 ps
CPU time 283.62 seconds
Started May 07 01:09:34 PM PDT 24
Finished May 07 01:14:18 PM PDT 24
Peak memory 191132 kb
Host smart-a0285fa9-7739-4d9a-a4c4-001264424cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972757155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2972757155
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.4228385336
Short name T221
Test name
Test status
Simulation time 282922507957 ps
CPU time 129.34 seconds
Started May 07 01:09:36 PM PDT 24
Finished May 07 01:11:46 PM PDT 24
Peak memory 191248 kb
Host smart-9a7f9924-ffdd-45b3-908c-f8c451c38bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228385336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4228385336
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3568564927
Short name T181
Test name
Test status
Simulation time 412848141925 ps
CPU time 346.28 seconds
Started May 07 01:07:41 PM PDT 24
Finished May 07 01:13:28 PM PDT 24
Peak memory 183064 kb
Host smart-3927d7da-d7c5-43ce-9618-e2f49a49c45a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568564927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3568564927
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3581860839
Short name T381
Test name
Test status
Simulation time 35052121234 ps
CPU time 57.57 seconds
Started May 07 01:07:39 PM PDT 24
Finished May 07 01:08:37 PM PDT 24
Peak memory 182912 kb
Host smart-84ccefc6-38dc-4493-b2f9-cd8638c5bed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581860839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3581860839
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/160.rv_timer_random.1019417690
Short name T158
Test name
Test status
Simulation time 78668527509 ps
CPU time 74.06 seconds
Started May 07 01:09:37 PM PDT 24
Finished May 07 01:10:52 PM PDT 24
Peak memory 183052 kb
Host smart-f945cf19-7fc0-4743-bc27-a88dfc851566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019417690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1019417690
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3614013073
Short name T352
Test name
Test status
Simulation time 118483272896 ps
CPU time 816.76 seconds
Started May 07 01:09:37 PM PDT 24
Finished May 07 01:23:15 PM PDT 24
Peak memory 191460 kb
Host smart-d2a59821-bcbf-4a71-9366-2fc463a3b85b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614013073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3614013073
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2052006783
Short name T94
Test name
Test status
Simulation time 247175136176 ps
CPU time 635.34 seconds
Started May 07 01:09:36 PM PDT 24
Finished May 07 01:20:13 PM PDT 24
Peak memory 191468 kb
Host smart-63bda0db-eaac-4299-8d70-779568ba5916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052006783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2052006783
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.924787479
Short name T48
Test name
Test status
Simulation time 145983813607 ps
CPU time 908.44 seconds
Started May 07 01:09:42 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 191260 kb
Host smart-666185ab-3258-4b6e-9b1d-6424bd622c84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924787479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.924787479
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3852644931
Short name T447
Test name
Test status
Simulation time 52373177313 ps
CPU time 42.37 seconds
Started May 07 01:09:43 PM PDT 24
Finished May 07 01:10:26 PM PDT 24
Peak memory 183052 kb
Host smart-0727eb6b-d1f6-479e-a8f8-6785f4050cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852644931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3852644931
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3255892889
Short name T104
Test name
Test status
Simulation time 123906834582 ps
CPU time 73.1 seconds
Started May 07 01:07:39 PM PDT 24
Finished May 07 01:08:52 PM PDT 24
Peak memory 183268 kb
Host smart-f189a275-8d7f-4330-ae56-beed154e7e41
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255892889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3255892889
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.4089730508
Short name T410
Test name
Test status
Simulation time 78047869040 ps
CPU time 123.34 seconds
Started May 07 01:07:38 PM PDT 24
Finished May 07 01:09:42 PM PDT 24
Peak memory 183088 kb
Host smart-61a4f183-90b1-485a-a317-36fe1f1e7ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089730508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.4089730508
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1096511826
Short name T427
Test name
Test status
Simulation time 166355956266 ps
CPU time 2587.03 seconds
Started May 07 01:07:39 PM PDT 24
Finished May 07 01:50:47 PM PDT 24
Peak memory 191212 kb
Host smart-1a7f7f2c-d07b-4537-99db-c0dd465a2922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096511826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1096511826
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3328512263
Short name T210
Test name
Test status
Simulation time 11522472811 ps
CPU time 5.84 seconds
Started May 07 01:07:36 PM PDT 24
Finished May 07 01:07:43 PM PDT 24
Peak memory 193684 kb
Host smart-0b123f74-0cea-433c-8fc6-d160e20de23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328512263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3328512263
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.600856316
Short name T184
Test name
Test status
Simulation time 117102981827 ps
CPU time 218.04 seconds
Started May 07 01:09:43 PM PDT 24
Finished May 07 01:13:21 PM PDT 24
Peak memory 191252 kb
Host smart-56bc8ece-8037-4a2b-8beb-d9faaa364445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600856316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.600856316
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.234318264
Short name T321
Test name
Test status
Simulation time 686087958675 ps
CPU time 436.1 seconds
Started May 07 01:09:41 PM PDT 24
Finished May 07 01:16:58 PM PDT 24
Peak memory 191236 kb
Host smart-f24ae756-e404-4f56-9f78-62cef2172a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234318264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.234318264
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3072877267
Short name T428
Test name
Test status
Simulation time 350115245825 ps
CPU time 180.26 seconds
Started May 07 01:09:41 PM PDT 24
Finished May 07 01:12:43 PM PDT 24
Peak memory 191252 kb
Host smart-dfd07ebb-9795-4196-9ff6-e128a806445a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072877267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3072877267
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1924128997
Short name T328
Test name
Test status
Simulation time 108595835951 ps
CPU time 1533.38 seconds
Started May 07 01:09:45 PM PDT 24
Finished May 07 01:35:19 PM PDT 24
Peak memory 191252 kb
Host smart-ed912678-1c94-4d74-9ebd-a66183b204cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924128997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1924128997
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3447605301
Short name T179
Test name
Test status
Simulation time 16881166237 ps
CPU time 98.53 seconds
Started May 07 01:09:42 PM PDT 24
Finished May 07 01:11:21 PM PDT 24
Peak memory 183068 kb
Host smart-dd7da70a-eaeb-4186-abb6-a35ed329b65a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447605301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3447605301
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.646562938
Short name T347
Test name
Test status
Simulation time 425655853508 ps
CPU time 215.99 seconds
Started May 07 01:09:43 PM PDT 24
Finished May 07 01:13:19 PM PDT 24
Peak memory 191240 kb
Host smart-1127928c-c7c0-4be8-874a-fcc204657ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646562938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.646562938
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2930339640
Short name T285
Test name
Test status
Simulation time 231894821365 ps
CPU time 133.97 seconds
Started May 07 01:09:44 PM PDT 24
Finished May 07 01:11:59 PM PDT 24
Peak memory 191252 kb
Host smart-9c22ad23-8590-4b34-ab96-36b68f1c493e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930339640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2930339640
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.87118140
Short name T167
Test name
Test status
Simulation time 571973357054 ps
CPU time 966.9 seconds
Started May 07 01:07:41 PM PDT 24
Finished May 07 01:23:49 PM PDT 24
Peak memory 183236 kb
Host smart-76bfd35c-9927-4061-bfed-5d2bebcd2908
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87118140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.rv_timer_cfg_update_on_fly.87118140
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.884609261
Short name T371
Test name
Test status
Simulation time 128043228469 ps
CPU time 88.23 seconds
Started May 07 01:07:39 PM PDT 24
Finished May 07 01:09:08 PM PDT 24
Peak memory 183068 kb
Host smart-d29c3769-223d-43d8-bada-913b480a10ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884609261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.884609261
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.4249063511
Short name T38
Test name
Test status
Simulation time 54636168733 ps
CPU time 95.2 seconds
Started May 07 01:07:38 PM PDT 24
Finished May 07 01:09:14 PM PDT 24
Peak memory 194048 kb
Host smart-2c6c6cb2-5b5d-4d33-9742-7d503e482bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249063511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4249063511
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3406325095
Short name T51
Test name
Test status
Simulation time 102044692467 ps
CPU time 61.72 seconds
Started May 07 01:07:40 PM PDT 24
Finished May 07 01:08:43 PM PDT 24
Peak memory 191256 kb
Host smart-98971976-d88e-40e9-8f83-8037eefed960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406325095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3406325095
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3171235215
Short name T403
Test name
Test status
Simulation time 380032153944 ps
CPU time 146.03 seconds
Started May 07 01:07:36 PM PDT 24
Finished May 07 01:10:03 PM PDT 24
Peak memory 195608 kb
Host smart-8840b6d4-0dc3-40bd-8ff9-13040e6ebfee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171235215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3171235215
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.2403323366
Short name T140
Test name
Test status
Simulation time 1032268778554 ps
CPU time 1888.56 seconds
Started May 07 01:09:50 PM PDT 24
Finished May 07 01:41:19 PM PDT 24
Peak memory 191256 kb
Host smart-57debeab-1aaf-4210-a140-e3ac4308d4b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403323366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2403323366
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3107446074
Short name T351
Test name
Test status
Simulation time 146257780040 ps
CPU time 97.39 seconds
Started May 07 01:09:49 PM PDT 24
Finished May 07 01:11:28 PM PDT 24
Peak memory 183056 kb
Host smart-12b63d62-f6d2-4beb-b2f2-0bef270c124f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107446074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3107446074
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2127388747
Short name T136
Test name
Test status
Simulation time 97753567670 ps
CPU time 298.32 seconds
Started May 07 01:09:51 PM PDT 24
Finished May 07 01:14:50 PM PDT 24
Peak memory 191244 kb
Host smart-512e22db-88ef-4943-b507-8be0f39ff3a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127388747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2127388747
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3861458223
Short name T171
Test name
Test status
Simulation time 198479667540 ps
CPU time 530.69 seconds
Started May 07 01:09:50 PM PDT 24
Finished May 07 01:18:42 PM PDT 24
Peak memory 191332 kb
Host smart-605ad3eb-ff81-4639-8c52-11e0b7887184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861458223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3861458223
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3005035112
Short name T233
Test name
Test status
Simulation time 203822678306 ps
CPU time 555.58 seconds
Started May 07 01:09:49 PM PDT 24
Finished May 07 01:19:05 PM PDT 24
Peak memory 183056 kb
Host smart-79491e5a-7480-4112-8777-89559946d2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005035112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3005035112
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3784307844
Short name T287
Test name
Test status
Simulation time 77454567934 ps
CPU time 126.9 seconds
Started May 07 01:09:50 PM PDT 24
Finished May 07 01:11:58 PM PDT 24
Peak memory 191252 kb
Host smart-89089690-0f81-4e05-a59e-130519c97cb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784307844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3784307844
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2333565578
Short name T311
Test name
Test status
Simulation time 890309307257 ps
CPU time 404.82 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:14:32 PM PDT 24
Peak memory 182988 kb
Host smart-67aa2cc8-e387-499e-bbb7-695d171b0ee9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333565578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2333565578
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2246177881
Short name T393
Test name
Test status
Simulation time 912586597279 ps
CPU time 242.63 seconds
Started May 07 01:07:43 PM PDT 24
Finished May 07 01:11:47 PM PDT 24
Peak memory 183036 kb
Host smart-f3fc8cd6-eb41-492d-bdbd-e32ffa878aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246177881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2246177881
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.525232524
Short name T70
Test name
Test status
Simulation time 111556587966 ps
CPU time 86.49 seconds
Started May 07 01:07:48 PM PDT 24
Finished May 07 01:09:15 PM PDT 24
Peak memory 183032 kb
Host smart-6fecf648-2d5e-4076-bd80-8817a7fe4a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525232524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.525232524
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.620550462
Short name T453
Test name
Test status
Simulation time 48367405209 ps
CPU time 112.34 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:09:37 PM PDT 24
Peak memory 191248 kb
Host smart-72965a0e-1d20-429e-a908-26c549591584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620550462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.620550462
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.738256694
Short name T55
Test name
Test status
Simulation time 57745603235 ps
CPU time 87.36 seconds
Started May 07 01:09:58 PM PDT 24
Finished May 07 01:11:26 PM PDT 24
Peak memory 191152 kb
Host smart-caaa9943-fb51-4a33-b567-db411d4a8aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738256694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.738256694
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3841328349
Short name T123
Test name
Test status
Simulation time 171007644686 ps
CPU time 1365.09 seconds
Started May 07 01:10:00 PM PDT 24
Finished May 07 01:32:46 PM PDT 24
Peak memory 191204 kb
Host smart-11b7af39-e122-41f5-a2af-b54d9855e0d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841328349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3841328349
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1575220323
Short name T256
Test name
Test status
Simulation time 331061871920 ps
CPU time 162.53 seconds
Started May 07 01:09:59 PM PDT 24
Finished May 07 01:12:42 PM PDT 24
Peak memory 191232 kb
Host smart-3c9b9608-1a24-477e-8f1e-724ff873e866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575220323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1575220323
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1054455511
Short name T209
Test name
Test status
Simulation time 592359016302 ps
CPU time 332.62 seconds
Started May 07 01:09:58 PM PDT 24
Finished May 07 01:15:31 PM PDT 24
Peak memory 191260 kb
Host smart-178c1c77-5d90-4840-b1c5-0141e499ece3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054455511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1054455511
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3051272421
Short name T424
Test name
Test status
Simulation time 174406655528 ps
CPU time 711.25 seconds
Started May 07 01:09:58 PM PDT 24
Finished May 07 01:21:50 PM PDT 24
Peak memory 191200 kb
Host smart-73d069b2-d648-4f82-b90a-c786be541379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051272421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3051272421
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1389290250
Short name T345
Test name
Test status
Simulation time 71597815672 ps
CPU time 132.96 seconds
Started May 07 01:10:07 PM PDT 24
Finished May 07 01:12:21 PM PDT 24
Peak memory 191220 kb
Host smart-7a3514f3-2954-407d-91d7-1fb54d096a08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389290250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1389290250
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1480918198
Short name T384
Test name
Test status
Simulation time 301048245637 ps
CPU time 124.22 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:09:28 PM PDT 24
Peak memory 183024 kb
Host smart-70e865df-df04-4055-a27c-fbdd12d1a429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480918198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1480918198
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1262929248
Short name T144
Test name
Test status
Simulation time 31351238979 ps
CPU time 16.67 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:07:41 PM PDT 24
Peak memory 183072 kb
Host smart-caaa97db-b6d7-44c7-b2ac-2b71836afb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262929248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1262929248
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1046058437
Short name T157
Test name
Test status
Simulation time 191041328736 ps
CPU time 99.73 seconds
Started May 07 01:07:25 PM PDT 24
Finished May 07 01:09:05 PM PDT 24
Peak memory 183084 kb
Host smart-d6987cf3-ace8-4cb8-b731-e9c79a420bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046058437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1046058437
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2287900234
Short name T15
Test name
Test status
Simulation time 39253788 ps
CPU time 0.72 seconds
Started May 07 01:07:26 PM PDT 24
Finished May 07 01:07:27 PM PDT 24
Peak memory 213488 kb
Host smart-c6ac4fb6-69fe-4f68-9821-bbe2130a3ff9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287900234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2287900234
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3938557776
Short name T20
Test name
Test status
Simulation time 107812371874 ps
CPU time 141.38 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:10:06 PM PDT 24
Peak memory 183048 kb
Host smart-5ac5a7c4-8e7a-4fb1-9389-aebd02cc7e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938557776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3938557776
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1087239349
Short name T120
Test name
Test status
Simulation time 32218354890 ps
CPU time 122.8 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:09:49 PM PDT 24
Peak memory 183060 kb
Host smart-0802f43c-a88d-4607-bbd2-9c31dbdbc6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087239349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1087239349
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2479276522
Short name T305
Test name
Test status
Simulation time 70705194577 ps
CPU time 102.66 seconds
Started May 07 01:07:51 PM PDT 24
Finished May 07 01:09:35 PM PDT 24
Peak memory 194792 kb
Host smart-b8c5a668-e624-462b-8631-0e24b84db12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479276522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2479276522
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2902612361
Short name T326
Test name
Test status
Simulation time 361639630072 ps
CPU time 283.62 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:12:30 PM PDT 24
Peak memory 191100 kb
Host smart-ecc7f915-0783-40b5-a8c0-fc1c5ad2a353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902612361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2902612361
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.122002835
Short name T224
Test name
Test status
Simulation time 1126785191967 ps
CPU time 610.39 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:17:57 PM PDT 24
Peak memory 183048 kb
Host smart-60833bc0-963f-4fc1-8782-4df638ee27ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122002835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.122002835
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2003855294
Short name T411
Test name
Test status
Simulation time 440336650364 ps
CPU time 188.74 seconds
Started May 07 01:07:46 PM PDT 24
Finished May 07 01:10:56 PM PDT 24
Peak memory 182964 kb
Host smart-cc6da115-5f50-4242-8f83-ecd621c1e258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003855294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2003855294
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2465393746
Short name T341
Test name
Test status
Simulation time 649168133 ps
CPU time 0.95 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:07:47 PM PDT 24
Peak memory 182812 kb
Host smart-cdd48508-befe-418b-b1c6-9041da8307b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465393746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2465393746
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4064730071
Short name T106
Test name
Test status
Simulation time 176640806676 ps
CPU time 302.55 seconds
Started May 07 01:07:46 PM PDT 24
Finished May 07 01:12:50 PM PDT 24
Peak memory 193024 kb
Host smart-1431de02-c112-4a17-83fb-ec2e60274ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064730071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4064730071
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1965816010
Short name T72
Test name
Test status
Simulation time 518184946571 ps
CPU time 267.44 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:12:13 PM PDT 24
Peak memory 183024 kb
Host smart-a8504681-6848-4685-b4d1-cbdc6b5b893e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965816010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1965816010
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.816685247
Short name T364
Test name
Test status
Simulation time 102569268565 ps
CPU time 161.63 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:10:27 PM PDT 24
Peak memory 183068 kb
Host smart-a201192a-c26b-4c05-9633-1433fa3f380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816685247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.816685247
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.544770239
Short name T205
Test name
Test status
Simulation time 127506305072 ps
CPU time 1700.74 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:36:08 PM PDT 24
Peak memory 191248 kb
Host smart-8c0e412d-2db2-47ec-ad48-f6cda195c76a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544770239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.544770239
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3337923048
Short name T334
Test name
Test status
Simulation time 1304173882 ps
CPU time 2.86 seconds
Started May 07 01:07:52 PM PDT 24
Finished May 07 01:07:56 PM PDT 24
Peak memory 183012 kb
Host smart-cebddc26-73ce-420a-bcec-7c1224adde85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337923048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3337923048
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3906376044
Short name T35
Test name
Test status
Simulation time 132152277636 ps
CPU time 574.53 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:17:21 PM PDT 24
Peak memory 208396 kb
Host smart-8864cf93-ec27-4ad9-b8af-e6208cb7eb81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906376044 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3906376044
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1904108858
Short name T239
Test name
Test status
Simulation time 2873095643486 ps
CPU time 1528.81 seconds
Started May 07 01:07:43 PM PDT 24
Finished May 07 01:33:13 PM PDT 24
Peak memory 183048 kb
Host smart-26fac489-7307-4477-b04a-85c29656c31d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904108858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1904108858
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.4041771010
Short name T77
Test name
Test status
Simulation time 91013054652 ps
CPU time 133.67 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:10:00 PM PDT 24
Peak memory 183048 kb
Host smart-04d61c90-56c2-444c-a2d7-727e9d7ab9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041771010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4041771010
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3342651312
Short name T385
Test name
Test status
Simulation time 225517237265 ps
CPU time 104.97 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:09:30 PM PDT 24
Peak memory 191212 kb
Host smart-f6263c31-4081-4204-a51e-a2b9622b9e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342651312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3342651312
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.14881093
Short name T401
Test name
Test status
Simulation time 48848845 ps
CPU time 0.92 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:07:46 PM PDT 24
Peak memory 182976 kb
Host smart-dc9d7302-9658-413c-afd7-85c7589ab492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14881093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.14881093
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2943266135
Short name T238
Test name
Test status
Simulation time 1842772709817 ps
CPU time 956.87 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:23:43 PM PDT 24
Peak memory 191268 kb
Host smart-fadc21a3-4ae4-45c3-83dd-d2e875002a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943266135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2943266135
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.971967986
Short name T289
Test name
Test status
Simulation time 24412518590 ps
CPU time 23.21 seconds
Started May 07 01:07:46 PM PDT 24
Finished May 07 01:08:10 PM PDT 24
Peak memory 183064 kb
Host smart-ce919dee-fd03-40a6-b52f-99bdcb44c656
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971967986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.971967986
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2398782440
Short name T363
Test name
Test status
Simulation time 65319167383 ps
CPU time 93.82 seconds
Started May 07 01:07:43 PM PDT 24
Finished May 07 01:09:18 PM PDT 24
Peak memory 183268 kb
Host smart-f8fccbe7-5814-49b7-ba71-19d94d0b2dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398782440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2398782440
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1700081588
Short name T373
Test name
Test status
Simulation time 1345490353 ps
CPU time 1.19 seconds
Started May 07 01:07:45 PM PDT 24
Finished May 07 01:07:48 PM PDT 24
Peak memory 192768 kb
Host smart-329f915a-5ab8-42cd-a09a-904aaa0aa5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700081588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1700081588
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3935764504
Short name T7
Test name
Test status
Simulation time 33065583124 ps
CPU time 51.77 seconds
Started May 07 01:07:46 PM PDT 24
Finished May 07 01:08:39 PM PDT 24
Peak memory 182960 kb
Host smart-05afd80e-1e7d-43f9-bfed-3d607fca2945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935764504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3935764504
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3490178273
Short name T286
Test name
Test status
Simulation time 1373886924475 ps
CPU time 773.52 seconds
Started May 07 01:07:51 PM PDT 24
Finished May 07 01:20:45 PM PDT 24
Peak memory 183080 kb
Host smart-2fa926c7-f028-4eb1-903e-1d3a4d39b5ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490178273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3490178273
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2590290593
Short name T360
Test name
Test status
Simulation time 56223458130 ps
CPU time 84.23 seconds
Started May 07 01:07:51 PM PDT 24
Finished May 07 01:09:16 PM PDT 24
Peak memory 183076 kb
Host smart-3cac977a-9b27-4d7c-a75d-93c5d4bdf02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590290593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2590290593
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.848849780
Short name T91
Test name
Test status
Simulation time 279161554145 ps
CPU time 128.18 seconds
Started May 07 01:07:52 PM PDT 24
Finished May 07 01:10:01 PM PDT 24
Peak memory 191276 kb
Host smart-31097ad6-1bb9-4b5e-80d4-2bf4af6f366f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848849780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.848849780
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.472056419
Short name T88
Test name
Test status
Simulation time 975647686573 ps
CPU time 1029.63 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:25:06 PM PDT 24
Peak memory 191232 kb
Host smart-d73d7eee-9f6c-4216-9346-f9654928f82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472056419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
472056419
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.429385061
Short name T29
Test name
Test status
Simulation time 49728919653 ps
CPU time 399.62 seconds
Started May 07 01:07:44 PM PDT 24
Finished May 07 01:14:25 PM PDT 24
Peak memory 205876 kb
Host smart-f46dd66e-67eb-49f1-bd9e-4bb83f7289b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429385061 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.429385061
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1465631861
Short name T95
Test name
Test status
Simulation time 19525775240 ps
CPU time 35.53 seconds
Started May 07 01:07:53 PM PDT 24
Finished May 07 01:08:30 PM PDT 24
Peak memory 183032 kb
Host smart-d7df04c4-ffd8-484e-ad56-b025dba090c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465631861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1465631861
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2930541076
Short name T76
Test name
Test status
Simulation time 26006246512 ps
CPU time 40.66 seconds
Started May 07 01:07:53 PM PDT 24
Finished May 07 01:08:35 PM PDT 24
Peak memory 183076 kb
Host smart-b7cc813f-6a35-4ebc-af5a-267e36e8d702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930541076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2930541076
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3857473867
Short name T150
Test name
Test status
Simulation time 101462904992 ps
CPU time 440.9 seconds
Started May 07 01:07:57 PM PDT 24
Finished May 07 01:15:18 PM PDT 24
Peak memory 191100 kb
Host smart-3eaebb75-eb38-4b8a-8310-54c5b7f84cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857473867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3857473867
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.483863978
Short name T455
Test name
Test status
Simulation time 190079378800 ps
CPU time 513.52 seconds
Started May 07 01:07:53 PM PDT 24
Finished May 07 01:16:28 PM PDT 24
Peak memory 183068 kb
Host smart-f142db0d-6fcb-4ed6-ac34-a6e799cbdad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483863978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.483863978
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3368981734
Short name T27
Test name
Test status
Simulation time 20487970 ps
CPU time 0.56 seconds
Started May 07 01:07:56 PM PDT 24
Finished May 07 01:07:58 PM PDT 24
Peak memory 182680 kb
Host smart-50809fc1-9d24-4e4c-9309-fb7f9d860d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368981734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3368981734
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2907080889
Short name T402
Test name
Test status
Simulation time 92240165352 ps
CPU time 148.09 seconds
Started May 07 01:07:56 PM PDT 24
Finished May 07 01:10:25 PM PDT 24
Peak memory 183068 kb
Host smart-fd487bef-ec53-4726-b3c2-badb79121858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907080889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2907080889
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2996591442
Short name T53
Test name
Test status
Simulation time 192858560142 ps
CPU time 469.71 seconds
Started May 07 01:07:54 PM PDT 24
Finished May 07 01:15:44 PM PDT 24
Peak memory 191264 kb
Host smart-2261f88d-d947-429a-b08d-35b7e5847264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996591442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2996591442
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3562298349
Short name T451
Test name
Test status
Simulation time 69067164 ps
CPU time 0.65 seconds
Started May 07 01:07:57 PM PDT 24
Finished May 07 01:07:59 PM PDT 24
Peak memory 183028 kb
Host smart-d888bb2f-c86b-48ce-acee-ef2463d58ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562298349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3562298349
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.547539141
Short name T32
Test name
Test status
Simulation time 43560058787 ps
CPU time 405.92 seconds
Started May 07 01:07:57 PM PDT 24
Finished May 07 01:14:44 PM PDT 24
Peak memory 206120 kb
Host smart-4ddb7f7c-e9e1-47b2-bc7f-294822485ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547539141 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.547539141
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.98095466
Short name T398
Test name
Test status
Simulation time 80073231616 ps
CPU time 129.35 seconds
Started May 07 01:07:54 PM PDT 24
Finished May 07 01:10:05 PM PDT 24
Peak memory 183064 kb
Host smart-7da62f59-a83e-4e05-80e8-e936523e1107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98095466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.98095466
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2399846094
Short name T266
Test name
Test status
Simulation time 133912845758 ps
CPU time 233.27 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:11:49 PM PDT 24
Peak memory 191204 kb
Host smart-855155e5-c92f-4063-bd23-0b5d0b5f8c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399846094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2399846094
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2328107798
Short name T434
Test name
Test status
Simulation time 198149542305 ps
CPU time 191.46 seconds
Started May 07 01:07:56 PM PDT 24
Finished May 07 01:11:09 PM PDT 24
Peak memory 183060 kb
Host smart-de600ae6-9943-44ed-a7af-8d29e0e4f287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328107798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2328107798
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1045428558
Short name T270
Test name
Test status
Simulation time 36965834135 ps
CPU time 34.5 seconds
Started May 07 01:07:53 PM PDT 24
Finished May 07 01:08:29 PM PDT 24
Peak memory 183084 kb
Host smart-e49e9930-c6ed-4a3b-882c-26d8022574d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045428558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1045428558
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.86121753
Short name T446
Test name
Test status
Simulation time 538572769464 ps
CPU time 124.51 seconds
Started May 07 01:07:54 PM PDT 24
Finished May 07 01:10:00 PM PDT 24
Peak memory 183076 kb
Host smart-579a19fb-808d-4bd2-98ed-b055bf1bd72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86121753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.86121753
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.4074864567
Short name T375
Test name
Test status
Simulation time 972737028 ps
CPU time 1.91 seconds
Started May 07 01:07:57 PM PDT 24
Finished May 07 01:08:00 PM PDT 24
Peak memory 182868 kb
Host smart-3f8ea3f6-fc2f-4c11-ba04-882b8ee6e249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074864567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.4074864567
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2125185173
Short name T407
Test name
Test status
Simulation time 123220992191 ps
CPU time 261.15 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:12:17 PM PDT 24
Peak memory 205960 kb
Host smart-21569504-5826-4b44-84dc-e3fd170b0590
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125185173 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2125185173
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.200069115
Short name T319
Test name
Test status
Simulation time 316884372122 ps
CPU time 546.49 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:16:31 PM PDT 24
Peak memory 183060 kb
Host smart-f2097f88-d5cb-42ef-8d1d-18510305ca1d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200069115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.200069115
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3523278191
Short name T376
Test name
Test status
Simulation time 213865241960 ps
CPU time 348.79 seconds
Started May 07 01:07:21 PM PDT 24
Finished May 07 01:13:11 PM PDT 24
Peak memory 182984 kb
Host smart-eed6b298-7a84-4d23-be37-18a55b8ab7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523278191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3523278191
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1123224702
Short name T131
Test name
Test status
Simulation time 215699867323 ps
CPU time 2736.6 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:53:09 PM PDT 24
Peak memory 191256 kb
Host smart-58358aa6-0a50-44a1-a46b-ea0ae4bf8aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123224702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1123224702
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3402651997
Short name T320
Test name
Test status
Simulation time 39750848060 ps
CPU time 39.43 seconds
Started May 07 01:07:20 PM PDT 24
Finished May 07 01:08:01 PM PDT 24
Peak memory 194992 kb
Host smart-c65a3392-3448-40bc-a159-d4eb8d45ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402651997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3402651997
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.327365017
Short name T5
Test name
Test status
Simulation time 81808938 ps
CPU time 0.74 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:07:26 PM PDT 24
Peak memory 213356 kb
Host smart-19034602-a2c7-406d-a9c5-2790634e21e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327365017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.327365017
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3013910885
Short name T66
Test name
Test status
Simulation time 2555812727189 ps
CPU time 962.08 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:23:27 PM PDT 24
Peak memory 191232 kb
Host smart-640bf257-794e-4f01-b581-4cbe7f0c1036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013910885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3013910885
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1789180792
Short name T12
Test name
Test status
Simulation time 60090818333 ps
CPU time 645.89 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:18:19 PM PDT 24
Peak memory 205864 kb
Host smart-7d8a86c0-1575-453b-8cdc-199f84002d25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789180792 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1789180792
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1067736749
Short name T49
Test name
Test status
Simulation time 1183607681 ps
CPU time 2.69 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:07:58 PM PDT 24
Peak memory 182852 kb
Host smart-83947b36-a4b2-4229-b80f-1bcc5939d654
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067736749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1067736749
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3298184993
Short name T366
Test name
Test status
Simulation time 49673163733 ps
CPU time 71.38 seconds
Started May 07 01:07:53 PM PDT 24
Finished May 07 01:09:06 PM PDT 24
Peak memory 183080 kb
Host smart-35dc7080-c9b6-438d-9272-afc165cce278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298184993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3298184993
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.291064752
Short name T340
Test name
Test status
Simulation time 320383215351 ps
CPU time 1018.52 seconds
Started May 07 01:07:57 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 191252 kb
Host smart-98d7c1fb-80ef-4dfc-913d-027c3b7e85cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291064752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.291064752
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.29933142
Short name T387
Test name
Test status
Simulation time 171911596 ps
CPU time 1.09 seconds
Started May 07 01:07:58 PM PDT 24
Finished May 07 01:08:00 PM PDT 24
Peak memory 191204 kb
Host smart-7efa3b7a-5f8b-4517-a4e3-8eceb59af4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29933142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.29933142
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.493721120
Short name T130
Test name
Test status
Simulation time 206358126088 ps
CPU time 78.49 seconds
Started May 07 01:08:04 PM PDT 24
Finished May 07 01:09:24 PM PDT 24
Peak memory 183052 kb
Host smart-24aaf45c-4a47-409c-af2a-047985e9bd7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493721120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.493721120
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2589556207
Short name T380
Test name
Test status
Simulation time 82493923895 ps
CPU time 68.47 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:09:04 PM PDT 24
Peak memory 183076 kb
Host smart-0729051b-3cfe-4481-ba2f-febb91d72471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589556207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2589556207
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.63326757
Short name T242
Test name
Test status
Simulation time 305087056824 ps
CPU time 263.39 seconds
Started May 07 01:07:55 PM PDT 24
Finished May 07 01:12:19 PM PDT 24
Peak memory 191228 kb
Host smart-b3b3e65e-c4db-431b-8e3f-c61be8830963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63326757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.63326757
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1231451060
Short name T231
Test name
Test status
Simulation time 267214071544 ps
CPU time 467.2 seconds
Started May 07 01:08:01 PM PDT 24
Finished May 07 01:15:50 PM PDT 24
Peak memory 182992 kb
Host smart-a3514a3d-3097-4b7c-a679-745fda39c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231451060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1231451060
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.175921788
Short name T78
Test name
Test status
Simulation time 1002724763394 ps
CPU time 325.28 seconds
Started May 07 01:08:04 PM PDT 24
Finished May 07 01:13:30 PM PDT 24
Peak memory 191252 kb
Host smart-7b29a839-651f-4377-85e2-ce33d430a989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175921788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
175921788
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3299676744
Short name T177
Test name
Test status
Simulation time 984158821714 ps
CPU time 552.63 seconds
Started May 07 01:08:01 PM PDT 24
Finished May 07 01:17:15 PM PDT 24
Peak memory 183116 kb
Host smart-1e9e1015-775f-43c8-b794-37e5a6e08625
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299676744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3299676744
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.414847129
Short name T121
Test name
Test status
Simulation time 77566252056 ps
CPU time 100.12 seconds
Started May 07 01:08:00 PM PDT 24
Finished May 07 01:09:41 PM PDT 24
Peak memory 183068 kb
Host smart-bfd6b65d-11af-49cb-9a8e-c43b56a5bf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414847129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.414847129
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2555716029
Short name T392
Test name
Test status
Simulation time 88469638437 ps
CPU time 73.43 seconds
Started May 07 01:08:00 PM PDT 24
Finished May 07 01:09:15 PM PDT 24
Peak memory 183040 kb
Host smart-0f1f1478-4703-4485-9b38-0d6f47f7321d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555716029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2555716029
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.830852704
Short name T344
Test name
Test status
Simulation time 38701958892 ps
CPU time 61.24 seconds
Started May 07 01:08:01 PM PDT 24
Finished May 07 01:09:04 PM PDT 24
Peak memory 191248 kb
Host smart-f5d1db18-2dcd-4378-b6d6-2b66d57c1232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830852704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.830852704
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1065471133
Short name T63
Test name
Test status
Simulation time 146778195813 ps
CPU time 262.15 seconds
Started May 07 01:08:01 PM PDT 24
Finished May 07 01:12:25 PM PDT 24
Peak memory 194960 kb
Host smart-d5f379ed-83f0-4d6d-8dbd-7e94fadfe526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065471133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1065471133
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.265821088
Short name T166
Test name
Test status
Simulation time 14163623816 ps
CPU time 7.82 seconds
Started May 07 01:08:01 PM PDT 24
Finished May 07 01:08:10 PM PDT 24
Peak memory 183060 kb
Host smart-b4868b2c-39d5-471e-a2cc-88f6c637908b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265821088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.265821088
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1681752065
Short name T372
Test name
Test status
Simulation time 281521387984 ps
CPU time 228.56 seconds
Started May 07 01:08:07 PM PDT 24
Finished May 07 01:11:57 PM PDT 24
Peak memory 183056 kb
Host smart-3eb93006-1277-4bfb-bd60-497f03312633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681752065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1681752065
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.529874884
Short name T353
Test name
Test status
Simulation time 64596886617 ps
CPU time 211.36 seconds
Started May 07 01:08:00 PM PDT 24
Finished May 07 01:11:32 PM PDT 24
Peak memory 191248 kb
Host smart-4df677b4-aae2-485a-97d8-618be5c3aade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529874884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.529874884
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.76506827
Short name T310
Test name
Test status
Simulation time 156130622243 ps
CPU time 163.43 seconds
Started May 07 01:07:59 PM PDT 24
Finished May 07 01:10:44 PM PDT 24
Peak memory 191232 kb
Host smart-498cf13e-1a97-4d8d-a46a-f4d347dbbff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76506827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.76506827
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3180944254
Short name T377
Test name
Test status
Simulation time 570488693773 ps
CPU time 133.51 seconds
Started May 07 01:08:02 PM PDT 24
Finished May 07 01:10:17 PM PDT 24
Peak memory 183056 kb
Host smart-bc885117-b3e1-4602-80fc-b01e029d5825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180944254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3180944254
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2028435785
Short name T304
Test name
Test status
Simulation time 20294609253 ps
CPU time 37.01 seconds
Started May 07 01:08:05 PM PDT 24
Finished May 07 01:08:43 PM PDT 24
Peak memory 183076 kb
Host smart-1a3fb376-0e06-4693-9d2d-819780faac5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028435785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2028435785
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1350818795
Short name T397
Test name
Test status
Simulation time 62235555146 ps
CPU time 43.54 seconds
Started May 07 01:08:05 PM PDT 24
Finished May 07 01:08:50 PM PDT 24
Peak memory 183064 kb
Host smart-56e2c006-c2ec-4b7e-ab9c-553499ff12c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350818795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1350818795
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2487582396
Short name T339
Test name
Test status
Simulation time 24934741261 ps
CPU time 54.45 seconds
Started May 07 01:08:00 PM PDT 24
Finished May 07 01:08:55 PM PDT 24
Peak memory 183060 kb
Host smart-d334e2a1-a5ce-4bec-855e-a31419bedb90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487582396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2487582396
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3357352095
Short name T313
Test name
Test status
Simulation time 186285852294 ps
CPU time 153.48 seconds
Started May 07 01:08:00 PM PDT 24
Finished May 07 01:10:35 PM PDT 24
Peak memory 194920 kb
Host smart-7160a6b2-2b66-490c-b0b3-255ad50c8a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357352095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3357352095
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2557545113
Short name T241
Test name
Test status
Simulation time 40908515181 ps
CPU time 75.54 seconds
Started May 07 01:08:02 PM PDT 24
Finished May 07 01:09:19 PM PDT 24
Peak memory 183084 kb
Host smart-3aa9ac3e-4b7e-4dcc-9c98-77f31bcc01f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557545113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2557545113
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1250459869
Short name T378
Test name
Test status
Simulation time 134559406285 ps
CPU time 187.88 seconds
Started May 07 01:08:03 PM PDT 24
Finished May 07 01:11:13 PM PDT 24
Peak memory 183068 kb
Host smart-33cc47c4-f62b-4524-94ee-1b063eae61e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250459869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1250459869
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.868764439
Short name T280
Test name
Test status
Simulation time 154211882098 ps
CPU time 283.49 seconds
Started May 07 01:08:05 PM PDT 24
Finished May 07 01:12:50 PM PDT 24
Peak memory 191240 kb
Host smart-cf14e72d-a126-4eac-b0f6-dcd15df588bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868764439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.868764439
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1951217621
Short name T368
Test name
Test status
Simulation time 37948291 ps
CPU time 0.54 seconds
Started May 07 01:08:06 PM PDT 24
Finished May 07 01:08:07 PM PDT 24
Peak memory 182864 kb
Host smart-7c522bf4-0142-4d35-b1fc-0e42258089df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951217621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1951217621
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4258725728
Short name T433
Test name
Test status
Simulation time 426771429678 ps
CPU time 168.01 seconds
Started May 07 01:08:03 PM PDT 24
Finished May 07 01:10:52 PM PDT 24
Peak memory 194664 kb
Host smart-e0118c89-a754-41f8-a713-612f726d194c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258725728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4258725728
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3347191206
Short name T43
Test name
Test status
Simulation time 60347516260 ps
CPU time 498.44 seconds
Started May 07 01:08:01 PM PDT 24
Finished May 07 01:16:21 PM PDT 24
Peak memory 205840 kb
Host smart-6b4135e8-747f-41fd-a541-29cc30d3a1e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347191206 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3347191206
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3410045415
Short name T213
Test name
Test status
Simulation time 4766437001921 ps
CPU time 1115.45 seconds
Started May 07 01:08:00 PM PDT 24
Finished May 07 01:26:37 PM PDT 24
Peak memory 183076 kb
Host smart-91ca8e9f-6652-479f-b4f7-75121b802d94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410045415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3410045415
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.303296901
Short name T374
Test name
Test status
Simulation time 503033067823 ps
CPU time 217.77 seconds
Started May 07 01:08:00 PM PDT 24
Finished May 07 01:11:39 PM PDT 24
Peak memory 183072 kb
Host smart-35af4c04-20a8-4f03-8460-d77a3ca0b3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303296901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.303296901
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.874039272
Short name T253
Test name
Test status
Simulation time 87160507698 ps
CPU time 418.73 seconds
Started May 07 01:08:02 PM PDT 24
Finished May 07 01:15:02 PM PDT 24
Peak memory 191260 kb
Host smart-974250e9-9ac7-482d-b024-23ac2db67697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874039272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.874039272
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3090727623
Short name T105
Test name
Test status
Simulation time 31575723048 ps
CPU time 45.3 seconds
Started May 07 01:08:04 PM PDT 24
Finished May 07 01:08:50 PM PDT 24
Peak memory 183072 kb
Host smart-6d4e39c8-be0a-44c7-90ce-1ffa3f24c21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090727623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3090727623
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.46740267
Short name T156
Test name
Test status
Simulation time 4211812639 ps
CPU time 6.52 seconds
Started May 07 01:08:00 PM PDT 24
Finished May 07 01:08:07 PM PDT 24
Peak memory 182968 kb
Host smart-edc2fba6-e81b-454f-a40c-ac7400aefec6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46740267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.rv_timer_cfg_update_on_fly.46740267
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2929942895
Short name T365
Test name
Test status
Simulation time 534323427221 ps
CPU time 202.27 seconds
Started May 07 01:08:01 PM PDT 24
Finished May 07 01:11:24 PM PDT 24
Peak memory 183040 kb
Host smart-5f553e10-06a8-4005-af93-84304481d063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929942895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2929942895
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.552966147
Short name T382
Test name
Test status
Simulation time 129068559176 ps
CPU time 87.07 seconds
Started May 07 01:08:04 PM PDT 24
Finished May 07 01:09:33 PM PDT 24
Peak memory 191172 kb
Host smart-4277cfce-a128-47e3-9f5b-4770e1961d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552966147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.552966147
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.675355562
Short name T435
Test name
Test status
Simulation time 15219594273 ps
CPU time 123.46 seconds
Started May 07 01:08:02 PM PDT 24
Finished May 07 01:10:07 PM PDT 24
Peak memory 197636 kb
Host smart-1e48557a-cc33-4df3-95f6-eb95fce5ac03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675355562 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.675355562
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3587930865
Short name T431
Test name
Test status
Simulation time 529214298169 ps
CPU time 193.64 seconds
Started May 07 01:08:02 PM PDT 24
Finished May 07 01:11:17 PM PDT 24
Peak memory 183000 kb
Host smart-b65eed5e-e09e-4c3e-ac5f-edb9b6243655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587930865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3587930865
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2546564021
Short name T441
Test name
Test status
Simulation time 37609492243 ps
CPU time 40.33 seconds
Started May 07 01:08:07 PM PDT 24
Finished May 07 01:08:48 PM PDT 24
Peak memory 183056 kb
Host smart-a36f48cb-e92f-426b-b25f-bb12585d9f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546564021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2546564021
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3332160428
Short name T200
Test name
Test status
Simulation time 231652699428 ps
CPU time 921.72 seconds
Started May 07 01:08:07 PM PDT 24
Finished May 07 01:23:30 PM PDT 24
Peak memory 192628 kb
Host smart-43919b9a-1fcf-4ff9-be5a-9609f08c89cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332160428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3332160428
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.714207040
Short name T107
Test name
Test status
Simulation time 1789179600162 ps
CPU time 937.6 seconds
Started May 07 01:08:10 PM PDT 24
Finished May 07 01:23:49 PM PDT 24
Peak memory 183264 kb
Host smart-d6c479d1-dab5-4cfb-96ac-e38730f75979
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714207040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.714207040
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.638012719
Short name T389
Test name
Test status
Simulation time 214960800182 ps
CPU time 168.5 seconds
Started May 07 01:08:11 PM PDT 24
Finished May 07 01:11:00 PM PDT 24
Peak memory 183076 kb
Host smart-4169cdab-cfcc-4400-b303-d30448595ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638012719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.638012719
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.786494470
Short name T342
Test name
Test status
Simulation time 17992372590 ps
CPU time 33.07 seconds
Started May 07 01:08:08 PM PDT 24
Finished May 07 01:08:43 PM PDT 24
Peak memory 191236 kb
Host smart-c3e7c457-ef0c-435d-958d-fdf3036e1960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786494470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.786494470
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3613764916
Short name T244
Test name
Test status
Simulation time 55259613534 ps
CPU time 25.48 seconds
Started May 07 01:08:13 PM PDT 24
Finished May 07 01:08:39 PM PDT 24
Peak memory 191268 kb
Host smart-52077381-782c-4ed1-b38f-eba75a973751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613764916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3613764916
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1669727441
Short name T439
Test name
Test status
Simulation time 33889149 ps
CPU time 0.6 seconds
Started May 07 01:08:07 PM PDT 24
Finished May 07 01:08:08 PM PDT 24
Peak memory 182800 kb
Host smart-5f938b87-1f03-4126-bc5c-8d11655995e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669727441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1669727441
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2554785262
Short name T454
Test name
Test status
Simulation time 2237244130451 ps
CPU time 833.8 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:21:17 PM PDT 24
Peak memory 183052 kb
Host smart-a70c58b9-5fb0-471b-ad59-a635baf156bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554785262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2554785262
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1202147385
Short name T36
Test name
Test status
Simulation time 66184499939 ps
CPU time 96.78 seconds
Started May 07 01:07:27 PM PDT 24
Finished May 07 01:09:05 PM PDT 24
Peak memory 183064 kb
Host smart-94603d97-4f09-4252-9457-fa01bb3188ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202147385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1202147385
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.588203614
Short name T332
Test name
Test status
Simulation time 1597390612202 ps
CPU time 404.83 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:14:08 PM PDT 24
Peak memory 191208 kb
Host smart-da51127d-02f3-4393-baff-220e75288b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588203614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.588203614
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2070926376
Short name T149
Test name
Test status
Simulation time 407655423884 ps
CPU time 156.93 seconds
Started May 07 01:07:21 PM PDT 24
Finished May 07 01:10:00 PM PDT 24
Peak memory 191236 kb
Host smart-4ae612db-09f3-4783-8a15-ee799c70d5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070926376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2070926376
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1375974410
Short name T17
Test name
Test status
Simulation time 160009540 ps
CPU time 0.98 seconds
Started May 07 01:07:24 PM PDT 24
Finished May 07 01:07:26 PM PDT 24
Peak memory 213516 kb
Host smart-17e8729f-dd15-4508-b068-2d07c8408a2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375974410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1375974410
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3322087173
Short name T33
Test name
Test status
Simulation time 79031453544 ps
CPU time 1251.35 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:28:24 PM PDT 24
Peak memory 206800 kb
Host smart-3d2957e0-25b9-4f1e-8b3f-6eb8b31599b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322087173 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3322087173
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.503648777
Short name T443
Test name
Test status
Simulation time 1894924457 ps
CPU time 3.94 seconds
Started May 07 01:08:09 PM PDT 24
Finished May 07 01:08:15 PM PDT 24
Peak memory 183040 kb
Host smart-01478afe-9a6d-4dc7-8530-b11781345b27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503648777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.503648777
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2493403849
Short name T379
Test name
Test status
Simulation time 564373284882 ps
CPU time 249.31 seconds
Started May 07 01:08:11 PM PDT 24
Finished May 07 01:12:21 PM PDT 24
Peak memory 183076 kb
Host smart-231b4ac5-64bc-4f6e-92ec-328f677e0764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493403849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2493403849
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.663233103
Short name T259
Test name
Test status
Simulation time 92371616875 ps
CPU time 164.02 seconds
Started May 07 01:08:10 PM PDT 24
Finished May 07 01:10:55 PM PDT 24
Peak memory 183068 kb
Host smart-165a5cd0-6683-4698-ad06-ead9893653c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663233103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.663233103
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2670710583
Short name T425
Test name
Test status
Simulation time 278368865 ps
CPU time 0.62 seconds
Started May 07 01:08:13 PM PDT 24
Finished May 07 01:08:14 PM PDT 24
Peak memory 182844 kb
Host smart-e5d2f05c-6169-4f80-8df9-154fbf2c5521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670710583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2670710583
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2517493425
Short name T277
Test name
Test status
Simulation time 56513977419 ps
CPU time 88.07 seconds
Started May 07 01:08:11 PM PDT 24
Finished May 07 01:09:40 PM PDT 24
Peak memory 183088 kb
Host smart-a2325e33-aad7-4f46-96b5-164ddd9525a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517493425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2517493425
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2201615864
Short name T386
Test name
Test status
Simulation time 687428653924 ps
CPU time 292.04 seconds
Started May 07 01:08:09 PM PDT 24
Finished May 07 01:13:02 PM PDT 24
Peak memory 183052 kb
Host smart-c6bf314e-8a26-45e8-93e7-821768fe538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201615864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2201615864
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1728941354
Short name T354
Test name
Test status
Simulation time 41210025238 ps
CPU time 153.68 seconds
Started May 07 01:08:09 PM PDT 24
Finished May 07 01:10:44 PM PDT 24
Peak memory 182972 kb
Host smart-da192b38-e813-4f64-922f-91a68e439506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728941354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1728941354
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.654583689
Short name T109
Test name
Test status
Simulation time 502728920 ps
CPU time 0.63 seconds
Started May 07 01:08:09 PM PDT 24
Finished May 07 01:08:11 PM PDT 24
Peak memory 182864 kb
Host smart-23b95344-306c-4fb6-b3ba-aa76d6ff2429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654583689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.654583689
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3074797025
Short name T60
Test name
Test status
Simulation time 23747607 ps
CPU time 0.54 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:08:18 PM PDT 24
Peak memory 182844 kb
Host smart-a6016dcd-1ba8-4e70-9e83-7227d85db28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074797025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3074797025
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1811457381
Short name T302
Test name
Test status
Simulation time 1924551534111 ps
CPU time 1034.31 seconds
Started May 07 01:08:15 PM PDT 24
Finished May 07 01:25:31 PM PDT 24
Peak memory 183068 kb
Host smart-365ae796-86c3-4e41-b61f-d9fcfa34bf39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811457381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1811457381
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2582000415
Short name T396
Test name
Test status
Simulation time 52251919726 ps
CPU time 78.71 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:09:37 PM PDT 24
Peak memory 183028 kb
Host smart-06af2215-0404-455f-bae7-3661ffd27d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582000415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2582000415
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1363884651
Short name T406
Test name
Test status
Simulation time 29548029 ps
CPU time 0.53 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:08:19 PM PDT 24
Peak memory 182872 kb
Host smart-b1f9aab7-6215-4ba2-bb1b-7a8f9d7800c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363884651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1363884651
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.596031673
Short name T207
Test name
Test status
Simulation time 336989618854 ps
CPU time 607.01 seconds
Started May 07 01:08:18 PM PDT 24
Finished May 07 01:18:26 PM PDT 24
Peak memory 183076 kb
Host smart-f4acd8d5-59b5-4e5c-a311-a79c2fc88b06
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596031673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.596031673
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2422978195
Short name T417
Test name
Test status
Simulation time 620349122814 ps
CPU time 266.08 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:12:44 PM PDT 24
Peak memory 183068 kb
Host smart-279dd326-1e59-4ddc-9f6b-2fb4cb57a500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422978195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2422978195
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2509594586
Short name T192
Test name
Test status
Simulation time 103341778624 ps
CPU time 248.79 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:12:27 PM PDT 24
Peak memory 191240 kb
Host smart-489ea9b2-516c-4a45-a924-2160ca8fea12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509594586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2509594586
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1098148009
Short name T243
Test name
Test status
Simulation time 694712793 ps
CPU time 1.92 seconds
Started May 07 01:08:18 PM PDT 24
Finished May 07 01:08:21 PM PDT 24
Peak memory 182944 kb
Host smart-6845543b-672f-4268-8fdd-79c4438e64bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098148009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1098148009
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3534391165
Short name T248
Test name
Test status
Simulation time 1998163408673 ps
CPU time 606.24 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:18:25 PM PDT 24
Peak memory 191268 kb
Host smart-b8eddedb-d607-47b7-a028-1dbf1dfe5c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534391165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3534391165
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1680624584
Short name T14
Test name
Test status
Simulation time 44157584784 ps
CPU time 306.12 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:13:24 PM PDT 24
Peak memory 205920 kb
Host smart-cee0e4ed-867f-4568-98a9-15b9e5e5ba61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680624584 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1680624584
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2456612468
Short name T421
Test name
Test status
Simulation time 179867295726 ps
CPU time 318.82 seconds
Started May 07 01:08:26 PM PDT 24
Finished May 07 01:13:47 PM PDT 24
Peak memory 183072 kb
Host smart-837a53ec-af40-42bd-8903-a9275e7e8e26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456612468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2456612468
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3777845329
Short name T80
Test name
Test status
Simulation time 619220556730 ps
CPU time 232.51 seconds
Started May 07 01:08:19 PM PDT 24
Finished May 07 01:12:12 PM PDT 24
Peak memory 183224 kb
Host smart-30b7c056-cc6a-49f4-873f-2d6f8756f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777845329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3777845329
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3468855412
Short name T87
Test name
Test status
Simulation time 905349723444 ps
CPU time 2144.11 seconds
Started May 07 01:08:17 PM PDT 24
Finished May 07 01:44:02 PM PDT 24
Peak memory 191188 kb
Host smart-c1e76604-da45-4bc0-841b-642edec08ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468855412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3468855412
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1638946461
Short name T306
Test name
Test status
Simulation time 68735065673 ps
CPU time 111.86 seconds
Started May 07 01:08:22 PM PDT 24
Finished May 07 01:10:15 PM PDT 24
Peak memory 191276 kb
Host smart-7de46e04-0fb7-48a3-b5af-789da1d1a7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638946461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1638946461
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.793278647
Short name T358
Test name
Test status
Simulation time 220713385415 ps
CPU time 180.66 seconds
Started May 07 01:08:23 PM PDT 24
Finished May 07 01:11:25 PM PDT 24
Peak memory 191244 kb
Host smart-a4905644-5ea1-4ecd-9bcc-e0097fee5c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793278647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
793278647
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2030848941
Short name T138
Test name
Test status
Simulation time 96055814127 ps
CPU time 143.26 seconds
Started May 07 01:08:24 PM PDT 24
Finished May 07 01:10:49 PM PDT 24
Peak memory 183040 kb
Host smart-8119cf29-0181-4794-961f-9cd5c17743e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030848941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2030848941
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2592366385
Short name T394
Test name
Test status
Simulation time 89092068424 ps
CPU time 129.8 seconds
Started May 07 01:08:23 PM PDT 24
Finished May 07 01:10:34 PM PDT 24
Peak memory 183076 kb
Host smart-10c70377-f4cb-42cf-8de2-97c6924dfcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592366385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2592366385
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3703317282
Short name T203
Test name
Test status
Simulation time 198064552554 ps
CPU time 1280.99 seconds
Started May 07 01:08:23 PM PDT 24
Finished May 07 01:29:45 PM PDT 24
Peak memory 191272 kb
Host smart-a96fdc46-92b9-4dba-8226-8884ef3bf004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703317282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3703317282
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.760115551
Short name T69
Test name
Test status
Simulation time 871928629 ps
CPU time 2 seconds
Started May 07 01:08:24 PM PDT 24
Finished May 07 01:08:27 PM PDT 24
Peak memory 191172 kb
Host smart-282a8e3f-4b89-4f7c-8900-6ae605b630ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760115551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.760115551
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3633100116
Short name T65
Test name
Test status
Simulation time 510458488073 ps
CPU time 449.53 seconds
Started May 07 01:08:25 PM PDT 24
Finished May 07 01:15:56 PM PDT 24
Peak memory 191252 kb
Host smart-a0a95de8-7d0d-4e3d-8545-d9a794fb4b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633100116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3633100116
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2881545019
Short name T37
Test name
Test status
Simulation time 719965072901 ps
CPU time 630.91 seconds
Started May 07 01:08:22 PM PDT 24
Finished May 07 01:18:54 PM PDT 24
Peak memory 183076 kb
Host smart-e42f973c-94db-4ef9-a649-17a47732df16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881545019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2881545019
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1191922505
Short name T420
Test name
Test status
Simulation time 130367379924 ps
CPU time 175.15 seconds
Started May 07 01:08:21 PM PDT 24
Finished May 07 01:11:18 PM PDT 24
Peak memory 183040 kb
Host smart-7e83edc9-ad76-44d7-9da7-b3ceb0d987bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191922505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1191922505
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2222718615
Short name T329
Test name
Test status
Simulation time 27513699753 ps
CPU time 18.09 seconds
Started May 07 01:08:23 PM PDT 24
Finished May 07 01:08:42 PM PDT 24
Peak memory 183028 kb
Host smart-0d94a2bf-fd68-43e4-878d-266fd197b0c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222718615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2222718615
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2376414762
Short name T237
Test name
Test status
Simulation time 212377674245 ps
CPU time 104.49 seconds
Started May 07 01:08:21 PM PDT 24
Finished May 07 01:10:06 PM PDT 24
Peak memory 194844 kb
Host smart-85336a9e-5594-44c4-a514-057e96250d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376414762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2376414762
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2804578561
Short name T45
Test name
Test status
Simulation time 28724331389 ps
CPU time 121.06 seconds
Started May 07 01:08:22 PM PDT 24
Finished May 07 01:10:24 PM PDT 24
Peak memory 196172 kb
Host smart-3925fd59-45ed-4475-991d-a82e5c03b5d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804578561 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2804578561
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2085412479
Short name T225
Test name
Test status
Simulation time 40095444755 ps
CPU time 63.17 seconds
Started May 07 01:08:30 PM PDT 24
Finished May 07 01:09:35 PM PDT 24
Peak memory 183004 kb
Host smart-392793c3-725e-433c-bf47-34cda80b9a16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085412479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2085412479
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3576039310
Short name T39
Test name
Test status
Simulation time 138126298703 ps
CPU time 53.89 seconds
Started May 07 01:08:29 PM PDT 24
Finished May 07 01:09:24 PM PDT 24
Peak memory 183048 kb
Host smart-fbe31bf8-696f-4f4f-a76d-403d7b1c214a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576039310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3576039310
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2617356195
Short name T316
Test name
Test status
Simulation time 387427005122 ps
CPU time 490.61 seconds
Started May 07 01:08:32 PM PDT 24
Finished May 07 01:16:44 PM PDT 24
Peak memory 191212 kb
Host smart-83ee9fde-010b-49c5-b707-7580cfa99bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617356195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2617356195
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1595731101
Short name T404
Test name
Test status
Simulation time 42834540136 ps
CPU time 39.01 seconds
Started May 07 01:08:32 PM PDT 24
Finished May 07 01:09:12 PM PDT 24
Peak memory 191232 kb
Host smart-4c9e76c9-d1e5-4875-be82-10fc013281aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595731101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1595731101
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2199158264
Short name T436
Test name
Test status
Simulation time 761768003 ps
CPU time 0.9 seconds
Started May 07 01:08:31 PM PDT 24
Finished May 07 01:08:34 PM PDT 24
Peak memory 182864 kb
Host smart-7848451d-e215-4d8d-b422-3b98d6b65583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199158264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2199158264
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4282934766
Short name T236
Test name
Test status
Simulation time 369945300542 ps
CPU time 244.44 seconds
Started May 07 01:08:29 PM PDT 24
Finished May 07 01:12:34 PM PDT 24
Peak memory 183076 kb
Host smart-23925b14-80b7-4fdb-92ce-c6a23ffc9f0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282934766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.4282934766
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3728919234
Short name T399
Test name
Test status
Simulation time 322130650411 ps
CPU time 131.83 seconds
Started May 07 01:08:32 PM PDT 24
Finished May 07 01:10:45 PM PDT 24
Peak memory 183024 kb
Host smart-b2a27915-a266-4e6e-a88e-41ea49cd0ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728919234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3728919234
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.136760369
Short name T274
Test name
Test status
Simulation time 48303848833 ps
CPU time 75.5 seconds
Started May 07 01:08:31 PM PDT 24
Finished May 07 01:09:48 PM PDT 24
Peak memory 191232 kb
Host smart-03102803-bb48-4a1c-aa43-4ef3f785a34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136760369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.136760369
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2174670104
Short name T73
Test name
Test status
Simulation time 75557533591 ps
CPU time 123.74 seconds
Started May 07 01:08:32 PM PDT 24
Finished May 07 01:10:38 PM PDT 24
Peak memory 191216 kb
Host smart-df36b267-fc82-4d58-a2bb-cbe8c3ca6f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174670104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2174670104
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1036373803
Short name T432
Test name
Test status
Simulation time 42868374325 ps
CPU time 60.31 seconds
Started May 07 01:08:31 PM PDT 24
Finished May 07 01:09:33 PM PDT 24
Peak memory 194680 kb
Host smart-cfac59b1-819d-4192-89c3-75cf624aefcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036373803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1036373803
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3917219258
Short name T202
Test name
Test status
Simulation time 1697221186746 ps
CPU time 938.78 seconds
Started May 07 01:08:38 PM PDT 24
Finished May 07 01:24:18 PM PDT 24
Peak memory 183236 kb
Host smart-868a699a-8cd2-430e-8bc7-0968969d7858
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917219258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3917219258
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1694070336
Short name T426
Test name
Test status
Simulation time 529123345309 ps
CPU time 231.31 seconds
Started May 07 01:08:44 PM PDT 24
Finished May 07 01:12:37 PM PDT 24
Peak memory 182892 kb
Host smart-c81ae636-e874-4c64-b002-49fd59c2b046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694070336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1694070336
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1621590522
Short name T234
Test name
Test status
Simulation time 130170013061 ps
CPU time 99.88 seconds
Started May 07 01:08:33 PM PDT 24
Finished May 07 01:10:14 PM PDT 24
Peak memory 193728 kb
Host smart-cce8a499-cb48-4a06-9f50-edf134046b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621590522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1621590522
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.4257303472
Short name T423
Test name
Test status
Simulation time 142879159380 ps
CPU time 229.31 seconds
Started May 07 01:08:36 PM PDT 24
Finished May 07 01:12:26 PM PDT 24
Peak memory 194256 kb
Host smart-eaedab7a-8e3a-45d9-8b61-2379b999d3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257303472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4257303472
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3896208532
Short name T291
Test name
Test status
Simulation time 647776373089 ps
CPU time 1250.42 seconds
Started May 07 01:08:36 PM PDT 24
Finished May 07 01:29:27 PM PDT 24
Peak memory 191268 kb
Host smart-93c9eb78-6f74-4486-8815-4e7f49bddbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896208532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3896208532
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.749398188
Short name T412
Test name
Test status
Simulation time 12254320309 ps
CPU time 21.4 seconds
Started May 07 01:07:24 PM PDT 24
Finished May 07 01:07:46 PM PDT 24
Peak memory 183060 kb
Host smart-48c09ed0-64f1-4db2-ae54-b9105e78acb4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749398188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.749398188
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1580313074
Short name T90
Test name
Test status
Simulation time 475039874447 ps
CPU time 216.89 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:11:00 PM PDT 24
Peak memory 183064 kb
Host smart-1b43b19b-ade7-401b-9d84-2a5776371839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580313074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1580313074
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1016760198
Short name T299
Test name
Test status
Simulation time 115329799139 ps
CPU time 1997.94 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:40:42 PM PDT 24
Peak memory 191256 kb
Host smart-23ff8f6b-c845-4331-9e70-cbf899cd882e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016760198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1016760198
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3878054650
Short name T416
Test name
Test status
Simulation time 43673334 ps
CPU time 0.61 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:07:33 PM PDT 24
Peak memory 182872 kb
Host smart-db140560-7c21-4327-9936-73f38f750031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878054650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3878054650
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.2917044099
Short name T34
Test name
Test status
Simulation time 306141553457 ps
CPU time 589.93 seconds
Started May 07 01:07:25 PM PDT 24
Finished May 07 01:17:16 PM PDT 24
Peak memory 205956 kb
Host smart-7616ac58-c515-423d-93fd-79ef10437b2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917044099 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.2917044099
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.3794745236
Short name T147
Test name
Test status
Simulation time 101340828949 ps
CPU time 67.56 seconds
Started May 07 01:08:36 PM PDT 24
Finished May 07 01:09:45 PM PDT 24
Peak memory 183052 kb
Host smart-456d435c-06fa-4c75-9a6c-a131b5752e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794745236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3794745236
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1650810304
Short name T152
Test name
Test status
Simulation time 70485908067 ps
CPU time 108.11 seconds
Started May 07 01:08:36 PM PDT 24
Finished May 07 01:10:25 PM PDT 24
Peak memory 191164 kb
Host smart-bad6bd87-7a76-428f-909a-ffa7c9c8276e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650810304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1650810304
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.91788314
Short name T161
Test name
Test status
Simulation time 502635328044 ps
CPU time 166.07 seconds
Started May 07 01:08:43 PM PDT 24
Finished May 07 01:11:31 PM PDT 24
Peak memory 191204 kb
Host smart-9a8c1ff4-3326-4aa4-858a-2aa1a86c3ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91788314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.91788314
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2921051186
Short name T165
Test name
Test status
Simulation time 63801258176 ps
CPU time 106.25 seconds
Started May 07 01:08:38 PM PDT 24
Finished May 07 01:10:25 PM PDT 24
Peak memory 193436 kb
Host smart-3a50acf2-b9a7-414d-8b61-1f984d0a245e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921051186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2921051186
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2980285993
Short name T160
Test name
Test status
Simulation time 37987884905 ps
CPU time 24.47 seconds
Started May 07 01:08:36 PM PDT 24
Finished May 07 01:09:02 PM PDT 24
Peak memory 183064 kb
Host smart-2ba57f4d-47cc-42e8-ab07-31225fbdff26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980285993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2980285993
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.505595684
Short name T10
Test name
Test status
Simulation time 532934786646 ps
CPU time 330.25 seconds
Started May 07 01:08:42 PM PDT 24
Finished May 07 01:14:14 PM PDT 24
Peak memory 191196 kb
Host smart-f7fdbcaa-bbc2-4978-a6be-7a1ad468b46c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505595684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.505595684
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2568852788
Short name T414
Test name
Test status
Simulation time 112265678606 ps
CPU time 95.07 seconds
Started May 07 01:08:37 PM PDT 24
Finished May 07 01:10:13 PM PDT 24
Peak memory 183040 kb
Host smart-20aefb1b-cff0-4519-a03d-22c38f3613ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568852788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2568852788
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3495756238
Short name T8
Test name
Test status
Simulation time 1321155487226 ps
CPU time 764.53 seconds
Started May 07 01:07:26 PM PDT 24
Finished May 07 01:20:12 PM PDT 24
Peak memory 183064 kb
Host smart-687aedda-05e4-46cc-a89f-040989284233
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495756238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3495756238
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.725086142
Short name T422
Test name
Test status
Simulation time 951703089890 ps
CPU time 216.52 seconds
Started May 07 01:07:23 PM PDT 24
Finished May 07 01:11:01 PM PDT 24
Peak memory 183072 kb
Host smart-453f3969-7452-432d-846c-bf3a327d274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725086142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.725086142
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.212871760
Short name T30
Test name
Test status
Simulation time 15337624546 ps
CPU time 54.97 seconds
Started May 07 01:07:29 PM PDT 24
Finished May 07 01:08:25 PM PDT 24
Peak memory 197732 kb
Host smart-ec31ebb0-8cda-47ff-9235-570e584ac17f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212871760 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.212871760
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2330862785
Short name T395
Test name
Test status
Simulation time 385582107659 ps
CPU time 952.28 seconds
Started May 07 01:08:35 PM PDT 24
Finished May 07 01:24:29 PM PDT 24
Peak memory 191248 kb
Host smart-a9bf1526-051a-458f-85fc-8ec280cae951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330862785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2330862785
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1572589365
Short name T317
Test name
Test status
Simulation time 218583388746 ps
CPU time 186.88 seconds
Started May 07 01:08:35 PM PDT 24
Finished May 07 01:11:43 PM PDT 24
Peak memory 191256 kb
Host smart-22aa895a-44bd-4712-adf4-7f1b8b50f479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572589365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1572589365
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.352622249
Short name T450
Test name
Test status
Simulation time 55283522083 ps
CPU time 338.27 seconds
Started May 07 01:08:45 PM PDT 24
Finished May 07 01:14:24 PM PDT 24
Peak memory 183052 kb
Host smart-0436edae-3f64-4d42-a028-3048beb5526f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352622249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.352622249
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2321673299
Short name T143
Test name
Test status
Simulation time 50657112468 ps
CPU time 115.44 seconds
Started May 07 01:08:45 PM PDT 24
Finished May 07 01:10:41 PM PDT 24
Peak memory 191240 kb
Host smart-55eec016-c33c-4f73-9077-3fd224fb8754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321673299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2321673299
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3473435902
Short name T264
Test name
Test status
Simulation time 90997264805 ps
CPU time 88.26 seconds
Started May 07 01:08:46 PM PDT 24
Finished May 07 01:10:15 PM PDT 24
Peak memory 183148 kb
Host smart-e8cdde05-506b-49c7-af6a-f163fd439d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473435902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3473435902
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3080515269
Short name T419
Test name
Test status
Simulation time 448263506282 ps
CPU time 414.84 seconds
Started May 07 01:08:46 PM PDT 24
Finished May 07 01:15:42 PM PDT 24
Peak memory 191268 kb
Host smart-09411b3b-b38d-42c9-a7f4-f280a22ea85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080515269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3080515269
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.162736605
Short name T3
Test name
Test status
Simulation time 198565760200 ps
CPU time 256.5 seconds
Started May 07 01:08:47 PM PDT 24
Finished May 07 01:13:04 PM PDT 24
Peak memory 191208 kb
Host smart-5f87c2cb-0847-468f-aea7-415b22395722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162736605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.162736605
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2428498213
Short name T267
Test name
Test status
Simulation time 19730761542 ps
CPU time 37.06 seconds
Started May 07 01:08:47 PM PDT 24
Finished May 07 01:09:24 PM PDT 24
Peak memory 183008 kb
Host smart-af3aee1f-17a6-4ab3-9810-acecb3657f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428498213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2428498213
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2911781777
Short name T235
Test name
Test status
Simulation time 437678937471 ps
CPU time 395.34 seconds
Started May 07 01:08:43 PM PDT 24
Finished May 07 01:15:20 PM PDT 24
Peak memory 191256 kb
Host smart-7137e0e1-ec09-440f-958d-cf4470be264d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911781777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2911781777
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3265140504
Short name T216
Test name
Test status
Simulation time 199088133399 ps
CPU time 160.56 seconds
Started May 07 01:08:43 PM PDT 24
Finished May 07 01:11:25 PM PDT 24
Peak memory 191232 kb
Host smart-d2cdd292-825f-406b-9849-754791bec4de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265140504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3265140504
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3960768926
Short name T273
Test name
Test status
Simulation time 110218240003 ps
CPU time 176.33 seconds
Started May 07 01:07:30 PM PDT 24
Finished May 07 01:10:27 PM PDT 24
Peak memory 183060 kb
Host smart-2aa9a580-7434-466b-8cbe-408a842b23d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960768926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3960768926
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.25198526
Short name T383
Test name
Test status
Simulation time 389736539114 ps
CPU time 154.35 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:10:07 PM PDT 24
Peak memory 183056 kb
Host smart-214bcd2c-b145-4e3f-945d-8007ad006bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25198526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.25198526
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2719669198
Short name T324
Test name
Test status
Simulation time 220765128045 ps
CPU time 21.83 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:07:53 PM PDT 24
Peak memory 183064 kb
Host smart-81726cb2-698a-41d4-a30e-49e209ba253f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719669198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2719669198
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1535365249
Short name T68
Test name
Test status
Simulation time 12718967823 ps
CPU time 120.35 seconds
Started May 07 01:07:29 PM PDT 24
Finished May 07 01:09:31 PM PDT 24
Peak memory 191196 kb
Host smart-f05b74a1-be93-4ee8-b28c-85f29911387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535365249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1535365249
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2912647547
Short name T169
Test name
Test status
Simulation time 2768796229998 ps
CPU time 2030.16 seconds
Started May 07 01:07:30 PM PDT 24
Finished May 07 01:41:21 PM PDT 24
Peak memory 195008 kb
Host smart-db66614e-21bb-4641-a1ee-0ea072db41a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912647547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2912647547
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.808863652
Short name T337
Test name
Test status
Simulation time 42747434202 ps
CPU time 60.03 seconds
Started May 07 01:08:43 PM PDT 24
Finished May 07 01:09:44 PM PDT 24
Peak memory 182900 kb
Host smart-da40d780-5661-443f-a354-1d6718f87801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808863652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.808863652
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2400704096
Short name T214
Test name
Test status
Simulation time 1539722289378 ps
CPU time 434.79 seconds
Started May 07 01:08:42 PM PDT 24
Finished May 07 01:15:58 PM PDT 24
Peak memory 191196 kb
Host smart-b22d3027-5943-47bc-b0a6-c72632b480bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400704096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2400704096
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2242338574
Short name T278
Test name
Test status
Simulation time 108014591943 ps
CPU time 601.54 seconds
Started May 07 01:08:43 PM PDT 24
Finished May 07 01:18:46 PM PDT 24
Peak memory 191260 kb
Host smart-39e81379-04ff-4884-9614-b68a5c792dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242338574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2242338574
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1846346632
Short name T357
Test name
Test status
Simulation time 117334007387 ps
CPU time 167.53 seconds
Started May 07 01:08:43 PM PDT 24
Finished May 07 01:11:32 PM PDT 24
Peak memory 195072 kb
Host smart-4acc1699-71fe-45da-8204-b07403865a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846346632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1846346632
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4278427593
Short name T336
Test name
Test status
Simulation time 604208584681 ps
CPU time 1912.57 seconds
Started May 07 01:08:42 PM PDT 24
Finished May 07 01:40:37 PM PDT 24
Peak memory 191228 kb
Host smart-4d7991c9-d18f-4a93-891f-1090ced598c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278427593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4278427593
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1649536000
Short name T218
Test name
Test status
Simulation time 249886477550 ps
CPU time 369.02 seconds
Started May 07 01:08:52 PM PDT 24
Finished May 07 01:15:01 PM PDT 24
Peak memory 191100 kb
Host smart-e8a4c499-ea9c-4276-8e78-af333ef95c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649536000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1649536000
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3967837078
Short name T212
Test name
Test status
Simulation time 103737761410 ps
CPU time 147.01 seconds
Started May 07 01:08:51 PM PDT 24
Finished May 07 01:11:19 PM PDT 24
Peak memory 183060 kb
Host smart-576bdc37-91da-4815-97f1-b80f04eaa593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967837078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3967837078
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2881797987
Short name T445
Test name
Test status
Simulation time 101992084802 ps
CPU time 253.24 seconds
Started May 07 01:08:51 PM PDT 24
Finished May 07 01:13:05 PM PDT 24
Peak memory 191340 kb
Host smart-eb6ce1b0-4d84-45c6-868d-1797e5b30852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881797987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2881797987
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3636348930
Short name T252
Test name
Test status
Simulation time 344387227242 ps
CPU time 169.45 seconds
Started May 07 01:07:29 PM PDT 24
Finished May 07 01:10:20 PM PDT 24
Peak memory 183028 kb
Host smart-ddac841d-bee9-45f2-96cb-551e39ae855f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636348930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3636348930
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.593309599
Short name T362
Test name
Test status
Simulation time 57914158726 ps
CPU time 95.31 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:09:08 PM PDT 24
Peak memory 183064 kb
Host smart-693f0f59-5e6c-4268-a4ce-766f16c43d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593309599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.593309599
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.816510130
Short name T294
Test name
Test status
Simulation time 127394273552 ps
CPU time 118.54 seconds
Started May 07 01:07:33 PM PDT 24
Finished May 07 01:09:32 PM PDT 24
Peak memory 191252 kb
Host smart-e0b92458-366f-4cea-8735-51163da8d179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816510130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.816510130
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.388039869
Short name T388
Test name
Test status
Simulation time 1633825525 ps
CPU time 1.82 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:07:35 PM PDT 24
Peak memory 191872 kb
Host smart-b9d60f93-8185-4a69-a7d4-4b527239a9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388039869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.388039869
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3996984511
Short name T201
Test name
Test status
Simulation time 242663417933 ps
CPU time 531.37 seconds
Started May 07 01:07:30 PM PDT 24
Finished May 07 01:16:22 PM PDT 24
Peak memory 191256 kb
Host smart-3a0944e6-0245-4d2e-b006-b44869cba344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996984511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3996984511
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.740182856
Short name T260
Test name
Test status
Simulation time 59743118615 ps
CPU time 104.23 seconds
Started May 07 01:08:51 PM PDT 24
Finished May 07 01:10:36 PM PDT 24
Peak memory 191248 kb
Host smart-a010ff7a-9f8b-4dfb-bdab-5e7efb987024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740182856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.740182856
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2654809914
Short name T190
Test name
Test status
Simulation time 455224097025 ps
CPU time 299.12 seconds
Started May 07 01:08:50 PM PDT 24
Finished May 07 01:13:50 PM PDT 24
Peak memory 191144 kb
Host smart-56ffcc94-ff2f-453e-923f-43427f58ad66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654809914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2654809914
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.19051137
Short name T314
Test name
Test status
Simulation time 364607043566 ps
CPU time 348.83 seconds
Started May 07 01:08:53 PM PDT 24
Finished May 07 01:14:42 PM PDT 24
Peak memory 191420 kb
Host smart-113747f4-6c59-4de2-8224-4b44f715af10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.19051137
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3651093662
Short name T247
Test name
Test status
Simulation time 433933278902 ps
CPU time 226 seconds
Started May 07 01:08:49 PM PDT 24
Finished May 07 01:12:36 PM PDT 24
Peak memory 191236 kb
Host smart-5b7f6953-cc65-4962-8c60-01df6a44cc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651093662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3651093662
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2031717259
Short name T4
Test name
Test status
Simulation time 84774466564 ps
CPU time 59.46 seconds
Started May 07 01:08:50 PM PDT 24
Finished May 07 01:09:51 PM PDT 24
Peak memory 194872 kb
Host smart-d5eb27a5-a7e2-4527-9582-01566a86ed92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031717259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2031717259
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4009353000
Short name T148
Test name
Test status
Simulation time 155439364238 ps
CPU time 74.28 seconds
Started May 07 01:08:52 PM PDT 24
Finished May 07 01:10:07 PM PDT 24
Peak memory 191256 kb
Host smart-abfa050d-aefc-4d23-b58c-8e0824ca20a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009353000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4009353000
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.528841571
Short name T308
Test name
Test status
Simulation time 301110046490 ps
CPU time 579.32 seconds
Started May 07 01:08:51 PM PDT 24
Finished May 07 01:18:31 PM PDT 24
Peak memory 191260 kb
Host smart-73853b86-9560-422e-a4df-59126f244808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528841571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.528841571
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2412653804
Short name T258
Test name
Test status
Simulation time 83706754733 ps
CPU time 64.06 seconds
Started May 07 01:08:57 PM PDT 24
Finished May 07 01:10:02 PM PDT 24
Peak memory 183092 kb
Host smart-be1ea034-508d-41fd-a55a-ca044a4b82a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412653804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2412653804
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1573539974
Short name T54
Test name
Test status
Simulation time 463833453318 ps
CPU time 1626.27 seconds
Started May 07 01:08:58 PM PDT 24
Finished May 07 01:36:05 PM PDT 24
Peak memory 191348 kb
Host smart-4dcee6d8-771b-4b3b-b911-675a2523fbd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573539974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1573539974
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3178673062
Short name T271
Test name
Test status
Simulation time 55039438543 ps
CPU time 80.37 seconds
Started May 07 01:07:29 PM PDT 24
Finished May 07 01:08:50 PM PDT 24
Peak memory 183016 kb
Host smart-28767652-16c4-40c5-b39a-4c0217036e3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178673062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3178673062
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1893757919
Short name T367
Test name
Test status
Simulation time 161082092430 ps
CPU time 121.57 seconds
Started May 07 01:07:31 PM PDT 24
Finished May 07 01:09:34 PM PDT 24
Peak memory 183064 kb
Host smart-22d1e7e9-bbb3-465b-9d5b-f9eb75fc2f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893757919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1893757919
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3060698986
Short name T390
Test name
Test status
Simulation time 498802407 ps
CPU time 1.67 seconds
Started May 07 01:07:34 PM PDT 24
Finished May 07 01:07:37 PM PDT 24
Peak memory 191184 kb
Host smart-b4243bb6-bf2f-463d-821d-c696b80cbd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060698986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3060698986
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1600950322
Short name T303
Test name
Test status
Simulation time 733882740820 ps
CPU time 702.55 seconds
Started May 07 01:07:29 PM PDT 24
Finished May 07 01:19:12 PM PDT 24
Peak memory 191256 kb
Host smart-bc268a10-5211-4b5e-bffc-b581a6d2a2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600950322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1600950322
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3569333752
Short name T409
Test name
Test status
Simulation time 17667827584 ps
CPU time 206.71 seconds
Started May 07 01:07:29 PM PDT 24
Finished May 07 01:10:57 PM PDT 24
Peak memory 197696 kb
Host smart-48e9cfab-3bad-4ad5-b602-c7d31b1b625b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569333752 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.3569333752
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1647075165
Short name T330
Test name
Test status
Simulation time 233027555828 ps
CPU time 217.35 seconds
Started May 07 01:08:59 PM PDT 24
Finished May 07 01:12:37 PM PDT 24
Peak memory 194640 kb
Host smart-257c7c1c-03f2-4a2d-a226-d8c0081da8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647075165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1647075165
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3163134183
Short name T281
Test name
Test status
Simulation time 98171938159 ps
CPU time 177.53 seconds
Started May 07 01:08:56 PM PDT 24
Finished May 07 01:11:54 PM PDT 24
Peak memory 191212 kb
Host smart-1e66fa84-0c44-41ce-98f7-dc26d3250caf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163134183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3163134183
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2644306423
Short name T226
Test name
Test status
Simulation time 83488048691 ps
CPU time 192.34 seconds
Started May 07 01:09:01 PM PDT 24
Finished May 07 01:12:14 PM PDT 24
Peak memory 191260 kb
Host smart-bb10b5d1-d01b-4bb8-9cb2-495c9d2d4799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644306423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2644306423
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.588321312
Short name T196
Test name
Test status
Simulation time 621494916285 ps
CPU time 2012.45 seconds
Started May 07 01:08:56 PM PDT 24
Finished May 07 01:42:30 PM PDT 24
Peak memory 182968 kb
Host smart-de0b9ba5-9e19-442c-8517-062ef6304e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588321312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.588321312
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3542738189
Short name T159
Test name
Test status
Simulation time 307486419272 ps
CPU time 91.16 seconds
Started May 07 01:08:59 PM PDT 24
Finished May 07 01:10:31 PM PDT 24
Peak memory 182944 kb
Host smart-88369803-9307-45b9-b746-934fc8443147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542738189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3542738189
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1682654864
Short name T268
Test name
Test status
Simulation time 215233471397 ps
CPU time 227.24 seconds
Started May 07 01:09:05 PM PDT 24
Finished May 07 01:12:54 PM PDT 24
Peak memory 191256 kb
Host smart-4008241d-0629-430d-8e80-d729ff624dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682654864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1682654864
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.4038607828
Short name T206
Test name
Test status
Simulation time 112765731473 ps
CPU time 171.29 seconds
Started May 07 01:09:06 PM PDT 24
Finished May 07 01:11:58 PM PDT 24
Peak memory 191244 kb
Host smart-5ae95f5e-82d8-440a-a95d-5de101b600c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038607828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4038607828
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2192693999
Short name T430
Test name
Test status
Simulation time 172171119243 ps
CPU time 84.64 seconds
Started May 07 01:09:06 PM PDT 24
Finished May 07 01:10:32 PM PDT 24
Peak memory 191204 kb
Host smart-957ae3b2-74ae-48cb-9e68-7c628d53f616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192693999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2192693999
Directory /workspace/99.rv_timer_random/latest
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