Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 578
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T506 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1153473454 May 09 12:39:31 PM PDT 24 May 09 12:39:38 PM PDT 24 58511557 ps
T507 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.532315390 May 09 12:38:32 PM PDT 24 May 09 12:38:49 PM PDT 24 14085886 ps
T508 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3877394456 May 09 12:38:36 PM PDT 24 May 09 12:38:55 PM PDT 24 112691289 ps
T509 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3158266163 May 09 12:38:37 PM PDT 24 May 09 12:38:56 PM PDT 24 368904679 ps
T510 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2007014149 May 09 12:38:43 PM PDT 24 May 09 12:39:01 PM PDT 24 325154374 ps
T511 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1011390857 May 09 12:38:48 PM PDT 24 May 09 12:39:04 PM PDT 24 20985821 ps
T512 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1663683065 May 09 12:39:01 PM PDT 24 May 09 12:39:15 PM PDT 24 57028179 ps
T513 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3613522827 May 09 12:38:30 PM PDT 24 May 09 12:38:47 PM PDT 24 165977543 ps
T92 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1781958255 May 09 12:38:13 PM PDT 24 May 09 12:38:32 PM PDT 24 75242840 ps
T514 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1078476950 May 09 12:38:46 PM PDT 24 May 09 12:39:03 PM PDT 24 61195216 ps
T515 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.778436914 May 09 12:38:32 PM PDT 24 May 09 12:38:49 PM PDT 24 14469698 ps
T93 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1417861444 May 09 12:38:30 PM PDT 24 May 09 12:38:47 PM PDT 24 30032466 ps
T108 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2515031521 May 09 12:39:46 PM PDT 24 May 09 12:39:56 PM PDT 24 1180302185 ps
T516 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3238653602 May 09 12:38:30 PM PDT 24 May 09 12:38:47 PM PDT 24 123266514 ps
T517 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1900414928 May 09 12:38:14 PM PDT 24 May 09 12:38:33 PM PDT 24 38913456 ps
T518 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2004101755 May 09 12:38:25 PM PDT 24 May 09 12:38:43 PM PDT 24 282550228 ps
T519 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.772968330 May 09 12:38:40 PM PDT 24 May 09 12:38:59 PM PDT 24 123907886 ps
T520 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.988664331 May 09 12:38:28 PM PDT 24 May 09 12:38:45 PM PDT 24 60191744 ps
T521 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3872633136 May 09 12:38:33 PM PDT 24 May 09 12:38:50 PM PDT 24 38472734 ps
T522 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.605793805 May 09 12:38:22 PM PDT 24 May 09 12:38:39 PM PDT 24 49338233 ps
T523 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3987547741 May 09 12:38:36 PM PDT 24 May 09 12:38:55 PM PDT 24 90461036 ps
T524 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2003216018 May 09 12:38:19 PM PDT 24 May 09 12:38:37 PM PDT 24 108352727 ps
T525 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2534091121 May 09 12:38:52 PM PDT 24 May 09 12:39:08 PM PDT 24 38181474 ps
T526 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1037192164 May 09 12:38:23 PM PDT 24 May 09 12:38:40 PM PDT 24 40572805 ps
T527 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4278541940 May 09 12:38:31 PM PDT 24 May 09 12:38:50 PM PDT 24 883113778 ps
T528 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1605260678 May 09 12:39:30 PM PDT 24 May 09 12:39:38 PM PDT 24 15737289 ps
T529 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2845897186 May 09 12:38:51 PM PDT 24 May 09 12:39:07 PM PDT 24 19551867 ps
T530 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3768079737 May 09 12:38:47 PM PDT 24 May 09 12:39:03 PM PDT 24 14560238 ps
T94 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2101440971 May 09 12:38:33 PM PDT 24 May 09 12:38:50 PM PDT 24 30588513 ps
T531 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2838008471 May 09 12:39:02 PM PDT 24 May 09 12:39:15 PM PDT 24 65917655 ps
T532 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1739342225 May 09 12:38:26 PM PDT 24 May 09 12:38:44 PM PDT 24 119472756 ps
T533 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2920539667 May 09 12:38:46 PM PDT 24 May 09 12:39:02 PM PDT 24 12130467 ps
T534 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1698660396 May 09 12:38:37 PM PDT 24 May 09 12:38:55 PM PDT 24 63956301 ps
T535 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.840333174 May 09 12:38:37 PM PDT 24 May 09 12:38:55 PM PDT 24 23216090 ps
T536 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.25984631 May 09 12:38:28 PM PDT 24 May 09 12:38:45 PM PDT 24 47121107 ps
T537 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2364844012 May 09 12:38:31 PM PDT 24 May 09 12:38:48 PM PDT 24 12172890 ps
T538 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.410033281 May 09 12:38:33 PM PDT 24 May 09 12:38:50 PM PDT 24 578882792 ps
T539 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3953158118 May 09 12:39:10 PM PDT 24 May 09 12:39:21 PM PDT 24 40625645 ps
T540 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2052349660 May 09 12:38:33 PM PDT 24 May 09 12:38:50 PM PDT 24 49445182 ps
T541 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1347362179 May 09 12:38:53 PM PDT 24 May 09 12:39:17 PM PDT 24 14536133 ps
T542 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1610481100 May 09 12:38:56 PM PDT 24 May 09 12:39:11 PM PDT 24 351602233 ps
T543 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1508952121 May 09 12:38:24 PM PDT 24 May 09 12:38:41 PM PDT 24 167651569 ps
T544 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2163896748 May 09 12:38:51 PM PDT 24 May 09 12:39:07 PM PDT 24 11912960 ps
T545 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3312834593 May 09 12:38:33 PM PDT 24 May 09 12:38:50 PM PDT 24 25180498 ps
T546 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1829669063 May 09 12:38:36 PM PDT 24 May 09 12:38:54 PM PDT 24 74511268 ps
T109 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.844636237 May 09 12:39:08 PM PDT 24 May 09 12:39:20 PM PDT 24 363074944 ps
T547 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3106637395 May 09 12:38:54 PM PDT 24 May 09 12:39:10 PM PDT 24 13377923 ps
T548 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2477337029 May 09 12:38:29 PM PDT 24 May 09 12:38:48 PM PDT 24 591025244 ps
T549 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.998445043 May 09 12:38:23 PM PDT 24 May 09 12:38:41 PM PDT 24 814238451 ps
T550 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.344591736 May 09 12:38:51 PM PDT 24 May 09 12:39:07 PM PDT 24 28586513 ps
T551 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.75503814 May 09 12:38:36 PM PDT 24 May 09 12:38:54 PM PDT 24 41768175 ps
T552 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3607924085 May 09 12:39:10 PM PDT 24 May 09 12:39:21 PM PDT 24 18464383 ps
T553 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.500683494 May 09 12:38:43 PM PDT 24 May 09 12:39:00 PM PDT 24 38147700 ps
T554 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3948798525 May 09 12:38:10 PM PDT 24 May 09 12:38:28 PM PDT 24 57183197 ps
T555 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.289313670 May 09 12:38:35 PM PDT 24 May 09 12:38:53 PM PDT 24 63420005 ps
T556 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1263407611 May 09 12:38:36 PM PDT 24 May 09 12:38:55 PM PDT 24 598544598 ps
T557 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2582117287 May 09 12:38:57 PM PDT 24 May 09 12:39:12 PM PDT 24 25381250 ps
T558 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1752217545 May 09 12:38:30 PM PDT 24 May 09 12:38:47 PM PDT 24 76529059 ps
T559 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3483163482 May 09 12:38:27 PM PDT 24 May 09 12:38:44 PM PDT 24 36041170 ps
T560 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3653424654 May 09 12:39:21 PM PDT 24 May 09 12:39:30 PM PDT 24 68347936 ps
T561 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3056787459 May 09 12:38:39 PM PDT 24 May 09 12:38:58 PM PDT 24 107074872 ps
T562 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3752738131 May 09 12:39:47 PM PDT 24 May 09 12:39:57 PM PDT 24 84363241 ps
T563 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2382254880 May 09 12:39:13 PM PDT 24 May 09 12:39:23 PM PDT 24 24298257 ps
T564 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2001128474 May 09 12:39:30 PM PDT 24 May 09 12:39:39 PM PDT 24 1332205576 ps
T565 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1582285650 May 09 12:38:36 PM PDT 24 May 09 12:38:55 PM PDT 24 127935054 ps
T566 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4111123436 May 09 12:38:55 PM PDT 24 May 09 12:39:10 PM PDT 24 19398165 ps
T567 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1369908995 May 09 12:38:28 PM PDT 24 May 09 12:38:45 PM PDT 24 14638914 ps
T568 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.183110198 May 09 12:38:18 PM PDT 24 May 09 12:38:36 PM PDT 24 44210356 ps
T569 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1094052833 May 09 12:38:28 PM PDT 24 May 09 12:38:45 PM PDT 24 44235858 ps
T570 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2855236268 May 09 12:38:51 PM PDT 24 May 09 12:39:07 PM PDT 24 80564633 ps
T571 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1433040609 May 09 12:38:29 PM PDT 24 May 09 12:38:45 PM PDT 24 22163027 ps
T572 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1526478770 May 09 12:38:36 PM PDT 24 May 09 12:38:54 PM PDT 24 22004142 ps
T573 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2189138585 May 09 12:38:35 PM PDT 24 May 09 12:38:56 PM PDT 24 757717722 ps
T574 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1973124518 May 09 12:38:09 PM PDT 24 May 09 12:38:27 PM PDT 24 67623623 ps
T575 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.644850969 May 09 12:38:18 PM PDT 24 May 09 12:38:36 PM PDT 24 24447836 ps
T576 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4210348557 May 09 12:38:20 PM PDT 24 May 09 12:38:39 PM PDT 24 70025605 ps
T577 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2893490259 May 09 12:38:43 PM PDT 24 May 09 12:39:01 PM PDT 24 26971932 ps
T578 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1093835216 May 09 12:38:33 PM PDT 24 May 09 12:38:50 PM PDT 24 167531386 ps

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.3895454298
Short name T7
Test name
Test status
Simulation time 262853710159 ps
CPU time 383.61 seconds
Started May 09 12:39:14 PM PDT 24
Finished May 09 12:45:47 PM PDT 24
Peak memory 205852 kb
Host smart-140db3e4-8382-46ec-ade5-a47b56e20022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895454298 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.3895454298
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_random.1705762231
Short name T3
Test name
Test status
Simulation time 126466888177 ps
CPU time 663.32 seconds
Started May 09 12:38:49 PM PDT 24
Finished May 09 12:50:07 PM PDT 24
Peak memory 191260 kb
Host smart-3b00a18d-ae06-4e9c-ba3c-0207e683b063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705762231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1705762231
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2427816534
Short name T28
Test name
Test status
Simulation time 53280755 ps
CPU time 0.86 seconds
Started May 09 12:38:25 PM PDT 24
Finished May 09 12:38:43 PM PDT 24
Peak memory 193544 kb
Host smart-b22e7d31-be2c-45b7-b178-a7ad1cb98099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427816534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2427816534
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3185984772
Short name T114
Test name
Test status
Simulation time 878686705421 ps
CPU time 2321.86 seconds
Started May 09 12:38:54 PM PDT 24
Finished May 09 01:17:51 PM PDT 24
Peak memory 191176 kb
Host smart-a3fac3e8-6eb8-4a16-bc0a-9198d3fe426d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185984772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3185984772
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.32087313
Short name T61
Test name
Test status
Simulation time 1535038385189 ps
CPU time 762.31 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:52:12 PM PDT 24
Peak memory 191200 kb
Host smart-75b815b2-e393-48cc-9944-7fb328910fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32087313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.32087313
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1174143687
Short name T226
Test name
Test status
Simulation time 1095549906299 ps
CPU time 5763.82 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 02:15:43 PM PDT 24
Peak memory 191260 kb
Host smart-a100b0f0-ad7a-4d50-b734-0f97f3bfa0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174143687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1174143687
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3707369013
Short name T181
Test name
Test status
Simulation time 755643077494 ps
CPU time 1976.52 seconds
Started May 09 12:39:04 PM PDT 24
Finished May 09 01:12:14 PM PDT 24
Peak memory 191244 kb
Host smart-c8b3cf16-cc6c-4176-a399-b14c475eeb11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707369013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3707369013
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1399906405
Short name T133
Test name
Test status
Simulation time 663703145347 ps
CPU time 2701.74 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 01:24:43 PM PDT 24
Peak memory 191212 kb
Host smart-8f54c609-68ab-4716-a3ed-701f7475779a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399906405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1399906405
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1480066304
Short name T134
Test name
Test status
Simulation time 3268606825614 ps
CPU time 1542.15 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 01:05:17 PM PDT 24
Peak memory 191228 kb
Host smart-926ff511-483d-47eb-a2d0-8ef987f86fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480066304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1480066304
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1250217351
Short name T217
Test name
Test status
Simulation time 5282078472845 ps
CPU time 3287.94 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 01:34:02 PM PDT 24
Peak memory 191220 kb
Host smart-36dccd6c-4aac-4b46-bce5-27067ce39e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250217351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1250217351
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2854423395
Short name T76
Test name
Test status
Simulation time 72797209 ps
CPU time 0.54 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:49 PM PDT 24
Peak memory 182620 kb
Host smart-a9338cb8-dcf3-4511-89ae-09621765502d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854423395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2854423395
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/80.rv_timer_random.1947522482
Short name T121
Test name
Test status
Simulation time 664138796613 ps
CPU time 323.15 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:45:20 PM PDT 24
Peak memory 194832 kb
Host smart-0e197f44-8749-4e98-a6db-acd46fb24717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947522482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1947522482
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1358720707
Short name T184
Test name
Test status
Simulation time 1467439843607 ps
CPU time 3587.22 seconds
Started May 09 12:39:12 PM PDT 24
Finished May 09 01:39:10 PM PDT 24
Peak memory 191228 kb
Host smart-78a484ef-b01a-4196-bf20-4c4ffa02997c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358720707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1358720707
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1959214290
Short name T17
Test name
Test status
Simulation time 35316641 ps
CPU time 0.75 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:39:03 PM PDT 24
Peak memory 213628 kb
Host smart-b8c1c77b-4305-49d4-8564-c898135e0433
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959214290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1959214290
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3422441352
Short name T131
Test name
Test status
Simulation time 348697495762 ps
CPU time 1138.72 seconds
Started May 09 12:38:50 PM PDT 24
Finished May 09 12:58:05 PM PDT 24
Peak memory 196200 kb
Host smart-2136fd33-14e0-4571-bbbf-9de5219d519d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422441352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3422441352
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.971348389
Short name T264
Test name
Test status
Simulation time 1939593260930 ps
CPU time 1075.97 seconds
Started May 09 12:38:57 PM PDT 24
Finished May 09 12:57:07 PM PDT 24
Peak memory 191140 kb
Host smart-583eb63d-0fa4-4ddf-8a4f-6ee975cdc1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971348389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.971348389
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.624549062
Short name T216
Test name
Test status
Simulation time 813645496331 ps
CPU time 1500.86 seconds
Started May 09 12:38:55 PM PDT 24
Finished May 09 01:04:11 PM PDT 24
Peak memory 191240 kb
Host smart-ec047498-7b9b-480b-a038-ef37719ff09c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624549062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
624549062
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.2065680267
Short name T38
Test name
Test status
Simulation time 81798491599 ps
CPU time 127.37 seconds
Started May 09 12:39:52 PM PDT 24
Finished May 09 12:42:11 PM PDT 24
Peak memory 191212 kb
Host smart-2ae12c89-44ed-458b-bef9-174d99758acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065680267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2065680267
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1660781436
Short name T255
Test name
Test status
Simulation time 109513299007 ps
CPU time 962.64 seconds
Started May 09 12:39:52 PM PDT 24
Finished May 09 12:56:07 PM PDT 24
Peak memory 191224 kb
Host smart-9f0386a9-6186-4bbe-9f2e-b4b46e597862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660781436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1660781436
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.3887862475
Short name T118
Test name
Test status
Simulation time 362774823466 ps
CPU time 525.32 seconds
Started May 09 12:39:12 PM PDT 24
Finished May 09 12:48:07 PM PDT 24
Peak memory 191212 kb
Host smart-2039b64e-4d93-45f9-a73c-61d7c8ff0126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887862475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3887862475
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2332832184
Short name T201
Test name
Test status
Simulation time 3276107477523 ps
CPU time 1446.35 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 01:03:55 PM PDT 24
Peak memory 191256 kb
Host smart-b390cb9f-d2e8-41f2-97d8-313220857610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332832184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2332832184
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2123658947
Short name T282
Test name
Test status
Simulation time 3967341300285 ps
CPU time 2039.57 seconds
Started May 09 12:39:04 PM PDT 24
Finished May 09 01:13:17 PM PDT 24
Peak memory 191168 kb
Host smart-17413b45-b6ed-413b-ad12-33a835099bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123658947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2123658947
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2697954276
Short name T50
Test name
Test status
Simulation time 133146893557 ps
CPU time 246.12 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:43:35 PM PDT 24
Peak memory 194884 kb
Host smart-81c6a4f5-6598-41d7-8f39-0ddea6fd6c8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697954276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2697954276
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3966783041
Short name T171
Test name
Test status
Simulation time 76722828887 ps
CPU time 506.63 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:47:57 PM PDT 24
Peak memory 191216 kb
Host smart-f0b7eb5c-e310-4bb2-afaf-b8c5d5c36aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966783041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3966783041
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.28296643
Short name T143
Test name
Test status
Simulation time 579123798627 ps
CPU time 564.01 seconds
Started May 09 12:39:34 PM PDT 24
Finished May 09 12:49:06 PM PDT 24
Peak memory 191228 kb
Host smart-29c08f8b-4326-4c49-b682-72cdcd4b474d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28296643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.28296643
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2085705875
Short name T450
Test name
Test status
Simulation time 101044051167 ps
CPU time 377.97 seconds
Started May 09 12:39:56 PM PDT 24
Finished May 09 12:46:27 PM PDT 24
Peak memory 193488 kb
Host smart-a013a5b2-843e-4bd7-8209-77c87fb912f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085705875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2085705875
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1229694757
Short name T258
Test name
Test status
Simulation time 341632056700 ps
CPU time 312.84 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:45:07 PM PDT 24
Peak memory 191236 kb
Host smart-5340f273-0fa8-40d7-824b-aed48464e488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229694757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1229694757
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2275410890
Short name T354
Test name
Test status
Simulation time 1309205530745 ps
CPU time 532.3 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:48:46 PM PDT 24
Peak memory 191112 kb
Host smart-7854df90-d05e-4f4e-bfe5-6b351176073a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275410890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2275410890
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3875231453
Short name T349
Test name
Test status
Simulation time 716031359689 ps
CPU time 297.94 seconds
Started May 09 12:39:36 PM PDT 24
Finished May 09 12:44:42 PM PDT 24
Peak memory 191248 kb
Host smart-0e7cae4a-16a9-4a00-8717-3eb18e825b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875231453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3875231453
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1451598288
Short name T60
Test name
Test status
Simulation time 784194325604 ps
CPU time 929.22 seconds
Started May 09 12:39:00 PM PDT 24
Finished May 09 12:54:43 PM PDT 24
Peak memory 191256 kb
Host smart-5b740bb0-c539-40c2-8a8c-7bfd7492e5c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451598288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1451598288
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/158.rv_timer_random.1176218371
Short name T116
Test name
Test status
Simulation time 175660385244 ps
CPU time 296.37 seconds
Started May 09 12:39:39 PM PDT 24
Finished May 09 12:44:43 PM PDT 24
Peak memory 191224 kb
Host smart-e8912790-bc25-455a-887a-09cf806ffa2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176218371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1176218371
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3988060262
Short name T291
Test name
Test status
Simulation time 1998956959400 ps
CPU time 1063.51 seconds
Started May 09 12:39:25 PM PDT 24
Finished May 09 12:57:15 PM PDT 24
Peak memory 195540 kb
Host smart-db6c3591-4948-4924-9eb0-740452d64a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988060262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3988060262
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_random.3135556612
Short name T172
Test name
Test status
Simulation time 361901241983 ps
CPU time 709.78 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:51:29 PM PDT 24
Peak memory 191232 kb
Host smart-c9e3f7e4-e021-41a9-b37a-2be8666c1c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135556612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3135556612
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3168325167
Short name T152
Test name
Test status
Simulation time 1284069691945 ps
CPU time 1076.89 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:57:03 PM PDT 24
Peak memory 191260 kb
Host smart-b08b2ced-b228-4334-889b-d61de5b8b4ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168325167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3168325167
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.4201286546
Short name T228
Test name
Test status
Simulation time 166020904172 ps
CPU time 456.31 seconds
Started May 09 12:39:45 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 182960 kb
Host smart-877fb34e-eb35-4d58-b880-64c44a7b19a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201286546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.4201286546
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.1612414454
Short name T157
Test name
Test status
Simulation time 106327316038 ps
CPU time 336.86 seconds
Started May 09 12:39:48 PM PDT 24
Finished May 09 12:45:35 PM PDT 24
Peak memory 191220 kb
Host smart-3fee77d8-6e9b-42c5-99ba-a668261aca5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612414454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1612414454
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1012167405
Short name T51
Test name
Test status
Simulation time 787542574899 ps
CPU time 506.62 seconds
Started May 09 12:39:45 PM PDT 24
Finished May 09 12:48:20 PM PDT 24
Peak memory 192196 kb
Host smart-543c5ef9-0b78-48f4-ba98-527295ab2261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012167405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1012167405
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2382106059
Short name T263
Test name
Test status
Simulation time 169611408675 ps
CPU time 304.91 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:45:02 PM PDT 24
Peak memory 195020 kb
Host smart-f278ab2a-0229-418f-a9a3-f6194e721e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382106059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2382106059
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2787450132
Short name T220
Test name
Test status
Simulation time 300013501629 ps
CPU time 253.73 seconds
Started May 09 12:39:35 PM PDT 24
Finished May 09 12:43:57 PM PDT 24
Peak memory 191224 kb
Host smart-b4429b58-74c8-4966-950b-56504b8cc7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787450132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2787450132
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1139669323
Short name T107
Test name
Test status
Simulation time 119357944 ps
CPU time 1.42 seconds
Started May 09 12:38:16 PM PDT 24
Finished May 09 12:38:35 PM PDT 24
Peak memory 183124 kb
Host smart-b3367392-c9e7-4791-a8f6-3acc234091c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139669323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1139669323
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/108.rv_timer_random.2628826744
Short name T223
Test name
Test status
Simulation time 138329796968 ps
CPU time 295.26 seconds
Started May 09 12:39:52 PM PDT 24
Finished May 09 12:45:00 PM PDT 24
Peak memory 191228 kb
Host smart-472aa79e-f8ad-4476-80b5-ce18c4dbc29c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628826744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2628826744
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3496173274
Short name T269
Test name
Test status
Simulation time 132140320702 ps
CPU time 165.78 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:42:45 PM PDT 24
Peak memory 194004 kb
Host smart-eae26697-9b0f-424c-8fdd-1d4f9fc2098f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496173274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3496173274
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2444273775
Short name T88
Test name
Test status
Simulation time 222542393036 ps
CPU time 299.66 seconds
Started May 09 12:39:45 PM PDT 24
Finished May 09 12:44:53 PM PDT 24
Peak memory 191192 kb
Host smart-473c83f8-e27b-491d-b02f-28ed0828c01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444273775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2444273775
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2602064818
Short name T292
Test name
Test status
Simulation time 893845834898 ps
CPU time 432.9 seconds
Started May 09 12:39:03 PM PDT 24
Finished May 09 12:46:29 PM PDT 24
Peak memory 191224 kb
Host smart-f9ef5ff6-be45-4f7c-9f94-bfcc0ace956b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602064818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2602064818
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/184.rv_timer_random.662960800
Short name T343
Test name
Test status
Simulation time 258941594776 ps
CPU time 347.4 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:45:35 PM PDT 24
Peak memory 191232 kb
Host smart-32edc073-de02-484b-95ec-8e8b73ec9b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662960800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.662960800
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.4153030014
Short name T187
Test name
Test status
Simulation time 146156768854 ps
CPU time 231.23 seconds
Started May 09 12:39:17 PM PDT 24
Finished May 09 12:43:17 PM PDT 24
Peak memory 191208 kb
Host smart-1bc48271-14d4-4108-a99a-1aa0046d5490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153030014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4153030014
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2892519435
Short name T180
Test name
Test status
Simulation time 1785704020316 ps
CPU time 3591.14 seconds
Started May 09 12:39:17 PM PDT 24
Finished May 09 01:39:17 PM PDT 24
Peak memory 196072 kb
Host smart-090ee30b-e869-47f6-8e55-3d87fba33a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892519435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2892519435
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3287994245
Short name T176
Test name
Test status
Simulation time 1465400893055 ps
CPU time 761.35 seconds
Started May 09 12:38:59 PM PDT 24
Finished May 09 12:51:54 PM PDT 24
Peak memory 183044 kb
Host smart-2ccbcb19-5d97-4b45-8db4-043152a86b9b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287994245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3287994245
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2266011344
Short name T148
Test name
Test status
Simulation time 781342210415 ps
CPU time 341.79 seconds
Started May 09 12:39:15 PM PDT 24
Finished May 09 12:45:06 PM PDT 24
Peak memory 183028 kb
Host smart-d99d2fc0-dd70-43d1-862f-889b1a2bad3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266011344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2266011344
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/133.rv_timer_random.2934291243
Short name T200
Test name
Test status
Simulation time 431976046715 ps
CPU time 602.9 seconds
Started May 09 12:39:43 PM PDT 24
Finished May 09 12:49:53 PM PDT 24
Peak memory 191060 kb
Host smart-1445a340-b207-4452-8690-8abf7d17e0f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934291243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2934291243
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2049536734
Short name T160
Test name
Test status
Simulation time 135443915543 ps
CPU time 108.37 seconds
Started May 09 12:39:50 PM PDT 24
Finished May 09 12:41:50 PM PDT 24
Peak memory 191208 kb
Host smart-8c4ee9e4-781c-43ae-bc5e-203aa087a864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049536734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2049536734
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.707738322
Short name T154
Test name
Test status
Simulation time 2195514077757 ps
CPU time 1247.98 seconds
Started May 09 12:39:03 PM PDT 24
Finished May 09 01:00:04 PM PDT 24
Peak memory 183008 kb
Host smart-cc0de70c-87cd-4c8c-b789-421b09881a98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707738322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.707738322
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/150.rv_timer_random.1139488338
Short name T179
Test name
Test status
Simulation time 110978064967 ps
CPU time 594.98 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:49:55 PM PDT 24
Peak memory 194764 kb
Host smart-cde1a5f8-6efe-469d-9ba2-1b86a7345081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139488338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1139488338
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.892031221
Short name T233
Test name
Test status
Simulation time 328108892538 ps
CPU time 177.27 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:42:52 PM PDT 24
Peak memory 191160 kb
Host smart-4d39e131-1aba-45ff-afe5-5ca128407532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892031221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.892031221
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1522198968
Short name T248
Test name
Test status
Simulation time 148071598276 ps
CPU time 307.72 seconds
Started May 09 12:39:39 PM PDT 24
Finished May 09 12:44:54 PM PDT 24
Peak memory 191220 kb
Host smart-cb13dabb-b75e-464e-8eb9-4e1501f62bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522198968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1522198968
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.4261651598
Short name T249
Test name
Test status
Simulation time 222631317660 ps
CPU time 294.73 seconds
Started May 09 12:39:48 PM PDT 24
Finished May 09 12:44:53 PM PDT 24
Peak memory 191200 kb
Host smart-20fc2462-b3db-48d3-898a-971f6e0dd40a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261651598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.4261651598
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1769449781
Short name T225
Test name
Test status
Simulation time 36916172231 ps
CPU time 83.99 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:41:00 PM PDT 24
Peak memory 183056 kb
Host smart-6b5b0e5c-24c1-4c9e-af5e-acff0bf6b105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769449781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1769449781
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/87.rv_timer_random.968313305
Short name T205
Test name
Test status
Simulation time 358121710216 ps
CPU time 694.76 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:51:34 PM PDT 24
Peak memory 191256 kb
Host smart-906b504d-643c-4997-9a6e-32d51ab482a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968313305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.968313305
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3122782070
Short name T103
Test name
Test status
Simulation time 46696132 ps
CPU time 0.81 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 194420 kb
Host smart-86fccfda-a2e9-4d91-be11-6d4800d0cdd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122782070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3122782070
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3771143573
Short name T73
Test name
Test status
Simulation time 92777248217 ps
CPU time 138.8 seconds
Started May 09 12:38:58 PM PDT 24
Finished May 09 12:41:31 PM PDT 24
Peak memory 182936 kb
Host smart-de8939a7-7830-4ad1-a55d-6170c195f5f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771143573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3771143573
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.438473609
Short name T299
Test name
Test status
Simulation time 673070506892 ps
CPU time 673.48 seconds
Started May 09 12:39:02 PM PDT 24
Finished May 09 12:50:29 PM PDT 24
Peak memory 183028 kb
Host smart-fd0f357d-49bf-407f-8d39-3d015b806bd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438473609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.438473609
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/110.rv_timer_random.1731533678
Short name T20
Test name
Test status
Simulation time 105290977903 ps
CPU time 334.68 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:45:08 PM PDT 24
Peak memory 191164 kb
Host smart-e6367e81-ecb3-44aa-ae6a-102d2355089a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731533678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1731533678
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.891466952
Short name T293
Test name
Test status
Simulation time 321379783081 ps
CPU time 484.41 seconds
Started May 09 12:39:36 PM PDT 24
Finished May 09 12:47:48 PM PDT 24
Peak memory 191248 kb
Host smart-632feb15-3931-40c1-b094-ca91bbfca315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891466952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.891466952
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.4161807747
Short name T155
Test name
Test status
Simulation time 120394477005 ps
CPU time 1265.08 seconds
Started May 09 12:39:48 PM PDT 24
Finished May 09 01:01:03 PM PDT 24
Peak memory 191200 kb
Host smart-91ae8efe-ad0e-4ab5-9eaa-efe0c127ece5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161807747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4161807747
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3359198174
Short name T65
Test name
Test status
Simulation time 378582618415 ps
CPU time 828.95 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:53:29 PM PDT 24
Peak memory 191136 kb
Host smart-f1d22a8f-2154-4067-bb0d-67313f7cba0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359198174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3359198174
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/157.rv_timer_random.3131310120
Short name T140
Test name
Test status
Simulation time 196904030276 ps
CPU time 136.46 seconds
Started May 09 12:39:44 PM PDT 24
Finished May 09 12:42:08 PM PDT 24
Peak memory 191104 kb
Host smart-b780e4f3-ea6a-4621-bbc9-7acad1ca9f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131310120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3131310120
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.4193877461
Short name T124
Test name
Test status
Simulation time 1057017016659 ps
CPU time 2022.34 seconds
Started May 09 12:39:38 PM PDT 24
Finished May 09 01:13:28 PM PDT 24
Peak memory 191240 kb
Host smart-6f043ffa-7baf-4a49-9a11-d012ac2a8cb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193877461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4193877461
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4230969347
Short name T301
Test name
Test status
Simulation time 685605250315 ps
CPU time 412.82 seconds
Started May 09 12:39:48 PM PDT 24
Finished May 09 12:46:50 PM PDT 24
Peak memory 191248 kb
Host smart-4f49bdfe-71ed-4639-ae1f-45be48916d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230969347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4230969347
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.3158997230
Short name T213
Test name
Test status
Simulation time 435476884538 ps
CPU time 238.9 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:43:32 PM PDT 24
Peak memory 191128 kb
Host smart-ad5dafaf-e086-40fd-9e6c-41acd9b2a029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158997230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3158997230
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1384914589
Short name T141
Test name
Test status
Simulation time 68235762667 ps
CPU time 165.94 seconds
Started May 09 12:39:40 PM PDT 24
Finished May 09 12:42:33 PM PDT 24
Peak memory 191184 kb
Host smart-e72262a6-fd2c-48ff-88f1-78f7f506fed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384914589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1384914589
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.16199268
Short name T149
Test name
Test status
Simulation time 630048132526 ps
CPU time 280.94 seconds
Started May 09 12:39:48 PM PDT 24
Finished May 09 12:44:40 PM PDT 24
Peak memory 191164 kb
Host smart-c08c2911-04e0-4198-9ec8-928ad0001ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16199268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.16199268
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.150738921
Short name T256
Test name
Test status
Simulation time 68370578414 ps
CPU time 342.36 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:45:42 PM PDT 24
Peak memory 191252 kb
Host smart-608904e9-9591-45b1-88d7-ee10ad992ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150738921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.150738921
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2094462781
Short name T163
Test name
Test status
Simulation time 184789440271 ps
CPU time 154.2 seconds
Started May 09 12:39:24 PM PDT 24
Finished May 09 12:42:05 PM PDT 24
Peak memory 191224 kb
Host smart-8cc1bd8c-ef49-417a-92ad-7c757ef6928f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094462781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2094462781
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1334555394
Short name T151
Test name
Test status
Simulation time 312059982856 ps
CPU time 506.53 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:48:04 PM PDT 24
Peak memory 183000 kb
Host smart-5d6446aa-b23d-4fba-9742-57504805365b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334555394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1334555394
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4256405889
Short name T288
Test name
Test status
Simulation time 239533110464 ps
CPU time 428.88 seconds
Started May 09 12:39:09 PM PDT 24
Finished May 09 12:46:29 PM PDT 24
Peak memory 183032 kb
Host smart-7ab4a959-064a-4fb1-8a5d-f3a89784e683
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256405889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4256405889
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2096804708
Short name T221
Test name
Test status
Simulation time 82892929117 ps
CPU time 150.6 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:42:04 PM PDT 24
Peak memory 182964 kb
Host smart-2d220de2-e397-4fa6-9b91-6ac34db063e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096804708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2096804708
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random.2010200417
Short name T272
Test name
Test status
Simulation time 29508020763 ps
CPU time 92.89 seconds
Started May 09 12:38:54 PM PDT 24
Finished May 09 12:40:42 PM PDT 24
Peak memory 191136 kb
Host smart-efef143a-575c-40a7-b44e-16bb27d35898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010200417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2010200417
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.1203589128
Short name T302
Test name
Test status
Simulation time 136087495314 ps
CPU time 208.99 seconds
Started May 09 12:39:23 PM PDT 24
Finished May 09 12:42:59 PM PDT 24
Peak memory 191196 kb
Host smart-400e4bb1-e137-445d-8ed2-4d3db3a4f245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203589128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1203589128
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.925982201
Short name T196
Test name
Test status
Simulation time 613473093971 ps
CPU time 1387.5 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 01:02:10 PM PDT 24
Peak memory 191500 kb
Host smart-3d9d2a52-d578-48bd-9b8f-20eb42258110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925982201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.925982201
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.4226822342
Short name T174
Test name
Test status
Simulation time 85443152348 ps
CPU time 1477.99 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 01:04:26 PM PDT 24
Peak memory 191164 kb
Host smart-4f94e72a-ccda-460a-9101-48839173b3e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226822342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4226822342
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2254740986
Short name T254
Test name
Test status
Simulation time 146626586255 ps
CPU time 153.39 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:42:30 PM PDT 24
Peak memory 191216 kb
Host smart-d0b8d6d5-ed42-40c5-affe-af018c881322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254740986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2254740986
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2944004191
Short name T125
Test name
Test status
Simulation time 557987324008 ps
CPU time 316.45 seconds
Started May 09 12:39:34 PM PDT 24
Finished May 09 12:44:58 PM PDT 24
Peak memory 191236 kb
Host smart-09647b18-71bf-4379-bcad-b5306c93cc4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944004191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2944004191
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3805729221
Short name T164
Test name
Test status
Simulation time 448936941333 ps
CPU time 273.29 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:43:48 PM PDT 24
Peak memory 191244 kb
Host smart-6e8be3e4-6e64-48f1-bbc6-984f004eb6f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805729221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3805729221
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3470743393
Short name T252
Test name
Test status
Simulation time 55047058733 ps
CPU time 134.5 seconds
Started May 09 12:39:39 PM PDT 24
Finished May 09 12:42:01 PM PDT 24
Peak memory 191188 kb
Host smart-dd4c7712-14fe-4956-8fcb-1304b82c8b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470743393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3470743393
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.517712663
Short name T320
Test name
Test status
Simulation time 334620917276 ps
CPU time 506.54 seconds
Started May 09 12:39:09 PM PDT 24
Finished May 09 12:47:46 PM PDT 24
Peak memory 183036 kb
Host smart-3c67e0d0-61bb-49a6-8267-37e244de2689
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517712663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.517712663
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random.3743218967
Short name T198
Test name
Test status
Simulation time 26362356252 ps
CPU time 90.66 seconds
Started May 09 12:38:57 PM PDT 24
Finished May 09 12:40:42 PM PDT 24
Peak memory 191232 kb
Host smart-80ad23ca-a363-4d41-892c-0c47e03ca337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743218967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3743218967
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.19516924
Short name T351
Test name
Test status
Simulation time 45469692883 ps
CPU time 72.09 seconds
Started May 09 12:39:43 PM PDT 24
Finished May 09 12:41:02 PM PDT 24
Peak memory 183012 kb
Host smart-cbd72756-b218-47e8-b255-a094e8726481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19516924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.19516924
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.2592867556
Short name T129
Test name
Test status
Simulation time 104881439786 ps
CPU time 148.2 seconds
Started May 09 12:39:02 PM PDT 24
Finished May 09 12:41:43 PM PDT 24
Peak memory 191244 kb
Host smart-ee602233-ec91-4520-986a-58b11d2a0a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592867556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2592867556
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2218579082
Short name T166
Test name
Test status
Simulation time 562723788339 ps
CPU time 352.62 seconds
Started May 09 12:39:48 PM PDT 24
Finished May 09 12:45:51 PM PDT 24
Peak memory 191208 kb
Host smart-39cfeae4-9a31-4d64-aa86-4071911f4543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218579082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2218579082
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2832588847
Short name T6
Test name
Test status
Simulation time 45973961852 ps
CPU time 75.4 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:40:30 PM PDT 24
Peak memory 183040 kb
Host smart-6fde4f96-537d-494d-8aa5-05ef8ebda1f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832588847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2832588847
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/173.rv_timer_random.1400115712
Short name T251
Test name
Test status
Simulation time 113353802451 ps
CPU time 287.29 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:44:42 PM PDT 24
Peak memory 191232 kb
Host smart-bb2a0032-97c3-4ea5-97ab-479affa82cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400115712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1400115712
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.601733851
Short name T178
Test name
Test status
Simulation time 567700646927 ps
CPU time 360.12 seconds
Started May 09 12:39:57 PM PDT 24
Finished May 09 12:46:10 PM PDT 24
Peak memory 191200 kb
Host smart-5e7fbeee-a6b8-4083-980c-8e7b1b3d3fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601733851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.601733851
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1565244276
Short name T128
Test name
Test status
Simulation time 2312990614796 ps
CPU time 1203.05 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:59:32 PM PDT 24
Peak memory 182964 kb
Host smart-ec7f99b7-e117-4056-a512-2ef121d5072f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565244276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1565244276
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.585966906
Short name T298
Test name
Test status
Simulation time 474917587224 ps
CPU time 793.32 seconds
Started May 09 12:39:13 PM PDT 24
Finished May 09 12:52:36 PM PDT 24
Peak memory 194772 kb
Host smart-5f003912-e450-47e7-82f4-bccf9cb2e73f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585966906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.585966906
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3308379937
Short name T183
Test name
Test status
Simulation time 88735804352 ps
CPU time 152.53 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:42:02 PM PDT 24
Peak memory 183008 kb
Host smart-c917d45b-c879-459c-80ce-9ca5b99f9298
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308379937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3308379937
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1002007457
Short name T168
Test name
Test status
Simulation time 433840206739 ps
CPU time 257.3 seconds
Started May 09 12:39:39 PM PDT 24
Finished May 09 12:44:04 PM PDT 24
Peak memory 183056 kb
Host smart-baf3e7bc-7e4a-4cb2-a279-f0bfc2bf1010
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002007457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1002007457
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random.3509495762
Short name T300
Test name
Test status
Simulation time 144366472032 ps
CPU time 1884.54 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 01:10:28 PM PDT 24
Peak memory 191212 kb
Host smart-c1115eb3-6fd3-49d9-8d27-8f9d318f5539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509495762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3509495762
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.4164503643
Short name T355
Test name
Test status
Simulation time 4159957520176 ps
CPU time 896.46 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:54:37 PM PDT 24
Peak memory 191212 kb
Host smart-9168add4-2501-455c-8744-a3081ad51666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164503643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.4164503643
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2102883493
Short name T347
Test name
Test status
Simulation time 131493826612 ps
CPU time 248.42 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:44:04 PM PDT 24
Peak memory 183012 kb
Host smart-84f1de0b-a268-4894-a3f4-4b8390fc1553
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102883493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2102883493
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/59.rv_timer_random.1158069420
Short name T295
Test name
Test status
Simulation time 33468397973 ps
CPU time 60.3 seconds
Started May 09 12:39:24 PM PDT 24
Finished May 09 12:40:32 PM PDT 24
Peak memory 191208 kb
Host smart-e33f9d54-b955-4899-acc7-3379bd6fb37f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158069420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1158069420
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3121200616
Short name T208
Test name
Test status
Simulation time 189971857071 ps
CPU time 172.07 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:42:30 PM PDT 24
Peak memory 191132 kb
Host smart-f02085b8-2bcd-4636-b0a9-8aaf08f20f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121200616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3121200616
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.532491385
Short name T57
Test name
Test status
Simulation time 156114138545 ps
CPU time 444 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:47:03 PM PDT 24
Peak memory 191240 kb
Host smart-7eff3a00-97b2-4e93-932b-0b40c0f4228e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532491385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.532491385
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3674947594
Short name T53
Test name
Test status
Simulation time 447965729452 ps
CPU time 616.15 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:49:54 PM PDT 24
Peak memory 191244 kb
Host smart-c5777a5c-cd2a-42cd-9a2f-6119001a4948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674947594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3674947594
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1973124518
Short name T574
Test name
Test status
Simulation time 67623623 ps
CPU time 0.6 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 191936 kb
Host smart-013bd2fa-e7bc-46c6-9375-616914f2dd99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973124518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1973124518
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.374967995
Short name T90
Test name
Test status
Simulation time 65406695 ps
CPU time 2.37 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:31 PM PDT 24
Peak memory 191088 kb
Host smart-b947d355-90cb-4bdc-aa4a-24a7199ea413
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374967995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.374967995
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.183110198
Short name T568
Test name
Test status
Simulation time 44210356 ps
CPU time 0.53 seconds
Started May 09 12:38:18 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 182692 kb
Host smart-a08bff3f-1066-405b-a6ed-f466091597aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183110198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.183110198
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.608454188
Short name T488
Test name
Test status
Simulation time 29124914 ps
CPU time 0.75 seconds
Started May 09 12:38:21 PM PDT 24
Finished May 09 12:38:39 PM PDT 24
Peak memory 195240 kb
Host smart-19230606-66fc-4334-8697-4584a5308042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608454188 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.608454188
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3948798525
Short name T554
Test name
Test status
Simulation time 57183197 ps
CPU time 0.57 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 182480 kb
Host smart-18cdda06-6d20-4d60-8664-006fd649125e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948798525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3948798525
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.575366016
Short name T451
Test name
Test status
Simulation time 13735433 ps
CPU time 0.52 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 182240 kb
Host smart-eb9c5bfc-de89-45c4-a836-3bb99d57ff3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575366016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.575366016
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1323244255
Short name T476
Test name
Test status
Simulation time 20533332 ps
CPU time 0.97 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 197156 kb
Host smart-bf25a095-ca43-4caf-9655-de86a3462597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323244255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1323244255
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1878488318
Short name T106
Test name
Test status
Simulation time 18196626 ps
CPU time 0.68 seconds
Started May 09 12:38:26 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 182596 kb
Host smart-9b06afc8-a194-4fd2-be82-e34a4730311a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878488318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1878488318
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4278541940
Short name T527
Test name
Test status
Simulation time 883113778 ps
CPU time 2.51 seconds
Started May 09 12:38:31 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 193604 kb
Host smart-cbca5825-ae35-45f0-b506-fc54d54de88e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278541940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4278541940
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3000648161
Short name T95
Test name
Test status
Simulation time 274950755 ps
CPU time 0.55 seconds
Started May 09 12:39:13 PM PDT 24
Finished May 09 12:39:23 PM PDT 24
Peak memory 182608 kb
Host smart-00276ca3-a73e-49c8-9a1f-327145ebc139
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000648161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3000648161
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.160543811
Short name T503
Test name
Test status
Simulation time 28121211 ps
CPU time 1.2 seconds
Started May 09 12:38:31 PM PDT 24
Finished May 09 12:38:49 PM PDT 24
Peak memory 197660 kb
Host smart-6744c072-5d6b-49ce-89d9-9494eee6f20b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160543811 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.160543811
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1180393621
Short name T46
Test name
Test status
Simulation time 37261238 ps
CPU time 0.53 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 182716 kb
Host smart-1d82ad47-c599-40a8-8264-e5f1315625f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180393621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1180393621
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4247782975
Short name T494
Test name
Test status
Simulation time 16090986 ps
CPU time 0.53 seconds
Started May 09 12:38:16 PM PDT 24
Finished May 09 12:38:35 PM PDT 24
Peak memory 182608 kb
Host smart-d4172f84-1c4b-4928-914e-d8f77467a6e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247782975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4247782975
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2003216018
Short name T524
Test name
Test status
Simulation time 108352727 ps
CPU time 0.72 seconds
Started May 09 12:38:19 PM PDT 24
Finished May 09 12:38:37 PM PDT 24
Peak memory 192212 kb
Host smart-3cc5a643-ee80-4e2c-bab9-aeffb931588e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003216018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2003216018
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2477337029
Short name T548
Test name
Test status
Simulation time 591025244 ps
CPU time 2.68 seconds
Started May 09 12:38:29 PM PDT 24
Finished May 09 12:38:48 PM PDT 24
Peak memory 197488 kb
Host smart-c2303aaa-de6e-48c8-be40-07c7f66a61d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477337029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2477337029
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2523613157
Short name T505
Test name
Test status
Simulation time 116263246 ps
CPU time 1.4 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:51 PM PDT 24
Peak memory 197564 kb
Host smart-cf3d802f-e911-4eda-92c2-c4d934d10afb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523613157 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2523613157
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1526478770
Short name T572
Test name
Test status
Simulation time 22004142 ps
CPU time 0.57 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:54 PM PDT 24
Peak memory 182608 kb
Host smart-5d9f3087-70eb-4b67-ac61-2ec1f0b4b432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526478770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1526478770
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.484698943
Short name T99
Test name
Test status
Simulation time 17820991 ps
CPU time 0.67 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:39:38 PM PDT 24
Peak memory 190816 kb
Host smart-1b1e372a-e402-417c-9d87-6e2fa05a494f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484698943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.484698943
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3056787459
Short name T561
Test name
Test status
Simulation time 107074872 ps
CPU time 1.95 seconds
Started May 09 12:38:39 PM PDT 24
Finished May 09 12:38:58 PM PDT 24
Peak memory 197624 kb
Host smart-8c3459eb-17b8-43cb-8ea2-f5df541ba99d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056787459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3056787459
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2515031521
Short name T108
Test name
Test status
Simulation time 1180302185 ps
CPU time 1.83 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:39:56 PM PDT 24
Peak memory 195096 kb
Host smart-cfc94d24-6a66-4705-95b3-9c2e892c8787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515031521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2515031521
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1322710065
Short name T465
Test name
Test status
Simulation time 82131943 ps
CPU time 0.71 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:39:38 PM PDT 24
Peak memory 194752 kb
Host smart-21e41049-2394-4c85-92c0-009288a36595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322710065 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1322710065
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3607924085
Short name T552
Test name
Test status
Simulation time 18464383 ps
CPU time 0.56 seconds
Started May 09 12:39:10 PM PDT 24
Finished May 09 12:39:21 PM PDT 24
Peak memory 182588 kb
Host smart-0ca0f204-4057-4984-ac47-e105947e1ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607924085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3607924085
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.778436914
Short name T515
Test name
Test status
Simulation time 14469698 ps
CPU time 0.52 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:49 PM PDT 24
Peak memory 182092 kb
Host smart-f68a55f5-825c-446b-a999-5836b7ace835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778436914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.778436914
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3653424654
Short name T560
Test name
Test status
Simulation time 68347936 ps
CPU time 0.69 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:39:30 PM PDT 24
Peak memory 193348 kb
Host smart-e56ec1b9-9801-45f9-b5a2-ba7e71e4312b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653424654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3653424654
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.4038201097
Short name T469
Test name
Test status
Simulation time 21650890 ps
CPU time 0.88 seconds
Started May 09 12:39:10 PM PDT 24
Finished May 09 12:39:21 PM PDT 24
Peak memory 196272 kb
Host smart-a5ab2f91-77ed-45b5-9efc-64d0d87a4660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038201097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.4038201097
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1093835216
Short name T578
Test name
Test status
Simulation time 167531386 ps
CPU time 1.1 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 195320 kb
Host smart-665bff94-97e2-4375-881e-4849a3690082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093835216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1093835216
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2765707036
Short name T498
Test name
Test status
Simulation time 25821207 ps
CPU time 1.17 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 197504 kb
Host smart-56ae8936-1de2-4eff-8511-294b5b9d7eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765707036 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2765707036
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2458644026
Short name T47
Test name
Test status
Simulation time 30954284 ps
CPU time 0.57 seconds
Started May 09 12:38:28 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 191936 kb
Host smart-4505b8d1-8240-4f0d-b8f6-a9056b74e783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458644026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2458644026
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3969360094
Short name T479
Test name
Test status
Simulation time 61440543 ps
CPU time 0.53 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:39:15 PM PDT 24
Peak memory 182340 kb
Host smart-390eaf06-52d0-43c6-b43c-6b0d9b80f81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969360094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3969360094
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3613522827
Short name T513
Test name
Test status
Simulation time 165977543 ps
CPU time 0.89 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:38:47 PM PDT 24
Peak memory 193672 kb
Host smart-fcd052a9-1d1c-428e-82db-efa1bde0ebc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613522827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3613522827
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.988664331
Short name T520
Test name
Test status
Simulation time 60191744 ps
CPU time 0.92 seconds
Started May 09 12:38:28 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 195796 kb
Host smart-e4100928-46fb-4178-8e90-3ad20ef39475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988664331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.988664331
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2001128474
Short name T564
Test name
Test status
Simulation time 1332205576 ps
CPU time 1.29 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:39:39 PM PDT 24
Peak memory 194392 kb
Host smart-29aba867-8c3d-45c8-927d-96d6e993437a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001128474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2001128474
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.19378095
Short name T30
Test name
Test status
Simulation time 75332767 ps
CPU time 0.87 seconds
Started May 09 12:38:45 PM PDT 24
Finished May 09 12:39:02 PM PDT 24
Peak memory 197236 kb
Host smart-02bd285a-6fb9-4e65-a85b-ee0c181389be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19378095 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.19378095
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2092281652
Short name T89
Test name
Test status
Simulation time 74224051 ps
CPU time 0.54 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:38:53 PM PDT 24
Peak memory 182452 kb
Host smart-302671a7-04df-4acd-9733-9d47467024dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092281652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2092281652
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3768079737
Short name T530
Test name
Test status
Simulation time 14560238 ps
CPU time 0.53 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:39:03 PM PDT 24
Peak memory 182228 kb
Host smart-334f7328-e38d-4ac4-b82b-e6ffd1fe622d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768079737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3768079737
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3641427474
Short name T105
Test name
Test status
Simulation time 24623953 ps
CPU time 0.71 seconds
Started May 09 12:38:34 PM PDT 24
Finished May 09 12:38:51 PM PDT 24
Peak memory 192296 kb
Host smart-ed33868a-01ce-48ac-8107-d3b9d22c7a10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641427474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3641427474
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2303864995
Short name T474
Test name
Test status
Simulation time 76066101 ps
CPU time 1.11 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:38:53 PM PDT 24
Peak memory 197636 kb
Host smart-a854bf4b-6281-4f4f-8efc-8f5793d01268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303864995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2303864995
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1610481100
Short name T542
Test name
Test status
Simulation time 351602233 ps
CPU time 1.07 seconds
Started May 09 12:38:56 PM PDT 24
Finished May 09 12:39:11 PM PDT 24
Peak memory 195264 kb
Host smart-c300a552-c7ab-4d8d-9355-09b4250fa697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610481100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1610481100
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3213351328
Short name T493
Test name
Test status
Simulation time 62262552 ps
CPU time 1.57 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 197648 kb
Host smart-b396847d-3ab1-4b3c-b010-b166e337007b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213351328 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3213351328
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1015761273
Short name T91
Test name
Test status
Simulation time 181513824 ps
CPU time 0.65 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 182748 kb
Host smart-9f629651-4c2f-484e-83ac-bd6bd625e3cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015761273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1015761273
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3797713760
Short name T468
Test name
Test status
Simulation time 40469940 ps
CPU time 0.53 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 182096 kb
Host smart-81da6379-f9d4-4b8b-b65c-55681f6ab3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797713760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3797713760
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3585709917
Short name T98
Test name
Test status
Simulation time 63926520 ps
CPU time 0.62 seconds
Started May 09 12:38:34 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 192296 kb
Host smart-01f38075-f09c-4d31-a7c6-6f369178276b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585709917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3585709917
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2189138585
Short name T573
Test name
Test status
Simulation time 757717722 ps
CPU time 2.94 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:38:56 PM PDT 24
Peak memory 197652 kb
Host smart-20c1184e-a4f7-4f78-9fac-d22670547232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189138585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2189138585
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4110023165
Short name T27
Test name
Test status
Simulation time 43187833 ps
CPU time 0.79 seconds
Started May 09 12:38:34 PM PDT 24
Finished May 09 12:38:51 PM PDT 24
Peak memory 183024 kb
Host smart-9d0d5ef1-21b7-40b2-9e68-0d3a8687e7c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110023165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4110023165
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1829669063
Short name T546
Test name
Test status
Simulation time 74511268 ps
CPU time 0.6 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:54 PM PDT 24
Peak memory 193784 kb
Host smart-0c336279-8c9b-4509-9c55-e0158cdf0373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829669063 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1829669063
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3312834593
Short name T545
Test name
Test status
Simulation time 25180498 ps
CPU time 0.57 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 182720 kb
Host smart-03bb977a-2c07-4fcf-b07e-018f9f8eabfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312834593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3312834593
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2364844012
Short name T537
Test name
Test status
Simulation time 12172890 ps
CPU time 0.55 seconds
Started May 09 12:38:31 PM PDT 24
Finished May 09 12:38:48 PM PDT 24
Peak memory 182572 kb
Host smart-b8a05f3f-4797-41fc-9db3-979f1ee65a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364844012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2364844012
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.289313670
Short name T555
Test name
Test status
Simulation time 63420005 ps
CPU time 0.76 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:38:53 PM PDT 24
Peak memory 194164 kb
Host smart-57e4d06c-ee1b-43d9-8b6a-72c678ae27dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289313670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.289313670
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2007014149
Short name T510
Test name
Test status
Simulation time 325154374 ps
CPU time 1.66 seconds
Started May 09 12:38:43 PM PDT 24
Finished May 09 12:39:01 PM PDT 24
Peak memory 197544 kb
Host smart-06f3cf65-941d-4270-bf2a-50bc8dbd26b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007014149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2007014149
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1582285650
Short name T565
Test name
Test status
Simulation time 127935054 ps
CPU time 1.11 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 194220 kb
Host smart-9d3d0b9f-b209-4a26-b0fd-261d72583a64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582285650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1582285650
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1078476950
Short name T514
Test name
Test status
Simulation time 61195216 ps
CPU time 0.83 seconds
Started May 09 12:38:46 PM PDT 24
Finished May 09 12:39:03 PM PDT 24
Peak memory 197056 kb
Host smart-dbe044c4-2611-4e32-abe9-21c737bb9eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078476950 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1078476950
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4201309397
Short name T75
Test name
Test status
Simulation time 41399453 ps
CPU time 0.56 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 182712 kb
Host smart-14f951c3-ed10-4582-b84e-a4849fd90d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201309397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4201309397
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3558039955
Short name T490
Test name
Test status
Simulation time 14238415 ps
CPU time 0.53 seconds
Started May 09 12:38:52 PM PDT 24
Finished May 09 12:39:08 PM PDT 24
Peak memory 182268 kb
Host smart-fbd12fa5-8454-44e5-ad1a-9652b6232cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558039955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3558039955
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1427560437
Short name T104
Test name
Test status
Simulation time 184041965 ps
CPU time 0.72 seconds
Started May 09 12:38:38 PM PDT 24
Finished May 09 12:38:56 PM PDT 24
Peak memory 191720 kb
Host smart-775cf045-8e9c-40ff-bd56-2d46c93c435f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427560437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1427560437
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.772968330
Short name T519
Test name
Test status
Simulation time 123907886 ps
CPU time 1.33 seconds
Started May 09 12:38:40 PM PDT 24
Finished May 09 12:38:59 PM PDT 24
Peak memory 197560 kb
Host smart-6806e176-0f75-46b9-a661-cc9e964a8569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772968330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.772968330
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.24948730
Short name T110
Test name
Test status
Simulation time 198611792 ps
CPU time 1.26 seconds
Started May 09 12:38:34 PM PDT 24
Finished May 09 12:38:51 PM PDT 24
Peak memory 195732 kb
Host smart-494492c2-6764-4d52-929d-1979c6487c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24948730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_int
g_err.24948730
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.840333174
Short name T535
Test name
Test status
Simulation time 23216090 ps
CPU time 1 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 197336 kb
Host smart-ec423430-b50b-4400-bf09-1f8329faaae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840333174 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.840333174
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.75503814
Short name T551
Test name
Test status
Simulation time 41768175 ps
CPU time 0.57 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:54 PM PDT 24
Peak memory 182712 kb
Host smart-2d76edbd-a62e-4fbd-a023-099e93c3f9da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75503814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.75503814
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2227547305
Short name T502
Test name
Test status
Simulation time 14568631 ps
CPU time 0.52 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 182096 kb
Host smart-7465f7f4-2793-48ac-bd68-0b46ab447754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227547305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2227547305
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2893490259
Short name T577
Test name
Test status
Simulation time 26971932 ps
CPU time 0.76 seconds
Started May 09 12:38:43 PM PDT 24
Finished May 09 12:39:01 PM PDT 24
Peak memory 191684 kb
Host smart-8caf4cb7-ccf2-4d2f-a63c-36c75806f75d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893490259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2893490259
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3224913903
Short name T467
Test name
Test status
Simulation time 230433399 ps
CPU time 2.16 seconds
Started May 09 12:38:34 PM PDT 24
Finished May 09 12:38:53 PM PDT 24
Peak memory 197640 kb
Host smart-6a0eea38-66a7-49a0-b040-e6e925fea627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224913903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3224913903
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.410033281
Short name T538
Test name
Test status
Simulation time 578882792 ps
CPU time 1.08 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 195080 kb
Host smart-b94a3af3-ae27-4a70-ba56-26310120e4f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410033281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.410033281
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2855236268
Short name T570
Test name
Test status
Simulation time 80564633 ps
CPU time 0.65 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:39:07 PM PDT 24
Peak memory 194564 kb
Host smart-a52aad63-9d51-4344-92d1-62a2f3de621e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855236268 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2855236268
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1420913780
Short name T45
Test name
Test status
Simulation time 53949734 ps
CPU time 0.56 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 182716 kb
Host smart-e3ef5c7b-ec8a-43b8-85c8-b4389f359a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420913780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1420913780
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3293731309
Short name T495
Test name
Test status
Simulation time 34216434 ps
CPU time 0.52 seconds
Started May 09 12:38:38 PM PDT 24
Finished May 09 12:39:00 PM PDT 24
Peak memory 182092 kb
Host smart-3ad2500e-babf-4fff-9712-97f8ac12875f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293731309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3293731309
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2052349660
Short name T540
Test name
Test status
Simulation time 49445182 ps
CPU time 0.78 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 193400 kb
Host smart-8c5d1c37-124e-4324-81eb-c15e74586ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052349660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2052349660
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3158266163
Short name T509
Test name
Test status
Simulation time 368904679 ps
CPU time 1.64 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:56 PM PDT 24
Peak memory 197432 kb
Host smart-5c4661f5-c3c4-4d7b-b63d-0b4e37448b84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158266163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3158266163
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1263407611
Short name T556
Test name
Test status
Simulation time 598544598 ps
CPU time 1.34 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 195396 kb
Host smart-48728f11-cc03-41ee-8226-c8ca4f22210e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263407611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1263407611
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3987547741
Short name T523
Test name
Test status
Simulation time 90461036 ps
CPU time 0.8 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 196380 kb
Host smart-c10ba6fb-dfe6-42df-94b4-18713b660217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987547741 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3987547741
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1698660396
Short name T534
Test name
Test status
Simulation time 63956301 ps
CPU time 0.61 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 182716 kb
Host smart-c3322d7c-4464-44b4-9a6d-3bf088af186f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698660396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1698660396
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3569673167
Short name T470
Test name
Test status
Simulation time 30112754 ps
CPU time 0.6 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:54 PM PDT 24
Peak memory 182572 kb
Host smart-b42bde66-7f0f-40e7-90d9-bee5ccad10d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569673167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3569673167
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.270748098
Short name T101
Test name
Test status
Simulation time 79707602 ps
CPU time 0.82 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 193508 kb
Host smart-780b339c-d020-4800-9b71-c61d61487d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270748098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.270748098
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3734085828
Short name T461
Test name
Test status
Simulation time 185320518 ps
CPU time 1.12 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 197396 kb
Host smart-1b7b47c1-3ca5-4aeb-bca7-5c3ead544ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734085828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3734085828
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1752217545
Short name T558
Test name
Test status
Simulation time 76529059 ps
CPU time 0.8 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:38:47 PM PDT 24
Peak memory 183240 kb
Host smart-0ef43821-1229-4001-9261-95fa9867e930
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752217545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1752217545
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4164495594
Short name T480
Test name
Test status
Simulation time 62869409 ps
CPU time 0.58 seconds
Started May 09 12:38:26 PM PDT 24
Finished May 09 12:38:43 PM PDT 24
Peak memory 182600 kb
Host smart-4cbfbf89-01d0-4a1f-858a-29e50c2018a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164495594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4164495594
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1900414928
Short name T517
Test name
Test status
Simulation time 38913456 ps
CPU time 1.4 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 191024 kb
Host smart-4f0e4836-c2ad-4165-9699-1288837c5af2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900414928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1900414928
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3740961742
Short name T77
Test name
Test status
Simulation time 52285569 ps
CPU time 0.53 seconds
Started May 09 12:38:18 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 182724 kb
Host smart-edad6e05-a21c-41d1-bd04-d636ed0ff63b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740961742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3740961742
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1721990094
Short name T464
Test name
Test status
Simulation time 262052775 ps
CPU time 1.01 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:38:47 PM PDT 24
Peak memory 197412 kb
Host smart-be5eaf90-3c61-44c1-aab1-ee4cd686b3ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721990094 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1721990094
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1037192164
Short name T526
Test name
Test status
Simulation time 40572805 ps
CPU time 0.64 seconds
Started May 09 12:38:23 PM PDT 24
Finished May 09 12:38:40 PM PDT 24
Peak memory 182724 kb
Host smart-0e013cb7-28e0-40b7-b7ea-a1fe26a9013b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037192164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1037192164
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1433040609
Short name T571
Test name
Test status
Simulation time 22163027 ps
CPU time 0.52 seconds
Started May 09 12:38:29 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 182156 kb
Host smart-e30ff62e-4ce8-451d-a3b5-dedd63f5c486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433040609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1433040609
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3317761523
Short name T102
Test name
Test status
Simulation time 44374995 ps
CPU time 0.61 seconds
Started May 09 12:38:27 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 192076 kb
Host smart-efd5e20f-e72a-40ca-9e8d-0045c1f6c0ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317761523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3317761523
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2301316090
Short name T459
Test name
Test status
Simulation time 51806676 ps
CPU time 1.42 seconds
Started May 09 12:38:15 PM PDT 24
Finished May 09 12:38:35 PM PDT 24
Peak memory 197568 kb
Host smart-f3fbc23d-5304-4ca4-ad4c-7472ef9fc818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301316090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2301316090
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2518129323
Short name T29
Test name
Test status
Simulation time 126035061 ps
CPU time 1.4 seconds
Started May 09 12:38:34 PM PDT 24
Finished May 09 12:38:52 PM PDT 24
Peak memory 195224 kb
Host smart-c599d368-82bb-4988-bd94-70cbad82cae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518129323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2518129323
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4255853651
Short name T463
Test name
Test status
Simulation time 13184900 ps
CPU time 0.51 seconds
Started May 09 12:38:31 PM PDT 24
Finished May 09 12:38:48 PM PDT 24
Peak memory 182092 kb
Host smart-1bac1a35-71ea-4460-a130-c828c2c26a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255853651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4255853651
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1021483478
Short name T489
Test name
Test status
Simulation time 129641669 ps
CPU time 0.56 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 182692 kb
Host smart-1c09e561-e9f0-41c7-9596-c16be6e12a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021483478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1021483478
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2534091121
Short name T525
Test name
Test status
Simulation time 38181474 ps
CPU time 0.51 seconds
Started May 09 12:38:52 PM PDT 24
Finished May 09 12:39:08 PM PDT 24
Peak memory 182104 kb
Host smart-8914df1c-3c8c-4474-a155-22a7d8b62917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534091121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2534091121
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1820013040
Short name T452
Test name
Test status
Simulation time 10741857 ps
CPU time 0.53 seconds
Started May 09 12:38:29 PM PDT 24
Finished May 09 12:38:46 PM PDT 24
Peak memory 182076 kb
Host smart-9d0d0fc2-31e3-49a1-85ba-83f6328980ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820013040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1820013040
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.76511229
Short name T481
Test name
Test status
Simulation time 18906585 ps
CPU time 0.52 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 182096 kb
Host smart-83299dfd-73e0-4f00-a08b-fb5ba5823bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76511229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.76511229
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1683690691
Short name T460
Test name
Test status
Simulation time 18033130 ps
CPU time 0.53 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 181860 kb
Host smart-852a9f0e-ee94-48f2-9dd8-ac667fd1c87e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683690691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1683690691
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2582117287
Short name T557
Test name
Test status
Simulation time 25381250 ps
CPU time 0.54 seconds
Started May 09 12:38:57 PM PDT 24
Finished May 09 12:39:12 PM PDT 24
Peak memory 182624 kb
Host smart-df7488ca-8d09-405c-a14c-ae845e2282bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582117287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2582117287
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2920539667
Short name T533
Test name
Test status
Simulation time 12130467 ps
CPU time 0.52 seconds
Started May 09 12:38:46 PM PDT 24
Finished May 09 12:39:02 PM PDT 24
Peak memory 182076 kb
Host smart-f065dd83-de83-4723-81a9-99a46535dd25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920539667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2920539667
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.344591736
Short name T550
Test name
Test status
Simulation time 28586513 ps
CPU time 0.52 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:39:07 PM PDT 24
Peak memory 182056 kb
Host smart-f1d1af59-c9c1-49fc-8dcc-93327949d63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344591736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.344591736
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1347362179
Short name T541
Test name
Test status
Simulation time 14536133 ps
CPU time 0.56 seconds
Started May 09 12:38:53 PM PDT 24
Finished May 09 12:39:17 PM PDT 24
Peak memory 182716 kb
Host smart-e0942c9c-ca0d-4378-a58a-7cb0f5a0ba98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347362179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1347362179
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1417861444
Short name T93
Test name
Test status
Simulation time 30032466 ps
CPU time 0.71 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:38:47 PM PDT 24
Peak memory 191952 kb
Host smart-a6d55d97-bbf9-4f2c-a534-e95f25068bf7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417861444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1417861444
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2004101755
Short name T518
Test name
Test status
Simulation time 282550228 ps
CPU time 1.56 seconds
Started May 09 12:38:25 PM PDT 24
Finished May 09 12:38:43 PM PDT 24
Peak memory 191048 kb
Host smart-917b668a-61be-4344-b543-50d76364d9a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004101755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2004101755
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1389226102
Short name T499
Test name
Test status
Simulation time 52579713 ps
CPU time 0.55 seconds
Started May 09 12:38:18 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 191960 kb
Host smart-f366a03f-d027-4a1f-b2f3-448247e80b54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389226102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1389226102
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2476618493
Short name T466
Test name
Test status
Simulation time 51343854 ps
CPU time 0.72 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 195600 kb
Host smart-50bc2e71-a382-4368-8a9d-d40382382e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476618493 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2476618493
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1781958255
Short name T92
Test name
Test status
Simulation time 75242840 ps
CPU time 0.59 seconds
Started May 09 12:38:13 PM PDT 24
Finished May 09 12:38:32 PM PDT 24
Peak memory 183012 kb
Host smart-642147da-9d58-43e1-9c25-13689b253a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781958255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1781958255
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1464879968
Short name T455
Test name
Test status
Simulation time 27151871 ps
CPU time 0.55 seconds
Started May 09 12:38:23 PM PDT 24
Finished May 09 12:38:40 PM PDT 24
Peak memory 182896 kb
Host smart-557e72b3-36db-42ea-9e15-50d2ff536f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464879968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1464879968
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.644850969
Short name T575
Test name
Test status
Simulation time 24447836 ps
CPU time 0.66 seconds
Started May 09 12:38:18 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 192088 kb
Host smart-38fdc449-0272-4953-8a4e-1e3fec954af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644850969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.644850969
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.998445043
Short name T549
Test name
Test status
Simulation time 814238451 ps
CPU time 1.64 seconds
Started May 09 12:38:23 PM PDT 24
Finished May 09 12:38:41 PM PDT 24
Peak memory 197628 kb
Host smart-0b75e92c-ac2e-4195-b9e3-c88980f8adc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998445043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.998445043
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.844636237
Short name T109
Test name
Test status
Simulation time 363074944 ps
CPU time 1.02 seconds
Started May 09 12:39:08 PM PDT 24
Finished May 09 12:39:20 PM PDT 24
Peak memory 194872 kb
Host smart-80a982db-77b4-4f5d-ac15-3511836deaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844636237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.844636237
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.500683494
Short name T553
Test name
Test status
Simulation time 38147700 ps
CPU time 0.55 seconds
Started May 09 12:38:43 PM PDT 24
Finished May 09 12:39:00 PM PDT 24
Peak memory 182632 kb
Host smart-2b4ad77e-c6f7-4ee2-8486-d6b06f42f67e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500683494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.500683494
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.245622955
Short name T471
Test name
Test status
Simulation time 23471438 ps
CPU time 0.53 seconds
Started May 09 12:38:49 PM PDT 24
Finished May 09 12:39:05 PM PDT 24
Peak memory 182132 kb
Host smart-6640260c-f127-4ae6-bded-20cd3ae70c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245622955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.245622955
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4111123436
Short name T566
Test name
Test status
Simulation time 19398165 ps
CPU time 0.5 seconds
Started May 09 12:38:55 PM PDT 24
Finished May 09 12:39:10 PM PDT 24
Peak memory 182032 kb
Host smart-ce85cae4-97bf-4965-a3cb-2add541ae85f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111123436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4111123436
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1011390857
Short name T511
Test name
Test status
Simulation time 20985821 ps
CPU time 0.54 seconds
Started May 09 12:38:48 PM PDT 24
Finished May 09 12:39:04 PM PDT 24
Peak memory 182604 kb
Host smart-54e22edf-f6fd-4e8a-b494-fd9451477c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011390857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1011390857
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.203410913
Short name T458
Test name
Test status
Simulation time 35172951 ps
CPU time 0.52 seconds
Started May 09 12:38:55 PM PDT 24
Finished May 09 12:39:11 PM PDT 24
Peak memory 182000 kb
Host smart-648c183c-f3ac-4a92-8445-2a7e22cdd328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203410913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.203410913
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.812839585
Short name T497
Test name
Test status
Simulation time 12009792 ps
CPU time 0.52 seconds
Started May 09 12:38:58 PM PDT 24
Finished May 09 12:39:12 PM PDT 24
Peak memory 182096 kb
Host smart-e512cc8f-ddb2-4d52-8236-6313a6f7b974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812839585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.812839585
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.179093536
Short name T477
Test name
Test status
Simulation time 135290179 ps
CPU time 0.56 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:39:07 PM PDT 24
Peak memory 182744 kb
Host smart-6bb33229-a583-4571-8de6-12b827002a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179093536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.179093536
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3364275225
Short name T472
Test name
Test status
Simulation time 14053961 ps
CPU time 0.55 seconds
Started May 09 12:38:58 PM PDT 24
Finished May 09 12:39:12 PM PDT 24
Peak memory 182624 kb
Host smart-7d1b1ac0-cdb4-4096-8ecc-fa88c71b21b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364275225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3364275225
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1680655276
Short name T456
Test name
Test status
Simulation time 31235988 ps
CPU time 0.54 seconds
Started May 09 12:38:48 PM PDT 24
Finished May 09 12:39:04 PM PDT 24
Peak memory 182572 kb
Host smart-8e9e8002-e53e-4fb2-8e2b-1e6f842eea3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680655276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1680655276
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2995971201
Short name T478
Test name
Test status
Simulation time 13962653 ps
CPU time 0.55 seconds
Started May 09 12:38:53 PM PDT 24
Finished May 09 12:39:08 PM PDT 24
Peak memory 182308 kb
Host smart-71fb634b-0246-4c38-b82e-4887c2079eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995971201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2995971201
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3483163482
Short name T559
Test name
Test status
Simulation time 36041170 ps
CPU time 0.76 seconds
Started May 09 12:38:27 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 192540 kb
Host smart-165ea02a-dc33-494b-a727-bd8824d0c7a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483163482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3483163482
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2975468499
Short name T79
Test name
Test status
Simulation time 267899770 ps
CPU time 1.53 seconds
Started May 09 12:38:27 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 191004 kb
Host smart-19117572-d995-4d78-b97f-ea550004230d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975468499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2975468499
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.782922227
Short name T496
Test name
Test status
Simulation time 23285929 ps
CPU time 0.54 seconds
Started May 09 12:38:19 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 182712 kb
Host smart-e84bba65-a149-4796-80ba-cd3c0b744593
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782922227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.782922227
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4212104860
Short name T58
Test name
Test status
Simulation time 51847717 ps
CPU time 0.81 seconds
Started May 09 12:38:28 PM PDT 24
Finished May 09 12:38:46 PM PDT 24
Peak memory 197284 kb
Host smart-8a037575-2acd-47ab-83f9-d743f3acb5c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212104860 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4212104860
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2838008471
Short name T531
Test name
Test status
Simulation time 65917655 ps
CPU time 0.58 seconds
Started May 09 12:39:02 PM PDT 24
Finished May 09 12:39:15 PM PDT 24
Peak memory 191672 kb
Host smart-c86b4f4b-1338-4782-8023-65e5bfbbf1b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838008471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2838008471
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.691159347
Short name T462
Test name
Test status
Simulation time 33405885 ps
CPU time 0.57 seconds
Started May 09 12:38:37 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 182000 kb
Host smart-a0897b6b-ac96-4ddd-bf5e-f27a38efe31a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691159347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.691159347
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3125060766
Short name T78
Test name
Test status
Simulation time 21834031 ps
CPU time 0.61 seconds
Started May 09 12:38:26 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 191440 kb
Host smart-980a518e-f81f-41d3-a38d-676c8d630678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125060766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3125060766
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3879584178
Short name T484
Test name
Test status
Simulation time 88778580 ps
CPU time 1.37 seconds
Started May 09 12:38:27 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 197472 kb
Host smart-08aa7fa0-8624-4587-aa23-81358a307547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879584178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3879584178
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1647253811
Short name T487
Test name
Test status
Simulation time 244243100 ps
CPU time 1.02 seconds
Started May 09 12:38:24 PM PDT 24
Finished May 09 12:38:42 PM PDT 24
Peak memory 183256 kb
Host smart-15eb1a93-c53f-469b-84e2-1fc28dcb0474
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647253811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1647253811
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.737220809
Short name T475
Test name
Test status
Simulation time 20110615 ps
CPU time 0.57 seconds
Started May 09 12:38:48 PM PDT 24
Finished May 09 12:39:04 PM PDT 24
Peak memory 182640 kb
Host smart-3c847904-aab4-4f70-ba69-896a0282318d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737220809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.737220809
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3106637395
Short name T547
Test name
Test status
Simulation time 13377923 ps
CPU time 0.51 seconds
Started May 09 12:38:54 PM PDT 24
Finished May 09 12:39:10 PM PDT 24
Peak memory 182024 kb
Host smart-8b32364d-20a6-4b9a-8152-10743df64d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106637395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3106637395
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3874888312
Short name T454
Test name
Test status
Simulation time 17884669 ps
CPU time 0.54 seconds
Started May 09 12:38:54 PM PDT 24
Finished May 09 12:39:09 PM PDT 24
Peak memory 182692 kb
Host smart-19535f86-0feb-4eda-bbb4-6a94e1b23885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874888312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3874888312
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4039813455
Short name T491
Test name
Test status
Simulation time 13130993 ps
CPU time 0.53 seconds
Started May 09 12:38:58 PM PDT 24
Finished May 09 12:39:13 PM PDT 24
Peak memory 181988 kb
Host smart-caab7824-8ffe-4d6f-b7e8-9f1e249d16e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039813455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4039813455
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4137644151
Short name T492
Test name
Test status
Simulation time 17915755 ps
CPU time 0.56 seconds
Started May 09 12:38:48 PM PDT 24
Finished May 09 12:39:04 PM PDT 24
Peak memory 182556 kb
Host smart-1a9cb2e2-7ca8-4fe6-9e1f-85b6801e1215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137644151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4137644151
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2163896748
Short name T544
Test name
Test status
Simulation time 11912960 ps
CPU time 0.54 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:39:07 PM PDT 24
Peak memory 182652 kb
Host smart-93911718-5deb-4589-9f7c-22036498dfb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163896748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2163896748
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2845897186
Short name T529
Test name
Test status
Simulation time 19551867 ps
CPU time 0.6 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:39:07 PM PDT 24
Peak memory 182688 kb
Host smart-fbd7824d-e88b-48d7-8cb7-0c54091e7008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845897186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2845897186
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4242728044
Short name T473
Test name
Test status
Simulation time 11226452 ps
CPU time 0.53 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:39:03 PM PDT 24
Peak memory 182684 kb
Host smart-d0d14b26-57fa-4907-813c-eef0d7e4ab49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242728044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4242728044
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2518546779
Short name T486
Test name
Test status
Simulation time 49474706 ps
CPU time 0.56 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:39:03 PM PDT 24
Peak memory 182640 kb
Host smart-36f6c7c7-e166-4c8e-96da-3b1c27c43752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518546779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2518546779
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1663683065
Short name T512
Test name
Test status
Simulation time 57028179 ps
CPU time 0.53 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:39:15 PM PDT 24
Peak memory 182652 kb
Host smart-64e26657-6c0b-4c35-8a14-d8518f36d63d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663683065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1663683065
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2374070111
Short name T44
Test name
Test status
Simulation time 33913945 ps
CPU time 0.82 seconds
Started May 09 12:38:19 PM PDT 24
Finished May 09 12:38:37 PM PDT 24
Peak memory 196808 kb
Host smart-fbd55e79-600b-4f6f-b455-e5190d974367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374070111 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2374070111
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3953158118
Short name T539
Test name
Test status
Simulation time 40625645 ps
CPU time 0.53 seconds
Started May 09 12:39:10 PM PDT 24
Finished May 09 12:39:21 PM PDT 24
Peak memory 182592 kb
Host smart-a1e6351b-1129-4fdc-a2c7-f73647035b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953158118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3953158118
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1369908995
Short name T567
Test name
Test status
Simulation time 14638914 ps
CPU time 0.53 seconds
Started May 09 12:38:28 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 182296 kb
Host smart-b0cba8b7-80c2-4699-a44f-ff6cfba992c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369908995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1369908995
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.522119191
Short name T100
Test name
Test status
Simulation time 31351554 ps
CPU time 0.71 seconds
Started May 09 12:38:18 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 191732 kb
Host smart-b40c9bad-3de6-4763-bc47-389d24dfcb06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522119191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.522119191
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4210348557
Short name T576
Test name
Test status
Simulation time 70025605 ps
CPU time 1.77 seconds
Started May 09 12:38:20 PM PDT 24
Finished May 09 12:38:39 PM PDT 24
Peak memory 197616 kb
Host smart-f63d9b80-1c76-4d30-9a8f-d92a1bb69593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210348557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4210348557
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.605793805
Short name T522
Test name
Test status
Simulation time 49338233 ps
CPU time 0.79 seconds
Started May 09 12:38:22 PM PDT 24
Finished May 09 12:38:39 PM PDT 24
Peak memory 192596 kb
Host smart-ff465a33-3e9f-41d4-993b-f98124f44708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605793805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.605793805
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1191091251
Short name T483
Test name
Test status
Simulation time 44508992 ps
CPU time 0.76 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 195760 kb
Host smart-8ed883d7-c406-4f04-970d-4cc97e48c800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191091251 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1191091251
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1097921464
Short name T96
Test name
Test status
Simulation time 12730351 ps
CPU time 0.56 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 182588 kb
Host smart-93bf9f28-aa6b-4dfa-b876-731a24a79791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097921464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1097921464
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3788634774
Short name T453
Test name
Test status
Simulation time 49628407 ps
CPU time 0.57 seconds
Started May 09 12:38:23 PM PDT 24
Finished May 09 12:38:40 PM PDT 24
Peak memory 182576 kb
Host smart-326ba3b9-d110-4db4-9cf2-22900c05232c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788634774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3788634774
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2745537101
Short name T501
Test name
Test status
Simulation time 182442079 ps
CPU time 0.83 seconds
Started May 09 12:38:28 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 191740 kb
Host smart-4c761bb4-bc0a-4d63-b080-554361d9d4a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745537101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2745537101
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1739342225
Short name T532
Test name
Test status
Simulation time 119472756 ps
CPU time 1.18 seconds
Started May 09 12:38:26 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 196960 kb
Host smart-bcbe0c78-e439-490e-a054-ff744d34e04a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739342225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1739342225
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3273127629
Short name T48
Test name
Test status
Simulation time 287511641 ps
CPU time 1.12 seconds
Started May 09 12:38:34 PM PDT 24
Finished May 09 12:38:52 PM PDT 24
Peak memory 183216 kb
Host smart-54feee93-0112-4a17-bd15-47cf581cdbbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273127629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3273127629
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1478697456
Short name T457
Test name
Test status
Simulation time 148326347 ps
CPU time 0.96 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 197368 kb
Host smart-f6865d7b-e242-4de6-b1fb-a6a00a750280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478697456 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1478697456
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3872633136
Short name T521
Test name
Test status
Simulation time 38472734 ps
CPU time 0.57 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 182724 kb
Host smart-8e1f54de-139c-4fe8-b183-c5e320aa7a17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872633136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3872633136
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1153473454
Short name T506
Test name
Test status
Simulation time 58511557 ps
CPU time 0.56 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:39:38 PM PDT 24
Peak memory 182008 kb
Host smart-0489c944-6b7b-486c-8bd7-887c10f7dc56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153473454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1153473454
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.967367646
Short name T97
Test name
Test status
Simulation time 28483283 ps
CPU time 0.73 seconds
Started May 09 12:38:27 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 193664 kb
Host smart-b5358d23-2bb7-473b-8c6e-61cb6811dcde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967367646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.967367646
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2389678607
Short name T482
Test name
Test status
Simulation time 116268651 ps
CPU time 2.83 seconds
Started May 09 12:38:21 PM PDT 24
Finished May 09 12:38:41 PM PDT 24
Peak memory 197620 kb
Host smart-74c8177f-28c2-4af4-9598-4352a973f06f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389678607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2389678607
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3238653602
Short name T516
Test name
Test status
Simulation time 123266514 ps
CPU time 0.83 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:38:47 PM PDT 24
Peak memory 193796 kb
Host smart-3a821307-a97e-488f-8585-494f076473d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238653602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3238653602
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.997733981
Short name T504
Test name
Test status
Simulation time 50821066 ps
CPU time 0.71 seconds
Started May 09 12:38:31 PM PDT 24
Finished May 09 12:38:49 PM PDT 24
Peak memory 195140 kb
Host smart-ddf0ec42-5d2d-4ff8-b7cc-7d8ff529a74d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997733981 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.997733981
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2382254880
Short name T563
Test name
Test status
Simulation time 24298257 ps
CPU time 0.55 seconds
Started May 09 12:39:13 PM PDT 24
Finished May 09 12:39:23 PM PDT 24
Peak memory 182564 kb
Host smart-d9f3d2c9-66b3-43e8-b013-0869263c6a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382254880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2382254880
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.532315390
Short name T507
Test name
Test status
Simulation time 14085886 ps
CPU time 0.56 seconds
Started May 09 12:38:32 PM PDT 24
Finished May 09 12:38:49 PM PDT 24
Peak memory 182536 kb
Host smart-0d91b9be-0508-4d43-bc57-0d41606c7f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532315390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.532315390
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1605260678
Short name T528
Test name
Test status
Simulation time 15737289 ps
CPU time 0.62 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:39:38 PM PDT 24
Peak memory 190268 kb
Host smart-2253d4c0-a5d2-48c7-9d9f-13b270e2f555
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605260678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1605260678
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3681020739
Short name T485
Test name
Test status
Simulation time 343317352 ps
CPU time 2.43 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:56 PM PDT 24
Peak memory 197588 kb
Host smart-047f8393-6228-4bb0-b39a-99231f7a7238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681020739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3681020739
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3752738131
Short name T562
Test name
Test status
Simulation time 84363241 ps
CPU time 1.06 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:39:57 PM PDT 24
Peak memory 195060 kb
Host smart-ff484571-952e-4419-bbf9-bfd6b5c5f26b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752738131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3752738131
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1508952121
Short name T543
Test name
Test status
Simulation time 167651569 ps
CPU time 0.95 seconds
Started May 09 12:38:24 PM PDT 24
Finished May 09 12:38:41 PM PDT 24
Peak memory 196672 kb
Host smart-54bb635b-9d9d-45cc-a87b-a5d53dfc5eb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508952121 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1508952121
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2101440971
Short name T94
Test name
Test status
Simulation time 30588513 ps
CPU time 0.56 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:38:50 PM PDT 24
Peak memory 182744 kb
Host smart-dfb80700-9d63-470c-9b22-c61d60102a20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101440971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2101440971
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1094052833
Short name T569
Test name
Test status
Simulation time 44235858 ps
CPU time 0.55 seconds
Started May 09 12:38:28 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 182648 kb
Host smart-1b05e54c-998d-4017-b31f-68aa62e2d706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094052833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1094052833
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.25984631
Short name T536
Test name
Test status
Simulation time 47121107 ps
CPU time 0.65 seconds
Started May 09 12:38:28 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 191984 kb
Host smart-e0bab88c-22a7-42de-93ea-a7700372ee4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25984631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_time
r_same_csr_outstanding.25984631
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2754076980
Short name T500
Test name
Test status
Simulation time 260779621 ps
CPU time 2.79 seconds
Started May 09 12:38:31 PM PDT 24
Finished May 09 12:38:51 PM PDT 24
Peak memory 197612 kb
Host smart-1941c081-eb44-4803-8d0e-a479ee0ed48c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754076980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2754076980
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3877394456
Short name T508
Test name
Test status
Simulation time 112691289 ps
CPU time 1.34 seconds
Started May 09 12:38:36 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 195488 kb
Host smart-89324e80-c2ad-4b2a-8b55-e7fdf0520201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877394456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3877394456
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2793746343
Short name T397
Test name
Test status
Simulation time 61168297408 ps
CPU time 94.06 seconds
Started May 09 12:38:50 PM PDT 24
Finished May 09 12:40:40 PM PDT 24
Peak memory 183032 kb
Host smart-9049ddd9-8bfa-4057-9e5e-a29ab141ab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793746343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2793746343
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.864583020
Short name T325
Test name
Test status
Simulation time 120164393650 ps
CPU time 63.61 seconds
Started May 09 12:38:54 PM PDT 24
Finished May 09 12:40:12 PM PDT 24
Peak memory 191152 kb
Host smart-1ed1a264-9afb-40f1-bd65-6dcbabd1137c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864583020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.864583020
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3361885232
Short name T72
Test name
Test status
Simulation time 229299126620 ps
CPU time 344.32 seconds
Started May 09 12:38:50 PM PDT 24
Finished May 09 12:44:50 PM PDT 24
Peak memory 182616 kb
Host smart-d49d48fb-7b36-488d-a87e-c63abb055026
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361885232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3361885232
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.4170209851
Short name T405
Test name
Test status
Simulation time 26742455765 ps
CPU time 39.76 seconds
Started May 09 12:38:56 PM PDT 24
Finished May 09 12:39:51 PM PDT 24
Peak memory 183032 kb
Host smart-c242bae9-403d-4203-bd25-f3561d16baae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170209851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.4170209851
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1379233177
Short name T413
Test name
Test status
Simulation time 31615848818 ps
CPU time 177.31 seconds
Started May 09 12:38:46 PM PDT 24
Finished May 09 12:42:00 PM PDT 24
Peak memory 182968 kb
Host smart-7c3d156c-389c-4b57-a79d-7bece55d469e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379233177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1379233177
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1853401796
Short name T335
Test name
Test status
Simulation time 679250156762 ps
CPU time 78.09 seconds
Started May 09 12:38:57 PM PDT 24
Finished May 09 12:40:29 PM PDT 24
Peak memory 191244 kb
Host smart-6fc69445-e6a3-4454-abee-e602680a0801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853401796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1853401796
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.41516177
Short name T14
Test name
Test status
Simulation time 232882865 ps
CPU time 1.08 seconds
Started May 09 12:38:55 PM PDT 24
Finished May 09 12:39:10 PM PDT 24
Peak memory 214592 kb
Host smart-eaf3f3a3-9f4d-4258-9486-461c1746965f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41516177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.41516177
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3551158469
Short name T366
Test name
Test status
Simulation time 83550373041 ps
CPU time 64.2 seconds
Started May 09 12:39:03 PM PDT 24
Finished May 09 12:40:20 PM PDT 24
Peak memory 183000 kb
Host smart-f0eea1df-f709-4a0d-a5cc-503099781a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551158469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3551158469
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1181213210
Short name T111
Test name
Test status
Simulation time 499613815855 ps
CPU time 478.31 seconds
Started May 09 12:38:56 PM PDT 24
Finished May 09 12:47:09 PM PDT 24
Peak memory 182960 kb
Host smart-afa126cb-0ecb-4060-bf81-a907b8914242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181213210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1181213210
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4068264676
Short name T363
Test name
Test status
Simulation time 176011602 ps
CPU time 0.57 seconds
Started May 09 12:39:17 PM PDT 24
Finished May 09 12:39:26 PM PDT 24
Peak memory 182852 kb
Host smart-cd36bd71-0536-4527-bb2b-be2b30fc731d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068264676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4068264676
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2104339374
Short name T340
Test name
Test status
Simulation time 19571764889 ps
CPU time 8.22 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:39:44 PM PDT 24
Peak memory 182964 kb
Host smart-8ac4e2bd-6996-40dc-8357-15354b26ef64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104339374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2104339374
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2484529352
Short name T222
Test name
Test status
Simulation time 4588917100 ps
CPU time 3.58 seconds
Started May 09 12:39:43 PM PDT 24
Finished May 09 12:39:53 PM PDT 24
Peak memory 182996 kb
Host smart-6115e728-69be-4fe1-a383-e434c9b2c9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484529352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2484529352
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2750494797
Short name T433
Test name
Test status
Simulation time 62528514467 ps
CPU time 22.22 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:40:19 PM PDT 24
Peak memory 183036 kb
Host smart-e9375ba4-ea22-4343-a0a2-4f72a4d62010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750494797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2750494797
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2919523613
Short name T333
Test name
Test status
Simulation time 118787732801 ps
CPU time 525.05 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:48:24 PM PDT 24
Peak memory 191208 kb
Host smart-b5d057aa-45b5-4864-9a03-c05867171a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919523613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2919523613
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2911846011
Short name T426
Test name
Test status
Simulation time 47637292565 ps
CPU time 73.9 seconds
Started May 09 12:39:42 PM PDT 24
Finished May 09 12:41:03 PM PDT 24
Peak memory 182896 kb
Host smart-79faf0ea-1c98-4ab7-b220-81f8030f5857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911846011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2911846011
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3276497898
Short name T352
Test name
Test status
Simulation time 38366075176 ps
CPU time 19.04 seconds
Started May 09 12:39:04 PM PDT 24
Finished May 09 12:39:36 PM PDT 24
Peak memory 182988 kb
Host smart-4a6a953d-e51f-466d-832c-f92ce2f54563
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276497898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3276497898
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.325163533
Short name T422
Test name
Test status
Simulation time 375828785347 ps
CPU time 146.92 seconds
Started May 09 12:39:00 PM PDT 24
Finished May 09 12:41:41 PM PDT 24
Peak memory 183024 kb
Host smart-3ff23fcb-37cf-4fd8-b093-84ca8586f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325163533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.325163533
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3356557876
Short name T341
Test name
Test status
Simulation time 16185354357 ps
CPU time 14.78 seconds
Started May 09 12:39:04 PM PDT 24
Finished May 09 12:39:32 PM PDT 24
Peak memory 191256 kb
Host smart-fa6c5dfe-fbf4-42e2-96c1-ef73cea6ff5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356557876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3356557876
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1886193295
Short name T372
Test name
Test status
Simulation time 121261792 ps
CPU time 0.56 seconds
Started May 09 12:38:57 PM PDT 24
Finished May 09 12:39:12 PM PDT 24
Peak memory 183088 kb
Host smart-b794cf23-ddaa-4e09-a796-6531d20ebeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886193295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1886193295
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2053517525
Short name T312
Test name
Test status
Simulation time 236518750385 ps
CPU time 610.78 seconds
Started May 09 12:39:00 PM PDT 24
Finished May 09 12:49:24 PM PDT 24
Peak memory 191180 kb
Host smart-b52a4a97-6a78-4ec6-babe-d0b15a813ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053517525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2053517525
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/112.rv_timer_random.1731270754
Short name T56
Test name
Test status
Simulation time 98809080887 ps
CPU time 79.85 seconds
Started May 09 12:39:35 PM PDT 24
Finished May 09 12:41:03 PM PDT 24
Peak memory 191236 kb
Host smart-4c78071a-ac24-4468-9690-5e69d4b8a94a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731270754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1731270754
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.73133120
Short name T328
Test name
Test status
Simulation time 17841436546 ps
CPU time 114.73 seconds
Started May 09 12:39:43 PM PDT 24
Finished May 09 12:41:45 PM PDT 24
Peak memory 192264 kb
Host smart-42645551-d7c5-4a23-9a9b-3b38dd99f1e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73133120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.73133120
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1102870907
Short name T424
Test name
Test status
Simulation time 191149551726 ps
CPU time 1825.45 seconds
Started May 09 12:39:51 PM PDT 24
Finished May 09 01:10:29 PM PDT 24
Peak memory 191208 kb
Host smart-79400469-8dc5-49e4-8c1c-0f5c86ce351e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102870907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1102870907
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.372986107
Short name T24
Test name
Test status
Simulation time 67315293326 ps
CPU time 1073.25 seconds
Started May 09 12:39:39 PM PDT 24
Finished May 09 12:57:40 PM PDT 24
Peak memory 191256 kb
Host smart-eb46e574-ce73-45c5-8498-2c531cbe8075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372986107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.372986107
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1490827668
Short name T210
Test name
Test status
Simulation time 51001290603 ps
CPU time 1016.37 seconds
Started May 09 12:39:50 PM PDT 24
Finished May 09 12:56:58 PM PDT 24
Peak memory 191188 kb
Host smart-eb188976-636c-433b-8d6c-ddd9b06a4dee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490827668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1490827668
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.234611380
Short name T445
Test name
Test status
Simulation time 110687010117 ps
CPU time 80.76 seconds
Started May 09 12:39:44 PM PDT 24
Finished May 09 12:41:13 PM PDT 24
Peak memory 191228 kb
Host smart-d93bc96c-5219-4257-b69c-8f1796ce426d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234611380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.234611380
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1728093646
Short name T391
Test name
Test status
Simulation time 120051427698 ps
CPU time 180.86 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:42:31 PM PDT 24
Peak memory 182976 kb
Host smart-f839331d-a380-4de1-ae23-7a49659a6e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728093646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1728093646
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2697886834
Short name T278
Test name
Test status
Simulation time 323800563796 ps
CPU time 407.11 seconds
Started May 09 12:39:05 PM PDT 24
Finished May 09 12:46:05 PM PDT 24
Peak memory 191244 kb
Host smart-15bc7dea-8b2a-47e9-8720-ea46636100e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697886834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2697886834
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3986627312
Short name T365
Test name
Test status
Simulation time 70742281 ps
CPU time 0.61 seconds
Started May 09 12:39:02 PM PDT 24
Finished May 09 12:39:15 PM PDT 24
Peak memory 182844 kb
Host smart-089e1aea-d90a-4e86-9586-49ff10d6bb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986627312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3986627312
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1770778320
Short name T224
Test name
Test status
Simulation time 30942176086 ps
CPU time 267.51 seconds
Started May 09 12:39:44 PM PDT 24
Finished May 09 12:44:20 PM PDT 24
Peak memory 183032 kb
Host smart-e87ccdde-8d36-495c-863b-de9c2c087151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770778320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1770778320
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.926825901
Short name T290
Test name
Test status
Simulation time 700798618007 ps
CPU time 1151.87 seconds
Started May 09 12:39:35 PM PDT 24
Finished May 09 12:58:55 PM PDT 24
Peak memory 193376 kb
Host smart-8fd45eed-0037-481b-8657-3fd0fdc0f941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926825901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.926825901
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2339887929
Short name T52
Test name
Test status
Simulation time 278061258963 ps
CPU time 501.37 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:48:09 PM PDT 24
Peak memory 191188 kb
Host smart-1c7c98eb-b76a-48e8-bf4b-b2b3f55d6860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339887929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2339887929
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3199500903
Short name T237
Test name
Test status
Simulation time 132479204154 ps
CPU time 456.93 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:47:33 PM PDT 24
Peak memory 191216 kb
Host smart-44036d43-1bab-40d9-aaef-a776708c9419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199500903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3199500903
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3691946610
Short name T303
Test name
Test status
Simulation time 137456579986 ps
CPU time 664.61 seconds
Started May 09 12:39:44 PM PDT 24
Finished May 09 12:50:57 PM PDT 24
Peak memory 183044 kb
Host smart-67d82441-ff7b-4778-89ba-8cfe7f84ddae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691946610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3691946610
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.769868371
Short name T219
Test name
Test status
Simulation time 406166552163 ps
CPU time 339.6 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:45:40 PM PDT 24
Peak memory 191244 kb
Host smart-bc6671c6-ef71-47bf-b202-bbbd15f212b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769868371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.769868371
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2260054366
Short name T177
Test name
Test status
Simulation time 148644792171 ps
CPU time 180.78 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:42:38 PM PDT 24
Peak memory 191156 kb
Host smart-5d8b5ca7-651a-4976-99fd-8dba380da7e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260054366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2260054366
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3617761290
Short name T427
Test name
Test status
Simulation time 98218125751 ps
CPU time 30.27 seconds
Started May 09 12:39:04 PM PDT 24
Finished May 09 12:39:47 PM PDT 24
Peak memory 183008 kb
Host smart-4c46462a-4bc9-491e-b632-6ad314f94377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617761290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3617761290
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.134625803
Short name T408
Test name
Test status
Simulation time 87315884 ps
CPU time 0.65 seconds
Started May 09 12:39:18 PM PDT 24
Finished May 09 12:39:27 PM PDT 24
Peak memory 182776 kb
Host smart-eb3ca717-81ca-4297-a762-631d2ddb607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134625803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.134625803
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.4052579232
Short name T308
Test name
Test status
Simulation time 69825327046 ps
CPU time 112.93 seconds
Started May 09 12:39:37 PM PDT 24
Finished May 09 12:41:38 PM PDT 24
Peak memory 191152 kb
Host smart-54999ae8-1628-433a-8645-fa5f186852cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052579232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.4052579232
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.709044585
Short name T150
Test name
Test status
Simulation time 150470711790 ps
CPU time 277.18 seconds
Started May 09 12:39:38 PM PDT 24
Finished May 09 12:44:23 PM PDT 24
Peak memory 191212 kb
Host smart-efcd61ee-a8f3-44a0-ad48-2357f9fedad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709044585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.709044585
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1488776636
Short name T10
Test name
Test status
Simulation time 60011434483 ps
CPU time 50.26 seconds
Started May 09 12:39:44 PM PDT 24
Finished May 09 12:40:42 PM PDT 24
Peak memory 194492 kb
Host smart-c5da4750-38e5-4007-883c-6ca40c1726df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488776636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1488776636
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.102413378
Short name T43
Test name
Test status
Simulation time 91733859834 ps
CPU time 77.05 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:41:05 PM PDT 24
Peak memory 191200 kb
Host smart-634ee351-d9eb-4682-ab4b-f194426ced45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102413378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.102413378
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2154207392
Short name T447
Test name
Test status
Simulation time 272927278625 ps
CPU time 669.31 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:51:04 PM PDT 24
Peak memory 191256 kb
Host smart-39b53593-f869-4dcd-97fb-714c909398f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154207392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2154207392
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2409920074
Short name T274
Test name
Test status
Simulation time 13737800396 ps
CPU time 24.59 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:40:12 PM PDT 24
Peak memory 182980 kb
Host smart-72ee38fb-2f00-42b9-ae58-501965213af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409920074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2409920074
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3807655580
Short name T21
Test name
Test status
Simulation time 47963680995 ps
CPU time 73.04 seconds
Started May 09 12:39:00 PM PDT 24
Finished May 09 12:40:27 PM PDT 24
Peak memory 182980 kb
Host smart-cf8cc2f2-8ea3-43cf-adbf-30cd5df53a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807655580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3807655580
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2354168290
Short name T11
Test name
Test status
Simulation time 92949108629 ps
CPU time 131.63 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:41:26 PM PDT 24
Peak memory 191224 kb
Host smart-8af2bf3f-d5f3-41ac-80a4-17958dd129f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354168290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2354168290
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1582280511
Short name T234
Test name
Test status
Simulation time 1515818868195 ps
CPU time 994.34 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:55:49 PM PDT 24
Peak memory 194908 kb
Host smart-1dc55bd0-98b7-4a76-aa01-402d2d8bae21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582280511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1582280511
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.510906998
Short name T285
Test name
Test status
Simulation time 178904493085 ps
CPU time 93.24 seconds
Started May 09 12:39:45 PM PDT 24
Finished May 09 12:41:26 PM PDT 24
Peak memory 191140 kb
Host smart-c912cc30-1c54-46c3-ab8a-1baeed24f92e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510906998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.510906998
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2252751433
Short name T235
Test name
Test status
Simulation time 357896329508 ps
CPU time 310.45 seconds
Started May 09 12:39:45 PM PDT 24
Finished May 09 12:45:03 PM PDT 24
Peak memory 191248 kb
Host smart-f60b2580-c831-4f10-9b9a-a9bc5aa8fa4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252751433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2252751433
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1895091049
Short name T42
Test name
Test status
Simulation time 215500219632 ps
CPU time 289.2 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:44:43 PM PDT 24
Peak memory 191108 kb
Host smart-1fc75151-55f0-4412-891d-2c90af09c6ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895091049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1895091049
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2431508876
Short name T324
Test name
Test status
Simulation time 43455808572 ps
CPU time 70.95 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:41:08 PM PDT 24
Peak memory 183008 kb
Host smart-6115e449-d550-47b6-9329-1f6a1259c2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431508876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2431508876
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3751648009
Short name T266
Test name
Test status
Simulation time 94036104432 ps
CPU time 175.56 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:42:53 PM PDT 24
Peak memory 194912 kb
Host smart-b38f692b-e0be-4e5c-bde3-532b47aad122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751648009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3751648009
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1377242233
Short name T344
Test name
Test status
Simulation time 232994869080 ps
CPU time 388.93 seconds
Started May 09 12:39:40 PM PDT 24
Finished May 09 12:46:17 PM PDT 24
Peak memory 191156 kb
Host smart-72dc3731-e244-4c9f-bd07-7fd4358a3819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377242233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1377242233
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1329635674
Short name T392
Test name
Test status
Simulation time 125258461397 ps
CPU time 210.04 seconds
Started May 09 12:39:04 PM PDT 24
Finished May 09 12:42:47 PM PDT 24
Peak memory 182976 kb
Host smart-e44b42b4-091f-4a68-96cd-722a9845d800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329635674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1329635674
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2961981790
Short name T214
Test name
Test status
Simulation time 73864956957 ps
CPU time 142.17 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:41:36 PM PDT 24
Peak memory 191196 kb
Host smart-88cf03c1-0b8d-4c67-952a-649d7210e03e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961981790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2961981790
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3595102899
Short name T337
Test name
Test status
Simulation time 65326935887 ps
CPU time 29.45 seconds
Started May 09 12:38:58 PM PDT 24
Finished May 09 12:39:41 PM PDT 24
Peak memory 183032 kb
Host smart-a5826fb4-572b-4283-a87c-7d89a898648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595102899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3595102899
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.3260087466
Short name T286
Test name
Test status
Simulation time 44699891294 ps
CPU time 345.23 seconds
Started May 09 12:39:43 PM PDT 24
Finished May 09 12:45:35 PM PDT 24
Peak memory 183012 kb
Host smart-13526c4c-b0a6-4d73-a1f2-ceda0aa57326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260087466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3260087466
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2210318477
Short name T126
Test name
Test status
Simulation time 107402022177 ps
CPU time 441.95 seconds
Started May 09 12:39:50 PM PDT 24
Finished May 09 12:47:24 PM PDT 24
Peak memory 191212 kb
Host smart-0ed3de80-8c13-4a1a-bf81-60975470024c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210318477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2210318477
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1662208252
Short name T294
Test name
Test status
Simulation time 39800804266 ps
CPU time 63.66 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:40:42 PM PDT 24
Peak memory 183004 kb
Host smart-c5992011-d2b8-4aca-8b69-77c0bb65243c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662208252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1662208252
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3780365983
Short name T230
Test name
Test status
Simulation time 50256455752 ps
CPU time 76.98 seconds
Started May 09 12:39:52 PM PDT 24
Finished May 09 12:41:22 PM PDT 24
Peak memory 182964 kb
Host smart-c7c0f4bc-36c5-421b-bec0-ce3345a60a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780365983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3780365983
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3145926555
Short name T229
Test name
Test status
Simulation time 2332020204218 ps
CPU time 911.68 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:55:09 PM PDT 24
Peak memory 191164 kb
Host smart-977a538b-df86-472f-af0e-460ddc8cec93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145926555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3145926555
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4213049593
Short name T357
Test name
Test status
Simulation time 415195628620 ps
CPU time 741.08 seconds
Started May 09 12:39:12 PM PDT 24
Finished May 09 12:51:43 PM PDT 24
Peak memory 183016 kb
Host smart-e2554f81-b668-4cb6-b8e8-4fd3f7ce8727
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213049593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4213049593
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3606267918
Short name T368
Test name
Test status
Simulation time 27366625262 ps
CPU time 19.39 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:39:34 PM PDT 24
Peak memory 183040 kb
Host smart-7eb68d3d-8c59-4a5f-90b7-7fa901c7ca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606267918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3606267918
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3266451299
Short name T369
Test name
Test status
Simulation time 867336698 ps
CPU time 1.21 seconds
Started May 09 12:39:04 PM PDT 24
Finished May 09 12:39:18 PM PDT 24
Peak memory 191788 kb
Host smart-3c99cb49-bf78-4a17-a63d-68242b370652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266451299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3266451299
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/164.rv_timer_random.3587417298
Short name T127
Test name
Test status
Simulation time 510281185358 ps
CPU time 315.42 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:45:10 PM PDT 24
Peak memory 194700 kb
Host smart-6323ab3d-804e-480d-af45-ee3bf6ad5bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587417298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3587417298
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2483040793
Short name T84
Test name
Test status
Simulation time 92773979678 ps
CPU time 147.6 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:42:22 PM PDT 24
Peak memory 191108 kb
Host smart-813d36ff-7db9-4f78-af5e-a72c21b1cfd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483040793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2483040793
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3009595920
Short name T218
Test name
Test status
Simulation time 53172874438 ps
CPU time 33.6 seconds
Started May 09 12:39:42 PM PDT 24
Finished May 09 12:40:23 PM PDT 24
Peak memory 191200 kb
Host smart-6366d834-ca92-4ea4-8072-0da5a2654054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009595920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3009595920
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2963908021
Short name T192
Test name
Test status
Simulation time 31499323090 ps
CPU time 161.78 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:42:42 PM PDT 24
Peak memory 191236 kb
Host smart-9428dd41-5f64-4231-8f23-2e2185aca9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963908021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2963908021
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.470868417
Short name T74
Test name
Test status
Simulation time 94722313524 ps
CPU time 19.58 seconds
Started May 09 12:39:42 PM PDT 24
Finished May 09 12:40:08 PM PDT 24
Peak memory 183012 kb
Host smart-1b705e4a-c201-41f5-97a1-7cc68b8c94fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470868417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.470868417
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2313040241
Short name T190
Test name
Test status
Simulation time 285396997439 ps
CPU time 96.14 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:41:33 PM PDT 24
Peak memory 191236 kb
Host smart-4f3081b7-e85b-4ba7-bb01-bc8d718eee80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313040241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2313040241
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3983771606
Short name T393
Test name
Test status
Simulation time 157582320062 ps
CPU time 72.32 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:40:27 PM PDT 24
Peak memory 183012 kb
Host smart-e0b040a2-f675-4354-8e00-b2034f027b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983771606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3983771606
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.287291038
Short name T388
Test name
Test status
Simulation time 96417994 ps
CPU time 0.92 seconds
Started May 09 12:39:03 PM PDT 24
Finished May 09 12:39:18 PM PDT 24
Peak memory 182960 kb
Host smart-067211c8-2b4b-422a-b052-759e1d641ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287291038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.287291038
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1266103145
Short name T12
Test name
Test status
Simulation time 108760412511 ps
CPU time 895.54 seconds
Started May 09 12:39:06 PM PDT 24
Finished May 09 12:54:14 PM PDT 24
Peak memory 210932 kb
Host smart-ebf54ccc-6d34-4906-8210-175b82cea476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266103145 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1266103145
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3961752712
Short name T307
Test name
Test status
Simulation time 87438778661 ps
CPU time 473.28 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:47:51 PM PDT 24
Peak memory 191208 kb
Host smart-8471fa99-a541-40ac-b89a-3aa8bdff2cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961752712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3961752712
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1888416521
Short name T245
Test name
Test status
Simulation time 87574664939 ps
CPU time 192.18 seconds
Started May 09 12:39:55 PM PDT 24
Finished May 09 12:43:21 PM PDT 24
Peak memory 191244 kb
Host smart-89ce98fe-cef2-4846-81b1-0bedc816dce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888416521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1888416521
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1882748574
Short name T315
Test name
Test status
Simulation time 465953469834 ps
CPU time 118.63 seconds
Started May 09 12:39:52 PM PDT 24
Finished May 09 12:42:02 PM PDT 24
Peak memory 183048 kb
Host smart-5918a5bf-89ac-46c9-9c61-66be184fd912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882748574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1882748574
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1732479968
Short name T444
Test name
Test status
Simulation time 162342001030 ps
CPU time 79.01 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:41:16 PM PDT 24
Peak memory 191212 kb
Host smart-bbe00466-1e46-42f8-a359-33d27a549702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732479968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1732479968
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4038583837
Short name T423
Test name
Test status
Simulation time 43885617392 ps
CPU time 44.37 seconds
Started May 09 12:39:48 PM PDT 24
Finished May 09 12:40:42 PM PDT 24
Peak memory 183044 kb
Host smart-0813ea91-39d0-4c36-b3a3-4d7a9e82f0ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038583837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4038583837
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3384573105
Short name T430
Test name
Test status
Simulation time 803268480478 ps
CPU time 450.49 seconds
Started May 09 12:39:11 PM PDT 24
Finished May 09 12:46:51 PM PDT 24
Peak memory 183040 kb
Host smart-41fc9c8a-289a-47eb-95fb-90fcd45a6bbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384573105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3384573105
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.284954946
Short name T87
Test name
Test status
Simulation time 49197768031 ps
CPU time 39.42 seconds
Started May 09 12:39:03 PM PDT 24
Finished May 09 12:39:55 PM PDT 24
Peak memory 182996 kb
Host smart-78c9ec29-d210-4319-aed1-eafe48aebcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284954946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.284954946
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3415937239
Short name T358
Test name
Test status
Simulation time 816169968164 ps
CPU time 154.75 seconds
Started May 09 12:39:00 PM PDT 24
Finished May 09 12:41:48 PM PDT 24
Peak memory 191192 kb
Host smart-df263c20-786b-4d27-9367-9ea7e52bb109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415937239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3415937239
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4250355280
Short name T334
Test name
Test status
Simulation time 234003567861 ps
CPU time 544.14 seconds
Started May 09 12:39:14 PM PDT 24
Finished May 09 12:48:27 PM PDT 24
Peak memory 191256 kb
Host smart-4457fda5-d86a-4b9e-8169-840beecafa68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250355280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4250355280
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.2635083275
Short name T120
Test name
Test status
Simulation time 128335272703 ps
CPU time 200.73 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:43:21 PM PDT 24
Peak memory 194816 kb
Host smart-b9d9e4d9-8a95-4041-a4c4-9614897f704e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635083275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2635083275
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2142443917
Short name T159
Test name
Test status
Simulation time 677502899127 ps
CPU time 309.11 seconds
Started May 09 12:39:52 PM PDT 24
Finished May 09 12:45:13 PM PDT 24
Peak memory 191060 kb
Host smart-005e8c33-3666-48da-9cb6-8219cd5e521f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142443917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2142443917
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1347787672
Short name T311
Test name
Test status
Simulation time 8001283317 ps
CPU time 8.07 seconds
Started May 09 12:39:50 PM PDT 24
Finished May 09 12:40:09 PM PDT 24
Peak memory 183008 kb
Host smart-4006a6e1-ed5b-4c35-b95b-a35752fe42f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347787672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1347787672
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2267713946
Short name T283
Test name
Test status
Simulation time 68261928703 ps
CPU time 123.69 seconds
Started May 09 12:39:53 PM PDT 24
Finished May 09 12:42:09 PM PDT 24
Peak memory 191072 kb
Host smart-3146a973-70bb-499f-87f3-aa70db7032f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267713946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2267713946
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2154064169
Short name T243
Test name
Test status
Simulation time 632486176348 ps
CPU time 247.71 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:44:07 PM PDT 24
Peak memory 191228 kb
Host smart-809cc99d-05f0-4cf3-b19b-e4d75cc32309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154064169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2154064169
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1173868744
Short name T123
Test name
Test status
Simulation time 521259165445 ps
CPU time 1596.59 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 01:06:33 PM PDT 24
Peak memory 191208 kb
Host smart-3bc071b7-1ed2-4ab9-85a1-d8ba83f6b304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173868744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1173868744
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3045961482
Short name T81
Test name
Test status
Simulation time 270418381530 ps
CPU time 2066.3 seconds
Started May 09 12:39:51 PM PDT 24
Finished May 09 01:14:30 PM PDT 24
Peak memory 191208 kb
Host smart-39a9ce85-368b-4db5-a11b-60ec444ad1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045961482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3045961482
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2520705503
Short name T165
Test name
Test status
Simulation time 5012127687 ps
CPU time 4.68 seconds
Started May 09 12:38:59 PM PDT 24
Finished May 09 12:39:17 PM PDT 24
Peak memory 183024 kb
Host smart-1a5f9491-0d6d-4629-8229-ec4978e4bad7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520705503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2520705503
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2936958214
Short name T410
Test name
Test status
Simulation time 288247220609 ps
CPU time 232.28 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:43:22 PM PDT 24
Peak memory 183032 kb
Host smart-fb943c66-53e1-4a45-acd3-958eb9f9d18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936958214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2936958214
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.4290901797
Short name T323
Test name
Test status
Simulation time 111985103764 ps
CPU time 95.82 seconds
Started May 09 12:38:59 PM PDT 24
Finished May 09 12:40:48 PM PDT 24
Peak memory 191240 kb
Host smart-1d1ac360-85e7-47db-a98b-05686982c63f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290901797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.4290901797
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2095628371
Short name T379
Test name
Test status
Simulation time 1851709534 ps
CPU time 5.44 seconds
Started May 09 12:39:02 PM PDT 24
Finished May 09 12:39:21 PM PDT 24
Peak memory 191144 kb
Host smart-8674f5be-aa18-42e4-85db-a9f74bbdb72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095628371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2095628371
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.654378670
Short name T66
Test name
Test status
Simulation time 44480962261 ps
CPU time 72.18 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:40:40 PM PDT 24
Peak memory 194064 kb
Host smart-ac24292f-f30c-4148-98a1-ca213b1b5a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654378670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
654378670
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1402826833
Short name T309
Test name
Test status
Simulation time 122901523280 ps
CPU time 52.66 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:40:50 PM PDT 24
Peak memory 182924 kb
Host smart-7711aac3-fa88-44f3-8d9b-a2d8ebd6c243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402826833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1402826833
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2182279464
Short name T146
Test name
Test status
Simulation time 345641941251 ps
CPU time 224.56 seconds
Started May 09 12:39:50 PM PDT 24
Finished May 09 12:43:46 PM PDT 24
Peak memory 191184 kb
Host smart-a73c382b-8a17-4c8f-8d81-b618857144c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182279464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2182279464
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.925419180
Short name T153
Test name
Test status
Simulation time 124092332909 ps
CPU time 241.09 seconds
Started May 09 12:39:50 PM PDT 24
Finished May 09 12:44:03 PM PDT 24
Peak memory 191220 kb
Host smart-40428048-d41c-49d8-a436-11e9979e5b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925419180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.925419180
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4099751313
Short name T359
Test name
Test status
Simulation time 281256135418 ps
CPU time 72.85 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:41:13 PM PDT 24
Peak memory 183004 kb
Host smart-98241e02-9788-4008-bdb7-ee3b5d5d5974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099751313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4099751313
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1502668085
Short name T314
Test name
Test status
Simulation time 25715344226 ps
CPU time 36.46 seconds
Started May 09 12:40:04 PM PDT 24
Finished May 09 12:40:53 PM PDT 24
Peak memory 182924 kb
Host smart-45cee876-8709-4862-8ff2-f79fa74837f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502668085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1502668085
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3944579818
Short name T345
Test name
Test status
Simulation time 1580624391352 ps
CPU time 384.82 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:46:19 PM PDT 24
Peak memory 191220 kb
Host smart-fbcb5929-f20c-439e-b973-6b8cbbdb7ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944579818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3944579818
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3929524936
Short name T261
Test name
Test status
Simulation time 343156347237 ps
CPU time 389.08 seconds
Started May 09 12:39:55 PM PDT 24
Finished May 09 12:46:37 PM PDT 24
Peak memory 191028 kb
Host smart-91b57aac-f26c-453e-80e6-468b5caae8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929524936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3929524936
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1824667528
Short name T202
Test name
Test status
Simulation time 61059686067 ps
CPU time 89.6 seconds
Started May 09 12:39:53 PM PDT 24
Finished May 09 12:41:35 PM PDT 24
Peak memory 191068 kb
Host smart-11890f62-50dd-4706-a4ff-63e7a6b0c67f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824667528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1824667528
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1774111176
Short name T156
Test name
Test status
Simulation time 411793976895 ps
CPU time 228.15 seconds
Started May 09 12:38:49 PM PDT 24
Finished May 09 12:42:52 PM PDT 24
Peak memory 182928 kb
Host smart-1b0bb489-37a5-4dcb-9fda-cac603e74a62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774111176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1774111176
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1071435501
Short name T69
Test name
Test status
Simulation time 397105555879 ps
CPU time 229.43 seconds
Started May 09 12:38:50 PM PDT 24
Finished May 09 12:42:55 PM PDT 24
Peak memory 183000 kb
Host smart-92fdda4e-6f00-40a6-b586-d4c1f1bd8361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071435501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1071435501
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3874326705
Short name T186
Test name
Test status
Simulation time 179363655638 ps
CPU time 150.38 seconds
Started May 09 12:38:46 PM PDT 24
Finished May 09 12:41:33 PM PDT 24
Peak memory 191160 kb
Host smart-d39ec27e-0a2d-46a0-b792-511bd4455c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874326705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3874326705
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2753612484
Short name T342
Test name
Test status
Simulation time 36179557873 ps
CPU time 240.93 seconds
Started May 09 12:38:46 PM PDT 24
Finished May 09 12:43:03 PM PDT 24
Peak memory 191236 kb
Host smart-9748af40-834d-494b-a1bd-efc82b3d713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753612484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2753612484
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.549537403
Short name T15
Test name
Test status
Simulation time 300952188 ps
CPU time 0.87 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:39:03 PM PDT 24
Peak memory 213508 kb
Host smart-b3ee2024-16d6-450d-ba50-e92340bac9f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549537403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.549537403
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2771775855
Short name T420
Test name
Test status
Simulation time 425525418507 ps
CPU time 403.59 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:45:46 PM PDT 24
Peak memory 196760 kb
Host smart-1fc7069b-b471-454c-81ae-433da6dff755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771775855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2771775855
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.4079962031
Short name T259
Test name
Test status
Simulation time 84008388245 ps
CPU time 132.17 seconds
Started May 09 12:39:08 PM PDT 24
Finished May 09 12:41:32 PM PDT 24
Peak memory 183012 kb
Host smart-c5facb1c-4380-4fa3-905e-db3737572b89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079962031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.4079962031
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3313223024
Short name T376
Test name
Test status
Simulation time 92832670439 ps
CPU time 69.19 seconds
Started May 09 12:39:03 PM PDT 24
Finished May 09 12:40:25 PM PDT 24
Peak memory 183036 kb
Host smart-aad88d61-2d73-416d-b85d-42616cf5b53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313223024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3313223024
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.561834201
Short name T241
Test name
Test status
Simulation time 197077144075 ps
CPU time 854.96 seconds
Started May 09 12:39:04 PM PDT 24
Finished May 09 12:53:32 PM PDT 24
Peak memory 191212 kb
Host smart-50e269f2-cc23-4d43-bfe2-e6d7b1cfe731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561834201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.561834201
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1901408890
Short name T425
Test name
Test status
Simulation time 1699936470 ps
CPU time 2.39 seconds
Started May 09 12:39:03 PM PDT 24
Finished May 09 12:39:18 PM PDT 24
Peak memory 191136 kb
Host smart-d60aecf3-e853-4df5-b9e7-de16971906f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901408890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1901408890
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.777419546
Short name T130
Test name
Test status
Simulation time 322204705827 ps
CPU time 565.24 seconds
Started May 09 12:39:02 PM PDT 24
Finished May 09 12:48:45 PM PDT 24
Peak memory 183036 kb
Host smart-b2d6a822-427d-4a8a-802d-3ee6e64c6bb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777419546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.777419546
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3831563478
Short name T411
Test name
Test status
Simulation time 27706021410 ps
CPU time 42.25 seconds
Started May 09 12:39:11 PM PDT 24
Finished May 09 12:40:03 PM PDT 24
Peak memory 182908 kb
Host smart-3f08ebf9-a195-49be-8dae-14db3d5aae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831563478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3831563478
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2435735222
Short name T407
Test name
Test status
Simulation time 484246520642 ps
CPU time 260.24 seconds
Started May 09 12:39:18 PM PDT 24
Finished May 09 12:43:50 PM PDT 24
Peak memory 191256 kb
Host smart-d172f8fe-04a6-4d66-bb2c-be15fc61a80e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435735222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2435735222
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2185665711
Short name T442
Test name
Test status
Simulation time 130786627587 ps
CPU time 191.04 seconds
Started May 09 12:39:12 PM PDT 24
Finished May 09 12:42:33 PM PDT 24
Peak memory 191244 kb
Host smart-9a008879-1168-454d-a3ac-77d64090aac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185665711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2185665711
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3790380515
Short name T402
Test name
Test status
Simulation time 346230280028 ps
CPU time 162.88 seconds
Started May 09 12:39:03 PM PDT 24
Finished May 09 12:41:59 PM PDT 24
Peak memory 183004 kb
Host smart-3228c05b-9c1f-44d7-81ba-52d839815af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790380515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3790380515
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3452094740
Short name T339
Test name
Test status
Simulation time 225466488013 ps
CPU time 429.01 seconds
Started May 09 12:39:08 PM PDT 24
Finished May 09 12:46:29 PM PDT 24
Peak memory 194980 kb
Host smart-295a0127-4d5a-4934-990b-ddafd7c96e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452094740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3452094740
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3312937984
Short name T431
Test name
Test status
Simulation time 384924481627 ps
CPU time 138.46 seconds
Started May 09 12:39:02 PM PDT 24
Finished May 09 12:41:34 PM PDT 24
Peak memory 183024 kb
Host smart-3872f9e2-a023-4299-87cd-a7a3558e3d52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312937984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3312937984
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3944973937
Short name T387
Test name
Test status
Simulation time 77374086185 ps
CPU time 66.38 seconds
Started May 09 12:39:12 PM PDT 24
Finished May 09 12:40:29 PM PDT 24
Peak memory 183008 kb
Host smart-0aff95fa-6412-4620-b507-a57d3920d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944973937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3944973937
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1529437935
Short name T250
Test name
Test status
Simulation time 47133448422 ps
CPU time 80.57 seconds
Started May 09 12:39:13 PM PDT 24
Finished May 09 12:40:43 PM PDT 24
Peak memory 191272 kb
Host smart-5544964e-ae5a-42a6-8a4c-d797ec210d31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529437935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1529437935
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2234312331
Short name T4
Test name
Test status
Simulation time 417486613 ps
CPU time 1.04 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:39:34 PM PDT 24
Peak memory 182808 kb
Host smart-5c028974-e381-4c35-ba4c-438ba3bee378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234312331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2234312331
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3270540863
Short name T412
Test name
Test status
Simulation time 394577474944 ps
CPU time 625.3 seconds
Started May 09 12:39:13 PM PDT 24
Finished May 09 12:49:48 PM PDT 24
Peak memory 183044 kb
Host smart-0675d907-fc73-497d-a41a-7a798d54d91a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270540863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3270540863
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3580913814
Short name T83
Test name
Test status
Simulation time 288032200665 ps
CPU time 111.29 seconds
Started May 09 12:39:12 PM PDT 24
Finished May 09 12:41:13 PM PDT 24
Peak memory 183024 kb
Host smart-2f726be7-102c-43bf-8ef5-0e2f5dd245c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580913814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3580913814
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.561928659
Short name T169
Test name
Test status
Simulation time 229550759357 ps
CPU time 176.03 seconds
Started May 09 12:39:18 PM PDT 24
Finished May 09 12:42:23 PM PDT 24
Peak memory 191220 kb
Host smart-63ece5f3-71fd-4965-9424-358013ebddd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561928659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.561928659
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2211304849
Short name T279
Test name
Test status
Simulation time 275621405663 ps
CPU time 70.01 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:40:50 PM PDT 24
Peak memory 183016 kb
Host smart-87c7f2f3-abbe-49b6-aac4-b31762ff8110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211304849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2211304849
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.731527320
Short name T270
Test name
Test status
Simulation time 1121709320280 ps
CPU time 407.51 seconds
Started May 09 12:39:15 PM PDT 24
Finished May 09 12:46:12 PM PDT 24
Peak memory 191256 kb
Host smart-7a290995-f525-4c11-adce-a5918f78b12b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731527320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
731527320
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.4167172197
Short name T145
Test name
Test status
Simulation time 72866155139 ps
CPU time 111.79 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:41:21 PM PDT 24
Peak memory 183040 kb
Host smart-4406f5ad-34c2-4984-a9e2-2e85efc5396a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167172197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.4167172197
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2769637009
Short name T8
Test name
Test status
Simulation time 52914038836 ps
CPU time 73.43 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:40:42 PM PDT 24
Peak memory 182920 kb
Host smart-75920d03-a6dc-4c7f-9b93-685e179e892e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769637009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2769637009
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2249708428
Short name T253
Test name
Test status
Simulation time 39954354894 ps
CPU time 73.39 seconds
Started May 09 12:39:23 PM PDT 24
Finished May 09 12:40:44 PM PDT 24
Peak memory 191144 kb
Host smart-80eebc20-d365-414b-96f5-db9712844956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249708428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2249708428
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.491735032
Short name T396
Test name
Test status
Simulation time 470911620 ps
CPU time 0.73 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:39:41 PM PDT 24
Peak memory 182812 kb
Host smart-a1aa0f31-d2b8-4765-9610-ffb40b5e08ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491735032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.491735032
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1747633892
Short name T64
Test name
Test status
Simulation time 346679952457 ps
CPU time 359.49 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:45:35 PM PDT 24
Peak memory 195044 kb
Host smart-e340dd4d-fd8c-484a-a2ce-74c67be8ed89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747633892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1747633892
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2550635727
Short name T23
Test name
Test status
Simulation time 1152647228837 ps
CPU time 599.98 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:49:29 PM PDT 24
Peak memory 183012 kb
Host smart-e5e35286-1759-40f3-8a68-8a767e15ab62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550635727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2550635727
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2147773063
Short name T55
Test name
Test status
Simulation time 138783742689 ps
CPU time 107.06 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:41:15 PM PDT 24
Peak memory 183008 kb
Host smart-623bfe2a-6e72-4ed4-9acf-4ddafad461ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147773063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2147773063
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1585055052
Short name T441
Test name
Test status
Simulation time 203677828348 ps
CPU time 135.08 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:41:51 PM PDT 24
Peak memory 183032 kb
Host smart-e08724ce-c07b-49e2-8dee-b1ba266e4b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585055052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1585055052
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2003971549
Short name T54
Test name
Test status
Simulation time 238974251 ps
CPU time 0.8 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:39:39 PM PDT 24
Peak memory 182816 kb
Host smart-fe5601a5-c878-45d1-a970-e580752d10a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003971549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2003971549
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2830911372
Short name T26
Test name
Test status
Simulation time 131071442423 ps
CPU time 228.41 seconds
Started May 09 12:39:35 PM PDT 24
Finished May 09 12:43:32 PM PDT 24
Peak memory 195132 kb
Host smart-dc2412bd-dd95-4792-9e49-4b0437c0f9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830911372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2830911372
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.693715166
Short name T435
Test name
Test status
Simulation time 6017599402 ps
CPU time 3.88 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:39:32 PM PDT 24
Peak memory 182984 kb
Host smart-0fc8711c-b347-4263-ae96-ece4ed4c7438
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693715166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.693715166
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1834494747
Short name T436
Test name
Test status
Simulation time 798227681142 ps
CPU time 216.93 seconds
Started May 09 12:39:50 PM PDT 24
Finished May 09 12:43:38 PM PDT 24
Peak memory 183016 kb
Host smart-8598e2f6-1b39-427f-aa92-2094449434b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834494747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1834494747
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.4173611463
Short name T418
Test name
Test status
Simulation time 67798464708 ps
CPU time 43.14 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:40:12 PM PDT 24
Peak memory 183004 kb
Host smart-da7140e4-f9d1-4660-a23e-f7c7f5c48d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173611463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.4173611463
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1145487606
Short name T306
Test name
Test status
Simulation time 29047943140 ps
CPU time 1018.17 seconds
Started May 09 12:39:24 PM PDT 24
Finished May 09 12:56:30 PM PDT 24
Peak memory 191188 kb
Host smart-d29783af-6257-4c69-b793-a7930710de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145487606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1145487606
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1207103691
Short name T257
Test name
Test status
Simulation time 1048479487512 ps
CPU time 1070.31 seconds
Started May 09 12:39:36 PM PDT 24
Finished May 09 12:57:34 PM PDT 24
Peak memory 191248 kb
Host smart-b25dbc24-399c-4e36-93ae-5fc042c038d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207103691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1207103691
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2531322325
Short name T19
Test name
Test status
Simulation time 804289274385 ps
CPU time 473.31 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 183000 kb
Host smart-c33390c1-6ead-4cab-9d73-164de0383205
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531322325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2531322325
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2056490925
Short name T448
Test name
Test status
Simulation time 492488940158 ps
CPU time 215.84 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:43:24 PM PDT 24
Peak memory 183052 kb
Host smart-2e1f7c90-896e-49ea-a1d2-846bcc482c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056490925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2056490925
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2766571675
Short name T193
Test name
Test status
Simulation time 103830693872 ps
CPU time 1632.14 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 01:06:51 PM PDT 24
Peak memory 192460 kb
Host smart-8070c98d-c8a3-44ce-abbf-0a01e5c16d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766571675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2766571675
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.184210812
Short name T144
Test name
Test status
Simulation time 130788032930 ps
CPU time 52.21 seconds
Started May 09 12:39:34 PM PDT 24
Finished May 09 12:40:35 PM PDT 24
Peak memory 194624 kb
Host smart-6dd7f8ba-1e04-4861-85f9-054d250ee959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184210812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.184210812
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3671646373
Short name T5
Test name
Test status
Simulation time 93871166684 ps
CPU time 121.51 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:41:42 PM PDT 24
Peak memory 194044 kb
Host smart-ae448f42-a1e7-47e3-9834-2ee137576015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671646373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3671646373
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2161983405
Short name T49
Test name
Test status
Simulation time 110596848345 ps
CPU time 45.13 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:40:25 PM PDT 24
Peak memory 182984 kb
Host smart-04a4a709-03a1-427b-b14b-e749e0f8afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161983405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2161983405
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3260042529
Short name T188
Test name
Test status
Simulation time 29481760870 ps
CPU time 240.86 seconds
Started May 09 12:39:37 PM PDT 24
Finished May 09 12:43:46 PM PDT 24
Peak memory 191216 kb
Host smart-7192be70-d481-476e-afd9-e3272919378c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260042529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3260042529
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2624646944
Short name T185
Test name
Test status
Simulation time 70218229350 ps
CPU time 108.11 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 12:41:22 PM PDT 24
Peak memory 191236 kb
Host smart-c2c7d7c1-f48f-4ac7-bbc6-c3662c3bc767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624646944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2624646944
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2903687375
Short name T416
Test name
Test status
Simulation time 474618662314 ps
CPU time 690.35 seconds
Started May 09 12:39:13 PM PDT 24
Finished May 09 12:50:53 PM PDT 24
Peak memory 191248 kb
Host smart-297077f7-58fc-4fca-900a-67e12b151ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903687375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2903687375
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.4292965499
Short name T33
Test name
Test status
Simulation time 104542047400 ps
CPU time 831.03 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 12:53:31 PM PDT 24
Peak memory 212780 kb
Host smart-dae093c3-b694-4988-bca2-c553bd701449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292965499 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.4292965499
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1383632006
Short name T318
Test name
Test status
Simulation time 20394448543 ps
CPU time 10.11 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:39:16 PM PDT 24
Peak memory 183056 kb
Host smart-463d3cce-c05e-4f25-9512-e9fa2a03a34c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383632006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1383632006
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1260551053
Short name T406
Test name
Test status
Simulation time 103113596438 ps
CPU time 170.97 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:41:54 PM PDT 24
Peak memory 182864 kb
Host smart-a35ef88b-af33-4235-b80a-eb3ac9ad4608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260551053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1260551053
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.214384391
Short name T122
Test name
Test status
Simulation time 282446540818 ps
CPU time 119.4 seconds
Started May 09 12:38:48 PM PDT 24
Finished May 09 12:41:03 PM PDT 24
Peak memory 191224 kb
Host smart-73db9e71-0b3b-4d0a-ad38-8ccf71b542fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214384391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.214384391
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.913870320
Short name T18
Test name
Test status
Simulation time 89079734 ps
CPU time 0.87 seconds
Started May 09 12:38:53 PM PDT 24
Finished May 09 12:39:08 PM PDT 24
Peak memory 214568 kb
Host smart-5279b484-15e6-4d68-918b-63fc63a8c94c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913870320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.913870320
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.794933533
Short name T167
Test name
Test status
Simulation time 664930701192 ps
CPU time 338.17 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:45:16 PM PDT 24
Peak memory 183056 kb
Host smart-c2e36bbe-8699-408f-9306-315efc07977e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794933533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.794933533
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.326947820
Short name T381
Test name
Test status
Simulation time 607895769688 ps
CPU time 271.35 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 12:44:06 PM PDT 24
Peak memory 183052 kb
Host smart-824f785c-0615-4eb6-b870-ddf82bf0f9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326947820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.326947820
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2298589429
Short name T297
Test name
Test status
Simulation time 1085619843512 ps
CPU time 2872.24 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 01:27:32 PM PDT 24
Peak memory 191096 kb
Host smart-058dcaab-aeae-4c64-98a8-7a617aad8f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298589429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2298589429
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2134402143
Short name T336
Test name
Test status
Simulation time 79008476802 ps
CPU time 65.43 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:40:43 PM PDT 24
Peak memory 182988 kb
Host smart-50c13dc5-8cef-43f8-837e-d5e7bd02396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134402143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2134402143
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2205757493
Short name T209
Test name
Test status
Simulation time 41307959968 ps
CPU time 73.19 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:40:43 PM PDT 24
Peak memory 183056 kb
Host smart-efbb973d-a811-4615-834c-f69602ab10f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205757493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2205757493
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.4266795467
Short name T443
Test name
Test status
Simulation time 133234059789 ps
CPU time 188.67 seconds
Started May 09 12:39:19 PM PDT 24
Finished May 09 12:42:36 PM PDT 24
Peak memory 183032 kb
Host smart-64fbbfd6-2c50-4d70-adec-350131545345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266795467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.4266795467
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2340708179
Short name T350
Test name
Test status
Simulation time 114460069052 ps
CPU time 572.53 seconds
Started May 09 12:39:17 PM PDT 24
Finished May 09 12:48:58 PM PDT 24
Peak memory 183052 kb
Host smart-f6c49b21-7679-439d-95ce-c0d2266e6f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340708179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2340708179
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3110527749
Short name T319
Test name
Test status
Simulation time 43353349382 ps
CPU time 414.1 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:46:27 PM PDT 24
Peak memory 191232 kb
Host smart-aceea1c6-bc8b-499b-8996-4fc5a9e03a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110527749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3110527749
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1636810238
Short name T59
Test name
Test status
Simulation time 356842884161 ps
CPU time 420.47 seconds
Started May 09 12:39:34 PM PDT 24
Finished May 09 12:46:43 PM PDT 24
Peak memory 191260 kb
Host smart-4581189e-c6b4-488b-86c9-b1fed13c6b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636810238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1636810238
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3376094834
Short name T404
Test name
Test status
Simulation time 50166125083 ps
CPU time 74.5 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:40:51 PM PDT 24
Peak memory 183056 kb
Host smart-dfec3bcd-4ba0-4075-af5b-17f54c0027a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376094834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3376094834
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.4258281251
Short name T289
Test name
Test status
Simulation time 284382908780 ps
CPU time 2317.63 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 01:18:08 PM PDT 24
Peak memory 191236 kb
Host smart-468d87d4-82b4-4030-ae73-8b0c3b34f14b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258281251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4258281251
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3864160572
Short name T63
Test name
Test status
Simulation time 49800849 ps
CPU time 0.58 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:39:38 PM PDT 24
Peak memory 182828 kb
Host smart-bb60740e-5c4b-4221-b187-fd05536ffd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864160572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3864160572
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.665845645
Short name T136
Test name
Test status
Simulation time 25035734356 ps
CPU time 14.31 seconds
Started May 09 12:39:23 PM PDT 24
Finished May 09 12:39:45 PM PDT 24
Peak memory 183032 kb
Host smart-7963f7d4-fd20-41f4-b7ad-4642287ccd42
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665845645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.665845645
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.364575679
Short name T371
Test name
Test status
Simulation time 117451947284 ps
CPU time 51.61 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:40:29 PM PDT 24
Peak memory 183056 kb
Host smart-74e6bd31-d912-45ea-ba25-01ddf6453e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364575679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.364575679
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2876147654
Short name T240
Test name
Test status
Simulation time 192571898052 ps
CPU time 179.64 seconds
Started May 09 12:39:34 PM PDT 24
Finished May 09 12:42:41 PM PDT 24
Peak memory 191252 kb
Host smart-40ff041e-7797-46f6-b26c-0b52afd34dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876147654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2876147654
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1206402980
Short name T139
Test name
Test status
Simulation time 161864402893 ps
CPU time 151.83 seconds
Started May 09 12:40:37 PM PDT 24
Finished May 09 12:43:10 PM PDT 24
Peak memory 191228 kb
Host smart-2641eadc-bc65-4890-94d7-a7ab7c979238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206402980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1206402980
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2020234152
Short name T305
Test name
Test status
Simulation time 33570231029 ps
CPU time 55.82 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:40:32 PM PDT 24
Peak memory 182928 kb
Host smart-d839a99a-b0ad-495c-a404-9aa2c57a3fa5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020234152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2020234152
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3875314631
Short name T421
Test name
Test status
Simulation time 364431027794 ps
CPU time 245.67 seconds
Started May 09 12:39:38 PM PDT 24
Finished May 09 12:43:51 PM PDT 24
Peak memory 183020 kb
Host smart-1edafa27-f340-4909-b0ef-e4ee3c828103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875314631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3875314631
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3914064968
Short name T182
Test name
Test status
Simulation time 85850789117 ps
CPU time 565.37 seconds
Started May 09 12:39:11 PM PDT 24
Finished May 09 12:48:46 PM PDT 24
Peak memory 194352 kb
Host smart-dda3228a-d90d-4211-9dbe-02442d7b39bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914064968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3914064968
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2229351937
Short name T296
Test name
Test status
Simulation time 86658062502 ps
CPU time 156.19 seconds
Started May 09 12:39:36 PM PDT 24
Finished May 09 12:42:20 PM PDT 24
Peak memory 183004 kb
Host smart-0369c317-5952-42ad-ba3b-a8a07e6c0b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229351937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2229351937
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2896945699
Short name T394
Test name
Test status
Simulation time 356542176 ps
CPU time 0.58 seconds
Started May 09 12:39:18 PM PDT 24
Finished May 09 12:39:27 PM PDT 24
Peak memory 182824 kb
Host smart-32a7743e-b0e2-46d3-b15d-15ced4b66722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896945699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2896945699
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2995699013
Short name T428
Test name
Test status
Simulation time 198471570993 ps
CPU time 112.99 seconds
Started May 09 12:39:16 PM PDT 24
Finished May 09 12:41:18 PM PDT 24
Peak memory 182988 kb
Host smart-a6a7f4c3-0fac-4af2-a947-9b0f6e8f07ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995699013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2995699013
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3740437608
Short name T375
Test name
Test status
Simulation time 371670967810 ps
CPU time 149.46 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:42:09 PM PDT 24
Peak memory 183016 kb
Host smart-f3f540a9-6ca8-49f3-b9a7-38d1c7a036cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740437608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3740437608
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1291966992
Short name T262
Test name
Test status
Simulation time 108120936328 ps
CPU time 164.91 seconds
Started May 09 12:39:28 PM PDT 24
Finished May 09 12:42:20 PM PDT 24
Peak memory 191232 kb
Host smart-c0ecc995-e39a-4186-9b68-758e869802c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291966992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1291966992
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.708882248
Short name T246
Test name
Test status
Simulation time 1587737474707 ps
CPU time 903.4 seconds
Started May 09 12:39:16 PM PDT 24
Finished May 09 12:54:28 PM PDT 24
Peak memory 191208 kb
Host smart-e5488b95-4723-4d85-87be-68823030a633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708882248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
708882248
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1162120135
Short name T80
Test name
Test status
Simulation time 18877503361 ps
CPU time 30.26 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:40:10 PM PDT 24
Peak memory 182984 kb
Host smart-4e01d1a1-f2fb-40a2-9fcd-df7d0f2a13b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162120135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1162120135
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3860743639
Short name T137
Test name
Test status
Simulation time 131472459296 ps
CPU time 52.12 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:40:22 PM PDT 24
Peak memory 183056 kb
Host smart-b21ff9ad-1426-46a3-8ba7-2cf2dc9db3b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860743639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3860743639
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1485005890
Short name T383
Test name
Test status
Simulation time 129849943 ps
CPU time 0.78 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:39:40 PM PDT 24
Peak memory 191472 kb
Host smart-a807c2b5-0403-406b-b954-1119f2703088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485005890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1485005890
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.98096990
Short name T384
Test name
Test status
Simulation time 23296331863 ps
CPU time 33.26 seconds
Started May 09 12:39:08 PM PDT 24
Finished May 09 12:39:53 PM PDT 24
Peak memory 183032 kb
Host smart-ccb66bd3-f7e7-4d5f-beef-3a09ca48990f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98096990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.98096990
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1884416170
Short name T273
Test name
Test status
Simulation time 1450355487823 ps
CPU time 849.65 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:53:40 PM PDT 24
Peak memory 183040 kb
Host smart-2a1b6283-48c8-48bd-be3c-c1e1c9f3da76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884416170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1884416170
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1812302279
Short name T367
Test name
Test status
Simulation time 117671093930 ps
CPU time 190.62 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:42:39 PM PDT 24
Peak memory 182908 kb
Host smart-531fe8be-d97b-4d01-8a2c-f5782a1fb47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812302279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1812302279
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2351491598
Short name T67
Test name
Test status
Simulation time 440800883593 ps
CPU time 208.1 seconds
Started May 09 12:39:25 PM PDT 24
Finished May 09 12:43:00 PM PDT 24
Peak memory 191144 kb
Host smart-e292a5e6-fdf3-4f87-8a09-a6afa61fcb24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351491598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2351491598
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2074424121
Short name T135
Test name
Test status
Simulation time 84182921966 ps
CPU time 84.23 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:40:52 PM PDT 24
Peak memory 191192 kb
Host smart-56cda061-8360-4e3e-9a34-77ba8015c18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074424121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2074424121
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4130455412
Short name T275
Test name
Test status
Simulation time 126179798959 ps
CPU time 215.31 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 12:43:10 PM PDT 24
Peak memory 196008 kb
Host smart-6fa443d7-fea8-49fe-be41-f4bd1c78b358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130455412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4130455412
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3136956377
Short name T71
Test name
Test status
Simulation time 227508418068 ps
CPU time 70.65 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:40:44 PM PDT 24
Peak memory 182988 kb
Host smart-c3f16847-bd87-4050-8cfb-52846e4e309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136956377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3136956377
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2737787
Short name T346
Test name
Test status
Simulation time 145786507010 ps
CPU time 79.67 seconds
Started May 09 12:39:17 PM PDT 24
Finished May 09 12:40:45 PM PDT 24
Peak memory 183020 kb
Host smart-eb40d10d-351c-48cd-a9b1-c246250aa602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2737787
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4035388822
Short name T284
Test name
Test status
Simulation time 138237185386 ps
CPU time 71.53 seconds
Started May 09 12:39:18 PM PDT 24
Finished May 09 12:40:38 PM PDT 24
Peak memory 191228 kb
Host smart-07fd5457-180b-4f3d-b74c-fc6e31934c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035388822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4035388822
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.780648440
Short name T162
Test name
Test status
Simulation time 1671074186705 ps
CPU time 1008.03 seconds
Started May 09 12:39:05 PM PDT 24
Finished May 09 12:56:05 PM PDT 24
Peak memory 191172 kb
Host smart-fbe42ce4-1eb1-4c8c-8cdf-7710a1ba0b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780648440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
780648440
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3966616059
Short name T434
Test name
Test status
Simulation time 3966948942 ps
CPU time 7.22 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:39:35 PM PDT 24
Peak memory 182988 kb
Host smart-84afeca8-b3ca-4b44-b8d4-ea271b06df83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966616059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3966616059
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3637245993
Short name T401
Test name
Test status
Simulation time 47402213450 ps
CPU time 75.54 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:40:53 PM PDT 24
Peak memory 182976 kb
Host smart-bc38b746-6cd1-46e7-b047-5f6b88272da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637245993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3637245993
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2930135344
Short name T2
Test name
Test status
Simulation time 1213518895 ps
CPU time 1.2 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:39:38 PM PDT 24
Peak memory 191168 kb
Host smart-2d8dcd96-3727-4975-94ba-a831ea6571e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930135344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2930135344
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2895780824
Short name T390
Test name
Test status
Simulation time 29943652 ps
CPU time 0.54 seconds
Started May 09 12:39:38 PM PDT 24
Finished May 09 12:39:46 PM PDT 24
Peak memory 182836 kb
Host smart-fb906aea-70fa-433e-9acd-bc93fdc6a012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895780824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2895780824
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.397852639
Short name T32
Test name
Test status
Simulation time 458952925754 ps
CPU time 782.95 seconds
Started May 09 12:39:12 PM PDT 24
Finished May 09 12:52:25 PM PDT 24
Peak memory 208828 kb
Host smart-2ead65c7-7f2b-4f44-a6c7-7a83ea5e74c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397852639 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.397852639
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.395856179
Short name T446
Test name
Test status
Simulation time 11768732966 ps
CPU time 18.32 seconds
Started May 09 12:38:49 PM PDT 24
Finished May 09 12:39:23 PM PDT 24
Peak memory 183032 kb
Host smart-9473f655-1ca2-4785-9d6f-1ac665e6bf86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395856179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.395856179
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.783429761
Short name T400
Test name
Test status
Simulation time 146073281020 ps
CPU time 116.79 seconds
Started May 09 12:38:49 PM PDT 24
Finished May 09 12:41:02 PM PDT 24
Peak memory 183040 kb
Host smart-8054987f-438a-4014-a135-49ec94310cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783429761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.783429761
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2321829223
Short name T117
Test name
Test status
Simulation time 31287730146 ps
CPU time 377.71 seconds
Started May 09 12:38:56 PM PDT 24
Finished May 09 12:45:28 PM PDT 24
Peak memory 183012 kb
Host smart-7708b7c3-671d-4e67-8cec-ff02b5049c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321829223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2321829223
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.871702472
Short name T16
Test name
Test status
Simulation time 262680051 ps
CPU time 0.89 seconds
Started May 09 12:38:48 PM PDT 24
Finished May 09 12:39:04 PM PDT 24
Peak memory 214576 kb
Host smart-cb71c29e-e5a4-48b0-ab65-505dc02b2999
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871702472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.871702472
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1179877673
Short name T356
Test name
Test status
Simulation time 379186088185 ps
CPU time 535.94 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:47:59 PM PDT 24
Peak memory 191204 kb
Host smart-b3097f8d-5418-4a4f-ad65-e3703f36c59d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179877673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1179877673
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.95452019
Short name T242
Test name
Test status
Simulation time 50506232909 ps
CPU time 91.73 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:41:01 PM PDT 24
Peak memory 183052 kb
Host smart-c4f35203-a46c-4812-b49f-25298a3570e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95452019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.rv_timer_cfg_update_on_fly.95452019
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.401902599
Short name T432
Test name
Test status
Simulation time 555737287299 ps
CPU time 218.06 seconds
Started May 09 12:39:23 PM PDT 24
Finished May 09 12:43:09 PM PDT 24
Peak memory 182980 kb
Host smart-156e5667-e0c7-4784-90ac-2e16eeaa5b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401902599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.401902599
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1265216190
Short name T206
Test name
Test status
Simulation time 104344195635 ps
CPU time 161.81 seconds
Started May 09 12:39:19 PM PDT 24
Finished May 09 12:42:09 PM PDT 24
Peak memory 191184 kb
Host smart-c75ed9d2-b31c-43a9-b113-a0be837640a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265216190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1265216190
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2359353431
Short name T271
Test name
Test status
Simulation time 147482297860 ps
CPU time 146.98 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:41:57 PM PDT 24
Peak memory 183040 kb
Host smart-6d3ea922-55e5-4dda-b46c-f8d2e4f18e91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359353431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2359353431
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.51384446
Short name T40
Test name
Test status
Simulation time 72373853191 ps
CPU time 104.01 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:41:14 PM PDT 24
Peak memory 183044 kb
Host smart-7c16f298-cfef-4397-9160-afc7ee0eacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51384446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.51384446
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.388434179
Short name T211
Test name
Test status
Simulation time 186415483875 ps
CPU time 194.79 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:42:44 PM PDT 24
Peak memory 191224 kb
Host smart-220e3102-4401-4731-a6ea-9196425f0b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388434179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.388434179
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1874558706
Short name T331
Test name
Test status
Simulation time 79067559640 ps
CPU time 205.29 seconds
Started May 09 12:39:15 PM PDT 24
Finished May 09 12:42:49 PM PDT 24
Peak memory 191244 kb
Host smart-5519805b-cc14-4ab9-8594-d8561b3b44cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874558706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1874558706
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3668282556
Short name T197
Test name
Test status
Simulation time 256499835411 ps
CPU time 487.46 seconds
Started May 09 12:39:19 PM PDT 24
Finished May 09 12:47:34 PM PDT 24
Peak memory 182988 kb
Host smart-39b2c933-01db-4178-a03a-e457edcdd612
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668282556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3668282556
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.693754161
Short name T373
Test name
Test status
Simulation time 118232234571 ps
CPU time 173.48 seconds
Started May 09 12:39:14 PM PDT 24
Finished May 09 12:42:17 PM PDT 24
Peak memory 182984 kb
Host smart-b7e6fb3b-3edc-4983-a3a8-a8af05b732db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693754161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.693754161
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1068535773
Short name T419
Test name
Test status
Simulation time 23797567932 ps
CPU time 287.6 seconds
Started May 09 12:39:28 PM PDT 24
Finished May 09 12:44:22 PM PDT 24
Peak memory 191172 kb
Host smart-33edaca8-ecff-42ad-980f-9b5efda9a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068535773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1068535773
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.786512508
Short name T31
Test name
Test status
Simulation time 2303593533887 ps
CPU time 4405.77 seconds
Started May 09 12:39:23 PM PDT 24
Finished May 09 01:52:57 PM PDT 24
Peak memory 195712 kb
Host smart-a2752b0e-50f9-46fa-9447-d9cf2fa640aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786512508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
786512508
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.736212709
Short name T39
Test name
Test status
Simulation time 676822882755 ps
CPU time 200.23 seconds
Started May 09 12:39:25 PM PDT 24
Finished May 09 12:42:52 PM PDT 24
Peak memory 183044 kb
Host smart-689341f5-ddf4-4f3b-be37-1c4b1fc71312
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736212709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.736212709
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.4241706476
Short name T70
Test name
Test status
Simulation time 243883987155 ps
CPU time 78.39 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:40:59 PM PDT 24
Peak memory 182980 kb
Host smart-3ec80aeb-ee12-40b8-8f42-b3bcc3de901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241706476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4241706476
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1694485281
Short name T268
Test name
Test status
Simulation time 227768275631 ps
CPU time 213.85 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:43:15 PM PDT 24
Peak memory 193912 kb
Host smart-89b9304b-ab54-4ace-bb6d-59fe0fe67dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694485281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1694485281
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2028799086
Short name T25
Test name
Test status
Simulation time 1174380564 ps
CPU time 1.46 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:39:40 PM PDT 24
Peak memory 193540 kb
Host smart-caaaecd2-6b3f-42fa-9538-5c90c7ba28e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028799086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2028799086
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2030602979
Short name T86
Test name
Test status
Simulation time 53656197975 ps
CPU time 84.01 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:40:52 PM PDT 24
Peak memory 182980 kb
Host smart-9de1254f-f31b-4186-b362-1fea79bf764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030602979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2030602979
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2488377742
Short name T170
Test name
Test status
Simulation time 77662385267 ps
CPU time 226.21 seconds
Started May 09 12:39:13 PM PDT 24
Finished May 09 12:43:09 PM PDT 24
Peak memory 191260 kb
Host smart-35c57c7a-6d18-41b2-96b3-2ebdb5d378b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488377742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2488377742
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.4267780285
Short name T212
Test name
Test status
Simulation time 316992677126 ps
CPU time 330.47 seconds
Started May 09 12:39:25 PM PDT 24
Finished May 09 12:45:03 PM PDT 24
Peak memory 194460 kb
Host smart-a5d82b95-aaa3-4c72-ae0f-f6f3b0ddfcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267780285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4267780285
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1447465727
Short name T158
Test name
Test status
Simulation time 702008106567 ps
CPU time 1952.16 seconds
Started May 09 12:39:18 PM PDT 24
Finished May 09 01:11:58 PM PDT 24
Peak memory 195112 kb
Host smart-8dec2494-5b31-428f-9245-51e1f12ca970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447465727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1447465727
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2666982792
Short name T34
Test name
Test status
Simulation time 64737841254 ps
CPU time 509.32 seconds
Started May 09 12:39:43 PM PDT 24
Finished May 09 12:48:19 PM PDT 24
Peak memory 205820 kb
Host smart-2ac7e6a1-70dc-4025-9d1c-67b75459e886
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666982792 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2666982792
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.964155881
Short name T360
Test name
Test status
Simulation time 2036497793942 ps
CPU time 566.02 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:49:06 PM PDT 24
Peak memory 182868 kb
Host smart-2f1f5045-eaad-4da7-8b2c-cf2dc6105981
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964155881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.964155881
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.4073443907
Short name T364
Test name
Test status
Simulation time 819441949310 ps
CPU time 296.91 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:44:34 PM PDT 24
Peak memory 182980 kb
Host smart-9174ba93-a3fa-46d1-ab39-cdbf19e33b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073443907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.4073443907
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.344478226
Short name T9
Test name
Test status
Simulation time 23158140842 ps
CPU time 33.94 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 12:40:08 PM PDT 24
Peak memory 182992 kb
Host smart-442c509b-680d-4117-b8e7-5da5fcb11541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344478226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.344478226
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3126287050
Short name T227
Test name
Test status
Simulation time 52785436613 ps
CPU time 105 seconds
Started May 09 12:39:25 PM PDT 24
Finished May 09 12:41:17 PM PDT 24
Peak memory 191220 kb
Host smart-2eff421a-fb73-46c0-b1cb-4c153891f3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126287050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3126287050
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1798355946
Short name T13
Test name
Test status
Simulation time 59173290326 ps
CPU time 332.05 seconds
Started May 09 12:39:22 PM PDT 24
Finished May 09 12:45:02 PM PDT 24
Peak memory 197632 kb
Host smart-e561aee4-2ad4-4672-93de-694049b35ad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798355946 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1798355946
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3584958638
Short name T276
Test name
Test status
Simulation time 138183060826 ps
CPU time 227.85 seconds
Started May 09 12:39:37 PM PDT 24
Finished May 09 12:43:32 PM PDT 24
Peak memory 183292 kb
Host smart-846815ba-00ea-4311-b996-29a2b2d136a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584958638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3584958638
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3418994408
Short name T389
Test name
Test status
Simulation time 16992367395 ps
CPU time 13.17 seconds
Started May 09 12:39:31 PM PDT 24
Finished May 09 12:39:52 PM PDT 24
Peak memory 183004 kb
Host smart-f41d8791-59e4-4db7-8486-d878dbc319e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418994408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3418994408
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.624252386
Short name T439
Test name
Test status
Simulation time 189427844620 ps
CPU time 1633.92 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 01:06:48 PM PDT 24
Peak memory 183052 kb
Host smart-ffa174e0-4987-452b-a7b9-abd6cd80ec80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624252386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.624252386
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4184903125
Short name T429
Test name
Test status
Simulation time 229594326 ps
CPU time 0.62 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:39:40 PM PDT 24
Peak memory 182804 kb
Host smart-03eed5ed-bee6-4259-81f7-dfd6003d01e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184903125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4184903125
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3835141572
Short name T374
Test name
Test status
Simulation time 43276013 ps
CPU time 0.53 seconds
Started May 09 12:39:35 PM PDT 24
Finished May 09 12:39:44 PM PDT 24
Peak memory 182728 kb
Host smart-b676cf16-b0de-448c-afa4-7ccdefd721af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835141572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3835141572
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2407116793
Short name T244
Test name
Test status
Simulation time 237613996953 ps
CPU time 440.85 seconds
Started May 09 12:39:25 PM PDT 24
Finished May 09 12:46:52 PM PDT 24
Peak memory 182992 kb
Host smart-d26fc2eb-648b-4b59-9964-0b569535244e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407116793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2407116793
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.592198216
Short name T399
Test name
Test status
Simulation time 301277536809 ps
CPU time 225.59 seconds
Started May 09 12:39:40 PM PDT 24
Finished May 09 12:43:33 PM PDT 24
Peak memory 182980 kb
Host smart-2882a2b0-4037-4786-9438-36bbc81137ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592198216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.592198216
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.974247736
Short name T239
Test name
Test status
Simulation time 108247899698 ps
CPU time 155.36 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:42:24 PM PDT 24
Peak memory 191116 kb
Host smart-b45db9c5-8618-4d9e-bf23-94cd2e2c0b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974247736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.974247736
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.744462544
Short name T362
Test name
Test status
Simulation time 255369498073 ps
CPU time 478.05 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:47:34 PM PDT 24
Peak memory 183044 kb
Host smart-4b295072-42f2-42b1-8fbd-c01af0c42d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744462544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.744462544
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1352433395
Short name T62
Test name
Test status
Simulation time 1936116237810 ps
CPU time 329.9 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:45:10 PM PDT 24
Peak memory 191220 kb
Host smart-b4443cd6-6ec3-4bf7-a8cd-7ef807dc5126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352433395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1352433395
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2760190479
Short name T68
Test name
Test status
Simulation time 274745444287 ps
CPU time 195.65 seconds
Started May 09 12:39:28 PM PDT 24
Finished May 09 12:42:50 PM PDT 24
Peak memory 183004 kb
Host smart-4f8e07c2-8a15-45db-adbd-a9dc42474b48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760190479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2760190479
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3723748338
Short name T380
Test name
Test status
Simulation time 182135020025 ps
CPU time 146.29 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:42:15 PM PDT 24
Peak memory 183036 kb
Host smart-e083802c-4bc7-4731-9cb2-ff70f5050a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723748338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3723748338
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2788332004
Short name T147
Test name
Test status
Simulation time 172733299509 ps
CPU time 133.67 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:41:54 PM PDT 24
Peak memory 191232 kb
Host smart-4ec881e5-6bb9-4ac4-a6d9-f8f61fde1f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788332004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2788332004
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2960497306
Short name T321
Test name
Test status
Simulation time 80488204124 ps
CPU time 120.21 seconds
Started May 09 12:39:36 PM PDT 24
Finished May 09 12:41:44 PM PDT 24
Peak memory 193540 kb
Host smart-dba6ba06-1e2f-4d2e-911b-f95858e7e2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960497306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2960497306
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2186155945
Short name T403
Test name
Test status
Simulation time 79985027 ps
CPU time 0.52 seconds
Started May 09 12:39:43 PM PDT 24
Finished May 09 12:39:51 PM PDT 24
Peak memory 182764 kb
Host smart-4d1e360b-4559-4086-8c5d-e15892b16383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186155945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2186155945
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.647881553
Short name T37
Test name
Test status
Simulation time 12886019276 ps
CPU time 68.87 seconds
Started May 09 12:39:21 PM PDT 24
Finished May 09 12:40:38 PM PDT 24
Peak memory 197672 kb
Host smart-8c3cb235-dae2-41ab-9fb2-8adec0eab0ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647881553 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.647881553
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3809194909
Short name T370
Test name
Test status
Simulation time 175873412766 ps
CPU time 282.91 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:44:31 PM PDT 24
Peak memory 182992 kb
Host smart-6df0561f-9f7b-428a-b8eb-531339976401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809194909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3809194909
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1903567166
Short name T82
Test name
Test status
Simulation time 21660326907 ps
CPU time 172.15 seconds
Started May 09 12:39:38 PM PDT 24
Finished May 09 12:42:38 PM PDT 24
Peak memory 182972 kb
Host smart-97679ca7-cc59-4735-b6dc-16f52a27fb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903567166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1903567166
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.4098790813
Short name T361
Test name
Test status
Simulation time 164711642 ps
CPU time 1.17 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:39:41 PM PDT 24
Peak memory 191164 kb
Host smart-0911e23d-5b5d-4f8c-88c8-66dec93d342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098790813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4098790813
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.622268891
Short name T414
Test name
Test status
Simulation time 635300895876 ps
CPU time 273.77 seconds
Started May 09 12:39:37 PM PDT 24
Finished May 09 12:44:18 PM PDT 24
Peak memory 193960 kb
Host smart-11a46790-6527-4187-b3b3-6e81ef584a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622268891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
622268891
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4190347845
Short name T280
Test name
Test status
Simulation time 1924852217 ps
CPU time 3.37 seconds
Started May 09 12:38:56 PM PDT 24
Finished May 09 12:39:14 PM PDT 24
Peak memory 182828 kb
Host smart-fcdaf891-45bc-4761-aa3c-215d2e2bd425
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190347845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4190347845
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3896127665
Short name T386
Test name
Test status
Simulation time 750074213606 ps
CPU time 160.46 seconds
Started May 09 12:38:55 PM PDT 24
Finished May 09 12:41:50 PM PDT 24
Peak memory 183008 kb
Host smart-747878f6-636b-407d-a2aa-ec5f585ea719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896127665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3896127665
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.202550659
Short name T189
Test name
Test status
Simulation time 72828451912 ps
CPU time 111.11 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:40:58 PM PDT 24
Peak memory 194112 kb
Host smart-be833602-b96c-4ded-bce3-c6a51dd62d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202550659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.202550659
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.3722726564
Short name T313
Test name
Test status
Simulation time 104157399965 ps
CPU time 198.22 seconds
Started May 09 12:39:43 PM PDT 24
Finished May 09 12:43:08 PM PDT 24
Peak memory 183012 kb
Host smart-43140f3d-f627-4701-8482-49b1c4453873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722726564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3722726564
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2624786781
Short name T332
Test name
Test status
Simulation time 94477396437 ps
CPU time 368.66 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:46:04 PM PDT 24
Peak memory 191236 kb
Host smart-30169cb8-a256-46b8-96f3-dbf686ecca35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624786781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2624786781
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.4040912156
Short name T287
Test name
Test status
Simulation time 111356373129 ps
CPU time 188.8 seconds
Started May 09 12:39:44 PM PDT 24
Finished May 09 12:43:00 PM PDT 24
Peak memory 191248 kb
Host smart-63516bed-27b5-4d86-8a50-4b86f4ee8da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040912156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.4040912156
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2381136077
Short name T322
Test name
Test status
Simulation time 59760238845 ps
CPU time 274.93 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:44:14 PM PDT 24
Peak memory 191160 kb
Host smart-28d32c58-a792-4129-a348-adfe2970542e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381136077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2381136077
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1537595707
Short name T260
Test name
Test status
Simulation time 337648896739 ps
CPU time 99.28 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:41:16 PM PDT 24
Peak memory 191500 kb
Host smart-77acae37-6613-4b92-a92c-018efaf14e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537595707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1537595707
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.147403898
Short name T267
Test name
Test status
Simulation time 13422903987 ps
CPU time 64.53 seconds
Started May 09 12:39:20 PM PDT 24
Finished May 09 12:40:32 PM PDT 24
Peak memory 182964 kb
Host smart-2d6db09f-f0dd-4ec2-a087-f4d8db37be02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147403898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.147403898
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.913359567
Short name T142
Test name
Test status
Simulation time 16944572045 ps
CPU time 30.91 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:40:07 PM PDT 24
Peak memory 183040 kb
Host smart-c47e0f40-9937-4e84-805b-4b90cdc1b4dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913359567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.913359567
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3728441024
Short name T175
Test name
Test status
Simulation time 65818731470 ps
CPU time 119.81 seconds
Started May 09 12:39:37 PM PDT 24
Finished May 09 12:41:45 PM PDT 24
Peak memory 191224 kb
Host smart-e928b534-ef5a-488f-b970-082eb2752ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728441024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3728441024
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1897203512
Short name T232
Test name
Test status
Simulation time 135068653002 ps
CPU time 226.43 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:43:01 PM PDT 24
Peak memory 183004 kb
Host smart-aea57c08-19d1-4848-b4e6-aff6c0c959d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897203512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1897203512
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1479605413
Short name T382
Test name
Test status
Simulation time 232015848383 ps
CPU time 87.22 seconds
Started May 09 12:38:57 PM PDT 24
Finished May 09 12:40:38 PM PDT 24
Peak memory 182904 kb
Host smart-74693a68-8801-46f5-85d2-03674ee6e73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479605413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1479605413
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.649790095
Short name T317
Test name
Test status
Simulation time 51883116188 ps
CPU time 87.85 seconds
Started May 09 12:38:56 PM PDT 24
Finished May 09 12:40:38 PM PDT 24
Peak memory 191228 kb
Host smart-dd207800-c105-451b-bb45-5d57a72653c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649790095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.649790095
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3003640366
Short name T378
Test name
Test status
Simulation time 100050896 ps
CPU time 0.95 seconds
Started May 09 12:38:50 PM PDT 24
Finished May 09 12:39:07 PM PDT 24
Peak memory 182852 kb
Host smart-276ddc93-8b0e-41f2-a232-294965138ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003640366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3003640366
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2379608524
Short name T438
Test name
Test status
Simulation time 65281181456 ps
CPU time 1108.73 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:58:10 PM PDT 24
Peak memory 191240 kb
Host smart-53f9e3b3-3385-47f8-88ca-cc6cf7fb041d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379608524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2379608524
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2023879934
Short name T112
Test name
Test status
Simulation time 133364444418 ps
CPU time 223.93 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:43:17 PM PDT 24
Peak memory 191256 kb
Host smart-14bb29d2-f783-48d9-99e7-458fc714727a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023879934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2023879934
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3236447638
Short name T330
Test name
Test status
Simulation time 232971855667 ps
CPU time 116.13 seconds
Started May 09 12:39:36 PM PDT 24
Finished May 09 12:41:40 PM PDT 24
Peak memory 191240 kb
Host smart-ef86196b-0129-45fc-860e-d20a5fe66a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236447638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3236447638
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1625084753
Short name T310
Test name
Test status
Simulation time 139794319539 ps
CPU time 203.18 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:43:00 PM PDT 24
Peak memory 191224 kb
Host smart-85092cf0-1bb7-4262-85b8-314a93c36ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625084753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1625084753
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3772432968
Short name T265
Test name
Test status
Simulation time 547961431211 ps
CPU time 1837.2 seconds
Started May 09 12:39:25 PM PDT 24
Finished May 09 01:10:09 PM PDT 24
Peak memory 191240 kb
Host smart-8037d71c-e6fe-4360-9a9e-7e95230dd945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772432968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3772432968
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1865665517
Short name T329
Test name
Test status
Simulation time 592103128217 ps
CPU time 203.53 seconds
Started May 09 12:39:48 PM PDT 24
Finished May 09 12:43:21 PM PDT 24
Peak memory 191252 kb
Host smart-bbc4c5ff-4eea-4d27-a196-aa9a31597c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865665517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1865665517
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2586342603
Short name T161
Test name
Test status
Simulation time 121329126171 ps
CPU time 213.99 seconds
Started May 09 12:39:41 PM PDT 24
Finished May 09 12:43:22 PM PDT 24
Peak memory 191232 kb
Host smart-a1261898-3e1e-4173-87ea-f9d3feb8a7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586342603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2586342603
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3930322965
Short name T316
Test name
Test status
Simulation time 215546879791 ps
CPU time 351.46 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 12:45:25 PM PDT 24
Peak memory 191264 kb
Host smart-91806c2a-387a-4427-ae0c-0393dc5b1c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930322965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3930322965
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2067570595
Short name T195
Test name
Test status
Simulation time 805304958918 ps
CPU time 613.41 seconds
Started May 09 12:39:45 PM PDT 24
Finished May 09 12:50:07 PM PDT 24
Peak memory 191260 kb
Host smart-dafb03ae-d0e1-4399-a989-cccdf2bf00e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067570595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2067570595
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.4060236481
Short name T85
Test name
Test status
Simulation time 113046355614 ps
CPU time 453.25 seconds
Started May 09 12:39:38 PM PDT 24
Finished May 09 12:47:19 PM PDT 24
Peak memory 191232 kb
Host smart-3c93df2a-1530-4a81-809d-9ed6e8022c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060236481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.4060236481
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3809081709
Short name T449
Test name
Test status
Simulation time 457523132289 ps
CPU time 246.43 seconds
Started May 09 12:38:48 PM PDT 24
Finished May 09 12:43:10 PM PDT 24
Peak memory 183020 kb
Host smart-8d90ab35-b31d-47dc-ae56-8269364a2774
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809081709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3809081709
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1149701043
Short name T437
Test name
Test status
Simulation time 78713299265 ps
CPU time 123.86 seconds
Started May 09 12:38:51 PM PDT 24
Finished May 09 12:41:10 PM PDT 24
Peak memory 182904 kb
Host smart-45409b61-768c-49e7-8439-58004296411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149701043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1149701043
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3754229961
Short name T304
Test name
Test status
Simulation time 414870655967 ps
CPU time 388.57 seconds
Started May 09 12:38:56 PM PDT 24
Finished May 09 12:45:39 PM PDT 24
Peak memory 194448 kb
Host smart-c01ffe47-6a1e-4ba0-b09b-a798cea996d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754229961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3754229961
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1888977353
Short name T327
Test name
Test status
Simulation time 149175161794 ps
CPU time 392.9 seconds
Started May 09 12:38:58 PM PDT 24
Finished May 09 12:45:45 PM PDT 24
Peak memory 183044 kb
Host smart-f0ae2e93-b34b-4452-a747-f8912fd43185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888977353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1888977353
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2157044513
Short name T36
Test name
Test status
Simulation time 268896364620 ps
CPU time 513.28 seconds
Started May 09 12:38:59 PM PDT 24
Finished May 09 12:47:46 PM PDT 24
Peak memory 205840 kb
Host smart-94a9bb47-ff7f-4329-9f67-bac527becbf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157044513 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2157044513
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2174798452
Short name T1
Test name
Test status
Simulation time 1227671248992 ps
CPU time 472.61 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:47:30 PM PDT 24
Peak memory 191264 kb
Host smart-a3e98360-1f4d-4039-bba9-5ecbc694af4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174798452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2174798452
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1313957044
Short name T41
Test name
Test status
Simulation time 58995886170 ps
CPU time 132.42 seconds
Started May 09 12:39:35 PM PDT 24
Finished May 09 12:41:56 PM PDT 24
Peak memory 191248 kb
Host smart-432d22a4-1a5d-410f-878a-d62dfcdab394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313957044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1313957044
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.589639467
Short name T395
Test name
Test status
Simulation time 37304967234 ps
CPU time 63.38 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:40:41 PM PDT 24
Peak memory 183060 kb
Host smart-e4b8766f-52df-4eb9-a603-8886d4e1419d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589639467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.589639467
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2385571394
Short name T281
Test name
Test status
Simulation time 721048745943 ps
CPU time 2113.89 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 01:14:51 PM PDT 24
Peak memory 191136 kb
Host smart-0e5a23ed-d775-436c-b38e-467e801ba2af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385571394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2385571394
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2678022492
Short name T204
Test name
Test status
Simulation time 498884223959 ps
CPU time 623.46 seconds
Started May 09 12:39:42 PM PDT 24
Finished May 09 12:50:12 PM PDT 24
Peak memory 191224 kb
Host smart-ff278df2-9d05-403b-816f-cd39eaa91d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678022492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2678022492
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3847561911
Short name T277
Test name
Test status
Simulation time 13866567851 ps
CPU time 33.94 seconds
Started May 09 12:39:29 PM PDT 24
Finished May 09 12:40:10 PM PDT 24
Peak memory 182940 kb
Host smart-7ecf0f84-af80-4519-ad72-800c71a44d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847561911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3847561911
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1688007051
Short name T199
Test name
Test status
Simulation time 220878302883 ps
CPU time 415.53 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:46:29 PM PDT 24
Peak memory 191140 kb
Host smart-6805234a-6b95-4317-891e-89e56fb90808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688007051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1688007051
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2343757689
Short name T238
Test name
Test status
Simulation time 26238420599 ps
CPU time 176.25 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:42:33 PM PDT 24
Peak memory 193724 kb
Host smart-775b6f3f-efe0-4e36-b11e-e6c9d8efa029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343757689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2343757689
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2982728669
Short name T22
Test name
Test status
Simulation time 31954813602 ps
CPU time 390.84 seconds
Started May 09 12:39:40 PM PDT 24
Finished May 09 12:46:18 PM PDT 24
Peak memory 191248 kb
Host smart-9d6572d5-d5d3-4cab-a7ad-4fb0be87f66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982728669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2982728669
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.860120861
Short name T231
Test name
Test status
Simulation time 3159513621219 ps
CPU time 1479.61 seconds
Started May 09 12:39:23 PM PDT 24
Finished May 09 01:04:10 PM PDT 24
Peak memory 183036 kb
Host smart-26e2d2ad-bfa2-413d-9f46-b309f401be25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860120861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.860120861
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3408273230
Short name T398
Test name
Test status
Simulation time 50981910282 ps
CPU time 76.61 seconds
Started May 09 12:39:07 PM PDT 24
Finished May 09 12:40:35 PM PDT 24
Peak memory 183008 kb
Host smart-1ab05409-4d31-4566-bd03-357636c64007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408273230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3408273230
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.783122663
Short name T440
Test name
Test status
Simulation time 160547441781 ps
CPU time 1039.53 seconds
Started May 09 12:38:58 PM PDT 24
Finished May 09 12:56:31 PM PDT 24
Peak memory 191124 kb
Host smart-a19c53c0-210c-4718-b896-93e775e89d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783122663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.783122663
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.658621454
Short name T236
Test name
Test status
Simulation time 33950056500 ps
CPU time 46.28 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:40:01 PM PDT 24
Peak memory 191216 kb
Host smart-e2f2d358-15ae-4876-9037-d663c83f5e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658621454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.658621454
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3735014313
Short name T377
Test name
Test status
Simulation time 23559072 ps
CPU time 0.54 seconds
Started May 09 12:39:00 PM PDT 24
Finished May 09 12:39:14 PM PDT 24
Peak memory 182832 kb
Host smart-366a8993-e859-45ff-b657-f2965582e0af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735014313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3735014313
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.1388222461
Short name T215
Test name
Test status
Simulation time 167112837287 ps
CPU time 240.79 seconds
Started May 09 12:39:47 PM PDT 24
Finished May 09 12:43:58 PM PDT 24
Peak memory 191224 kb
Host smart-0511bf0e-1455-4cfc-b59a-e9d76c4ab4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388222461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1388222461
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.446850179
Short name T247
Test name
Test status
Simulation time 79502869318 ps
CPU time 116.15 seconds
Started May 09 12:39:37 PM PDT 24
Finished May 09 12:41:41 PM PDT 24
Peak memory 194724 kb
Host smart-545d3ea0-141c-4026-a1cd-d1ae2329ffa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446850179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.446850179
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.956636467
Short name T132
Test name
Test status
Simulation time 48841636074 ps
CPU time 30.97 seconds
Started May 09 12:39:36 PM PDT 24
Finished May 09 12:40:15 PM PDT 24
Peak memory 183056 kb
Host smart-8fc9c212-5395-47de-9ed4-e086bb6d6f77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956636467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.956636467
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3149164136
Short name T138
Test name
Test status
Simulation time 53013647152 ps
CPU time 70.6 seconds
Started May 09 12:39:33 PM PDT 24
Finished May 09 12:40:51 PM PDT 24
Peak memory 191244 kb
Host smart-d01f03a3-2be6-4a10-a609-494bf9332302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149164136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3149164136
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3893294858
Short name T415
Test name
Test status
Simulation time 231218090372 ps
CPU time 51.09 seconds
Started May 09 12:39:49 PM PDT 24
Finished May 09 12:40:51 PM PDT 24
Peak memory 183052 kb
Host smart-dfd7ca07-fb09-47c7-9814-e646b31394e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893294858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3893294858
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1674487554
Short name T348
Test name
Test status
Simulation time 31872459042 ps
CPU time 356.98 seconds
Started May 09 12:39:45 PM PDT 24
Finished May 09 12:45:50 PM PDT 24
Peak memory 183060 kb
Host smart-068955ef-e729-430b-ac13-d23f071ea0ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674487554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1674487554
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.345014643
Short name T173
Test name
Test status
Simulation time 139602588524 ps
CPU time 385.79 seconds
Started May 09 12:39:30 PM PDT 24
Finished May 09 12:46:02 PM PDT 24
Peak memory 191248 kb
Host smart-1bcce76c-9c67-4ded-af9d-2a10e03402ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345014643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.345014643
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2339289149
Short name T207
Test name
Test status
Simulation time 38258101681 ps
CPU time 61.75 seconds
Started May 09 12:39:26 PM PDT 24
Finished May 09 12:40:35 PM PDT 24
Peak memory 183032 kb
Host smart-508453f6-bdc7-4aaf-9173-90d4a50bc559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339289149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2339289149
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.9886086
Short name T191
Test name
Test status
Simulation time 337832340389 ps
CPU time 628.71 seconds
Started May 09 12:39:10 PM PDT 24
Finished May 09 12:49:49 PM PDT 24
Peak memory 183028 kb
Host smart-99abe3ed-3572-4314-a801-d016d42657f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9886086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.r
v_timer_cfg_update_on_fly.9886086
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1978807584
Short name T385
Test name
Test status
Simulation time 58190376577 ps
CPU time 97.66 seconds
Started May 09 12:39:01 PM PDT 24
Finished May 09 12:40:52 PM PDT 24
Peak memory 183004 kb
Host smart-b8e08b99-8b1c-4687-95e8-49492f231c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978807584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1978807584
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3807793620
Short name T194
Test name
Test status
Simulation time 201652472711 ps
CPU time 257.54 seconds
Started May 09 12:39:32 PM PDT 24
Finished May 09 12:43:57 PM PDT 24
Peak memory 191232 kb
Host smart-e7b1039f-fab3-4f0d-a634-23eafbed979c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807793620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3807793620
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1331210556
Short name T409
Test name
Test status
Simulation time 60200644679 ps
CPU time 122.76 seconds
Started May 09 12:39:12 PM PDT 24
Finished May 09 12:41:24 PM PDT 24
Peak memory 191220 kb
Host smart-4fb15f5c-30e2-4984-b72c-f1356c0318eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331210556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1331210556
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1197694585
Short name T119
Test name
Test status
Simulation time 573684238062 ps
CPU time 784.27 seconds
Started May 09 12:39:05 PM PDT 24
Finished May 09 12:52:22 PM PDT 24
Peak memory 195020 kb
Host smart-703db24c-7362-4b5d-bf24-eb62e7bcc215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197694585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1197694585
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2892331693
Short name T35
Test name
Test status
Simulation time 52041530638 ps
CPU time 347.64 seconds
Started May 09 12:39:34 PM PDT 24
Finished May 09 12:45:29 PM PDT 24
Peak memory 205772 kb
Host smart-c98e726d-417c-49af-bc64-86f766e26352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892331693 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2892331693
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2353303315
Short name T115
Test name
Test status
Simulation time 211415408619 ps
CPU time 632.37 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:50:27 PM PDT 24
Peak memory 191244 kb
Host smart-3267abdd-a87a-4473-8f07-2f1fab30a7b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353303315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2353303315
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3381052470
Short name T326
Test name
Test status
Simulation time 38308616753 ps
CPU time 284.01 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:44:39 PM PDT 24
Peak memory 191172 kb
Host smart-09baf126-8532-4adc-bc92-53aa9ed873a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381052470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3381052470
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3819486760
Short name T417
Test name
Test status
Simulation time 88013969087 ps
CPU time 70.03 seconds
Started May 09 12:39:44 PM PDT 24
Finished May 09 12:41:02 PM PDT 24
Peak memory 183036 kb
Host smart-c4421197-7f60-4ee3-812d-26392a613598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819486760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3819486760
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1382379631
Short name T203
Test name
Test status
Simulation time 62904518227 ps
CPU time 147.69 seconds
Started May 09 12:39:27 PM PDT 24
Finished May 09 12:42:02 PM PDT 24
Peak memory 191172 kb
Host smart-8410e396-1d2f-4acd-bc89-14d86d6fa110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382379631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1382379631
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3953254574
Short name T338
Test name
Test status
Simulation time 26149318760 ps
CPU time 50.41 seconds
Started May 09 12:39:39 PM PDT 24
Finished May 09 12:40:37 PM PDT 24
Peak memory 182968 kb
Host smart-b278e4dc-8013-48f3-a382-7451b153f1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953254574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3953254574
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1026623700
Short name T113
Test name
Test status
Simulation time 350785014940 ps
CPU time 342.32 seconds
Started May 09 12:39:38 PM PDT 24
Finished May 09 12:45:28 PM PDT 24
Peak memory 191172 kb
Host smart-4d02dfd3-5161-40fb-98a7-a0e81ca23ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026623700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1026623700
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3151269751
Short name T353
Test name
Test status
Simulation time 63006441026 ps
CPU time 109.84 seconds
Started May 09 12:39:46 PM PDT 24
Finished May 09 12:41:45 PM PDT 24
Peak memory 182936 kb
Host smart-b2533a76-a785-43f8-80da-dc952171ff1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151269751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3151269751
Directory /workspace/98.rv_timer_random/latest
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