Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 576
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T505 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4080993986 May 12 01:14:44 PM PDT 24 May 12 01:14:45 PM PDT 24 14050756 ps
T506 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.274211463 May 12 01:15:01 PM PDT 24 May 12 01:15:02 PM PDT 24 14973888 ps
T507 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2672017032 May 12 01:15:04 PM PDT 24 May 12 01:15:05 PM PDT 24 71861320 ps
T508 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1227585201 May 12 01:14:54 PM PDT 24 May 12 01:14:56 PM PDT 24 54775074 ps
T509 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2264194337 May 12 01:14:43 PM PDT 24 May 12 01:14:44 PM PDT 24 144204401 ps
T510 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.495443100 May 12 01:14:55 PM PDT 24 May 12 01:14:55 PM PDT 24 13741048 ps
T511 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4214116422 May 12 01:14:36 PM PDT 24 May 12 01:14:38 PM PDT 24 248347835 ps
T512 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3415131778 May 12 01:14:31 PM PDT 24 May 12 01:14:32 PM PDT 24 35527267 ps
T513 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1212419081 May 12 01:14:39 PM PDT 24 May 12 01:14:39 PM PDT 24 43844048 ps
T514 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1208084177 May 12 01:14:39 PM PDT 24 May 12 01:14:41 PM PDT 24 269381784 ps
T515 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3050442871 May 12 01:14:39 PM PDT 24 May 12 01:14:41 PM PDT 24 291689695 ps
T516 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1147408214 May 12 01:14:46 PM PDT 24 May 12 01:14:49 PM PDT 24 219338133 ps
T517 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.935605069 May 12 01:14:43 PM PDT 24 May 12 01:14:44 PM PDT 24 52804447 ps
T518 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.588220472 May 12 01:15:02 PM PDT 24 May 12 01:15:03 PM PDT 24 42721860 ps
T81 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3737724860 May 12 01:14:34 PM PDT 24 May 12 01:14:35 PM PDT 24 14708323 ps
T519 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3243103663 May 12 01:15:03 PM PDT 24 May 12 01:15:04 PM PDT 24 36182940 ps
T520 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2256924026 May 12 01:14:24 PM PDT 24 May 12 01:14:25 PM PDT 24 42020159 ps
T521 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.179107230 May 12 01:15:03 PM PDT 24 May 12 01:15:04 PM PDT 24 20344690 ps
T522 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.744848912 May 12 01:14:48 PM PDT 24 May 12 01:14:49 PM PDT 24 30215221 ps
T523 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.161100748 May 12 01:14:36 PM PDT 24 May 12 01:14:37 PM PDT 24 103441200 ps
T524 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.713941388 May 12 01:14:51 PM PDT 24 May 12 01:14:52 PM PDT 24 141353926 ps
T525 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3583933720 May 12 01:14:58 PM PDT 24 May 12 01:14:59 PM PDT 24 61498714 ps
T526 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1727100163 May 12 01:14:58 PM PDT 24 May 12 01:15:00 PM PDT 24 38279147 ps
T527 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2961827753 May 12 01:15:02 PM PDT 24 May 12 01:15:03 PM PDT 24 11771954 ps
T528 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.406914506 May 12 01:14:26 PM PDT 24 May 12 01:14:30 PM PDT 24 277506153 ps
T529 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1653152439 May 12 01:14:54 PM PDT 24 May 12 01:14:55 PM PDT 24 25472122 ps
T530 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3565574744 May 12 01:14:45 PM PDT 24 May 12 01:14:47 PM PDT 24 390638823 ps
T531 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3335506093 May 12 01:14:58 PM PDT 24 May 12 01:14:59 PM PDT 24 39458220 ps
T532 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2040088611 May 12 01:14:34 PM PDT 24 May 12 01:14:36 PM PDT 24 157217571 ps
T82 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.935908599 May 12 01:14:57 PM PDT 24 May 12 01:14:58 PM PDT 24 31403665 ps
T533 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.370810101 May 12 01:14:31 PM PDT 24 May 12 01:14:33 PM PDT 24 18898342 ps
T534 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3763715575 May 12 01:14:49 PM PDT 24 May 12 01:14:50 PM PDT 24 15617199 ps
T535 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3540231839 May 12 01:15:02 PM PDT 24 May 12 01:15:03 PM PDT 24 115138395 ps
T536 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2733778502 May 12 01:14:58 PM PDT 24 May 12 01:14:59 PM PDT 24 17541317 ps
T537 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2452300499 May 12 01:14:45 PM PDT 24 May 12 01:14:46 PM PDT 24 59613308 ps
T538 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2573044688 May 12 01:14:30 PM PDT 24 May 12 01:14:31 PM PDT 24 31464480 ps
T539 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2417127901 May 12 01:14:58 PM PDT 24 May 12 01:14:59 PM PDT 24 21418787 ps
T540 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1193226352 May 12 01:15:05 PM PDT 24 May 12 01:15:06 PM PDT 24 12425128 ps
T541 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2804754690 May 12 01:14:59 PM PDT 24 May 12 01:15:00 PM PDT 24 82227448 ps
T542 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2316254681 May 12 01:14:43 PM PDT 24 May 12 01:14:44 PM PDT 24 227576794 ps
T543 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.78140490 May 12 01:14:43 PM PDT 24 May 12 01:14:44 PM PDT 24 48504347 ps
T544 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2074991451 May 12 01:15:02 PM PDT 24 May 12 01:15:03 PM PDT 24 54933094 ps
T545 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3106606558 May 12 01:14:55 PM PDT 24 May 12 01:14:57 PM PDT 24 132712040 ps
T546 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3136079304 May 12 01:15:09 PM PDT 24 May 12 01:15:10 PM PDT 24 15950695 ps
T547 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.770681886 May 12 01:14:39 PM PDT 24 May 12 01:14:43 PM PDT 24 500059673 ps
T83 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3673485314 May 12 01:14:27 PM PDT 24 May 12 01:14:28 PM PDT 24 13219938 ps
T548 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1778422011 May 12 01:14:57 PM PDT 24 May 12 01:14:59 PM PDT 24 169003908 ps
T549 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2509121038 May 12 01:14:53 PM PDT 24 May 12 01:14:55 PM PDT 24 38347879 ps
T550 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3966309409 May 12 01:14:33 PM PDT 24 May 12 01:14:36 PM PDT 24 1219181881 ps
T551 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3897667882 May 12 01:14:53 PM PDT 24 May 12 01:14:55 PM PDT 24 235636183 ps
T552 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1616843168 May 12 01:14:43 PM PDT 24 May 12 01:14:45 PM PDT 24 92940600 ps
T553 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2945280667 May 12 01:14:44 PM PDT 24 May 12 01:14:46 PM PDT 24 289353130 ps
T554 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2005104035 May 12 01:14:39 PM PDT 24 May 12 01:14:40 PM PDT 24 25414427 ps
T555 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3940850606 May 12 01:14:58 PM PDT 24 May 12 01:15:00 PM PDT 24 61928736 ps
T556 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3733355562 May 12 01:14:34 PM PDT 24 May 12 01:14:36 PM PDT 24 133807659 ps
T557 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3277248359 May 12 01:15:01 PM PDT 24 May 12 01:15:04 PM PDT 24 633522596 ps
T558 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1557940170 May 12 01:14:49 PM PDT 24 May 12 01:14:50 PM PDT 24 43428539 ps
T559 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2410820081 May 12 01:14:25 PM PDT 24 May 12 01:14:26 PM PDT 24 74053864 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1918683872 May 12 01:14:37 PM PDT 24 May 12 01:14:38 PM PDT 24 21897500 ps
T561 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.116415236 May 12 01:14:53 PM PDT 24 May 12 01:14:54 PM PDT 24 48803730 ps
T562 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3639255009 May 12 01:14:47 PM PDT 24 May 12 01:14:51 PM PDT 24 57179414 ps
T563 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2377836623 May 12 01:15:02 PM PDT 24 May 12 01:15:03 PM PDT 24 13972234 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2741397431 May 12 01:14:35 PM PDT 24 May 12 01:14:36 PM PDT 24 51284187 ps
T565 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.736658471 May 12 01:14:48 PM PDT 24 May 12 01:14:50 PM PDT 24 96475652 ps
T566 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1345972155 May 12 01:14:46 PM PDT 24 May 12 01:14:47 PM PDT 24 406720876 ps
T85 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.394891665 May 12 01:14:29 PM PDT 24 May 12 01:14:33 PM PDT 24 1633883221 ps
T567 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2028633222 May 12 01:14:47 PM PDT 24 May 12 01:14:48 PM PDT 24 19288173 ps
T568 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2092020246 May 12 01:14:52 PM PDT 24 May 12 01:14:53 PM PDT 24 107446384 ps
T569 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2751259960 May 12 01:14:41 PM PDT 24 May 12 01:14:44 PM PDT 24 965551127 ps
T570 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2977908304 May 12 01:14:54 PM PDT 24 May 12 01:14:56 PM PDT 24 348381699 ps
T571 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1916189218 May 12 01:15:06 PM PDT 24 May 12 01:15:07 PM PDT 24 17387543 ps
T572 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1466345516 May 12 01:14:56 PM PDT 24 May 12 01:14:57 PM PDT 24 16205160 ps
T573 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.253664434 May 12 01:14:36 PM PDT 24 May 12 01:14:37 PM PDT 24 31959897 ps
T574 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3030133254 May 12 01:14:53 PM PDT 24 May 12 01:14:54 PM PDT 24 63384032 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.546515473 May 12 01:14:28 PM PDT 24 May 12 01:14:30 PM PDT 24 294828163 ps
T576 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1400082471 May 12 01:14:32 PM PDT 24 May 12 01:14:33 PM PDT 24 38460130 ps

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1493743437
Short name T3
Test name
Test status
Simulation time 416168760462 ps
CPU time 217.66 seconds
Started May 12 12:26:56 PM PDT 24
Finished May 12 12:30:35 PM PDT 24
Peak memory 182784 kb
Host smart-786ea868-6c42-4074-b5dd-cc70b95363d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493743437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1493743437
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3138189968
Short name T17
Test name
Test status
Simulation time 82863198922 ps
CPU time 505.45 seconds
Started May 12 12:27:04 PM PDT 24
Finished May 12 12:35:30 PM PDT 24
Peak memory 205652 kb
Host smart-fad1703e-3cff-41bd-bc61-05fd284145aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138189968 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3138189968
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.4045825409
Short name T103
Test name
Test status
Simulation time 3483759631886 ps
CPU time 2456.85 seconds
Started May 12 12:27:19 PM PDT 24
Finished May 12 01:08:17 PM PDT 24
Peak memory 191080 kb
Host smart-b0ad1aed-2652-4aa2-aa07-c04cbda554ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045825409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.4045825409
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1533814173
Short name T26
Test name
Test status
Simulation time 2777343182453 ps
CPU time 1976.16 seconds
Started May 12 12:27:21 PM PDT 24
Finished May 12 01:00:18 PM PDT 24
Peak memory 190960 kb
Host smart-580e7515-f43b-4b8a-a5dc-1acb7391618e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533814173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1533814173
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2499859502
Short name T19
Test name
Test status
Simulation time 528147025 ps
CPU time 0.88 seconds
Started May 12 12:27:12 PM PDT 24
Finished May 12 12:27:13 PM PDT 24
Peak memory 213720 kb
Host smart-c2cc1d5b-5f84-426b-a790-957fee401a1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499859502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2499859502
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3262165433
Short name T113
Test name
Test status
Simulation time 3264021569592 ps
CPU time 4964.44 seconds
Started May 12 12:26:12 PM PDT 24
Finished May 12 01:48:58 PM PDT 24
Peak memory 193064 kb
Host smart-bb46e66a-7ee0-4e10-a2bb-f440a61bbdba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262165433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3262165433
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_random.3711602964
Short name T15
Test name
Test status
Simulation time 291365502023 ps
CPU time 784.66 seconds
Started May 12 12:27:19 PM PDT 24
Finished May 12 12:40:25 PM PDT 24
Peak memory 190976 kb
Host smart-04fba8f7-61d1-43e8-a6c9-40e404c0f5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711602964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3711602964
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2226156795
Short name T139
Test name
Test status
Simulation time 2247895398515 ps
CPU time 1392.56 seconds
Started May 12 12:27:22 PM PDT 24
Finished May 12 12:50:35 PM PDT 24
Peak memory 190952 kb
Host smart-22f76eea-ed96-4702-ab73-787166a4b544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226156795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2226156795
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4097828043
Short name T104
Test name
Test status
Simulation time 1315577742007 ps
CPU time 1593.18 seconds
Started May 12 12:27:11 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 194888 kb
Host smart-836eb1f2-c6cf-4607-a9df-676cab5073ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097828043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4097828043
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2803752582
Short name T180
Test name
Test status
Simulation time 5844037736754 ps
CPU time 6225.91 seconds
Started May 12 12:27:20 PM PDT 24
Finished May 12 02:11:08 PM PDT 24
Peak memory 195404 kb
Host smart-b2e24446-1e84-45ab-a60a-6b76b5c09459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803752582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2803752582
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1723874676
Short name T32
Test name
Test status
Simulation time 162344504 ps
CPU time 0.8 seconds
Started May 12 01:14:50 PM PDT 24
Finished May 12 01:14:51 PM PDT 24
Peak memory 192880 kb
Host smart-51446519-4cc7-40de-8b04-d68f44b0039a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723874676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1723874676
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1877672123
Short name T68
Test name
Test status
Simulation time 676433572431 ps
CPU time 1724.34 seconds
Started May 12 12:26:06 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 190732 kb
Host smart-8183a6b9-db9f-4da6-b741-24f9a00f8dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877672123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1877672123
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3870441936
Short name T211
Test name
Test status
Simulation time 704829983185 ps
CPU time 2357.16 seconds
Started May 12 12:26:45 PM PDT 24
Finished May 12 01:06:03 PM PDT 24
Peak memory 190932 kb
Host smart-2a0563e6-3d01-4c4f-936d-20830ae21637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870441936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3870441936
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3301947894
Short name T185
Test name
Test status
Simulation time 785082831764 ps
CPU time 466.34 seconds
Started May 12 12:26:46 PM PDT 24
Finished May 12 12:34:33 PM PDT 24
Peak memory 191416 kb
Host smart-06145a52-bf27-4b5c-9b54-58869c52c7e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301947894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3301947894
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.152376132
Short name T231
Test name
Test status
Simulation time 1657526549428 ps
CPU time 1677.94 seconds
Started May 12 12:26:35 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 189708 kb
Host smart-58cffedc-c293-4e30-9f3e-d23889c95b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152376132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
152376132
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_random.957407999
Short name T8
Test name
Test status
Simulation time 224811216789 ps
CPU time 207.64 seconds
Started May 12 12:22:59 PM PDT 24
Finished May 12 12:26:27 PM PDT 24
Peak memory 190980 kb
Host smart-958fa426-447d-4ffc-9848-84615bbcf67d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957407999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.957407999
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3673485314
Short name T83
Test name
Test status
Simulation time 13219938 ps
CPU time 0.56 seconds
Started May 12 01:14:27 PM PDT 24
Finished May 12 01:14:28 PM PDT 24
Peak memory 182772 kb
Host smart-eaf18e21-b6e8-4a23-aee9-a23ff672e817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673485314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3673485314
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/17.rv_timer_random.1363791113
Short name T303
Test name
Test status
Simulation time 173909445840 ps
CPU time 484.41 seconds
Started May 12 12:26:40 PM PDT 24
Finished May 12 12:34:45 PM PDT 24
Peak memory 194568 kb
Host smart-d6d29b8a-7c8d-475e-93b6-4fd426db3e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363791113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1363791113
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1192827687
Short name T118
Test name
Test status
Simulation time 95072376802 ps
CPU time 332.16 seconds
Started May 12 12:28:08 PM PDT 24
Finished May 12 12:33:42 PM PDT 24
Peak memory 191000 kb
Host smart-15db4305-5da8-4a34-9b64-250f438498ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192827687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1192827687
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4003982560
Short name T154
Test name
Test status
Simulation time 1296913457731 ps
CPU time 937.46 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:43:02 PM PDT 24
Peak memory 191004 kb
Host smart-e64eb71b-a491-406d-bca7-0c72004e7bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003982560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4003982560
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2936131229
Short name T171
Test name
Test status
Simulation time 3504050039741 ps
CPU time 2006.99 seconds
Started May 12 12:26:45 PM PDT 24
Finished May 12 01:00:13 PM PDT 24
Peak memory 196344 kb
Host smart-e056e4d2-61bc-4b75-a4fa-b695bf2880aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936131229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2936131229
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.2007907504
Short name T221
Test name
Test status
Simulation time 72610172741 ps
CPU time 126.06 seconds
Started May 12 12:27:52 PM PDT 24
Finished May 12 12:30:00 PM PDT 24
Peak memory 190964 kb
Host smart-99f7f6a5-bc76-4380-bf6c-7f4222af4604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007907504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2007907504
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.356630841
Short name T179
Test name
Test status
Simulation time 407993431325 ps
CPU time 297.59 seconds
Started May 12 12:27:38 PM PDT 24
Finished May 12 12:32:36 PM PDT 24
Peak memory 190972 kb
Host smart-5fbe3a72-9750-4973-9259-6f7b17d6fe47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356630841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.356630841
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1872082549
Short name T199
Test name
Test status
Simulation time 1153881278731 ps
CPU time 974.34 seconds
Started May 12 12:27:08 PM PDT 24
Finished May 12 12:43:23 PM PDT 24
Peak memory 191080 kb
Host smart-57b3bfee-1d53-4d85-9a4c-516729739aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872082549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1872082549
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random.3015109887
Short name T52
Test name
Test status
Simulation time 266002321286 ps
CPU time 231.35 seconds
Started May 12 12:27:15 PM PDT 24
Finished May 12 12:31:08 PM PDT 24
Peak memory 191448 kb
Host smart-bd74c85f-78a4-4d38-9d77-28163c005578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015109887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3015109887
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1766173619
Short name T133
Test name
Test status
Simulation time 142840287223 ps
CPU time 391.7 seconds
Started May 12 12:27:50 PM PDT 24
Finished May 12 12:34:23 PM PDT 24
Peak memory 194444 kb
Host smart-3e2e169b-e565-4671-a560-967cdb8f92bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766173619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1766173619
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2008231096
Short name T111
Test name
Test status
Simulation time 303826823490 ps
CPU time 836.49 seconds
Started May 12 12:27:33 PM PDT 24
Finished May 12 12:41:30 PM PDT 24
Peak memory 191032 kb
Host smart-5159663a-12de-4a9b-be50-f46aaa9bc63e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008231096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2008231096
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.918847911
Short name T308
Test name
Test status
Simulation time 149219348419 ps
CPU time 505.67 seconds
Started May 12 12:27:36 PM PDT 24
Finished May 12 12:36:02 PM PDT 24
Peak memory 190972 kb
Host smart-d18264e6-d6bf-4f76-b49f-8525a6869510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918847911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.918847911
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.456871514
Short name T181
Test name
Test status
Simulation time 759091709566 ps
CPU time 882.28 seconds
Started May 12 12:26:59 PM PDT 24
Finished May 12 12:41:42 PM PDT 24
Peak memory 190968 kb
Host smart-d6e075fb-2d52-444c-99b7-41f4e8949284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456871514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
456871514
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.3684959264
Short name T172
Test name
Test status
Simulation time 110904684535 ps
CPU time 1133.83 seconds
Started May 12 12:27:50 PM PDT 24
Finished May 12 12:46:46 PM PDT 24
Peak memory 190964 kb
Host smart-3143109e-a976-49a5-8349-3ae5c761488a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684959264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3684959264
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.386703980
Short name T162
Test name
Test status
Simulation time 1478814074471 ps
CPU time 869.49 seconds
Started May 12 12:27:50 PM PDT 24
Finished May 12 12:42:20 PM PDT 24
Peak memory 191000 kb
Host smart-0d8818f6-ee4c-4a8b-85e2-f0f3047fbff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386703980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.386703980
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3760058926
Short name T134
Test name
Test status
Simulation time 2274278378585 ps
CPU time 3960.63 seconds
Started May 12 12:26:55 PM PDT 24
Finished May 12 01:32:58 PM PDT 24
Peak memory 195908 kb
Host smart-b8ea8e7b-9138-4a62-a374-53b75f66b15d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760058926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3760058926
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2527283858
Short name T151
Test name
Test status
Simulation time 208286603807 ps
CPU time 318.54 seconds
Started May 12 12:27:04 PM PDT 24
Finished May 12 12:32:24 PM PDT 24
Peak memory 194660 kb
Host smart-3b03da4e-cc26-467d-980e-97537052caf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527283858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2527283858
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.2988157474
Short name T261
Test name
Test status
Simulation time 126770415773 ps
CPU time 547.88 seconds
Started May 12 12:26:44 PM PDT 24
Finished May 12 12:35:54 PM PDT 24
Peak memory 190648 kb
Host smart-19b79b56-030f-4817-b4a7-b69def25658c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988157474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2988157474
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.344235154
Short name T69
Test name
Test status
Simulation time 436818989877 ps
CPU time 691.24 seconds
Started May 12 12:22:03 PM PDT 24
Finished May 12 12:33:34 PM PDT 24
Peak memory 191364 kb
Host smart-77e6d0e5-7691-4a99-8be3-235f5f026a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344235154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.344235154
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/97.rv_timer_random.1329387048
Short name T286
Test name
Test status
Simulation time 129755052549 ps
CPU time 203.72 seconds
Started May 12 12:27:32 PM PDT 24
Finished May 12 12:30:57 PM PDT 24
Peak memory 191004 kb
Host smart-ab33afd9-70f1-4b8f-bcb1-35d9b4800619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329387048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1329387048
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3776640121
Short name T102
Test name
Test status
Simulation time 717991861630 ps
CPU time 1993.6 seconds
Started May 12 12:21:45 PM PDT 24
Finished May 12 12:54:59 PM PDT 24
Peak memory 191000 kb
Host smart-d913967c-6207-4904-8156-6ac7cd4af3f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776640121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3776640121
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/115.rv_timer_random.3720182814
Short name T419
Test name
Test status
Simulation time 128113625692 ps
CPU time 66.98 seconds
Started May 12 12:27:39 PM PDT 24
Finished May 12 12:28:47 PM PDT 24
Peak memory 190972 kb
Host smart-e07b6d21-61f7-4a28-9159-9d2d4b823690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720182814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3720182814
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.549165056
Short name T269
Test name
Test status
Simulation time 348501263884 ps
CPU time 194.26 seconds
Started May 12 12:27:38 PM PDT 24
Finished May 12 12:30:53 PM PDT 24
Peak memory 190984 kb
Host smart-0d29f9a5-770d-42b9-a106-3f4cb2901be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549165056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.549165056
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.926976640
Short name T247
Test name
Test status
Simulation time 617068338779 ps
CPU time 1317.22 seconds
Started May 12 12:26:44 PM PDT 24
Finished May 12 12:48:43 PM PDT 24
Peak memory 190104 kb
Host smart-d4562dad-4852-476e-a71a-bf5aa67b395b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926976640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
926976640
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/199.rv_timer_random.3858667921
Short name T147
Test name
Test status
Simulation time 278978400915 ps
CPU time 260.65 seconds
Started May 12 12:27:54 PM PDT 24
Finished May 12 12:32:16 PM PDT 24
Peak memory 190988 kb
Host smart-ac51d332-8495-4c20-b1dc-fa1f2cea9399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858667921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3858667921
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.596808343
Short name T109
Test name
Test status
Simulation time 681928583587 ps
CPU time 426.58 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:34:35 PM PDT 24
Peak memory 190968 kb
Host smart-ad3d7bd8-3f2e-42c4-8d0c-dfbe0aa3c889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596808343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.596808343
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3235168040
Short name T322
Test name
Test status
Simulation time 271211407436 ps
CPU time 269.11 seconds
Started May 12 12:27:44 PM PDT 24
Finished May 12 12:32:14 PM PDT 24
Peak memory 190976 kb
Host smart-dd48ac7c-3756-4c26-8b34-86e8b13b8540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235168040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3235168040
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1010898884
Short name T203
Test name
Test status
Simulation time 194931563866 ps
CPU time 259.56 seconds
Started May 12 12:27:50 PM PDT 24
Finished May 12 12:32:10 PM PDT 24
Peak memory 194152 kb
Host smart-246e8b8e-7bba-4ac9-a333-e721b89049cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010898884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1010898884
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.4277426306
Short name T176
Test name
Test status
Simulation time 153364138707 ps
CPU time 74.68 seconds
Started May 12 12:27:47 PM PDT 24
Finished May 12 12:29:02 PM PDT 24
Peak memory 191004 kb
Host smart-c65bd159-6c7c-4795-831a-bb2c2acfa1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277426306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.4277426306
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4087446582
Short name T290
Test name
Test status
Simulation time 623726990751 ps
CPU time 343.69 seconds
Started May 12 12:28:00 PM PDT 24
Finished May 12 12:33:46 PM PDT 24
Peak memory 190956 kb
Host smart-273c81b6-52a0-43ed-86ba-1eac654c3034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087446582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4087446582
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1796512310
Short name T282
Test name
Test status
Simulation time 601145022007 ps
CPU time 312.35 seconds
Started May 12 12:26:42 PM PDT 24
Finished May 12 12:31:55 PM PDT 24
Peak memory 182812 kb
Host smart-217113ce-7de4-455d-af3c-034e23df7082
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796512310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1796512310
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.3468444103
Short name T274
Test name
Test status
Simulation time 2523096120007 ps
CPU time 847.54 seconds
Started May 12 12:26:57 PM PDT 24
Finished May 12 12:41:06 PM PDT 24
Peak memory 190904 kb
Host smart-60916117-840e-4f53-93c4-0c0fc9c2aee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468444103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3468444103
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.1263401399
Short name T324
Test name
Test status
Simulation time 95574874406 ps
CPU time 543.72 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:36:19 PM PDT 24
Peak memory 190992 kb
Host smart-6db6eded-91f9-445e-abda-bacd6313bc5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263401399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1263401399
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.2720473280
Short name T277
Test name
Test status
Simulation time 132656260462 ps
CPU time 914.19 seconds
Started May 12 12:27:03 PM PDT 24
Finished May 12 12:42:18 PM PDT 24
Peak memory 190932 kb
Host smart-ea316d66-53ac-48e4-a526-e1417686557c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720473280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2720473280
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random.1727240362
Short name T301
Test name
Test status
Simulation time 604268054470 ps
CPU time 637.05 seconds
Started May 12 12:28:07 PM PDT 24
Finished May 12 12:38:45 PM PDT 24
Peak memory 194836 kb
Host smart-28f0e199-4f19-448f-af5a-9a207d66d636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727240362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1727240362
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2292130855
Short name T98
Test name
Test status
Simulation time 686899403402 ps
CPU time 983.4 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:42:29 PM PDT 24
Peak memory 189928 kb
Host smart-0327f8c3-0f7b-45ad-aa05-9e482c2a278e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292130855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2292130855
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2794158890
Short name T87
Test name
Test status
Simulation time 16190525 ps
CPU time 0.6 seconds
Started May 12 01:14:47 PM PDT 24
Finished May 12 01:14:49 PM PDT 24
Peak memory 191548 kb
Host smart-45f3f73f-9d8c-4da2-a58d-c3d4eb1a1622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794158890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2794158890
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2988129309
Short name T34
Test name
Test status
Simulation time 385011937 ps
CPU time 1.11 seconds
Started May 12 01:14:48 PM PDT 24
Finished May 12 01:14:50 PM PDT 24
Peak memory 195088 kb
Host smart-57910a11-df5c-407f-8b71-0fd62333ce88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988129309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2988129309
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/103.rv_timer_random.2666277047
Short name T252
Test name
Test status
Simulation time 137703386251 ps
CPU time 227.96 seconds
Started May 12 12:27:36 PM PDT 24
Finished May 12 12:31:24 PM PDT 24
Peak memory 190948 kb
Host smart-dd53f4dc-8b7c-4269-b2c2-dc8bf94a2bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666277047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2666277047
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.773569247
Short name T333
Test name
Test status
Simulation time 37006321239 ps
CPU time 21.16 seconds
Started May 12 12:27:32 PM PDT 24
Finished May 12 12:27:54 PM PDT 24
Peak memory 182808 kb
Host smart-13c1b8fa-b6d9-423b-9c70-786941632546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773569247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.773569247
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1116019088
Short name T51
Test name
Test status
Simulation time 46189080293 ps
CPU time 41.51 seconds
Started May 12 12:27:31 PM PDT 24
Finished May 12 12:28:13 PM PDT 24
Peak memory 190972 kb
Host smart-070d60dd-ca6d-475b-93e8-263e0ab33a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116019088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1116019088
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.912163347
Short name T262
Test name
Test status
Simulation time 142064905901 ps
CPU time 609.95 seconds
Started May 12 12:27:35 PM PDT 24
Finished May 12 12:37:46 PM PDT 24
Peak memory 190988 kb
Host smart-a9519817-69a7-4359-9a39-955ce759569d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912163347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.912163347
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2155274511
Short name T255
Test name
Test status
Simulation time 161501657115 ps
CPU time 58.81 seconds
Started May 12 12:27:31 PM PDT 24
Finished May 12 12:28:30 PM PDT 24
Peak memory 182780 kb
Host smart-e6e62227-c398-4bc8-9678-9fe2ff3c18d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155274511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2155274511
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1189221194
Short name T271
Test name
Test status
Simulation time 42166395712 ps
CPU time 1467.21 seconds
Started May 12 12:27:45 PM PDT 24
Finished May 12 12:52:13 PM PDT 24
Peak memory 182776 kb
Host smart-61f4952e-d4e1-4ed7-9638-988cfc01de9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189221194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1189221194
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1135006355
Short name T298
Test name
Test status
Simulation time 245801503022 ps
CPU time 215.6 seconds
Started May 12 12:27:30 PM PDT 24
Finished May 12 12:31:06 PM PDT 24
Peak memory 190900 kb
Host smart-26ad10dc-3fce-4c66-9bf4-40834ea264f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135006355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1135006355
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.562218747
Short name T190
Test name
Test status
Simulation time 67328994555 ps
CPU time 101.25 seconds
Started May 12 12:27:48 PM PDT 24
Finished May 12 12:29:30 PM PDT 24
Peak memory 190976 kb
Host smart-95ec0ea6-df4d-4bf4-84c8-b557273f690d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562218747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.562218747
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3572063478
Short name T216
Test name
Test status
Simulation time 315605978654 ps
CPU time 590.82 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:37:51 PM PDT 24
Peak memory 182760 kb
Host smart-d3d57a85-951b-443a-8817-115cc1461bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572063478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3572063478
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1342880189
Short name T288
Test name
Test status
Simulation time 616734399291 ps
CPU time 352.41 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:33:52 PM PDT 24
Peak memory 190988 kb
Host smart-b882b981-9512-4934-80b4-2a8a11750819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342880189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1342880189
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2330427820
Short name T248
Test name
Test status
Simulation time 58111656886 ps
CPU time 88.94 seconds
Started May 12 12:26:47 PM PDT 24
Finished May 12 12:28:17 PM PDT 24
Peak memory 194620 kb
Host smart-a2fbb019-419e-4450-b0cb-32651fec5b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330427820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2330427820
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_random.400948811
Short name T249
Test name
Test status
Simulation time 655574085820 ps
CPU time 236.05 seconds
Started May 12 12:27:13 PM PDT 24
Finished May 12 12:31:11 PM PDT 24
Peak memory 190988 kb
Host smart-0b479875-0ec8-4d9c-81eb-6fd4f6a47666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400948811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.400948811
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.860746286
Short name T209
Test name
Test status
Simulation time 18587819463 ps
CPU time 31.6 seconds
Started May 12 12:27:02 PM PDT 24
Finished May 12 12:27:34 PM PDT 24
Peak memory 182784 kb
Host smart-57deddac-effd-4122-8bb0-32a93603a403
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860746286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.860746286
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1224226042
Short name T196
Test name
Test status
Simulation time 279422298416 ps
CPU time 157.45 seconds
Started May 12 12:28:05 PM PDT 24
Finished May 12 12:30:44 PM PDT 24
Peak memory 190972 kb
Host smart-259b293d-6f95-425c-bd82-048907655615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224226042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1224226042
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.80010110
Short name T215
Test name
Test status
Simulation time 129203605691 ps
CPU time 74.02 seconds
Started May 12 12:25:01 PM PDT 24
Finished May 12 12:26:16 PM PDT 24
Peak memory 183228 kb
Host smart-b843192f-5be3-40bb-8e39-fc282e98554a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80010110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
rv_timer_cfg_update_on_fly.80010110
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4178070720
Short name T163
Test name
Test status
Simulation time 482594648824 ps
CPU time 2600.27 seconds
Started May 12 12:26:06 PM PDT 24
Finished May 12 01:09:27 PM PDT 24
Peak memory 190748 kb
Host smart-9cf9dba6-f7d0-4e83-b16b-0c1ca51969fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178070720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4178070720
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3748517880
Short name T168
Test name
Test status
Simulation time 301972693883 ps
CPU time 403.75 seconds
Started May 12 12:21:50 PM PDT 24
Finished May 12 12:28:35 PM PDT 24
Peak memory 182832 kb
Host smart-2af5d37c-bcb5-4931-b9cc-5dec69c2222c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748517880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3748517880
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/89.rv_timer_random.2947229184
Short name T137
Test name
Test status
Simulation time 399638391713 ps
CPU time 147.22 seconds
Started May 12 12:27:34 PM PDT 24
Finished May 12 12:30:01 PM PDT 24
Peak memory 190944 kb
Host smart-cda45b71-7e65-44e9-a07f-c0b8b6c58280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947229184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2947229184
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.3284265873
Short name T110
Test name
Test status
Simulation time 154774580073 ps
CPU time 2827.48 seconds
Started May 12 12:27:49 PM PDT 24
Finished May 12 01:14:58 PM PDT 24
Peak memory 190976 kb
Host smart-4bc1ed65-633f-4065-901c-03cf32400b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284265873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3284265873
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3453163498
Short name T336
Test name
Test status
Simulation time 253512279393 ps
CPU time 819.63 seconds
Started May 12 12:21:02 PM PDT 24
Finished May 12 12:34:42 PM PDT 24
Peak memory 190988 kb
Host smart-a9a375a0-7a37-4d52-9b01-fb18c28b2862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453163498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3453163498
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3508463334
Short name T143
Test name
Test status
Simulation time 312172760732 ps
CPU time 292.21 seconds
Started May 12 12:27:11 PM PDT 24
Finished May 12 12:32:04 PM PDT 24
Peak memory 181484 kb
Host smart-ee288e49-a712-4841-b45b-d8967c179b76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508463334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3508463334
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3285677033
Short name T287
Test name
Test status
Simulation time 683943131341 ps
CPU time 351.11 seconds
Started May 12 12:24:46 PM PDT 24
Finished May 12 12:30:37 PM PDT 24
Peak memory 182796 kb
Host smart-6daf84dc-ea4c-48d5-8684-edd54fcb9378
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285677033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3285677033
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.2219985993
Short name T232
Test name
Test status
Simulation time 172849914052 ps
CPU time 638.65 seconds
Started May 12 12:26:59 PM PDT 24
Finished May 12 12:37:39 PM PDT 24
Peak memory 190228 kb
Host smart-f63307e8-dca5-43c2-a961-84cb40c45f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219985993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2219985993
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1921547780
Short name T126
Test name
Test status
Simulation time 51053682719 ps
CPU time 208.44 seconds
Started May 12 12:27:52 PM PDT 24
Finished May 12 12:31:21 PM PDT 24
Peak memory 192868 kb
Host smart-36f901de-a693-49dc-9b11-79c46b488068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921547780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1921547780
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.848213028
Short name T263
Test name
Test status
Simulation time 188295634831 ps
CPU time 370.74 seconds
Started May 12 12:24:17 PM PDT 24
Finished May 12 12:30:29 PM PDT 24
Peak memory 191436 kb
Host smart-abda3222-3315-496b-aded-afaa80243115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848213028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.848213028
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.77980213
Short name T184
Test name
Test status
Simulation time 309695197847 ps
CPU time 389.28 seconds
Started May 12 12:27:39 PM PDT 24
Finished May 12 12:34:09 PM PDT 24
Peak memory 190976 kb
Host smart-de4f187b-fd46-4fa0-a514-d8c74fa6d909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77980213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.77980213
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2968898767
Short name T108
Test name
Test status
Simulation time 122929079369 ps
CPU time 738.2 seconds
Started May 12 12:27:42 PM PDT 24
Finished May 12 12:40:01 PM PDT 24
Peak memory 190976 kb
Host smart-ab1f1e6e-ca14-4c74-b7f7-bda8266e0cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968898767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2968898767
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2442402038
Short name T291
Test name
Test status
Simulation time 106931142271 ps
CPU time 925.3 seconds
Started May 12 12:27:31 PM PDT 24
Finished May 12 12:42:57 PM PDT 24
Peak memory 190996 kb
Host smart-094b4817-3c2d-4159-9dfb-6828674453e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442402038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2442402038
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1904792071
Short name T101
Test name
Test status
Simulation time 50639389398 ps
CPU time 76.29 seconds
Started May 12 12:27:35 PM PDT 24
Finished May 12 12:28:52 PM PDT 24
Peak memory 182632 kb
Host smart-6ca03286-a208-4fe9-914e-796f9b14f0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904792071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1904792071
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1961827090
Short name T245
Test name
Test status
Simulation time 36830673009 ps
CPU time 330.5 seconds
Started May 12 12:27:36 PM PDT 24
Finished May 12 12:33:07 PM PDT 24
Peak memory 190964 kb
Host smart-ef669243-eba7-4675-89da-1dd7a29bb8f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961827090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1961827090
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2162097014
Short name T144
Test name
Test status
Simulation time 123100953129 ps
CPU time 1185.13 seconds
Started May 12 12:27:31 PM PDT 24
Finished May 12 12:47:17 PM PDT 24
Peak memory 190900 kb
Host smart-7616cea6-081c-46bb-9471-3ad1118b0437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162097014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2162097014
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4268893721
Short name T297
Test name
Test status
Simulation time 122216643000 ps
CPU time 224.65 seconds
Started May 12 12:27:42 PM PDT 24
Finished May 12 12:31:27 PM PDT 24
Peak memory 190920 kb
Host smart-7fff4596-aae3-4f8d-815c-6a27207e79fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268893721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4268893721
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1117805175
Short name T302
Test name
Test status
Simulation time 162496230704 ps
CPU time 263.74 seconds
Started May 12 12:27:32 PM PDT 24
Finished May 12 12:31:57 PM PDT 24
Peak memory 190968 kb
Host smart-7bdf379a-b941-4e8a-9ce0-54c24e3ab861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117805175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1117805175
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2180791237
Short name T225
Test name
Test status
Simulation time 410039988844 ps
CPU time 162.48 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:30:35 PM PDT 24
Peak memory 194516 kb
Host smart-6ab08278-4f6c-4cdc-ae39-7740fbe8e8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180791237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2180791237
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1455491933
Short name T208
Test name
Test status
Simulation time 57542356743 ps
CPU time 374.78 seconds
Started May 12 12:27:50 PM PDT 24
Finished May 12 12:34:07 PM PDT 24
Peak memory 190992 kb
Host smart-0742a331-b75c-4a62-99fa-99c1849d6789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455491933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1455491933
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3760450187
Short name T344
Test name
Test status
Simulation time 39576022804 ps
CPU time 1147.96 seconds
Started May 12 12:27:50 PM PDT 24
Finished May 12 12:46:59 PM PDT 24
Peak memory 190900 kb
Host smart-798b3081-6d69-4d7e-a0ff-352a963a6f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760450187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3760450187
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.831826043
Short name T316
Test name
Test status
Simulation time 70988532508 ps
CPU time 34.38 seconds
Started May 12 12:27:48 PM PDT 24
Finished May 12 12:28:23 PM PDT 24
Peak memory 190976 kb
Host smart-2b4d1d67-3836-43bd-838e-3107ddf868eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831826043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.831826043
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1022760395
Short name T320
Test name
Test status
Simulation time 2233506634395 ps
CPU time 327.57 seconds
Started May 12 12:27:56 PM PDT 24
Finished May 12 12:33:25 PM PDT 24
Peak memory 191004 kb
Host smart-b62459cc-6196-4fde-9cb8-3f7a35d99093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022760395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1022760395
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2423305553
Short name T210
Test name
Test status
Simulation time 262724779152 ps
CPU time 369.81 seconds
Started May 12 12:27:21 PM PDT 24
Finished May 12 12:33:32 PM PDT 24
Peak memory 190984 kb
Host smart-0e192602-c6f2-4832-b923-635e642a2f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423305553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2423305553
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.189504181
Short name T157
Test name
Test status
Simulation time 393865273751 ps
CPU time 236.54 seconds
Started May 12 12:26:56 PM PDT 24
Finished May 12 12:30:54 PM PDT 24
Peak memory 191440 kb
Host smart-00ddf3f7-f457-4def-883b-f51e0863be47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189504181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
189504181
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_random.782663010
Short name T178
Test name
Test status
Simulation time 112265061015 ps
CPU time 655.49 seconds
Started May 12 12:26:53 PM PDT 24
Finished May 12 12:37:49 PM PDT 24
Peak memory 190980 kb
Host smart-6db16d4b-a8b3-4f7a-a7a6-5ca82f4f7f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782663010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.782663010
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1791647461
Short name T230
Test name
Test status
Simulation time 23647097450 ps
CPU time 28.58 seconds
Started May 12 12:27:08 PM PDT 24
Finished May 12 12:27:37 PM PDT 24
Peak memory 182772 kb
Host smart-8f6cd395-5ee6-4207-9b6e-178b1f8772cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791647461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1791647461
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3808916586
Short name T49
Test name
Test status
Simulation time 346479286676 ps
CPU time 170.67 seconds
Started May 12 12:27:12 PM PDT 24
Finished May 12 12:30:04 PM PDT 24
Peak memory 182788 kb
Host smart-2648b226-5928-43fb-a1d2-86a5cff9eec9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808916586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3808916586
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.2691522707
Short name T218
Test name
Test status
Simulation time 221827690353 ps
CPU time 200.03 seconds
Started May 12 12:27:20 PM PDT 24
Finished May 12 12:30:41 PM PDT 24
Peak memory 191080 kb
Host smart-0716a62d-278a-4a85-a544-4e5a36241fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691522707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2691522707
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1554378633
Short name T300
Test name
Test status
Simulation time 145334929376 ps
CPU time 245.12 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:31:30 PM PDT 24
Peak memory 182836 kb
Host smart-212328b4-d08a-43a3-9303-9ea453a32afa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554378633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1554378633
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2828365559
Short name T258
Test name
Test status
Simulation time 92763531066 ps
CPU time 591.86 seconds
Started May 12 12:27:20 PM PDT 24
Finished May 12 12:37:13 PM PDT 24
Peak memory 190980 kb
Host smart-0d0cd96c-0e86-4d63-b9cb-23eca531438c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828365559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2828365559
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/57.rv_timer_random.204686569
Short name T99
Test name
Test status
Simulation time 508907547175 ps
CPU time 381.65 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:34:14 PM PDT 24
Peak memory 193312 kb
Host smart-edd522a0-f2e7-42cd-a621-9571e1f2a4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204686569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.204686569
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.522710696
Short name T219
Test name
Test status
Simulation time 190221246974 ps
CPU time 550.03 seconds
Started May 12 12:27:29 PM PDT 24
Finished May 12 12:36:40 PM PDT 24
Peak memory 190976 kb
Host smart-7e6ed46b-c790-4015-ac64-34e37f4dfa24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522710696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.522710696
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4155182432
Short name T182
Test name
Test status
Simulation time 270725194011 ps
CPU time 511.47 seconds
Started May 12 12:27:32 PM PDT 24
Finished May 12 12:36:05 PM PDT 24
Peak memory 190284 kb
Host smart-aacb9280-9524-4bc4-b132-1cfba6e57867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155182432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4155182432
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2256924026
Short name T520
Test name
Test status
Simulation time 42020159 ps
CPU time 0.6 seconds
Started May 12 01:14:24 PM PDT 24
Finished May 12 01:14:25 PM PDT 24
Peak memory 182752 kb
Host smart-7d8b30af-95d5-4384-98db-71843ff97d07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256924026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2256924026
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.406914506
Short name T528
Test name
Test status
Simulation time 277506153 ps
CPU time 3.76 seconds
Started May 12 01:14:26 PM PDT 24
Finished May 12 01:14:30 PM PDT 24
Peak memory 193964 kb
Host smart-41e657fd-6306-4830-9cdf-dc61664ac382
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406914506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.406914506
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2965019335
Short name T501
Test name
Test status
Simulation time 14609030 ps
CPU time 0.52 seconds
Started May 12 01:14:26 PM PDT 24
Finished May 12 01:14:27 PM PDT 24
Peak memory 182092 kb
Host smart-093199a8-a5b5-4bc2-9027-f9cea2fc4cdf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965019335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2965019335
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.657663376
Short name T474
Test name
Test status
Simulation time 238185006 ps
CPU time 0.87 seconds
Started May 12 01:14:27 PM PDT 24
Finished May 12 01:14:28 PM PDT 24
Peak memory 196476 kb
Host smart-0a7f11fe-288a-4a3a-a6c3-4fce57384c65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657663376 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.657663376
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.630822447
Short name T57
Test name
Test status
Simulation time 51742205 ps
CPU time 0.65 seconds
Started May 12 01:14:23 PM PDT 24
Finished May 12 01:14:24 PM PDT 24
Peak memory 182712 kb
Host smart-c5cb3a84-6e13-4f16-ade9-274f2a6da358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630822447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.630822447
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2065564435
Short name T504
Test name
Test status
Simulation time 26498068 ps
CPU time 0.54 seconds
Started May 12 01:14:23 PM PDT 24
Finished May 12 01:14:24 PM PDT 24
Peak memory 182692 kb
Host smart-079db521-f705-44d4-b0e7-b6cb70dca3e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065564435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2065564435
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2410820081
Short name T559
Test name
Test status
Simulation time 74053864 ps
CPU time 0.61 seconds
Started May 12 01:14:25 PM PDT 24
Finished May 12 01:14:26 PM PDT 24
Peak memory 192092 kb
Host smart-397624cd-01ed-473a-a630-38055329d5a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410820081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2410820081
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.6343203
Short name T448
Test name
Test status
Simulation time 78339355 ps
CPU time 1.72 seconds
Started May 12 01:14:24 PM PDT 24
Finished May 12 01:14:26 PM PDT 24
Peak memory 197528 kb
Host smart-f8bd0793-d036-4422-bfbf-509f53e575b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6343203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.6343203
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2774627396
Short name T497
Test name
Test status
Simulation time 355418408 ps
CPU time 0.82 seconds
Started May 12 01:14:25 PM PDT 24
Finished May 12 01:14:26 PM PDT 24
Peak memory 182840 kb
Host smart-8bca7fa0-4132-4387-9296-cc153dc9f0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774627396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2774627396
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2392066631
Short name T471
Test name
Test status
Simulation time 40193593 ps
CPU time 0.61 seconds
Started May 12 01:14:27 PM PDT 24
Finished May 12 01:14:28 PM PDT 24
Peak memory 182716 kb
Host smart-be86b79d-0b7e-4578-af61-6e39b7dd4c5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392066631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2392066631
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.394891665
Short name T85
Test name
Test status
Simulation time 1633883221 ps
CPU time 3.96 seconds
Started May 12 01:14:29 PM PDT 24
Finished May 12 01:14:33 PM PDT 24
Peak memory 193836 kb
Host smart-1c8f7f5d-cf17-45ff-a7f6-00d8291492c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394891665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.394891665
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3584434835
Short name T73
Test name
Test status
Simulation time 102176504 ps
CPU time 0.55 seconds
Started May 12 01:14:29 PM PDT 24
Finished May 12 01:14:29 PM PDT 24
Peak memory 182724 kb
Host smart-b0ec3b29-6ff7-4410-aeba-6d4004e3f03c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584434835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3584434835
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2573044688
Short name T538
Test name
Test status
Simulation time 31464480 ps
CPU time 0.63 seconds
Started May 12 01:14:30 PM PDT 24
Finished May 12 01:14:31 PM PDT 24
Peak memory 193680 kb
Host smart-a3522f54-cd7d-4356-a9ca-a8e086c7221c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573044688 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2573044688
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4114224230
Short name T487
Test name
Test status
Simulation time 29304038 ps
CPU time 0.57 seconds
Started May 12 01:14:26 PM PDT 24
Finished May 12 01:14:27 PM PDT 24
Peak memory 182504 kb
Host smart-8bfda361-358f-4817-8a86-3ae9a487db35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114224230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4114224230
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1989058708
Short name T503
Test name
Test status
Simulation time 41403370 ps
CPU time 0.82 seconds
Started May 12 01:14:30 PM PDT 24
Finished May 12 01:14:31 PM PDT 24
Peak memory 193260 kb
Host smart-c771c797-0a82-423f-a604-335458901624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989058708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1989058708
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.546515473
Short name T575
Test name
Test status
Simulation time 294828163 ps
CPU time 2.14 seconds
Started May 12 01:14:28 PM PDT 24
Finished May 12 01:14:30 PM PDT 24
Peak memory 197824 kb
Host smart-a717561b-4a21-4fee-80a6-6aa3fb032954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546515473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.546515473
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1704083930
Short name T93
Test name
Test status
Simulation time 129783758 ps
CPU time 1.41 seconds
Started May 12 01:14:27 PM PDT 24
Finished May 12 01:14:29 PM PDT 24
Peak memory 195436 kb
Host smart-be695d49-cf8a-485b-b8ad-47e8915de914
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704083930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1704083930
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2945280667
Short name T553
Test name
Test status
Simulation time 289353130 ps
CPU time 0.9 seconds
Started May 12 01:14:44 PM PDT 24
Finished May 12 01:14:46 PM PDT 24
Peak memory 196768 kb
Host smart-09420616-46c4-422b-8924-e01abc1d5e54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945280667 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2945280667
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3763715575
Short name T534
Test name
Test status
Simulation time 15617199 ps
CPU time 0.6 seconds
Started May 12 01:14:49 PM PDT 24
Finished May 12 01:14:50 PM PDT 24
Peak memory 182708 kb
Host smart-c0072939-ee27-435b-9e0d-67820ff5643b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763715575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3763715575
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2188063015
Short name T480
Test name
Test status
Simulation time 104430157 ps
CPU time 0.56 seconds
Started May 12 01:14:51 PM PDT 24
Finished May 12 01:14:52 PM PDT 24
Peak memory 182644 kb
Host smart-04d287d7-4305-4ab4-9364-b41cb6580967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188063015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2188063015
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2501348610
Short name T498
Test name
Test status
Simulation time 22480365 ps
CPU time 0.61 seconds
Started May 12 01:14:45 PM PDT 24
Finished May 12 01:14:46 PM PDT 24
Peak memory 191412 kb
Host smart-9c494990-f53e-4394-b2ca-0192e06d53e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501348610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2501348610
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1147408214
Short name T516
Test name
Test status
Simulation time 219338133 ps
CPU time 2.34 seconds
Started May 12 01:14:46 PM PDT 24
Finished May 12 01:14:49 PM PDT 24
Peak memory 197660 kb
Host smart-7f08fb10-e79b-4c7a-8e5b-354a09055207
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147408214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1147408214
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1345972155
Short name T566
Test name
Test status
Simulation time 406720876 ps
CPU time 1.33 seconds
Started May 12 01:14:46 PM PDT 24
Finished May 12 01:14:47 PM PDT 24
Peak memory 195180 kb
Host smart-b294bc54-bced-4be0-853c-060fd4bfadfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345972155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1345972155
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4138371708
Short name T475
Test name
Test status
Simulation time 101025587 ps
CPU time 0.82 seconds
Started May 12 01:14:50 PM PDT 24
Finished May 12 01:14:51 PM PDT 24
Peak memory 196216 kb
Host smart-48523189-7cb6-4154-9ec6-b4f52b683a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138371708 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4138371708
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.744848912
Short name T522
Test name
Test status
Simulation time 30215221 ps
CPU time 0.55 seconds
Started May 12 01:14:48 PM PDT 24
Finished May 12 01:14:49 PM PDT 24
Peak memory 182756 kb
Host smart-5392ab40-9a39-45c6-b657-fefaff2e9930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744848912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.744848912
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2452300499
Short name T537
Test name
Test status
Simulation time 59613308 ps
CPU time 0.55 seconds
Started May 12 01:14:45 PM PDT 24
Finished May 12 01:14:46 PM PDT 24
Peak memory 182620 kb
Host smart-7a672d47-b821-4e08-955e-3ae0c690d916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452300499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2452300499
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2028633222
Short name T567
Test name
Test status
Simulation time 19288173 ps
CPU time 0.61 seconds
Started May 12 01:14:47 PM PDT 24
Finished May 12 01:14:48 PM PDT 24
Peak memory 191224 kb
Host smart-ea6ec0b8-d706-4f9d-835f-f94b6b35717d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028633222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2028633222
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3897667882
Short name T551
Test name
Test status
Simulation time 235636183 ps
CPU time 1.51 seconds
Started May 12 01:14:53 PM PDT 24
Finished May 12 01:14:55 PM PDT 24
Peak memory 197656 kb
Host smart-45a9d81d-05d7-479b-a20d-545a9d446385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897667882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3897667882
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.805139721
Short name T453
Test name
Test status
Simulation time 137433305 ps
CPU time 1.14 seconds
Started May 12 01:14:47 PM PDT 24
Finished May 12 01:14:49 PM PDT 24
Peak memory 197620 kb
Host smart-f19cffae-2020-4d63-9bdb-85b5c0438825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805139721 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.805139721
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1557940170
Short name T558
Test name
Test status
Simulation time 43428539 ps
CPU time 0.63 seconds
Started May 12 01:14:49 PM PDT 24
Finished May 12 01:14:50 PM PDT 24
Peak memory 182508 kb
Host smart-ce8827d1-5de9-4366-b010-24433322795f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557940170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1557940170
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1972228953
Short name T458
Test name
Test status
Simulation time 53618709 ps
CPU time 0.57 seconds
Started May 12 01:14:49 PM PDT 24
Finished May 12 01:14:50 PM PDT 24
Peak memory 182528 kb
Host smart-a60b2d9a-cc58-41b2-b216-26d391a68e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972228953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1972228953
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.774459261
Short name T462
Test name
Test status
Simulation time 63693620 ps
CPU time 1.21 seconds
Started May 12 01:14:48 PM PDT 24
Finished May 12 01:14:49 PM PDT 24
Peak memory 197256 kb
Host smart-0f38c1d2-3671-4938-81cc-ac53386df1a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774459261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.774459261
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3512360500
Short name T491
Test name
Test status
Simulation time 43399167 ps
CPU time 0.68 seconds
Started May 12 01:14:56 PM PDT 24
Finished May 12 01:14:57 PM PDT 24
Peak memory 194556 kb
Host smart-186522d0-17a1-4c6e-90c9-71aa16c22e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512360500 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3512360500
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.468481953
Short name T493
Test name
Test status
Simulation time 32144094 ps
CPU time 0.64 seconds
Started May 12 01:14:50 PM PDT 24
Finished May 12 01:14:51 PM PDT 24
Peak memory 182776 kb
Host smart-e2e97e9d-c2a2-4742-bb7d-b1ac049eebdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468481953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.468481953
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3968656029
Short name T463
Test name
Test status
Simulation time 15145636 ps
CPU time 0.54 seconds
Started May 12 01:14:50 PM PDT 24
Finished May 12 01:14:51 PM PDT 24
Peak memory 182296 kb
Host smart-c4177aa3-01b7-4bbe-aa09-23e1b769b548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968656029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3968656029
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2509121038
Short name T549
Test name
Test status
Simulation time 38347879 ps
CPU time 0.8 seconds
Started May 12 01:14:53 PM PDT 24
Finished May 12 01:14:55 PM PDT 24
Peak memory 193264 kb
Host smart-526ab9e3-e793-4aba-ba80-3b4f6b7224b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509121038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2509121038
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3639255009
Short name T562
Test name
Test status
Simulation time 57179414 ps
CPU time 2.67 seconds
Started May 12 01:14:47 PM PDT 24
Finished May 12 01:14:51 PM PDT 24
Peak memory 197632 kb
Host smart-178c15f1-099e-495b-b929-7de18fa87bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639255009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3639255009
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3442049562
Short name T502
Test name
Test status
Simulation time 625535335 ps
CPU time 1.17 seconds
Started May 12 01:14:53 PM PDT 24
Finished May 12 01:14:55 PM PDT 24
Peak memory 183296 kb
Host smart-59d2fe9d-fa8d-44fd-b336-464b2c30e5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442049562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3442049562
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2644251019
Short name T486
Test name
Test status
Simulation time 14701879 ps
CPU time 0.62 seconds
Started May 12 01:14:55 PM PDT 24
Finished May 12 01:14:56 PM PDT 24
Peak memory 193420 kb
Host smart-5feb94a4-500e-461a-b29e-f0c59d0da119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644251019 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2644251019
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1317953440
Short name T92
Test name
Test status
Simulation time 16073339 ps
CPU time 0.57 seconds
Started May 12 01:14:55 PM PDT 24
Finished May 12 01:14:56 PM PDT 24
Peak memory 182684 kb
Host smart-2cacef34-e3d2-45cb-a595-40d84a41b278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317953440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1317953440
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.701624772
Short name T466
Test name
Test status
Simulation time 59646604 ps
CPU time 0.52 seconds
Started May 12 01:14:53 PM PDT 24
Finished May 12 01:14:54 PM PDT 24
Peak memory 181956 kb
Host smart-c8718b83-4f2d-43c9-9d42-6d5fce46c648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701624772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.701624772
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2092020246
Short name T568
Test name
Test status
Simulation time 107446384 ps
CPU time 0.77 seconds
Started May 12 01:14:52 PM PDT 24
Finished May 12 01:14:53 PM PDT 24
Peak memory 191716 kb
Host smart-be2180bc-5ade-45f5-9d9a-3786a245524a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092020246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2092020246
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.395643138
Short name T451
Test name
Test status
Simulation time 113571709 ps
CPU time 2.85 seconds
Started May 12 01:14:53 PM PDT 24
Finished May 12 01:14:56 PM PDT 24
Peak memory 197696 kb
Host smart-7b8cca42-be64-497d-864c-aaab5d34630d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395643138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.395643138
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3182149313
Short name T482
Test name
Test status
Simulation time 414138166 ps
CPU time 0.86 seconds
Started May 12 01:14:55 PM PDT 24
Finished May 12 01:14:57 PM PDT 24
Peak memory 193508 kb
Host smart-27a1c4e0-bfe2-4477-bba4-ffe2d97b1f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182149313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3182149313
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.57115552
Short name T460
Test name
Test status
Simulation time 35610662 ps
CPU time 1.47 seconds
Started May 12 01:14:55 PM PDT 24
Finished May 12 01:14:57 PM PDT 24
Peak memory 197572 kb
Host smart-6f2055cc-8989-4246-9c0b-60b46840c1f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57115552 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.57115552
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.495443100
Short name T510
Test name
Test status
Simulation time 13741048 ps
CPU time 0.55 seconds
Started May 12 01:14:55 PM PDT 24
Finished May 12 01:14:55 PM PDT 24
Peak memory 182672 kb
Host smart-ba5b33fe-a1e1-474f-a66f-172a950c9819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495443100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.495443100
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3030133254
Short name T574
Test name
Test status
Simulation time 63384032 ps
CPU time 0.55 seconds
Started May 12 01:14:53 PM PDT 24
Finished May 12 01:14:54 PM PDT 24
Peak memory 182580 kb
Host smart-27214a86-ffed-4cc0-bebf-c9bb79282460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030133254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3030133254
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4248461607
Short name T59
Test name
Test status
Simulation time 85030502 ps
CPU time 0.63 seconds
Started May 12 01:14:54 PM PDT 24
Finished May 12 01:14:55 PM PDT 24
Peak memory 191596 kb
Host smart-4100806e-5061-4b37-b722-8bc93e93d00b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248461607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4248461607
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1227585201
Short name T508
Test name
Test status
Simulation time 54775074 ps
CPU time 1.17 seconds
Started May 12 01:14:54 PM PDT 24
Finished May 12 01:14:56 PM PDT 24
Peak memory 196728 kb
Host smart-ed6d5649-8b02-481d-b917-3c929eed53dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227585201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1227585201
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2977908304
Short name T570
Test name
Test status
Simulation time 348381699 ps
CPU time 0.84 seconds
Started May 12 01:14:54 PM PDT 24
Finished May 12 01:14:56 PM PDT 24
Peak memory 192748 kb
Host smart-df4e4e7e-cbf5-4d6f-bb63-e1dd196980d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977908304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2977908304
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.116415236
Short name T561
Test name
Test status
Simulation time 48803730 ps
CPU time 0.77 seconds
Started May 12 01:14:53 PM PDT 24
Finished May 12 01:14:54 PM PDT 24
Peak memory 195096 kb
Host smart-e65211ca-7d78-44dc-8f37-6a11eb0845c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116415236 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.116415236
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1466345516
Short name T572
Test name
Test status
Simulation time 16205160 ps
CPU time 0.58 seconds
Started May 12 01:14:56 PM PDT 24
Finished May 12 01:14:57 PM PDT 24
Peak memory 182756 kb
Host smart-bea7ee61-f294-45d3-b43d-254ba421fde4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466345516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1466345516
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.670909971
Short name T495
Test name
Test status
Simulation time 13110654 ps
CPU time 0.57 seconds
Started May 12 01:14:53 PM PDT 24
Finished May 12 01:14:54 PM PDT 24
Peak memory 182660 kb
Host smart-66752fd9-7d18-48fb-8612-ca8ce79549ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670909971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.670909971
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1363097053
Short name T76
Test name
Test status
Simulation time 19384205 ps
CPU time 0.63 seconds
Started May 12 01:14:52 PM PDT 24
Finished May 12 01:14:53 PM PDT 24
Peak memory 191316 kb
Host smart-e7f33568-92fb-4e6b-8212-0bcf33e07b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363097053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1363097053
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1653152439
Short name T529
Test name
Test status
Simulation time 25472122 ps
CPU time 1.34 seconds
Started May 12 01:14:54 PM PDT 24
Finished May 12 01:14:55 PM PDT 24
Peak memory 197444 kb
Host smart-d5327fd6-0ac8-4055-b354-5ca151188e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653152439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1653152439
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3106606558
Short name T545
Test name
Test status
Simulation time 132712040 ps
CPU time 1.37 seconds
Started May 12 01:14:55 PM PDT 24
Finished May 12 01:14:57 PM PDT 24
Peak memory 195160 kb
Host smart-eebe5b66-f28d-4a8d-9319-538cb7994217
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106606558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3106606558
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3027305585
Short name T481
Test name
Test status
Simulation time 39936736 ps
CPU time 0.9 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:15:00 PM PDT 24
Peak memory 196776 kb
Host smart-6bc2386f-02e7-4ef5-bf96-d05e54eb9057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027305585 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3027305585
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.935908599
Short name T82
Test name
Test status
Simulation time 31403665 ps
CPU time 0.57 seconds
Started May 12 01:14:57 PM PDT 24
Finished May 12 01:14:58 PM PDT 24
Peak memory 182600 kb
Host smart-4cecc953-74f7-4081-8af2-5ed1734e6d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935908599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.935908599
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3335506093
Short name T531
Test name
Test status
Simulation time 39458220 ps
CPU time 0.56 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:14:59 PM PDT 24
Peak memory 182652 kb
Host smart-a8e391ef-7647-41c3-a47b-04c73b9d6398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335506093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3335506093
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.375886447
Short name T37
Test name
Test status
Simulation time 48380312 ps
CPU time 0.64 seconds
Started May 12 01:14:57 PM PDT 24
Finished May 12 01:14:58 PM PDT 24
Peak memory 192060 kb
Host smart-4f5e851b-52e2-4e6a-a9e3-9e79bd9172db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375886447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.375886447
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2858136338
Short name T461
Test name
Test status
Simulation time 592684407 ps
CPU time 1.68 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:15:01 PM PDT 24
Peak memory 197492 kb
Host smart-fb33321b-909c-4bf6-9a0a-2dd4cc6e82d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858136338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2858136338
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1778422011
Short name T548
Test name
Test status
Simulation time 169003908 ps
CPU time 0.85 seconds
Started May 12 01:14:57 PM PDT 24
Finished May 12 01:14:59 PM PDT 24
Peak memory 193648 kb
Host smart-e141a05f-a785-47ff-b48e-ceb55d3d1871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778422011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1778422011
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3940850606
Short name T555
Test name
Test status
Simulation time 61928736 ps
CPU time 0.68 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:15:00 PM PDT 24
Peak memory 195000 kb
Host smart-f0d3bc65-cd72-4752-b5e2-f68297ed89ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940850606 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3940850606
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2804754690
Short name T541
Test name
Test status
Simulation time 82227448 ps
CPU time 0.58 seconds
Started May 12 01:14:59 PM PDT 24
Finished May 12 01:15:00 PM PDT 24
Peak memory 182728 kb
Host smart-24fa5213-b84b-4189-8aee-230e411d0feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804754690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2804754690
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1727100163
Short name T526
Test name
Test status
Simulation time 38279147 ps
CPU time 0.53 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:15:00 PM PDT 24
Peak memory 182136 kb
Host smart-3d59743d-9b29-4c7a-bf75-f7984cc82776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727100163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1727100163
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.816521960
Short name T88
Test name
Test status
Simulation time 32937375 ps
CPU time 0.72 seconds
Started May 12 01:15:01 PM PDT 24
Finished May 12 01:15:03 PM PDT 24
Peak memory 193304 kb
Host smart-07b7942e-d10e-43c1-92ec-180418793c6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816521960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.816521960
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.677142091
Short name T66
Test name
Test status
Simulation time 440783278 ps
CPU time 2.26 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:15:01 PM PDT 24
Peak memory 197564 kb
Host smart-9dfb8470-0224-4eec-a632-adc3010c1387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677142091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.677142091
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2481502249
Short name T468
Test name
Test status
Simulation time 51811113 ps
CPU time 0.88 seconds
Started May 12 01:14:57 PM PDT 24
Finished May 12 01:14:58 PM PDT 24
Peak memory 193940 kb
Host smart-a5b5ef8e-f6f8-4f71-890c-ff341d9fb527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481502249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2481502249
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.292946426
Short name T452
Test name
Test status
Simulation time 21803906 ps
CPU time 0.88 seconds
Started May 12 01:14:56 PM PDT 24
Finished May 12 01:14:58 PM PDT 24
Peak memory 196596 kb
Host smart-9c15c14c-e573-4947-8287-c9915a956cae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292946426 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.292946426
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3583933720
Short name T525
Test name
Test status
Simulation time 61498714 ps
CPU time 0.61 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:14:59 PM PDT 24
Peak memory 191936 kb
Host smart-b279715c-1287-4e0d-8d9a-a283de0d0c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583933720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3583933720
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2598694172
Short name T449
Test name
Test status
Simulation time 50097873 ps
CPU time 0.59 seconds
Started May 12 01:15:00 PM PDT 24
Finished May 12 01:15:01 PM PDT 24
Peak memory 182600 kb
Host smart-967bddcd-9038-4ecc-9d2a-5986efffd5cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598694172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2598694172
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3374499418
Short name T56
Test name
Test status
Simulation time 28656451 ps
CPU time 0.71 seconds
Started May 12 01:15:00 PM PDT 24
Finished May 12 01:15:01 PM PDT 24
Peak memory 192140 kb
Host smart-6d8ec235-71ae-4c5f-ae18-35cbe947d83e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374499418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3374499418
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3277248359
Short name T557
Test name
Test status
Simulation time 633522596 ps
CPU time 2.38 seconds
Started May 12 01:15:01 PM PDT 24
Finished May 12 01:15:04 PM PDT 24
Peak memory 197584 kb
Host smart-bf792b63-0d45-4d57-b5ef-669666224380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277248359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3277248359
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1671086561
Short name T488
Test name
Test status
Simulation time 82313726 ps
CPU time 0.83 seconds
Started May 12 01:15:00 PM PDT 24
Finished May 12 01:15:01 PM PDT 24
Peak memory 193616 kb
Host smart-af98375f-4bfa-49aa-aa36-8069bc1eba52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671086561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1671086561
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1590987285
Short name T77
Test name
Test status
Simulation time 13392964 ps
CPU time 0.62 seconds
Started May 12 01:14:32 PM PDT 24
Finished May 12 01:14:33 PM PDT 24
Peak memory 182752 kb
Host smart-eea35128-57d9-4081-9350-d36f06713c83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590987285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1590987285
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2062705313
Short name T74
Test name
Test status
Simulation time 99545368 ps
CPU time 1.52 seconds
Started May 12 01:14:32 PM PDT 24
Finished May 12 01:14:34 PM PDT 24
Peak memory 191048 kb
Host smart-0d09d68f-5442-4689-9be7-7285170a9d8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062705313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2062705313
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1400082471
Short name T576
Test name
Test status
Simulation time 38460130 ps
CPU time 0.55 seconds
Started May 12 01:14:32 PM PDT 24
Finished May 12 01:14:33 PM PDT 24
Peak memory 182748 kb
Host smart-15676a91-f190-425e-a2ee-ddc9af5a1a82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400082471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1400082471
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3209176054
Short name T485
Test name
Test status
Simulation time 92293464 ps
CPU time 0.77 seconds
Started May 12 01:14:32 PM PDT 24
Finished May 12 01:14:33 PM PDT 24
Peak memory 195556 kb
Host smart-0e8396fd-3422-4179-9ec7-8206d0d650ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209176054 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3209176054
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2680350286
Short name T78
Test name
Test status
Simulation time 74413245 ps
CPU time 0.57 seconds
Started May 12 01:14:32 PM PDT 24
Finished May 12 01:14:33 PM PDT 24
Peak memory 182912 kb
Host smart-8fd6d638-43cb-4789-a120-09185a6d746b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680350286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2680350286
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2078659504
Short name T492
Test name
Test status
Simulation time 23807286 ps
CPU time 0.54 seconds
Started May 12 01:14:32 PM PDT 24
Finished May 12 01:14:33 PM PDT 24
Peak memory 182068 kb
Host smart-39337f3a-e2fb-4f5b-ad9e-35fb996c65ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078659504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2078659504
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.408716355
Short name T86
Test name
Test status
Simulation time 64890007 ps
CPU time 0.65 seconds
Started May 12 01:14:30 PM PDT 24
Finished May 12 01:14:32 PM PDT 24
Peak memory 192020 kb
Host smart-2f918cc4-5ed4-4938-9b43-d3a3679268f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408716355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.408716355
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3704489817
Short name T496
Test name
Test status
Simulation time 141355933 ps
CPU time 1.75 seconds
Started May 12 01:14:31 PM PDT 24
Finished May 12 01:14:33 PM PDT 24
Peak memory 197408 kb
Host smart-b2a1aaf1-e862-44da-adc3-1373c98ac9c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704489817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3704489817
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1891004052
Short name T94
Test name
Test status
Simulation time 224865793 ps
CPU time 1.11 seconds
Started May 12 01:14:31 PM PDT 24
Finished May 12 01:14:32 PM PDT 24
Peak memory 183220 kb
Host smart-23b2225b-31f1-4e7c-9f3c-0353960fe364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891004052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1891004052
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.615589374
Short name T477
Test name
Test status
Simulation time 27327827 ps
CPU time 0.57 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:14:59 PM PDT 24
Peak memory 182628 kb
Host smart-c344216d-e30b-42c5-b1ea-38833a8863bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615589374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.615589374
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.662958745
Short name T484
Test name
Test status
Simulation time 17640873 ps
CPU time 0.56 seconds
Started May 12 01:15:00 PM PDT 24
Finished May 12 01:15:01 PM PDT 24
Peak memory 182716 kb
Host smart-6fb6a4f9-808e-44ae-9353-e7d255fa2e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662958745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.662958745
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2733778502
Short name T536
Test name
Test status
Simulation time 17541317 ps
CPU time 0.55 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:14:59 PM PDT 24
Peak memory 182524 kb
Host smart-07eea870-732d-434d-abfb-72c4185af995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733778502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2733778502
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3726089659
Short name T479
Test name
Test status
Simulation time 15254689 ps
CPU time 0.56 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:14:59 PM PDT 24
Peak memory 182644 kb
Host smart-fe017048-ec24-403e-a0b4-06fcc8a50a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726089659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3726089659
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3349379765
Short name T489
Test name
Test status
Simulation time 18813506 ps
CPU time 0.56 seconds
Started May 12 01:15:01 PM PDT 24
Finished May 12 01:15:02 PM PDT 24
Peak memory 182576 kb
Host smart-67447091-b890-4971-8adb-f5141c521625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349379765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3349379765
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2417127901
Short name T539
Test name
Test status
Simulation time 21418787 ps
CPU time 0.54 seconds
Started May 12 01:14:58 PM PDT 24
Finished May 12 01:14:59 PM PDT 24
Peak memory 182516 kb
Host smart-14f9ae7e-4507-48ca-b879-f83fabf1f007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417127901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2417127901
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2962149936
Short name T455
Test name
Test status
Simulation time 13833286 ps
CPU time 0.58 seconds
Started May 12 01:15:00 PM PDT 24
Finished May 12 01:15:01 PM PDT 24
Peak memory 181880 kb
Host smart-48d30c88-b3b4-437d-8281-d434dc46e3ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962149936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2962149936
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1683998963
Short name T459
Test name
Test status
Simulation time 22657863 ps
CPU time 0.61 seconds
Started May 12 01:15:01 PM PDT 24
Finished May 12 01:15:03 PM PDT 24
Peak memory 182524 kb
Host smart-70951e63-8ce0-4c88-83c2-1a4215a38dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683998963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1683998963
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3540231839
Short name T535
Test name
Test status
Simulation time 115138395 ps
CPU time 0.54 seconds
Started May 12 01:15:02 PM PDT 24
Finished May 12 01:15:03 PM PDT 24
Peak memory 182612 kb
Host smart-b72feb02-83e0-48b6-8fc2-7fbf01d92842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540231839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3540231839
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2074991451
Short name T544
Test name
Test status
Simulation time 54933094 ps
CPU time 0.57 seconds
Started May 12 01:15:02 PM PDT 24
Finished May 12 01:15:03 PM PDT 24
Peak memory 182652 kb
Host smart-6f0d4d44-5cc4-4d2b-84e5-ff83d42fa5a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074991451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2074991451
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3799691244
Short name T75
Test name
Test status
Simulation time 160548620 ps
CPU time 0.73 seconds
Started May 12 01:14:33 PM PDT 24
Finished May 12 01:14:34 PM PDT 24
Peak memory 191780 kb
Host smart-f4152a14-89a5-474a-ad15-6d4c1fd8b97e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799691244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3799691244
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3966309409
Short name T550
Test name
Test status
Simulation time 1219181881 ps
CPU time 2.64 seconds
Started May 12 01:14:33 PM PDT 24
Finished May 12 01:14:36 PM PDT 24
Peak memory 192416 kb
Host smart-19880374-8a29-48a2-8ba8-4717a81ab83f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966309409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3966309409
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3737724860
Short name T81
Test name
Test status
Simulation time 14708323 ps
CPU time 0.62 seconds
Started May 12 01:14:34 PM PDT 24
Finished May 12 01:14:35 PM PDT 24
Peak memory 182760 kb
Host smart-478af0ad-d0cd-49f3-8c62-d40003384316
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737724860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3737724860
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1257811185
Short name T36
Test name
Test status
Simulation time 29385074 ps
CPU time 0.8 seconds
Started May 12 01:14:36 PM PDT 24
Finished May 12 01:14:37 PM PDT 24
Peak memory 196208 kb
Host smart-de04c4cf-f19d-4d31-ace5-e45ee954d1db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257811185 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1257811185
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.840544419
Short name T470
Test name
Test status
Simulation time 38510396 ps
CPU time 0.53 seconds
Started May 12 01:14:31 PM PDT 24
Finished May 12 01:14:32 PM PDT 24
Peak memory 182664 kb
Host smart-1cc9725f-96a0-4969-8710-017594c8b698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840544419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.840544419
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3415131778
Short name T512
Test name
Test status
Simulation time 35527267 ps
CPU time 0.54 seconds
Started May 12 01:14:31 PM PDT 24
Finished May 12 01:14:32 PM PDT 24
Peak memory 182612 kb
Host smart-253e30ee-a0b6-46cf-b12e-45dac52880ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415131778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3415131778
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.370810101
Short name T533
Test name
Test status
Simulation time 18898342 ps
CPU time 0.74 seconds
Started May 12 01:14:31 PM PDT 24
Finished May 12 01:14:33 PM PDT 24
Peak memory 191648 kb
Host smart-2177586f-a6f5-4c5c-802b-b6786012e442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370810101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.370810101
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1391331954
Short name T499
Test name
Test status
Simulation time 41140987 ps
CPU time 1.18 seconds
Started May 12 01:14:30 PM PDT 24
Finished May 12 01:14:32 PM PDT 24
Peak memory 197532 kb
Host smart-c26129b5-0cab-4274-b5f8-9ce710e444b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391331954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1391331954
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3733355562
Short name T556
Test name
Test status
Simulation time 133807659 ps
CPU time 0.82 seconds
Started May 12 01:14:34 PM PDT 24
Finished May 12 01:14:36 PM PDT 24
Peak memory 183120 kb
Host smart-ae7e442c-3ab1-41ce-bda9-bb1ed072851e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733355562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3733355562
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3614585552
Short name T472
Test name
Test status
Simulation time 14718129 ps
CPU time 0.55 seconds
Started May 12 01:15:04 PM PDT 24
Finished May 12 01:15:05 PM PDT 24
Peak memory 182728 kb
Host smart-438ed68e-7b5a-416f-b5b5-6689beff4256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614585552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3614585552
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.179107230
Short name T521
Test name
Test status
Simulation time 20344690 ps
CPU time 0.55 seconds
Started May 12 01:15:03 PM PDT 24
Finished May 12 01:15:04 PM PDT 24
Peak memory 182612 kb
Host smart-c7b58a92-8658-4f12-a693-c1f6c31de115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179107230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.179107230
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2672017032
Short name T507
Test name
Test status
Simulation time 71861320 ps
CPU time 0.56 seconds
Started May 12 01:15:04 PM PDT 24
Finished May 12 01:15:05 PM PDT 24
Peak memory 182696 kb
Host smart-16e7e1c8-1c5c-4078-90c2-bb258e86820b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672017032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2672017032
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.274211463
Short name T506
Test name
Test status
Simulation time 14973888 ps
CPU time 0.55 seconds
Started May 12 01:15:01 PM PDT 24
Finished May 12 01:15:02 PM PDT 24
Peak memory 182596 kb
Host smart-dbb4aeca-637f-4ec8-b637-f0929c1a9096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274211463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.274211463
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1082313723
Short name T464
Test name
Test status
Simulation time 15723249 ps
CPU time 0.55 seconds
Started May 12 01:15:08 PM PDT 24
Finished May 12 01:15:09 PM PDT 24
Peak memory 182480 kb
Host smart-0a1e154c-88a1-4b95-8158-bef99b8dbc21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082313723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1082313723
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.588220472
Short name T518
Test name
Test status
Simulation time 42721860 ps
CPU time 0.54 seconds
Started May 12 01:15:02 PM PDT 24
Finished May 12 01:15:03 PM PDT 24
Peak memory 182224 kb
Host smart-794be5a4-7104-4404-a58f-0505f98a9823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588220472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.588220472
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2961827753
Short name T527
Test name
Test status
Simulation time 11771954 ps
CPU time 0.55 seconds
Started May 12 01:15:02 PM PDT 24
Finished May 12 01:15:03 PM PDT 24
Peak memory 182144 kb
Host smart-00196c72-bd2a-4f44-b490-1c0ecc341c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961827753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2961827753
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3727656524
Short name T450
Test name
Test status
Simulation time 15475482 ps
CPU time 0.55 seconds
Started May 12 01:15:02 PM PDT 24
Finished May 12 01:15:03 PM PDT 24
Peak memory 182544 kb
Host smart-a8e569e1-6256-4005-b0d1-46903b2a18a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727656524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3727656524
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1788731938
Short name T478
Test name
Test status
Simulation time 13889521 ps
CPU time 0.51 seconds
Started May 12 01:15:05 PM PDT 24
Finished May 12 01:15:06 PM PDT 24
Peak memory 181952 kb
Host smart-a737f854-56c6-4068-b983-b5e17463044d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788731938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1788731938
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3243103663
Short name T519
Test name
Test status
Simulation time 36182940 ps
CPU time 0.57 seconds
Started May 12 01:15:03 PM PDT 24
Finished May 12 01:15:04 PM PDT 24
Peak memory 182124 kb
Host smart-63d48e61-cc05-48d3-b02b-998475d00b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243103663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3243103663
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.661087602
Short name T80
Test name
Test status
Simulation time 65507207 ps
CPU time 0.63 seconds
Started May 12 01:14:37 PM PDT 24
Finished May 12 01:14:38 PM PDT 24
Peak memory 182716 kb
Host smart-99771bfa-5cfb-4e73-a63e-0d6c35204a61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661087602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.661087602
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2544651690
Short name T84
Test name
Test status
Simulation time 593674252 ps
CPU time 2.71 seconds
Started May 12 01:14:34 PM PDT 24
Finished May 12 01:14:38 PM PDT 24
Peak memory 191148 kb
Host smart-c62d76a0-1305-4397-9c1f-b96daa56dd98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544651690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2544651690
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2806822978
Short name T79
Test name
Test status
Simulation time 47121605 ps
CPU time 0.58 seconds
Started May 12 01:14:36 PM PDT 24
Finished May 12 01:14:38 PM PDT 24
Peak memory 182648 kb
Host smart-83cc087c-a0f9-4bfd-95ba-9c999c70df0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806822978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2806822978
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.161100748
Short name T523
Test name
Test status
Simulation time 103441200 ps
CPU time 0.74 seconds
Started May 12 01:14:36 PM PDT 24
Finished May 12 01:14:37 PM PDT 24
Peak memory 194404 kb
Host smart-239aaeff-6907-4fa5-9447-ffc2daa58655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161100748 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.161100748
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1918683872
Short name T560
Test name
Test status
Simulation time 21897500 ps
CPU time 0.55 seconds
Started May 12 01:14:37 PM PDT 24
Finished May 12 01:14:38 PM PDT 24
Peak memory 182740 kb
Host smart-ac536b16-34c7-4a36-b165-4f1c47851ca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918683872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1918683872
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2587215759
Short name T473
Test name
Test status
Simulation time 17620214 ps
CPU time 0.55 seconds
Started May 12 01:14:35 PM PDT 24
Finished May 12 01:14:36 PM PDT 24
Peak memory 182552 kb
Host smart-b682b538-2893-4271-b614-32df5d95cd16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587215759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2587215759
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.253664434
Short name T573
Test name
Test status
Simulation time 31959897 ps
CPU time 0.73 seconds
Started May 12 01:14:36 PM PDT 24
Finished May 12 01:14:37 PM PDT 24
Peak memory 191768 kb
Host smart-176ea838-1e28-4ff2-ab32-f89ad31c1d1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253664434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.253664434
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2741397431
Short name T564
Test name
Test status
Simulation time 51284187 ps
CPU time 1.09 seconds
Started May 12 01:14:35 PM PDT 24
Finished May 12 01:14:36 PM PDT 24
Peak memory 197464 kb
Host smart-43ba2527-24c0-4fb1-992f-900a9ce2d964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741397431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2741397431
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2040088611
Short name T532
Test name
Test status
Simulation time 157217571 ps
CPU time 1.13 seconds
Started May 12 01:14:34 PM PDT 24
Finished May 12 01:14:36 PM PDT 24
Peak memory 183336 kb
Host smart-dc1823be-e12c-46a9-8314-4eb35f575fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040088611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2040088611
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1916189218
Short name T571
Test name
Test status
Simulation time 17387543 ps
CPU time 0.6 seconds
Started May 12 01:15:06 PM PDT 24
Finished May 12 01:15:07 PM PDT 24
Peak memory 182480 kb
Host smart-30373d3c-02b1-4ef7-8fbb-45f6f9044ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916189218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1916189218
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2677869607
Short name T469
Test name
Test status
Simulation time 13446014 ps
CPU time 0.55 seconds
Started May 12 01:15:03 PM PDT 24
Finished May 12 01:15:04 PM PDT 24
Peak memory 182708 kb
Host smart-187a3799-5c34-4837-b7de-7787216ebd5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677869607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2677869607
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2377836623
Short name T563
Test name
Test status
Simulation time 13972234 ps
CPU time 0.54 seconds
Started May 12 01:15:02 PM PDT 24
Finished May 12 01:15:03 PM PDT 24
Peak memory 182000 kb
Host smart-23b9babd-b0af-49ef-9f0a-19b7cc4edf99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377836623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2377836623
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3340777606
Short name T457
Test name
Test status
Simulation time 16497548 ps
CPU time 0.59 seconds
Started May 12 01:15:01 PM PDT 24
Finished May 12 01:15:02 PM PDT 24
Peak memory 182860 kb
Host smart-217b818b-cd94-43cd-9a34-ec982e970a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340777606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3340777606
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1193226352
Short name T540
Test name
Test status
Simulation time 12425128 ps
CPU time 0.51 seconds
Started May 12 01:15:05 PM PDT 24
Finished May 12 01:15:06 PM PDT 24
Peak memory 182104 kb
Host smart-8852b810-df30-4896-a2d3-0ccbf51cbdc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193226352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1193226352
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1387391932
Short name T500
Test name
Test status
Simulation time 15558025 ps
CPU time 0.62 seconds
Started May 12 01:15:06 PM PDT 24
Finished May 12 01:15:07 PM PDT 24
Peak memory 182548 kb
Host smart-676023b2-046a-49bc-ae7e-a8332927b99a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387391932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1387391932
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.379842200
Short name T476
Test name
Test status
Simulation time 22183302 ps
CPU time 0.55 seconds
Started May 12 01:15:09 PM PDT 24
Finished May 12 01:15:10 PM PDT 24
Peak memory 182216 kb
Host smart-1de2a5b8-0bdf-4a4b-8bb4-52289e4a52e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379842200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.379842200
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1194187182
Short name T490
Test name
Test status
Simulation time 23682457 ps
CPU time 0.54 seconds
Started May 12 01:15:09 PM PDT 24
Finished May 12 01:15:10 PM PDT 24
Peak memory 181912 kb
Host smart-401d75bf-9888-4b77-8b21-d2a81fed3215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194187182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1194187182
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3136079304
Short name T546
Test name
Test status
Simulation time 15950695 ps
CPU time 0.59 seconds
Started May 12 01:15:09 PM PDT 24
Finished May 12 01:15:10 PM PDT 24
Peak memory 182540 kb
Host smart-198524c6-7233-49e2-97f0-b4bb46386f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136079304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3136079304
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3084817374
Short name T467
Test name
Test status
Simulation time 12655687 ps
CPU time 0.57 seconds
Started May 12 01:15:10 PM PDT 24
Finished May 12 01:15:11 PM PDT 24
Peak memory 182640 kb
Host smart-4833f01d-2ea3-4550-9ad8-8e3bc9db1e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084817374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3084817374
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1651481433
Short name T494
Test name
Test status
Simulation time 57325450 ps
CPU time 0.84 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:40 PM PDT 24
Peak memory 197004 kb
Host smart-93fcada0-793a-4eee-a8a1-1cfe6b2a63f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651481433 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1651481433
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.949212556
Short name T60
Test name
Test status
Simulation time 38802438 ps
CPU time 0.56 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:40 PM PDT 24
Peak memory 182620 kb
Host smart-79b6add4-0bf0-4a02-a9cc-3ccf4340298a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949212556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.949212556
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3284128363
Short name T454
Test name
Test status
Simulation time 16060140 ps
CPU time 0.55 seconds
Started May 12 01:14:34 PM PDT 24
Finished May 12 01:14:35 PM PDT 24
Peak memory 182664 kb
Host smart-db0d25a1-6dd8-42c0-870a-5329f4d84aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284128363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3284128363
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.229955538
Short name T90
Test name
Test status
Simulation time 26756590 ps
CPU time 0.7 seconds
Started May 12 01:14:43 PM PDT 24
Finished May 12 01:14:44 PM PDT 24
Peak memory 192256 kb
Host smart-8e082ace-2497-4376-9a84-5acffb2a99c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229955538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.229955538
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.537276127
Short name T61
Test name
Test status
Simulation time 614712159 ps
CPU time 2.74 seconds
Started May 12 01:14:34 PM PDT 24
Finished May 12 01:14:37 PM PDT 24
Peak memory 197648 kb
Host smart-80de1b11-c270-4574-95fe-68323a92d255
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537276127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.537276127
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4214116422
Short name T511
Test name
Test status
Simulation time 248347835 ps
CPU time 1.1 seconds
Started May 12 01:14:36 PM PDT 24
Finished May 12 01:14:38 PM PDT 24
Peak memory 195420 kb
Host smart-6e25cc9f-c183-42bf-b010-77d8ea21ec1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214116422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.4214116422
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3050442871
Short name T515
Test name
Test status
Simulation time 291689695 ps
CPU time 0.87 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:41 PM PDT 24
Peak memory 196988 kb
Host smart-3a06408e-127e-46a9-9349-4df149f4387b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050442871 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3050442871
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1212419081
Short name T513
Test name
Test status
Simulation time 43844048 ps
CPU time 0.55 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:39 PM PDT 24
Peak memory 182532 kb
Host smart-2a3d632a-a83b-427b-8212-831e67ffbd15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212419081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1212419081
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2264194337
Short name T509
Test name
Test status
Simulation time 144204401 ps
CPU time 0.6 seconds
Started May 12 01:14:43 PM PDT 24
Finished May 12 01:14:44 PM PDT 24
Peak memory 182568 kb
Host smart-6ae1dca2-82fe-4d0f-ba9c-43b8d0208d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264194337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2264194337
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.371815263
Short name T89
Test name
Test status
Simulation time 94189889 ps
CPU time 0.7 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:41 PM PDT 24
Peak memory 193560 kb
Host smart-55a47b84-c2f8-40fd-88c6-53f5ca4ea291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371815263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.371815263
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2751259960
Short name T569
Test name
Test status
Simulation time 965551127 ps
CPU time 2.77 seconds
Started May 12 01:14:41 PM PDT 24
Finished May 12 01:14:44 PM PDT 24
Peak memory 197580 kb
Host smart-f65e4591-dc00-40f3-8386-e610db98ee33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751259960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2751259960
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2004967348
Short name T95
Test name
Test status
Simulation time 84797844 ps
CPU time 1.12 seconds
Started May 12 01:14:41 PM PDT 24
Finished May 12 01:14:42 PM PDT 24
Peak memory 195316 kb
Host smart-1741367b-e4d9-4085-b8ac-5dbb995468b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004967348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2004967348
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.787268975
Short name T483
Test name
Test status
Simulation time 108185600 ps
CPU time 0.77 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:40 PM PDT 24
Peak memory 195088 kb
Host smart-a9296cfb-1d23-45ee-adfa-ee03b56b26e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787268975 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.787268975
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2005104035
Short name T554
Test name
Test status
Simulation time 25414427 ps
CPU time 0.61 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:40 PM PDT 24
Peak memory 182736 kb
Host smart-612f75d1-14b5-47fa-99ed-321e90ef1539
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005104035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2005104035
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.935605069
Short name T517
Test name
Test status
Simulation time 52804447 ps
CPU time 0.6 seconds
Started May 12 01:14:43 PM PDT 24
Finished May 12 01:14:44 PM PDT 24
Peak memory 182616 kb
Host smart-a061375f-e7a1-4404-a631-8b760e2e1e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935605069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.935605069
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2316254681
Short name T542
Test name
Test status
Simulation time 227576794 ps
CPU time 0.69 seconds
Started May 12 01:14:43 PM PDT 24
Finished May 12 01:14:44 PM PDT 24
Peak memory 193116 kb
Host smart-4fbd4fbd-cdc8-4817-9711-247dcb1cbd1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316254681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2316254681
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.770681886
Short name T547
Test name
Test status
Simulation time 500059673 ps
CPU time 2.7 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:43 PM PDT 24
Peak memory 197532 kb
Host smart-3289b804-59fb-4a0f-bef3-0169511d942b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770681886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.770681886
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1208084177
Short name T514
Test name
Test status
Simulation time 269381784 ps
CPU time 1.08 seconds
Started May 12 01:14:39 PM PDT 24
Finished May 12 01:14:41 PM PDT 24
Peak memory 195056 kb
Host smart-0767a921-ca4f-467a-9a03-fd3239fd1fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208084177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1208084177
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1209236518
Short name T58
Test name
Test status
Simulation time 67253184 ps
CPU time 0.68 seconds
Started May 12 01:14:44 PM PDT 24
Finished May 12 01:14:45 PM PDT 24
Peak memory 194832 kb
Host smart-b1a94ab9-4396-46be-8915-e68624072f94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209236518 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1209236518
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.9124885
Short name T35
Test name
Test status
Simulation time 47679907 ps
CPU time 0.56 seconds
Started May 12 01:14:46 PM PDT 24
Finished May 12 01:14:46 PM PDT 24
Peak memory 182640 kb
Host smart-66ce210b-3a7d-4f95-87db-0a5e550d60ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9124885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.9124885
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4080993986
Short name T505
Test name
Test status
Simulation time 14050756 ps
CPU time 0.57 seconds
Started May 12 01:14:44 PM PDT 24
Finished May 12 01:14:45 PM PDT 24
Peak memory 182636 kb
Host smart-fff11ca1-b781-4118-92d8-fdf53108226a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080993986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4080993986
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.275114323
Short name T55
Test name
Test status
Simulation time 131204325 ps
CPU time 0.66 seconds
Started May 12 01:14:45 PM PDT 24
Finished May 12 01:14:46 PM PDT 24
Peak memory 191936 kb
Host smart-42e610c9-acea-44a8-a289-29de310c34d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275114323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.275114323
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.78140490
Short name T543
Test name
Test status
Simulation time 48504347 ps
CPU time 0.99 seconds
Started May 12 01:14:43 PM PDT 24
Finished May 12 01:14:44 PM PDT 24
Peak memory 197472 kb
Host smart-ca01a78a-806a-453d-98f5-86bd66633725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78140490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.78140490
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3565574744
Short name T530
Test name
Test status
Simulation time 390638823 ps
CPU time 1.36 seconds
Started May 12 01:14:45 PM PDT 24
Finished May 12 01:14:47 PM PDT 24
Peak memory 195272 kb
Host smart-4cb275e1-fb0e-4830-a053-33ff9854d46b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565574744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3565574744
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1616843168
Short name T552
Test name
Test status
Simulation time 92940600 ps
CPU time 0.8 seconds
Started May 12 01:14:43 PM PDT 24
Finished May 12 01:14:45 PM PDT 24
Peak memory 195372 kb
Host smart-2d6abd73-9fc9-43bc-9ae9-49bff1a0de42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616843168 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1616843168
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2845117556
Short name T456
Test name
Test status
Simulation time 47689421 ps
CPU time 0.53 seconds
Started May 12 01:14:48 PM PDT 24
Finished May 12 01:14:49 PM PDT 24
Peak memory 182688 kb
Host smart-ac1e55c5-58c6-43a8-9691-30b8138ece93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845117556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2845117556
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.125398211
Short name T465
Test name
Test status
Simulation time 18758320 ps
CPU time 0.56 seconds
Started May 12 01:14:51 PM PDT 24
Finished May 12 01:14:52 PM PDT 24
Peak memory 182108 kb
Host smart-9ee46ffe-d891-474b-9be6-87cc2fb73816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125398211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.125398211
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.713941388
Short name T524
Test name
Test status
Simulation time 141353926 ps
CPU time 0.85 seconds
Started May 12 01:14:51 PM PDT 24
Finished May 12 01:14:52 PM PDT 24
Peak memory 194628 kb
Host smart-163c0963-2d3e-4e21-a874-c1dd1ea3ecf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713941388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.713941388
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.736658471
Short name T565
Test name
Test status
Simulation time 96475652 ps
CPU time 1.57 seconds
Started May 12 01:14:48 PM PDT 24
Finished May 12 01:14:50 PM PDT 24
Peak memory 197544 kb
Host smart-5b707f4d-8a1b-4b31-98d9-c1a0689f283c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736658471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.736658471
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.57474712
Short name T33
Test name
Test status
Simulation time 98394694 ps
CPU time 1.3 seconds
Started May 12 01:14:44 PM PDT 24
Finished May 12 01:14:45 PM PDT 24
Peak memory 183368 kb
Host smart-2218cb2f-24c0-459d-8295-b1531b0330d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57474712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg
_err.57474712
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3303678824
Short name T239
Test name
Test status
Simulation time 400502096290 ps
CPU time 720.52 seconds
Started May 12 12:21:01 PM PDT 24
Finished May 12 12:33:02 PM PDT 24
Peak memory 182752 kb
Host smart-f28b1145-d838-4bc1-9d02-03df9c17d8d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303678824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3303678824
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3128111466
Short name T413
Test name
Test status
Simulation time 257660277526 ps
CPU time 829.71 seconds
Started May 12 12:21:10 PM PDT 24
Finished May 12 12:35:00 PM PDT 24
Peak memory 191076 kb
Host smart-fef773c3-1bae-4711-a327-8d8040e9a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128111466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3128111466
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.274108505
Short name T395
Test name
Test status
Simulation time 537853924386 ps
CPU time 186 seconds
Started May 12 12:21:01 PM PDT 24
Finished May 12 12:24:08 PM PDT 24
Peak memory 182808 kb
Host smart-8d0040cc-d01d-432d-b7c7-1f8e1e257e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274108505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.274108505
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2314763525
Short name T201
Test name
Test status
Simulation time 147077454648 ps
CPU time 412.24 seconds
Started May 12 12:21:02 PM PDT 24
Finished May 12 12:27:55 PM PDT 24
Peak memory 190988 kb
Host smart-658be1b9-4779-432a-821e-c6c518b9cbc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314763525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2314763525
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3320003087
Short name T371
Test name
Test status
Simulation time 139779354 ps
CPU time 1.03 seconds
Started May 12 12:21:01 PM PDT 24
Finished May 12 12:21:04 PM PDT 24
Peak memory 180976 kb
Host smart-6768c769-8a1e-4f7a-ac9e-5fd0b6bfa993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320003087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3320003087
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.104488540
Short name T23
Test name
Test status
Simulation time 332037223 ps
CPU time 0.97 seconds
Started May 12 12:26:06 PM PDT 24
Finished May 12 12:26:08 PM PDT 24
Peak memory 214056 kb
Host smart-38d291e7-77ad-4212-b3a0-d923a5b595b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104488540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.104488540
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.382058788
Short name T67
Test name
Test status
Simulation time 531988400364 ps
CPU time 796.18 seconds
Started May 12 12:21:45 PM PDT 24
Finished May 12 12:35:02 PM PDT 24
Peak memory 191004 kb
Host smart-338e8584-fd4f-4753-9a0f-0a4923ff4657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382058788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.382058788
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1439839022
Short name T40
Test name
Test status
Simulation time 218358234916 ps
CPU time 438.86 seconds
Started May 12 12:22:03 PM PDT 24
Finished May 12 12:29:22 PM PDT 24
Peak memory 206004 kb
Host smart-bee86255-9e47-48f3-8d99-cfd159a907ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439839022 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1439839022
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1875947590
Short name T374
Test name
Test status
Simulation time 233874187048 ps
CPU time 63.13 seconds
Started May 12 12:23:57 PM PDT 24
Finished May 12 12:25:01 PM PDT 24
Peak memory 182812 kb
Host smart-0088e79d-a14e-4770-99d4-eefa095ec326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875947590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1875947590
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3243580183
Short name T64
Test name
Test status
Simulation time 54760101480 ps
CPU time 57.1 seconds
Started May 12 12:27:26 PM PDT 24
Finished May 12 12:28:24 PM PDT 24
Peak memory 182776 kb
Host smart-7e4fb83a-c6f7-49eb-9f83-a269f1f0343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243580183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3243580183
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3526676572
Short name T187
Test name
Test status
Simulation time 334381263716 ps
CPU time 459.02 seconds
Started May 12 12:23:44 PM PDT 24
Finished May 12 12:31:24 PM PDT 24
Peak memory 191360 kb
Host smart-ee4755a5-958e-4ee8-9be4-4a28528a3aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526676572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3526676572
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.2140876930
Short name T142
Test name
Test status
Simulation time 1636893600971 ps
CPU time 797.38 seconds
Started May 12 12:27:31 PM PDT 24
Finished May 12 12:40:50 PM PDT 24
Peak memory 191004 kb
Host smart-66efbae4-1850-4c44-9203-e3355b01eba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140876930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2140876930
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3599476723
Short name T430
Test name
Test status
Simulation time 58355454870 ps
CPU time 1610.93 seconds
Started May 12 12:27:44 PM PDT 24
Finished May 12 12:54:36 PM PDT 24
Peak memory 190964 kb
Host smart-66ea7e15-7d75-4929-aee9-58ce9d175891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599476723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3599476723
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3012126023
Short name T331
Test name
Test status
Simulation time 168543870859 ps
CPU time 686.92 seconds
Started May 12 12:27:36 PM PDT 24
Finished May 12 12:39:04 PM PDT 24
Peak memory 190968 kb
Host smart-84095e01-a4ef-45a0-8475-215989e4d165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012126023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3012126023
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3328078900
Short name T377
Test name
Test status
Simulation time 219517071219 ps
CPU time 79.62 seconds
Started May 12 12:27:33 PM PDT 24
Finished May 12 12:28:53 PM PDT 24
Peak memory 182784 kb
Host smart-3a31622b-32ed-4574-a8ce-e705167a45d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328078900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3328078900
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2507164168
Short name T428
Test name
Test status
Simulation time 184342026836 ps
CPU time 633.6 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:38:03 PM PDT 24
Peak memory 190992 kb
Host smart-a794e862-b7b9-408a-8365-92ab8db8564d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507164168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2507164168
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2279422521
Short name T114
Test name
Test status
Simulation time 65031362287 ps
CPU time 115.95 seconds
Started May 12 12:33:07 PM PDT 24
Finished May 12 12:35:03 PM PDT 24
Peak memory 182708 kb
Host smart-a39914ec-74d8-4877-937d-888a12c9f45d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279422521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2279422521
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2033746128
Short name T358
Test name
Test status
Simulation time 252382493016 ps
CPU time 97.67 seconds
Started May 12 12:33:19 PM PDT 24
Finished May 12 12:34:58 PM PDT 24
Peak memory 182812 kb
Host smart-eed1aa9a-9378-496d-908e-fd02b325a080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033746128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2033746128
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1774719664
Short name T355
Test name
Test status
Simulation time 39689834 ps
CPU time 0.54 seconds
Started May 12 12:23:42 PM PDT 24
Finished May 12 12:23:43 PM PDT 24
Peak memory 182632 kb
Host smart-fb0781f3-164a-4c71-94fe-8500387f4ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774719664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1774719664
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4182378360
Short name T304
Test name
Test status
Simulation time 139854324303 ps
CPU time 198.74 seconds
Started May 12 12:26:13 PM PDT 24
Finished May 12 12:29:32 PM PDT 24
Peak memory 190576 kb
Host smart-2de9c464-5330-4dda-86f1-dae61c32135c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182378360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4182378360
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2157974322
Short name T193
Test name
Test status
Simulation time 17017314827 ps
CPU time 29.46 seconds
Started May 12 12:27:30 PM PDT 24
Finished May 12 12:28:00 PM PDT 24
Peak memory 182748 kb
Host smart-701a2b4a-3de5-48af-8dcb-e0df26cf91d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157974322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2157974322
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1118186865
Short name T334
Test name
Test status
Simulation time 653848239209 ps
CPU time 894.74 seconds
Started May 12 12:27:33 PM PDT 24
Finished May 12 12:42:28 PM PDT 24
Peak memory 190936 kb
Host smart-3592ee69-8a83-483b-bd12-7c71bf06a38b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118186865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1118186865
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2322281635
Short name T166
Test name
Test status
Simulation time 158983587321 ps
CPU time 990.85 seconds
Started May 12 12:27:38 PM PDT 24
Finished May 12 12:44:10 PM PDT 24
Peak memory 190972 kb
Host smart-cd9eed1c-abea-46be-84b6-9b7e654e21b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322281635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2322281635
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.8427458
Short name T96
Test name
Test status
Simulation time 350028193434 ps
CPU time 204.03 seconds
Started May 12 12:23:48 PM PDT 24
Finished May 12 12:27:12 PM PDT 24
Peak memory 183216 kb
Host smart-4a6f40e1-7514-4848-b67e-cebfe19207e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8427458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
rv_timer_cfg_update_on_fly.8427458
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1311963225
Short name T406
Test name
Test status
Simulation time 151596052874 ps
CPU time 115.59 seconds
Started May 12 12:32:51 PM PDT 24
Finished May 12 12:34:47 PM PDT 24
Peak memory 182496 kb
Host smart-d05f8809-aea7-4e15-a877-92523c2b4197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311963225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1311963225
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1234317875
Short name T106
Test name
Test status
Simulation time 1721327547184 ps
CPU time 1153.14 seconds
Started May 12 12:33:06 PM PDT 24
Finished May 12 12:52:20 PM PDT 24
Peak memory 192948 kb
Host smart-b9f5de1d-51aa-4316-a9fa-dd4378e3e6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234317875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1234317875
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.710482098
Short name T310
Test name
Test status
Simulation time 68014952529 ps
CPU time 54.37 seconds
Started May 12 12:27:26 PM PDT 24
Finished May 12 12:28:21 PM PDT 24
Peak memory 194340 kb
Host smart-0b97df77-bdd1-4b59-b455-75bdd8b046fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710482098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.710482098
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3649140510
Short name T253
Test name
Test status
Simulation time 263028544085 ps
CPU time 427.62 seconds
Started May 12 12:26:12 PM PDT 24
Finished May 12 12:33:21 PM PDT 24
Peak memory 190928 kb
Host smart-22c3f945-2e81-4c23-9871-f47a19968b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649140510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3649140510
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.1366701921
Short name T279
Test name
Test status
Simulation time 171579744945 ps
CPU time 618.16 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:38:19 PM PDT 24
Peak memory 194292 kb
Host smart-f9755092-64f9-4bb5-be8a-38f3d71dde8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366701921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1366701921
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2956336404
Short name T236
Test name
Test status
Simulation time 61161686291 ps
CPU time 118.79 seconds
Started May 12 12:27:37 PM PDT 24
Finished May 12 12:29:37 PM PDT 24
Peak memory 190968 kb
Host smart-37d541a5-cf81-419e-a1a4-b98258a79721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956336404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2956336404
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1962087261
Short name T150
Test name
Test status
Simulation time 517293284730 ps
CPU time 497.52 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:36:10 PM PDT 24
Peak memory 190964 kb
Host smart-325672a5-ee2c-49dd-b552-da5c992dcfa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962087261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1962087261
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1994198024
Short name T270
Test name
Test status
Simulation time 410446942701 ps
CPU time 368.07 seconds
Started May 12 12:25:59 PM PDT 24
Finished May 12 12:32:09 PM PDT 24
Peak memory 181716 kb
Host smart-2ec37e94-0d5f-4605-92fc-f52130c94951
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994198024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1994198024
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1750760662
Short name T372
Test name
Test status
Simulation time 299795248826 ps
CPU time 84.75 seconds
Started May 12 12:26:00 PM PDT 24
Finished May 12 12:27:26 PM PDT 24
Peak memory 182416 kb
Host smart-bba0e512-232a-47d1-a0ab-7a07b59e70c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750760662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1750760662
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2914764217
Short name T328
Test name
Test status
Simulation time 203677380612 ps
CPU time 2063.74 seconds
Started May 12 12:26:13 PM PDT 24
Finished May 12 01:00:37 PM PDT 24
Peak memory 190924 kb
Host smart-647fcaf4-beb3-4cf3-a1dc-1cad0f8de817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914764217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2914764217
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3929950184
Short name T427
Test name
Test status
Simulation time 15272443870 ps
CPU time 22.79 seconds
Started May 12 12:26:15 PM PDT 24
Finished May 12 12:26:38 PM PDT 24
Peak memory 182328 kb
Host smart-c64adbaa-0dfe-49f9-896f-f77b62b79a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929950184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3929950184
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.454875489
Short name T18
Test name
Test status
Simulation time 56314096428 ps
CPU time 102.4 seconds
Started May 12 12:26:15 PM PDT 24
Finished May 12 12:27:58 PM PDT 24
Peak memory 197348 kb
Host smart-9ed32b56-d00d-4f37-8dd1-b8ac1ef42ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454875489 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.454875489
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2154182597
Short name T339
Test name
Test status
Simulation time 1104429394291 ps
CPU time 967.6 seconds
Started May 12 12:27:38 PM PDT 24
Finished May 12 12:43:46 PM PDT 24
Peak memory 193308 kb
Host smart-54f848e9-2a84-4921-aeca-673461fe054a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154182597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2154182597
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1078960394
Short name T228
Test name
Test status
Simulation time 116137951653 ps
CPU time 240 seconds
Started May 12 12:27:38 PM PDT 24
Finished May 12 12:31:38 PM PDT 24
Peak memory 194400 kb
Host smart-0b34c4e5-95dd-4983-8943-2c981a2fb6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078960394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1078960394
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3762204568
Short name T292
Test name
Test status
Simulation time 70445105519 ps
CPU time 30.61 seconds
Started May 12 12:27:35 PM PDT 24
Finished May 12 12:28:06 PM PDT 24
Peak memory 182776 kb
Host smart-6fb51a2f-6faf-4ccc-b709-d96b321c59ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762204568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3762204568
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1025188728
Short name T198
Test name
Test status
Simulation time 48300126274 ps
CPU time 451.14 seconds
Started May 12 12:27:43 PM PDT 24
Finished May 12 12:35:15 PM PDT 24
Peak memory 190964 kb
Host smart-f822fb38-f255-433a-acf2-a401fbc3d78b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025188728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1025188728
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1440870643
Short name T346
Test name
Test status
Simulation time 116696141751 ps
CPU time 470.64 seconds
Started May 12 12:27:55 PM PDT 24
Finished May 12 12:35:46 PM PDT 24
Peak memory 190972 kb
Host smart-48e87877-51e8-4117-bc43-d53a07483272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440870643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1440870643
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1927194315
Short name T152
Test name
Test status
Simulation time 490441838486 ps
CPU time 139.18 seconds
Started May 12 12:27:38 PM PDT 24
Finished May 12 12:29:58 PM PDT 24
Peak memory 182424 kb
Host smart-e345ef24-af73-4ae0-8de9-f3a2eb4f40d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927194315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1927194315
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2097124323
Short name T318
Test name
Test status
Simulation time 8116665269 ps
CPU time 4.76 seconds
Started May 12 12:27:05 PM PDT 24
Finished May 12 12:27:11 PM PDT 24
Peak memory 182744 kb
Host smart-d919eae7-f0c9-4db1-9a37-574be935fc44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097124323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2097124323
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3125496317
Short name T393
Test name
Test status
Simulation time 49558680702 ps
CPU time 72.06 seconds
Started May 12 12:24:38 PM PDT 24
Finished May 12 12:25:51 PM PDT 24
Peak memory 182728 kb
Host smart-7622ba7f-1918-4d59-815c-1b0a5c007230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125496317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3125496317
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3512159135
Short name T280
Test name
Test status
Simulation time 92453282960 ps
CPU time 90.42 seconds
Started May 12 12:23:19 PM PDT 24
Finished May 12 12:24:50 PM PDT 24
Peak memory 190916 kb
Host smart-016668b0-c45c-4d10-8065-72e36f4be691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512159135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3512159135
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3110414386
Short name T156
Test name
Test status
Simulation time 107249045238 ps
CPU time 59.35 seconds
Started May 12 12:24:42 PM PDT 24
Finished May 12 12:25:42 PM PDT 24
Peak memory 191404 kb
Host smart-db23a30b-bbea-4e69-be82-f9b9be400386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110414386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3110414386
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.847442291
Short name T29
Test name
Test status
Simulation time 13366346062 ps
CPU time 25.79 seconds
Started May 12 12:27:36 PM PDT 24
Finished May 12 12:28:02 PM PDT 24
Peak memory 190916 kb
Host smart-7611ec50-7281-4afe-b39f-7b5a82c5b38f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847442291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.847442291
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.720408782
Short name T275
Test name
Test status
Simulation time 153690809773 ps
CPU time 97.21 seconds
Started May 12 12:27:43 PM PDT 24
Finished May 12 12:29:21 PM PDT 24
Peak memory 182724 kb
Host smart-d8e24d63-ec79-4384-a9c5-8e68bf45dc97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720408782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.720408782
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2109608460
Short name T409
Test name
Test status
Simulation time 39321926650 ps
CPU time 1010.89 seconds
Started May 12 12:27:30 PM PDT 24
Finished May 12 12:44:22 PM PDT 24
Peak memory 182780 kb
Host smart-585dc79d-c5eb-462d-b6a4-c32edfaa6a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109608460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2109608460
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.850475421
Short name T340
Test name
Test status
Simulation time 444516408659 ps
CPU time 267.39 seconds
Started May 12 12:27:35 PM PDT 24
Finished May 12 12:32:03 PM PDT 24
Peak memory 190952 kb
Host smart-43796a6f-1c44-4bac-8ba9-96e9145f5ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850475421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.850475421
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1930650189
Short name T401
Test name
Test status
Simulation time 94270719827 ps
CPU time 74.82 seconds
Started May 12 12:27:37 PM PDT 24
Finished May 12 12:28:53 PM PDT 24
Peak memory 182712 kb
Host smart-becd7593-e60e-40ac-9c65-38b5d00bc2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930650189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1930650189
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3582810177
Short name T124
Test name
Test status
Simulation time 106450236040 ps
CPU time 1292.05 seconds
Started May 12 12:27:50 PM PDT 24
Finished May 12 12:49:24 PM PDT 24
Peak memory 191004 kb
Host smart-0bb441ad-0310-4e19-820f-744183472c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582810177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3582810177
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.54386994
Short name T436
Test name
Test status
Simulation time 119549758881 ps
CPU time 42.94 seconds
Started May 12 12:27:36 PM PDT 24
Finished May 12 12:28:20 PM PDT 24
Peak memory 194436 kb
Host smart-e8fb0093-0e9c-4ceb-842d-2d983bfac689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54386994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.54386994
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1181907587
Short name T405
Test name
Test status
Simulation time 401023756417 ps
CPU time 171.5 seconds
Started May 12 12:27:57 PM PDT 24
Finished May 12 12:30:51 PM PDT 24
Peak memory 180904 kb
Host smart-81a1552b-899b-47cb-8fb7-88c8e3871777
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181907587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1181907587
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1552521477
Short name T396
Test name
Test status
Simulation time 142218905370 ps
CPU time 197.41 seconds
Started May 12 12:26:39 PM PDT 24
Finished May 12 12:29:57 PM PDT 24
Peak memory 182792 kb
Host smart-e86e82cc-25e3-450a-8dac-993900504e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552521477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1552521477
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2540722349
Short name T234
Test name
Test status
Simulation time 658112172181 ps
CPU time 224.51 seconds
Started May 12 12:26:45 PM PDT 24
Finished May 12 12:30:30 PM PDT 24
Peak memory 190664 kb
Host smart-e5f165b4-6efa-4cd0-904a-ddaf1e753253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540722349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2540722349
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.993838909
Short name T363
Test name
Test status
Simulation time 963915229 ps
CPU time 7.33 seconds
Started May 12 12:26:44 PM PDT 24
Finished May 12 12:26:53 PM PDT 24
Peak memory 190872 kb
Host smart-7f400acd-a965-4a7f-bf35-09881517161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993838909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.993838909
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.335451865
Short name T188
Test name
Test status
Simulation time 278306160176 ps
CPU time 919.78 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:43:20 PM PDT 24
Peak memory 190752 kb
Host smart-36fbac25-f138-4b9d-8db6-bcffe461fb69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335451865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
335451865
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.3242611007
Short name T312
Test name
Test status
Simulation time 28156138447 ps
CPU time 38.57 seconds
Started May 12 12:27:46 PM PDT 24
Finished May 12 12:28:25 PM PDT 24
Peak memory 182724 kb
Host smart-8dfd7ab7-560b-472a-a7a5-cb31efabad14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242611007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3242611007
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1416057816
Short name T177
Test name
Test status
Simulation time 240016058820 ps
CPU time 113.75 seconds
Started May 12 12:27:53 PM PDT 24
Finished May 12 12:29:48 PM PDT 24
Peak memory 190996 kb
Host smart-140da11f-6d2f-446f-b2af-047ff5e4256b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416057816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1416057816
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3827660756
Short name T107
Test name
Test status
Simulation time 98615073494 ps
CPU time 639.57 seconds
Started May 12 12:27:45 PM PDT 24
Finished May 12 12:38:25 PM PDT 24
Peak memory 190972 kb
Host smart-5581ba75-66a4-4d34-9e1e-98775f641633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827660756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3827660756
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3851062299
Short name T202
Test name
Test status
Simulation time 85381878715 ps
CPU time 130.44 seconds
Started May 12 12:27:48 PM PDT 24
Finished May 12 12:29:59 PM PDT 24
Peak memory 193328 kb
Host smart-23834e12-e726-43b5-97ab-b952cdf40ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851062299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3851062299
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3335859785
Short name T242
Test name
Test status
Simulation time 190070781828 ps
CPU time 654.95 seconds
Started May 12 12:27:57 PM PDT 24
Finished May 12 12:38:53 PM PDT 24
Peak memory 190952 kb
Host smart-cd845d0a-eec9-4a12-9ba4-abfc12a3166e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335859785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3335859785
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.425952737
Short name T27
Test name
Test status
Simulation time 15359247116 ps
CPU time 456.74 seconds
Started May 12 12:27:54 PM PDT 24
Finished May 12 12:35:32 PM PDT 24
Peak memory 182780 kb
Host smart-8b89c283-733a-4f16-bf6a-8c3695539c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425952737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.425952737
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.891056894
Short name T233
Test name
Test status
Simulation time 440778899332 ps
CPU time 124.25 seconds
Started May 12 12:27:49 PM PDT 24
Finished May 12 12:29:54 PM PDT 24
Peak memory 190940 kb
Host smart-4085ec03-806d-4321-af25-d65771d454a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891056894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.891056894
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2684406445
Short name T119
Test name
Test status
Simulation time 1973427735085 ps
CPU time 952.86 seconds
Started May 12 12:26:43 PM PDT 24
Finished May 12 12:42:37 PM PDT 24
Peak memory 182780 kb
Host smart-c3716f73-d51d-4b6b-bb1f-4be1929a0355
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684406445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2684406445
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1544095376
Short name T379
Test name
Test status
Simulation time 865932505003 ps
CPU time 271.99 seconds
Started May 12 12:27:16 PM PDT 24
Finished May 12 12:31:49 PM PDT 24
Peak memory 182852 kb
Host smart-bea290a9-87f8-4197-a74b-912f0d6fc9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544095376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1544095376
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.10944976
Short name T191
Test name
Test status
Simulation time 127974652696 ps
CPU time 100.15 seconds
Started May 12 12:26:39 PM PDT 24
Finished May 12 12:28:20 PM PDT 24
Peak memory 191076 kb
Host smart-422ea1a3-4808-4597-a048-bd40ee4dabaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.10944976
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3948766791
Short name T206
Test name
Test status
Simulation time 59518275809 ps
CPU time 455.7 seconds
Started May 12 12:27:17 PM PDT 24
Finished May 12 12:34:54 PM PDT 24
Peak memory 182808 kb
Host smart-f31ad7e4-c394-46d4-af61-59b0d2b41b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948766791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3948766791
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3351294097
Short name T28
Test name
Test status
Simulation time 1839303745667 ps
CPU time 3025.69 seconds
Started May 12 12:26:37 PM PDT 24
Finished May 12 01:17:04 PM PDT 24
Peak memory 191424 kb
Host smart-cadd8877-8e2c-4c20-9f15-a9b4673d82e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351294097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3351294097
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.1684474615
Short name T43
Test name
Test status
Simulation time 485913129266 ps
CPU time 1305.71 seconds
Started May 12 12:26:43 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 209260 kb
Host smart-2b80d9fe-1718-4f7c-9db5-d23cb5d30007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684474615 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.1684474615
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3514470570
Short name T398
Test name
Test status
Simulation time 93383762284 ps
CPU time 456.22 seconds
Started May 12 12:27:40 PM PDT 24
Finished May 12 12:35:17 PM PDT 24
Peak memory 191084 kb
Host smart-99547f98-73f0-4a98-a324-12696ea8d99d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514470570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3514470570
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1378595319
Short name T276
Test name
Test status
Simulation time 51143420329 ps
CPU time 778.83 seconds
Started May 12 12:27:52 PM PDT 24
Finished May 12 12:40:52 PM PDT 24
Peak memory 190948 kb
Host smart-bed78551-8d0f-491a-ac81-d9f1fe2d34dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378595319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1378595319
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3381333994
Short name T327
Test name
Test status
Simulation time 75648744683 ps
CPU time 513.97 seconds
Started May 12 12:27:47 PM PDT 24
Finished May 12 12:36:22 PM PDT 24
Peak memory 191976 kb
Host smart-b7c9dcf6-b4ce-4075-9da3-3466836b39c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381333994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3381333994
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2366488155
Short name T347
Test name
Test status
Simulation time 2269472807 ps
CPU time 3.74 seconds
Started May 12 12:28:01 PM PDT 24
Finished May 12 12:28:06 PM PDT 24
Peak memory 182660 kb
Host smart-a6caeb08-b8c2-45f0-8c7f-9a3fed111069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366488155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2366488155
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2318304809
Short name T260
Test name
Test status
Simulation time 1956396420282 ps
CPU time 472.64 seconds
Started May 12 12:27:53 PM PDT 24
Finished May 12 12:35:47 PM PDT 24
Peak memory 191000 kb
Host smart-ffc399c8-8708-421a-bb74-b4a21b94174c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318304809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2318304809
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2655564123
Short name T220
Test name
Test status
Simulation time 267121415911 ps
CPU time 384.39 seconds
Started May 12 12:27:53 PM PDT 24
Finished May 12 12:34:18 PM PDT 24
Peak memory 183160 kb
Host smart-a65a2346-1d9c-47bc-b61b-aeb9c4eb5f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655564123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2655564123
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.877836493
Short name T370
Test name
Test status
Simulation time 23297126356 ps
CPU time 34.65 seconds
Started May 12 12:27:59 PM PDT 24
Finished May 12 12:28:36 PM PDT 24
Peak memory 182724 kb
Host smart-9d2d773f-9926-418b-97d0-5bc820df6ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877836493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.877836493
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1619761644
Short name T256
Test name
Test status
Simulation time 113240907325 ps
CPU time 178.65 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:30:51 PM PDT 24
Peak memory 190964 kb
Host smart-e38ea3a0-8e49-458c-b65c-7fd4efec2158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619761644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1619761644
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3584882472
Short name T294
Test name
Test status
Simulation time 119338845794 ps
CPU time 93.11 seconds
Started May 12 12:27:49 PM PDT 24
Finished May 12 12:29:23 PM PDT 24
Peak memory 194604 kb
Host smart-c1a09685-b918-4147-97fc-b7c05628c7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584882472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3584882472
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3628141409
Short name T400
Test name
Test status
Simulation time 75283548206 ps
CPU time 127.01 seconds
Started May 12 12:26:43 PM PDT 24
Finished May 12 12:28:51 PM PDT 24
Peak memory 182784 kb
Host smart-f8776be2-45d4-4764-854a-eaa2040ea759
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628141409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3628141409
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3647871692
Short name T394
Test name
Test status
Simulation time 590220752719 ps
CPU time 197.3 seconds
Started May 12 12:26:36 PM PDT 24
Finished May 12 12:29:54 PM PDT 24
Peak memory 182744 kb
Host smart-e024bc53-0e77-4bf3-bedb-660a0c12e62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647871692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3647871692
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.346482755
Short name T235
Test name
Test status
Simulation time 148030496334 ps
CPU time 710.98 seconds
Started May 12 12:27:34 PM PDT 24
Finished May 12 12:39:25 PM PDT 24
Peak memory 182744 kb
Host smart-fa34a49a-0b16-45ed-9732-1e41bebf86b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346482755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.346482755
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3321580133
Short name T71
Test name
Test status
Simulation time 689931719761 ps
CPU time 709.66 seconds
Started May 12 12:26:58 PM PDT 24
Finished May 12 12:38:48 PM PDT 24
Peak memory 194504 kb
Host smart-468f71f3-4aee-43fe-88ad-667022c13c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321580133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3321580133
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.357259802
Short name T105
Test name
Test status
Simulation time 107038114686 ps
CPU time 104.86 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:29:37 PM PDT 24
Peak memory 194288 kb
Host smart-cecfcd31-965d-4544-82ec-5298120d12e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357259802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.357259802
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2269073373
Short name T296
Test name
Test status
Simulation time 195761828794 ps
CPU time 64.59 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:28:57 PM PDT 24
Peak memory 182632 kb
Host smart-bdeb0def-2694-4825-989b-b0e02c684c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269073373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2269073373
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3615641982
Short name T408
Test name
Test status
Simulation time 107684274728 ps
CPU time 173.04 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:30:45 PM PDT 24
Peak memory 194616 kb
Host smart-b711921c-4404-4f44-b3e2-a0bee3b410a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615641982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3615641982
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2950129249
Short name T445
Test name
Test status
Simulation time 161871642838 ps
CPU time 266.74 seconds
Started May 12 12:27:52 PM PDT 24
Finished May 12 12:32:21 PM PDT 24
Peak memory 190932 kb
Host smart-0b2ea9bb-958f-45b9-bc78-f15a94005cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950129249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2950129249
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2087291304
Short name T120
Test name
Test status
Simulation time 280292423576 ps
CPU time 150.41 seconds
Started May 12 12:27:59 PM PDT 24
Finished May 12 12:30:32 PM PDT 24
Peak memory 190932 kb
Host smart-cc020fc5-4c66-4cdf-8b57-08cd590f605e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087291304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2087291304
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.696679234
Short name T251
Test name
Test status
Simulation time 170990059122 ps
CPU time 70.51 seconds
Started May 12 12:27:48 PM PDT 24
Finished May 12 12:28:59 PM PDT 24
Peak memory 193300 kb
Host smart-03809da6-59ef-4453-8bb7-d448fa895fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696679234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.696679234
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3606263358
Short name T392
Test name
Test status
Simulation time 140608872893 ps
CPU time 232.54 seconds
Started May 12 12:27:57 PM PDT 24
Finished May 12 12:31:52 PM PDT 24
Peak memory 181340 kb
Host smart-1d879723-456f-4bc0-943b-a51e79a77779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606263358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3606263358
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.218809856
Short name T173
Test name
Test status
Simulation time 1908286131689 ps
CPU time 899.57 seconds
Started May 12 12:26:42 PM PDT 24
Finished May 12 12:41:42 PM PDT 24
Peak memory 190984 kb
Host smart-aeeda161-5b63-4488-8c47-57ccd3fbc0a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218809856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.218809856
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1993441262
Short name T212
Test name
Test status
Simulation time 44617961025 ps
CPU time 59.18 seconds
Started May 12 12:26:40 PM PDT 24
Finished May 12 12:27:39 PM PDT 24
Peak memory 190936 kb
Host smart-0c32cfeb-44fa-4121-b185-21233d396438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993441262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1993441262
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2186531841
Short name T332
Test name
Test status
Simulation time 54274547450 ps
CPU time 74.02 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:28:43 PM PDT 24
Peak memory 191364 kb
Host smart-5f56efca-4331-48fe-ac76-bfd1a5828da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186531841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2186531841
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.4088118652
Short name T226
Test name
Test status
Simulation time 55962741131 ps
CPU time 92.39 seconds
Started May 12 12:27:52 PM PDT 24
Finished May 12 12:29:26 PM PDT 24
Peak memory 182800 kb
Host smart-fa5366a7-9e75-49fd-8ba3-d89d4b161e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088118652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4088118652
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1819196347
Short name T189
Test name
Test status
Simulation time 146314383391 ps
CPU time 291.53 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:32:51 PM PDT 24
Peak memory 191004 kb
Host smart-00d56ac3-7226-40b1-b504-0a0e65f355ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819196347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1819196347
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.301792867
Short name T50
Test name
Test status
Simulation time 108138276454 ps
CPU time 168.03 seconds
Started May 12 12:27:56 PM PDT 24
Finished May 12 12:30:45 PM PDT 24
Peak memory 190972 kb
Host smart-206cef6f-30ab-47c8-9a70-1a699dd9a135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301792867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.301792867
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.632142382
Short name T131
Test name
Test status
Simulation time 134696784656 ps
CPU time 250.66 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:32:03 PM PDT 24
Peak memory 194356 kb
Host smart-2e0b0532-a78b-4cfa-a550-c0ff7f9c3787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632142382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.632142382
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.581993846
Short name T5
Test name
Test status
Simulation time 6835819980 ps
CPU time 6.38 seconds
Started May 12 12:27:52 PM PDT 24
Finished May 12 12:28:00 PM PDT 24
Peak memory 182804 kb
Host smart-b9831190-ec66-4cc2-870e-a83d121231c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581993846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.581993846
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1853678958
Short name T223
Test name
Test status
Simulation time 920392078682 ps
CPU time 932.69 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:43:25 PM PDT 24
Peak memory 190988 kb
Host smart-8dc6fe51-4431-4ba3-b0b3-dfe2e45904dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853678958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1853678958
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1595028393
Short name T416
Test name
Test status
Simulation time 30525095482 ps
CPU time 81.75 seconds
Started May 12 12:27:59 PM PDT 24
Finished May 12 12:29:23 PM PDT 24
Peak memory 190996 kb
Host smart-77e65af0-fe14-4d48-885f-8bbb0b53c769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595028393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1595028393
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1948600287
Short name T160
Test name
Test status
Simulation time 133852699696 ps
CPU time 1763.82 seconds
Started May 12 12:27:47 PM PDT 24
Finished May 12 12:57:12 PM PDT 24
Peak memory 190972 kb
Host smart-adfd10d5-79b8-4a5a-896d-2f0949eb7144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948600287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1948600287
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.351559827
Short name T30
Test name
Test status
Simulation time 63571099836 ps
CPU time 99.02 seconds
Started May 12 12:27:49 PM PDT 24
Finished May 12 12:29:29 PM PDT 24
Peak memory 191000 kb
Host smart-7e4344f5-0fbb-47f1-990c-50fc41a40f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351559827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.351559827
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3853071608
Short name T158
Test name
Test status
Simulation time 109983788573 ps
CPU time 505.07 seconds
Started May 12 12:28:08 PM PDT 24
Finished May 12 12:36:35 PM PDT 24
Peak memory 190992 kb
Host smart-6b5ae610-5eee-47ea-84ff-579147a9c0dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853071608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3853071608
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2259350739
Short name T244
Test name
Test status
Simulation time 472484126652 ps
CPU time 803.03 seconds
Started May 12 12:27:05 PM PDT 24
Finished May 12 12:40:28 PM PDT 24
Peak memory 182788 kb
Host smart-7a43b3da-7784-4431-a8c7-89785741535b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259350739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2259350739
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3683576740
Short name T397
Test name
Test status
Simulation time 280751806956 ps
CPU time 253.58 seconds
Started May 12 12:27:46 PM PDT 24
Finished May 12 12:32:01 PM PDT 24
Peak memory 182748 kb
Host smart-08b941c6-63fa-4db1-b1f3-9c0bed5d5b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683576740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3683576740
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.392109623
Short name T165
Test name
Test status
Simulation time 149306905600 ps
CPU time 589.49 seconds
Started May 12 12:26:43 PM PDT 24
Finished May 12 12:36:33 PM PDT 24
Peak memory 190956 kb
Host smart-bf5fc7ce-b6ca-4e77-9a64-557c79922212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392109623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.392109623
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1658880314
Short name T348
Test name
Test status
Simulation time 173654120 ps
CPU time 1.78 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:28:01 PM PDT 24
Peak memory 182344 kb
Host smart-116ee71d-f22d-4d90-9096-54d98160d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658880314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1658880314
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/191.rv_timer_random.3372958967
Short name T391
Test name
Test status
Simulation time 36020252394 ps
CPU time 153.69 seconds
Started May 12 12:28:02 PM PDT 24
Finished May 12 12:30:38 PM PDT 24
Peak memory 182732 kb
Host smart-e3a16f8c-0ead-4809-bc30-371c8ed44d88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372958967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3372958967
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3935357169
Short name T130
Test name
Test status
Simulation time 15884066060 ps
CPU time 28.82 seconds
Started May 12 12:28:05 PM PDT 24
Finished May 12 12:28:35 PM PDT 24
Peak memory 182804 kb
Host smart-eb2ac326-610a-401d-bef5-acb599f55ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935357169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3935357169
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1063293492
Short name T116
Test name
Test status
Simulation time 103337409734 ps
CPU time 256.57 seconds
Started May 12 12:27:55 PM PDT 24
Finished May 12 12:32:13 PM PDT 24
Peak memory 190980 kb
Host smart-abc94698-2833-487e-9023-a68965fce4d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063293492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1063293492
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2236067455
Short name T161
Test name
Test status
Simulation time 113680714111 ps
CPU time 330.33 seconds
Started May 12 12:28:03 PM PDT 24
Finished May 12 12:33:35 PM PDT 24
Peak memory 193056 kb
Host smart-059f8317-af44-42b0-84de-d3bb5c3828b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236067455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2236067455
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2385701377
Short name T240
Test name
Test status
Simulation time 61805964673 ps
CPU time 117.14 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:29:57 PM PDT 24
Peak memory 191004 kb
Host smart-349a87ca-8ffb-4278-871b-bb1c0ef80689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385701377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2385701377
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3093999383
Short name T278
Test name
Test status
Simulation time 129688581038 ps
CPU time 199.45 seconds
Started May 12 12:22:03 PM PDT 24
Finished May 12 12:25:23 PM PDT 24
Peak memory 183176 kb
Host smart-6c7d1a2b-cbe8-470f-b2bf-7aa23ac79792
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093999383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3093999383
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1122080731
Short name T390
Test name
Test status
Simulation time 157856528247 ps
CPU time 72.62 seconds
Started May 12 12:21:53 PM PDT 24
Finished May 12 12:23:07 PM PDT 24
Peak memory 182692 kb
Host smart-a388be53-3f3e-4754-8422-c45540e3c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122080731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1122080731
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.542743993
Short name T293
Test name
Test status
Simulation time 169918814114 ps
CPU time 121.01 seconds
Started May 12 12:21:10 PM PDT 24
Finished May 12 12:23:12 PM PDT 24
Peak memory 191068 kb
Host smart-19599a25-b4f7-4870-afb9-6d1f9a9c3e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542743993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.542743993
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3287746035
Short name T349
Test name
Test status
Simulation time 5117774698 ps
CPU time 8.89 seconds
Started May 12 12:22:03 PM PDT 24
Finished May 12 12:22:12 PM PDT 24
Peak memory 195168 kb
Host smart-80ecbc54-8e84-4ed4-854f-248cc14588c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287746035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3287746035
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.605257381
Short name T20
Test name
Test status
Simulation time 132018619 ps
CPU time 0.85 seconds
Started May 12 12:21:01 PM PDT 24
Finished May 12 12:21:03 PM PDT 24
Peak memory 211504 kb
Host smart-8d4ced43-9447-4605-9dc4-be8d163d4576
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605257381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.605257381
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3706910424
Short name T205
Test name
Test status
Simulation time 239207033534 ps
CPU time 228.78 seconds
Started May 12 12:27:07 PM PDT 24
Finished May 12 12:30:56 PM PDT 24
Peak memory 182744 kb
Host smart-4223646d-b36b-4f6f-a900-98e44e108aab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706910424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3706910424
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_random.999064193
Short name T388
Test name
Test status
Simulation time 119256971706 ps
CPU time 73.99 seconds
Started May 12 12:27:18 PM PDT 24
Finished May 12 12:28:33 PM PDT 24
Peak memory 191076 kb
Host smart-5a0cbb8c-b01c-4dcd-baff-e1247e0f8624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999064193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.999064193
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3621270982
Short name T281
Test name
Test status
Simulation time 113071610210 ps
CPU time 1557.39 seconds
Started May 12 12:26:44 PM PDT 24
Finished May 12 12:52:42 PM PDT 24
Peak memory 190980 kb
Host smart-58ae1ed7-f3ec-40aa-9fb3-46d1ff9be61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621270982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3621270982
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.4048107954
Short name T229
Test name
Test status
Simulation time 7611110816 ps
CPU time 13.37 seconds
Started May 12 12:26:57 PM PDT 24
Finished May 12 12:27:11 PM PDT 24
Peak memory 182728 kb
Host smart-f9e0f4fa-0982-4a9c-beae-d0cb98ec3cdd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048107954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.4048107954
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2654645880
Short name T381
Test name
Test status
Simulation time 215152075410 ps
CPU time 86.62 seconds
Started May 12 12:26:58 PM PDT 24
Finished May 12 12:28:26 PM PDT 24
Peak memory 182828 kb
Host smart-dc928cc5-9c15-43b3-9731-2da22a41d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654645880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2654645880
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1770742372
Short name T204
Test name
Test status
Simulation time 675225232446 ps
CPU time 869.76 seconds
Started May 12 12:26:43 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 191008 kb
Host smart-7560efba-ac3f-4a0f-b3d1-8e358b68b609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770742372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1770742372
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4178310069
Short name T360
Test name
Test status
Simulation time 36214428 ps
CPU time 0.5 seconds
Started May 12 12:26:40 PM PDT 24
Finished May 12 12:26:41 PM PDT 24
Peak memory 182568 kb
Host smart-56bdf3df-3abf-475a-a363-c572d71e8839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178310069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4178310069
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.635489180
Short name T194
Test name
Test status
Simulation time 17200445151 ps
CPU time 29.17 seconds
Started May 12 12:26:47 PM PDT 24
Finished May 12 12:27:17 PM PDT 24
Peak memory 182740 kb
Host smart-8b3fc8ff-2b24-4601-a4e8-a6c5217b9cf3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635489180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.635489180
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1814177042
Short name T368
Test name
Test status
Simulation time 389940911137 ps
CPU time 243.35 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:30:52 PM PDT 24
Peak memory 183160 kb
Host smart-470e9e74-74a6-4d5a-90fd-9cd115c00840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814177042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1814177042
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3830898686
Short name T127
Test name
Test status
Simulation time 361323420943 ps
CPU time 310.47 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:32:00 PM PDT 24
Peak memory 182780 kb
Host smart-70d7ff1f-a9aa-4be6-aedb-74eb378c239d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830898686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3830898686
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3282078498
Short name T433
Test name
Test status
Simulation time 58526585146 ps
CPU time 86.55 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:28:15 PM PDT 24
Peak memory 182812 kb
Host smart-9c0203c9-bd5f-482c-8104-88c43a21ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282078498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3282078498
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3840142098
Short name T382
Test name
Test status
Simulation time 7545329075 ps
CPU time 8.78 seconds
Started May 12 12:26:49 PM PDT 24
Finished May 12 12:26:59 PM PDT 24
Peak memory 182748 kb
Host smart-894c9b18-6f49-49d1-97c9-6a7e6e38daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840142098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3840142098
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1915516326
Short name T141
Test name
Test status
Simulation time 660535144194 ps
CPU time 738.04 seconds
Started May 12 12:26:49 PM PDT 24
Finished May 12 12:39:08 PM PDT 24
Peak memory 191096 kb
Host smart-c7b08024-f37c-4162-b0be-094e4a587188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915516326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1915516326
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.263677229
Short name T169
Test name
Test status
Simulation time 28394557566 ps
CPU time 14.52 seconds
Started May 12 12:26:49 PM PDT 24
Finished May 12 12:27:05 PM PDT 24
Peak memory 182884 kb
Host smart-f6639afb-dc0e-454f-9c2d-341b5a20b28d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263677229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.263677229
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3797113756
Short name T376
Test name
Test status
Simulation time 49249137539 ps
CPU time 64.11 seconds
Started May 12 12:26:45 PM PDT 24
Finished May 12 12:27:51 PM PDT 24
Peak memory 182836 kb
Host smart-77656ada-aab3-4f76-a786-bacf32be0c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797113756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3797113756
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.953888400
Short name T314
Test name
Test status
Simulation time 95872814902 ps
CPU time 79.59 seconds
Started May 12 12:26:56 PM PDT 24
Finished May 12 12:28:17 PM PDT 24
Peak memory 190904 kb
Host smart-96bb6551-3adc-4241-8cf8-f14cff164318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953888400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.953888400
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.944584619
Short name T39
Test name
Test status
Simulation time 239247626361 ps
CPU time 78.79 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:28:08 PM PDT 24
Peak memory 182852 kb
Host smart-d2353096-146e-49fe-8164-7a1e45872eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944584619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
944584619
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.4261277753
Short name T389
Test name
Test status
Simulation time 318834484109 ps
CPU time 127.86 seconds
Started May 12 12:26:50 PM PDT 24
Finished May 12 12:28:59 PM PDT 24
Peak memory 182784 kb
Host smart-92463f59-784c-475c-9cd7-2cb30954a75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261277753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.4261277753
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2450466097
Short name T112
Test name
Test status
Simulation time 330919889977 ps
CPU time 511.37 seconds
Started May 12 12:26:47 PM PDT 24
Finished May 12 12:35:20 PM PDT 24
Peak memory 194560 kb
Host smart-b23b537f-0c46-4d82-9ad3-8bd572d79048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450466097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2450466097
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1182191127
Short name T410
Test name
Test status
Simulation time 136047881 ps
CPU time 0.79 seconds
Started May 12 12:26:53 PM PDT 24
Finished May 12 12:26:54 PM PDT 24
Peak memory 182592 kb
Host smart-c20408e4-9040-4abf-9b37-92b65fb2b013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182191127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1182191127
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1049591024
Short name T350
Test name
Test status
Simulation time 243703101340 ps
CPU time 62.34 seconds
Started May 12 12:27:05 PM PDT 24
Finished May 12 12:28:08 PM PDT 24
Peak memory 182772 kb
Host smart-1d387435-3f46-4230-ac68-51c13ec87ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049591024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1049591024
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.4193954751
Short name T44
Test name
Test status
Simulation time 159787827242 ps
CPU time 305.08 seconds
Started May 12 12:26:57 PM PDT 24
Finished May 12 12:32:03 PM PDT 24
Peak memory 205544 kb
Host smart-7e5b77f7-5c70-4d4b-b3ff-537df7b9bb1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193954751 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.4193954751
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4000522965
Short name T313
Test name
Test status
Simulation time 7191673451 ps
CPU time 11.76 seconds
Started May 12 12:26:53 PM PDT 24
Finished May 12 12:27:06 PM PDT 24
Peak memory 182792 kb
Host smart-419041f8-a7ac-4d9c-b1c5-ab1012e8177a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000522965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4000522965
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1238597827
Short name T359
Test name
Test status
Simulation time 29610392968 ps
CPU time 30.79 seconds
Started May 12 12:26:53 PM PDT 24
Finished May 12 12:27:24 PM PDT 24
Peak memory 182820 kb
Host smart-2531a961-6511-45b0-a8d8-61070dc15db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238597827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1238597827
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3464609405
Short name T122
Test name
Test status
Simulation time 84244224998 ps
CPU time 147.68 seconds
Started May 12 12:26:50 PM PDT 24
Finished May 12 12:29:18 PM PDT 24
Peak memory 190976 kb
Host smart-b423669d-55af-4ad5-94ef-a787833a393a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464609405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3464609405
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3441089702
Short name T11
Test name
Test status
Simulation time 1479291968 ps
CPU time 2.88 seconds
Started May 12 12:26:49 PM PDT 24
Finished May 12 12:26:53 PM PDT 24
Peak memory 182612 kb
Host smart-82342943-4773-48e0-8284-b437c81a3c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441089702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3441089702
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2295454092
Short name T237
Test name
Test status
Simulation time 380974427633 ps
CPU time 545 seconds
Started May 12 12:26:49 PM PDT 24
Finished May 12 12:35:55 PM PDT 24
Peak memory 182816 kb
Host smart-4e40a4a8-e43a-4d3e-a44c-8875c563f225
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295454092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2295454092
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.80693171
Short name T423
Test name
Test status
Simulation time 135445198228 ps
CPU time 195.2 seconds
Started May 12 12:26:55 PM PDT 24
Finished May 12 12:30:12 PM PDT 24
Peak memory 182740 kb
Host smart-05bc3a7f-1ace-4ebe-9032-78a494ec3d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80693171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.80693171
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3050435719
Short name T299
Test name
Test status
Simulation time 20299640313 ps
CPU time 21.08 seconds
Started May 12 12:26:49 PM PDT 24
Finished May 12 12:27:11 PM PDT 24
Peak memory 182752 kb
Host smart-860f9f71-bd2b-41f6-9506-0fd75c9d2d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050435719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3050435719
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.4177601582
Short name T285
Test name
Test status
Simulation time 6561824762914 ps
CPU time 1109.55 seconds
Started May 12 12:27:02 PM PDT 24
Finished May 12 12:45:33 PM PDT 24
Peak memory 190980 kb
Host smart-0f8c3c2b-b3a1-4fe1-9811-07e72b0c6011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177601582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.4177601582
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1899356551
Short name T284
Test name
Test status
Simulation time 39316571708 ps
CPU time 22.87 seconds
Started May 12 12:26:55 PM PDT 24
Finished May 12 12:27:20 PM PDT 24
Peak memory 182816 kb
Host smart-e6987242-126a-4dcd-9e58-2481776caba2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899356551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1899356551
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.1209827261
Short name T342
Test name
Test status
Simulation time 261353436107 ps
CPU time 566.1 seconds
Started May 12 12:27:19 PM PDT 24
Finished May 12 12:36:47 PM PDT 24
Peak memory 191044 kb
Host smart-93d86dad-e7ca-4dd2-b557-a5e8eee43470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209827261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1209827261
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.4106419116
Short name T411
Test name
Test status
Simulation time 108771156 ps
CPU time 0.73 seconds
Started May 12 12:26:52 PM PDT 24
Finished May 12 12:26:54 PM PDT 24
Peak memory 182600 kb
Host smart-7a7359d9-487c-422f-95b3-0e20a91c81f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106419116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4106419116
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3338560599
Short name T289
Test name
Test status
Simulation time 130652108582 ps
CPU time 209.27 seconds
Started May 12 12:26:53 PM PDT 24
Finished May 12 12:30:24 PM PDT 24
Peak memory 182796 kb
Host smart-414b5808-f9ab-4645-a873-aa19d5eea787
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338560599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3338560599
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4067586474
Short name T351
Test name
Test status
Simulation time 85332599648 ps
CPU time 71.15 seconds
Started May 12 12:26:54 PM PDT 24
Finished May 12 12:28:07 PM PDT 24
Peak memory 182812 kb
Host smart-20415233-f429-4878-8ec9-f15755d174d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067586474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4067586474
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1351061313
Short name T159
Test name
Test status
Simulation time 196982504276 ps
CPU time 293.89 seconds
Started May 12 12:26:52 PM PDT 24
Finished May 12 12:31:47 PM PDT 24
Peak memory 190924 kb
Host smart-26787a35-bfbd-480c-81d9-50397d4035f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351061313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1351061313
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1362599976
Short name T311
Test name
Test status
Simulation time 93954091748 ps
CPU time 79.36 seconds
Started May 12 12:26:55 PM PDT 24
Finished May 12 12:28:16 PM PDT 24
Peak memory 194196 kb
Host smart-fbf27be9-5a73-4534-b092-51071a9bfe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362599976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1362599976
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4157500461
Short name T47
Test name
Test status
Simulation time 132223775920 ps
CPU time 230.48 seconds
Started May 12 12:26:46 PM PDT 24
Finished May 12 12:30:37 PM PDT 24
Peak memory 181468 kb
Host smart-a0a381b7-3120-4e11-9e2d-baafaff8d507
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157500461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4157500461
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1720194128
Short name T440
Test name
Test status
Simulation time 269269800199 ps
CPU time 182.01 seconds
Started May 12 12:22:03 PM PDT 24
Finished May 12 12:25:05 PM PDT 24
Peak memory 183152 kb
Host smart-3e0a16d3-e101-4e17-ab13-878998ae7046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720194128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1720194128
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.430860365
Short name T148
Test name
Test status
Simulation time 97078743013 ps
CPU time 145.59 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:28:32 PM PDT 24
Peak memory 190652 kb
Host smart-dd357f16-080d-47ea-8269-548ff1b5aba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430860365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.430860365
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2939579195
Short name T329
Test name
Test status
Simulation time 48058802244 ps
CPU time 357.83 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:32:03 PM PDT 24
Peak memory 189836 kb
Host smart-f79bc6fc-917f-4534-bdca-16995a47f68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939579195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2939579195
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2537346195
Short name T22
Test name
Test status
Simulation time 38103041 ps
CPU time 0.76 seconds
Started May 12 12:27:11 PM PDT 24
Finished May 12 12:27:13 PM PDT 24
Peak memory 212096 kb
Host smart-ad9a7f5c-005a-4f0e-a492-8d877220bfec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537346195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2537346195
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3997378480
Short name T366
Test name
Test status
Simulation time 170630707 ps
CPU time 0.55 seconds
Started May 12 12:25:37 PM PDT 24
Finished May 12 12:25:38 PM PDT 24
Peak memory 182556 kb
Host smart-e30a57be-7abc-4633-ac21-13e1dd48eec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997378480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3997378480
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1150995172
Short name T357
Test name
Test status
Simulation time 46974620339 ps
CPU time 65.17 seconds
Started May 12 12:27:01 PM PDT 24
Finished May 12 12:28:07 PM PDT 24
Peak memory 183160 kb
Host smart-2c75aff5-c25a-4ab4-a47c-bb2518186312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150995172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1150995172
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3221943463
Short name T361
Test name
Test status
Simulation time 13571101 ps
CPU time 0.53 seconds
Started May 12 12:27:04 PM PDT 24
Finished May 12 12:27:05 PM PDT 24
Peak memory 182564 kb
Host smart-f5a8ddc6-2df0-4dde-b3f5-d137253ec3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221943463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3221943463
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.363766481
Short name T41
Test name
Test status
Simulation time 19500133483 ps
CPU time 237.74 seconds
Started May 12 12:26:57 PM PDT 24
Finished May 12 12:30:56 PM PDT 24
Peak memory 206084 kb
Host smart-fcd9a112-7e8c-4039-a437-a6e7de23b7d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363766481 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.363766481
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.635219739
Short name T53
Test name
Test status
Simulation time 2278905790 ps
CPU time 4.6 seconds
Started May 12 12:26:58 PM PDT 24
Finished May 12 12:27:04 PM PDT 24
Peak memory 183236 kb
Host smart-f1673af0-c18f-4312-aa4e-9583640b4f9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635219739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.635219739
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.392470194
Short name T65
Test name
Test status
Simulation time 848382616525 ps
CPU time 212.26 seconds
Started May 12 12:26:57 PM PDT 24
Finished May 12 12:30:30 PM PDT 24
Peak memory 182728 kb
Host smart-52f3def1-e985-4d69-8c35-df6132d16379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392470194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.392470194
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.4222839707
Short name T315
Test name
Test status
Simulation time 45457487777 ps
CPU time 83.78 seconds
Started May 12 12:26:56 PM PDT 24
Finished May 12 12:28:21 PM PDT 24
Peak memory 182764 kb
Host smart-46e7cded-e38c-41cd-9c45-3c272477dc48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222839707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4222839707
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2100765899
Short name T63
Test name
Test status
Simulation time 42724435928 ps
CPU time 36.1 seconds
Started May 12 12:27:06 PM PDT 24
Finished May 12 12:27:43 PM PDT 24
Peak memory 182780 kb
Host smart-a79865d5-75ce-435d-a291-5679ca4ff2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100765899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2100765899
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.88571379
Short name T414
Test name
Test status
Simulation time 572101420422 ps
CPU time 782.68 seconds
Started May 12 12:28:01 PM PDT 24
Finished May 12 12:41:05 PM PDT 24
Peak memory 190952 kb
Host smart-cde36502-9f3a-4c21-adb0-caae2b0d33e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88571379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.88571379
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2342341828
Short name T439
Test name
Test status
Simulation time 22721789540 ps
CPU time 12.68 seconds
Started May 12 12:27:59 PM PDT 24
Finished May 12 12:28:14 PM PDT 24
Peak memory 182736 kb
Host smart-eeb2843f-5c35-45bf-921f-ba60b27b67fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342341828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2342341828
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.872091567
Short name T385
Test name
Test status
Simulation time 19494157832 ps
CPU time 32.52 seconds
Started May 12 12:27:04 PM PDT 24
Finished May 12 12:27:38 PM PDT 24
Peak memory 182768 kb
Host smart-14e34f3f-67df-4240-b86d-e47392c48d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872091567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.872091567
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.4084937321
Short name T48
Test name
Test status
Simulation time 623635414298 ps
CPU time 260.7 seconds
Started May 12 12:28:09 PM PDT 24
Finished May 12 12:32:32 PM PDT 24
Peak memory 190980 kb
Host smart-a355f8bd-5838-4ae6-bc22-f01c8661f1bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084937321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4084937321
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3537308810
Short name T246
Test name
Test status
Simulation time 4362484655 ps
CPU time 7.16 seconds
Started May 12 12:27:02 PM PDT 24
Finished May 12 12:27:09 PM PDT 24
Peak memory 182656 kb
Host smart-ecce9b35-fc77-4bb2-ab62-fd17726f3d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537308810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3537308810
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.135777004
Short name T319
Test name
Test status
Simulation time 37081847078 ps
CPU time 57.04 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:28:07 PM PDT 24
Peak memory 182788 kb
Host smart-4996255c-035f-4119-ad51-3fe745bbb664
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135777004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.135777004
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3448575978
Short name T353
Test name
Test status
Simulation time 223579840279 ps
CPU time 154.58 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:29:45 PM PDT 24
Peak memory 182656 kb
Host smart-7cc11687-6178-4f9e-93b2-e9285c3e7a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448575978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3448575978
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2200800
Short name T417
Test name
Test status
Simulation time 1799448419 ps
CPU time 3.66 seconds
Started May 12 12:27:01 PM PDT 24
Finished May 12 12:27:05 PM PDT 24
Peak memory 182956 kb
Host smart-ce487aee-f139-4776-b770-ea664d6d7b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2200800
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1817206708
Short name T373
Test name
Test status
Simulation time 44264490 ps
CPU time 0.52 seconds
Started May 12 12:27:50 PM PDT 24
Finished May 12 12:27:52 PM PDT 24
Peak memory 182548 kb
Host smart-0cc311c7-00f4-423a-87e7-7397de6758b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817206708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1817206708
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3880810532
Short name T13
Test name
Test status
Simulation time 168301766851 ps
CPU time 267.4 seconds
Started May 12 12:27:04 PM PDT 24
Finished May 12 12:31:33 PM PDT 24
Peak memory 190964 kb
Host smart-e4573b8b-f3bb-40bf-b014-badb8428c5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880810532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3880810532
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.220012065
Short name T224
Test name
Test status
Simulation time 687586537904 ps
CPU time 393.85 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:33:45 PM PDT 24
Peak memory 182736 kb
Host smart-db84ddd3-4b0b-4082-bdbe-856d4c2f6fdd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220012065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.220012065
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3299885657
Short name T434
Test name
Test status
Simulation time 71174839224 ps
CPU time 99.98 seconds
Started May 12 12:27:43 PM PDT 24
Finished May 12 12:29:24 PM PDT 24
Peak memory 182748 kb
Host smart-136747b9-98d5-4bca-b4d4-17d84e4660b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299885657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3299885657
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.8587087
Short name T266
Test name
Test status
Simulation time 77270163678 ps
CPU time 297.81 seconds
Started May 12 12:27:00 PM PDT 24
Finished May 12 12:31:58 PM PDT 24
Peak memory 182844 kb
Host smart-aeccb829-dc86-4c4e-b1b5-a357acb4d679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8587087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.8587087
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.4230445895
Short name T404
Test name
Test status
Simulation time 128511943 ps
CPU time 1.16 seconds
Started May 12 12:27:02 PM PDT 24
Finished May 12 12:27:04 PM PDT 24
Peak memory 182748 kb
Host smart-6c4f022d-9dce-47b2-960b-9def448ee736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230445895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.4230445895
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2376630123
Short name T343
Test name
Test status
Simulation time 400020774334 ps
CPU time 222.26 seconds
Started May 12 12:28:10 PM PDT 24
Finished May 12 12:31:54 PM PDT 24
Peak memory 190928 kb
Host smart-455c4517-1006-4596-b509-cc9e2e4b5b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376630123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2376630123
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3374255045
Short name T183
Test name
Test status
Simulation time 110149819511 ps
CPU time 203.22 seconds
Started May 12 12:27:05 PM PDT 24
Finished May 12 12:30:29 PM PDT 24
Peak memory 182768 kb
Host smart-b7152fd0-3290-4fea-a684-67e3339b2036
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374255045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3374255045
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2813163731
Short name T386
Test name
Test status
Simulation time 122502203881 ps
CPU time 207.71 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:30:43 PM PDT 24
Peak memory 182672 kb
Host smart-53db8119-cfd9-4d2d-8c71-ace003d72b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813163731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2813163731
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3386128056
Short name T4
Test name
Test status
Simulation time 35781443685 ps
CPU time 594.35 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:37:04 PM PDT 24
Peak memory 182784 kb
Host smart-80bb0f34-b2ea-4a9b-b433-76b0b8736f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386128056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3386128056
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3718392034
Short name T431
Test name
Test status
Simulation time 123353694 ps
CPU time 0.86 seconds
Started May 12 12:27:15 PM PDT 24
Finished May 12 12:27:18 PM PDT 24
Peak memory 192344 kb
Host smart-b5025c42-efe3-42fc-aba7-ef0557b58fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718392034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3718392034
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3132783434
Short name T337
Test name
Test status
Simulation time 1017022041565 ps
CPU time 1709.05 seconds
Started May 12 12:27:13 PM PDT 24
Finished May 12 12:55:44 PM PDT 24
Peak memory 194220 kb
Host smart-1bccc7d1-5e16-4edc-9497-56faffc9d3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132783434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3132783434
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2290701864
Short name T306
Test name
Test status
Simulation time 19299051731 ps
CPU time 18.89 seconds
Started May 12 12:27:04 PM PDT 24
Finished May 12 12:27:24 PM PDT 24
Peak memory 182796 kb
Host smart-2e2a0432-195c-4fd1-bf61-bb21062db20a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290701864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2290701864
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2879762256
Short name T365
Test name
Test status
Simulation time 910533914547 ps
CPU time 369.4 seconds
Started May 12 12:27:13 PM PDT 24
Finished May 12 12:33:25 PM PDT 24
Peak memory 182772 kb
Host smart-a44b5303-e944-4b54-a3d9-ddcdea1036d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879762256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2879762256
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.1625920177
Short name T16
Test name
Test status
Simulation time 296720490432 ps
CPU time 567.05 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:36:42 PM PDT 24
Peak memory 205516 kb
Host smart-c6bf7419-6ee9-4f1b-a5dc-05948a2c4441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625920177 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.1625920177
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.388955945
Short name T305
Test name
Test status
Simulation time 960713470008 ps
CPU time 544.03 seconds
Started May 12 12:27:08 PM PDT 24
Finished May 12 12:36:13 PM PDT 24
Peak memory 182784 kb
Host smart-87452d76-b172-4bae-ac3c-3bf2a52da097
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388955945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.388955945
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2381600198
Short name T7
Test name
Test status
Simulation time 410771735405 ps
CPU time 337.04 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:32:47 PM PDT 24
Peak memory 182748 kb
Host smart-9faeb4ef-da73-4c1d-aafc-d7a69b11d3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381600198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2381600198
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3057758402
Short name T175
Test name
Test status
Simulation time 2094120747945 ps
CPU time 339.33 seconds
Started May 12 12:27:13 PM PDT 24
Finished May 12 12:32:54 PM PDT 24
Peak memory 191004 kb
Host smart-a615f0b0-6dfc-4a80-bf54-d241846614ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057758402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3057758402
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2168606400
Short name T399
Test name
Test status
Simulation time 169579373366 ps
CPU time 93.84 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:28:45 PM PDT 24
Peak memory 190996 kb
Host smart-4567d3a9-d0f6-4691-88bd-1ea2f286d2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168606400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2168606400
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1303531132
Short name T257
Test name
Test status
Simulation time 497275875690 ps
CPU time 265.27 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:31:35 PM PDT 24
Peak memory 182784 kb
Host smart-51986212-6857-4f6b-89e2-30263590aa8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303531132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1303531132
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3864267764
Short name T435
Test name
Test status
Simulation time 167994641078 ps
CPU time 270.73 seconds
Started May 12 12:27:06 PM PDT 24
Finished May 12 12:31:38 PM PDT 24
Peak memory 182820 kb
Host smart-1fe167cc-49af-4d73-8e80-946b07a25c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864267764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3864267764
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1713750920
Short name T380
Test name
Test status
Simulation time 182807828886 ps
CPU time 165.78 seconds
Started May 12 12:27:15 PM PDT 24
Finished May 12 12:30:02 PM PDT 24
Peak memory 191048 kb
Host smart-37d140bf-6b69-45c4-9753-2c28d274d481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713750920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1713750920
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4113487656
Short name T444
Test name
Test status
Simulation time 265907630 ps
CPU time 1.52 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:27:17 PM PDT 24
Peak memory 183148 kb
Host smart-a1bea290-987f-4b6c-8f42-615211469011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113487656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4113487656
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4283842149
Short name T31
Test name
Test status
Simulation time 243842556277 ps
CPU time 163.63 seconds
Started May 12 12:28:03 PM PDT 24
Finished May 12 12:30:49 PM PDT 24
Peak memory 190936 kb
Host smart-e0de804b-0ec7-4873-83ea-608a9d8dcf33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283842149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4283842149
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.2175447782
Short name T272
Test name
Test status
Simulation time 299149310300 ps
CPU time 164.04 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:30:00 PM PDT 24
Peak memory 191000 kb
Host smart-97fe6d7c-0a0c-4a5c-aa10-de35b86348d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175447782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2175447782
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1729216078
Short name T424
Test name
Test status
Simulation time 141212552399 ps
CPU time 103.61 seconds
Started May 12 12:27:13 PM PDT 24
Finished May 12 12:28:58 PM PDT 24
Peak memory 182736 kb
Host smart-78e82b4a-8bd3-4f66-be79-56f911d6e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729216078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1729216078
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4208790422
Short name T1
Test name
Test status
Simulation time 71929552279 ps
CPU time 110.02 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:27:56 PM PDT 24
Peak memory 181584 kb
Host smart-86953638-5806-4d28-a8e1-b9e4325d51ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208790422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.4208790422
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3200839003
Short name T362
Test name
Test status
Simulation time 105628239340 ps
CPU time 72.59 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:27:19 PM PDT 24
Peak memory 181656 kb
Host smart-3308541a-7c91-4a15-91a5-235ff394cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200839003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3200839003
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2814816915
Short name T265
Test name
Test status
Simulation time 259862555818 ps
CPU time 432.09 seconds
Started May 12 12:26:06 PM PDT 24
Finished May 12 12:33:19 PM PDT 24
Peak memory 190648 kb
Host smart-95d59a92-28ef-4817-9be7-76001f131768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814816915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2814816915
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3362598982
Short name T335
Test name
Test status
Simulation time 49750527099 ps
CPU time 137.95 seconds
Started May 12 12:22:59 PM PDT 24
Finished May 12 12:25:18 PM PDT 24
Peak memory 190992 kb
Host smart-d30e302d-5e22-49e8-beab-7489fb90dfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362598982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3362598982
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2962585924
Short name T21
Test name
Test status
Simulation time 362382532 ps
CPU time 0.96 seconds
Started May 12 12:21:54 PM PDT 24
Finished May 12 12:21:56 PM PDT 24
Peak memory 214664 kb
Host smart-8bfcca8c-41a8-4d72-89d6-2316a826a486
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962585924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2962585924
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3940082811
Short name T174
Test name
Test status
Simulation time 364438848636 ps
CPU time 554.96 seconds
Started May 12 12:21:50 PM PDT 24
Finished May 12 12:31:05 PM PDT 24
Peak memory 193148 kb
Host smart-2c89cd9f-2442-4cbc-97da-0f05009d8f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940082811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3940082811
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1883376305
Short name T420
Test name
Test status
Simulation time 5013385005 ps
CPU time 8.75 seconds
Started May 12 12:28:11 PM PDT 24
Finished May 12 12:28:21 PM PDT 24
Peak memory 182768 kb
Host smart-919ed62c-c479-475f-aba9-151946b93b08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883376305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1883376305
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1312544255
Short name T356
Test name
Test status
Simulation time 99402201287 ps
CPU time 140.11 seconds
Started May 12 12:27:18 PM PDT 24
Finished May 12 12:29:39 PM PDT 24
Peak memory 182772 kb
Host smart-b00d7324-ce79-4a96-a30e-33696bbe9013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312544255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1312544255
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2369038847
Short name T62
Test name
Test status
Simulation time 145311847861 ps
CPU time 697.56 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:39:02 PM PDT 24
Peak memory 182796 kb
Host smart-7be61532-6c86-4b0a-8cb6-ed2866731c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369038847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2369038847
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1399488814
Short name T72
Test name
Test status
Simulation time 13945415701 ps
CPU time 21.57 seconds
Started May 12 12:27:15 PM PDT 24
Finished May 12 12:27:38 PM PDT 24
Peak memory 182772 kb
Host smart-12cccafb-e5dd-4781-8efb-7504cf59a917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399488814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1399488814
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.103137803
Short name T426
Test name
Test status
Simulation time 186068591761 ps
CPU time 540.81 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:36:25 PM PDT 24
Peak memory 191004 kb
Host smart-178b7f7d-1f62-476a-8c21-098db3a03880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103137803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
103137803
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.375636973
Short name T45
Test name
Test status
Simulation time 10938887287 ps
CPU time 81.55 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:28:37 PM PDT 24
Peak memory 194112 kb
Host smart-5cfc5b6b-6882-4a7a-b6da-a2fd901d4479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375636973 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.375636973
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.675431107
Short name T442
Test name
Test status
Simulation time 197480659434 ps
CPU time 343.57 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:33:08 PM PDT 24
Peak memory 182816 kb
Host smart-60037492-c18f-4a30-8a0c-5a51383e207d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675431107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.675431107
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2648854557
Short name T438
Test name
Test status
Simulation time 169873855162 ps
CPU time 252.06 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:31:28 PM PDT 24
Peak memory 182784 kb
Host smart-445aa0dc-1063-4f8c-a190-5d34b978f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648854557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2648854557
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3607570945
Short name T267
Test name
Test status
Simulation time 189996505093 ps
CPU time 870.41 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:41:47 PM PDT 24
Peak memory 195000 kb
Host smart-02ca41a3-60e9-4262-bfc5-5c51ffbfafc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607570945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3607570945
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.608376017
Short name T25
Test name
Test status
Simulation time 32377355901 ps
CPU time 28.36 seconds
Started May 12 12:27:19 PM PDT 24
Finished May 12 12:27:48 PM PDT 24
Peak memory 182772 kb
Host smart-22c1808b-493e-4b33-8a92-0c15e269580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608376017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.608376017
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2367485083
Short name T197
Test name
Test status
Simulation time 154501173601 ps
CPU time 138.94 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:29:35 PM PDT 24
Peak memory 183212 kb
Host smart-d4382ad9-50f0-4596-a0c0-251cf68f7299
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367485083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2367485083
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1883908944
Short name T352
Test name
Test status
Simulation time 53005016763 ps
CPU time 19.78 seconds
Started May 12 12:27:17 PM PDT 24
Finished May 12 12:27:38 PM PDT 24
Peak memory 182884 kb
Host smart-2e12978c-f81e-41ab-9ec1-1c26b5982f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883908944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1883908944
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2586490556
Short name T317
Test name
Test status
Simulation time 848692305536 ps
CPU time 289.91 seconds
Started May 12 12:28:11 PM PDT 24
Finished May 12 12:33:03 PM PDT 24
Peak memory 191108 kb
Host smart-88528f6b-8922-4138-bfc8-2899f3716e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586490556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2586490556
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1425212593
Short name T145
Test name
Test status
Simulation time 523457363141 ps
CPU time 321.84 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:32:46 PM PDT 24
Peak memory 191016 kb
Host smart-a6db1be3-94ea-4661-8836-3e387a9650cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425212593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1425212593
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3501827051
Short name T70
Test name
Test status
Simulation time 384013522944 ps
CPU time 345.16 seconds
Started May 12 12:27:15 PM PDT 24
Finished May 12 12:33:02 PM PDT 24
Peak memory 190984 kb
Host smart-08a91f99-84f0-4e1c-bbd9-42e27f60d276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501827051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3501827051
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.3057572119
Short name T42
Test name
Test status
Simulation time 378888056628 ps
CPU time 812.4 seconds
Started May 12 12:27:24 PM PDT 24
Finished May 12 12:40:58 PM PDT 24
Peak memory 209952 kb
Host smart-39ed5649-8f29-4854-b862-ecb4bb8f5a7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057572119 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.3057572119
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1239100647
Short name T283
Test name
Test status
Simulation time 74432968781 ps
CPU time 123.89 seconds
Started May 12 12:27:16 PM PDT 24
Finished May 12 12:29:21 PM PDT 24
Peak memory 182768 kb
Host smart-8c8284ff-167c-4b38-978c-453fb85e11bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239100647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1239100647
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1351094452
Short name T443
Test name
Test status
Simulation time 109082273553 ps
CPU time 38.05 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:28:02 PM PDT 24
Peak memory 182816 kb
Host smart-55136411-a4da-451b-9612-a11917f50b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351094452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1351094452
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.4128434276
Short name T138
Test name
Test status
Simulation time 366137940700 ps
CPU time 430.24 seconds
Started May 12 12:27:16 PM PDT 24
Finished May 12 12:34:27 PM PDT 24
Peak memory 190944 kb
Host smart-a95f8a02-c624-4465-9e4f-e6f4d23971d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128434276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4128434276
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2946110502
Short name T38
Test name
Test status
Simulation time 64257059 ps
CPU time 0.51 seconds
Started May 12 12:27:34 PM PDT 24
Finished May 12 12:27:35 PM PDT 24
Peak memory 182548 kb
Host smart-9ea23f7b-93b1-4b24-903b-0ec8309fb002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946110502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2946110502
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.4069697008
Short name T46
Test name
Test status
Simulation time 93943138579 ps
CPU time 245.16 seconds
Started May 12 12:27:16 PM PDT 24
Finished May 12 12:31:22 PM PDT 24
Peak memory 197508 kb
Host smart-3ddfb3c7-47c4-44ae-be42-ae4d82397098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069697008 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.4069697008
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3500566820
Short name T100
Test name
Test status
Simulation time 226209399250 ps
CPU time 127.38 seconds
Started May 12 12:27:15 PM PDT 24
Finished May 12 12:29:24 PM PDT 24
Peak memory 182788 kb
Host smart-dd4ebdf1-0402-4e5c-ad58-7bf3495d3dc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500566820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3500566820
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1891746480
Short name T422
Test name
Test status
Simulation time 117836246641 ps
CPU time 165.42 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:30:01 PM PDT 24
Peak memory 182728 kb
Host smart-36de1d65-3bd4-46b9-9a50-9c54586849cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891746480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1891746480
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.244488076
Short name T309
Test name
Test status
Simulation time 40062680596 ps
CPU time 66.27 seconds
Started May 12 12:27:14 PM PDT 24
Finished May 12 12:28:22 PM PDT 24
Peak memory 182768 kb
Host smart-88de56f9-55f6-40e8-ac96-31cb228b92bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244488076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.244488076
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3426091939
Short name T326
Test name
Test status
Simulation time 425268205714 ps
CPU time 262.32 seconds
Started May 12 12:27:19 PM PDT 24
Finished May 12 12:31:42 PM PDT 24
Peak memory 182792 kb
Host smart-e87e60a8-0bbc-41e5-b0e4-a5ba9879a090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426091939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3426091939
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2128073441
Short name T140
Test name
Test status
Simulation time 516639467267 ps
CPU time 285.37 seconds
Started May 12 12:27:24 PM PDT 24
Finished May 12 12:32:11 PM PDT 24
Peak memory 191000 kb
Host smart-4d84d51c-8530-4aa0-bde5-811e108a6427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128073441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2128073441
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.115083755
Short name T441
Test name
Test status
Simulation time 5155297871 ps
CPU time 8.6 seconds
Started May 12 12:27:24 PM PDT 24
Finished May 12 12:27:34 PM PDT 24
Peak memory 182764 kb
Host smart-2024248b-605a-42e6-9a69-29e7bb305ab3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115083755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.115083755
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1452723332
Short name T383
Test name
Test status
Simulation time 673065903245 ps
CPU time 127.74 seconds
Started May 12 12:28:03 PM PDT 24
Finished May 12 12:30:13 PM PDT 24
Peak memory 182748 kb
Host smart-f6cdd786-b243-4208-9828-78b630aa3a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452723332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1452723332
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2733816897
Short name T429
Test name
Test status
Simulation time 1420967198 ps
CPU time 1.69 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:27:30 PM PDT 24
Peak memory 193600 kb
Host smart-539e1290-4ff0-4b91-922d-332249128e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733816897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2733816897
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3737810261
Short name T125
Test name
Test status
Simulation time 744768358761 ps
CPU time 990.44 seconds
Started May 12 12:27:18 PM PDT 24
Finished May 12 12:43:49 PM PDT 24
Peak memory 191004 kb
Host smart-def45ddc-018d-4856-a45e-64d9e9d8637c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737810261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3737810261
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2768215541
Short name T24
Test name
Test status
Simulation time 1664186964719 ps
CPU time 1662.65 seconds
Started May 12 12:27:51 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 182792 kb
Host smart-6e065238-8701-4227-a8e9-9c6170de1319
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768215541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2768215541
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3649743496
Short name T375
Test name
Test status
Simulation time 67115548369 ps
CPU time 100.65 seconds
Started May 12 12:28:01 PM PDT 24
Finished May 12 12:29:44 PM PDT 24
Peak memory 182760 kb
Host smart-1e288c70-eeef-49b8-95d4-ac56e92f1095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649743496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3649743496
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.566712254
Short name T387
Test name
Test status
Simulation time 167636980 ps
CPU time 0.64 seconds
Started May 12 12:27:24 PM PDT 24
Finished May 12 12:27:26 PM PDT 24
Peak memory 182532 kb
Host smart-8cbac530-974d-40fc-9a6a-15a9884cc291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566712254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.566712254
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2933766556
Short name T369
Test name
Test status
Simulation time 226222701893 ps
CPU time 179.73 seconds
Started May 12 12:27:17 PM PDT 24
Finished May 12 12:30:18 PM PDT 24
Peak memory 182900 kb
Host smart-9ccb5980-eae7-4107-9997-046f21896939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933766556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2933766556
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3369453040
Short name T364
Test name
Test status
Simulation time 169455246566 ps
CPU time 198.12 seconds
Started May 12 12:27:20 PM PDT 24
Finished May 12 12:30:39 PM PDT 24
Peak memory 182772 kb
Host smart-232958b2-1f0b-45ea-af67-bcf7729a2eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369453040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3369453040
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.191617594
Short name T207
Test name
Test status
Simulation time 31166002285 ps
CPU time 31.11 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:28:00 PM PDT 24
Peak memory 183212 kb
Host smart-bc7af6d0-c814-48e8-a428-062cf7b57423
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191617594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.191617594
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2646458523
Short name T321
Test name
Test status
Simulation time 158973466641 ps
CPU time 79.82 seconds
Started May 12 12:27:29 PM PDT 24
Finished May 12 12:28:50 PM PDT 24
Peak memory 182748 kb
Host smart-5b0d72d1-2bb2-46eb-aa71-2f870edd5a14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646458523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2646458523
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1105843072
Short name T384
Test name
Test status
Simulation time 16416995 ps
CPU time 0.54 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:27:29 PM PDT 24
Peak memory 182628 kb
Host smart-1526a517-2059-4a5a-9f50-73139d1ceda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105843072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1105843072
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1150267
Short name T153
Test name
Test status
Simulation time 1723890311616 ps
CPU time 614.13 seconds
Started May 12 12:27:22 PM PDT 24
Finished May 12 12:37:37 PM PDT 24
Peak memory 182776 kb
Host smart-ecc00a40-ed4b-4638-83e9-fd0dda5a6a6f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
rv_timer_cfg_update_on_fly.1150267
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.260881453
Short name T407
Test name
Test status
Simulation time 129234332172 ps
CPU time 180.89 seconds
Started May 12 12:27:26 PM PDT 24
Finished May 12 12:30:27 PM PDT 24
Peak memory 182748 kb
Host smart-51aaf5c0-efe2-4376-a1fd-d3ffa263c669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260881453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.260881453
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2942872224
Short name T200
Test name
Test status
Simulation time 4482304073 ps
CPU time 5.08 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:27:34 PM PDT 24
Peak memory 182912 kb
Host smart-0dda3e96-ab24-4cba-bfdc-d505e881932a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942872224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2942872224
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.988526173
Short name T146
Test name
Test status
Simulation time 37465713486 ps
CPU time 68.14 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:28:38 PM PDT 24
Peak memory 182816 kb
Host smart-c0494d77-c817-4e87-bbd2-c8f411adbd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988526173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.988526173
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2594270552
Short name T330
Test name
Test status
Simulation time 2559509860223 ps
CPU time 1518.12 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:52:43 PM PDT 24
Peak memory 190928 kb
Host smart-4bfaada9-82f1-4ad3-9d4c-b27cf9c06ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594270552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2594270552
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3387199351
Short name T9
Test name
Test status
Simulation time 436219870793 ps
CPU time 253.15 seconds
Started May 12 12:25:14 PM PDT 24
Finished May 12 12:29:27 PM PDT 24
Peak memory 182772 kb
Host smart-5bc58481-cd88-4c83-a846-a838c0b62d6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387199351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3387199351
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.501405830
Short name T354
Test name
Test status
Simulation time 46706524109 ps
CPU time 72.51 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:27:18 PM PDT 24
Peak memory 182432 kb
Host smart-4e8511d6-e8c4-434f-9a09-2443ba55e890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501405830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.501405830
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2727508106
Short name T250
Test name
Test status
Simulation time 145274315613 ps
CPU time 167.18 seconds
Started May 12 12:26:47 PM PDT 24
Finished May 12 12:29:34 PM PDT 24
Peak memory 190656 kb
Host smart-ec499e50-c710-4ad5-abf3-4eafa7e1528a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727508106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2727508106
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3780528761
Short name T268
Test name
Test status
Simulation time 232152189873 ps
CPU time 124.59 seconds
Started May 12 12:27:22 PM PDT 24
Finished May 12 12:29:27 PM PDT 24
Peak memory 190968 kb
Host smart-e143e486-d618-4c98-8d68-3500605f3aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780528761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3780528761
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3198966628
Short name T402
Test name
Test status
Simulation time 82753657246 ps
CPU time 124.01 seconds
Started May 12 12:27:21 PM PDT 24
Finished May 12 12:29:26 PM PDT 24
Peak memory 190988 kb
Host smart-caf21f80-4cd4-402f-94b1-a1bebb2190cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198966628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3198966628
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4054955986
Short name T149
Test name
Test status
Simulation time 62403803011 ps
CPU time 100.74 seconds
Started May 12 12:27:32 PM PDT 24
Finished May 12 12:29:14 PM PDT 24
Peak memory 191364 kb
Host smart-2e0824b4-dae2-49c3-b986-40d5fbb7fc9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054955986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4054955986
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2692395595
Short name T14
Test name
Test status
Simulation time 110290410468 ps
CPU time 306.07 seconds
Started May 12 12:27:24 PM PDT 24
Finished May 12 12:32:31 PM PDT 24
Peak memory 190924 kb
Host smart-baeb91ea-73d4-40fd-b145-85e940b129bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692395595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2692395595
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2782956150
Short name T227
Test name
Test status
Simulation time 32144786332 ps
CPU time 138.45 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:29:42 PM PDT 24
Peak memory 190960 kb
Host smart-0cc37435-b47c-492a-831e-2e7647796a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782956150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2782956150
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2196887062
Short name T132
Test name
Test status
Simulation time 193545880668 ps
CPU time 378.83 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:33:48 PM PDT 24
Peak memory 191448 kb
Host smart-cba7e7ae-dd61-41a6-a00e-7d40a3906ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196887062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2196887062
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3609891579
Short name T345
Test name
Test status
Simulation time 77544243475 ps
CPU time 154.38 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:29:59 PM PDT 24
Peak memory 191052 kb
Host smart-527db0eb-a745-4f64-b5ba-d408abe312a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609891579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3609891579
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.888234369
Short name T121
Test name
Test status
Simulation time 180658596816 ps
CPU time 262.84 seconds
Started May 12 12:27:23 PM PDT 24
Finished May 12 12:31:47 PM PDT 24
Peak memory 193316 kb
Host smart-0704aff8-929e-440f-ae3d-90e0f7160381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888234369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.888234369
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1410211645
Short name T170
Test name
Test status
Simulation time 153653553882 ps
CPU time 1700.12 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:56:21 PM PDT 24
Peak memory 190928 kb
Host smart-a549c43e-e976-489c-b935-bad7afb6b2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410211645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1410211645
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2321895769
Short name T367
Test name
Test status
Simulation time 707289420330 ps
CPU time 281.65 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:30:48 PM PDT 24
Peak memory 181884 kb
Host smart-d28b5cda-1ada-4cb6-9fc9-2bda66da4e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321895769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2321895769
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1376796867
Short name T341
Test name
Test status
Simulation time 78703985443 ps
CPU time 636.66 seconds
Started May 12 12:26:47 PM PDT 24
Finished May 12 12:37:25 PM PDT 24
Peak memory 193384 kb
Host smart-88ad2bd2-b655-4199-a37d-abd183209037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376796867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1376796867
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3217171224
Short name T241
Test name
Test status
Simulation time 365804335292 ps
CPU time 572.78 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:36:21 PM PDT 24
Peak memory 190732 kb
Host smart-4aedf193-7968-4bca-9a45-8675a4da79c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217171224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3217171224
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3530361460
Short name T123
Test name
Test status
Simulation time 626075890704 ps
CPU time 137.53 seconds
Started May 12 12:27:31 PM PDT 24
Finished May 12 12:29:55 PM PDT 24
Peak memory 182748 kb
Host smart-afe63178-af3d-4994-a2b7-f206ffb5a446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530361460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3530361460
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2251155421
Short name T136
Test name
Test status
Simulation time 164021237367 ps
CPU time 455.39 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:35:05 PM PDT 24
Peak memory 191140 kb
Host smart-7d9d08d5-a110-4ec1-bbe7-bfb7a0692107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251155421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2251155421
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3204372074
Short name T195
Test name
Test status
Simulation time 120227883053 ps
CPU time 1357.58 seconds
Started May 12 12:27:30 PM PDT 24
Finished May 12 12:50:08 PM PDT 24
Peak memory 190968 kb
Host smart-458f649c-bd99-42fd-8f07-0108c1409ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204372074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3204372074
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4168786223
Short name T214
Test name
Test status
Simulation time 307456704318 ps
CPU time 160.31 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:30:10 PM PDT 24
Peak memory 191416 kb
Host smart-c0e6f710-65a2-4be0-8454-a5afe012e6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168786223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4168786223
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2286495948
Short name T412
Test name
Test status
Simulation time 175097411312 ps
CPU time 82.93 seconds
Started May 12 12:27:30 PM PDT 24
Finished May 12 12:28:54 PM PDT 24
Peak memory 190836 kb
Host smart-1b5537a3-544e-4ba0-b28c-94d583ae7ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286495948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2286495948
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3939387732
Short name T447
Test name
Test status
Simulation time 152873142408 ps
CPU time 215.95 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:31:05 PM PDT 24
Peak memory 191440 kb
Host smart-9a72e2f5-09af-4be8-96c6-ac44a3ab15bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939387732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3939387732
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2423034540
Short name T338
Test name
Test status
Simulation time 255731751645 ps
CPU time 122.25 seconds
Started May 12 12:27:22 PM PDT 24
Finished May 12 12:29:25 PM PDT 24
Peak memory 194412 kb
Host smart-b1ad5e17-496a-4aba-93d4-37a99fe21002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423034540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2423034540
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3576826100
Short name T222
Test name
Test status
Simulation time 204088090147 ps
CPU time 165.19 seconds
Started May 12 12:27:43 PM PDT 24
Finished May 12 12:30:28 PM PDT 24
Peak memory 193316 kb
Host smart-50cdc657-c43c-4d1b-b97d-2827d9af765e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576826100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3576826100
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.56754098
Short name T217
Test name
Test status
Simulation time 2299136196159 ps
CPU time 1767.38 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:56:56 PM PDT 24
Peak memory 190984 kb
Host smart-1a895e7c-b598-4a9c-b107-d2c47f4f1f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56754098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.56754098
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.460820104
Short name T259
Test name
Test status
Simulation time 50600354999 ps
CPU time 142.14 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:29:51 PM PDT 24
Peak memory 182720 kb
Host smart-32fafda4-6465-4cdd-a06b-379e053ccdca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460820104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.460820104
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.344771976
Short name T432
Test name
Test status
Simulation time 331805770792 ps
CPU time 129.99 seconds
Started May 12 12:26:47 PM PDT 24
Finished May 12 12:28:58 PM PDT 24
Peak memory 182468 kb
Host smart-806060a7-e0ef-476f-bd12-9aae02ebf486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344771976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.344771976
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3084855550
Short name T54
Test name
Test status
Simulation time 137283913103 ps
CPU time 117.73 seconds
Started May 12 12:26:47 PM PDT 24
Finished May 12 12:28:46 PM PDT 24
Peak memory 190704 kb
Host smart-4e1adb74-9ded-4ab8-b527-e570dc8c52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084855550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3084855550
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3470588315
Short name T12
Test name
Test status
Simulation time 196669641279 ps
CPU time 81.22 seconds
Started May 12 12:26:46 PM PDT 24
Finished May 12 12:28:08 PM PDT 24
Peak memory 190616 kb
Host smart-e363f4de-bb23-45e9-8348-9cfd3e0c9dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470588315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3470588315
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1312064877
Short name T91
Test name
Test status
Simulation time 106574243318 ps
CPU time 131.36 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:28:17 PM PDT 24
Peak memory 197064 kb
Host smart-468cc763-b34a-4e60-ac94-65205053adb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312064877 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1312064877
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3034311784
Short name T128
Test name
Test status
Simulation time 200417801961 ps
CPU time 125.89 seconds
Started May 12 12:27:35 PM PDT 24
Finished May 12 12:29:41 PM PDT 24
Peak memory 182724 kb
Host smart-990c9b5b-8c25-42d1-ad4b-4ceac8f062b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034311784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3034311784
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3572541466
Short name T418
Test name
Test status
Simulation time 28928359451 ps
CPU time 49.21 seconds
Started May 12 12:27:34 PM PDT 24
Finished May 12 12:28:24 PM PDT 24
Peak memory 182508 kb
Host smart-47090c9f-293f-4285-a4a9-fe05c9980dac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572541466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3572541466
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1050446398
Short name T307
Test name
Test status
Simulation time 171942452027 ps
CPU time 134.66 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:29:44 PM PDT 24
Peak memory 191000 kb
Host smart-ea8c2147-ce4b-44fa-9405-df08f047163d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050446398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1050446398
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3329754369
Short name T295
Test name
Test status
Simulation time 69528158162 ps
CPU time 127.43 seconds
Started May 12 12:27:32 PM PDT 24
Finished May 12 12:29:40 PM PDT 24
Peak memory 190996 kb
Host smart-2cce8f89-7b2e-4e0e-abc1-675bab0144ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329754369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3329754369
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2326122518
Short name T415
Test name
Test status
Simulation time 138728935502 ps
CPU time 819.74 seconds
Started May 12 12:27:48 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 182784 kb
Host smart-a576b2c4-6ad2-4b7e-b1f1-0bbf2ac44901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326122518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2326122518
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3363667043
Short name T97
Test name
Test status
Simulation time 122062597323 ps
CPU time 98 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:29:07 PM PDT 24
Peak memory 183216 kb
Host smart-ebc9c6af-6b4d-4ac9-a73b-129a245cafa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363667043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3363667043
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.4053051146
Short name T155
Test name
Test status
Simulation time 419105485525 ps
CPU time 369.49 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:33:38 PM PDT 24
Peak memory 190948 kb
Host smart-37cb7f08-4b88-4b13-9033-db48b9534651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053051146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.4053051146
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3247683702
Short name T254
Test name
Test status
Simulation time 830703463988 ps
CPU time 1543.56 seconds
Started May 12 12:22:06 PM PDT 24
Finished May 12 12:47:51 PM PDT 24
Peak memory 182724 kb
Host smart-56240508-a160-4b80-aa47-ccbe2dc981e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247683702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3247683702
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3408427663
Short name T446
Test name
Test status
Simulation time 106878324863 ps
CPU time 160.91 seconds
Started May 12 12:26:46 PM PDT 24
Finished May 12 12:29:28 PM PDT 24
Peak memory 181752 kb
Host smart-3f32a1d8-8cf6-4b99-adba-fba622bdbc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408427663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3408427663
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2649302840
Short name T117
Test name
Test status
Simulation time 72377334466 ps
CPU time 1026.53 seconds
Started May 12 12:26:46 PM PDT 24
Finished May 12 12:43:54 PM PDT 24
Peak memory 189564 kb
Host smart-0998298c-4aaf-4faa-9067-c6cf7bdb7838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649302840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2649302840
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1510378083
Short name T403
Test name
Test status
Simulation time 5241072195 ps
CPU time 2.77 seconds
Started May 12 12:24:32 PM PDT 24
Finished May 12 12:24:35 PM PDT 24
Peak memory 191408 kb
Host smart-1015c6aa-d30e-475a-aa55-c98cf2d4f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510378083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1510378083
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.329428321
Short name T243
Test name
Test status
Simulation time 312876895698 ps
CPU time 1470.86 seconds
Started May 12 12:27:43 PM PDT 24
Finished May 12 12:52:15 PM PDT 24
Peak memory 194524 kb
Host smart-10ecc971-37ea-4272-9071-4e929b88ac9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329428321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.329428321
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3518255243
Short name T421
Test name
Test status
Simulation time 40247793610 ps
CPU time 44.95 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:28:13 PM PDT 24
Peak memory 182772 kb
Host smart-ff6f299d-2f91-4554-83d8-6e43a82cc577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518255243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3518255243
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1585950530
Short name T323
Test name
Test status
Simulation time 90084707777 ps
CPU time 74.15 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:28:44 PM PDT 24
Peak memory 182764 kb
Host smart-62f18ba9-cb10-4fa7-b867-66c29767171e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585950530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1585950530
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.133382446
Short name T437
Test name
Test status
Simulation time 64869750649 ps
CPU time 280.01 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:32:09 PM PDT 24
Peak memory 190968 kb
Host smart-9cc221e4-9e7b-4fd8-8227-9c4e4fdecb49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133382446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.133382446
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1305334750
Short name T264
Test name
Test status
Simulation time 84430465743 ps
CPU time 174.3 seconds
Started May 12 12:27:45 PM PDT 24
Finished May 12 12:30:40 PM PDT 24
Peak memory 191000 kb
Host smart-e90d0ef3-8030-4fc1-83f4-05fbe2fdc9fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305334750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1305334750
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1827516136
Short name T213
Test name
Test status
Simulation time 172096398952 ps
CPU time 67.7 seconds
Started May 12 12:27:34 PM PDT 24
Finished May 12 12:28:43 PM PDT 24
Peak memory 190972 kb
Host smart-4eb4cf53-0490-4e76-bc88-432017abc519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827516136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1827516136
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4098996634
Short name T186
Test name
Test status
Simulation time 101660247025 ps
CPU time 52.67 seconds
Started May 12 12:27:47 PM PDT 24
Finished May 12 12:28:41 PM PDT 24
Peak memory 182724 kb
Host smart-7265eaf1-95d3-4cb7-afe1-d837f911422f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098996634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4098996634
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1029725345
Short name T2
Test name
Test status
Simulation time 149693568675 ps
CPU time 72.55 seconds
Started May 12 12:27:30 PM PDT 24
Finished May 12 12:28:43 PM PDT 24
Peak memory 182636 kb
Host smart-f7312520-cd18-401a-9cfe-5a491e99ff00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029725345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1029725345
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3378135655
Short name T192
Test name
Test status
Simulation time 497562364222 ps
CPU time 2581.24 seconds
Started May 12 12:27:34 PM PDT 24
Finished May 12 01:10:36 PM PDT 24
Peak memory 190676 kb
Host smart-c55b0df1-c6d3-4d56-9be5-671806020a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378135655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3378135655
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4089598880
Short name T10
Test name
Test status
Simulation time 1137226374533 ps
CPU time 611.65 seconds
Started May 12 12:25:58 PM PDT 24
Finished May 12 12:36:11 PM PDT 24
Peak memory 182440 kb
Host smart-ae8b79d1-a7ba-42d5-9c6d-94c4fab7de5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089598880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4089598880
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.175431700
Short name T6
Test name
Test status
Simulation time 501143719041 ps
CPU time 174.86 seconds
Started May 12 12:25:57 PM PDT 24
Finished May 12 12:28:54 PM PDT 24
Peak memory 181440 kb
Host smart-f51ddb45-04a6-4c2b-a90a-6b4091e540ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175431700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.175431700
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1900763357
Short name T115
Test name
Test status
Simulation time 1804106042233 ps
CPU time 213.58 seconds
Started May 12 12:23:17 PM PDT 24
Finished May 12 12:26:51 PM PDT 24
Peak memory 193144 kb
Host smart-bed9a71b-832d-455e-9ba8-9a789ab16468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900763357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1900763357
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.285318624
Short name T378
Test name
Test status
Simulation time 201123995 ps
CPU time 0.78 seconds
Started May 12 12:25:57 PM PDT 24
Finished May 12 12:25:59 PM PDT 24
Peak memory 180684 kb
Host smart-cc9c570f-0084-4767-bc72-f52e1876458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285318624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.285318624
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.2936816942
Short name T129
Test name
Test status
Simulation time 72486876876 ps
CPU time 1174.09 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:47:03 PM PDT 24
Peak memory 190996 kb
Host smart-557e837c-d1c2-4684-827f-675c608cec37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936816942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2936816942
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3263238193
Short name T425
Test name
Test status
Simulation time 104962898425 ps
CPU time 177.72 seconds
Started May 12 12:27:29 PM PDT 24
Finished May 12 12:30:27 PM PDT 24
Peak memory 190972 kb
Host smart-38395898-fbbf-49a2-a985-167f4712a2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263238193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3263238193
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3317310106
Short name T325
Test name
Test status
Simulation time 25665883699 ps
CPU time 40.51 seconds
Started May 12 12:27:28 PM PDT 24
Finished May 12 12:28:10 PM PDT 24
Peak memory 182724 kb
Host smart-95caa29d-e195-4015-b59d-11f1dbdd1012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317310106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3317310106
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3023575915
Short name T273
Test name
Test status
Simulation time 257050297566 ps
CPU time 189.8 seconds
Started May 12 12:27:32 PM PDT 24
Finished May 12 12:30:43 PM PDT 24
Peak memory 193576 kb
Host smart-b278e983-6463-4b47-81d8-033cd70300c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023575915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3023575915
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4132095626
Short name T135
Test name
Test status
Simulation time 296746176403 ps
CPU time 758.66 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:40:08 PM PDT 24
Peak memory 190924 kb
Host smart-2c5b0ad7-29f2-4521-a636-00cd3dceea5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132095626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4132095626
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1674326726
Short name T164
Test name
Test status
Simulation time 89386186517 ps
CPU time 19.35 seconds
Started May 12 12:27:26 PM PDT 24
Finished May 12 12:27:46 PM PDT 24
Peak memory 190984 kb
Host smart-c641bd8d-afeb-4007-8992-185679d2489e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674326726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1674326726
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.387928222
Short name T167
Test name
Test status
Simulation time 211714167814 ps
CPU time 107.98 seconds
Started May 12 12:27:31 PM PDT 24
Finished May 12 12:29:20 PM PDT 24
Peak memory 193176 kb
Host smart-fdccdb3a-c2f1-47e1-8adb-01333599a559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387928222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.387928222
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1138852057
Short name T238
Test name
Test status
Simulation time 279385221898 ps
CPU time 83.82 seconds
Started May 12 12:27:31 PM PDT 24
Finished May 12 12:28:56 PM PDT 24
Peak memory 182760 kb
Host smart-0624912d-3167-4985-9d91-7b01d824543d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138852057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1138852057
Directory /workspace/99.rv_timer_random/latest
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