Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
132006998 |
1 |
|
T1 |
229436 |
|
T2 |
26266 |
|
T3 |
30251 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
69982417 |
1 |
|
T1 |
217860 |
|
T2 |
15389 |
|
T3 |
3727 |
auto[1] |
62024581 |
1 |
|
T1 |
11576 |
|
T2 |
10877 |
|
T3 |
26524 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
132001424 |
1 |
|
T1 |
229423 |
|
T2 |
26258 |
|
T3 |
30214 |
auto[1] |
5574 |
1 |
|
T1 |
13 |
|
T2 |
8 |
|
T3 |
37 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
69979617 |
1 |
|
T1 |
217851 |
|
T2 |
15385 |
|
T3 |
3704 |
all_values[0] |
auto[0] |
auto[1] |
2800 |
1 |
|
T1 |
9 |
|
T2 |
4 |
|
T3 |
23 |
all_values[0] |
auto[1] |
auto[0] |
62021807 |
1 |
|
T1 |
11572 |
|
T2 |
10873 |
|
T3 |
26510 |
all_values[0] |
auto[1] |
auto[1] |
2774 |
1 |
|
T1 |
4 |
|
T2 |
4 |
|
T3 |
14 |