| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.55 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.21 |
| T507 | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2420113424 | May 14 12:41:40 PM PDT 24 | May 14 12:41:43 PM PDT 24 | 16977253 ps | ||
| T508 | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.207973336 | May 14 12:42:01 PM PDT 24 | May 14 12:42:04 PM PDT 24 | 636865357 ps | ||
| T509 | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2954905465 | May 14 12:42:19 PM PDT 24 | May 14 12:42:21 PM PDT 24 | 24697741 ps | ||
| T510 | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1480140939 | May 14 12:41:56 PM PDT 24 | May 14 12:41:59 PM PDT 24 | 24534564 ps | ||
| T511 | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1835923124 | May 14 12:42:00 PM PDT 24 | May 14 12:42:02 PM PDT 24 | 24450028 ps | ||
| T512 | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.865006271 | May 14 12:41:58 PM PDT 24 | May 14 12:42:00 PM PDT 24 | 17699801 ps | ||
| T513 | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1379407979 | May 14 12:41:58 PM PDT 24 | May 14 12:42:01 PM PDT 24 | 92711927 ps | ||
| T87 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3742524945 | May 14 12:41:43 PM PDT 24 | May 14 12:41:47 PM PDT 24 | 36435339 ps | ||
| T514 | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.955301391 | May 14 12:42:02 PM PDT 24 | May 14 12:42:05 PM PDT 24 | 33506155 ps | ||
| T515 | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2820408377 | May 14 12:41:29 PM PDT 24 | May 14 12:41:32 PM PDT 24 | 300441970 ps | ||
| T516 | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3481109745 | May 14 12:41:18 PM PDT 24 | May 14 12:41:22 PM PDT 24 | 34643766 ps | ||
| T83 | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.456437500 | May 14 12:41:42 PM PDT 24 | May 14 12:41:50 PM PDT 24 | 35096501 ps | ||
| T517 | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.929999648 | May 14 12:41:36 PM PDT 24 | May 14 12:41:40 PM PDT 24 | 302302344 ps | ||
| T518 | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4282546208 | May 14 12:41:47 PM PDT 24 | May 14 12:41:50 PM PDT 24 | 40321930 ps | ||
| T101 | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4240569765 | May 14 12:41:51 PM PDT 24 | May 14 12:41:55 PM PDT 24 | 121144033 ps | ||
| T519 | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3664392917 | May 14 12:41:48 PM PDT 24 | May 14 12:41:51 PM PDT 24 | 41970338 ps | ||
| T520 | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3073095314 | May 14 12:41:43 PM PDT 24 | May 14 12:41:47 PM PDT 24 | 191951869 ps | ||
| T521 | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3056608621 | May 14 12:41:42 PM PDT 24 | May 14 12:41:45 PM PDT 24 | 169739527 ps | ||
| T522 | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2889516254 | May 14 12:41:51 PM PDT 24 | May 14 12:41:55 PM PDT 24 | 37987117 ps | ||
| T523 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3255435312 | May 14 12:41:48 PM PDT 24 | May 14 12:41:52 PM PDT 24 | 22281109 ps | ||
| T524 | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4126739320 | May 14 12:41:37 PM PDT 24 | May 14 12:41:40 PM PDT 24 | 68843247 ps | ||
| T525 | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2104709456 | May 14 12:41:36 PM PDT 24 | May 14 12:41:40 PM PDT 24 | 113767681 ps | ||
| T526 | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.4142439024 | May 14 12:41:44 PM PDT 24 | May 14 12:41:47 PM PDT 24 | 15800875 ps | ||
| T527 | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3549061005 | May 14 12:41:56 PM PDT 24 | May 14 12:42:00 PM PDT 24 | 42491290 ps | ||
| T528 | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.173814504 | May 14 12:41:49 PM PDT 24 | May 14 12:41:52 PM PDT 24 | 53691494 ps | ||
| T529 | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.760708797 | May 14 12:41:43 PM PDT 24 | May 14 12:41:46 PM PDT 24 | 14853021 ps | ||
| T530 | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.468070840 | May 14 12:41:34 PM PDT 24 | May 14 12:41:36 PM PDT 24 | 12461758 ps | ||
| T531 | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2881689327 | May 14 12:41:21 PM PDT 24 | May 14 12:41:24 PM PDT 24 | 44179536 ps | ||
| T532 | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3198039844 | May 14 12:42:00 PM PDT 24 | May 14 12:42:03 PM PDT 24 | 65812456 ps | ||
| T533 | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3638620875 | May 14 12:42:02 PM PDT 24 | May 14 12:42:05 PM PDT 24 | 47081385 ps | ||
| T534 | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1543921794 | May 14 12:41:47 PM PDT 24 | May 14 12:41:50 PM PDT 24 | 84958075 ps | ||
| T535 | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3518324254 | May 14 12:41:58 PM PDT 24 | May 14 12:42:00 PM PDT 24 | 15898157 ps | ||
| T536 | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1934903903 | May 14 12:41:38 PM PDT 24 | May 14 12:41:42 PM PDT 24 | 92678939 ps | ||
| T537 | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1748510423 | May 14 12:41:36 PM PDT 24 | May 14 12:41:39 PM PDT 24 | 280352694 ps | ||
| T538 | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4127856525 | May 14 12:41:45 PM PDT 24 | May 14 12:41:48 PM PDT 24 | 48809807 ps | ||
| T539 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4205541153 | May 14 12:41:43 PM PDT 24 | May 14 12:41:49 PM PDT 24 | 415403286 ps | ||
| T540 | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1123899374 | May 14 12:41:56 PM PDT 24 | May 14 12:41:59 PM PDT 24 | 113373865 ps | ||
| T541 | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3535223997 | May 14 12:41:49 PM PDT 24 | May 14 12:41:54 PM PDT 24 | 179967433 ps | ||
| T542 | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2971406988 | May 14 12:41:34 PM PDT 24 | May 14 12:41:36 PM PDT 24 | 27408485 ps | ||
| T543 | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3399401952 | May 14 12:41:36 PM PDT 24 | May 14 12:41:40 PM PDT 24 | 972738991 ps | ||
| T544 | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.206417375 | May 14 12:41:49 PM PDT 24 | May 14 12:41:53 PM PDT 24 | 13160906 ps | ||
| T545 | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1472622774 | May 14 12:41:52 PM PDT 24 | May 14 12:41:55 PM PDT 24 | 13708511 ps | ||
| T546 | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1852633160 | May 14 12:41:30 PM PDT 24 | May 14 12:41:33 PM PDT 24 | 470746544 ps | ||
| T547 | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.354433502 | May 14 12:41:48 PM PDT 24 | May 14 12:41:51 PM PDT 24 | 61977528 ps | ||
| T548 | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2811002741 | May 14 12:41:38 PM PDT 24 | May 14 12:41:41 PM PDT 24 | 40306085 ps | ||
| T549 | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2343652006 | May 14 12:41:46 PM PDT 24 | May 14 12:41:50 PM PDT 24 | 38210070 ps | ||
| T550 | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2505169902 | May 14 12:41:43 PM PDT 24 | May 14 12:41:46 PM PDT 24 | 16866427 ps | ||
| T551 | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3945338202 | May 14 12:41:53 PM PDT 24 | May 14 12:41:57 PM PDT 24 | 394294900 ps | ||
| T552 | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2922302403 | May 14 12:41:47 PM PDT 24 | May 14 12:41:50 PM PDT 24 | 100704328 ps | ||
| T553 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.813180452 | May 14 12:41:32 PM PDT 24 | May 14 12:41:35 PM PDT 24 | 139044241 ps | ||
| T554 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.380174244 | May 14 12:41:36 PM PDT 24 | May 14 12:41:38 PM PDT 24 | 19792776 ps | ||
| T555 | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3851581481 | May 14 12:42:05 PM PDT 24 | May 14 12:42:08 PM PDT 24 | 51766782 ps | ||
| T556 | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1950007946 | May 14 12:41:50 PM PDT 24 | May 14 12:41:53 PM PDT 24 | 14536349 ps | ||
| T557 | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1416651775 | May 14 12:41:48 PM PDT 24 | May 14 12:41:57 PM PDT 24 | 45839792 ps | ||
| T558 | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.370590915 | May 14 12:42:01 PM PDT 24 | May 14 12:42:04 PM PDT 24 | 15556333 ps | ||
| T559 | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3089389840 | May 14 12:41:35 PM PDT 24 | May 14 12:41:38 PM PDT 24 | 85533273 ps | ||
| T560 | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1771205271 | May 14 12:41:49 PM PDT 24 | May 14 12:41:52 PM PDT 24 | 13613924 ps | ||
| T561 | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2667748000 | May 14 12:41:54 PM PDT 24 | May 14 12:41:58 PM PDT 24 | 1016066878 ps | ||
| T562 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4011511241 | May 14 12:41:44 PM PDT 24 | May 14 12:41:50 PM PDT 24 | 3084007719 ps | ||
| T563 | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.366634030 | May 14 12:41:52 PM PDT 24 | May 14 12:41:56 PM PDT 24 | 17156889 ps | ||
| T564 | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1806014984 | May 14 12:41:37 PM PDT 24 | May 14 12:41:39 PM PDT 24 | 12900018 ps | ||
| T565 | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1660265563 | May 14 12:41:33 PM PDT 24 | May 14 12:41:36 PM PDT 24 | 126901469 ps | ||
| T566 | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.814066007 | May 14 12:41:47 PM PDT 24 | May 14 12:41:51 PM PDT 24 | 37804002 ps | ||
| T567 | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2940490542 | May 14 12:41:54 PM PDT 24 | May 14 12:41:57 PM PDT 24 | 23086248 ps | ||
| T568 | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4114633987 | May 14 12:41:46 PM PDT 24 | May 14 12:41:49 PM PDT 24 | 70014318 ps | ||
| T569 | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1599170165 | May 14 12:41:39 PM PDT 24 | May 14 12:41:42 PM PDT 24 | 22954044 ps | ||
| T570 | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1517932452 | May 14 12:41:38 PM PDT 24 | May 14 12:41:42 PM PDT 24 | 14310060 ps | ||
| T571 | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2269703358 | May 14 12:41:47 PM PDT 24 | May 14 12:41:51 PM PDT 24 | 337975247 ps | ||
| T84 | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3383116557 | May 14 12:42:01 PM PDT 24 | May 14 12:42:04 PM PDT 24 | 15989616 ps | ||
| T572 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1025029638 | May 14 12:41:30 PM PDT 24 | May 14 12:41:32 PM PDT 24 | 34487105 ps | ||
| T85 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1664404591 | May 14 12:41:32 PM PDT 24 | May 14 12:41:34 PM PDT 24 | 16391489 ps | ||
| T573 | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3527659225 | May 14 12:41:30 PM PDT 24 | May 14 12:41:34 PM PDT 24 | 132013406 ps | ||
| T574 | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.968180892 | May 14 12:41:44 PM PDT 24 | May 14 12:41:47 PM PDT 24 | 409428194 ps | ||
| T575 | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2688719105 | May 14 12:41:43 PM PDT 24 | May 14 12:41:46 PM PDT 24 | 133474104 ps | ||
| T576 | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4257662653 | May 14 12:41:35 PM PDT 24 | May 14 12:41:39 PM PDT 24 | 237018852 ps | ||
| T577 | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3560646696 | May 14 12:41:43 PM PDT 24 | May 14 12:41:46 PM PDT 24 | 56473675 ps | ||
| T578 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2184120889 | May 14 12:41:44 PM PDT 24 | May 14 12:41:47 PM PDT 24 | 30203397 ps | ||
| T579 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1389068649 | May 14 12:41:35 PM PDT 24 | May 14 12:41:37 PM PDT 24 | 21667233 ps | ||
| T580 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1116575915 | May 14 12:41:21 PM PDT 24 | May 14 12:41:24 PM PDT 24 | 46845723 ps | ||
| T86 | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2949051463 | May 14 12:41:43 PM PDT 24 | May 14 12:41:46 PM PDT 24 | 15315598 ps |
| Test location | /workspace/coverage/default/91.rv_timer_random.1355021985 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 264629100206 ps |
| CPU time | 264.35 seconds |
| Started | May 14 12:42:43 PM PDT 24 |
| Finished | May 14 12:47:11 PM PDT 24 |
| Peak memory | 190696 kb |
| Host | smart-b030e949-88c7-4e99-86dc-2318da78557a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355021985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1355021985 |
| Directory | /workspace/91.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.1380056054 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 73184321004 ps |
| CPU time | 520.19 seconds |
| Started | May 14 12:42:20 PM PDT 24 |
| Finished | May 14 12:51:01 PM PDT 24 |
| Peak memory | 205376 kb |
| Host | smart-77c7b415-4547-4cb8-a9b5-387847af938e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380056054 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.1380056054 |
| Directory | /workspace/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/149.rv_timer_random.672500736 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 180726627657 ps |
| CPU time | 320.41 seconds |
| Started | May 14 12:42:41 PM PDT 24 |
| Finished | May 14 12:48:05 PM PDT 24 |
| Peak memory | 194132 kb |
| Host | smart-0b507eea-7b27-4efc-ac22-dd78dbc51a9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672500736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.672500736 |
| Directory | /workspace/149.rv_timer_random/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all.2321957931 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1518785095014 ps |
| CPU time | 1284.28 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 01:03:56 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-71469751-2378-49f5-9bb2-bdaa43925f8c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321957931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all .2321957931 |
| Directory | /workspace/44.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1859699488 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 754080743 ps |
| CPU time | 1.06 seconds |
| Started | May 14 12:41:27 PM PDT 24 |
| Finished | May 14 12:41:30 PM PDT 24 |
| Peak memory | 195004 kb |
| Host | smart-347592c8-5f56-4135-ac67-22733be5950f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859699488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in tg_err.1859699488 |
| Directory | /workspace/2.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all.4001482022 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 855623124111 ps |
| CPU time | 2041.12 seconds |
| Started | May 14 12:41:55 PM PDT 24 |
| Finished | May 14 01:15:59 PM PDT 24 |
| Peak memory | 190716 kb |
| Host | smart-44f0a46b-8e43-4b08-a192-b4ddba039aed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001482022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 4001482022 |
| Directory | /workspace/3.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all.1875593498 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1331052060771 ps |
| CPU time | 1909.19 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 01:14:01 PM PDT 24 |
| Peak memory | 196256 kb |
| Host | smart-fd5cf87c-4e92-4835-b250-a5f31f80cd6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875593498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all .1875593498 |
| Directory | /workspace/34.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all.3659872732 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1348071614994 ps |
| CPU time | 3815.08 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 01:45:43 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-7d503dc6-0646-4873-8d44-b23b7e133d12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659872732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all .3659872732 |
| Directory | /workspace/18.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all.744807613 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1041476008918 ps |
| CPU time | 1189.55 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 01:01:58 PM PDT 24 |
| Peak memory | 190828 kb |
| Host | smart-253546b4-db87-4e83-83f0-ce83635fafb0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744807613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all. 744807613 |
| Directory | /workspace/27.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all.800514697 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1434175009495 ps |
| CPU time | 1855.28 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 01:13:08 PM PDT 24 |
| Peak memory | 190748 kb |
| Host | smart-f8b2a47c-afff-49e7-a8cb-4b0f05a07cf4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800514697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all. 800514697 |
| Directory | /workspace/19.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all.1081846394 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1973274973421 ps |
| CPU time | 2777.48 seconds |
| Started | May 14 12:42:20 PM PDT 24 |
| Finished | May 14 01:28:39 PM PDT 24 |
| Peak memory | 194232 kb |
| Host | smart-b209ef20-fdc5-4934-981d-f70932a03835 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081846394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all .1081846394 |
| Directory | /workspace/28.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all.450885405 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 498694498260 ps |
| CPU time | 1014.83 seconds |
| Started | May 14 12:42:18 PM PDT 24 |
| Finished | May 14 12:59:14 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-cd856302-72eb-49ff-9716-0140c02dc6dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450885405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all. 450885405 |
| Directory | /workspace/13.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all.1339835854 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 845316935119 ps |
| CPU time | 2026.57 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 01:16:18 PM PDT 24 |
| Peak memory | 190620 kb |
| Host | smart-5618e32a-347f-4e9c-857f-1f450c569a0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339835854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all .1339835854 |
| Directory | /workspace/46.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3240930361 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 54835023 ps |
| CPU time | 0.83 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 191760 kb |
| Host | smart-2b600525-fb08-4bbc-b417-37c83c0a57d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240930361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.3240930361 |
| Directory | /workspace/3.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/default/0.rv_timer_sec_cm.2636607970 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 808227589 ps |
| CPU time | 0.91 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:42:06 PM PDT 24 |
| Peak memory | 213996 kb |
| Host | smart-dcf77946-d46a-4829-b283-594529a2de89 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636607970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2636607970 |
| Directory | /workspace/0.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/119.rv_timer_random.2561803553 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 564007587001 ps |
| CPU time | 1047.11 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 01:00:14 PM PDT 24 |
| Peak memory | 190636 kb |
| Host | smart-85392758-c3b3-4477-bb45-7a7c597ab5f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561803553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2561803553 |
| Directory | /workspace/119.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all.2337602628 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1882762955043 ps |
| CPU time | 1480.98 seconds |
| Started | May 14 12:42:23 PM PDT 24 |
| Finished | May 14 01:07:05 PM PDT 24 |
| Peak memory | 190644 kb |
| Host | smart-f0d41834-ca8f-4001-b4dd-acab076a6d91 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337602628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .2337602628 |
| Directory | /workspace/23.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all.1900716522 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 512284646649 ps |
| CPU time | 713.4 seconds |
| Started | May 14 12:42:20 PM PDT 24 |
| Finished | May 14 12:54:15 PM PDT 24 |
| Peak memory | 194416 kb |
| Host | smart-f2df1656-ab33-43c3-a44a-da7f480fc5b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900716522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all .1900716522 |
| Directory | /workspace/26.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all.3422452916 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 858451483479 ps |
| CPU time | 668.62 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:53:43 PM PDT 24 |
| Peak memory | 190716 kb |
| Host | smart-6b99b6f2-e6e1-4802-be3d-4a01046d2bbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422452916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all .3422452916 |
| Directory | /workspace/48.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random.1501178130 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 145571507784 ps |
| CPU time | 253.62 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:46:48 PM PDT 24 |
| Peak memory | 194400 kb |
| Host | smart-8d5d6d5a-b5a4-4db9-80f2-22f4556bb645 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501178130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1501178130 |
| Directory | /workspace/11.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all.3862685012 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3209343080239 ps |
| CPU time | 1837.84 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 01:13:05 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-a896263d-4ced-483f-a39a-14659ce19834 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862685012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all .3862685012 |
| Directory | /workspace/42.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/129.rv_timer_random.1289988876 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 179614343313 ps |
| CPU time | 1494.75 seconds |
| Started | May 14 12:42:55 PM PDT 24 |
| Finished | May 14 01:07:52 PM PDT 24 |
| Peak memory | 190624 kb |
| Host | smart-798d7f71-1985-4af1-a006-298b67b025d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289988876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1289988876 |
| Directory | /workspace/129.rv_timer_random/latest |
| Test location | /workspace/coverage/default/105.rv_timer_random.2234558754 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1262631024944 ps |
| CPU time | 902.45 seconds |
| Started | May 14 12:42:44 PM PDT 24 |
| Finished | May 14 12:57:51 PM PDT 24 |
| Peak memory | 190756 kb |
| Host | smart-80134363-c1e6-4224-a9dc-fc2599c01843 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234558754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2234558754 |
| Directory | /workspace/105.rv_timer_random/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random.217352215 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 168806528483 ps |
| CPU time | 679.34 seconds |
| Started | May 14 12:42:12 PM PDT 24 |
| Finished | May 14 12:53:33 PM PDT 24 |
| Peak memory | 190572 kb |
| Host | smart-9a84c356-8212-4b0c-afaf-d452cacf8704 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217352215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.217352215 |
| Directory | /workspace/36.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all.1075181570 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 548188047485 ps |
| CPU time | 2626.58 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 01:25:53 PM PDT 24 |
| Peak memory | 196148 kb |
| Host | smart-05432c9d-6441-4a42-b7b8-4f140c58641f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075181570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .1075181570 |
| Directory | /workspace/11.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/146.rv_timer_random.3374778764 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 873999155767 ps |
| CPU time | 3481.33 seconds |
| Started | May 14 12:42:45 PM PDT 24 |
| Finished | May 14 01:40:52 PM PDT 24 |
| Peak memory | 190676 kb |
| Host | smart-cc80012d-7859-42ef-bd35-36d3be574efa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374778764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3374778764 |
| Directory | /workspace/146.rv_timer_random/latest |
| Test location | /workspace/coverage/default/79.rv_timer_random.2563973422 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 451301782752 ps |
| CPU time | 895.85 seconds |
| Started | May 14 12:42:39 PM PDT 24 |
| Finished | May 14 12:57:38 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-f987988e-a215-43d7-a2d5-fbeb0f1cbb25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563973422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2563973422 |
| Directory | /workspace/79.rv_timer_random/latest |
| Test location | /workspace/coverage/default/110.rv_timer_random.708921610 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 462410038623 ps |
| CPU time | 900.22 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:57:35 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-ea5e32ee-b61b-43b3-bbbe-85623e25baf0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708921610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.708921610 |
| Directory | /workspace/110.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all.713744942 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3022869884139 ps |
| CPU time | 1752.94 seconds |
| Started | May 14 12:42:10 PM PDT 24 |
| Finished | May 14 01:11:26 PM PDT 24 |
| Peak memory | 190676 kb |
| Host | smart-6f8f7f3d-082b-470d-b1bb-29faf714f213 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713744942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all. 713744942 |
| Directory | /workspace/15.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/168.rv_timer_random.2519656892 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 146729125657 ps |
| CPU time | 515.01 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:51:21 PM PDT 24 |
| Peak memory | 192940 kb |
| Host | smart-efb2bb65-c9a8-489a-ae70-8f493fe8b244 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519656892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2519656892 |
| Directory | /workspace/168.rv_timer_random/latest |
| Test location | /workspace/coverage/default/169.rv_timer_random.225437002 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 604718805051 ps |
| CPU time | 913.76 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:58:00 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-e4b5e32e-334f-4d96-88e4-ad268ce46072 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225437002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.225437002 |
| Directory | /workspace/169.rv_timer_random/latest |
| Test location | /workspace/coverage/default/52.rv_timer_random.320724421 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 552622571048 ps |
| CPU time | 2795.06 seconds |
| Started | May 14 12:42:46 PM PDT 24 |
| Finished | May 14 01:29:26 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-8a287fab-0760-43f8-85cd-4f2d817c11c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320724421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.320724421 |
| Directory | /workspace/52.rv_timer_random/latest |
| Test location | /workspace/coverage/default/154.rv_timer_random.3235959986 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 151943448821 ps |
| CPU time | 674.25 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:54:07 PM PDT 24 |
| Peak memory | 190608 kb |
| Host | smart-fb418edd-cde0-4463-8bf7-679b777d73ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235959986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3235959986 |
| Directory | /workspace/154.rv_timer_random/latest |
| Test location | /workspace/coverage/default/160.rv_timer_random.3936244090 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2031749250092 ps |
| CPU time | 683 seconds |
| Started | May 14 12:42:40 PM PDT 24 |
| Finished | May 14 12:54:07 PM PDT 24 |
| Peak memory | 190816 kb |
| Host | smart-60a669d7-e3c4-4718-8c15-4186ebdb0321 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936244090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3936244090 |
| Directory | /workspace/160.rv_timer_random/latest |
| Test location | /workspace/coverage/default/172.rv_timer_random.2348422263 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 202251722226 ps |
| CPU time | 345.76 seconds |
| Started | May 14 12:42:46 PM PDT 24 |
| Finished | May 14 12:48:37 PM PDT 24 |
| Peak memory | 194436 kb |
| Host | smart-a7c6c26d-2b2d-484b-8ff7-1080332f892a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348422263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2348422263 |
| Directory | /workspace/172.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random.847195410 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 811976571324 ps |
| CPU time | 442.42 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:49:28 PM PDT 24 |
| Peak memory | 190664 kb |
| Host | smart-6d36641d-01bd-45f5-b229-ea2d72a949bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847195410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.847195410 |
| Directory | /workspace/8.rv_timer_random/latest |
| Test location | /workspace/coverage/default/107.rv_timer_random.3857015160 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 172950889458 ps |
| CPU time | 448.45 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:50:09 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-b57d6241-f3a4-4fa8-88e1-0cd9e4855c02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857015160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3857015160 |
| Directory | /workspace/107.rv_timer_random/latest |
| Test location | /workspace/coverage/default/123.rv_timer_random.2894603478 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2508562481092 ps |
| CPU time | 854.61 seconds |
| Started | May 14 12:42:58 PM PDT 24 |
| Finished | May 14 12:57:16 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-9b7f9b80-a8aa-4c52-a2b8-6052e0381653 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894603478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2894603478 |
| Directory | /workspace/123.rv_timer_random/latest |
| Test location | /workspace/coverage/default/134.rv_timer_random.1143613054 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 428010426963 ps |
| CPU time | 390.38 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:49:12 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-4aeb4e47-5da4-4426-832b-5d040b45815e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143613054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1143613054 |
| Directory | /workspace/134.rv_timer_random/latest |
| Test location | /workspace/coverage/default/145.rv_timer_random.2065812536 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 108265785947 ps |
| CPU time | 164.7 seconds |
| Started | May 14 12:42:41 PM PDT 24 |
| Finished | May 14 12:45:30 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-6c87ce8c-c42c-4b89-8882-26d90c3eda63 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065812536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2065812536 |
| Directory | /workspace/145.rv_timer_random/latest |
| Test location | /workspace/coverage/default/180.rv_timer_random.2007544664 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1902822040746 ps |
| CPU time | 505.8 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:51:12 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-a55f9b0f-083c-449a-93d6-55c53673f01e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007544664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2007544664 |
| Directory | /workspace/180.rv_timer_random/latest |
| Test location | /workspace/coverage/default/187.rv_timer_random.1079186455 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 94944471570 ps |
| CPU time | 169.94 seconds |
| Started | May 14 12:43:00 PM PDT 24 |
| Finished | May 14 12:45:55 PM PDT 24 |
| Peak memory | 190816 kb |
| Host | smart-fb961d08-5cfa-4393-aa96-a08b05268187 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079186455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1079186455 |
| Directory | /workspace/187.rv_timer_random/latest |
| Test location | /workspace/coverage/default/188.rv_timer_random.1353659159 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 37545024988 ps |
| CPU time | 94.52 seconds |
| Started | May 14 12:42:50 PM PDT 24 |
| Finished | May 14 12:44:29 PM PDT 24 |
| Peak memory | 190624 kb |
| Host | smart-752ac0f0-1761-46d4-94e3-ca2d054ba271 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353659159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1353659159 |
| Directory | /workspace/188.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all.3255668003 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4002166402651 ps |
| CPU time | 2763.39 seconds |
| Started | May 14 12:41:59 PM PDT 24 |
| Finished | May 14 01:28:04 PM PDT 24 |
| Peak memory | 190616 kb |
| Host | smart-8205e22b-4507-4d76-ac70-78213160cb74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255668003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 3255668003 |
| Directory | /workspace/2.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random_reset.3277758008 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 197823587512 ps |
| CPU time | 95.65 seconds |
| Started | May 14 12:42:07 PM PDT 24 |
| Finished | May 14 12:43:46 PM PDT 24 |
| Peak memory | 190748 kb |
| Host | smart-220089a8-92c1-4650-a22a-c62f7958626d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277758008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3277758008 |
| Directory | /workspace/41.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random.3807158687 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 232454529962 ps |
| CPU time | 248.2 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 12:46:16 PM PDT 24 |
| Peak memory | 194440 kb |
| Host | smart-7abe6b25-c702-4e56-9aab-e5b7d8695356 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807158687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3807158687 |
| Directory | /workspace/9.rv_timer_random/latest |
| Test location | /workspace/coverage/default/133.rv_timer_random.3149564048 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 85647338475 ps |
| CPU time | 169.65 seconds |
| Started | May 14 12:42:45 PM PDT 24 |
| Finished | May 14 12:45:40 PM PDT 24 |
| Peak memory | 190740 kb |
| Host | smart-2e157546-df36-4dda-9ff1-2cc11d1d8a78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149564048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3149564048 |
| Directory | /workspace/133.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random.4208099045 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 92679187575 ps |
| CPU time | 200.37 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 12:45:32 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-2002fa75-50a1-4fdc-93db-b5ae074ceb16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208099045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.4208099045 |
| Directory | /workspace/14.rv_timer_random/latest |
| Test location | /workspace/coverage/default/141.rv_timer_random.1145739740 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 777244872153 ps |
| CPU time | 389.66 seconds |
| Started | May 14 12:42:58 PM PDT 24 |
| Finished | May 14 12:49:31 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-5dee0c9c-575e-4e96-87a9-c6ac360662f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145739740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1145739740 |
| Directory | /workspace/141.rv_timer_random/latest |
| Test location | /workspace/coverage/default/194.rv_timer_random.4014256065 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 75341433096 ps |
| CPU time | 138.73 seconds |
| Started | May 14 12:43:02 PM PDT 24 |
| Finished | May 14 12:45:25 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-cd26a96b-2547-4778-9641-b5527b6d20bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014256065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4014256065 |
| Directory | /workspace/194.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random.1836974153 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 818892869892 ps |
| CPU time | 722.07 seconds |
| Started | May 14 12:41:52 PM PDT 24 |
| Finished | May 14 12:53:58 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-c55e5fcb-7f32-47c3-8d40-b5cb2fdfa9d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836974153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1836974153 |
| Directory | /workspace/3.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all.2887805539 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 314645020666 ps |
| CPU time | 1223.92 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 01:02:36 PM PDT 24 |
| Peak memory | 195136 kb |
| Host | smart-f90be29f-6bd6-4e0d-8412-843b8b883647 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887805539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .2887805539 |
| Directory | /workspace/38.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/57.rv_timer_random.3921944906 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 153987695358 ps |
| CPU time | 248.7 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:46:42 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-4be47d11-1bd6-43cc-b06f-484125bf588d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921944906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3921944906 |
| Directory | /workspace/57.rv_timer_random/latest |
| Test location | /workspace/coverage/default/81.rv_timer_random.2597402524 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1572419951463 ps |
| CPU time | 503.08 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:51:10 PM PDT 24 |
| Peak memory | 190628 kb |
| Host | smart-9d759d5b-7df3-4209-976c-2305846f65e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597402524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2597402524 |
| Directory | /workspace/81.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.637706466 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 97270243 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:51 PM PDT 24 |
| Peak memory | 182512 kb |
| Host | smart-22f6bf44-4b04-4e38-a496-1bf7fd75e39a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637706466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.637706466 |
| Directory | /workspace/10.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1248296155 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 16487031 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:53 PM PDT 24 |
| Peak memory | 182680 kb |
| Host | smart-04e0fc4d-a0bc-45c9-88ce-171da39c5334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248296155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1248296155 |
| Directory | /workspace/15.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.850141789 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 85756809 ps |
| CPU time | 1.1 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 194732 kb |
| Host | smart-c09caab4-cb1d-43c4-9a3c-1c66b6ebc114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850141789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in tg_err.850141789 |
| Directory | /workspace/14.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random.1275098822 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 319957865790 ps |
| CPU time | 1957.21 seconds |
| Started | May 14 12:42:07 PM PDT 24 |
| Finished | May 14 01:14:48 PM PDT 24 |
| Peak memory | 190680 kb |
| Host | smart-3695d1a5-02fa-4cdc-9c36-a6e83a7e984b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275098822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1275098822 |
| Directory | /workspace/10.rv_timer_random/latest |
| Test location | /workspace/coverage/default/114.rv_timer_random.1959274442 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 453356299023 ps |
| CPU time | 673.97 seconds |
| Started | May 14 12:42:35 PM PDT 24 |
| Finished | May 14 12:53:50 PM PDT 24 |
| Peak memory | 190676 kb |
| Host | smart-e5160bbd-1fcd-4872-8853-80428d083b46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959274442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1959274442 |
| Directory | /workspace/114.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.848169452 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29058939916 ps |
| CPU time | 252.45 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:46:20 PM PDT 24 |
| Peak memory | 197152 kb |
| Host | smart-57c14d0b-5901-496c-8867-7511c3c1b537 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848169452 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.848169452 |
| Directory | /workspace/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/159.rv_timer_random.1285169799 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 128273393915 ps |
| CPU time | 114.78 seconds |
| Started | May 14 12:42:57 PM PDT 24 |
| Finished | May 14 12:44:54 PM PDT 24 |
| Peak memory | 194268 kb |
| Host | smart-f81790ce-063d-4deb-a506-1a39d3a4d0d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285169799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1285169799 |
| Directory | /workspace/159.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2873326700 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1125990124662 ps |
| CPU time | 615.3 seconds |
| Started | May 14 12:41:59 PM PDT 24 |
| Finished | May 14 12:52:16 PM PDT 24 |
| Peak memory | 182464 kb |
| Host | smart-15930a4b-4867-4bf8-b92e-ce696c76eeca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873326700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.2873326700 |
| Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/190.rv_timer_random.3586455866 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2600900414399 ps |
| CPU time | 1326.68 seconds |
| Started | May 14 12:42:45 PM PDT 24 |
| Finished | May 14 01:04:57 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-2fc74731-198d-41fb-91c4-9c3394e871a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586455866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3586455866 |
| Directory | /workspace/190.rv_timer_random/latest |
| Test location | /workspace/coverage/default/192.rv_timer_random.962008210 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 260375779234 ps |
| CPU time | 702.48 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:54:29 PM PDT 24 |
| Peak memory | 191108 kb |
| Host | smart-80beae78-2924-42b4-8426-43911cb083d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962008210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.962008210 |
| Directory | /workspace/192.rv_timer_random/latest |
| Test location | /workspace/coverage/default/199.rv_timer_random.4261341751 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 134413008428 ps |
| CPU time | 111.57 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:44:45 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-f9c6c64b-37d8-487c-b7a2-9c11cc269e30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261341751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4261341751 |
| Directory | /workspace/199.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3495152252 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 197839986683 ps |
| CPU time | 304.57 seconds |
| Started | May 14 12:42:18 PM PDT 24 |
| Finished | May 14 12:47:23 PM PDT 24 |
| Peak memory | 182468 kb |
| Host | smart-0f47dc25-95f5-430e-81bc-0b25e3ce571a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495152252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.3495152252 |
| Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random.244585393 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 384474384037 ps |
| CPU time | 360.54 seconds |
| Started | May 14 12:42:18 PM PDT 24 |
| Finished | May 14 12:48:20 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-72c2dda7-f12a-4f3c-a622-22e3f976df9d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244585393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.244585393 |
| Directory | /workspace/30.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random.821628938 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 223656471038 ps |
| CPU time | 577.76 seconds |
| Started | May 14 12:41:59 PM PDT 24 |
| Finished | May 14 12:51:38 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-71002058-d89d-49bf-85a7-1647463180ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821628938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.821628938 |
| Directory | /workspace/4.rv_timer_random/latest |
| Test location | /workspace/coverage/default/82.rv_timer_random.3116869121 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 589946573784 ps |
| CPU time | 530.84 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:51:44 PM PDT 24 |
| Peak memory | 190740 kb |
| Host | smart-a1df40be-b2f9-4550-bdda-8ede6cac023a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116869121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3116869121 |
| Directory | /workspace/82.rv_timer_random/latest |
| Test location | /workspace/coverage/default/97.rv_timer_random.169459323 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 135833748840 ps |
| CPU time | 141.17 seconds |
| Started | May 14 12:42:40 PM PDT 24 |
| Finished | May 14 12:45:05 PM PDT 24 |
| Peak memory | 193608 kb |
| Host | smart-97ef1eb4-b354-4695-a43b-12d577a91c26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169459323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.169459323 |
| Directory | /workspace/97.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all.3508766348 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1115059836087 ps |
| CPU time | 456.57 seconds |
| Started | May 14 12:41:54 PM PDT 24 |
| Finished | May 14 12:49:33 PM PDT 24 |
| Peak memory | 190636 kb |
| Host | smart-c37d0a5b-44fb-4199-88dd-8ed23c22a6ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508766348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 3508766348 |
| Directory | /workspace/0.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.4224036057 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 17128246377 ps |
| CPU time | 30.89 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:42:22 PM PDT 24 |
| Peak memory | 182468 kb |
| Host | smart-1025a2c2-0d82-4bdc-930d-d15add17871f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224036057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.4224036057 |
| Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/106.rv_timer_random.2446216408 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 409040154177 ps |
| CPU time | 1300.51 seconds |
| Started | May 14 12:42:50 PM PDT 24 |
| Finished | May 14 01:04:35 PM PDT 24 |
| Peak memory | 190708 kb |
| Host | smart-5e4a32e1-a15c-4fdc-b58b-3a58a59807a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446216408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2446216408 |
| Directory | /workspace/106.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.4085120150 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 126318693486 ps |
| CPU time | 58.45 seconds |
| Started | May 14 12:42:10 PM PDT 24 |
| Finished | May 14 12:43:11 PM PDT 24 |
| Peak memory | 182552 kb |
| Host | smart-4f919587-9632-4653-90d8-4db101771a04 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085120150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.4085120150 |
| Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/116.rv_timer_random.2607285205 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 231739132604 ps |
| CPU time | 231.41 seconds |
| Started | May 14 12:42:36 PM PDT 24 |
| Finished | May 14 12:46:29 PM PDT 24 |
| Peak memory | 190676 kb |
| Host | smart-157e7396-5e4c-404d-af76-fb457b581f0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607285205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2607285205 |
| Directory | /workspace/116.rv_timer_random/latest |
| Test location | /workspace/coverage/default/117.rv_timer_random.2013549512 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 113621448685 ps |
| CPU time | 105.76 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:44:32 PM PDT 24 |
| Peak memory | 190812 kb |
| Host | smart-9336f159-e782-4ab4-b94c-ef1aab7d02a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013549512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2013549512 |
| Directory | /workspace/117.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all.3596228277 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 510270638294 ps |
| CPU time | 1997.44 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 01:15:29 PM PDT 24 |
| Peak memory | 190620 kb |
| Host | smart-40ad5ab8-661f-4344-a69e-8c90f288b1e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596228277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .3596228277 |
| Directory | /workspace/12.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/127.rv_timer_random.3288614673 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 86959994105 ps |
| CPU time | 125.37 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:44:52 PM PDT 24 |
| Peak memory | 194148 kb |
| Host | smart-a5660e88-6b71-478d-a101-7b4aad803b16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288614673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3288614673 |
| Directory | /workspace/127.rv_timer_random/latest |
| Test location | /workspace/coverage/default/136.rv_timer_random.2366009225 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 786722061796 ps |
| CPU time | 462.81 seconds |
| Started | May 14 12:42:41 PM PDT 24 |
| Finished | May 14 12:50:28 PM PDT 24 |
| Peak memory | 190676 kb |
| Host | smart-634149f3-d31a-4b51-87e9-2e9ef179db8f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366009225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2366009225 |
| Directory | /workspace/136.rv_timer_random/latest |
| Test location | /workspace/coverage/default/140.rv_timer_random.3264918937 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 647650672256 ps |
| CPU time | 526.46 seconds |
| Started | May 14 12:42:46 PM PDT 24 |
| Finished | May 14 12:51:38 PM PDT 24 |
| Peak memory | 190664 kb |
| Host | smart-09fdfe3e-79f9-4d90-9514-6a7a666cc9c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264918937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3264918937 |
| Directory | /workspace/140.rv_timer_random/latest |
| Test location | /workspace/coverage/default/151.rv_timer_random.3608516765 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 16365291771 ps |
| CPU time | 27.51 seconds |
| Started | May 14 12:42:43 PM PDT 24 |
| Finished | May 14 12:43:14 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-d58235b4-7310-4197-8064-899f9f51cf61 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608516765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3608516765 |
| Directory | /workspace/151.rv_timer_random/latest |
| Test location | /workspace/coverage/default/158.rv_timer_random.2136446161 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4460701973 ps |
| CPU time | 7.96 seconds |
| Started | May 14 12:42:44 PM PDT 24 |
| Finished | May 14 12:42:56 PM PDT 24 |
| Peak memory | 182468 kb |
| Host | smart-c10d15e5-b245-44c7-8f47-0364258cf9a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136446161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2136446161 |
| Directory | /workspace/158.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random_reset.1815970879 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 33864552741 ps |
| CPU time | 62.84 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 12:43:14 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-4520b349-6b45-4d55-b0bd-386a1ff4323b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815970879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1815970879 |
| Directory | /workspace/17.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/170.rv_timer_random.2391921770 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 48804560995 ps |
| CPU time | 28.26 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:43:14 PM PDT 24 |
| Peak memory | 182420 kb |
| Host | smart-190afcdd-1f58-435d-b39f-0aad81ef1e1e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391921770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2391921770 |
| Directory | /workspace/170.rv_timer_random/latest |
| Test location | /workspace/coverage/default/177.rv_timer_random.3401356549 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 130209077201 ps |
| CPU time | 1157.01 seconds |
| Started | May 14 12:42:36 PM PDT 24 |
| Finished | May 14 01:01:54 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-2affb613-43bd-41b7-8304-7b4e8932a08c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401356549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3401356549 |
| Directory | /workspace/177.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random_reset.3038429311 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 113916530572 ps |
| CPU time | 119.89 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:44:05 PM PDT 24 |
| Peak memory | 194020 kb |
| Host | smart-896dc55b-b713-4b37-af99-3439a680e8f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038429311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3038429311 |
| Directory | /workspace/19.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all.771150584 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 56729035179 ps |
| CPU time | 98.8 seconds |
| Started | May 14 12:42:14 PM PDT 24 |
| Finished | May 14 12:43:54 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-f1ce6cd2-e3a8-4ed6-8202-154155d26a3d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771150584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all. 771150584 |
| Directory | /workspace/21.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random.3510738501 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 563605253064 ps |
| CPU time | 274.08 seconds |
| Started | May 14 12:42:13 PM PDT 24 |
| Finished | May 14 12:46:49 PM PDT 24 |
| Peak memory | 193948 kb |
| Host | smart-ba634ed3-a9ba-49d6-a303-de9cc4fec179 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510738501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3510738501 |
| Directory | /workspace/23.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random_reset.559675319 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 33913115665 ps |
| CPU time | 52.16 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 12:43:03 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-1934e933-2e38-487e-9269-32f5443a2aaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559675319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.559675319 |
| Directory | /workspace/24.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random.2440948072 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 298782732674 ps |
| CPU time | 116.2 seconds |
| Started | May 14 12:42:11 PM PDT 24 |
| Finished | May 14 12:44:09 PM PDT 24 |
| Peak memory | 190652 kb |
| Host | smart-57a1c997-88de-44ee-a152-56242cce1e23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440948072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2440948072 |
| Directory | /workspace/26.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all.2311031300 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2251146656125 ps |
| CPU time | 615.71 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:52:24 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-fff399ed-c439-4bd4-8afd-d14098e3affd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311031300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .2311031300 |
| Directory | /workspace/29.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2337497542 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 98925797104 ps |
| CPU time | 58.32 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:43:04 PM PDT 24 |
| Peak memory | 182480 kb |
| Host | smart-f0041c63-ea31-48cb-bc0e-6459bf530768 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337497542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.2337497542 |
| Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all.2554742195 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 672393379204 ps |
| CPU time | 431.76 seconds |
| Started | May 14 12:42:24 PM PDT 24 |
| Finished | May 14 12:49:38 PM PDT 24 |
| Peak memory | 190644 kb |
| Host | smart-70bdde61-8e55-46b2-baac-d128b93d2240 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554742195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .2554742195 |
| Directory | /workspace/30.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random_reset.2420924092 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 55238632444 ps |
| CPU time | 89.08 seconds |
| Started | May 14 12:42:22 PM PDT 24 |
| Finished | May 14 12:43:52 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-0b25b95f-b70e-45c1-abb6-08ec1747ee4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2420924092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2420924092 |
| Directory | /workspace/36.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random.3872369113 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 75756757229 ps |
| CPU time | 793.34 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 12:55:25 PM PDT 24 |
| Peak memory | 190488 kb |
| Host | smart-a5305086-5979-4751-860c-92958c5feb35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872369113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3872369113 |
| Directory | /workspace/39.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2794230889 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1827322168164 ps |
| CPU time | 923.16 seconds |
| Started | May 14 12:42:00 PM PDT 24 |
| Finished | May 14 12:57:25 PM PDT 24 |
| Peak memory | 182472 kb |
| Host | smart-fb0bfe4a-76f8-4d8a-ba67-ff28ca74d890 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794230889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.2794230889 |
| Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all.3099455786 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 793403394617 ps |
| CPU time | 399.03 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:49:14 PM PDT 24 |
| Peak memory | 190636 kb |
| Host | smart-3d12e671-2111-4660-bdd0-7068e03fda0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099455786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all .3099455786 |
| Directory | /workspace/45.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all.2719923002 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 27748092103 ps |
| CPU time | 45.15 seconds |
| Started | May 14 12:42:20 PM PDT 24 |
| Finished | May 14 12:43:07 PM PDT 24 |
| Peak memory | 194112 kb |
| Host | smart-b6ca39fe-7a11-416c-b17c-42f6198f449a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719923002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all .2719923002 |
| Directory | /workspace/47.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1818830153 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 327163148719 ps |
| CPU time | 584.67 seconds |
| Started | May 14 12:42:40 PM PDT 24 |
| Finished | May 14 12:52:28 PM PDT 24 |
| Peak memory | 182456 kb |
| Host | smart-75c02cd0-60eb-4fd4-9370-23692a527937 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818830153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1818830153 |
| Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1943065473 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 250847451775 ps |
| CPU time | 142.37 seconds |
| Started | May 14 12:42:26 PM PDT 24 |
| Finished | May 14 12:44:50 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-96357975-71ab-4470-896d-9251a14a4a9a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943065473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.1943065473 |
| Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.703635397 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 611781674570 ps |
| CPU time | 534.07 seconds |
| Started | May 14 12:41:52 PM PDT 24 |
| Finished | May 14 12:50:50 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-0976d5a5-2882-4245-9262-5cf1c098d271 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703635397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .rv_timer_cfg_update_on_fly.703635397 |
| Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all.3565842320 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 519861449981 ps |
| CPU time | 1482.89 seconds |
| Started | May 14 12:41:58 PM PDT 24 |
| Finished | May 14 01:06:43 PM PDT 24 |
| Peak memory | 190636 kb |
| Host | smart-c66104ab-2bb9-4683-a15b-bd79f31c2f7d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565842320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all. 3565842320 |
| Directory | /workspace/7.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/95.rv_timer_random.3266262221 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 236848122087 ps |
| CPU time | 212.31 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:46:25 PM PDT 24 |
| Peak memory | 190428 kb |
| Host | smart-9d91a64f-63aa-40e9-afee-343ffeca792c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266262221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3266262221 |
| Directory | /workspace/95.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1885500545 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 48947288 ps |
| CPU time | 0.68 seconds |
| Started | May 14 12:41:26 PM PDT 24 |
| Finished | May 14 12:41:29 PM PDT 24 |
| Peak memory | 191740 kb |
| Host | smart-17dcb7ac-0fdc-4111-8d40-0705261c7f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885500545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia sing.1885500545 |
| Directory | /workspace/0.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3742524945 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 36435339 ps |
| CPU time | 1.4 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:47 PM PDT 24 |
| Peak memory | 182680 kb |
| Host | smart-dbd4e8c3-b4bf-49e8-a082-07a704e8ab35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742524945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ bash.3742524945 |
| Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1116575915 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 46845723 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:21 PM PDT 24 |
| Finished | May 14 12:41:24 PM PDT 24 |
| Peak memory | 182144 kb |
| Host | smart-3b5b252e-7703-45c3-8643-c0dbf0f16f71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116575915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.1116575915 |
| Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3112240657 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 33100765 ps |
| CPU time | 0.71 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 193976 kb |
| Host | smart-dbc6b734-8bfb-49fd-8b58-b1265ef9d9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112240657 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3112240657 |
| Directory | /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2802514535 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 28374766 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:39 PM PDT 24 |
| Finished | May 14 12:41:42 PM PDT 24 |
| Peak memory | 182552 kb |
| Host | smart-30824b56-c3b9-4850-9335-738823b34994 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802514535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2802514535 |
| Directory | /workspace/0.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2971406988 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 27408485 ps |
| CPU time | 0.56 seconds |
| Started | May 14 12:41:34 PM PDT 24 |
| Finished | May 14 12:41:36 PM PDT 24 |
| Peak memory | 182460 kb |
| Host | smart-9a2150cb-5fc4-4713-9394-bf3a7eac3c5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971406988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2971406988 |
| Directory | /workspace/0.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2688719105 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 133474104 ps |
| CPU time | 0.76 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:46 PM PDT 24 |
| Peak memory | 191564 kb |
| Host | smart-81a6c6e6-0dbd-4648-9a5b-9f0373d1c2b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688719105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti mer_same_csr_outstanding.2688719105 |
| Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2071119075 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 161209190 ps |
| CPU time | 2.09 seconds |
| Started | May 14 12:41:39 PM PDT 24 |
| Finished | May 14 12:41:43 PM PDT 24 |
| Peak memory | 197544 kb |
| Host | smart-2d120e1b-0197-4539-8874-677c88fd3a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071119075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2071119075 |
| Directory | /workspace/0.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4278247769 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 455537684 ps |
| CPU time | 1.43 seconds |
| Started | May 14 12:41:22 PM PDT 24 |
| Finished | May 14 12:41:26 PM PDT 24 |
| Peak memory | 194968 kb |
| Host | smart-5f8291e9-6ae0-4df5-b6af-ea0035525d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278247769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in tg_err.4278247769 |
| Directory | /workspace/0.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.683182782 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30375852 ps |
| CPU time | 0.71 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 182564 kb |
| Host | smart-21c31bce-6eac-4e5b-8a55-ae6c0948d732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683182782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias ing.683182782 |
| Directory | /workspace/1.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.279055902 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 35656016 ps |
| CPU time | 1.55 seconds |
| Started | May 14 12:41:31 PM PDT 24 |
| Finished | May 14 12:41:34 PM PDT 24 |
| Peak memory | 192272 kb |
| Host | smart-50bd9d07-a3ce-4f3f-a4c0-71008e58307b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279055902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b ash.279055902 |
| Directory | /workspace/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.181762015 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 68130232 ps |
| CPU time | 0.56 seconds |
| Started | May 14 12:41:33 PM PDT 24 |
| Finished | May 14 12:41:35 PM PDT 24 |
| Peak memory | 182544 kb |
| Host | smart-62a9b07b-ecd8-4c4e-987e-7a15a4b60a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181762015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re set.181762015 |
| Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3042719391 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 43790300 ps |
| CPU time | 0.74 seconds |
| Started | May 14 12:41:41 PM PDT 24 |
| Finished | May 14 12:41:44 PM PDT 24 |
| Peak memory | 195592 kb |
| Host | smart-d8472ae3-3d8b-4b53-b9b0-d29ba5d48729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042719391 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3042719391 |
| Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1664404591 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 16391489 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:32 PM PDT 24 |
| Finished | May 14 12:41:34 PM PDT 24 |
| Peak memory | 182568 kb |
| Host | smart-fb26ac0b-51ed-4e00-8944-76f8c02ca7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664404591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1664404591 |
| Directory | /workspace/1.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.297347923 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 53441028 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:32 PM PDT 24 |
| Finished | May 14 12:41:34 PM PDT 24 |
| Peak memory | 182328 kb |
| Host | smart-d3466e02-7d50-4e2f-a8fb-96d3ae57a7c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297347923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.297347923 |
| Directory | /workspace/1.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2889516254 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 37987117 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:51 PM PDT 24 |
| Finished | May 14 12:41:55 PM PDT 24 |
| Peak memory | 191208 kb |
| Host | smart-bdeb2c30-df57-41cb-beb5-6a25ca581c71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889516254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.2889516254 |
| Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3089389840 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 85533273 ps |
| CPU time | 1.78 seconds |
| Started | May 14 12:41:35 PM PDT 24 |
| Finished | May 14 12:41:38 PM PDT 24 |
| Peak memory | 197616 kb |
| Host | smart-270b740a-ceb4-49a2-9aa2-89fb046497f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089389840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3089389840 |
| Directory | /workspace/1.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1748510423 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 280352694 ps |
| CPU time | 1.08 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 194740 kb |
| Host | smart-ae543f0c-f3b9-487f-916f-8ddfe46f7c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748510423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in tg_err.1748510423 |
| Directory | /workspace/1.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2343652006 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 38210070 ps |
| CPU time | 1.56 seconds |
| Started | May 14 12:41:46 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 197416 kb |
| Host | smart-299e96cd-0bcf-4ba9-9974-686fac13cd60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343652006 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2343652006 |
| Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2420113424 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 16977253 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:40 PM PDT 24 |
| Finished | May 14 12:41:43 PM PDT 24 |
| Peak memory | 182424 kb |
| Host | smart-44bc041e-1221-4179-9326-37d11a57900b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420113424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2420113424 |
| Directory | /workspace/10.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.914711415 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 36976546 ps |
| CPU time | 0.84 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 193380 kb |
| Host | smart-43d55982-27e5-4814-a056-0c6546ca62a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914711415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti mer_same_csr_outstanding.914711415 |
| Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1852633160 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 470746544 ps |
| CPU time | 2.39 seconds |
| Started | May 14 12:41:30 PM PDT 24 |
| Finished | May 14 12:41:33 PM PDT 24 |
| Peak memory | 197396 kb |
| Host | smart-9e4b7e94-5b44-48e0-be71-325a870570f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852633160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1852633160 |
| Directory | /workspace/10.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2667748000 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1016066878 ps |
| CPU time | 1.01 seconds |
| Started | May 14 12:41:54 PM PDT 24 |
| Finished | May 14 12:41:58 PM PDT 24 |
| Peak memory | 195016 kb |
| Host | smart-4c512359-bd23-4037-b165-b7fa8eab20d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667748000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i ntg_err.2667748000 |
| Directory | /workspace/10.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3814472122 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 181761527 ps |
| CPU time | 0.68 seconds |
| Started | May 14 12:41:41 PM PDT 24 |
| Finished | May 14 12:41:48 PM PDT 24 |
| Peak memory | 194472 kb |
| Host | smart-980a34a3-25e5-4923-8877-06d47789614c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814472122 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3814472122 |
| Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4121787080 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 42874428 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:38 PM PDT 24 |
| Finished | May 14 12:41:42 PM PDT 24 |
| Peak memory | 182540 kb |
| Host | smart-cf30622c-4244-4628-81ac-a84e070b5499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121787080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4121787080 |
| Directory | /workspace/11.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2469258800 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 48734683 ps |
| CPU time | 0.59 seconds |
| Started | May 14 12:41:44 PM PDT 24 |
| Finished | May 14 12:41:47 PM PDT 24 |
| Peak memory | 182420 kb |
| Host | smart-fbb93d89-851a-4c4a-9aa9-198fcdbd2a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469258800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2469258800 |
| Directory | /workspace/11.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1634690746 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 16669355 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:31 PM PDT 24 |
| Finished | May 14 12:41:33 PM PDT 24 |
| Peak memory | 191348 kb |
| Host | smart-e93191ba-c9cb-428f-af75-f3452199d789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634690746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.1634690746 |
| Directory | /workspace/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3527659225 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 132013406 ps |
| CPU time | 2.57 seconds |
| Started | May 14 12:41:30 PM PDT 24 |
| Finished | May 14 12:41:34 PM PDT 24 |
| Peak memory | 197396 kb |
| Host | smart-591bec8d-a7a2-4ade-ac32-0f97c4f4b6dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527659225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3527659225 |
| Directory | /workspace/11.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4106277313 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 246263622 ps |
| CPU time | 1.08 seconds |
| Started | May 14 12:41:46 PM PDT 24 |
| Finished | May 14 12:41:49 PM PDT 24 |
| Peak memory | 183096 kb |
| Host | smart-42339b0c-47e9-4879-896e-7fc3934a8dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106277313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i ntg_err.4106277313 |
| Directory | /workspace/11.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.968180892 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 409428194 ps |
| CPU time | 1 seconds |
| Started | May 14 12:41:44 PM PDT 24 |
| Finished | May 14 12:41:47 PM PDT 24 |
| Peak memory | 197212 kb |
| Host | smart-7222961c-25c6-4909-bc57-d44fd72ed2a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968180892 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.968180892 |
| Directory | /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1742127210 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 13431272 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:41 PM PDT 24 |
| Finished | May 14 12:41:44 PM PDT 24 |
| Peak memory | 182544 kb |
| Host | smart-1d664999-a8c4-4e78-8dd0-e71c057f81c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742127210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1742127210 |
| Directory | /workspace/12.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.801110946 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 89380164 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:42 PM PDT 24 |
| Finished | May 14 12:41:45 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-d6d0bf18-4380-4aad-85fc-12714ebe8b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801110946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.801110946 |
| Directory | /workspace/12.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1543921794 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 84958075 ps |
| CPU time | 0.61 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 191800 kb |
| Host | smart-0b186efb-7963-4762-92b3-7525c24b959a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543921794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t imer_same_csr_outstanding.1543921794 |
| Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2622208486 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 27474639 ps |
| CPU time | 0.89 seconds |
| Started | May 14 12:41:42 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 194988 kb |
| Host | smart-4fcc9ccc-64c9-40af-92d4-1c951845cda1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622208486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2622208486 |
| Directory | /workspace/12.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3058655615 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 149960895 ps |
| CPU time | 0.99 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:53 PM PDT 24 |
| Peak memory | 183320 kb |
| Host | smart-f7439867-a038-46d8-a9d3-e163627b7208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058655615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.3058655615 |
| Directory | /workspace/12.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1379407979 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 92711927 ps |
| CPU time | 0.77 seconds |
| Started | May 14 12:41:58 PM PDT 24 |
| Finished | May 14 12:42:01 PM PDT 24 |
| Peak memory | 195960 kb |
| Host | smart-2ede4d70-aa42-4214-a3b7-25079f0e09d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379407979 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1379407979 |
| Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.394705335 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 12520935 ps |
| CPU time | 0.57 seconds |
| Started | May 14 12:41:38 PM PDT 24 |
| Finished | May 14 12:41:42 PM PDT 24 |
| Peak memory | 182536 kb |
| Host | smart-7fac8d4d-13d4-4af6-ba33-ba35de2e3092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394705335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.394705335 |
| Directory | /workspace/13.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2100904918 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 17108516 ps |
| CPU time | 0.57 seconds |
| Started | May 14 12:41:39 PM PDT 24 |
| Finished | May 14 12:41:43 PM PDT 24 |
| Peak memory | 182380 kb |
| Host | smart-be3bd461-810c-41ec-82b8-29e32c5e372f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100904918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2100904918 |
| Directory | /workspace/13.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3198039844 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 65812456 ps |
| CPU time | 0.83 seconds |
| Started | May 14 12:42:00 PM PDT 24 |
| Finished | May 14 12:42:03 PM PDT 24 |
| Peak memory | 193424 kb |
| Host | smart-5fb57a97-cca7-401f-99fe-84bc90b25de3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198039844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t imer_same_csr_outstanding.3198039844 |
| Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2295870642 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2211761584 ps |
| CPU time | 2.53 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 12:42:09 PM PDT 24 |
| Peak memory | 197472 kb |
| Host | smart-3f0d3b00-3746-4a94-b733-052058cc044c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295870642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2295870642 |
| Directory | /workspace/13.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3286000611 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 89423644 ps |
| CPU time | 0.86 seconds |
| Started | May 14 12:41:55 PM PDT 24 |
| Finished | May 14 12:41:59 PM PDT 24 |
| Peak memory | 193368 kb |
| Host | smart-8a63d42f-21e3-4b83-b106-8c7a93bdbb52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286000611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.3286000611 |
| Directory | /workspace/13.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1440304323 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 22586255 ps |
| CPU time | 0.94 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:52 PM PDT 24 |
| Peak memory | 197268 kb |
| Host | smart-af73a647-bf8e-40cc-8a65-472fc9e20ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440304323 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1440304323 |
| Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1472622774 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 13708511 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:52 PM PDT 24 |
| Finished | May 14 12:41:55 PM PDT 24 |
| Peak memory | 182532 kb |
| Host | smart-d062a162-0e20-40c5-bbd4-d42fa1d3f650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472622774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1472622774 |
| Directory | /workspace/14.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2954905465 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 24697741 ps |
| CPU time | 0.56 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:42:21 PM PDT 24 |
| Peak memory | 182496 kb |
| Host | smart-55e97a1e-c035-4a68-8b19-144cc313ed51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954905465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2954905465 |
| Directory | /workspace/14.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4254432727 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 61295849 ps |
| CPU time | 0.6 seconds |
| Started | May 14 12:41:45 PM PDT 24 |
| Finished | May 14 12:41:48 PM PDT 24 |
| Peak memory | 192248 kb |
| Host | smart-2f027937-09da-4754-b7ef-41886a17e0dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254432727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.4254432727 |
| Directory | /workspace/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1416651775 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 45839792 ps |
| CPU time | 0.87 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:41:57 PM PDT 24 |
| Peak memory | 196884 kb |
| Host | smart-79ca94f1-cf02-4f45-88a3-828b0440ca6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416651775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1416651775 |
| Directory | /workspace/14.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3549061005 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 42491290 ps |
| CPU time | 1.59 seconds |
| Started | May 14 12:41:56 PM PDT 24 |
| Finished | May 14 12:42:00 PM PDT 24 |
| Peak memory | 197488 kb |
| Host | smart-af7bb2bc-5181-440a-b7ef-3ec73198a92b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549061005 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3549061005 |
| Directory | /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1714581990 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 25126377 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:46 PM PDT 24 |
| Finished | May 14 12:41:54 PM PDT 24 |
| Peak memory | 182508 kb |
| Host | smart-c99d5176-407c-4e64-9929-f6e355ef8bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714581990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1714581990 |
| Directory | /workspace/15.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1191624961 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 29154798 ps |
| CPU time | 0.75 seconds |
| Started | May 14 12:41:54 PM PDT 24 |
| Finished | May 14 12:41:58 PM PDT 24 |
| Peak memory | 193192 kb |
| Host | smart-3c2a2481-80b9-45a0-bde0-ef4cf2b43458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191624961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t imer_same_csr_outstanding.1191624961 |
| Directory | /workspace/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2269703358 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 337975247 ps |
| CPU time | 1.81 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:51 PM PDT 24 |
| Peak memory | 197448 kb |
| Host | smart-c24dd7ce-b30c-46f9-a706-802d1e88174d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269703358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2269703358 |
| Directory | /workspace/15.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2382326444 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 41981928 ps |
| CPU time | 0.83 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 192584 kb |
| Host | smart-e81f8fb1-f3e3-4f14-bcf0-4de6a7ca544a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382326444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i ntg_err.2382326444 |
| Directory | /workspace/15.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3131626137 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 79927475 ps |
| CPU time | 0.69 seconds |
| Started | May 14 12:41:42 PM PDT 24 |
| Finished | May 14 12:41:45 PM PDT 24 |
| Peak memory | 194860 kb |
| Host | smart-0bd9385a-4da4-409b-b1f8-6bbd01ee11e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131626137 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3131626137 |
| Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3383116557 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 15989616 ps |
| CPU time | 0.6 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:42:04 PM PDT 24 |
| Peak memory | 182524 kb |
| Host | smart-3b41a265-8b6e-4871-947a-f3eefc174670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383116557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3383116557 |
| Directory | /workspace/16.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3638620875 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 47081385 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:42:05 PM PDT 24 |
| Peak memory | 182264 kb |
| Host | smart-4b7cdd83-da84-42d5-837e-d92ed5cd149c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638620875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3638620875 |
| Directory | /workspace/16.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3518324254 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 15898157 ps |
| CPU time | 0.77 seconds |
| Started | May 14 12:41:58 PM PDT 24 |
| Finished | May 14 12:42:00 PM PDT 24 |
| Peak memory | 193108 kb |
| Host | smart-c81dbe78-7ab3-40b4-a2f8-f8bad786da98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518324254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t imer_same_csr_outstanding.3518324254 |
| Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.503786326 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 57062153 ps |
| CPU time | 2.54 seconds |
| Started | May 14 12:41:54 PM PDT 24 |
| Finished | May 14 12:42:04 PM PDT 24 |
| Peak memory | 197464 kb |
| Host | smart-2fa5cf93-d5a0-4cc7-8b51-a07fb3df4b1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503786326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.503786326 |
| Directory | /workspace/16.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.207973336 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 636865357 ps |
| CPU time | 0.88 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:42:04 PM PDT 24 |
| Peak memory | 183056 kb |
| Host | smart-92d4995c-7225-47da-b8df-7aac4aef467d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207973336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in tg_err.207973336 |
| Directory | /workspace/16.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3959619982 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 62609062 ps |
| CPU time | 0.8 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:41:51 PM PDT 24 |
| Peak memory | 196532 kb |
| Host | smart-9de0b855-fe47-4442-8bff-ce5de63a7ade |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959619982 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3959619982 |
| Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4125444401 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 28971841 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:42 PM PDT 24 |
| Finished | May 14 12:41:45 PM PDT 24 |
| Peak memory | 182548 kb |
| Host | smart-8dfe781a-1bd8-427f-8360-c3c0384d0759 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125444401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4125444401 |
| Directory | /workspace/17.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3059581748 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 12594088 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:55 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-c0f28990-6508-4dab-8a05-f1ca3205eb79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059581748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3059581748 |
| Directory | /workspace/17.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2950433881 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 18926493 ps |
| CPU time | 0.64 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 12:42:07 PM PDT 24 |
| Peak memory | 191408 kb |
| Host | smart-ed662f65-ffdc-4ae0-9b2d-399643203836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950433881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t imer_same_csr_outstanding.2950433881 |
| Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3535223997 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 179967433 ps |
| CPU time | 2.79 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:54 PM PDT 24 |
| Peak memory | 197472 kb |
| Host | smart-dc81dc2c-a43f-4e3a-9e63-b063ca603d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535223997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3535223997 |
| Directory | /workspace/17.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3181042436 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 82146681 ps |
| CPU time | 0.78 seconds |
| Started | May 14 12:41:39 PM PDT 24 |
| Finished | May 14 12:41:43 PM PDT 24 |
| Peak memory | 193172 kb |
| Host | smart-2fd2b796-83a1-4683-8cd9-f686b03177b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181042436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i ntg_err.3181042436 |
| Directory | /workspace/17.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.462156119 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 93516760 ps |
| CPU time | 1.06 seconds |
| Started | May 14 12:41:52 PM PDT 24 |
| Finished | May 14 12:41:57 PM PDT 24 |
| Peak memory | 197364 kb |
| Host | smart-9ba15eb1-6d1b-4bb9-9964-985fd1f89e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462156119 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.462156119 |
| Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2949051463 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 15315598 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:46 PM PDT 24 |
| Peak memory | 182556 kb |
| Host | smart-2b07d810-d897-4328-bb16-2098e0a1cb38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949051463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2949051463 |
| Directory | /workspace/18.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2917221171 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 14134157 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:53 PM PDT 24 |
| Peak memory | 182380 kb |
| Host | smart-ef31d4ce-d1e8-4ada-85c7-dcd6683827f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917221171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2917221171 |
| Directory | /workspace/18.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3509123370 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 50413536 ps |
| CPU time | 0.68 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:42:06 PM PDT 24 |
| Peak memory | 191560 kb |
| Host | smart-b3a8debc-b418-496a-b10a-9b07a6843527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509123370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.3509123370 |
| Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.328942371 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1429226175 ps |
| CPU time | 3.33 seconds |
| Started | May 14 12:41:40 PM PDT 24 |
| Finished | May 14 12:41:46 PM PDT 24 |
| Peak memory | 197456 kb |
| Host | smart-b6e68207-548b-4fb2-b31f-01c08b47640d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328942371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.328942371 |
| Directory | /workspace/18.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3945338202 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 394294900 ps |
| CPU time | 1.29 seconds |
| Started | May 14 12:41:53 PM PDT 24 |
| Finished | May 14 12:41:57 PM PDT 24 |
| Peak memory | 195292 kb |
| Host | smart-627bfb14-d53c-424f-b737-88de8c74a4b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945338202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i ntg_err.3945338202 |
| Directory | /workspace/18.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.955301391 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 33506155 ps |
| CPU time | 0.61 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:42:05 PM PDT 24 |
| Peak memory | 193164 kb |
| Host | smart-6d090594-091a-40bf-9399-23b909c85c48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955301391 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.955301391 |
| Directory | /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3924482807 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 15068451 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:50 PM PDT 24 |
| Finished | May 14 12:41:54 PM PDT 24 |
| Peak memory | 182580 kb |
| Host | smart-2b3b8777-b02c-4acb-b8e4-a1ace9b852d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924482807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3924482807 |
| Directory | /workspace/19.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.370590915 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 15556333 ps |
| CPU time | 0.52 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:42:04 PM PDT 24 |
| Peak memory | 182520 kb |
| Host | smart-5fc183ec-7b45-4bc3-982b-ed60a5a499e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370590915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.370590915 |
| Directory | /workspace/19.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4114633987 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 70014318 ps |
| CPU time | 0.61 seconds |
| Started | May 14 12:41:46 PM PDT 24 |
| Finished | May 14 12:41:49 PM PDT 24 |
| Peak memory | 191280 kb |
| Host | smart-ab448c88-7a8b-4a9e-abc5-ddf8e7ba46de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114633987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.4114633987 |
| Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2483969640 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 424195447 ps |
| CPU time | 3.01 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:42:08 PM PDT 24 |
| Peak memory | 197460 kb |
| Host | smart-44b62116-1388-45e5-a076-504cc3f16502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483969640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2483969640 |
| Directory | /workspace/19.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1524132335 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 285643908 ps |
| CPU time | 0.8 seconds |
| Started | May 14 12:41:51 PM PDT 24 |
| Finished | May 14 12:41:56 PM PDT 24 |
| Peak memory | 193508 kb |
| Host | smart-1213434b-d580-48e3-bd53-580dc31a776f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524132335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i ntg_err.1524132335 |
| Directory | /workspace/19.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2184120889 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 30203397 ps |
| CPU time | 0.73 seconds |
| Started | May 14 12:41:44 PM PDT 24 |
| Finished | May 14 12:41:47 PM PDT 24 |
| Peak memory | 192192 kb |
| Host | smart-f28b3be6-d407-4838-a98e-d94bcadbaf88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184120889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia sing.2184120889 |
| Directory | /workspace/2.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.813180452 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 139044241 ps |
| CPU time | 1.43 seconds |
| Started | May 14 12:41:32 PM PDT 24 |
| Finished | May 14 12:41:35 PM PDT 24 |
| Peak memory | 192196 kb |
| Host | smart-9350a7c5-863d-4f0e-8eb8-a487ba2c571f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813180452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b ash.813180452 |
| Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.380174244 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 19792776 ps |
| CPU time | 0.65 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:38 PM PDT 24 |
| Peak memory | 182572 kb |
| Host | smart-8b57b5f3-1ab3-4fa3-8d42-5c57dfa1e250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380174244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re set.380174244 |
| Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1389068649 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 21667233 ps |
| CPU time | 0.7 seconds |
| Started | May 14 12:41:35 PM PDT 24 |
| Finished | May 14 12:41:37 PM PDT 24 |
| Peak memory | 194872 kb |
| Host | smart-d8f3b4bd-c8bb-41a9-bce5-fc1f67a24735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389068649 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1389068649 |
| Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3026445581 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 19642515 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 181724 kb |
| Host | smart-d2bc90e7-2093-4190-b195-9f4169c71b1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026445581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3026445581 |
| Directory | /workspace/2.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2771913722 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 17149306 ps |
| CPU time | 0.56 seconds |
| Started | May 14 12:41:23 PM PDT 24 |
| Finished | May 14 12:41:25 PM PDT 24 |
| Peak memory | 182464 kb |
| Host | smart-83409d32-bda3-44ba-bb43-675a1e527667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771913722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2771913722 |
| Directory | /workspace/2.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3481109745 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 34643766 ps |
| CPU time | 0.63 seconds |
| Started | May 14 12:41:18 PM PDT 24 |
| Finished | May 14 12:41:22 PM PDT 24 |
| Peak memory | 190772 kb |
| Host | smart-ec4d44cf-737c-4d10-b84d-f1b8752bb1e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481109745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti mer_same_csr_outstanding.3481109745 |
| Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2020556961 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 505758775 ps |
| CPU time | 1.93 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:40 PM PDT 24 |
| Peak memory | 197464 kb |
| Host | smart-e096134d-ab6f-4d14-9556-9ca8363701a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020556961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2020556961 |
| Directory | /workspace/2.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2368939913 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 25594527 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:50 PM PDT 24 |
| Finished | May 14 12:41:54 PM PDT 24 |
| Peak memory | 182072 kb |
| Host | smart-8861e910-f78c-4e85-b177-1961a733988d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368939913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2368939913 |
| Directory | /workspace/20.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1806014984 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 12900018 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:37 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 181912 kb |
| Host | smart-b98ea877-b4be-485d-b06b-82eb08ef334d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806014984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1806014984 |
| Directory | /workspace/21.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.791591441 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 20493700 ps |
| CPU time | 0.5 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:42:06 PM PDT 24 |
| Peak memory | 182088 kb |
| Host | smart-edcb53c3-5694-4f16-ae20-74426627da05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791591441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.791591441 |
| Directory | /workspace/22.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3560646696 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 56473675 ps |
| CPU time | 0.52 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:46 PM PDT 24 |
| Peak memory | 182112 kb |
| Host | smart-de2aa808-6c64-4497-bbd6-56e744a8ba25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560646696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3560646696 |
| Directory | /workspace/23.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2936926940 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 16704207 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:42:06 PM PDT 24 |
| Peak memory | 182428 kb |
| Host | smart-2eeabcb2-2fc3-4d7d-a7bd-bcb126e552b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936926940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2936926940 |
| Directory | /workspace/24.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3158209737 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 52613123 ps |
| CPU time | 0.59 seconds |
| Started | May 14 12:41:59 PM PDT 24 |
| Finished | May 14 12:42:01 PM PDT 24 |
| Peak memory | 182512 kb |
| Host | smart-6cfe5131-f8ac-4b7b-a24d-8beafebdef5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158209737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3158209737 |
| Directory | /workspace/25.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3664392917 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 41970338 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:41:51 PM PDT 24 |
| Peak memory | 182324 kb |
| Host | smart-4ee82fd8-2fc0-4c15-bf10-01d82f1779f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664392917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3664392917 |
| Directory | /workspace/26.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.760708797 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 14853021 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:46 PM PDT 24 |
| Peak memory | 182524 kb |
| Host | smart-cfb24512-cefd-431f-9963-8557d20bca17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760708797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.760708797 |
| Directory | /workspace/27.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1123899374 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 113373865 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:56 PM PDT 24 |
| Finished | May 14 12:41:59 PM PDT 24 |
| Peak memory | 182420 kb |
| Host | smart-74949a7c-e625-4120-b1f8-d650520e648b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123899374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1123899374 |
| Directory | /workspace/28.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.354433502 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 61977528 ps |
| CPU time | 0.52 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:41:51 PM PDT 24 |
| Peak memory | 182432 kb |
| Host | smart-b8c9a646-0971-4360-b7ba-e9489a611bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354433502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.354433502 |
| Directory | /workspace/29.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4011511241 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3084007719 ps |
| CPU time | 3.59 seconds |
| Started | May 14 12:41:44 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 192948 kb |
| Host | smart-02fcf484-fdf3-45fc-9c85-e729540d19bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011511241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.4011511241 |
| Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.566502847 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 26254901 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:46 PM PDT 24 |
| Peak memory | 182652 kb |
| Host | smart-f15af689-6c6c-460a-90a0-b851390851ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566502847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re set.566502847 |
| Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1025029638 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 34487105 ps |
| CPU time | 1.47 seconds |
| Started | May 14 12:41:30 PM PDT 24 |
| Finished | May 14 12:41:32 PM PDT 24 |
| Peak memory | 197384 kb |
| Host | smart-756e66e9-7b2c-4708-b213-2cf41905ce54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025029638 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1025029638 |
| Directory | /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.229944314 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 20652284 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:31 PM PDT 24 |
| Finished | May 14 12:41:33 PM PDT 24 |
| Peak memory | 182660 kb |
| Host | smart-19f8f31c-3a20-4912-a002-8bddbb40bbec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229944314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.229944314 |
| Directory | /workspace/3.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4229103709 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 35407536 ps |
| CPU time | 0.51 seconds |
| Started | May 14 12:41:35 PM PDT 24 |
| Finished | May 14 12:41:37 PM PDT 24 |
| Peak memory | 181900 kb |
| Host | smart-0b03a14f-7984-42e8-af29-8501c25879ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229103709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4229103709 |
| Directory | /workspace/3.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2881689327 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 44179536 ps |
| CPU time | 0.69 seconds |
| Started | May 14 12:41:21 PM PDT 24 |
| Finished | May 14 12:41:24 PM PDT 24 |
| Peak memory | 192888 kb |
| Host | smart-05cc18ac-be51-4563-a0e0-66ada1f94e84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881689327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti mer_same_csr_outstanding.2881689327 |
| Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2820408377 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 300441970 ps |
| CPU time | 1.57 seconds |
| Started | May 14 12:41:29 PM PDT 24 |
| Finished | May 14 12:41:32 PM PDT 24 |
| Peak memory | 197424 kb |
| Host | smart-f6b303dc-a024-4c83-a83e-c351b74b29fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820408377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2820408377 |
| Directory | /workspace/3.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1660265563 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 126901469 ps |
| CPU time | 1.4 seconds |
| Started | May 14 12:41:33 PM PDT 24 |
| Finished | May 14 12:41:36 PM PDT 24 |
| Peak memory | 195104 kb |
| Host | smart-9542b37c-0f48-4514-82ea-d31e474f562e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660265563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.1660265563 |
| Directory | /workspace/3.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.366634030 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 17156889 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:52 PM PDT 24 |
| Finished | May 14 12:41:56 PM PDT 24 |
| Peak memory | 182420 kb |
| Host | smart-dce601b0-627c-479b-aa6f-7b1d3aa87360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366634030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.366634030 |
| Directory | /workspace/30.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2922302403 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 100704328 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-79d9f3d0-9b06-4d54-a95f-46de8bef43a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922302403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2922302403 |
| Directory | /workspace/31.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1707266423 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 26002970 ps |
| CPU time | 0.61 seconds |
| Started | May 14 12:41:53 PM PDT 24 |
| Finished | May 14 12:41:57 PM PDT 24 |
| Peak memory | 182416 kb |
| Host | smart-1ac22536-a07a-4a72-bfb3-10c6c3059239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707266423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1707266423 |
| Directory | /workspace/32.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.865006271 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 17699801 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:58 PM PDT 24 |
| Finished | May 14 12:42:00 PM PDT 24 |
| Peak memory | 182396 kb |
| Host | smart-5f3efc4e-21b7-4457-9ed5-cd13af8b9d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865006271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.865006271 |
| Directory | /workspace/33.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.180764941 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 37374714 ps |
| CPU time | 0.56 seconds |
| Started | May 14 12:41:46 PM PDT 24 |
| Finished | May 14 12:41:49 PM PDT 24 |
| Peak memory | 182380 kb |
| Host | smart-93df1e2a-46ba-4c5e-8e58-0bc9792519a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180764941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.180764941 |
| Directory | /workspace/34.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2267084328 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 16806859 ps |
| CPU time | 0.6 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:42:06 PM PDT 24 |
| Peak memory | 182568 kb |
| Host | smart-18384728-b40c-4cdb-9a9b-c1b37d899b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267084328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2267084328 |
| Directory | /workspace/35.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.805068866 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 15435558 ps |
| CPU time | 0.56 seconds |
| Started | May 14 12:41:51 PM PDT 24 |
| Finished | May 14 12:41:55 PM PDT 24 |
| Peak memory | 182096 kb |
| Host | smart-8d0bb016-89d4-4fcc-a70d-db81a331c9e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805068866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.805068866 |
| Directory | /workspace/36.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2505169902 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 16866427 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:46 PM PDT 24 |
| Peak memory | 182240 kb |
| Host | smart-1494f4dd-c8ef-4c03-beaa-2852bfe8bca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505169902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2505169902 |
| Directory | /workspace/37.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3286717192 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 165146561 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:42:04 PM PDT 24 |
| Peak memory | 181892 kb |
| Host | smart-fa9c3ff7-7c7e-45b7-aa9c-f6b825376d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286717192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3286717192 |
| Directory | /workspace/38.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1487116304 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 71923490 ps |
| CPU time | 0.51 seconds |
| Started | May 14 12:41:50 PM PDT 24 |
| Finished | May 14 12:41:54 PM PDT 24 |
| Peak memory | 181920 kb |
| Host | smart-a5ac073b-28f6-4086-b80d-957e1e6ef7aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487116304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1487116304 |
| Directory | /workspace/39.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2031809715 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 120994597 ps |
| CPU time | 0.8 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 192540 kb |
| Host | smart-dc703b53-3269-492a-a4d2-2831daa76bfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031809715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.2031809715 |
| Directory | /workspace/4.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4205541153 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 415403286 ps |
| CPU time | 3.55 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:49 PM PDT 24 |
| Peak memory | 190948 kb |
| Host | smart-03e26569-bebd-4d71-8762-c060b05239ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205541153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.4205541153 |
| Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2247871687 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 39010855 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:56 PM PDT 24 |
| Peak memory | 182548 kb |
| Host | smart-30840fb5-f0f3-412f-ba29-97cb45bac28b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247871687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.2247871687 |
| Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3255435312 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 22281109 ps |
| CPU time | 0.66 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:41:52 PM PDT 24 |
| Peak memory | 194236 kb |
| Host | smart-8a2f7ace-5670-4aa0-b8ca-9ccd0d8f3dbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255435312 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3255435312 |
| Directory | /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3405643310 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 32289820 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:44 PM PDT 24 |
| Finished | May 14 12:41:47 PM PDT 24 |
| Peak memory | 182348 kb |
| Host | smart-8d8b5b16-9fcf-4d65-a526-8d8667cbfe78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405643310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3405643310 |
| Directory | /workspace/4.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.468070840 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 12461758 ps |
| CPU time | 0.52 seconds |
| Started | May 14 12:41:34 PM PDT 24 |
| Finished | May 14 12:41:36 PM PDT 24 |
| Peak memory | 181940 kb |
| Host | smart-3dc9bf16-6eea-4553-a87b-09aa7ac4903d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468070840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.468070840 |
| Directory | /workspace/4.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4126739320 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 68843247 ps |
| CPU time | 0.78 seconds |
| Started | May 14 12:41:37 PM PDT 24 |
| Finished | May 14 12:41:40 PM PDT 24 |
| Peak memory | 191568 kb |
| Host | smart-5f7f6920-3e5b-446d-9164-294fc9201f19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126739320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.4126739320 |
| Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.166564246 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 45894137 ps |
| CPU time | 1.14 seconds |
| Started | May 14 12:41:34 PM PDT 24 |
| Finished | May 14 12:41:36 PM PDT 24 |
| Peak memory | 191088 kb |
| Host | smart-307b84ae-1cf2-46dd-8d64-8370e423343a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166564246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.166564246 |
| Directory | /workspace/4.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4257662653 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 237018852 ps |
| CPU time | 1.11 seconds |
| Started | May 14 12:41:35 PM PDT 24 |
| Finished | May 14 12:41:39 PM PDT 24 |
| Peak memory | 183196 kb |
| Host | smart-e2caab85-87b3-473b-b2ee-ef3d95e7c6ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257662653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.4257662653 |
| Directory | /workspace/4.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1662412530 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 16739314 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:53 PM PDT 24 |
| Peak memory | 182536 kb |
| Host | smart-e72dc114-885a-4550-a69f-52b76a97b947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662412530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1662412530 |
| Directory | /workspace/40.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.4142439024 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 15800875 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:44 PM PDT 24 |
| Finished | May 14 12:41:47 PM PDT 24 |
| Peak memory | 182380 kb |
| Host | smart-fe50a6ab-e5a3-43a4-aeaf-e22954967f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142439024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.4142439024 |
| Directory | /workspace/41.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2292443399 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 52469956 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:52 PM PDT 24 |
| Peak memory | 182792 kb |
| Host | smart-1ad7a53f-1354-429e-aebe-775ee168e77d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292443399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2292443399 |
| Directory | /workspace/42.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3476410214 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 19210186 ps |
| CPU time | 0.57 seconds |
| Started | May 14 12:41:53 PM PDT 24 |
| Finished | May 14 12:41:56 PM PDT 24 |
| Peak memory | 182388 kb |
| Host | smart-0ab0dbbd-01b6-413e-b355-e0efc9d38bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476410214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3476410214 |
| Directory | /workspace/43.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1771205271 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 13613924 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:52 PM PDT 24 |
| Peak memory | 182368 kb |
| Host | smart-0ec0cebc-51c6-412e-a46b-54d8fe16e44a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771205271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1771205271 |
| Directory | /workspace/44.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.206417375 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 13160906 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:53 PM PDT 24 |
| Peak memory | 182420 kb |
| Host | smart-be344b88-1681-4b94-beaf-880eff9be5dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206417375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.206417375 |
| Directory | /workspace/45.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1480140939 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 24534564 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:56 PM PDT 24 |
| Finished | May 14 12:41:59 PM PDT 24 |
| Peak memory | 182384 kb |
| Host | smart-6bdc5952-05ef-4991-b55e-dedf9054cc3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480140939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1480140939 |
| Directory | /workspace/46.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1835923124 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 24450028 ps |
| CPU time | 0.52 seconds |
| Started | May 14 12:42:00 PM PDT 24 |
| Finished | May 14 12:42:02 PM PDT 24 |
| Peak memory | 182212 kb |
| Host | smart-6f492a07-23ba-4444-b958-fbbafb4a0816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835923124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1835923124 |
| Directory | /workspace/47.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3422489310 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 24133444 ps |
| CPU time | 0.52 seconds |
| Started | May 14 12:41:52 PM PDT 24 |
| Finished | May 14 12:41:56 PM PDT 24 |
| Peak memory | 181896 kb |
| Host | smart-204846fe-a49f-4b90-9e01-93d27f61ed0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422489310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3422489310 |
| Directory | /workspace/48.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4282546208 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 40321930 ps |
| CPU time | 0.51 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 182028 kb |
| Host | smart-a737b8bb-c551-409a-a403-7ec4a124607a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282546208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4282546208 |
| Directory | /workspace/49.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1982103668 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 87229258 ps |
| CPU time | 0.93 seconds |
| Started | May 14 12:41:46 PM PDT 24 |
| Finished | May 14 12:41:49 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-3e0f968d-d58a-4c9b-a919-ceb1b420b46b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982103668 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1982103668 |
| Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2798574969 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 20545029 ps |
| CPU time | 0.59 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:41:52 PM PDT 24 |
| Peak memory | 182572 kb |
| Host | smart-7e59b24d-aa1b-4dce-b9c8-0661840fffb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798574969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2798574969 |
| Directory | /workspace/5.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4127856525 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 48809807 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:45 PM PDT 24 |
| Finished | May 14 12:41:48 PM PDT 24 |
| Peak memory | 182364 kb |
| Host | smart-cffa2e48-ccec-41a0-8dcb-e3258f887131 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127856525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4127856525 |
| Directory | /workspace/5.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1934903903 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 92678939 ps |
| CPU time | 0.71 seconds |
| Started | May 14 12:41:38 PM PDT 24 |
| Finished | May 14 12:41:42 PM PDT 24 |
| Peak memory | 193248 kb |
| Host | smart-5a96a9d7-c0d0-49da-8524-78cc667b23a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934903903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.1934903903 |
| Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1739056616 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 87938156 ps |
| CPU time | 1.24 seconds |
| Started | May 14 12:41:35 PM PDT 24 |
| Finished | May 14 12:41:37 PM PDT 24 |
| Peak memory | 197396 kb |
| Host | smart-ddfa1626-abc0-4689-8dd2-4f568bcf7a72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739056616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1739056616 |
| Directory | /workspace/5.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4113135858 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 151685550 ps |
| CPU time | 1.3 seconds |
| Started | May 14 12:41:30 PM PDT 24 |
| Finished | May 14 12:41:32 PM PDT 24 |
| Peak memory | 183068 kb |
| Host | smart-17f7ef13-a2fa-429b-86c1-0ac0c9a7ba59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113135858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in tg_err.4113135858 |
| Directory | /workspace/5.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.929999648 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 302302344 ps |
| CPU time | 1.43 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:40 PM PDT 24 |
| Peak memory | 197460 kb |
| Host | smart-e6fc8e12-9f11-4300-a38f-1e940eff1637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929999648 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.929999648 |
| Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1517932452 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 14310060 ps |
| CPU time | 0.56 seconds |
| Started | May 14 12:41:38 PM PDT 24 |
| Finished | May 14 12:41:42 PM PDT 24 |
| Peak memory | 182520 kb |
| Host | smart-083e14df-e0e5-4816-8bc3-48f3d51938a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517932452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1517932452 |
| Directory | /workspace/6.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2940490542 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 23086248 ps |
| CPU time | 0.53 seconds |
| Started | May 14 12:41:54 PM PDT 24 |
| Finished | May 14 12:41:57 PM PDT 24 |
| Peak memory | 181868 kb |
| Host | smart-043f05ba-62df-4baf-9fcc-3e95e08fe2ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940490542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2940490542 |
| Directory | /workspace/6.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1709384295 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 50123075 ps |
| CPU time | 0.57 seconds |
| Started | May 14 12:41:41 PM PDT 24 |
| Finished | May 14 12:41:44 PM PDT 24 |
| Peak memory | 191248 kb |
| Host | smart-47f9d97c-7f0d-46d4-b575-a0923ff9c2cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709384295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.1709384295 |
| Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3646408982 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 53727825 ps |
| CPU time | 2.52 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:41:54 PM PDT 24 |
| Peak memory | 197440 kb |
| Host | smart-98137ec4-2161-42c9-adbf-31f5a31f1a69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646408982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3646408982 |
| Directory | /workspace/6.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2104709456 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 113767681 ps |
| CPU time | 1.37 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:40 PM PDT 24 |
| Peak memory | 195116 kb |
| Host | smart-7b8c898e-9cf2-4ce7-b385-9007eb4195c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104709456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.2104709456 |
| Directory | /workspace/6.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3851581481 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 51766782 ps |
| CPU time | 0.7 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:42:08 PM PDT 24 |
| Peak memory | 194480 kb |
| Host | smart-06254263-6393-4aef-9404-fdec8534d3b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851581481 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3851581481 |
| Directory | /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4136418147 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 14944965 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:41:40 PM PDT 24 |
| Finished | May 14 12:41:44 PM PDT 24 |
| Peak memory | 182556 kb |
| Host | smart-dd6546a5-bf5b-4c5c-b2f3-ca95db3b8ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136418147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.4136418147 |
| Directory | /workspace/7.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3056608621 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 169739527 ps |
| CPU time | 0.58 seconds |
| Started | May 14 12:41:42 PM PDT 24 |
| Finished | May 14 12:41:45 PM PDT 24 |
| Peak memory | 182556 kb |
| Host | smart-9b1dcdf4-d052-4802-b022-92b8c96d7f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056608621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3056608621 |
| Directory | /workspace/7.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.814066007 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 37804002 ps |
| CPU time | 0.86 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:51 PM PDT 24 |
| Peak memory | 193336 kb |
| Host | smart-ebcd54ba-dcdd-4044-9803-71d897ff8518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814066007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim er_same_csr_outstanding.814066007 |
| Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3519752266 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 543768592 ps |
| CPU time | 1.61 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:41:51 PM PDT 24 |
| Peak memory | 197452 kb |
| Host | smart-a26c0529-26c7-4166-8853-fefffabcb884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519752266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3519752266 |
| Directory | /workspace/7.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4240569765 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 121144033 ps |
| CPU time | 1.39 seconds |
| Started | May 14 12:41:51 PM PDT 24 |
| Finished | May 14 12:41:55 PM PDT 24 |
| Peak memory | 194408 kb |
| Host | smart-84a54189-3bf9-4d65-9336-b712345dfee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240569765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in tg_err.4240569765 |
| Directory | /workspace/7.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1599170165 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 22954044 ps |
| CPU time | 0.61 seconds |
| Started | May 14 12:41:39 PM PDT 24 |
| Finished | May 14 12:41:42 PM PDT 24 |
| Peak memory | 193472 kb |
| Host | smart-d77cbc9a-386a-4f1e-8c4d-873fbf096685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599170165 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1599170165 |
| Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1950007946 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 14536349 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:50 PM PDT 24 |
| Finished | May 14 12:41:53 PM PDT 24 |
| Peak memory | 182560 kb |
| Host | smart-34f643fa-c330-4e4d-8e9a-b09caa82d789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950007946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1950007946 |
| Directory | /workspace/8.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.173814504 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 53691494 ps |
| CPU time | 0.52 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:52 PM PDT 24 |
| Peak memory | 181976 kb |
| Host | smart-50635735-2fd2-4f0a-a9ae-7847124cb5c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173814504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.173814504 |
| Directory | /workspace/8.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1133579129 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 21259456 ps |
| CPU time | 0.65 seconds |
| Started | May 14 12:41:59 PM PDT 24 |
| Finished | May 14 12:42:01 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-35a9aba2-a541-4cbf-940c-05e32380cce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133579129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti mer_same_csr_outstanding.1133579129 |
| Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3399401952 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 972738991 ps |
| CPU time | 1.62 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:40 PM PDT 24 |
| Peak memory | 197392 kb |
| Host | smart-f2784bc4-b3a7-447c-8fcb-02c0b0561153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399401952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3399401952 |
| Directory | /workspace/8.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3073095314 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 191951869 ps |
| CPU time | 1.01 seconds |
| Started | May 14 12:41:43 PM PDT 24 |
| Finished | May 14 12:41:47 PM PDT 24 |
| Peak memory | 193512 kb |
| Host | smart-012feaba-b689-4d4b-80aa-3b9e5d75e1ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073095314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in tg_err.3073095314 |
| Directory | /workspace/8.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1393673259 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 126414895 ps |
| CPU time | 1.4 seconds |
| Started | May 14 12:41:39 PM PDT 24 |
| Finished | May 14 12:41:43 PM PDT 24 |
| Peak memory | 197424 kb |
| Host | smart-0b6f2d79-7456-4eed-a75f-2f049f18033a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393673259 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1393673259 |
| Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.456437500 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 35096501 ps |
| CPU time | 0.6 seconds |
| Started | May 14 12:41:42 PM PDT 24 |
| Finished | May 14 12:41:50 PM PDT 24 |
| Peak memory | 182672 kb |
| Host | smart-498631a0-fae8-428e-b71e-f58d83528339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456437500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.456437500 |
| Directory | /workspace/9.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2811002741 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 40306085 ps |
| CPU time | 0.54 seconds |
| Started | May 14 12:41:38 PM PDT 24 |
| Finished | May 14 12:41:41 PM PDT 24 |
| Peak memory | 182412 kb |
| Host | smart-451c01ca-46c8-48d6-80c3-261072a209b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811002741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2811002741 |
| Directory | /workspace/9.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.184233539 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 150894871 ps |
| CPU time | 0.61 seconds |
| Started | May 14 12:41:40 PM PDT 24 |
| Finished | May 14 12:41:43 PM PDT 24 |
| Peak memory | 191804 kb |
| Host | smart-bcdd1c96-ff08-4d47-bb91-e1eb667d32d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184233539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim er_same_csr_outstanding.184233539 |
| Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2811930546 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 415108718 ps |
| CPU time | 1.47 seconds |
| Started | May 14 12:41:33 PM PDT 24 |
| Finished | May 14 12:41:36 PM PDT 24 |
| Peak memory | 197424 kb |
| Host | smart-805c9bf8-cc13-47b8-9bc1-603a0fa44752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811930546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2811930546 |
| Directory | /workspace/9.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3684978279 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 146688453 ps |
| CPU time | 1.3 seconds |
| Started | May 14 12:41:36 PM PDT 24 |
| Finished | May 14 12:41:40 PM PDT 24 |
| Peak memory | 194240 kb |
| Host | smart-730cfade-4638-44b4-af2d-4606da01f7cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684978279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.3684978279 |
| Directory | /workspace/9.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.558505830 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 40767975234 ps |
| CPU time | 36.21 seconds |
| Started | May 14 12:41:53 PM PDT 24 |
| Finished | May 14 12:42:33 PM PDT 24 |
| Peak memory | 182464 kb |
| Host | smart-b8d60e3e-a6b3-403c-ab83-4ffa61df9bd4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558505830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rv_timer_cfg_update_on_fly.558505830 |
| Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/0.rv_timer_disabled.3571883663 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 222689327413 ps |
| CPU time | 89.83 seconds |
| Started | May 14 12:41:54 PM PDT 24 |
| Finished | May 14 12:43:27 PM PDT 24 |
| Peak memory | 182408 kb |
| Host | smart-8394da97-63f4-4b2c-abca-162c2c8c7a7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3571883663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3571883663 |
| Directory | /workspace/0.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random.3382491863 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 184472696848 ps |
| CPU time | 281 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:46:46 PM PDT 24 |
| Peak memory | 190792 kb |
| Host | smart-f58ed2a2-4ccf-4d80-93fc-a81523e957d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382491863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3382491863 |
| Directory | /workspace/0.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random_reset.3072355380 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 9520723258 ps |
| CPU time | 14.94 seconds |
| Started | May 14 12:41:47 PM PDT 24 |
| Finished | May 14 12:42:04 PM PDT 24 |
| Peak memory | 182472 kb |
| Host | smart-9344895f-63fd-4a01-8e18-e539aea1e1b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072355380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3072355380 |
| Directory | /workspace/0.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_disabled.2797885408 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 43498755134 ps |
| CPU time | 55.9 seconds |
| Started | May 14 12:42:11 PM PDT 24 |
| Finished | May 14 12:43:09 PM PDT 24 |
| Peak memory | 182480 kb |
| Host | smart-9d239e0d-b4c5-4ca9-a101-14d31ed76767 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797885408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2797885408 |
| Directory | /workspace/1.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random.607640532 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 383035366750 ps |
| CPU time | 200.48 seconds |
| Started | May 14 12:41:51 PM PDT 24 |
| Finished | May 14 12:45:15 PM PDT 24 |
| Peak memory | 190632 kb |
| Host | smart-67bd2c08-e1ae-4209-ad37-57709bcdb95c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607640532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.607640532 |
| Directory | /workspace/1.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random_reset.3641137025 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 92564208044 ps |
| CPU time | 73.2 seconds |
| Started | May 14 12:41:58 PM PDT 24 |
| Finished | May 14 12:43:13 PM PDT 24 |
| Peak memory | 193852 kb |
| Host | smart-6092b3f9-db92-49d9-aadf-74095f555bf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641137025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3641137025 |
| Directory | /workspace/1.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_sec_cm.1972904564 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 78691932 ps |
| CPU time | 0.73 seconds |
| Started | May 14 12:41:51 PM PDT 24 |
| Finished | May 14 12:41:54 PM PDT 24 |
| Peak memory | 212852 kb |
| Host | smart-f9b74940-3455-4fba-9389-57d41ce68538 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972904564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1972904564 |
| Directory | /workspace/1.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all.4068564402 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 132563024506 ps |
| CPU time | 170.34 seconds |
| Started | May 14 12:42:06 PM PDT 24 |
| Finished | May 14 12:44:59 PM PDT 24 |
| Peak memory | 182544 kb |
| Host | smart-85b19a51-2e4c-4fc8-b23c-b3c64d3e88d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068564402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 4068564402 |
| Directory | /workspace/1.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2872522615 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 174794232344 ps |
| CPU time | 279.05 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:46:42 PM PDT 24 |
| Peak memory | 182460 kb |
| Host | smart-64c32598-a9fb-44f2-a5b0-e16049858bcf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872522615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.2872522615 |
| Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_disabled.3491324083 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 373783053180 ps |
| CPU time | 292.15 seconds |
| Started | May 14 12:42:06 PM PDT 24 |
| Finished | May 14 12:47:02 PM PDT 24 |
| Peak memory | 182432 kb |
| Host | smart-74854269-8951-4bd9-b2fd-66f56475dd86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491324083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3491324083 |
| Directory | /workspace/10.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random_reset.3299251324 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 109651125247 ps |
| CPU time | 227.3 seconds |
| Started | May 14 12:41:52 PM PDT 24 |
| Finished | May 14 12:45:42 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-b1055ed4-7177-472a-9066-cdd73ce7a414 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299251324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3299251324 |
| Directory | /workspace/10.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all.3620871634 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 544965596474 ps |
| CPU time | 132.34 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:44:22 PM PDT 24 |
| Peak memory | 182488 kb |
| Host | smart-0cff864d-df73-47d9-b7c9-8617410f7c35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620871634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all .3620871634 |
| Directory | /workspace/10.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/100.rv_timer_random.2718378016 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 194159591813 ps |
| CPU time | 106.31 seconds |
| Started | May 14 12:42:34 PM PDT 24 |
| Finished | May 14 12:44:22 PM PDT 24 |
| Peak memory | 190664 kb |
| Host | smart-64962874-96a0-4b38-8999-98b577d1ecde |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718378016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2718378016 |
| Directory | /workspace/100.rv_timer_random/latest |
| Test location | /workspace/coverage/default/101.rv_timer_random.1393946211 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2074221322434 ps |
| CPU time | 875.12 seconds |
| Started | May 14 12:42:39 PM PDT 24 |
| Finished | May 14 12:57:17 PM PDT 24 |
| Peak memory | 190680 kb |
| Host | smart-c9b4e6f6-dc44-4054-8d05-064d2fc9b3bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393946211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1393946211 |
| Directory | /workspace/101.rv_timer_random/latest |
| Test location | /workspace/coverage/default/102.rv_timer_random.3199344446 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 45857167915 ps |
| CPU time | 504.88 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:51:18 PM PDT 24 |
| Peak memory | 182444 kb |
| Host | smart-cc3528cc-df8f-470d-a370-b89bda8b4beb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199344446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3199344446 |
| Directory | /workspace/102.rv_timer_random/latest |
| Test location | /workspace/coverage/default/103.rv_timer_random.937376511 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 83355753240 ps |
| CPU time | 462 seconds |
| Started | May 14 12:42:35 PM PDT 24 |
| Finished | May 14 12:50:18 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-1c4a3d83-4ed7-47f7-bb95-eff1149f7344 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937376511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.937376511 |
| Directory | /workspace/103.rv_timer_random/latest |
| Test location | /workspace/coverage/default/104.rv_timer_random.3028597714 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 278562462638 ps |
| CPU time | 222.85 seconds |
| Started | May 14 12:42:43 PM PDT 24 |
| Finished | May 14 12:46:30 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-1b58fc7a-32d1-49d0-af92-54fce92f49ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028597714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3028597714 |
| Directory | /workspace/104.rv_timer_random/latest |
| Test location | /workspace/coverage/default/108.rv_timer_random.1570835118 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 51333463240 ps |
| CPU time | 85.55 seconds |
| Started | May 14 12:42:41 PM PDT 24 |
| Finished | May 14 12:44:11 PM PDT 24 |
| Peak memory | 182332 kb |
| Host | smart-a203f7f0-02cd-4e23-9ba2-c1e81eb526f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570835118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1570835118 |
| Directory | /workspace/108.rv_timer_random/latest |
| Test location | /workspace/coverage/default/109.rv_timer_random.886635006 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 77625043645 ps |
| CPU time | 96.36 seconds |
| Started | May 14 12:42:36 PM PDT 24 |
| Finished | May 14 12:44:14 PM PDT 24 |
| Peak memory | 191372 kb |
| Host | smart-fb228550-f4b0-4bde-a723-2016be0eea1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886635006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.886635006 |
| Directory | /workspace/109.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_disabled.1607171677 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 438027409206 ps |
| CPU time | 182.71 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 12:45:10 PM PDT 24 |
| Peak memory | 182568 kb |
| Host | smart-cbd9dad8-5742-43ff-ad24-2122900470fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607171677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1607171677 |
| Directory | /workspace/11.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random_reset.4111261929 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1975965798 ps |
| CPU time | 1.15 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:42:07 PM PDT 24 |
| Peak memory | 192216 kb |
| Host | smart-c9029c6e-b2c7-49a8-a819-208f1468ce3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111261929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4111261929 |
| Directory | /workspace/11.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/111.rv_timer_random.44811907 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 742612030874 ps |
| CPU time | 221.68 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:46:16 PM PDT 24 |
| Peak memory | 190640 kb |
| Host | smart-3277583f-93f1-44f4-9b54-863b4a9250ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44811907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.44811907 |
| Directory | /workspace/111.rv_timer_random/latest |
| Test location | /workspace/coverage/default/112.rv_timer_random.2646870078 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 26711867630 ps |
| CPU time | 28.84 seconds |
| Started | May 14 12:42:39 PM PDT 24 |
| Finished | May 14 12:43:11 PM PDT 24 |
| Peak memory | 182472 kb |
| Host | smart-a3d495d1-ef51-40d3-8278-08a7845145ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646870078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2646870078 |
| Directory | /workspace/112.rv_timer_random/latest |
| Test location | /workspace/coverage/default/113.rv_timer_random.1147978928 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 63707141308 ps |
| CPU time | 63.86 seconds |
| Started | May 14 12:42:55 PM PDT 24 |
| Finished | May 14 12:44:01 PM PDT 24 |
| Peak memory | 182292 kb |
| Host | smart-bff99f59-cfbf-4ceb-bc1b-a1d3ee3fe6a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147978928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1147978928 |
| Directory | /workspace/113.rv_timer_random/latest |
| Test location | /workspace/coverage/default/115.rv_timer_random.1001059769 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 28237581786 ps |
| CPU time | 80.18 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:43:55 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-3e65b096-da92-4158-8a39-a5804e1b266d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001059769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1001059769 |
| Directory | /workspace/115.rv_timer_random/latest |
| Test location | /workspace/coverage/default/118.rv_timer_random.1234520193 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 355265689945 ps |
| CPU time | 191.88 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 12:45:50 PM PDT 24 |
| Peak memory | 190680 kb |
| Host | smart-ce139b20-8a6d-4dc4-b826-574ba307243f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234520193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1234520193 |
| Directory | /workspace/118.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.145076870 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1469980783 ps |
| CPU time | 1.79 seconds |
| Started | May 14 12:42:10 PM PDT 24 |
| Finished | May 14 12:42:14 PM PDT 24 |
| Peak memory | 182256 kb |
| Host | smart-1ce8b464-f1b5-40a7-a3ed-d65587e5b897 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145076870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.rv_timer_cfg_update_on_fly.145076870 |
| Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/12.rv_timer_disabled.229051237 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 91638398745 ps |
| CPU time | 123.83 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 12:44:11 PM PDT 24 |
| Peak memory | 182452 kb |
| Host | smart-70db20cf-64a0-4fc6-a27e-0eee173883eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229051237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.229051237 |
| Directory | /workspace/12.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random.3550291747 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 30676769677 ps |
| CPU time | 55.12 seconds |
| Started | May 14 12:42:10 PM PDT 24 |
| Finished | May 14 12:43:08 PM PDT 24 |
| Peak memory | 182468 kb |
| Host | smart-b1ab40a8-64d1-410d-8e23-fc99d11c6563 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550291747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3550291747 |
| Directory | /workspace/12.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random_reset.2640310807 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1673187838 ps |
| CPU time | 2.8 seconds |
| Started | May 14 12:42:07 PM PDT 24 |
| Finished | May 14 12:42:13 PM PDT 24 |
| Peak memory | 191364 kb |
| Host | smart-b6f485bf-8afe-4539-adc7-834a95703344 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640310807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2640310807 |
| Directory | /workspace/12.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/120.rv_timer_random.4145405115 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 901738081236 ps |
| CPU time | 457.42 seconds |
| Started | May 14 12:42:51 PM PDT 24 |
| Finished | May 14 12:50:33 PM PDT 24 |
| Peak memory | 190644 kb |
| Host | smart-9cbb760a-b296-4561-afd7-168b76b485d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145405115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.4145405115 |
| Directory | /workspace/120.rv_timer_random/latest |
| Test location | /workspace/coverage/default/121.rv_timer_random.923806622 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 121256307480 ps |
| CPU time | 93.96 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:44:27 PM PDT 24 |
| Peak memory | 190704 kb |
| Host | smart-3bf7a835-9a82-4389-80c2-44b7629c2d6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923806622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.923806622 |
| Directory | /workspace/121.rv_timer_random/latest |
| Test location | /workspace/coverage/default/122.rv_timer_random.371967769 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 95495401782 ps |
| CPU time | 317.09 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:48:04 PM PDT 24 |
| Peak memory | 194936 kb |
| Host | smart-d45e486a-1299-45c8-b239-d7b1080101b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371967769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.371967769 |
| Directory | /workspace/122.rv_timer_random/latest |
| Test location | /workspace/coverage/default/124.rv_timer_random.2610520924 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 71075099013 ps |
| CPU time | 535.29 seconds |
| Started | May 14 12:42:59 PM PDT 24 |
| Finished | May 14 12:51:58 PM PDT 24 |
| Peak memory | 182548 kb |
| Host | smart-b1a73866-9635-40d3-91fc-9fc430c96055 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610520924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2610520924 |
| Directory | /workspace/124.rv_timer_random/latest |
| Test location | /workspace/coverage/default/125.rv_timer_random.3397066730 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 19748692599 ps |
| CPU time | 81.83 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:44:09 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-ae9cfc68-e4b8-4cc2-95a0-9f75f6a10220 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397066730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3397066730 |
| Directory | /workspace/125.rv_timer_random/latest |
| Test location | /workspace/coverage/default/126.rv_timer_random.1881443577 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 250491372877 ps |
| CPU time | 130.91 seconds |
| Started | May 14 12:42:59 PM PDT 24 |
| Finished | May 14 12:45:14 PM PDT 24 |
| Peak memory | 190700 kb |
| Host | smart-0f6a7c53-404d-4aa1-bea5-2bf38f45accb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881443577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1881443577 |
| Directory | /workspace/126.rv_timer_random/latest |
| Test location | /workspace/coverage/default/128.rv_timer_random.560448640 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 40003192707 ps |
| CPU time | 282.75 seconds |
| Started | May 14 12:42:58 PM PDT 24 |
| Finished | May 14 12:47:43 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-945e9f75-4df1-4f7c-8290-89f1192e82ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560448640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.560448640 |
| Directory | /workspace/128.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1959960395 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 20276720643 ps |
| CPU time | 31.66 seconds |
| Started | May 14 12:42:27 PM PDT 24 |
| Finished | May 14 12:43:00 PM PDT 24 |
| Peak memory | 182436 kb |
| Host | smart-aaac1d36-3703-48c2-8e85-b071903598f6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959960395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.1959960395 |
| Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/13.rv_timer_disabled.599932713 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 440271137540 ps |
| CPU time | 185.45 seconds |
| Started | May 14 12:41:51 PM PDT 24 |
| Finished | May 14 12:45:00 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-527c91c6-6f53-4c84-84f4-65f27e633e8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599932713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.599932713 |
| Directory | /workspace/13.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random.2838922367 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 149186931 ps |
| CPU time | 0.79 seconds |
| Started | May 14 12:42:26 PM PDT 24 |
| Finished | May 14 12:42:28 PM PDT 24 |
| Peak memory | 182276 kb |
| Host | smart-3c80d224-113e-4680-8a7e-3c763992fa9f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838922367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2838922367 |
| Directory | /workspace/13.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random_reset.1103799997 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 170227598815 ps |
| CPU time | 117.36 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 12:44:09 PM PDT 24 |
| Peak memory | 190672 kb |
| Host | smart-15cef9dd-5c94-46b9-a293-2bc878357354 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103799997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1103799997 |
| Directory | /workspace/13.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/130.rv_timer_random.1871665020 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 286521453602 ps |
| CPU time | 288.54 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:47:34 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-754557f7-cefa-4d8f-addd-bb5d1e690fce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871665020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1871665020 |
| Directory | /workspace/130.rv_timer_random/latest |
| Test location | /workspace/coverage/default/131.rv_timer_random.398965432 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 32376545603 ps |
| CPU time | 32.82 seconds |
| Started | May 14 12:42:43 PM PDT 24 |
| Finished | May 14 12:43:21 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-f6c8babc-2aee-40ad-ab56-d43e1ed5cac8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398965432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.398965432 |
| Directory | /workspace/131.rv_timer_random/latest |
| Test location | /workspace/coverage/default/132.rv_timer_random.3598267221 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 99828290941 ps |
| CPU time | 417.41 seconds |
| Started | May 14 12:42:54 PM PDT 24 |
| Finished | May 14 12:49:54 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-a2a176d8-8444-4eea-b3e2-de640ff4fc9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598267221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3598267221 |
| Directory | /workspace/132.rv_timer_random/latest |
| Test location | /workspace/coverage/default/135.rv_timer_random.3219189057 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 12754364477 ps |
| CPU time | 6.09 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:42:52 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-3d005105-06b6-4f71-aca4-5ac88ff22c29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219189057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3219189057 |
| Directory | /workspace/135.rv_timer_random/latest |
| Test location | /workspace/coverage/default/137.rv_timer_random.2210098604 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 396434310757 ps |
| CPU time | 244.52 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:46:57 PM PDT 24 |
| Peak memory | 190640 kb |
| Host | smart-c88df469-b046-48d1-b6c7-a301a00fbb74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210098604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2210098604 |
| Directory | /workspace/137.rv_timer_random/latest |
| Test location | /workspace/coverage/default/138.rv_timer_random.497368076 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 544692771967 ps |
| CPU time | 553.98 seconds |
| Started | May 14 12:42:49 PM PDT 24 |
| Finished | May 14 12:52:08 PM PDT 24 |
| Peak memory | 190652 kb |
| Host | smart-c504fe2c-5a42-4dee-9cf0-40e5a51d9faa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497368076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.497368076 |
| Directory | /workspace/138.rv_timer_random/latest |
| Test location | /workspace/coverage/default/139.rv_timer_random.147786045 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 297080219076 ps |
| CPU time | 473.89 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:50:40 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-0e276f2c-6d81-477e-88d0-895274480ea4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147786045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.147786045 |
| Directory | /workspace/139.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3119837581 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 251593990273 ps |
| CPU time | 153.44 seconds |
| Started | May 14 12:42:06 PM PDT 24 |
| Finished | May 14 12:44:43 PM PDT 24 |
| Peak memory | 182624 kb |
| Host | smart-add49a67-256d-4d22-96e1-873327a8b655 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119837581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.3119837581 |
| Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/14.rv_timer_disabled.3107932872 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 57042565285 ps |
| CPU time | 86.96 seconds |
| Started | May 14 12:42:18 PM PDT 24 |
| Finished | May 14 12:43:46 PM PDT 24 |
| Peak memory | 182616 kb |
| Host | smart-518c6b3c-1354-4bd9-8758-4f9d9203be8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107932872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3107932872 |
| Directory | /workspace/14.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random_reset.2597887526 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 383003017 ps |
| CPU time | 3.7 seconds |
| Started | May 14 12:42:00 PM PDT 24 |
| Finished | May 14 12:42:05 PM PDT 24 |
| Peak memory | 190524 kb |
| Host | smart-29a38f71-8beb-4731-83eb-65590789af81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597887526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2597887526 |
| Directory | /workspace/14.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all.297880354 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 600574051733 ps |
| CPU time | 446.87 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:49:35 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-328881b5-9be3-4a0a-86b7-69836ba68d1d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297880354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all. 297880354 |
| Directory | /workspace/14.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/142.rv_timer_random.647511321 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 115408839463 ps |
| CPU time | 1890.33 seconds |
| Started | May 14 12:42:41 PM PDT 24 |
| Finished | May 14 01:14:15 PM PDT 24 |
| Peak memory | 190628 kb |
| Host | smart-6d3d312f-ccf5-4668-a45a-38932f272259 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647511321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.647511321 |
| Directory | /workspace/142.rv_timer_random/latest |
| Test location | /workspace/coverage/default/143.rv_timer_random.3435310334 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 92751553298 ps |
| CPU time | 156.75 seconds |
| Started | May 14 12:42:52 PM PDT 24 |
| Finished | May 14 12:45:32 PM PDT 24 |
| Peak memory | 190632 kb |
| Host | smart-ed27931d-2b52-4620-a831-842cdcef7603 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435310334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3435310334 |
| Directory | /workspace/143.rv_timer_random/latest |
| Test location | /workspace/coverage/default/144.rv_timer_random.1035736321 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 57992538830 ps |
| CPU time | 30.86 seconds |
| Started | May 14 12:42:47 PM PDT 24 |
| Finished | May 14 12:43:23 PM PDT 24 |
| Peak memory | 182484 kb |
| Host | smart-ecb90ea2-160d-42fb-babd-1c03d3aac944 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035736321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1035736321 |
| Directory | /workspace/144.rv_timer_random/latest |
| Test location | /workspace/coverage/default/147.rv_timer_random.723578224 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 81729193136 ps |
| CPU time | 368.31 seconds |
| Started | May 14 12:42:58 PM PDT 24 |
| Finished | May 14 12:49:10 PM PDT 24 |
| Peak memory | 190620 kb |
| Host | smart-83ce7e8d-8c3f-4939-9eba-dc35f80453ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723578224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.723578224 |
| Directory | /workspace/147.rv_timer_random/latest |
| Test location | /workspace/coverage/default/148.rv_timer_random.3845953379 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 77414599068 ps |
| CPU time | 119.26 seconds |
| Started | May 14 12:42:52 PM PDT 24 |
| Finished | May 14 12:44:55 PM PDT 24 |
| Peak memory | 190652 kb |
| Host | smart-d7045bd6-f379-4b77-9429-fd9f70924a7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845953379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3845953379 |
| Directory | /workspace/148.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1215111753 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3143856654 ps |
| CPU time | 5.05 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:41:57 PM PDT 24 |
| Peak memory | 182456 kb |
| Host | smart-b70bb631-49ac-43ce-860e-e3a90f538777 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215111753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1215111753 |
| Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/15.rv_timer_disabled.3567741700 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 78528789591 ps |
| CPU time | 127.6 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:44:12 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-0cedfe5e-3a9e-4456-940b-7a33fda055c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567741700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3567741700 |
| Directory | /workspace/15.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random.3562855947 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 111205378725 ps |
| CPU time | 251.91 seconds |
| Started | May 14 12:42:15 PM PDT 24 |
| Finished | May 14 12:46:28 PM PDT 24 |
| Peak memory | 190788 kb |
| Host | smart-b05f8ea9-ef75-461b-b701-4ee29983b622 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562855947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3562855947 |
| Directory | /workspace/15.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random_reset.500315663 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 84889973999 ps |
| CPU time | 86.38 seconds |
| Started | May 14 12:42:12 PM PDT 24 |
| Finished | May 14 12:43:40 PM PDT 24 |
| Peak memory | 182412 kb |
| Host | smart-b02646d2-fd20-4774-b73a-8a3c86698da1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500315663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.500315663 |
| Directory | /workspace/15.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.1800382987 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 27761476033 ps |
| CPU time | 227.19 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:46:22 PM PDT 24 |
| Peak memory | 205188 kb |
| Host | smart-7abe1cf6-4a34-4572-b9d0-642b1a1bfb0e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800382987 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.1800382987 |
| Directory | /workspace/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/150.rv_timer_random.2297416218 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 62643720634 ps |
| CPU time | 117.54 seconds |
| Started | May 14 12:42:40 PM PDT 24 |
| Finished | May 14 12:44:41 PM PDT 24 |
| Peak memory | 182444 kb |
| Host | smart-00c39d6f-207f-4d82-850f-ca7093de93c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297416218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2297416218 |
| Directory | /workspace/150.rv_timer_random/latest |
| Test location | /workspace/coverage/default/152.rv_timer_random.1616900211 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 351921008401 ps |
| CPU time | 134.25 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:44:56 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-2b979cba-dea0-4f13-9863-73dd9fdaf0a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616900211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1616900211 |
| Directory | /workspace/152.rv_timer_random/latest |
| Test location | /workspace/coverage/default/153.rv_timer_random.3291699736 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 345957504196 ps |
| CPU time | 1026.27 seconds |
| Started | May 14 12:42:39 PM PDT 24 |
| Finished | May 14 12:59:49 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-399791b2-9941-4e8b-9717-c6f392c09a00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291699736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3291699736 |
| Directory | /workspace/153.rv_timer_random/latest |
| Test location | /workspace/coverage/default/155.rv_timer_random.2811486047 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 82042575282 ps |
| CPU time | 131.6 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:45:04 PM PDT 24 |
| Peak memory | 190652 kb |
| Host | smart-7d4e3cfb-7f69-48a3-8b40-9cdb531952f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811486047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2811486047 |
| Directory | /workspace/155.rv_timer_random/latest |
| Test location | /workspace/coverage/default/156.rv_timer_random.3197171042 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 108877041540 ps |
| CPU time | 78.13 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:44:11 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-8de64828-22af-4c4c-9f8d-606d8f279e4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197171042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3197171042 |
| Directory | /workspace/156.rv_timer_random/latest |
| Test location | /workspace/coverage/default/157.rv_timer_random.374046907 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 106021842144 ps |
| CPU time | 238.66 seconds |
| Started | May 14 12:42:58 PM PDT 24 |
| Finished | May 14 12:47:00 PM PDT 24 |
| Peak memory | 190700 kb |
| Host | smart-751f044b-1fea-408d-96fa-6a8cb7da1f2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374046907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.374046907 |
| Directory | /workspace/157.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3496300338 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 33517237681 ps |
| CPU time | 59.94 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 12:43:13 PM PDT 24 |
| Peak memory | 182484 kb |
| Host | smart-f7a5b6fe-006f-4314-88a8-9dca02051d4f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496300338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.3496300338 |
| Directory | /workspace/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/16.rv_timer_disabled.1399995868 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 227619233533 ps |
| CPU time | 72.09 seconds |
| Started | May 14 12:42:10 PM PDT 24 |
| Finished | May 14 12:43:25 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-31eacc20-2c16-46ed-9ee6-a6c00db40e05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399995868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1399995868 |
| Directory | /workspace/16.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random.4207224649 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 142146750336 ps |
| CPU time | 1396.23 seconds |
| Started | May 14 12:42:06 PM PDT 24 |
| Finished | May 14 01:05:25 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-cfd26a9e-1c77-4148-a7fe-24360da7d9a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207224649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4207224649 |
| Directory | /workspace/16.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random_reset.2490372742 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 375923007 ps |
| CPU time | 0.69 seconds |
| Started | May 14 12:42:11 PM PDT 24 |
| Finished | May 14 12:42:14 PM PDT 24 |
| Peak memory | 182244 kb |
| Host | smart-20de1960-eed2-49f9-abf6-e1bf201fb8c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490372742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2490372742 |
| Directory | /workspace/16.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2100584863 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 15112971892 ps |
| CPU time | 168.96 seconds |
| Started | May 14 12:41:54 PM PDT 24 |
| Finished | May 14 12:44:46 PM PDT 24 |
| Peak memory | 197264 kb |
| Host | smart-fd2cf757-a41b-4d8c-a2c5-a31953e63943 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100584863 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2100584863 |
| Directory | /workspace/16.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/161.rv_timer_random.3276915326 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 88056906369 ps |
| CPU time | 118.77 seconds |
| Started | May 14 12:42:51 PM PDT 24 |
| Finished | May 14 12:44:54 PM PDT 24 |
| Peak memory | 194228 kb |
| Host | smart-92e87316-ab2c-4554-8f70-ff9877a20079 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276915326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3276915326 |
| Directory | /workspace/161.rv_timer_random/latest |
| Test location | /workspace/coverage/default/162.rv_timer_random.1465988966 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 456415559801 ps |
| CPU time | 234.82 seconds |
| Started | May 14 12:42:45 PM PDT 24 |
| Finished | May 14 12:46:45 PM PDT 24 |
| Peak memory | 190824 kb |
| Host | smart-8fec6686-3ae1-4ea0-a2a5-5ee440d62084 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465988966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1465988966 |
| Directory | /workspace/162.rv_timer_random/latest |
| Test location | /workspace/coverage/default/163.rv_timer_random.649691516 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 117270910363 ps |
| CPU time | 65.77 seconds |
| Started | May 14 12:42:58 PM PDT 24 |
| Finished | May 14 12:44:08 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-ff6003ae-51d3-416c-b652-30c8c238e426 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649691516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.649691516 |
| Directory | /workspace/163.rv_timer_random/latest |
| Test location | /workspace/coverage/default/164.rv_timer_random.439832116 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 662353410017 ps |
| CPU time | 453.54 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:50:27 PM PDT 24 |
| Peak memory | 190700 kb |
| Host | smart-8a37abba-e370-404b-a70c-f91fd3c1a4ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439832116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.439832116 |
| Directory | /workspace/164.rv_timer_random/latest |
| Test location | /workspace/coverage/default/165.rv_timer_random.912766222 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 281483764103 ps |
| CPU time | 267.43 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:47:13 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-00acbdb3-7fd8-4467-815a-9fc8284e5500 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912766222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.912766222 |
| Directory | /workspace/165.rv_timer_random/latest |
| Test location | /workspace/coverage/default/166.rv_timer_random.4209503761 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 111085665487 ps |
| CPU time | 419.18 seconds |
| Started | May 14 12:42:51 PM PDT 24 |
| Finished | May 14 12:49:54 PM PDT 24 |
| Peak memory | 190816 kb |
| Host | smart-8acda8d5-f7b1-4182-8d50-05dc7c2f5b38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209503761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4209503761 |
| Directory | /workspace/166.rv_timer_random/latest |
| Test location | /workspace/coverage/default/167.rv_timer_random.267450883 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 113160127980 ps |
| CPU time | 463.01 seconds |
| Started | May 14 12:42:36 PM PDT 24 |
| Finished | May 14 12:50:20 PM PDT 24 |
| Peak memory | 190828 kb |
| Host | smart-ea9fe81a-9486-41b7-8c0c-211563ceb103 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267450883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.267450883 |
| Directory | /workspace/167.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3681364939 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 24921751470 ps |
| CPU time | 39.86 seconds |
| Started | May 14 12:42:13 PM PDT 24 |
| Finished | May 14 12:42:54 PM PDT 24 |
| Peak memory | 182556 kb |
| Host | smart-1dc3deb3-9ab6-401f-adc5-18833a7c4dcb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681364939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.3681364939 |
| Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/17.rv_timer_disabled.3746424858 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 197334779000 ps |
| CPU time | 230.42 seconds |
| Started | May 14 12:42:07 PM PDT 24 |
| Finished | May 14 12:46:01 PM PDT 24 |
| Peak memory | 182468 kb |
| Host | smart-d5d3bc7a-8a42-4a3f-a157-c49d79ce1d06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746424858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3746424858 |
| Directory | /workspace/17.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random.752312068 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 22336836892 ps |
| CPU time | 31.24 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:42:52 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-1d4502e2-c2af-4e98-a033-ebb3f1b9a87b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752312068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.752312068 |
| Directory | /workspace/17.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all.1011173871 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 219228520034 ps |
| CPU time | 189.68 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 12:45:22 PM PDT 24 |
| Peak memory | 182624 kb |
| Host | smart-2b8dd4c3-977a-4156-8588-c39dd567cc5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011173871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all .1011173871 |
| Directory | /workspace/17.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/171.rv_timer_random.1354909483 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 71351451044 ps |
| CPU time | 138.14 seconds |
| Started | May 14 12:42:57 PM PDT 24 |
| Finished | May 14 12:45:17 PM PDT 24 |
| Peak memory | 194124 kb |
| Host | smart-05ab876e-715b-4aad-b262-74286c6852d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354909483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1354909483 |
| Directory | /workspace/171.rv_timer_random/latest |
| Test location | /workspace/coverage/default/173.rv_timer_random.2285663406 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 86609484656 ps |
| CPU time | 75.34 seconds |
| Started | May 14 12:42:55 PM PDT 24 |
| Finished | May 14 12:44:13 PM PDT 24 |
| Peak memory | 190812 kb |
| Host | smart-0e122314-a12b-43fd-9a49-c0c2d82389dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285663406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2285663406 |
| Directory | /workspace/173.rv_timer_random/latest |
| Test location | /workspace/coverage/default/174.rv_timer_random.11626759 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 35244328134 ps |
| CPU time | 23.23 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:43:03 PM PDT 24 |
| Peak memory | 182236 kb |
| Host | smart-7aa21d2e-35cf-4b08-989f-9052ff72ab85 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11626759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.11626759 |
| Directory | /workspace/174.rv_timer_random/latest |
| Test location | /workspace/coverage/default/175.rv_timer_random.435301733 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 851886837553 ps |
| CPU time | 344.3 seconds |
| Started | May 14 12:42:51 PM PDT 24 |
| Finished | May 14 12:48:39 PM PDT 24 |
| Peak memory | 190672 kb |
| Host | smart-bd09e307-cdad-436d-a9eb-b742605a97a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435301733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.435301733 |
| Directory | /workspace/175.rv_timer_random/latest |
| Test location | /workspace/coverage/default/176.rv_timer_random.376492212 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1753240457622 ps |
| CPU time | 324.87 seconds |
| Started | May 14 12:42:50 PM PDT 24 |
| Finished | May 14 12:48:19 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-181f8433-a4e0-4cd6-9c2d-4a88da5c647c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376492212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.376492212 |
| Directory | /workspace/176.rv_timer_random/latest |
| Test location | /workspace/coverage/default/178.rv_timer_random.537954251 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 338066716705 ps |
| CPU time | 406.59 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:49:28 PM PDT 24 |
| Peak memory | 190664 kb |
| Host | smart-196f5979-c1cd-4fd7-b406-f68c401310ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537954251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.537954251 |
| Directory | /workspace/178.rv_timer_random/latest |
| Test location | /workspace/coverage/default/179.rv_timer_random.1798443718 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 207319900214 ps |
| CPU time | 1439.38 seconds |
| Started | May 14 12:42:58 PM PDT 24 |
| Finished | May 14 01:07:01 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-016c5313-a333-42a5-90c6-5b9ec5f8f69e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798443718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1798443718 |
| Directory | /workspace/179.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_disabled.3451432554 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 141908176897 ps |
| CPU time | 184.01 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:45:13 PM PDT 24 |
| Peak memory | 182460 kb |
| Host | smart-43f0346b-1324-415c-9205-26eb58dc47a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451432554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3451432554 |
| Directory | /workspace/18.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random.2725111065 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 131151034292 ps |
| CPU time | 399.25 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 12:48:46 PM PDT 24 |
| Peak memory | 194116 kb |
| Host | smart-76d720bf-b8fa-4665-b107-bb2134b6e8a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725111065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2725111065 |
| Directory | /workspace/18.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random_reset.2815797876 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 25910378415 ps |
| CPU time | 165.28 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 12:44:52 PM PDT 24 |
| Peak memory | 194220 kb |
| Host | smart-e37a2958-cbd9-4c3d-a3b9-925fdcd1d1a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815797876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2815797876 |
| Directory | /workspace/18.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/181.rv_timer_random.1429695381 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 261170435122 ps |
| CPU time | 677.88 seconds |
| Started | May 14 12:42:52 PM PDT 24 |
| Finished | May 14 12:54:14 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-6aaf60d7-21b7-4f3b-820c-3bdeace6a3d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429695381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1429695381 |
| Directory | /workspace/181.rv_timer_random/latest |
| Test location | /workspace/coverage/default/182.rv_timer_random.4194295178 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 462493401733 ps |
| CPU time | 1186.59 seconds |
| Started | May 14 12:42:56 PM PDT 24 |
| Finished | May 14 01:02:45 PM PDT 24 |
| Peak memory | 190652 kb |
| Host | smart-fa148211-b800-4994-aecf-3b2d96f9fec1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194295178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.4194295178 |
| Directory | /workspace/182.rv_timer_random/latest |
| Test location | /workspace/coverage/default/183.rv_timer_random.1137560895 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 56873913645 ps |
| CPU time | 159.28 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:45:32 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-e61d5939-09a6-47d0-9e97-4b903dbce2af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137560895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1137560895 |
| Directory | /workspace/183.rv_timer_random/latest |
| Test location | /workspace/coverage/default/184.rv_timer_random.855235417 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 27802921250 ps |
| CPU time | 47.31 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:43:28 PM PDT 24 |
| Peak memory | 182320 kb |
| Host | smart-1d8042a1-ac38-44ce-b20d-548e9d0be9be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855235417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.855235417 |
| Directory | /workspace/184.rv_timer_random/latest |
| Test location | /workspace/coverage/default/185.rv_timer_random.3995821695 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 400423433213 ps |
| CPU time | 1777.81 seconds |
| Started | May 14 12:42:59 PM PDT 24 |
| Finished | May 14 01:12:41 PM PDT 24 |
| Peak memory | 190812 kb |
| Host | smart-f469c8bd-1d68-4207-aa87-bd6dc93da136 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995821695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3995821695 |
| Directory | /workspace/185.rv_timer_random/latest |
| Test location | /workspace/coverage/default/186.rv_timer_random.4239366797 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 123558738614 ps |
| CPU time | 371.21 seconds |
| Started | May 14 12:42:59 PM PDT 24 |
| Finished | May 14 12:49:14 PM PDT 24 |
| Peak memory | 190624 kb |
| Host | smart-f5f5fa97-ce4c-4f4b-a630-652c1a286727 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239366797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4239366797 |
| Directory | /workspace/186.rv_timer_random/latest |
| Test location | /workspace/coverage/default/189.rv_timer_random.3280714580 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 76660524843 ps |
| CPU time | 35.47 seconds |
| Started | May 14 12:43:01 PM PDT 24 |
| Finished | May 14 12:43:40 PM PDT 24 |
| Peak memory | 190636 kb |
| Host | smart-b6391746-eea6-41a0-b9cb-754bbcbe6df4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280714580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3280714580 |
| Directory | /workspace/189.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3180246717 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 267620806889 ps |
| CPU time | 151.15 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:44:40 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-fc6c8e63-bca4-46ca-a1f3-65e8cbdff40d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180246717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.3180246717 |
| Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random.323741160 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 208132639251 ps |
| CPU time | 367.85 seconds |
| Started | May 14 12:42:15 PM PDT 24 |
| Finished | May 14 12:48:24 PM PDT 24 |
| Peak memory | 190632 kb |
| Host | smart-553ca4b8-4a6b-4106-9e6a-49045d1debcf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323741160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.323741160 |
| Directory | /workspace/19.rv_timer_random/latest |
| Test location | /workspace/coverage/default/191.rv_timer_random.1626412567 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 307627260959 ps |
| CPU time | 1224.19 seconds |
| Started | May 14 12:42:41 PM PDT 24 |
| Finished | May 14 01:03:09 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-acffe42a-64aa-4130-a7ea-7600ff673e9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626412567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1626412567 |
| Directory | /workspace/191.rv_timer_random/latest |
| Test location | /workspace/coverage/default/193.rv_timer_random.1375184531 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 75277643773 ps |
| CPU time | 106.98 seconds |
| Started | May 14 12:42:59 PM PDT 24 |
| Finished | May 14 12:44:49 PM PDT 24 |
| Peak memory | 190696 kb |
| Host | smart-e3bf20f2-4517-40dc-a40f-da3d2ba23106 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375184531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1375184531 |
| Directory | /workspace/193.rv_timer_random/latest |
| Test location | /workspace/coverage/default/195.rv_timer_random.1506996422 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 60638966227 ps |
| CPU time | 93.43 seconds |
| Started | May 14 12:43:02 PM PDT 24 |
| Finished | May 14 12:44:39 PM PDT 24 |
| Peak memory | 190716 kb |
| Host | smart-43735672-7bb0-42b6-b3ef-5d543f99e50f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506996422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1506996422 |
| Directory | /workspace/195.rv_timer_random/latest |
| Test location | /workspace/coverage/default/196.rv_timer_random.1665528613 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 770236564405 ps |
| CPU time | 1031.66 seconds |
| Started | May 14 12:42:59 PM PDT 24 |
| Finished | May 14 01:00:15 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-ad82b2e0-cda6-4d2c-a150-ccf88578423e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665528613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1665528613 |
| Directory | /workspace/196.rv_timer_random/latest |
| Test location | /workspace/coverage/default/197.rv_timer_random.152450902 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 73302628596 ps |
| CPU time | 85.01 seconds |
| Started | May 14 12:42:45 PM PDT 24 |
| Finished | May 14 12:44:14 PM PDT 24 |
| Peak memory | 190628 kb |
| Host | smart-0f660df5-a6df-4877-a5a4-10e585435f3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152450902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.152450902 |
| Directory | /workspace/197.rv_timer_random/latest |
| Test location | /workspace/coverage/default/198.rv_timer_random.1656739637 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 789316763687 ps |
| CPU time | 2667.1 seconds |
| Started | May 14 12:42:49 PM PDT 24 |
| Finished | May 14 01:27:21 PM PDT 24 |
| Peak memory | 190776 kb |
| Host | smart-70b559ea-71ec-4889-b674-41d3ee8148c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656739637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1656739637 |
| Directory | /workspace/198.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.840284429 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15431762468 ps |
| CPU time | 26.13 seconds |
| Started | May 14 12:41:57 PM PDT 24 |
| Finished | May 14 12:42:25 PM PDT 24 |
| Peak memory | 182428 kb |
| Host | smart-99b1e574-6907-4f47-9dcb-21fafeb75a5f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840284429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rv_timer_cfg_update_on_fly.840284429 |
| Directory | /workspace/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/2.rv_timer_disabled.285483295 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 870903718768 ps |
| CPU time | 142.36 seconds |
| Started | May 14 12:41:45 PM PDT 24 |
| Finished | May 14 12:44:09 PM PDT 24 |
| Peak memory | 182464 kb |
| Host | smart-ff9b448c-95c3-4e52-a0fc-42b3d20e96cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=285483295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.285483295 |
| Directory | /workspace/2.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random.800987420 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 165564833576 ps |
| CPU time | 246.59 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:46:11 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-799e5961-233e-4f34-854e-cadc7911fb8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800987420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.800987420 |
| Directory | /workspace/2.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random_reset.1017680417 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 146656931869 ps |
| CPU time | 255.24 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:46:19 PM PDT 24 |
| Peak memory | 190696 kb |
| Host | smart-da6a1a62-a1f0-43a2-b614-d5fd6b305cef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017680417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1017680417 |
| Directory | /workspace/2.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_sec_cm.1865646801 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 481809782 ps |
| CPU time | 0.82 seconds |
| Started | May 14 12:42:00 PM PDT 24 |
| Finished | May 14 12:42:03 PM PDT 24 |
| Peak memory | 212984 kb |
| Host | smart-f9c3bea5-7b21-4f8d-9eb5-0dfce4ff8eed |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865646801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1865646801 |
| Directory | /workspace/2.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1415156566 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 840917327191 ps |
| CPU time | 562.94 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:51:29 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-0581fc5e-4da3-4a86-a0a3-bd11dd63eba7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415156566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.1415156566 |
| Directory | /workspace/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/20.rv_timer_disabled.954909600 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 48398216570 ps |
| CPU time | 70.67 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:43:15 PM PDT 24 |
| Peak memory | 182540 kb |
| Host | smart-be9d27e1-59cd-40dc-acca-07848dc65ad8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954909600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.954909600 |
| Directory | /workspace/20.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random.2173080642 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 119582483784 ps |
| CPU time | 59.13 seconds |
| Started | May 14 12:42:06 PM PDT 24 |
| Finished | May 14 12:43:09 PM PDT 24 |
| Peak memory | 190664 kb |
| Host | smart-d1a6603f-9e59-4e45-b005-fea6cab2e604 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173080642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2173080642 |
| Directory | /workspace/20.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random_reset.117734177 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 145124414757 ps |
| CPU time | 231.39 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:46:02 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-5b6fe86c-5c4c-45af-85c5-88c43977cac3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117734177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.117734177 |
| Directory | /workspace/20.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all.458255837 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3553065848294 ps |
| CPU time | 1664.64 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 01:09:56 PM PDT 24 |
| Peak memory | 190736 kb |
| Host | smart-a5da85e2-35e9-4b2e-a3b6-06bd9ad1b705 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458255837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all. 458255837 |
| Directory | /workspace/20.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3545807382 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 926162728498 ps |
| CPU time | 476.23 seconds |
| Started | May 14 12:42:00 PM PDT 24 |
| Finished | May 14 12:49:58 PM PDT 24 |
| Peak memory | 182484 kb |
| Host | smart-efd76a65-4273-4500-962f-79897bb31701 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545807382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.3545807382 |
| Directory | /workspace/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/21.rv_timer_disabled.2835650075 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 562773496116 ps |
| CPU time | 236.53 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:46:04 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-c588a743-f522-4110-81d3-c978a5d67772 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2835650075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2835650075 |
| Directory | /workspace/21.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random.2212024287 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 106382022484 ps |
| CPU time | 414.74 seconds |
| Started | May 14 12:42:15 PM PDT 24 |
| Finished | May 14 12:49:11 PM PDT 24 |
| Peak memory | 190644 kb |
| Host | smart-adfcfce8-1c84-4c63-9578-f4b971e0046c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212024287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2212024287 |
| Directory | /workspace/21.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random_reset.688033599 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 15007596079 ps |
| CPU time | 25.08 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:42:34 PM PDT 24 |
| Peak memory | 190776 kb |
| Host | smart-face38ae-a6f6-4c4e-8a59-0d3b94c86713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688033599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.688033599 |
| Directory | /workspace/21.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2839171670 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2222698987317 ps |
| CPU time | 813.09 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 12:55:48 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-ecd23e6d-f51e-4a66-b4c7-ea4ef12c613d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839171670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.2839171670 |
| Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/22.rv_timer_disabled.1540505144 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 154023871028 ps |
| CPU time | 64.19 seconds |
| Started | May 14 12:42:14 PM PDT 24 |
| Finished | May 14 12:43:20 PM PDT 24 |
| Peak memory | 182464 kb |
| Host | smart-a23e768a-9f3a-4bdc-a471-fa5cb109724b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540505144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1540505144 |
| Directory | /workspace/22.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random.4014516589 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 370275578728 ps |
| CPU time | 349.42 seconds |
| Started | May 14 12:42:31 PM PDT 24 |
| Finished | May 14 12:48:22 PM PDT 24 |
| Peak memory | 190696 kb |
| Host | smart-49c1cc03-fd99-45a1-ae13-eef26421cd10 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014516589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.4014516589 |
| Directory | /workspace/22.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random_reset.616943162 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 98404199 ps |
| CPU time | 1.91 seconds |
| Started | May 14 12:42:31 PM PDT 24 |
| Finished | May 14 12:42:35 PM PDT 24 |
| Peak memory | 182356 kb |
| Host | smart-33b78460-c647-4fb1-9234-07415e59985f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616943162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.616943162 |
| Directory | /workspace/22.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all.3059298563 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 245314815987 ps |
| CPU time | 581.56 seconds |
| Started | May 14 12:42:23 PM PDT 24 |
| Finished | May 14 12:52:06 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-8b80be39-3431-43d5-81f3-909d1ff68c14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059298563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all .3059298563 |
| Directory | /workspace/22.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3487211104 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 128965676456 ps |
| CPU time | 576.35 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 12:51:48 PM PDT 24 |
| Peak memory | 197176 kb |
| Host | smart-0619fecd-eb48-4e01-8b38-8f026cb4ccf2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487211104 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3487211104 |
| Directory | /workspace/22.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1873370246 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 102721851983 ps |
| CPU time | 98.62 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:43:45 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-d34d07af-91a7-42cd-a597-c7ccf3c89c71 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873370246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.1873370246 |
| Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/23.rv_timer_disabled.3365708771 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 37048878901 ps |
| CPU time | 57.7 seconds |
| Started | May 14 12:42:28 PM PDT 24 |
| Finished | May 14 12:43:27 PM PDT 24 |
| Peak memory | 182616 kb |
| Host | smart-e5e793f6-851f-4d4f-80ce-f3e8df473401 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365708771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3365708771 |
| Directory | /workspace/23.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random_reset.1742988286 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 238950929 ps |
| CPU time | 0.93 seconds |
| Started | May 14 12:42:21 PM PDT 24 |
| Finished | May 14 12:42:23 PM PDT 24 |
| Peak memory | 190448 kb |
| Host | smart-2331ee18-c78d-4677-b4f7-864fd4af5e77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742988286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1742988286 |
| Directory | /workspace/23.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2670433326 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 252713154875 ps |
| CPU time | 487.98 seconds |
| Started | May 14 12:42:23 PM PDT 24 |
| Finished | May 14 12:50:33 PM PDT 24 |
| Peak memory | 205492 kb |
| Host | smart-0654bb10-962c-4e7c-a4b1-db8882a3d257 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670433326 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2670433326 |
| Directory | /workspace/23.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3070376742 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 999585686635 ps |
| CPU time | 256.49 seconds |
| Started | May 14 12:42:23 PM PDT 24 |
| Finished | May 14 12:46:41 PM PDT 24 |
| Peak memory | 182552 kb |
| Host | smart-e7397f86-3705-4e8c-bdab-faff5472f2a2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070376742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.3070376742 |
| Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_disabled.960530050 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 45584627001 ps |
| CPU time | 31.43 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 12:43:03 PM PDT 24 |
| Peak memory | 182560 kb |
| Host | smart-d292e8da-23e1-438e-b68b-d7074b9ab12a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960530050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.960530050 |
| Directory | /workspace/24.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random.3694431443 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 146630392959 ps |
| CPU time | 1992.12 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 01:15:24 PM PDT 24 |
| Peak memory | 190584 kb |
| Host | smart-18043a1b-c279-42fa-bf73-142711b35126 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694431443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3694431443 |
| Directory | /workspace/24.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all.1402391798 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1451076011757 ps |
| CPU time | 595.4 seconds |
| Started | May 14 12:42:12 PM PDT 24 |
| Finished | May 14 12:52:09 PM PDT 24 |
| Peak memory | 190816 kb |
| Host | smart-0d35c278-0b1b-40f9-9fcc-a747e743bdcb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402391798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all .1402391798 |
| Directory | /workspace/24.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2796363659 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4362781645 ps |
| CPU time | 2.85 seconds |
| Started | May 14 12:42:12 PM PDT 24 |
| Finished | May 14 12:42:17 PM PDT 24 |
| Peak memory | 182552 kb |
| Host | smart-36390554-d4d0-4870-836b-68f4dbfd42a3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796363659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2796363659 |
| Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/25.rv_timer_disabled.1473130013 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 50191358100 ps |
| CPU time | 83.96 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 12:43:55 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-b18be5f4-8f84-404d-a171-b41804683dd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473130013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1473130013 |
| Directory | /workspace/25.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random.2299659901 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 638522188029 ps |
| CPU time | 458.19 seconds |
| Started | May 14 12:42:18 PM PDT 24 |
| Finished | May 14 12:49:57 PM PDT 24 |
| Peak memory | 190624 kb |
| Host | smart-58dd9223-ab95-49eb-ba91-a7d242efec17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299659901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2299659901 |
| Directory | /workspace/25.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random_reset.3136477622 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 102093974352 ps |
| CPU time | 1891.36 seconds |
| Started | May 14 12:42:15 PM PDT 24 |
| Finished | May 14 01:13:48 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-bc8e23fc-bcaf-4be3-9c09-aba408ae59d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136477622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3136477622 |
| Directory | /workspace/25.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all.2708296928 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 52789936 ps |
| CPU time | 0.52 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:42:04 PM PDT 24 |
| Peak memory | 181768 kb |
| Host | smart-72848265-99c9-427e-a02d-bb265d5ce60f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708296928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all .2708296928 |
| Directory | /workspace/25.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3659795642 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 21665397242 ps |
| CPU time | 37.59 seconds |
| Started | May 14 12:42:04 PM PDT 24 |
| Finished | May 14 12:42:45 PM PDT 24 |
| Peak memory | 182580 kb |
| Host | smart-ed75d741-d6e4-47cb-b673-177a9a47f759 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659795642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3659795642 |
| Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/26.rv_timer_disabled.1551188382 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 272225266011 ps |
| CPU time | 123.44 seconds |
| Started | May 14 12:42:07 PM PDT 24 |
| Finished | May 14 12:44:14 PM PDT 24 |
| Peak memory | 182452 kb |
| Host | smart-e57927fa-836d-4463-b1d6-a0526974a405 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551188382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1551188382 |
| Directory | /workspace/26.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random_reset.3453858722 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1106206300 ps |
| CPU time | 0.91 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:42:10 PM PDT 24 |
| Peak memory | 190928 kb |
| Host | smart-c1972717-5e4c-4caf-9f0d-96139cceef2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453858722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3453858722 |
| Directory | /workspace/26.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1068106682 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 320751454043 ps |
| CPU time | 563.56 seconds |
| Started | May 14 12:42:23 PM PDT 24 |
| Finished | May 14 12:51:48 PM PDT 24 |
| Peak memory | 182456 kb |
| Host | smart-0ab4a001-49a8-4b26-82c6-6bf9aadca969 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068106682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.1068106682 |
| Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/27.rv_timer_disabled.919108865 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 128113862696 ps |
| CPU time | 210.46 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:45:51 PM PDT 24 |
| Peak memory | 182472 kb |
| Host | smart-cbe6c95e-3a89-480c-b707-aa7f1cc59038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919108865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.919108865 |
| Directory | /workspace/27.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random.3426831707 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 148658578796 ps |
| CPU time | 508.09 seconds |
| Started | May 14 12:42:15 PM PDT 24 |
| Finished | May 14 12:50:44 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-c409b895-baa3-4604-908f-60cc12fd732a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426831707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3426831707 |
| Directory | /workspace/27.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random_reset.3035451089 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 80335707578 ps |
| CPU time | 1504.4 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 01:07:38 PM PDT 24 |
| Peak memory | 182456 kb |
| Host | smart-8e67942f-5101-498d-9232-d637c4554abb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035451089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3035451089 |
| Directory | /workspace/27.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.697738530 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1092990534736 ps |
| CPU time | 610.75 seconds |
| Started | May 14 12:42:21 PM PDT 24 |
| Finished | May 14 12:52:33 PM PDT 24 |
| Peak memory | 182472 kb |
| Host | smart-897c10e7-0c38-4302-a10d-69c02df21305 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697738530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.rv_timer_cfg_update_on_fly.697738530 |
| Directory | /workspace/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/28.rv_timer_disabled.960129831 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 25494532684 ps |
| CPU time | 36.28 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 12:42:47 PM PDT 24 |
| Peak memory | 182500 kb |
| Host | smart-71ec0c2c-35bd-4fab-a6c2-3483eff3ecfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960129831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.960129831 |
| Directory | /workspace/28.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random.1215565044 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 147571286394 ps |
| CPU time | 167 seconds |
| Started | May 14 12:42:27 PM PDT 24 |
| Finished | May 14 12:45:15 PM PDT 24 |
| Peak memory | 190672 kb |
| Host | smart-0a7e09c2-83aa-4e16-aa2e-6a2ef3379e03 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215565044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1215565044 |
| Directory | /workspace/28.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random_reset.221178042 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 77762616161 ps |
| CPU time | 43.17 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:42:51 PM PDT 24 |
| Peak memory | 192580 kb |
| Host | smart-0c4de737-dc3b-4d72-9b49-f1b0e8f32037 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=221178042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.221178042 |
| Directory | /workspace/28.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2613756327 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 54612280473 ps |
| CPU time | 227.8 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 12:46:15 PM PDT 24 |
| Peak memory | 197104 kb |
| Host | smart-ee19c30c-5459-4e69-b0bc-478c6f028e3d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613756327 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2613756327 |
| Directory | /workspace/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_disabled.1255901495 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 311389343230 ps |
| CPU time | 82.77 seconds |
| Started | May 14 12:42:02 PM PDT 24 |
| Finished | May 14 12:43:27 PM PDT 24 |
| Peak memory | 182440 kb |
| Host | smart-f3348713-7a26-4894-87f7-4431af462927 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255901495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1255901495 |
| Directory | /workspace/29.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random.1020370385 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 174733576601 ps |
| CPU time | 153.31 seconds |
| Started | May 14 12:42:03 PM PDT 24 |
| Finished | May 14 12:44:39 PM PDT 24 |
| Peak memory | 190636 kb |
| Host | smart-1bd2bbb4-41e9-4516-92cb-436d8b1a5c74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020370385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1020370385 |
| Directory | /workspace/29.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random_reset.1671214696 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 40166973133 ps |
| CPU time | 162.41 seconds |
| Started | May 14 12:42:07 PM PDT 24 |
| Finished | May 14 12:44:53 PM PDT 24 |
| Peak memory | 190704 kb |
| Host | smart-e8ebf28c-f6d7-4d1a-9a09-fb85d80301f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671214696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1671214696 |
| Directory | /workspace/29.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random_reset.974459683 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 20146512053 ps |
| CPU time | 28.11 seconds |
| Started | May 14 12:42:00 PM PDT 24 |
| Finished | May 14 12:42:30 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-c8360a09-3086-4e99-89ed-7b73ed5fc5c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974459683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.974459683 |
| Directory | /workspace/3.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_sec_cm.3798510013 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 362470807 ps |
| CPU time | 0.83 seconds |
| Started | May 14 12:41:51 PM PDT 24 |
| Finished | May 14 12:41:54 PM PDT 24 |
| Peak memory | 212884 kb |
| Host | smart-41f045c6-57a8-4a7e-9ca5-fad7428da66d |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798510013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3798510013 |
| Directory | /workspace/3.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3026734038 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 9240665885 ps |
| CPU time | 16.86 seconds |
| Started | May 14 12:42:28 PM PDT 24 |
| Finished | May 14 12:42:46 PM PDT 24 |
| Peak memory | 182516 kb |
| Host | smart-2be529cf-3b77-4cac-ae32-e44298fe6a1a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026734038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.3026734038 |
| Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_disabled.3472367456 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 790717393241 ps |
| CPU time | 264.38 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:47:04 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-0a61fa5f-74b6-4fbb-ad82-a5c1bfa89c1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472367456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3472367456 |
| Directory | /workspace/30.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random_reset.1720826313 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 76680663094 ps |
| CPU time | 60.14 seconds |
| Started | May 14 12:42:21 PM PDT 24 |
| Finished | May 14 12:43:22 PM PDT 24 |
| Peak memory | 193796 kb |
| Host | smart-037a620e-66a5-4b5b-abd0-c8fc2d928ad3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1720826313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1720826313 |
| Directory | /workspace/30.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1788160616 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30918365116 ps |
| CPU time | 346.52 seconds |
| Started | May 14 12:42:51 PM PDT 24 |
| Finished | May 14 12:48:42 PM PDT 24 |
| Peak memory | 205224 kb |
| Host | smart-8e38c76c-df70-42f0-a738-e11ef5333669 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788160616 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1788160616 |
| Directory | /workspace/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.622710411 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 96810218966 ps |
| CPU time | 95.36 seconds |
| Started | May 14 12:42:20 PM PDT 24 |
| Finished | May 14 12:43:57 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-f5514a1a-5ecd-48ad-b851-aafcb30a0cc4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622710411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.rv_timer_cfg_update_on_fly.622710411 |
| Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/31.rv_timer_disabled.3235683700 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 397565528923 ps |
| CPU time | 151.36 seconds |
| Started | May 14 12:42:24 PM PDT 24 |
| Finished | May 14 12:44:57 PM PDT 24 |
| Peak memory | 182416 kb |
| Host | smart-58d6af2c-4002-4846-b006-d2ca67fa220a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235683700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3235683700 |
| Directory | /workspace/31.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random.616214538 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 30497599751 ps |
| CPU time | 98.63 seconds |
| Started | May 14 12:41:59 PM PDT 24 |
| Finished | May 14 12:43:39 PM PDT 24 |
| Peak memory | 190816 kb |
| Host | smart-30173192-996f-4b58-ae1e-c8a56d46d1e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616214538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.616214538 |
| Directory | /workspace/31.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random_reset.3455419468 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 159493176310 ps |
| CPU time | 74.83 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:43:36 PM PDT 24 |
| Peak memory | 194288 kb |
| Host | smart-17a4b9b9-aa23-4225-8564-a16c90c4cb00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455419468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3455419468 |
| Directory | /workspace/31.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all.4001565835 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 629392484069 ps |
| CPU time | 393.01 seconds |
| Started | May 14 12:42:22 PM PDT 24 |
| Finished | May 14 12:48:56 PM PDT 24 |
| Peak memory | 190604 kb |
| Host | smart-ab80cef9-7f48-4750-8ef6-84451fe2eae1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001565835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all .4001565835 |
| Directory | /workspace/31.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1509579179 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 258041599635 ps |
| CPU time | 150.67 seconds |
| Started | May 14 12:42:50 PM PDT 24 |
| Finished | May 14 12:45:25 PM PDT 24 |
| Peak memory | 182456 kb |
| Host | smart-5a7670df-5f9e-4cc8-894f-0d99a5fc48b9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509579179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.1509579179 |
| Directory | /workspace/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/32.rv_timer_disabled.4209129215 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 315473685156 ps |
| CPU time | 120.67 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 12:44:13 PM PDT 24 |
| Peak memory | 182472 kb |
| Host | smart-7696814f-8477-410d-b2ec-d78c4a4ec6f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209129215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4209129215 |
| Directory | /workspace/32.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random.1889252061 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 156929147075 ps |
| CPU time | 377.99 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:48:21 PM PDT 24 |
| Peak memory | 190784 kb |
| Host | smart-c3b52ad7-b54c-40b8-a5d2-dc25ce43803c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889252061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1889252061 |
| Directory | /workspace/32.rv_timer_random/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random_reset.3221698946 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 721699572688 ps |
| CPU time | 139.6 seconds |
| Started | May 14 12:42:22 PM PDT 24 |
| Finished | May 14 12:44:43 PM PDT 24 |
| Peak memory | 190744 kb |
| Host | smart-92b41ec6-3f23-4b5b-b92a-f11019bfa7e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221698946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3221698946 |
| Directory | /workspace/32.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all.3243103068 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 612376191817 ps |
| CPU time | 507.9 seconds |
| Started | May 14 12:42:16 PM PDT 24 |
| Finished | May 14 12:50:45 PM PDT 24 |
| Peak memory | 190620 kb |
| Host | smart-7232df0d-7408-4dee-a0bc-43b578d51054 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243103068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all .3243103068 |
| Directory | /workspace/32.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1004996308 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1557729854 ps |
| CPU time | 3.35 seconds |
| Started | May 14 12:42:16 PM PDT 24 |
| Finished | May 14 12:42:21 PM PDT 24 |
| Peak memory | 182212 kb |
| Host | smart-e4e21daa-1b91-4868-9403-deea128baa0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004996308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1004996308 |
| Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/33.rv_timer_disabled.162668140 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 71167617697 ps |
| CPU time | 29.04 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:42:49 PM PDT 24 |
| Peak memory | 182508 kb |
| Host | smart-7f7ddee9-2f17-419f-97fe-43773e517258 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162668140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.162668140 |
| Directory | /workspace/33.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random.3272675616 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 368607190643 ps |
| CPU time | 222.33 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 12:46:22 PM PDT 24 |
| Peak memory | 190680 kb |
| Host | smart-b87b5348-6091-409c-9731-c6f88358d5d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272675616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3272675616 |
| Directory | /workspace/33.rv_timer_random/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random_reset.1492640425 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 58594856432 ps |
| CPU time | 95.96 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:44:17 PM PDT 24 |
| Peak memory | 190644 kb |
| Host | smart-307a36bc-d2c0-4e35-90e2-3cbaf94ae00b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492640425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1492640425 |
| Directory | /workspace/33.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all.623987973 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 167155018124 ps |
| CPU time | 227.96 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 12:46:00 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-adefcc67-374c-4858-9589-6ccf417c0f31 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623987973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all. 623987973 |
| Directory | /workspace/33.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2997338487 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 134223628006 ps |
| CPU time | 250.23 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:46:31 PM PDT 24 |
| Peak memory | 182568 kb |
| Host | smart-8d106c18-19b4-45be-bb38-25dc11b1a729 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997338487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.2997338487 |
| Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/34.rv_timer_disabled.1528903233 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 556196709483 ps |
| CPU time | 241.04 seconds |
| Started | May 14 12:42:36 PM PDT 24 |
| Finished | May 14 12:46:38 PM PDT 24 |
| Peak memory | 182496 kb |
| Host | smart-d313779a-28d8-4de5-9875-9a04ac5d529a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528903233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1528903233 |
| Directory | /workspace/34.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random.2862904904 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 359440535356 ps |
| CPU time | 351.9 seconds |
| Started | May 14 12:42:14 PM PDT 24 |
| Finished | May 14 12:48:07 PM PDT 24 |
| Peak memory | 192844 kb |
| Host | smart-0ba9fd54-1ea6-49b0-80ff-4c089066ee41 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862904904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2862904904 |
| Directory | /workspace/34.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random_reset.2935633084 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 23958371366 ps |
| CPU time | 38.46 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:43:12 PM PDT 24 |
| Peak memory | 182480 kb |
| Host | smart-aed220ad-9efc-467a-83c2-751d7936f2e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935633084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2935633084 |
| Directory | /workspace/34.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2146006560 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 455416831844 ps |
| CPU time | 428.3 seconds |
| Started | May 14 12:42:21 PM PDT 24 |
| Finished | May 14 12:49:31 PM PDT 24 |
| Peak memory | 182464 kb |
| Host | smart-395f5557-d008-4729-875e-147e0befc1c8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146006560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.2146006560 |
| Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/35.rv_timer_disabled.2758263118 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 74707784949 ps |
| CPU time | 119.16 seconds |
| Started | May 14 12:42:23 PM PDT 24 |
| Finished | May 14 12:44:23 PM PDT 24 |
| Peak memory | 182456 kb |
| Host | smart-ef18487c-819a-4fa3-a248-0ca2df861930 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758263118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2758263118 |
| Directory | /workspace/35.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random.3898822549 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 137903146789 ps |
| CPU time | 152.95 seconds |
| Started | May 14 12:42:24 PM PDT 24 |
| Finished | May 14 12:44:58 PM PDT 24 |
| Peak memory | 190624 kb |
| Host | smart-d85f3a4d-1ad7-41a9-ba60-d18eb58082c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898822549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3898822549 |
| Directory | /workspace/35.rv_timer_random/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random_reset.3963241811 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 380900071 ps |
| CPU time | 1.41 seconds |
| Started | May 14 12:42:17 PM PDT 24 |
| Finished | May 14 12:42:20 PM PDT 24 |
| Peak memory | 182372 kb |
| Host | smart-842ba11c-225b-44f9-a482-f782e6bbd99a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963241811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3963241811 |
| Directory | /workspace/35.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all.2689354084 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 694392225466 ps |
| CPU time | 553.55 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:51:34 PM PDT 24 |
| Peak memory | 190712 kb |
| Host | smart-5d9d3ca1-1bfc-41cc-9e10-850a76f914a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689354084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all .2689354084 |
| Directory | /workspace/35.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.521723809 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2160347702680 ps |
| CPU time | 879.29 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 12:57:06 PM PDT 24 |
| Peak memory | 182428 kb |
| Host | smart-91f62ff2-7535-4001-9829-9b21646dfba8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521723809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.rv_timer_cfg_update_on_fly.521723809 |
| Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/36.rv_timer_disabled.382135102 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 557185921303 ps |
| CPU time | 206.61 seconds |
| Started | May 14 12:42:11 PM PDT 24 |
| Finished | May 14 12:45:40 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-da9b3dc5-1f07-4e0c-ac92-caea6e780bf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382135102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.382135102 |
| Directory | /workspace/36.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all.757594616 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 816477093306 ps |
| CPU time | 1132.5 seconds |
| Started | May 14 12:42:34 PM PDT 24 |
| Finished | May 14 01:01:28 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-5fc69458-0ab4-41a3-98e8-444b1605cee5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757594616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all. 757594616 |
| Directory | /workspace/36.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.4262389770 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 120750797854 ps |
| CPU time | 168.52 seconds |
| Started | May 14 12:42:24 PM PDT 24 |
| Finished | May 14 12:45:14 PM PDT 24 |
| Peak memory | 182460 kb |
| Host | smart-1bd06870-65a7-4631-acc2-aaa981062c87 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262389770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.4262389770 |
| Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/37.rv_timer_disabled.4265181440 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 412351080237 ps |
| CPU time | 176.88 seconds |
| Started | May 14 12:42:20 PM PDT 24 |
| Finished | May 14 12:45:18 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-8d07586a-91d9-4ccd-a9d5-b0c13017f26c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265181440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.4265181440 |
| Directory | /workspace/37.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random.1551061707 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 219216694807 ps |
| CPU time | 170.79 seconds |
| Started | May 14 12:42:17 PM PDT 24 |
| Finished | May 14 12:45:08 PM PDT 24 |
| Peak memory | 194380 kb |
| Host | smart-463aeaa0-7492-4752-b720-59d10613a600 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551061707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1551061707 |
| Directory | /workspace/37.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random_reset.712004616 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 62920930283 ps |
| CPU time | 117.9 seconds |
| Started | May 14 12:42:06 PM PDT 24 |
| Finished | May 14 12:44:07 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-5b96fc5d-c7f1-48c4-87be-6cc8a8e5b384 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712004616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.712004616 |
| Directory | /workspace/37.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all.94118397 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 929810347121 ps |
| CPU time | 329.08 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 12:47:56 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-19a1ddb9-40fb-44e4-babf-734273e00209 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94118397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.94118397 |
| Directory | /workspace/37.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4241207855 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 206027750744 ps |
| CPU time | 334.87 seconds |
| Started | May 14 12:42:36 PM PDT 24 |
| Finished | May 14 12:48:12 PM PDT 24 |
| Peak memory | 182480 kb |
| Host | smart-70ce23e4-7a4b-4769-9de9-6511d355301a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241207855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.4241207855 |
| Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/38.rv_timer_disabled.2019714133 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 111253452061 ps |
| CPU time | 140.08 seconds |
| Started | May 14 12:42:49 PM PDT 24 |
| Finished | May 14 12:45:14 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-cd18eba8-627d-4bd2-a5a8-3cde9e7dfded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019714133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2019714133 |
| Directory | /workspace/38.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random.3633247029 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 110457999542 ps |
| CPU time | 104.62 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:44:26 PM PDT 24 |
| Peak memory | 194152 kb |
| Host | smart-ef58f2e4-a664-47fa-81bf-f6e949784f3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633247029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3633247029 |
| Directory | /workspace/38.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random_reset.744309762 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 243679140716 ps |
| CPU time | 112.59 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:44:14 PM PDT 24 |
| Peak memory | 182440 kb |
| Host | smart-f6cc5133-f63e-471a-ae8e-e465a7255f2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744309762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.744309762 |
| Directory | /workspace/38.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1262943373 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11997703937 ps |
| CPU time | 129.26 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:44:44 PM PDT 24 |
| Peak memory | 197092 kb |
| Host | smart-6b50cce0-8789-4034-8564-ab58cd126f9e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262943373 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1262943373 |
| Directory | /workspace/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2981220946 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 482946406044 ps |
| CPU time | 443.58 seconds |
| Started | May 14 12:42:19 PM PDT 24 |
| Finished | May 14 12:49:44 PM PDT 24 |
| Peak memory | 182612 kb |
| Host | smart-1788c1f2-2d3c-4083-be19-0e93970f65ae |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981220946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.2981220946 |
| Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/39.rv_timer_disabled.1701224840 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 303789699102 ps |
| CPU time | 126.06 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:44:40 PM PDT 24 |
| Peak memory | 182552 kb |
| Host | smart-43861278-c906-4f1f-a070-8807e4041eb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701224840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1701224840 |
| Directory | /workspace/39.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random_reset.4184423171 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 931968774 ps |
| CPU time | 3.23 seconds |
| Started | May 14 12:42:22 PM PDT 24 |
| Finished | May 14 12:42:26 PM PDT 24 |
| Peak memory | 182384 kb |
| Host | smart-11160bb6-3baf-4cc2-868f-b61a35210ea2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184423171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.4184423171 |
| Directory | /workspace/39.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all.3585197046 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 401088018516 ps |
| CPU time | 240.66 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:46:54 PM PDT 24 |
| Peak memory | 190468 kb |
| Host | smart-590f4468-37e7-4008-9545-3d72335b8958 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585197046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .3585197046 |
| Directory | /workspace/39.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.rv_timer_disabled.2099944890 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 164096468488 ps |
| CPU time | 134.11 seconds |
| Started | May 14 12:42:10 PM PDT 24 |
| Finished | May 14 12:44:28 PM PDT 24 |
| Peak memory | 182464 kb |
| Host | smart-a9c3b1c9-99f3-4e0d-9c98-40e0abc33861 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099944890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2099944890 |
| Directory | /workspace/4.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random_reset.3411830136 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 90862396629 ps |
| CPU time | 150.1 seconds |
| Started | May 14 12:42:07 PM PDT 24 |
| Finished | May 14 12:44:40 PM PDT 24 |
| Peak memory | 190660 kb |
| Host | smart-a7f5633a-dd03-41f5-85ad-41380db8b335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411830136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3411830136 |
| Directory | /workspace/4.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_sec_cm.3371497747 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 426553079 ps |
| CPU time | 0.93 seconds |
| Started | May 14 12:41:53 PM PDT 24 |
| Finished | May 14 12:41:57 PM PDT 24 |
| Peak memory | 214000 kb |
| Host | smart-f72bfe94-422c-4c5d-b7a7-356b04de68ae |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371497747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3371497747 |
| Directory | /workspace/4.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all.1986120129 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 157157389090 ps |
| CPU time | 112.08 seconds |
| Started | May 14 12:42:08 PM PDT 24 |
| Finished | May 14 12:44:03 PM PDT 24 |
| Peak memory | 182468 kb |
| Host | smart-66808af3-9699-4fe8-a953-baaf924dbc48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986120129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 1986120129 |
| Directory | /workspace/4.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1688467259 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 706174977536 ps |
| CPU time | 392.82 seconds |
| Started | May 14 12:42:12 PM PDT 24 |
| Finished | May 14 12:48:47 PM PDT 24 |
| Peak memory | 182560 kb |
| Host | smart-2b92bb78-2450-4f4c-b092-211e2b456496 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688467259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.1688467259 |
| Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/40.rv_timer_disabled.2742740267 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 50817265914 ps |
| CPU time | 24.58 seconds |
| Started | May 14 12:42:15 PM PDT 24 |
| Finished | May 14 12:42:41 PM PDT 24 |
| Peak memory | 182508 kb |
| Host | smart-df751cfd-e2a7-4de7-bfa7-3bb39644e4be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2742740267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2742740267 |
| Directory | /workspace/40.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random.812131224 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 27516105620 ps |
| CPU time | 45.16 seconds |
| Started | May 14 12:42:13 PM PDT 24 |
| Finished | May 14 12:43:00 PM PDT 24 |
| Peak memory | 182436 kb |
| Host | smart-050e8f4a-f6bd-4fe6-968c-9e85cefebbbb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812131224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.812131224 |
| Directory | /workspace/40.rv_timer_random/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random_reset.3689022013 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 51082697423 ps |
| CPU time | 154.42 seconds |
| Started | May 14 12:42:21 PM PDT 24 |
| Finished | May 14 12:44:56 PM PDT 24 |
| Peak memory | 192872 kb |
| Host | smart-79515f51-7bfb-47b8-926b-5615566f96ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689022013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3689022013 |
| Directory | /workspace/40.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all.1104444139 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 46101791635 ps |
| CPU time | 73.3 seconds |
| Started | May 14 12:42:23 PM PDT 24 |
| Finished | May 14 12:43:38 PM PDT 24 |
| Peak memory | 193388 kb |
| Host | smart-480fdb2a-3643-464e-9a98-6548ef30ced9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104444139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all .1104444139 |
| Directory | /workspace/40.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.725247955 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 47964817796 ps |
| CPU time | 555.21 seconds |
| Started | May 14 12:42:05 PM PDT 24 |
| Finished | May 14 12:51:24 PM PDT 24 |
| Peak memory | 209600 kb |
| Host | smart-e19dcf97-68ec-4398-8b05-b3fb2b360f08 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725247955 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.725247955 |
| Directory | /workspace/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1567362812 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 78892989148 ps |
| CPU time | 128.09 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 12:44:39 PM PDT 24 |
| Peak memory | 182616 kb |
| Host | smart-46c10fae-1bf2-4d9a-b683-9dc5a5069ed9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567362812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.1567362812 |
| Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/41.rv_timer_disabled.273167712 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 132001120134 ps |
| CPU time | 216.67 seconds |
| Started | May 14 12:42:24 PM PDT 24 |
| Finished | May 14 12:46:02 PM PDT 24 |
| Peak memory | 182556 kb |
| Host | smart-b9523838-d0bb-4d88-99c9-d68ea9ca0d85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273167712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.273167712 |
| Directory | /workspace/41.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random.302218061 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 233638731293 ps |
| CPU time | 217.45 seconds |
| Started | May 14 12:42:13 PM PDT 24 |
| Finished | May 14 12:45:52 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-cbf999bc-f7e5-440e-8ec8-1a7ab0306dd4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302218061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.302218061 |
| Directory | /workspace/41.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all.38326076 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 614741576153 ps |
| CPU time | 1103.53 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 01:01:02 PM PDT 24 |
| Peak memory | 190676 kb |
| Host | smart-16c7b00c-9c10-47b3-9a17-e4c4c0ad44b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.38326076 |
| Directory | /workspace/41.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3370544168 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 324529539972 ps |
| CPU time | 567.79 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 12:52:00 PM PDT 24 |
| Peak memory | 182488 kb |
| Host | smart-692f9ac5-fdca-4a70-8973-8e6357cfc78f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370544168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.3370544168 |
| Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_disabled.2168918519 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 596171529986 ps |
| CPU time | 77.58 seconds |
| Started | May 14 12:42:47 PM PDT 24 |
| Finished | May 14 12:44:10 PM PDT 24 |
| Peak memory | 182604 kb |
| Host | smart-d9046226-14b4-487f-8aa3-7b7aad77a593 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168918519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2168918519 |
| Directory | /workspace/42.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random.1164195441 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 613198793013 ps |
| CPU time | 645.49 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:53:20 PM PDT 24 |
| Peak memory | 190740 kb |
| Host | smart-a78a33a8-76d0-4b29-99b5-a5febb12bce3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164195441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1164195441 |
| Directory | /workspace/42.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random_reset.1351652011 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 77950556408 ps |
| CPU time | 113.86 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:44:29 PM PDT 24 |
| Peak memory | 190616 kb |
| Host | smart-d5d5bd3d-db52-46f5-8beb-e3b3d2cedd86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1351652011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1351652011 |
| Directory | /workspace/42.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2614650608 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 371803327218 ps |
| CPU time | 355.88 seconds |
| Started | May 14 12:42:31 PM PDT 24 |
| Finished | May 14 12:48:29 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-dc25129f-2a10-45ae-8b47-efb2ad247620 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614650608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.2614650608 |
| Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_disabled.3449157611 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 200150757753 ps |
| CPU time | 146.27 seconds |
| Started | May 14 12:42:26 PM PDT 24 |
| Finished | May 14 12:44:54 PM PDT 24 |
| Peak memory | 182616 kb |
| Host | smart-8d8eb109-360e-4018-8e8b-c56286a7a699 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449157611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3449157611 |
| Directory | /workspace/43.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random.3039075754 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 124942665721 ps |
| CPU time | 1583.98 seconds |
| Started | May 14 12:42:31 PM PDT 24 |
| Finished | May 14 01:08:57 PM PDT 24 |
| Peak memory | 193020 kb |
| Host | smart-97aeb3cb-2f55-431b-8603-048b10fe7413 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039075754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3039075754 |
| Directory | /workspace/43.rv_timer_random/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random_reset.4087231252 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 38094294208 ps |
| CPU time | 59.42 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 12:43:30 PM PDT 24 |
| Peak memory | 194232 kb |
| Host | smart-4ad3d6d8-e46e-4bef-8e58-66e232cba743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087231252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4087231252 |
| Directory | /workspace/43.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all.55857589 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1159762128205 ps |
| CPU time | 512.04 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:51:07 PM PDT 24 |
| Peak memory | 190640 kb |
| Host | smart-1b23d7e1-14cd-4c08-8ed1-09dfa4ea4a97 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55857589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.55857589 |
| Directory | /workspace/43.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.401663565 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 42544137268 ps |
| CPU time | 125.1 seconds |
| Started | May 14 12:42:28 PM PDT 24 |
| Finished | May 14 12:44:34 PM PDT 24 |
| Peak memory | 205260 kb |
| Host | smart-906b0524-9b81-4d15-9201-9538120bf3d5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401663565 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.401663565 |
| Directory | /workspace/43.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3613756251 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 346095130395 ps |
| CPU time | 329.52 seconds |
| Started | May 14 12:42:18 PM PDT 24 |
| Finished | May 14 12:47:49 PM PDT 24 |
| Peak memory | 182592 kb |
| Host | smart-d5754e9d-43cb-4394-b15d-4a101d4e40d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613756251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.3613756251 |
| Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_disabled.4033681389 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 179011899028 ps |
| CPU time | 253.4 seconds |
| Started | May 14 12:42:40 PM PDT 24 |
| Finished | May 14 12:46:58 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-8f35f1bf-9b40-431f-939f-7232be8eea08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033681389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4033681389 |
| Directory | /workspace/44.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random.2739200825 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 188112647801 ps |
| CPU time | 485.52 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 12:50:32 PM PDT 24 |
| Peak memory | 192384 kb |
| Host | smart-a7bf130d-5a6d-44be-aae8-26bd6d64f83e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739200825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2739200825 |
| Directory | /workspace/44.rv_timer_random/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random_reset.1337007438 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 653214264 ps |
| CPU time | 0.86 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:42:36 PM PDT 24 |
| Peak memory | 182372 kb |
| Host | smart-74308d77-77f7-4a9a-8d62-fdb62181a5a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1337007438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1337007438 |
| Directory | /workspace/44.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.66256911 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 573598462279 ps |
| CPU time | 510.14 seconds |
| Started | May 14 12:42:44 PM PDT 24 |
| Finished | May 14 12:51:20 PM PDT 24 |
| Peak memory | 182420 kb |
| Host | smart-ec3b15e6-2047-42de-aede-98d391efe1e4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66256911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .rv_timer_cfg_update_on_fly.66256911 |
| Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/45.rv_timer_disabled.4248279966 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 310750656427 ps |
| CPU time | 130.25 seconds |
| Started | May 14 12:42:40 PM PDT 24 |
| Finished | May 14 12:44:53 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-b5ac2806-296a-4473-bd02-a7bdaf738847 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4248279966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.4248279966 |
| Directory | /workspace/45.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random.831671833 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 157121316025 ps |
| CPU time | 127.39 seconds |
| Started | May 14 12:42:18 PM PDT 24 |
| Finished | May 14 12:44:27 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-4b87173d-ec84-4c3a-bd64-6957f3104e16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831671833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.831671833 |
| Directory | /workspace/45.rv_timer_random/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random_reset.4048758429 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 14361479 ps |
| CPU time | 0.55 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:42:34 PM PDT 24 |
| Peak memory | 182272 kb |
| Host | smart-854b1c36-cb8c-44ba-b59e-707af3e19e42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048758429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4048758429 |
| Directory | /workspace/45.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1306042098 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 67413689778 ps |
| CPU time | 105.32 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:44:19 PM PDT 24 |
| Peak memory | 182608 kb |
| Host | smart-1f8476d7-e351-472b-abd3-9ec2ff5d2d62 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306042098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.1306042098 |
| Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_disabled.390377576 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 71091175308 ps |
| CPU time | 61.4 seconds |
| Started | May 14 12:42:36 PM PDT 24 |
| Finished | May 14 12:43:38 PM PDT 24 |
| Peak memory | 182508 kb |
| Host | smart-08a58ec9-a1e0-4cc8-b8a8-c3cb9b5a037e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390377576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.390377576 |
| Directory | /workspace/46.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random.4084753466 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 327610513811 ps |
| CPU time | 177.28 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 12:45:24 PM PDT 24 |
| Peak memory | 193532 kb |
| Host | smart-50fb758e-8523-4992-9893-75b1a9fd5450 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084753466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4084753466 |
| Directory | /workspace/46.rv_timer_random/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random_reset.3961189108 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 785372027 ps |
| CPU time | 0.93 seconds |
| Started | May 14 12:42:44 PM PDT 24 |
| Finished | May 14 12:42:50 PM PDT 24 |
| Peak memory | 192220 kb |
| Host | smart-70189a5e-c5c1-478c-9f04-b12f202ba7e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961189108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3961189108 |
| Directory | /workspace/46.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2568990937 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 84231196096 ps |
| CPU time | 910.05 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 12:57:37 PM PDT 24 |
| Peak memory | 213260 kb |
| Host | smart-6178045c-fccc-4093-b8b9-4d8f15bcc53b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568990937 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2568990937 |
| Directory | /workspace/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1302454160 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 561232872617 ps |
| CPU time | 988.84 seconds |
| Started | May 14 12:42:55 PM PDT 24 |
| Finished | May 14 12:59:26 PM PDT 24 |
| Peak memory | 182480 kb |
| Host | smart-32bf0d81-8d96-4bd0-ae72-c3ddedcba4ad |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302454160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.1302454160 |
| Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/47.rv_timer_disabled.2153586602 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 47662258862 ps |
| CPU time | 71.82 seconds |
| Started | May 14 12:42:24 PM PDT 24 |
| Finished | May 14 12:43:37 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-b1379099-5aec-4ec8-a743-8ebce947209a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153586602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2153586602 |
| Directory | /workspace/47.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random.3307812633 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 532368790372 ps |
| CPU time | 241.64 seconds |
| Started | May 14 12:42:26 PM PDT 24 |
| Finished | May 14 12:46:29 PM PDT 24 |
| Peak memory | 190740 kb |
| Host | smart-b959e921-dea2-4c0d-8b5b-e114dbf0b01d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307812633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3307812633 |
| Directory | /workspace/47.rv_timer_random/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random_reset.372339049 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 81177675589 ps |
| CPU time | 32.31 seconds |
| Started | May 14 12:42:31 PM PDT 24 |
| Finished | May 14 12:43:04 PM PDT 24 |
| Peak memory | 190776 kb |
| Host | smart-f8967535-ff5a-41e4-9069-cff83a4c7501 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372339049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.372339049 |
| Directory | /workspace/47.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_disabled.413025128 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 43156757721 ps |
| CPU time | 72.78 seconds |
| Started | May 14 12:42:18 PM PDT 24 |
| Finished | May 14 12:43:32 PM PDT 24 |
| Peak memory | 182448 kb |
| Host | smart-97073795-811a-482b-bf09-d1bc04cdeb6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=413025128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.413025128 |
| Directory | /workspace/48.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random.1511533252 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 80976347901 ps |
| CPU time | 1838.13 seconds |
| Started | May 14 12:42:27 PM PDT 24 |
| Finished | May 14 01:13:06 PM PDT 24 |
| Peak memory | 190680 kb |
| Host | smart-fc3943a5-ee13-4848-9cdd-662d79de4596 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511533252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1511533252 |
| Directory | /workspace/48.rv_timer_random/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random_reset.3105162787 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 23671021508 ps |
| CPU time | 90.38 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 12:44:09 PM PDT 24 |
| Peak memory | 182580 kb |
| Host | smart-80f1e9b9-37f5-4813-b125-a285d5ff8ef0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105162787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3105162787 |
| Directory | /workspace/48.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_disabled.1658288503 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 47472738996 ps |
| CPU time | 69.21 seconds |
| Started | May 14 12:42:29 PM PDT 24 |
| Finished | May 14 12:43:40 PM PDT 24 |
| Peak memory | 182436 kb |
| Host | smart-826a1a1f-4d4c-4101-ad3c-578a55a14300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658288503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1658288503 |
| Directory | /workspace/49.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random.4046723330 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 156635452083 ps |
| CPU time | 278.83 seconds |
| Started | May 14 12:42:34 PM PDT 24 |
| Finished | May 14 12:47:15 PM PDT 24 |
| Peak memory | 190672 kb |
| Host | smart-ba01a5eb-c2e9-4ad0-9f3e-8e95751d2b92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046723330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4046723330 |
| Directory | /workspace/49.rv_timer_random/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random_reset.3051793742 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 22666562745 ps |
| CPU time | 34.13 seconds |
| Started | May 14 12:42:26 PM PDT 24 |
| Finished | May 14 12:43:02 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-2c7011f3-07bd-41f3-bd0e-a7db7b1fc1ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051793742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3051793742 |
| Directory | /workspace/49.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all.4200931494 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 64331802753 ps |
| CPU time | 833.13 seconds |
| Started | May 14 12:42:31 PM PDT 24 |
| Finished | May 14 12:56:26 PM PDT 24 |
| Peak memory | 190640 kb |
| Host | smart-3951555e-a473-4b69-9fc0-25e44da7d03a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200931494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all .4200931494 |
| Directory | /workspace/49.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.3433471821 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 115683342664 ps |
| CPU time | 800.33 seconds |
| Started | May 14 12:42:25 PM PDT 24 |
| Finished | May 14 12:55:47 PM PDT 24 |
| Peak memory | 207956 kb |
| Host | smart-7da865f6-f118-41ff-9a4a-c609632dcf95 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433471821 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.3433471821 |
| Directory | /workspace/49.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.36245 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 66514978641 ps |
| CPU time | 109.45 seconds |
| Started | May 14 12:41:53 PM PDT 24 |
| Finished | May 14 12:43:46 PM PDT 24 |
| Peak memory | 182512 kb |
| Host | smart-8d3fadf8-811f-4404-9c4c-f00df71ecddb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t imer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_ timer_cfg_update_on_fly.36245 |
| Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/5.rv_timer_disabled.536858362 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 227803155426 ps |
| CPU time | 187.29 seconds |
| Started | May 14 12:41:50 PM PDT 24 |
| Finished | May 14 12:45:00 PM PDT 24 |
| Peak memory | 182400 kb |
| Host | smart-c83a58d8-4c1a-45da-8e56-4fac4fce0c64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536858362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.536858362 |
| Directory | /workspace/5.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random.715793022 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 666774385728 ps |
| CPU time | 794.56 seconds |
| Started | May 14 12:41:53 PM PDT 24 |
| Finished | May 14 12:55:11 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-80f263a4-fef3-43bc-86d4-2c5dd54a1bdd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715793022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.715793022 |
| Directory | /workspace/5.rv_timer_random/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random_reset.806938888 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 31695465863 ps |
| CPU time | 40.05 seconds |
| Started | May 14 12:42:06 PM PDT 24 |
| Finished | May 14 12:42:49 PM PDT 24 |
| Peak memory | 190760 kb |
| Host | smart-7fd96410-01e8-4a98-ad01-da3d70002fde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806938888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.806938888 |
| Directory | /workspace/5.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all.2291976162 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 645283838033 ps |
| CPU time | 760.84 seconds |
| Started | May 14 12:42:09 PM PDT 24 |
| Finished | May 14 12:54:54 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-c16cdfdf-38ba-4c6e-bcae-b0192d7cceff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291976162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 2291976162 |
| Directory | /workspace/5.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/50.rv_timer_random.3837348808 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 283004912498 ps |
| CPU time | 348.7 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:48:35 PM PDT 24 |
| Peak memory | 190696 kb |
| Host | smart-7c367929-a3b0-4545-8aca-6f95caf883ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837348808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3837348808 |
| Directory | /workspace/50.rv_timer_random/latest |
| Test location | /workspace/coverage/default/51.rv_timer_random.262373567 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 118557169512 ps |
| CPU time | 1613.78 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 01:09:26 PM PDT 24 |
| Peak memory | 190652 kb |
| Host | smart-ad108839-22c1-40fd-b46d-709c7b9c39a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262373567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.262373567 |
| Directory | /workspace/51.rv_timer_random/latest |
| Test location | /workspace/coverage/default/53.rv_timer_random.3475918686 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 148100091225 ps |
| CPU time | 318.53 seconds |
| Started | May 14 12:42:26 PM PDT 24 |
| Finished | May 14 12:47:50 PM PDT 24 |
| Peak memory | 190620 kb |
| Host | smart-caf5ebd3-6cf7-41fc-833d-7cbffb0d686f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475918686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3475918686 |
| Directory | /workspace/53.rv_timer_random/latest |
| Test location | /workspace/coverage/default/54.rv_timer_random.2621697025 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 31801786292 ps |
| CPU time | 50.53 seconds |
| Started | May 14 12:42:28 PM PDT 24 |
| Finished | May 14 12:43:20 PM PDT 24 |
| Peak memory | 182376 kb |
| Host | smart-68aaab80-a66a-4933-8bc4-07be588a036b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621697025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2621697025 |
| Directory | /workspace/54.rv_timer_random/latest |
| Test location | /workspace/coverage/default/55.rv_timer_random.3517430976 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 51907620005 ps |
| CPU time | 96.23 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 12:44:08 PM PDT 24 |
| Peak memory | 190680 kb |
| Host | smart-253c4c05-d0e1-43f7-be2f-1f045c64b640 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517430976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3517430976 |
| Directory | /workspace/55.rv_timer_random/latest |
| Test location | /workspace/coverage/default/56.rv_timer_random.3370857786 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 173298817787 ps |
| CPU time | 1628.35 seconds |
| Started | May 14 12:42:31 PM PDT 24 |
| Finished | May 14 01:09:41 PM PDT 24 |
| Peak memory | 190680 kb |
| Host | smart-cf5e374f-5e8d-474b-a307-2636de593a6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370857786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3370857786 |
| Directory | /workspace/56.rv_timer_random/latest |
| Test location | /workspace/coverage/default/58.rv_timer_random.3471550901 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 200587159600 ps |
| CPU time | 94.25 seconds |
| Started | May 14 12:42:24 PM PDT 24 |
| Finished | May 14 12:43:59 PM PDT 24 |
| Peak memory | 182488 kb |
| Host | smart-53ce3532-1762-4688-91ac-3569f8f3d8ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471550901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3471550901 |
| Directory | /workspace/58.rv_timer_random/latest |
| Test location | /workspace/coverage/default/59.rv_timer_random.2578999097 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 235751041251 ps |
| CPU time | 110.2 seconds |
| Started | May 14 12:42:30 PM PDT 24 |
| Finished | May 14 12:44:22 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-587a085d-e190-412c-bb6f-05372617e790 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578999097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2578999097 |
| Directory | /workspace/59.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_disabled.2921162875 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 46939511865 ps |
| CPU time | 72.88 seconds |
| Started | May 14 12:41:44 PM PDT 24 |
| Finished | May 14 12:42:59 PM PDT 24 |
| Peak memory | 182908 kb |
| Host | smart-323d2b15-753f-456f-9e04-63cea46c0409 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921162875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2921162875 |
| Directory | /workspace/6.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random.1784456166 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 497209623913 ps |
| CPU time | 227.05 seconds |
| Started | May 14 12:41:55 PM PDT 24 |
| Finished | May 14 12:45:45 PM PDT 24 |
| Peak memory | 190768 kb |
| Host | smart-dfd8495a-aa5d-4446-9173-8cfbffe81dcd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784456166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1784456166 |
| Directory | /workspace/6.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random_reset.572546973 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 45371275894 ps |
| CPU time | 69.04 seconds |
| Started | May 14 12:41:57 PM PDT 24 |
| Finished | May 14 12:43:08 PM PDT 24 |
| Peak memory | 192884 kb |
| Host | smart-ba01b9ab-c923-451d-ad3c-bfb5346fdac3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572546973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.572546973 |
| Directory | /workspace/6.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all.4038156994 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 527962447127 ps |
| CPU time | 735.42 seconds |
| Started | May 14 12:41:58 PM PDT 24 |
| Finished | May 14 12:54:15 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-8a76a9cf-2fb8-401f-8174-a4f59b732808 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038156994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all. 4038156994 |
| Directory | /workspace/6.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/60.rv_timer_random.826912025 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 109568729367 ps |
| CPU time | 966.1 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:58:46 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-29fc61f4-851d-4ad3-8d48-ef584935286f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826912025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.826912025 |
| Directory | /workspace/60.rv_timer_random/latest |
| Test location | /workspace/coverage/default/61.rv_timer_random.2997077969 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 321982237352 ps |
| CPU time | 189.2 seconds |
| Started | May 14 12:42:59 PM PDT 24 |
| Finished | May 14 12:46:11 PM PDT 24 |
| Peak memory | 190820 kb |
| Host | smart-d1d18440-f505-46e2-8272-e80832fbb2f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997077969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2997077969 |
| Directory | /workspace/61.rv_timer_random/latest |
| Test location | /workspace/coverage/default/62.rv_timer_random.240957427 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 316928459175 ps |
| CPU time | 158.96 seconds |
| Started | May 14 12:42:51 PM PDT 24 |
| Finished | May 14 12:45:34 PM PDT 24 |
| Peak memory | 190692 kb |
| Host | smart-06d2cb43-0871-45d2-8c87-9158d579ee76 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240957427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.240957427 |
| Directory | /workspace/62.rv_timer_random/latest |
| Test location | /workspace/coverage/default/63.rv_timer_random.781701772 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 571776289328 ps |
| CPU time | 644.93 seconds |
| Started | May 14 12:42:46 PM PDT 24 |
| Finished | May 14 12:53:36 PM PDT 24 |
| Peak memory | 190664 kb |
| Host | smart-965c923b-065d-4cbb-9af8-5cde16cd0546 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781701772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.781701772 |
| Directory | /workspace/63.rv_timer_random/latest |
| Test location | /workspace/coverage/default/64.rv_timer_random.1288783741 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 277283065776 ps |
| CPU time | 349.38 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 12:48:28 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-00bdc2f7-5c03-47d4-ba99-9d7e8615b7d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288783741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1288783741 |
| Directory | /workspace/64.rv_timer_random/latest |
| Test location | /workspace/coverage/default/65.rv_timer_random.2764000185 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 10055712279 ps |
| CPU time | 23.14 seconds |
| Started | May 14 12:42:49 PM PDT 24 |
| Finished | May 14 12:43:17 PM PDT 24 |
| Peak memory | 182460 kb |
| Host | smart-f546503b-b589-4195-ba83-98957869f1f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764000185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2764000185 |
| Directory | /workspace/65.rv_timer_random/latest |
| Test location | /workspace/coverage/default/66.rv_timer_random.912368400 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 97277723730 ps |
| CPU time | 1256.25 seconds |
| Started | May 14 12:42:46 PM PDT 24 |
| Finished | May 14 01:03:48 PM PDT 24 |
| Peak memory | 190676 kb |
| Host | smart-4ec08fa8-e50b-444f-8390-9136782fc466 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912368400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.912368400 |
| Directory | /workspace/66.rv_timer_random/latest |
| Test location | /workspace/coverage/default/67.rv_timer_random.1542265361 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 67237291498 ps |
| CPU time | 100.05 seconds |
| Started | May 14 12:42:50 PM PDT 24 |
| Finished | May 14 12:44:35 PM PDT 24 |
| Peak memory | 190628 kb |
| Host | smart-4721e733-2f36-4a02-b1d2-41767133e09f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542265361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1542265361 |
| Directory | /workspace/67.rv_timer_random/latest |
| Test location | /workspace/coverage/default/68.rv_timer_random.1292128584 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 40408723213 ps |
| CPU time | 44.56 seconds |
| Started | May 14 12:42:27 PM PDT 24 |
| Finished | May 14 12:43:13 PM PDT 24 |
| Peak memory | 190664 kb |
| Host | smart-dc948c1c-e7b5-4ea7-8f59-63bcb4fdae45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292128584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1292128584 |
| Directory | /workspace/68.rv_timer_random/latest |
| Test location | /workspace/coverage/default/69.rv_timer_random.1719052906 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 718773875645 ps |
| CPU time | 188.12 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:45:43 PM PDT 24 |
| Peak memory | 190620 kb |
| Host | smart-2fc7ea92-5c7f-47c5-b883-16d8f61a7df1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719052906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1719052906 |
| Directory | /workspace/69.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2446509172 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1317136780937 ps |
| CPU time | 727.35 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:54:00 PM PDT 24 |
| Peak memory | 182480 kb |
| Host | smart-95df889a-b7f3-4cfa-a4d2-93a0a3c8d4a5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446509172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.2446509172 |
| Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_disabled.4032107721 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 75484426459 ps |
| CPU time | 59.6 seconds |
| Started | May 14 12:41:59 PM PDT 24 |
| Finished | May 14 12:43:00 PM PDT 24 |
| Peak memory | 182500 kb |
| Host | smart-f385a020-a37d-4ed5-9aaa-80bfec144633 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032107721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4032107721 |
| Directory | /workspace/7.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random.1165424871 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 101469950231 ps |
| CPU time | 191.93 seconds |
| Started | May 14 12:42:07 PM PDT 24 |
| Finished | May 14 12:45:22 PM PDT 24 |
| Peak memory | 182456 kb |
| Host | smart-11b9bd4c-97c9-4e2f-b98e-efeb7fe03f3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165424871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1165424871 |
| Directory | /workspace/7.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random_reset.1635579889 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 117105943039 ps |
| CPU time | 59.97 seconds |
| Started | May 14 12:41:48 PM PDT 24 |
| Finished | May 14 12:42:51 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-730fffa1-fd7b-43dd-b4f6-0e3506e490ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635579889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1635579889 |
| Directory | /workspace/7.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/70.rv_timer_random.382554517 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 704781504003 ps |
| CPU time | 1242.49 seconds |
| Started | May 14 12:42:58 PM PDT 24 |
| Finished | May 14 01:03:44 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-7555c39e-3ffb-42fd-a373-a58325734034 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382554517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.382554517 |
| Directory | /workspace/70.rv_timer_random/latest |
| Test location | /workspace/coverage/default/71.rv_timer_random.3843690574 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 33547005175 ps |
| CPU time | 31.52 seconds |
| Started | May 14 12:42:39 PM PDT 24 |
| Finished | May 14 12:43:14 PM PDT 24 |
| Peak memory | 190700 kb |
| Host | smart-a5fa460a-0868-467f-8ad9-a423bc52837d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843690574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3843690574 |
| Directory | /workspace/71.rv_timer_random/latest |
| Test location | /workspace/coverage/default/72.rv_timer_random.3532323871 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 582724945289 ps |
| CPU time | 504.93 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:51:12 PM PDT 24 |
| Peak memory | 190744 kb |
| Host | smart-4a8ed125-67e0-4ead-9d0a-2f5f04cc5d66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532323871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3532323871 |
| Directory | /workspace/72.rv_timer_random/latest |
| Test location | /workspace/coverage/default/73.rv_timer_random.109266052 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 341138470982 ps |
| CPU time | 765.44 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:55:27 PM PDT 24 |
| Peak memory | 190656 kb |
| Host | smart-95356086-31e7-46cf-9a99-b46c38feeda0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109266052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.109266052 |
| Directory | /workspace/73.rv_timer_random/latest |
| Test location | /workspace/coverage/default/74.rv_timer_random.4040744831 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 31974883047 ps |
| CPU time | 25.16 seconds |
| Started | May 14 12:42:36 PM PDT 24 |
| Finished | May 14 12:43:03 PM PDT 24 |
| Peak memory | 182440 kb |
| Host | smart-dd693c06-fc9a-433f-958e-b8102e8b0715 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040744831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4040744831 |
| Directory | /workspace/74.rv_timer_random/latest |
| Test location | /workspace/coverage/default/75.rv_timer_random.1785699275 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 106108607398 ps |
| CPU time | 192.26 seconds |
| Started | May 14 12:42:42 PM PDT 24 |
| Finished | May 14 12:45:58 PM PDT 24 |
| Peak memory | 190668 kb |
| Host | smart-2837539e-77cc-4e34-a027-db1939c3b8b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785699275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1785699275 |
| Directory | /workspace/75.rv_timer_random/latest |
| Test location | /workspace/coverage/default/76.rv_timer_random.4106645137 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 914439445689 ps |
| CPU time | 834.6 seconds |
| Started | May 14 12:42:34 PM PDT 24 |
| Finished | May 14 12:56:30 PM PDT 24 |
| Peak memory | 190640 kb |
| Host | smart-146e35d0-993b-47ed-9b0a-19b54b3099b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106645137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4106645137 |
| Directory | /workspace/76.rv_timer_random/latest |
| Test location | /workspace/coverage/default/77.rv_timer_random.661109251 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 87984420578 ps |
| CPU time | 494.66 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 12:50:53 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-69db7da8-b1ba-4989-ba06-7de82a4a48de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661109251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.661109251 |
| Directory | /workspace/77.rv_timer_random/latest |
| Test location | /workspace/coverage/default/78.rv_timer_random.668328338 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 36728871537 ps |
| CPU time | 59.03 seconds |
| Started | May 14 12:42:39 PM PDT 24 |
| Finished | May 14 12:43:41 PM PDT 24 |
| Peak memory | 191104 kb |
| Host | smart-b4bd2626-d76f-4a1e-83cc-754d0026c7cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668328338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.668328338 |
| Directory | /workspace/78.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.4136727826 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 60803173728 ps |
| CPU time | 108.86 seconds |
| Started | May 14 12:41:49 PM PDT 24 |
| Finished | May 14 12:43:41 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-1dac8fb2-c519-4243-a1ec-50243a702292 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136727826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.4136727826 |
| Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/8.rv_timer_disabled.869963905 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 343389294241 ps |
| CPU time | 273.09 seconds |
| Started | May 14 12:41:50 PM PDT 24 |
| Finished | May 14 12:46:26 PM PDT 24 |
| Peak memory | 182444 kb |
| Host | smart-fb8cbf28-219c-4ea7-9ded-a8c8b4b10549 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869963905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.869963905 |
| Directory | /workspace/8.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random_reset.791002222 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 32759623809 ps |
| CPU time | 577.63 seconds |
| Started | May 14 12:42:01 PM PDT 24 |
| Finished | May 14 12:51:42 PM PDT 24 |
| Peak memory | 193788 kb |
| Host | smart-156d2868-ccfb-46dc-9b30-3e8eef3f9a52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791002222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.791002222 |
| Directory | /workspace/8.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all.2793150980 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 245317916560 ps |
| CPU time | 381.7 seconds |
| Started | May 14 12:42:06 PM PDT 24 |
| Finished | May 14 12:48:31 PM PDT 24 |
| Peak memory | 194212 kb |
| Host | smart-e8ac7d92-9477-479a-b861-dbc1fc70f985 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793150980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 2793150980 |
| Directory | /workspace/8.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/80.rv_timer_random.717089089 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 206701090434 ps |
| CPU time | 226.95 seconds |
| Started | May 14 12:42:33 PM PDT 24 |
| Finished | May 14 12:46:22 PM PDT 24 |
| Peak memory | 190644 kb |
| Host | smart-db9cba5e-afd7-427b-aa90-3681e9978673 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717089089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.717089089 |
| Directory | /workspace/80.rv_timer_random/latest |
| Test location | /workspace/coverage/default/83.rv_timer_random.1643526151 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 146531066291 ps |
| CPU time | 111.34 seconds |
| Started | May 14 12:42:48 PM PDT 24 |
| Finished | May 14 12:44:45 PM PDT 24 |
| Peak memory | 194148 kb |
| Host | smart-5b0a7f7b-03d1-4563-a693-8717e1ebe228 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643526151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1643526151 |
| Directory | /workspace/83.rv_timer_random/latest |
| Test location | /workspace/coverage/default/84.rv_timer_random.4148649012 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 136502646941 ps |
| CPU time | 517.7 seconds |
| Started | May 14 12:42:29 PM PDT 24 |
| Finished | May 14 12:51:08 PM PDT 24 |
| Peak memory | 182508 kb |
| Host | smart-7d0e72c9-3cd7-496f-8788-78c4187e93a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148649012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4148649012 |
| Directory | /workspace/84.rv_timer_random/latest |
| Test location | /workspace/coverage/default/85.rv_timer_random.2641821787 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 14551591319 ps |
| CPU time | 28.99 seconds |
| Started | May 14 12:42:41 PM PDT 24 |
| Finished | May 14 12:43:14 PM PDT 24 |
| Peak memory | 182476 kb |
| Host | smart-18a336b4-5cf1-4ccc-a31c-31c43490e9eb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641821787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2641821787 |
| Directory | /workspace/85.rv_timer_random/latest |
| Test location | /workspace/coverage/default/86.rv_timer_random.435978429 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 40619554119 ps |
| CPU time | 32.92 seconds |
| Started | May 14 12:42:57 PM PDT 24 |
| Finished | May 14 12:43:33 PM PDT 24 |
| Peak memory | 191372 kb |
| Host | smart-0deabc49-fb79-4571-9d05-bfe7c637df5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435978429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.435978429 |
| Directory | /workspace/86.rv_timer_random/latest |
| Test location | /workspace/coverage/default/87.rv_timer_random.511464892 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 79826426111 ps |
| CPU time | 348.81 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 12:48:27 PM PDT 24 |
| Peak memory | 190688 kb |
| Host | smart-65235b9c-0935-4154-bd76-4059172894fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511464892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.511464892 |
| Directory | /workspace/87.rv_timer_random/latest |
| Test location | /workspace/coverage/default/88.rv_timer_random.1338598780 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 55524374810 ps |
| CPU time | 83.27 seconds |
| Started | May 14 12:42:29 PM PDT 24 |
| Finished | May 14 12:43:53 PM PDT 24 |
| Peak memory | 190768 kb |
| Host | smart-f5adea74-044c-45b1-bf5b-f9e066e1cc99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338598780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1338598780 |
| Directory | /workspace/88.rv_timer_random/latest |
| Test location | /workspace/coverage/default/89.rv_timer_random.2411381538 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 101811262435 ps |
| CPU time | 276.53 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:47:10 PM PDT 24 |
| Peak memory | 190620 kb |
| Host | smart-6ca0f86e-7453-4f18-a294-07630bf60a51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411381538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2411381538 |
| Directory | /workspace/89.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.124127035 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1440113140964 ps |
| CPU time | 622.08 seconds |
| Started | May 14 12:41:56 PM PDT 24 |
| Finished | May 14 12:52:21 PM PDT 24 |
| Peak memory | 182540 kb |
| Host | smart-09a12f31-a579-4967-b205-9e9e4ab91496 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124127035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .rv_timer_cfg_update_on_fly.124127035 |
| Directory | /workspace/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/9.rv_timer_disabled.2605217642 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 36614993644 ps |
| CPU time | 55.66 seconds |
| Started | May 14 12:42:10 PM PDT 24 |
| Finished | May 14 12:43:08 PM PDT 24 |
| Peak memory | 182500 kb |
| Host | smart-ccee8483-648b-4d42-a10d-01c26daa6e8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605217642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2605217642 |
| Directory | /workspace/9.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random_reset.359276357 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 8861785662 ps |
| CPU time | 16.51 seconds |
| Started | May 14 12:41:57 PM PDT 24 |
| Finished | May 14 12:42:16 PM PDT 24 |
| Peak memory | 193948 kb |
| Host | smart-9a2b4bb1-7433-4ea3-90d3-a186c36c8449 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359276357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.359276357 |
| Directory | /workspace/9.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all.1637965412 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 165054107573 ps |
| CPU time | 148.13 seconds |
| Started | May 14 12:41:53 PM PDT 24 |
| Finished | May 14 12:44:25 PM PDT 24 |
| Peak memory | 182424 kb |
| Host | smart-afdb4b11-6109-4336-8b1d-0ada60dd3158 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637965412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 1637965412 |
| Directory | /workspace/9.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/90.rv_timer_random.1485325702 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 148067286259 ps |
| CPU time | 344.12 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 12:48:23 PM PDT 24 |
| Peak memory | 190648 kb |
| Host | smart-03ed69d1-838f-44e7-b972-5ee86e70286c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485325702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1485325702 |
| Directory | /workspace/90.rv_timer_random/latest |
| Test location | /workspace/coverage/default/92.rv_timer_random.930900783 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 172477292095 ps |
| CPU time | 757.2 seconds |
| Started | May 14 12:42:32 PM PDT 24 |
| Finished | May 14 12:55:11 PM PDT 24 |
| Peak memory | 190744 kb |
| Host | smart-0489e35f-6f6a-4a19-81ed-64f1503263a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930900783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.930900783 |
| Directory | /workspace/92.rv_timer_random/latest |
| Test location | /workspace/coverage/default/93.rv_timer_random.2036639687 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 187665638536 ps |
| CPU time | 588.95 seconds |
| Started | May 14 12:42:37 PM PDT 24 |
| Finished | May 14 12:52:27 PM PDT 24 |
| Peak memory | 190652 kb |
| Host | smart-ba38033c-8f60-47b7-9418-3db5fb17f610 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036639687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2036639687 |
| Directory | /workspace/93.rv_timer_random/latest |
| Test location | /workspace/coverage/default/94.rv_timer_random.2376828535 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 589632916069 ps |
| CPU time | 636.05 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:53:17 PM PDT 24 |
| Peak memory | 190768 kb |
| Host | smart-533788f8-c3b1-463b-a9b1-31ebd35e87c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376828535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2376828535 |
| Directory | /workspace/94.rv_timer_random/latest |
| Test location | /workspace/coverage/default/96.rv_timer_random.969618374 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 98353125287 ps |
| CPU time | 389.93 seconds |
| Started | May 14 12:42:44 PM PDT 24 |
| Finished | May 14 12:49:19 PM PDT 24 |
| Peak memory | 190676 kb |
| Host | smart-ab88f5a1-60b3-4e42-8f61-88c88446efde |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969618374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.969618374 |
| Directory | /workspace/96.rv_timer_random/latest |
| Test location | /workspace/coverage/default/98.rv_timer_random.4265923894 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 171585377904 ps |
| CPU time | 96.55 seconds |
| Started | May 14 12:42:38 PM PDT 24 |
| Finished | May 14 12:44:17 PM PDT 24 |
| Peak memory | 190684 kb |
| Host | smart-122c5d61-7534-4db0-b1ce-a61566827594 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265923894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4265923894 |
| Directory | /workspace/98.rv_timer_random/latest |
| Test location | /workspace/coverage/default/99.rv_timer_random.4230905472 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 107057165523 ps |
| CPU time | 55.14 seconds |
| Started | May 14 12:42:43 PM PDT 24 |
| Finished | May 14 12:43:42 PM PDT 24 |
| Peak memory | 182560 kb |
| Host | smart-614ba507-8f88-4b32-afa5-dcfd7fb207ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230905472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4230905472 |
| Directory | /workspace/99.rv_timer_random/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |