Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.51 99.36 98.73 100.00 100.00 100.00 98.98


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T505 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2088157944 May 16 12:41:10 PM PDT 24 May 16 12:41:13 PM PDT 24 93382267 ps
T506 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2124518363 May 16 12:40:55 PM PDT 24 May 16 12:41:01 PM PDT 24 57281474 ps
T507 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1830492785 May 16 12:41:21 PM PDT 24 May 16 12:41:27 PM PDT 24 139912970 ps
T95 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2883814525 May 16 12:40:57 PM PDT 24 May 16 12:41:02 PM PDT 24 21751662 ps
T508 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2910347784 May 16 12:41:20 PM PDT 24 May 16 12:41:25 PM PDT 24 58989067 ps
T509 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2176435979 May 16 12:40:54 PM PDT 24 May 16 12:40:59 PM PDT 24 30906140 ps
T510 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3411647515 May 16 12:41:14 PM PDT 24 May 16 12:41:17 PM PDT 24 23864859 ps
T511 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3878671843 May 16 12:41:01 PM PDT 24 May 16 12:41:06 PM PDT 24 36158851 ps
T512 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.586451075 May 16 12:40:49 PM PDT 24 May 16 12:40:53 PM PDT 24 12240077 ps
T513 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3084396368 May 16 12:41:35 PM PDT 24 May 16 12:41:42 PM PDT 24 15437587 ps
T514 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.467541500 May 16 12:41:05 PM PDT 24 May 16 12:41:09 PM PDT 24 13902840 ps
T87 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1129210479 May 16 12:41:31 PM PDT 24 May 16 12:41:37 PM PDT 24 28096220 ps
T515 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2940919819 May 16 12:40:51 PM PDT 24 May 16 12:41:01 PM PDT 24 13800278 ps
T516 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2528478511 May 16 12:40:48 PM PDT 24 May 16 12:40:52 PM PDT 24 73411646 ps
T517 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1785592321 May 16 12:41:13 PM PDT 24 May 16 12:41:15 PM PDT 24 52537434 ps
T518 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2930578715 May 16 12:40:54 PM PDT 24 May 16 12:40:59 PM PDT 24 13348723 ps
T519 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4263793892 May 16 12:40:59 PM PDT 24 May 16 12:41:05 PM PDT 24 285119873 ps
T520 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3109663753 May 16 12:41:00 PM PDT 24 May 16 12:41:05 PM PDT 24 44897479 ps
T521 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2228474842 May 16 12:40:49 PM PDT 24 May 16 12:40:56 PM PDT 24 820548432 ps
T522 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2232493539 May 16 12:41:11 PM PDT 24 May 16 12:41:14 PM PDT 24 22077575 ps
T523 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4117322926 May 16 12:40:56 PM PDT 24 May 16 12:41:04 PM PDT 24 153638546 ps
T524 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4280066011 May 16 12:41:02 PM PDT 24 May 16 12:41:06 PM PDT 24 64977187 ps
T525 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3316605494 May 16 12:41:06 PM PDT 24 May 16 12:41:11 PM PDT 24 181043859 ps
T526 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1775330455 May 16 12:40:58 PM PDT 24 May 16 12:41:04 PM PDT 24 185219238 ps
T527 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1574147558 May 16 12:41:19 PM PDT 24 May 16 12:41:23 PM PDT 24 13806492 ps
T528 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1671842905 May 16 12:41:17 PM PDT 24 May 16 12:41:20 PM PDT 24 15915131 ps
T529 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2365305880 May 16 12:41:28 PM PDT 24 May 16 12:41:35 PM PDT 24 755596836 ps
T530 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2621562265 May 16 12:41:31 PM PDT 24 May 16 12:41:38 PM PDT 24 28766830 ps
T531 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4203922099 May 16 12:41:15 PM PDT 24 May 16 12:41:19 PM PDT 24 43442590 ps
T532 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3051728169 May 16 12:41:00 PM PDT 24 May 16 12:41:05 PM PDT 24 27606881 ps
T533 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1893244418 May 16 12:41:23 PM PDT 24 May 16 12:41:30 PM PDT 24 46065554 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.694761788 May 16 12:40:54 PM PDT 24 May 16 12:41:00 PM PDT 24 35894621 ps
T535 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2606036450 May 16 12:41:14 PM PDT 24 May 16 12:41:17 PM PDT 24 11081181 ps
T536 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.510511827 May 16 12:41:07 PM PDT 24 May 16 12:41:10 PM PDT 24 29593817 ps
T537 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3656999821 May 16 12:41:07 PM PDT 24 May 16 12:41:11 PM PDT 24 28664771 ps
T538 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3240107221 May 16 12:40:56 PM PDT 24 May 16 12:41:06 PM PDT 24 39040876 ps
T539 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2879730654 May 16 12:41:26 PM PDT 24 May 16 12:41:33 PM PDT 24 12710525 ps
T88 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.4084577782 May 16 12:40:57 PM PDT 24 May 16 12:41:03 PM PDT 24 62922769 ps
T540 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.866414129 May 16 12:40:50 PM PDT 24 May 16 12:40:54 PM PDT 24 17966119 ps
T541 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2950539360 May 16 12:41:18 PM PDT 24 May 16 12:41:22 PM PDT 24 11958982 ps
T542 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1325509655 May 16 12:41:09 PM PDT 24 May 16 12:41:13 PM PDT 24 130494493 ps
T543 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3174842593 May 16 12:40:54 PM PDT 24 May 16 12:41:00 PM PDT 24 18287157 ps
T544 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3580639006 May 16 12:40:57 PM PDT 24 May 16 12:41:03 PM PDT 24 861200667 ps
T545 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2653674186 May 16 12:40:53 PM PDT 24 May 16 12:41:01 PM PDT 24 527287017 ps
T546 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1205045169 May 16 12:41:17 PM PDT 24 May 16 12:41:22 PM PDT 24 119668060 ps
T547 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3912757077 May 16 12:41:07 PM PDT 24 May 16 12:41:12 PM PDT 24 335679323 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.865469210 May 16 12:40:50 PM PDT 24 May 16 12:40:54 PM PDT 24 12818854 ps
T549 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2324920180 May 16 12:41:04 PM PDT 24 May 16 12:41:08 PM PDT 24 124388024 ps
T550 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2589876165 May 16 12:41:13 PM PDT 24 May 16 12:41:16 PM PDT 24 43005142 ps
T551 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1268664887 May 16 12:41:05 PM PDT 24 May 16 12:41:09 PM PDT 24 164435004 ps
T552 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4130374692 May 16 12:40:56 PM PDT 24 May 16 12:41:02 PM PDT 24 163774785 ps
T553 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3340949576 May 16 12:40:52 PM PDT 24 May 16 12:40:57 PM PDT 24 50102723 ps
T554 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2407110588 May 16 12:41:20 PM PDT 24 May 16 12:41:25 PM PDT 24 28423080 ps
T555 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2181851372 May 16 12:41:30 PM PDT 24 May 16 12:41:37 PM PDT 24 33707147 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4038269583 May 16 12:40:53 PM PDT 24 May 16 12:40:59 PM PDT 24 134358174 ps
T556 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.66775978 May 16 12:40:55 PM PDT 24 May 16 12:41:01 PM PDT 24 15129339 ps
T557 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2699386534 May 16 12:41:11 PM PDT 24 May 16 12:41:14 PM PDT 24 36126318 ps
T558 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.369998503 May 16 12:41:04 PM PDT 24 May 16 12:41:08 PM PDT 24 19881800 ps
T559 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2892581948 May 16 12:41:24 PM PDT 24 May 16 12:41:31 PM PDT 24 80622212 ps
T560 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.337769212 May 16 12:40:54 PM PDT 24 May 16 12:41:00 PM PDT 24 157985993 ps
T561 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.227895286 May 16 12:40:50 PM PDT 24 May 16 12:40:54 PM PDT 24 27460289 ps
T562 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.342993828 May 16 12:40:55 PM PDT 24 May 16 12:41:01 PM PDT 24 22434909 ps
T563 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.241613518 May 16 12:40:50 PM PDT 24 May 16 12:40:56 PM PDT 24 94530386 ps
T564 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2346884533 May 16 12:41:14 PM PDT 24 May 16 12:41:17 PM PDT 24 33320804 ps
T565 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3877782549 May 16 12:41:27 PM PDT 24 May 16 12:41:34 PM PDT 24 11940673 ps
T566 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.957803556 May 16 12:40:51 PM PDT 24 May 16 12:40:56 PM PDT 24 42381623 ps
T567 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2613462654 May 16 12:41:19 PM PDT 24 May 16 12:41:25 PM PDT 24 61230911 ps
T568 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3014240921 May 16 12:40:50 PM PDT 24 May 16 12:40:55 PM PDT 24 211032375 ps
T569 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.531151001 May 16 12:40:50 PM PDT 24 May 16 12:40:54 PM PDT 24 40617156 ps
T570 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3583957339 May 16 12:41:14 PM PDT 24 May 16 12:41:17 PM PDT 24 42754693 ps
T571 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3989382413 May 16 12:40:55 PM PDT 24 May 16 12:41:01 PM PDT 24 154866754 ps
T572 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1614628543 May 16 12:40:42 PM PDT 24 May 16 12:40:44 PM PDT 24 20142997 ps
T573 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4184297041 May 16 12:41:23 PM PDT 24 May 16 12:41:30 PM PDT 24 49297280 ps
T574 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3277399722 May 16 12:41:00 PM PDT 24 May 16 12:41:05 PM PDT 24 23385077 ps
T575 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3392792082 May 16 12:41:01 PM PDT 24 May 16 12:41:06 PM PDT 24 30461832 ps
T576 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1342022429 May 16 12:41:03 PM PDT 24 May 16 12:41:08 PM PDT 24 16406088 ps
T577 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1640579604 May 16 12:40:53 PM PDT 24 May 16 12:40:59 PM PDT 24 30131660 ps
T578 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3697560531 May 16 12:40:53 PM PDT 24 May 16 12:40:58 PM PDT 24 65583546 ps
T579 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2990600410 May 16 12:40:52 PM PDT 24 May 16 12:40:57 PM PDT 24 35536934 ps
T580 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.512122416 May 16 12:41:01 PM PDT 24 May 16 12:41:06 PM PDT 24 209059651 ps
T581 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1003855092 May 16 12:40:55 PM PDT 24 May 16 12:41:02 PM PDT 24 231853565 ps

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1462084550
Short name T4
Test name
Test status
Simulation time 43355120588 ps
CPU time 244.45 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 12:45:47 PM PDT 24
Peak memory 205412 kb
Host smart-dc4f5223-17b8-4810-b6bb-bc7a710d995b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462084550 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1462084550
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.rv_timer_random.963325507
Short name T9
Test name
Test status
Simulation time 594123656996 ps
CPU time 329.25 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:47:48 PM PDT 24
Peak memory 190844 kb
Host smart-da8b1474-49dd-4726-a179-962196b29623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963325507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.963325507
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1428010155
Short name T114
Test name
Test status
Simulation time 2277618032651 ps
CPU time 1238.83 seconds
Started May 16 12:41:54 PM PDT 24
Finished May 16 01:02:41 PM PDT 24
Peak memory 190708 kb
Host smart-e6a65dc3-3275-40b2-8f7f-95b08960b96f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428010155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1428010155
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2537073871
Short name T28
Test name
Test status
Simulation time 443954264 ps
CPU time 1.34 seconds
Started May 16 12:40:54 PM PDT 24
Finished May 16 12:41:01 PM PDT 24
Peak memory 195612 kb
Host smart-3caacaca-a348-460f-b73a-1b323e662793
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537073871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2537073871
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.630719684
Short name T59
Test name
Test status
Simulation time 560522050132 ps
CPU time 1237.9 seconds
Started May 16 12:41:33 PM PDT 24
Finished May 16 01:02:18 PM PDT 24
Peak memory 190784 kb
Host smart-2816a633-f2ea-417e-ad94-a16d7ba01ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630719684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
630719684
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2096848933
Short name T79
Test name
Test status
Simulation time 15365466 ps
CPU time 0.58 seconds
Started May 16 12:41:08 PM PDT 24
Finished May 16 12:41:12 PM PDT 24
Peak memory 182708 kb
Host smart-dfc0a539-3a32-41f9-8105-ad37b5d03cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096848933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2096848933
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3973202712
Short name T172
Test name
Test status
Simulation time 578044053004 ps
CPU time 1197.58 seconds
Started May 16 12:41:38 PM PDT 24
Finished May 16 01:01:43 PM PDT 24
Peak memory 190792 kb
Host smart-e49fe2a5-3a30-4fb3-ad24-24855b443c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973202712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3973202712
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/75.rv_timer_random.1533815865
Short name T69
Test name
Test status
Simulation time 611392827541 ps
CPU time 485.02 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:50:02 PM PDT 24
Peak memory 190768 kb
Host smart-44c9d286-3587-4872-9a71-8d56a25d21a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533815865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1533815865
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4033139090
Short name T130
Test name
Test status
Simulation time 1619356217747 ps
CPU time 1236.4 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 01:02:31 PM PDT 24
Peak memory 190736 kb
Host smart-2fe07b1b-40da-45f0-b762-95ca0eeddae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033139090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4033139090
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1184494997
Short name T70
Test name
Test status
Simulation time 243646470551 ps
CPU time 890.33 seconds
Started May 16 12:41:42 PM PDT 24
Finished May 16 12:56:39 PM PDT 24
Peak memory 195472 kb
Host smart-1d297764-1f4f-4df5-96e2-5ee364d1dc3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184494997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1184494997
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1336608904
Short name T152
Test name
Test status
Simulation time 543287089404 ps
CPU time 1067.13 seconds
Started May 16 12:41:43 PM PDT 24
Finished May 16 12:59:37 PM PDT 24
Peak memory 195444 kb
Host smart-aa810b36-ed56-4b55-b935-60bbaf58569b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336608904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1336608904
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3379211358
Short name T161
Test name
Test status
Simulation time 323870826794 ps
CPU time 1287.09 seconds
Started May 16 12:41:43 PM PDT 24
Finished May 16 01:03:17 PM PDT 24
Peak memory 190700 kb
Host smart-d63d9c06-5315-4581-967c-c435f101350d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379211358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3379211358
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.390442293
Short name T244
Test name
Test status
Simulation time 1362458271413 ps
CPU time 1376.74 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 01:04:20 PM PDT 24
Peak memory 190796 kb
Host smart-6f4bb3a5-d9d0-4be8-87e5-8d4a0dd547c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390442293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.390442293
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.170290813
Short name T60
Test name
Test status
Simulation time 582044952814 ps
CPU time 791.95 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:55:07 PM PDT 24
Peak memory 190788 kb
Host smart-0c8aa7be-56c2-478a-979d-1cd15d146a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170290813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
170290813
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1081803325
Short name T14
Test name
Test status
Simulation time 293601503 ps
CPU time 0.87 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:41:29 PM PDT 24
Peak memory 213132 kb
Host smart-42a9ee77-978a-47b0-baf9-873f657387c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081803325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1081803325
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2722782498
Short name T150
Test name
Test status
Simulation time 1023809015377 ps
CPU time 883.11 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:56:07 PM PDT 24
Peak memory 190796 kb
Host smart-e74c74e0-ba47-4bd7-bd0e-d568e653e5e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722782498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2722782498
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/144.rv_timer_random.975254232
Short name T113
Test name
Test status
Simulation time 539918252907 ps
CPU time 298.92 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:47:18 PM PDT 24
Peak memory 193232 kb
Host smart-0de1ef8f-d2e9-4b64-992d-a72bc2accbf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975254232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.975254232
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3195443622
Short name T224
Test name
Test status
Simulation time 1740998332008 ps
CPU time 2431.6 seconds
Started May 16 12:41:45 PM PDT 24
Finished May 16 01:22:24 PM PDT 24
Peak memory 190784 kb
Host smart-e492f9b3-ca73-4b2e-9f7a-cb9e3a406228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195443622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3195443622
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3990051796
Short name T185
Test name
Test status
Simulation time 280327039977 ps
CPU time 1753.09 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 01:10:39 PM PDT 24
Peak memory 190540 kb
Host smart-f8992cf6-b16b-4d10-8e6a-225368768879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990051796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3990051796
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_random.1617736490
Short name T221
Test name
Test status
Simulation time 752427594673 ps
CPU time 381.97 seconds
Started May 16 12:41:29 PM PDT 24
Finished May 16 12:47:58 PM PDT 24
Peak memory 193272 kb
Host smart-9b3ea55b-1794-4052-bb97-f59d53e100a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617736490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1617736490
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.5728082
Short name T61
Test name
Test status
Simulation time 717633517733 ps
CPU time 619.28 seconds
Started May 16 12:41:26 PM PDT 24
Finished May 16 12:51:51 PM PDT 24
Peak memory 195608 kb
Host smart-a07438a2-21d4-45d1-aeb8-7fff172c2b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5728082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.5728082
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.735922006
Short name T168
Test name
Test status
Simulation time 708746022908 ps
CPU time 1054.7 seconds
Started May 16 12:42:05 PM PDT 24
Finished May 16 12:59:46 PM PDT 24
Peak memory 194756 kb
Host smart-3506899f-dc91-4c3d-8442-9cc8fd414dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735922006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
735922006
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/185.rv_timer_random.944003037
Short name T235
Test name
Test status
Simulation time 493378066911 ps
CPU time 572.33 seconds
Started May 16 12:42:17 PM PDT 24
Finished May 16 12:51:53 PM PDT 24
Peak memory 190696 kb
Host smart-759831a3-5b03-4f13-8387-cff5e0e37d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944003037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.944003037
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1946407752
Short name T62
Test name
Test status
Simulation time 355105471182 ps
CPU time 1140.41 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 01:00:24 PM PDT 24
Peak memory 190712 kb
Host smart-ee4d8e88-e35f-4588-b01b-00dd54a79ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946407752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1946407752
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.4010055306
Short name T104
Test name
Test status
Simulation time 1391823213231 ps
CPU time 607.75 seconds
Started May 16 12:42:04 PM PDT 24
Finished May 16 12:52:17 PM PDT 24
Peak memory 190792 kb
Host smart-140df81d-4196-42c9-8e32-22e60c422277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010055306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.4010055306
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.554407290
Short name T112
Test name
Test status
Simulation time 136483369053 ps
CPU time 1114.82 seconds
Started May 16 12:41:55 PM PDT 24
Finished May 16 01:00:37 PM PDT 24
Peak memory 190696 kb
Host smart-b8ae2c33-b754-4662-9fac-9a5ad0000442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554407290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.554407290
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.3254418317
Short name T205
Test name
Test status
Simulation time 98193306550 ps
CPU time 193.91 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:44:40 PM PDT 24
Peak memory 190676 kb
Host smart-b113dd1c-afc5-44f8-a97b-79e880a488e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254418317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3254418317
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.686909127
Short name T42
Test name
Test status
Simulation time 98034741066 ps
CPU time 174.82 seconds
Started May 16 12:42:05 PM PDT 24
Finished May 16 12:45:06 PM PDT 24
Peak memory 190772 kb
Host smart-27b933ef-023d-4fd7-bc8b-f6300f727bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686909127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.686909127
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.989024636
Short name T179
Test name
Test status
Simulation time 381557216233 ps
CPU time 508.69 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 12:50:11 PM PDT 24
Peak memory 190772 kb
Host smart-8ddef1a4-436c-4317-9ef4-8aec6776dfa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989024636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
989024636
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.2735567601
Short name T202
Test name
Test status
Simulation time 602643523117 ps
CPU time 354.65 seconds
Started May 16 12:42:11 PM PDT 24
Finished May 16 12:48:09 PM PDT 24
Peak memory 190748 kb
Host smart-608b6c06-b2d0-4b77-8426-c2ea94840672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735567601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2735567601
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1999876189
Short name T155
Test name
Test status
Simulation time 153686257467 ps
CPU time 263.88 seconds
Started May 16 12:41:45 PM PDT 24
Finished May 16 12:46:15 PM PDT 24
Peak memory 190784 kb
Host smart-816886b8-2921-4f67-83c4-107f43ec5a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999876189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1999876189
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4038269583
Short name T89
Test name
Test status
Simulation time 134358174 ps
CPU time 0.76 seconds
Started May 16 12:40:53 PM PDT 24
Finished May 16 12:40:59 PM PDT 24
Peak memory 192620 kb
Host smart-e9bc4fa6-2225-450c-8768-c6b7cc838990
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038269583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4038269583
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/100.rv_timer_random.2639714628
Short name T105
Test name
Test status
Simulation time 837952563343 ps
CPU time 729.84 seconds
Started May 16 12:42:07 PM PDT 24
Finished May 16 12:54:22 PM PDT 24
Peak memory 190684 kb
Host smart-f4bce525-4b37-4ea7-9f3d-63aaabaf000c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639714628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2639714628
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2500552853
Short name T218
Test name
Test status
Simulation time 2474828587578 ps
CPU time 798.69 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:55:39 PM PDT 24
Peak memory 190696 kb
Host smart-445e9543-deb3-4a65-bdba-58d45a212cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500552853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2500552853
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.1421045200
Short name T163
Test name
Test status
Simulation time 556626782301 ps
CPU time 531.22 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:51:08 PM PDT 24
Peak memory 190788 kb
Host smart-b84deaac-d469-45ef-ad41-7580473bde3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421045200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1421045200
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3538917499
Short name T222
Test name
Test status
Simulation time 343252336421 ps
CPU time 302.45 seconds
Started May 16 12:42:19 PM PDT 24
Finished May 16 12:47:25 PM PDT 24
Peak memory 190772 kb
Host smart-05d5c5df-1b59-496d-b4e7-2d95ffeb36d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538917499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3538917499
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.252230491
Short name T338
Test name
Test status
Simulation time 73619856573 ps
CPU time 538.17 seconds
Started May 16 12:41:40 PM PDT 24
Finished May 16 12:50:45 PM PDT 24
Peak memory 182688 kb
Host smart-3c48ac17-22f2-4445-b07b-4d6a46c0df53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252230491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.252230491
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.3836758162
Short name T138
Test name
Test status
Simulation time 686280245232 ps
CPU time 341.28 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:47:39 PM PDT 24
Peak memory 190696 kb
Host smart-c7eaef8f-cdf8-4475-8f00-adb9147a24e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836758162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3836758162
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1514073765
Short name T173
Test name
Test status
Simulation time 162391170183 ps
CPU time 1465.27 seconds
Started May 16 12:43:05 PM PDT 24
Finished May 16 01:07:37 PM PDT 24
Peak memory 192848 kb
Host smart-d4fb8116-9ddc-46b3-9aa9-741b5c1475ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514073765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1514073765
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1756209279
Short name T195
Test name
Test status
Simulation time 556557246493 ps
CPU time 780.49 seconds
Started May 16 12:42:05 PM PDT 24
Finished May 16 12:55:11 PM PDT 24
Peak memory 190732 kb
Host smart-cbefdc01-544c-46ef-b9b9-3d401555fceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756209279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1756209279
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.152595309
Short name T177
Test name
Test status
Simulation time 413156535708 ps
CPU time 361.58 seconds
Started May 16 12:42:02 PM PDT 24
Finished May 16 12:48:09 PM PDT 24
Peak memory 193300 kb
Host smart-c7ee1b1d-c7e3-4ef9-8a71-5d4961613e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152595309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.152595309
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.779163626
Short name T268
Test name
Test status
Simulation time 369611447510 ps
CPU time 211.83 seconds
Started May 16 12:42:01 PM PDT 24
Finished May 16 12:45:39 PM PDT 24
Peak memory 190792 kb
Host smart-f4f59b04-8d60-4d12-ad70-a8024a82edfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779163626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.779163626
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1893007094
Short name T132
Test name
Test status
Simulation time 557005592723 ps
CPU time 849.02 seconds
Started May 16 12:42:12 PM PDT 24
Finished May 16 12:56:24 PM PDT 24
Peak memory 190760 kb
Host smart-57c6c884-281d-4f6c-87be-1fc28f73ba3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893007094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1893007094
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.970046684
Short name T226
Test name
Test status
Simulation time 1184644109953 ps
CPU time 664.38 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 12:52:47 PM PDT 24
Peak memory 182548 kb
Host smart-2734f91c-5776-4581-be13-c2c7eb2f21e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970046684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
970046684
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.79711069
Short name T10
Test name
Test status
Simulation time 1427565084381 ps
CPU time 772.45 seconds
Started May 16 12:41:53 PM PDT 24
Finished May 16 12:54:53 PM PDT 24
Peak memory 182568 kb
Host smart-3df14b98-7d9c-4a5f-bf93-bedbad463417
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79711069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.rv_timer_cfg_update_on_fly.79711069
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.1903058778
Short name T291
Test name
Test status
Simulation time 1022730367398 ps
CPU time 408.89 seconds
Started May 16 12:41:48 PM PDT 24
Finished May 16 12:48:44 PM PDT 24
Peak memory 190668 kb
Host smart-c51e9a95-2556-4a17-b503-e0d9a847c82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903058778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1903058778
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2484757452
Short name T280
Test name
Test status
Simulation time 83303478495 ps
CPU time 1576.99 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 01:07:40 PM PDT 24
Peak memory 190804 kb
Host smart-3ed284df-28e0-4654-9aa0-5ae8dd03de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484757452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2484757452
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_random.3344878951
Short name T313
Test name
Test status
Simulation time 1570592078922 ps
CPU time 253.86 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:45:44 PM PDT 24
Peak memory 190736 kb
Host smart-b7a91137-adc4-4482-b7d1-61a30cdcc1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344878951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3344878951
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.4249373893
Short name T285
Test name
Test status
Simulation time 248909315862 ps
CPU time 668.5 seconds
Started May 16 12:42:01 PM PDT 24
Finished May 16 12:53:16 PM PDT 24
Peak memory 190784 kb
Host smart-a316d324-6495-47b2-9e84-f712bc045a12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249373893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4249373893
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3148568554
Short name T110
Test name
Test status
Simulation time 517916831196 ps
CPU time 1855.15 seconds
Started May 16 12:42:13 PM PDT 24
Finished May 16 01:13:11 PM PDT 24
Peak memory 190768 kb
Host smart-769a5306-9ade-42ba-af35-bc7156cd7508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148568554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3148568554
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.903452159
Short name T106
Test name
Test status
Simulation time 599011929088 ps
CPU time 2078.55 seconds
Started May 16 12:41:39 PM PDT 24
Finished May 16 01:16:24 PM PDT 24
Peak memory 190772 kb
Host smart-662c3298-d033-4141-90e6-b45edf95b413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903452159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.903452159
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2513201490
Short name T213
Test name
Test status
Simulation time 236324391192 ps
CPU time 178.39 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:45:18 PM PDT 24
Peak memory 190776 kb
Host smart-5210236a-b7e7-441b-856f-69c303fced9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513201490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2513201490
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2596078315
Short name T175
Test name
Test status
Simulation time 187223032402 ps
CPU time 327.65 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 12:47:10 PM PDT 24
Peak memory 182512 kb
Host smart-fd3d6db9-7f96-4cd8-bb0d-44395fc680dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596078315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2596078315
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/172.rv_timer_random.708279492
Short name T351
Test name
Test status
Simulation time 416314629961 ps
CPU time 437.4 seconds
Started May 16 12:42:21 PM PDT 24
Finished May 16 12:49:42 PM PDT 24
Peak memory 190688 kb
Host smart-22036a1a-5815-4ba9-886c-8eff5b23f5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708279492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.708279492
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.186385372
Short name T20
Test name
Test status
Simulation time 2162102565304 ps
CPU time 284.29 seconds
Started May 16 12:42:21 PM PDT 24
Finished May 16 12:47:08 PM PDT 24
Peak memory 190736 kb
Host smart-47f192f6-618b-471e-ba82-7fbdc5a78590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186385372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.186385372
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2332314510
Short name T230
Test name
Test status
Simulation time 418808567399 ps
CPU time 400.38 seconds
Started May 16 12:42:17 PM PDT 24
Finished May 16 12:49:01 PM PDT 24
Peak memory 190756 kb
Host smart-0097daaf-67d9-4c61-9eba-322ac9d95a91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332314510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2332314510
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2700074514
Short name T149
Test name
Test status
Simulation time 1678654861506 ps
CPU time 875.26 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:56:22 PM PDT 24
Peak memory 182596 kb
Host smart-32c88e11-d00e-468d-805a-8cdcd8dfe2ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700074514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2700074514
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.1242975701
Short name T158
Test name
Test status
Simulation time 81852394386 ps
CPU time 160.84 seconds
Started May 16 12:41:38 PM PDT 24
Finished May 16 12:44:26 PM PDT 24
Peak memory 190660 kb
Host smart-557353bf-231b-4650-bb3d-0552b7323134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242975701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1242975701
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3263795304
Short name T72
Test name
Test status
Simulation time 8941033221473 ps
CPU time 1435.21 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 01:05:40 PM PDT 24
Peak memory 190820 kb
Host smart-695c2330-f9f8-4138-853a-a932f596fe97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263795304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3263795304
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/57.rv_timer_random.3850635293
Short name T335
Test name
Test status
Simulation time 318959779910 ps
CPU time 500.92 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:50:18 PM PDT 24
Peak memory 190748 kb
Host smart-ced2e25f-e7b1-4934-a111-30c47b2c5c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850635293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3850635293
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1227437435
Short name T245
Test name
Test status
Simulation time 386036251504 ps
CPU time 197.05 seconds
Started May 16 12:41:55 PM PDT 24
Finished May 16 12:45:20 PM PDT 24
Peak memory 190784 kb
Host smart-7a01e9f4-77c0-407f-a580-356a3557d42b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227437435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1227437435
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3121864402
Short name T99
Test name
Test status
Simulation time 277978826 ps
CPU time 1.03 seconds
Started May 16 12:41:00 PM PDT 24
Finished May 16 12:41:05 PM PDT 24
Peak memory 183448 kb
Host smart-787b4937-c0e1-4250-af3d-0435a3ae47f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121864402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3121864402
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4155074836
Short name T339
Test name
Test status
Simulation time 1739575587052 ps
CPU time 532.41 seconds
Started May 16 12:41:14 PM PDT 24
Finished May 16 12:50:09 PM PDT 24
Peak memory 182468 kb
Host smart-97ddeb52-8821-4535-87bb-42f9d3b64a90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155074836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4155074836
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/105.rv_timer_random.1882188647
Short name T162
Test name
Test status
Simulation time 344712486320 ps
CPU time 311.62 seconds
Started May 16 12:41:57 PM PDT 24
Finished May 16 12:47:16 PM PDT 24
Peak memory 190796 kb
Host smart-cba965ab-9607-4187-9121-f1b63d1c5bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882188647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1882188647
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.723780084
Short name T196
Test name
Test status
Simulation time 83825359762 ps
CPU time 144.14 seconds
Started May 16 12:41:57 PM PDT 24
Finished May 16 12:44:28 PM PDT 24
Peak memory 190744 kb
Host smart-99db4338-2025-4a24-9bc1-34b80f54eda1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723780084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.723780084
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4054581198
Short name T170
Test name
Test status
Simulation time 352918498715 ps
CPU time 555.23 seconds
Started May 16 12:41:56 PM PDT 24
Finished May 16 12:51:19 PM PDT 24
Peak memory 190768 kb
Host smart-cb2952c3-4fdb-48fe-bfae-270ce5eee434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054581198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4054581198
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.160483519
Short name T182
Test name
Test status
Simulation time 124831317536 ps
CPU time 1296.03 seconds
Started May 16 12:42:05 PM PDT 24
Finished May 16 01:03:47 PM PDT 24
Peak memory 190712 kb
Host smart-4987d265-7c99-4c5c-b466-8fa4a7de05cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160483519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.160483519
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2902326920
Short name T234
Test name
Test status
Simulation time 34664513117 ps
CPU time 54.38 seconds
Started May 16 12:42:10 PM PDT 24
Finished May 16 12:43:08 PM PDT 24
Peak memory 190704 kb
Host smart-a1d40655-84d7-4c41-a9c7-bdff157e83b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902326920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2902326920
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.597937378
Short name T180
Test name
Test status
Simulation time 167820366901 ps
CPU time 1622.84 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 01:09:21 PM PDT 24
Peak memory 190736 kb
Host smart-f8e9983d-11be-49ba-935f-d7483117a858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597937378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.597937378
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3144345442
Short name T194
Test name
Test status
Simulation time 163198128191 ps
CPU time 252.78 seconds
Started May 16 12:41:32 PM PDT 24
Finished May 16 12:45:51 PM PDT 24
Peak memory 182488 kb
Host smart-24571042-2bce-4a85-bdb9-2d2f575b74c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144345442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3144345442
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/178.rv_timer_random.3643074031
Short name T66
Test name
Test status
Simulation time 298812960461 ps
CPU time 108.47 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:44:06 PM PDT 24
Peak memory 190780 kb
Host smart-60edae33-246d-4ed0-bd64-704143d2542b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643074031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3643074031
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2265544721
Short name T282
Test name
Test status
Simulation time 1211920798802 ps
CPU time 1435.18 seconds
Started May 16 12:41:42 PM PDT 24
Finished May 16 01:05:44 PM PDT 24
Peak memory 182484 kb
Host smart-c3a57113-f227-4600-87ab-77d2ad63f187
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265544721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2265544721
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2329969259
Short name T346
Test name
Test status
Simulation time 234322775327 ps
CPU time 231.11 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 12:45:35 PM PDT 24
Peak memory 182636 kb
Host smart-0aef9423-5699-4853-ad35-2876bcd528c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329969259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2329969259
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_random.2533090027
Short name T333
Test name
Test status
Simulation time 17405350611 ps
CPU time 27.98 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:42:21 PM PDT 24
Peak memory 190772 kb
Host smart-4eefd29d-0050-41a7-b38f-67e7cb78ca50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533090027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2533090027
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.3420802544
Short name T154
Test name
Test status
Simulation time 338932747240 ps
CPU time 784.28 seconds
Started May 16 12:41:53 PM PDT 24
Finished May 16 12:55:06 PM PDT 24
Peak memory 190792 kb
Host smart-2d5a4201-30d0-4d52-87e5-1977b1c7a900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420802544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3420802544
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3188317796
Short name T117
Test name
Test status
Simulation time 1868985753178 ps
CPU time 991.99 seconds
Started May 16 12:41:44 PM PDT 24
Finished May 16 12:58:23 PM PDT 24
Peak memory 182516 kb
Host smart-bf1946e4-82b8-4428-b099-6e41c4eefed8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188317796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3188317796
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3239041258
Short name T208
Test name
Test status
Simulation time 118705821874 ps
CPU time 195.61 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:45:15 PM PDT 24
Peak memory 182492 kb
Host smart-0a557e27-2429-43f0-a27e-029722381124
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239041258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3239041258
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/54.rv_timer_random.3588163420
Short name T146
Test name
Test status
Simulation time 204497266520 ps
CPU time 107.22 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:43:47 PM PDT 24
Peak memory 190676 kb
Host smart-88149c0a-41e0-4f67-b8e3-5a6437ed1e6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588163420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3588163420
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.809743561
Short name T308
Test name
Test status
Simulation time 144969289915 ps
CPU time 577.2 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:51:31 PM PDT 24
Peak memory 191784 kb
Host smart-082bd1a8-f046-4bb5-b351-76b56c88346d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809743561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.809743561
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3666274158
Short name T301
Test name
Test status
Simulation time 108911501781 ps
CPU time 894.36 seconds
Started May 16 12:42:06 PM PDT 24
Finished May 16 12:57:06 PM PDT 24
Peak memory 182600 kb
Host smart-dde2d688-53e7-4ebc-892b-f26e5d17dfb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666274158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3666274158
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1267541811
Short name T192
Test name
Test status
Simulation time 189261041492 ps
CPU time 159.74 seconds
Started May 16 12:42:05 PM PDT 24
Finished May 16 12:44:51 PM PDT 24
Peak memory 190780 kb
Host smart-3407b2c6-9791-4f23-8594-a6317088a89a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267541811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1267541811
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3183220040
Short name T263
Test name
Test status
Simulation time 102505597470 ps
CPU time 152.78 seconds
Started May 16 12:42:04 PM PDT 24
Finished May 16 12:44:43 PM PDT 24
Peak memory 190728 kb
Host smart-7bbf4495-a83e-454e-92cd-c02bb3954e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183220040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3183220040
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.42973137
Short name T219
Test name
Test status
Simulation time 641755829474 ps
CPU time 695.79 seconds
Started May 16 12:42:00 PM PDT 24
Finished May 16 12:53:42 PM PDT 24
Peak memory 190788 kb
Host smart-68428c77-2a44-42aa-ae34-60e07bf8e7b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42973137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.42973137
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2310931146
Short name T223
Test name
Test status
Simulation time 88852153098 ps
CPU time 317.75 seconds
Started May 16 12:42:01 PM PDT 24
Finished May 16 12:47:25 PM PDT 24
Peak memory 190788 kb
Host smart-ce7fb83c-9d59-4b4f-9722-6a549fea7c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310931146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2310931146
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.1373126821
Short name T107
Test name
Test status
Simulation time 159748459377 ps
CPU time 655.82 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:52:30 PM PDT 24
Peak memory 190800 kb
Host smart-c994f8f6-efd8-41c8-b8bb-7665d927b7c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373126821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1373126821
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2157880361
Short name T357
Test name
Test status
Simulation time 64687442025 ps
CPU time 392.75 seconds
Started May 16 12:41:27 PM PDT 24
Finished May 16 12:48:06 PM PDT 24
Peak memory 190780 kb
Host smart-af8d8bce-fdcf-4e74-b095-33487be3cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157880361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2157880361
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/153.rv_timer_random.1509561810
Short name T75
Test name
Test status
Simulation time 88709638780 ps
CPU time 39.51 seconds
Started May 16 12:42:19 PM PDT 24
Finished May 16 12:43:01 PM PDT 24
Peak memory 190816 kb
Host smart-a7d104b8-0b02-43f7-a312-644e9cf58cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509561810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1509561810
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2180541277
Short name T165
Test name
Test status
Simulation time 85353885848 ps
CPU time 142.95 seconds
Started May 16 12:42:21 PM PDT 24
Finished May 16 12:44:47 PM PDT 24
Peak memory 190780 kb
Host smart-bb8c4170-74b7-4e98-b239-bebe114ac519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180541277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2180541277
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.2930908080
Short name T129
Test name
Test status
Simulation time 163112114959 ps
CPU time 1555.35 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 01:08:14 PM PDT 24
Peak memory 191724 kb
Host smart-e493c724-767f-493d-a79a-c1625a2e5bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930908080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2930908080
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2933992572
Short name T236
Test name
Test status
Simulation time 199231292463 ps
CPU time 107.43 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:44:06 PM PDT 24
Peak memory 190788 kb
Host smart-00451775-be69-4c11-963f-51ce1d2e5ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933992572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2933992572
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3929853177
Short name T250
Test name
Test status
Simulation time 351657002786 ps
CPU time 208.47 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:45:48 PM PDT 24
Peak memory 190776 kb
Host smart-c78e4eb8-e32d-4fbb-9b23-baf59ee94ec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929853177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3929853177
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.3040747530
Short name T324
Test name
Test status
Simulation time 1030339216990 ps
CPU time 557.25 seconds
Started May 16 12:42:17 PM PDT 24
Finished May 16 12:51:38 PM PDT 24
Peak memory 190704 kb
Host smart-52beb337-91fb-4001-b633-a512628269e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040747530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3040747530
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2336261224
Short name T156
Test name
Test status
Simulation time 464421382641 ps
CPU time 176.66 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:44:21 PM PDT 24
Peak memory 195532 kb
Host smart-4622fdb8-2865-4847-9b00-57b6bb9d3fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336261224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2336261224
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3060704295
Short name T327
Test name
Test status
Simulation time 39855898200 ps
CPU time 75.43 seconds
Started May 16 12:41:29 PM PDT 24
Finished May 16 12:42:50 PM PDT 24
Peak memory 182600 kb
Host smart-4d4ccac6-dc4d-4fd3-91af-19cce965db77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060704295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3060704295
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.4278545414
Short name T102
Test name
Test status
Simulation time 31435441808 ps
CPU time 81.9 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 12:43:06 PM PDT 24
Peak memory 194512 kb
Host smart-44552052-26ce-404c-a4ac-c017515532db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278545414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4278545414
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_random.171220448
Short name T277
Test name
Test status
Simulation time 90674862388 ps
CPU time 965.14 seconds
Started May 16 12:41:32 PM PDT 24
Finished May 16 12:57:44 PM PDT 24
Peak memory 190816 kb
Host smart-f8e23f32-45c4-4f19-8af0-9e93da7742ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171220448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.171220448
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1721606423
Short name T26
Test name
Test status
Simulation time 204232191202 ps
CPU time 82.98 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:43:18 PM PDT 24
Peak memory 193080 kb
Host smart-21937c49-2b0f-45dd-ae89-f893d6473a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721606423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1721606423
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/53.rv_timer_random.1056289267
Short name T187
Test name
Test status
Simulation time 117726240284 ps
CPU time 199.36 seconds
Started May 16 12:42:04 PM PDT 24
Finished May 16 12:45:30 PM PDT 24
Peak memory 190688 kb
Host smart-6ad38bc9-0b28-49f0-b8bb-ce881af388d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056289267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1056289267
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.2123071357
Short name T293
Test name
Test status
Simulation time 91934930857 ps
CPU time 243.08 seconds
Started May 16 12:42:01 PM PDT 24
Finished May 16 12:46:11 PM PDT 24
Peak memory 190696 kb
Host smart-53eaa86c-0134-4a96-ae38-ff59d8e9464f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123071357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2123071357
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.412464394
Short name T127
Test name
Test status
Simulation time 29691915208 ps
CPU time 174.29 seconds
Started May 16 12:41:53 PM PDT 24
Finished May 16 12:44:55 PM PDT 24
Peak memory 190780 kb
Host smart-4bdf71a8-2455-4dab-9bc3-a63481c98af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412464394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.412464394
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.428810981
Short name T190
Test name
Test status
Simulation time 130434033854 ps
CPU time 181.55 seconds
Started May 16 12:41:55 PM PDT 24
Finished May 16 12:45:04 PM PDT 24
Peak memory 194260 kb
Host smart-2b7b9348-1a8b-44b5-a8c6-409185af7809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428810981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.428810981
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1596145278
Short name T151
Test name
Test status
Simulation time 9983475477930 ps
CPU time 3037.28 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 01:32:03 PM PDT 24
Peak memory 190588 kb
Host smart-63a0c9f4-8a1b-4018-9288-99ff74629c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596145278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1596145278
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4130374692
Short name T552
Test name
Test status
Simulation time 163774785 ps
CPU time 0.71 seconds
Started May 16 12:40:56 PM PDT 24
Finished May 16 12:41:02 PM PDT 24
Peak memory 182564 kb
Host smart-7948a64c-505a-44ee-8028-f368a7c830c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130374692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4130374692
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2228474842
Short name T521
Test name
Test status
Simulation time 820548432 ps
CPU time 3.69 seconds
Started May 16 12:40:49 PM PDT 24
Finished May 16 12:40:56 PM PDT 24
Peak memory 193924 kb
Host smart-2eb83600-4343-423e-b84b-427c68588ad0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228474842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2228474842
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.293119236
Short name T467
Test name
Test status
Simulation time 31203749 ps
CPU time 0.56 seconds
Started May 16 12:40:45 PM PDT 24
Finished May 16 12:40:48 PM PDT 24
Peak memory 182680 kb
Host smart-77ae3480-508c-43f3-b9f4-37724ccd75d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293119236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.293119236
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.227895286
Short name T561
Test name
Test status
Simulation time 27460289 ps
CPU time 0.63 seconds
Started May 16 12:40:50 PM PDT 24
Finished May 16 12:40:54 PM PDT 24
Peak memory 193084 kb
Host smart-ce167c2f-5c6a-44d0-8058-4ba221288f02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227895286 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.227895286
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2940919819
Short name T515
Test name
Test status
Simulation time 13800278 ps
CPU time 0.58 seconds
Started May 16 12:40:51 PM PDT 24
Finished May 16 12:41:01 PM PDT 24
Peak memory 182696 kb
Host smart-0688329f-5d4c-4c88-b652-c7d5611df52f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940919819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2940919819
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2528478511
Short name T516
Test name
Test status
Simulation time 73411646 ps
CPU time 0.55 seconds
Started May 16 12:40:48 PM PDT 24
Finished May 16 12:40:52 PM PDT 24
Peak memory 181912 kb
Host smart-f9bedfa2-af53-4f71-aed4-8cce5b351b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528478511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2528478511
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4280066011
Short name T524
Test name
Test status
Simulation time 64977187 ps
CPU time 0.65 seconds
Started May 16 12:41:02 PM PDT 24
Finished May 16 12:41:06 PM PDT 24
Peak memory 193028 kb
Host smart-86f3865e-ea0a-43df-8c20-d98d8190c4e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280066011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4280066011
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1003855092
Short name T581
Test name
Test status
Simulation time 231853565 ps
CPU time 1.96 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:02 PM PDT 24
Peak memory 197548 kb
Host smart-81a3bafe-be70-4c0e-a31a-b7a33b65f874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003855092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1003855092
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.143777350
Short name T82
Test name
Test status
Simulation time 34093258 ps
CPU time 0.6 seconds
Started May 16 12:40:49 PM PDT 24
Finished May 16 12:40:53 PM PDT 24
Peak memory 182700 kb
Host smart-5513bcc1-d676-4587-92f6-e435e0dd55d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143777350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.143777350
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1273237520
Short name T496
Test name
Test status
Simulation time 1244246245 ps
CPU time 3.6 seconds
Started May 16 12:40:43 PM PDT 24
Finished May 16 12:40:49 PM PDT 24
Peak memory 191108 kb
Host smart-6ddd4591-3558-4984-88f1-8797685987f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273237520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1273237520
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2785019050
Short name T86
Test name
Test status
Simulation time 73435304 ps
CPU time 0.58 seconds
Started May 16 12:40:58 PM PDT 24
Finished May 16 12:41:04 PM PDT 24
Peak memory 182700 kb
Host smart-5b8c0601-ac63-48ef-b2e0-dcc3c0deebe0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785019050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2785019050
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3564322310
Short name T481
Test name
Test status
Simulation time 64752492 ps
CPU time 1.51 seconds
Started May 16 12:41:05 PM PDT 24
Finished May 16 12:41:10 PM PDT 24
Peak memory 197648 kb
Host smart-bf3da305-1a6a-4e8c-8948-3d45706511a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564322310 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3564322310
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2124518363
Short name T506
Test name
Test status
Simulation time 57281474 ps
CPU time 0.58 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:01 PM PDT 24
Peak memory 182728 kb
Host smart-01924216-17e3-47f6-9646-866fde9821a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124518363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2124518363
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1847830661
Short name T492
Test name
Test status
Simulation time 11317900 ps
CPU time 0.52 seconds
Started May 16 12:40:48 PM PDT 24
Finished May 16 12:40:59 PM PDT 24
Peak memory 182052 kb
Host smart-55aec32e-3972-4954-98c0-0a196d9e82fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847830661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1847830661
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.531151001
Short name T569
Test name
Test status
Simulation time 40617156 ps
CPU time 0.56 seconds
Started May 16 12:40:50 PM PDT 24
Finished May 16 12:40:54 PM PDT 24
Peak memory 191996 kb
Host smart-baaf8376-5f76-45df-ae20-fd462eb9e900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531151001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.531151001
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3014240921
Short name T568
Test name
Test status
Simulation time 211032375 ps
CPU time 1.28 seconds
Started May 16 12:40:50 PM PDT 24
Finished May 16 12:40:55 PM PDT 24
Peak memory 196784 kb
Host smart-3e64c074-0084-42e2-a16e-403ac44c00e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014240921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3014240921
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3406678275
Short name T100
Test name
Test status
Simulation time 78995491 ps
CPU time 1.05 seconds
Started May 16 12:40:49 PM PDT 24
Finished May 16 12:40:54 PM PDT 24
Peak memory 195044 kb
Host smart-f69e2374-d5d3-430a-9667-786f5626de2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406678275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3406678275
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2990600410
Short name T579
Test name
Test status
Simulation time 35536934 ps
CPU time 0.84 seconds
Started May 16 12:40:52 PM PDT 24
Finished May 16 12:40:57 PM PDT 24
Peak memory 196024 kb
Host smart-2c942923-c104-4ab5-8e61-eaeaa37b53a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990600410 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2990600410
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.512122416
Short name T580
Test name
Test status
Simulation time 209059651 ps
CPU time 0.58 seconds
Started May 16 12:41:01 PM PDT 24
Finished May 16 12:41:06 PM PDT 24
Peak memory 182656 kb
Host smart-047d2e27-507e-408d-80f1-1b03d8a4ae18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512122416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.512122416
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2324920180
Short name T549
Test name
Test status
Simulation time 124388024 ps
CPU time 0.52 seconds
Started May 16 12:41:04 PM PDT 24
Finished May 16 12:41:08 PM PDT 24
Peak memory 182512 kb
Host smart-fc2bb134-7c61-4bfe-8d6d-901c316db39c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324920180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2324920180
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1614628543
Short name T572
Test name
Test status
Simulation time 20142997 ps
CPU time 0.76 seconds
Started May 16 12:40:42 PM PDT 24
Finished May 16 12:40:44 PM PDT 24
Peak memory 193356 kb
Host smart-829bd7b2-ab64-45bb-b4b4-49a8bbea1e51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614628543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1614628543
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3060134269
Short name T479
Test name
Test status
Simulation time 240637120 ps
CPU time 3 seconds
Started May 16 12:40:57 PM PDT 24
Finished May 16 12:41:05 PM PDT 24
Peak memory 197596 kb
Host smart-70c947a8-fdeb-44e4-8779-705b03d71b45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060134269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3060134269
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.694761788
Short name T534
Test name
Test status
Simulation time 35894621 ps
CPU time 0.81 seconds
Started May 16 12:40:54 PM PDT 24
Finished May 16 12:41:00 PM PDT 24
Peak memory 196944 kb
Host smart-77b597c1-24ac-4675-9ff7-d1574f7b231a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694761788 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.694761788
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.345156841
Short name T452
Test name
Test status
Simulation time 55657530 ps
CPU time 0.61 seconds
Started May 16 12:41:13 PM PDT 24
Finished May 16 12:41:16 PM PDT 24
Peak memory 182624 kb
Host smart-e964b000-7070-4509-9734-f076d8483128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345156841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.345156841
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4269799327
Short name T93
Test name
Test status
Simulation time 18721019 ps
CPU time 0.79 seconds
Started May 16 12:40:53 PM PDT 24
Finished May 16 12:40:59 PM PDT 24
Peak memory 193196 kb
Host smart-9bda9f19-7d91-4e16-9e56-db0ae6bf3064
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269799327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.4269799327
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1924370618
Short name T461
Test name
Test status
Simulation time 47040953 ps
CPU time 2.15 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:03 PM PDT 24
Peak memory 197596 kb
Host smart-5fc3d331-4407-40bf-b399-46fff105fd05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924370618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1924370618
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.410041478
Short name T30
Test name
Test status
Simulation time 50766957 ps
CPU time 0.81 seconds
Started May 16 12:41:03 PM PDT 24
Finished May 16 12:41:07 PM PDT 24
Peak memory 193792 kb
Host smart-b899392a-db0f-4bfa-875e-1789dcfc2806
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410041478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.410041478
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2181851372
Short name T555
Test name
Test status
Simulation time 33707147 ps
CPU time 1.45 seconds
Started May 16 12:41:30 PM PDT 24
Finished May 16 12:41:37 PM PDT 24
Peak memory 197608 kb
Host smart-a5d74d1c-8b88-450d-ba30-c4826944089b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181851372 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2181851372
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1775330455
Short name T526
Test name
Test status
Simulation time 185219238 ps
CPU time 0.57 seconds
Started May 16 12:40:58 PM PDT 24
Finished May 16 12:41:04 PM PDT 24
Peak memory 182708 kb
Host smart-bfe24762-9d98-499a-b333-85336a7450d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775330455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1775330455
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3519725061
Short name T475
Test name
Test status
Simulation time 196627426 ps
CPU time 0.6 seconds
Started May 16 12:40:53 PM PDT 24
Finished May 16 12:40:58 PM PDT 24
Peak memory 182700 kb
Host smart-2f66d59d-b7f5-4dba-be9f-d3c0baf1cb65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519725061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3519725061
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2407110588
Short name T554
Test name
Test status
Simulation time 28423080 ps
CPU time 0.73 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:41:25 PM PDT 24
Peak memory 191620 kb
Host smart-35de7166-84b2-41a1-bf66-a292e46c3658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407110588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2407110588
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1325509655
Short name T542
Test name
Test status
Simulation time 130494493 ps
CPU time 1.98 seconds
Started May 16 12:41:09 PM PDT 24
Finished May 16 12:41:13 PM PDT 24
Peak memory 197584 kb
Host smart-7a2cd1ab-60a7-4c53-a390-62582cd509a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325509655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1325509655
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4031507714
Short name T97
Test name
Test status
Simulation time 151855612 ps
CPU time 0.82 seconds
Started May 16 12:41:02 PM PDT 24
Finished May 16 12:41:07 PM PDT 24
Peak memory 192668 kb
Host smart-a77e7f7c-e73b-4ebc-a5c1-86421095b4ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031507714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4031507714
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2346884533
Short name T564
Test name
Test status
Simulation time 33320804 ps
CPU time 0.84 seconds
Started May 16 12:41:14 PM PDT 24
Finished May 16 12:41:17 PM PDT 24
Peak memory 197420 kb
Host smart-8b2b442b-b3ad-4e35-8558-652998b0cd0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346884533 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2346884533
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.369998503
Short name T558
Test name
Test status
Simulation time 19881800 ps
CPU time 0.53 seconds
Started May 16 12:41:04 PM PDT 24
Finished May 16 12:41:08 PM PDT 24
Peak memory 182512 kb
Host smart-a90b28ef-d4a8-4b80-a134-c9a4f2de3f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369998503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.369998503
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2589876165
Short name T550
Test name
Test status
Simulation time 43005142 ps
CPU time 0.54 seconds
Started May 16 12:41:13 PM PDT 24
Finished May 16 12:41:16 PM PDT 24
Peak memory 182636 kb
Host smart-d9f50804-b4bb-4ff0-a93b-24daaa83c982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589876165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2589876165
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.559794035
Short name T80
Test name
Test status
Simulation time 74248222 ps
CPU time 0.73 seconds
Started May 16 12:41:32 PM PDT 24
Finished May 16 12:41:38 PM PDT 24
Peak memory 193288 kb
Host smart-d88982d9-93ea-423b-bb0d-99889eac6682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559794035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.559794035
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2077220921
Short name T462
Test name
Test status
Simulation time 130371177 ps
CPU time 1.42 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:41:24 PM PDT 24
Peak memory 191252 kb
Host smart-a5132790-1a3b-4cc3-a1a3-4ad9b0923f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077220921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2077220921
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3580639006
Short name T544
Test name
Test status
Simulation time 861200667 ps
CPU time 1.41 seconds
Started May 16 12:40:57 PM PDT 24
Finished May 16 12:41:03 PM PDT 24
Peak memory 183268 kb
Host smart-13272e91-6691-48f8-9a1b-9f0df3f0ebd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580639006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3580639006
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1830492785
Short name T507
Test name
Test status
Simulation time 139912970 ps
CPU time 0.74 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:27 PM PDT 24
Peak memory 194564 kb
Host smart-adf96245-22d6-483e-95ba-8b753e3bd21d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830492785 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1830492785
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.272971256
Short name T84
Test name
Test status
Simulation time 14615634 ps
CPU time 0.57 seconds
Started May 16 12:41:03 PM PDT 24
Finished May 16 12:41:07 PM PDT 24
Peak memory 182668 kb
Host smart-e11aa840-7b1c-406a-901f-ea713b8406b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272971256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.272971256
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3084396368
Short name T513
Test name
Test status
Simulation time 15437587 ps
CPU time 0.54 seconds
Started May 16 12:41:35 PM PDT 24
Finished May 16 12:41:42 PM PDT 24
Peak memory 182052 kb
Host smart-d42d0223-9c21-4067-ba9b-af43df42801c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084396368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3084396368
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2910347784
Short name T508
Test name
Test status
Simulation time 58989067 ps
CPU time 0.79 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:41:25 PM PDT 24
Peak memory 193516 kb
Host smart-7e99f989-dc7f-4ee5-8f9b-df4d5e9a06d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910347784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2910347784
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1004458842
Short name T470
Test name
Test status
Simulation time 983082962 ps
CPU time 2.38 seconds
Started May 16 12:41:39 PM PDT 24
Finished May 16 12:41:48 PM PDT 24
Peak memory 197488 kb
Host smart-34b39e57-3495-40ca-bafe-1bcf4c65ae65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004458842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1004458842
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2003861220
Short name T47
Test name
Test status
Simulation time 90294356 ps
CPU time 1.08 seconds
Started May 16 12:41:15 PM PDT 24
Finished May 16 12:41:19 PM PDT 24
Peak memory 183184 kb
Host smart-035d84d9-453b-4317-aefc-7e259ce471fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003861220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2003861220
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.4224913919
Short name T504
Test name
Test status
Simulation time 36016991 ps
CPU time 0.83 seconds
Started May 16 12:41:14 PM PDT 24
Finished May 16 12:41:18 PM PDT 24
Peak memory 196920 kb
Host smart-d39540ac-3b4c-4dce-bb6f-5a472131604a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224913919 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.4224913919
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1671842905
Short name T528
Test name
Test status
Simulation time 15915131 ps
CPU time 0.55 seconds
Started May 16 12:41:17 PM PDT 24
Finished May 16 12:41:20 PM PDT 24
Peak memory 182536 kb
Host smart-b723b90e-98d9-4f72-8831-b030cb45e9e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671842905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1671842905
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2547615903
Short name T491
Test name
Test status
Simulation time 23807068 ps
CPU time 0.56 seconds
Started May 16 12:41:14 PM PDT 24
Finished May 16 12:41:17 PM PDT 24
Peak memory 182096 kb
Host smart-8f779754-9b5c-4e81-9be6-ae1fe7ef7891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547615903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2547615903
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3487438227
Short name T32
Test name
Test status
Simulation time 27442726 ps
CPU time 0.71 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:27 PM PDT 24
Peak memory 191592 kb
Host smart-0806dc59-7f74-45a0-b966-51048aefa6fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487438227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3487438227
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2298093309
Short name T465
Test name
Test status
Simulation time 146500608 ps
CPU time 1.89 seconds
Started May 16 12:41:03 PM PDT 24
Finished May 16 12:41:08 PM PDT 24
Peak memory 197632 kb
Host smart-7612e159-4e1c-4d3d-a73a-00162c7f724c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298093309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2298093309
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2006238581
Short name T471
Test name
Test status
Simulation time 38733147 ps
CPU time 0.82 seconds
Started May 16 12:41:07 PM PDT 24
Finished May 16 12:41:11 PM PDT 24
Peak memory 193232 kb
Host smart-bd7dbebb-cdf4-4433-b4f3-aeb0b278c64e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006238581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2006238581
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4075044172
Short name T476
Test name
Test status
Simulation time 71705755 ps
CPU time 1.68 seconds
Started May 16 12:41:15 PM PDT 24
Finished May 16 12:41:19 PM PDT 24
Peak memory 197492 kb
Host smart-16b934e4-da9a-48c1-87d0-8e8beb08b0ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075044172 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.4075044172
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1342022429
Short name T576
Test name
Test status
Simulation time 16406088 ps
CPU time 0.57 seconds
Started May 16 12:41:03 PM PDT 24
Finished May 16 12:41:08 PM PDT 24
Peak memory 182704 kb
Host smart-4a41cef5-903d-4478-b8db-d7f219492989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342022429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1342022429
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1621399539
Short name T494
Test name
Test status
Simulation time 59820998 ps
CPU time 0.57 seconds
Started May 16 12:41:12 PM PDT 24
Finished May 16 12:41:15 PM PDT 24
Peak memory 182440 kb
Host smart-9c5d2ba0-73fd-4a5c-a944-cda152b496f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621399539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1621399539
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2857165877
Short name T92
Test name
Test status
Simulation time 20736658 ps
CPU time 0.6 seconds
Started May 16 12:41:11 PM PDT 24
Finished May 16 12:41:14 PM PDT 24
Peak memory 192068 kb
Host smart-8017d0cc-4989-4e02-8b7d-3932bd304e06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857165877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2857165877
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3298607322
Short name T451
Test name
Test status
Simulation time 46771667 ps
CPU time 2.22 seconds
Started May 16 12:41:16 PM PDT 24
Finished May 16 12:41:21 PM PDT 24
Peak memory 197552 kb
Host smart-dba7f467-8d46-4e4c-8ebd-d31b85ddbef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298607322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3298607322
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3403195791
Short name T503
Test name
Test status
Simulation time 303020392 ps
CPU time 1.07 seconds
Started May 16 12:41:06 PM PDT 24
Finished May 16 12:41:10 PM PDT 24
Peak memory 183256 kb
Host smart-cb6c4fe9-832c-4d6f-b941-004f98685e08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403195791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3403195791
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.617102697
Short name T493
Test name
Test status
Simulation time 48248954 ps
CPU time 1.06 seconds
Started May 16 12:41:15 PM PDT 24
Finished May 16 12:41:19 PM PDT 24
Peak memory 197408 kb
Host smart-0c4d1def-e177-4840-8bc9-eadfa03750be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617102697 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.617102697
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1129210479
Short name T87
Test name
Test status
Simulation time 28096220 ps
CPU time 0.59 seconds
Started May 16 12:41:31 PM PDT 24
Finished May 16 12:41:37 PM PDT 24
Peak memory 182584 kb
Host smart-4eb168f1-f04c-4d18-9664-2341720e2473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129210479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1129210479
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1002557335
Short name T458
Test name
Test status
Simulation time 23004070 ps
CPU time 0.55 seconds
Started May 16 12:41:18 PM PDT 24
Finished May 16 12:41:22 PM PDT 24
Peak memory 181908 kb
Host smart-fed4806e-cbce-45a8-85fc-372f301da364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002557335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1002557335
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3017392641
Short name T90
Test name
Test status
Simulation time 133230298 ps
CPU time 0.85 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:41:25 PM PDT 24
Peak memory 191616 kb
Host smart-c7da2900-22fc-4d48-8501-17a9873c9fc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017392641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3017392641
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3049579487
Short name T455
Test name
Test status
Simulation time 44337553 ps
CPU time 1.73 seconds
Started May 16 12:41:10 PM PDT 24
Finished May 16 12:41:14 PM PDT 24
Peak memory 197448 kb
Host smart-7eb44570-142f-48d0-97b4-acb2a208ea2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049579487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3049579487
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2365305880
Short name T529
Test name
Test status
Simulation time 755596836 ps
CPU time 1.36 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:41:35 PM PDT 24
Peak memory 195412 kb
Host smart-ab462fd9-3317-480e-b780-fdc09764b220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365305880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2365305880
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3656999821
Short name T537
Test name
Test status
Simulation time 28664771 ps
CPU time 1.2 seconds
Started May 16 12:41:07 PM PDT 24
Finished May 16 12:41:11 PM PDT 24
Peak memory 197504 kb
Host smart-c66bc6a2-5900-4321-87c1-a82c4d1bfba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656999821 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3656999821
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2699386534
Short name T557
Test name
Test status
Simulation time 36126318 ps
CPU time 0.58 seconds
Started May 16 12:41:11 PM PDT 24
Finished May 16 12:41:14 PM PDT 24
Peak memory 182600 kb
Host smart-cc0c6690-9ca2-487f-8c35-a77a9a2734d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699386534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2699386534
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2915907441
Short name T490
Test name
Test status
Simulation time 60742023 ps
CPU time 0.56 seconds
Started May 16 12:41:05 PM PDT 24
Finished May 16 12:41:09 PM PDT 24
Peak memory 182516 kb
Host smart-7a15c3ab-f6b8-49f7-9ebd-f39cf46dece5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915907441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2915907441
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3583957339
Short name T570
Test name
Test status
Simulation time 42754693 ps
CPU time 0.78 seconds
Started May 16 12:41:14 PM PDT 24
Finished May 16 12:41:17 PM PDT 24
Peak memory 191612 kb
Host smart-e18b5a2e-ad8a-455b-8d4e-7335467704f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583957339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3583957339
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1205045169
Short name T546
Test name
Test status
Simulation time 119668060 ps
CPU time 2.33 seconds
Started May 16 12:41:17 PM PDT 24
Finished May 16 12:41:22 PM PDT 24
Peak memory 197588 kb
Host smart-4fbe1779-939e-4859-8090-522068248e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205045169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1205045169
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3135332089
Short name T477
Test name
Test status
Simulation time 625911345 ps
CPU time 1.4 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:28 PM PDT 24
Peak memory 195192 kb
Host smart-add46a37-2b69-4ae5-b3ad-c4237c8d0fee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135332089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3135332089
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2613462654
Short name T567
Test name
Test status
Simulation time 61230911 ps
CPU time 1.46 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:41:25 PM PDT 24
Peak memory 197556 kb
Host smart-e308299e-40d5-40b0-88a1-88ecd45c6a20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613462654 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2613462654
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2274466417
Short name T31
Test name
Test status
Simulation time 11889585 ps
CPU time 0.54 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:27 PM PDT 24
Peak memory 182680 kb
Host smart-8f131999-388f-46a3-89d9-9af14e3e8fda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274466417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2274466417
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3847423076
Short name T456
Test name
Test status
Simulation time 15511573 ps
CPU time 0.55 seconds
Started May 16 12:41:12 PM PDT 24
Finished May 16 12:41:15 PM PDT 24
Peak memory 182532 kb
Host smart-1328a90c-3f68-4728-997c-a4dd985ceab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847423076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3847423076
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2232493539
Short name T522
Test name
Test status
Simulation time 22077575 ps
CPU time 0.72 seconds
Started May 16 12:41:11 PM PDT 24
Finished May 16 12:41:14 PM PDT 24
Peak memory 191596 kb
Host smart-8a9f36a9-485d-45ec-b113-60240a658973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232493539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2232493539
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3246555402
Short name T478
Test name
Test status
Simulation time 165749556 ps
CPU time 2.2 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:41:30 PM PDT 24
Peak memory 197504 kb
Host smart-4d773764-890a-4bf3-99ed-735ac65b7a46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246555402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3246555402
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3210459529
Short name T489
Test name
Test status
Simulation time 83997916 ps
CPU time 1.03 seconds
Started May 16 12:41:17 PM PDT 24
Finished May 16 12:41:21 PM PDT 24
Peak memory 183316 kb
Host smart-593c4549-7b90-4883-baea-fb3e27764e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210459529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3210459529
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2653674186
Short name T545
Test name
Test status
Simulation time 527287017 ps
CPU time 3.22 seconds
Started May 16 12:40:53 PM PDT 24
Finished May 16 12:41:01 PM PDT 24
Peak memory 193780 kb
Host smart-e1f090f2-6382-4dac-a1fe-64784629cce4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653674186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2653674186
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3290456826
Short name T484
Test name
Test status
Simulation time 20696824 ps
CPU time 0.58 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:41:25 PM PDT 24
Peak memory 182828 kb
Host smart-9983e037-61e7-43dc-93a2-4e2657a20480
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290456826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3290456826
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3240107221
Short name T538
Test name
Test status
Simulation time 39040876 ps
CPU time 0.85 seconds
Started May 16 12:40:56 PM PDT 24
Finished May 16 12:41:06 PM PDT 24
Peak memory 196836 kb
Host smart-9fb9e70c-3139-4a20-afa5-6eea969bbfd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240107221 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3240107221
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2215210896
Short name T83
Test name
Test status
Simulation time 23626648 ps
CPU time 0.62 seconds
Started May 16 12:40:59 PM PDT 24
Finished May 16 12:41:04 PM PDT 24
Peak memory 182588 kb
Host smart-fa085879-a8b4-4894-aca9-7065a6edc854
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215210896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2215210896
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.865469210
Short name T548
Test name
Test status
Simulation time 12818854 ps
CPU time 0.53 seconds
Started May 16 12:40:50 PM PDT 24
Finished May 16 12:40:54 PM PDT 24
Peak memory 181992 kb
Host smart-765987c7-b721-476b-a384-cb31d727ab1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865469210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.865469210
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2883814525
Short name T95
Test name
Test status
Simulation time 21751662 ps
CPU time 0.74 seconds
Started May 16 12:40:57 PM PDT 24
Finished May 16 12:41:02 PM PDT 24
Peak memory 191560 kb
Host smart-6cab5a2d-cd46-4c92-ba6a-7550d6a9e3f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883814525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2883814525
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.241613518
Short name T563
Test name
Test status
Simulation time 94530386 ps
CPU time 2.52 seconds
Started May 16 12:40:50 PM PDT 24
Finished May 16 12:40:56 PM PDT 24
Peak memory 197604 kb
Host smart-ce8a271d-9c4d-4669-8fff-1fff4d3813c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241613518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.241613518
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3780089765
Short name T96
Test name
Test status
Simulation time 281543574 ps
CPU time 1.39 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:02 PM PDT 24
Peak memory 195008 kb
Host smart-e54c04c4-0a88-4441-95c3-d3802f5cf6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780089765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3780089765
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.510511827
Short name T536
Test name
Test status
Simulation time 29593817 ps
CPU time 0.55 seconds
Started May 16 12:41:07 PM PDT 24
Finished May 16 12:41:10 PM PDT 24
Peak memory 182680 kb
Host smart-e02e24ed-6221-4cb9-93af-25d4977a465d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510511827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.510511827
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3411647515
Short name T510
Test name
Test status
Simulation time 23864859 ps
CPU time 0.54 seconds
Started May 16 12:41:14 PM PDT 24
Finished May 16 12:41:17 PM PDT 24
Peak memory 181900 kb
Host smart-0482465b-da51-4052-982c-71cf5c21a23d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411647515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3411647515
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.933804726
Short name T469
Test name
Test status
Simulation time 58897381 ps
CPU time 0.51 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:27 PM PDT 24
Peak memory 182072 kb
Host smart-0707840e-befe-4ed1-aaf4-887db274ab8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933804726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.933804726
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2606036450
Short name T535
Test name
Test status
Simulation time 11081181 ps
CPU time 0.54 seconds
Started May 16 12:41:14 PM PDT 24
Finished May 16 12:41:17 PM PDT 24
Peak memory 182680 kb
Host smart-21f523f5-0b0d-4f49-82c9-78868f132985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606036450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2606036450
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4184297041
Short name T573
Test name
Test status
Simulation time 49297280 ps
CPU time 0.55 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:41:30 PM PDT 24
Peak memory 182700 kb
Host smart-ad2988db-1c00-44ed-9a20-e80ec2fe5488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184297041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.4184297041
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.581195740
Short name T498
Test name
Test status
Simulation time 49656558 ps
CPU time 0.55 seconds
Started May 16 12:41:09 PM PDT 24
Finished May 16 12:41:12 PM PDT 24
Peak memory 182416 kb
Host smart-06dc0b38-03d4-428e-afd2-6ed24e25cfab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581195740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.581195740
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1893244418
Short name T533
Test name
Test status
Simulation time 46065554 ps
CPU time 0.53 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:41:30 PM PDT 24
Peak memory 182560 kb
Host smart-9825c1db-50f4-4985-a8a3-c39182827737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893244418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1893244418
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2621562265
Short name T530
Test name
Test status
Simulation time 28766830 ps
CPU time 0.54 seconds
Started May 16 12:41:31 PM PDT 24
Finished May 16 12:41:38 PM PDT 24
Peak memory 182768 kb
Host smart-ec3729b3-b02d-4ed1-83ad-3709e1c4df46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621562265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2621562265
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.749179997
Short name T453
Test name
Test status
Simulation time 52416554 ps
CPU time 0.55 seconds
Started May 16 12:41:16 PM PDT 24
Finished May 16 12:41:19 PM PDT 24
Peak memory 182652 kb
Host smart-2eb4f582-9bc1-4b0f-8f5d-a051d22ff76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749179997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.749179997
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.592671298
Short name T497
Test name
Test status
Simulation time 23913694 ps
CPU time 0.56 seconds
Started May 16 12:41:17 PM PDT 24
Finished May 16 12:41:20 PM PDT 24
Peak memory 182552 kb
Host smart-7c62ad14-2858-49bd-af68-3ac2584c3849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592671298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.592671298
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3989382413
Short name T571
Test name
Test status
Simulation time 154866754 ps
CPU time 0.59 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:01 PM PDT 24
Peak memory 182556 kb
Host smart-3663f086-fcf0-4180-96a7-947f44f89b1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989382413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3989382413
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1665402936
Short name T486
Test name
Test status
Simulation time 264338375 ps
CPU time 2.32 seconds
Started May 16 12:40:51 PM PDT 24
Finished May 16 12:40:58 PM PDT 24
Peak memory 193532 kb
Host smart-2181033b-af3b-4bbe-8c66-c1d377db58d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665402936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1665402936
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3174842593
Short name T543
Test name
Test status
Simulation time 18287157 ps
CPU time 0.58 seconds
Started May 16 12:40:54 PM PDT 24
Finished May 16 12:41:00 PM PDT 24
Peak memory 182560 kb
Host smart-a6c1f22c-1131-4f96-bb34-6cbc502184f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174842593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3174842593
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3277399722
Short name T574
Test name
Test status
Simulation time 23385077 ps
CPU time 0.65 seconds
Started May 16 12:41:00 PM PDT 24
Finished May 16 12:41:05 PM PDT 24
Peak memory 194264 kb
Host smart-8da468f4-c42e-487d-b8dd-a6a7193fc5f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277399722 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3277399722
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1233839396
Short name T45
Test name
Test status
Simulation time 20733739 ps
CPU time 0.54 seconds
Started May 16 12:41:11 PM PDT 24
Finished May 16 12:41:14 PM PDT 24
Peak memory 182572 kb
Host smart-6c0961f9-c4cc-472e-ab7f-87fefe726f68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233839396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1233839396
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3109663753
Short name T520
Test name
Test status
Simulation time 44897479 ps
CPU time 0.55 seconds
Started May 16 12:41:00 PM PDT 24
Finished May 16 12:41:05 PM PDT 24
Peak memory 182540 kb
Host smart-b4bdd0c3-f82a-470f-8373-8b9c7809df9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109663753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3109663753
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.337769212
Short name T560
Test name
Test status
Simulation time 157985993 ps
CPU time 0.66 seconds
Started May 16 12:40:54 PM PDT 24
Finished May 16 12:41:00 PM PDT 24
Peak memory 191620 kb
Host smart-05df4eae-f9fd-46db-8371-11ed3ad538e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337769212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.337769212
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2690589860
Short name T57
Test name
Test status
Simulation time 178758570 ps
CPU time 1.65 seconds
Started May 16 12:41:14 PM PDT 24
Finished May 16 12:41:19 PM PDT 24
Peak memory 197436 kb
Host smart-5ccd9cfc-82ae-4deb-8798-9a808dbd565f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690589860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2690589860
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2456565821
Short name T101
Test name
Test status
Simulation time 116868686 ps
CPU time 1.3 seconds
Started May 16 12:41:00 PM PDT 24
Finished May 16 12:41:06 PM PDT 24
Peak memory 195344 kb
Host smart-b388840c-9aa7-45e6-8c2a-5296d91777f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456565821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2456565821
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2614797589
Short name T480
Test name
Test status
Simulation time 18296521 ps
CPU time 0.56 seconds
Started May 16 12:41:06 PM PDT 24
Finished May 16 12:41:10 PM PDT 24
Peak memory 182440 kb
Host smart-0ce58a8d-917f-4b8e-a058-3cf8c7fa73a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614797589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2614797589
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1573399515
Short name T499
Test name
Test status
Simulation time 20881426 ps
CPU time 0.63 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:26 PM PDT 24
Peak memory 182448 kb
Host smart-c2901696-3dd2-47a0-a653-aaebabcef1dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573399515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1573399515
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3736320002
Short name T500
Test name
Test status
Simulation time 28642267 ps
CPU time 0.53 seconds
Started May 16 12:41:31 PM PDT 24
Finished May 16 12:41:37 PM PDT 24
Peak memory 182644 kb
Host smart-28603aba-2b33-4719-957b-4cbee5306023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736320002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3736320002
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1054410212
Short name T485
Test name
Test status
Simulation time 27592810 ps
CPU time 0.58 seconds
Started May 16 12:41:13 PM PDT 24
Finished May 16 12:41:16 PM PDT 24
Peak memory 182568 kb
Host smart-449b2b9c-7487-4d71-8a83-562663f3f4bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054410212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1054410212
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4203922099
Short name T531
Test name
Test status
Simulation time 43442590 ps
CPU time 0.56 seconds
Started May 16 12:41:15 PM PDT 24
Finished May 16 12:41:19 PM PDT 24
Peak memory 182496 kb
Host smart-5b82ed68-2c5f-47d3-b606-2e599e3936a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203922099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4203922099
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3542400923
Short name T454
Test name
Test status
Simulation time 32917542 ps
CPU time 0.55 seconds
Started May 16 12:41:31 PM PDT 24
Finished May 16 12:41:38 PM PDT 24
Peak memory 182580 kb
Host smart-765fd5e4-20aa-4330-b269-b91374172da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542400923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3542400923
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3823331355
Short name T466
Test name
Test status
Simulation time 27341973 ps
CPU time 0.54 seconds
Started May 16 12:41:17 PM PDT 24
Finished May 16 12:41:20 PM PDT 24
Peak memory 182484 kb
Host smart-c94e21be-edbf-4c10-b47f-d807d193cd1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823331355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3823331355
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1382186734
Short name T459
Test name
Test status
Simulation time 44338716 ps
CPU time 0.54 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:26 PM PDT 24
Peak memory 181868 kb
Host smart-f84b7ba4-9f9f-4993-a9ac-563a8f516bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382186734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1382186734
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3051728169
Short name T532
Test name
Test status
Simulation time 27606881 ps
CPU time 0.6 seconds
Started May 16 12:41:00 PM PDT 24
Finished May 16 12:41:05 PM PDT 24
Peak memory 182496 kb
Host smart-7d7fe6b6-7192-4d57-a4ff-e7a94aa15404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051728169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3051728169
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3441674659
Short name T502
Test name
Test status
Simulation time 14308921 ps
CPU time 0.52 seconds
Started May 16 12:41:18 PM PDT 24
Finished May 16 12:41:21 PM PDT 24
Peak memory 182540 kb
Host smart-a3813bee-78d1-4858-ad17-96cab7502b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441674659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3441674659
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4274232518
Short name T468
Test name
Test status
Simulation time 36220514 ps
CPU time 0.69 seconds
Started May 16 12:40:54 PM PDT 24
Finished May 16 12:40:59 PM PDT 24
Peak memory 191780 kb
Host smart-aae47056-caae-4694-b3d0-c2912721a5b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274232518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.4274232518
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3427635015
Short name T46
Test name
Test status
Simulation time 689343077 ps
CPU time 3.71 seconds
Started May 16 12:40:56 PM PDT 24
Finished May 16 12:41:05 PM PDT 24
Peak memory 193880 kb
Host smart-f6df8caa-9a2e-4f3c-967e-aa92fcec59d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427635015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3427635015
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.4084577782
Short name T88
Test name
Test status
Simulation time 62922769 ps
CPU time 0.59 seconds
Started May 16 12:40:57 PM PDT 24
Finished May 16 12:41:03 PM PDT 24
Peak memory 182692 kb
Host smart-0bf01bd9-04e0-438c-876c-531214170bab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084577782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.4084577782
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1640579604
Short name T577
Test name
Test status
Simulation time 30131660 ps
CPU time 0.83 seconds
Started May 16 12:40:53 PM PDT 24
Finished May 16 12:40:59 PM PDT 24
Peak memory 195276 kb
Host smart-446deaf2-7b88-4416-86f6-0134f50b5cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640579604 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1640579604
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4163909909
Short name T501
Test name
Test status
Simulation time 38301065 ps
CPU time 0.55 seconds
Started May 16 12:40:59 PM PDT 24
Finished May 16 12:41:04 PM PDT 24
Peak memory 182528 kb
Host smart-8f3fe7b8-105d-474c-b683-c112cb30aed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163909909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.4163909909
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2930578715
Short name T518
Test name
Test status
Simulation time 13348723 ps
CPU time 0.54 seconds
Started May 16 12:40:54 PM PDT 24
Finished May 16 12:40:59 PM PDT 24
Peak memory 182064 kb
Host smart-3302e644-1961-4fba-881a-18c130a2d779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930578715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2930578715
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.252178209
Short name T91
Test name
Test status
Simulation time 55206877 ps
CPU time 0.78 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:41:31 PM PDT 24
Peak memory 193292 kb
Host smart-ef14b9a4-96f8-4568-a25c-f0af71547eeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252178209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.252178209
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4117322926
Short name T523
Test name
Test status
Simulation time 153638546 ps
CPU time 2.71 seconds
Started May 16 12:40:56 PM PDT 24
Finished May 16 12:41:04 PM PDT 24
Peak memory 197612 kb
Host smart-0da0a6bd-4f70-43e6-901b-62328b2d1f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117322926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.4117322926
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.123553725
Short name T98
Test name
Test status
Simulation time 849739966 ps
CPU time 0.8 seconds
Started May 16 12:41:32 PM PDT 24
Finished May 16 12:41:40 PM PDT 24
Peak memory 182960 kb
Host smart-835c8471-a12e-4294-b95a-0263a562dd72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123553725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.123553725
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2879730654
Short name T539
Test name
Test status
Simulation time 12710525 ps
CPU time 0.53 seconds
Started May 16 12:41:26 PM PDT 24
Finished May 16 12:41:33 PM PDT 24
Peak memory 182616 kb
Host smart-bca82b87-c69f-42e8-acc4-5c710d123f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879730654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2879730654
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1785592321
Short name T517
Test name
Test status
Simulation time 52537434 ps
CPU time 0.58 seconds
Started May 16 12:41:13 PM PDT 24
Finished May 16 12:41:15 PM PDT 24
Peak memory 182508 kb
Host smart-86ae6267-0bff-452e-bd40-4f59bae9c4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785592321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1785592321
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.459155032
Short name T474
Test name
Test status
Simulation time 31379998 ps
CPU time 0.55 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:41:34 PM PDT 24
Peak memory 182556 kb
Host smart-7c88e538-07ba-4fc5-bb37-3ce039686728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459155032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.459155032
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3080772300
Short name T483
Test name
Test status
Simulation time 16235282 ps
CPU time 0.56 seconds
Started May 16 12:41:18 PM PDT 24
Finished May 16 12:41:21 PM PDT 24
Peak memory 182456 kb
Host smart-e96c13e9-14f4-477e-86a0-137777e35913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080772300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3080772300
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.904561127
Short name T482
Test name
Test status
Simulation time 41426195 ps
CPU time 0.52 seconds
Started May 16 12:41:22 PM PDT 24
Finished May 16 12:41:28 PM PDT 24
Peak memory 182060 kb
Host smart-85254a04-91f6-48a2-a8e2-abd271c25d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904561127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.904561127
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2892581948
Short name T559
Test name
Test status
Simulation time 80622212 ps
CPU time 0.56 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:41:31 PM PDT 24
Peak memory 182568 kb
Host smart-95859a46-a736-4bd3-b1a3-a5f94da8d364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892581948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2892581948
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3877782549
Short name T565
Test name
Test status
Simulation time 11940673 ps
CPU time 0.54 seconds
Started May 16 12:41:27 PM PDT 24
Finished May 16 12:41:34 PM PDT 24
Peak memory 182544 kb
Host smart-85299394-5b4d-446c-ab90-a5a1d378832f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877782549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3877782549
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.72579167
Short name T463
Test name
Test status
Simulation time 53870678 ps
CPU time 0.57 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:41:30 PM PDT 24
Peak memory 182460 kb
Host smart-d8739cdb-889e-4686-816c-bbbe159d14a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72579167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.72579167
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2950539360
Short name T541
Test name
Test status
Simulation time 11958982 ps
CPU time 0.55 seconds
Started May 16 12:41:18 PM PDT 24
Finished May 16 12:41:22 PM PDT 24
Peak memory 182420 kb
Host smart-db9ff2cb-a6c0-475e-9c87-e5037ae710d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950539360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2950539360
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1574147558
Short name T527
Test name
Test status
Simulation time 13806492 ps
CPU time 0.53 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:41:23 PM PDT 24
Peak memory 182052 kb
Host smart-337a8851-5fc1-4c37-b7cd-6fd614845fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574147558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1574147558
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.285962743
Short name T460
Test name
Test status
Simulation time 29810546 ps
CPU time 0.83 seconds
Started May 16 12:41:10 PM PDT 24
Finished May 16 12:41:14 PM PDT 24
Peak memory 196792 kb
Host smart-1ff78fbe-08f4-44e8-8669-1e211493ede6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285962743 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.285962743
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3574528792
Short name T81
Test name
Test status
Simulation time 45885983 ps
CPU time 0.56 seconds
Started May 16 12:40:54 PM PDT 24
Finished May 16 12:40:59 PM PDT 24
Peak memory 182696 kb
Host smart-6e881247-7784-49c6-a68c-79ca1b5e9791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574528792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3574528792
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3450260207
Short name T473
Test name
Test status
Simulation time 55168629 ps
CPU time 0.53 seconds
Started May 16 12:40:56 PM PDT 24
Finished May 16 12:41:10 PM PDT 24
Peak memory 182060 kb
Host smart-8727a865-07e5-4832-8ee6-4b80070c007c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450260207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3450260207
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3556550280
Short name T33
Test name
Test status
Simulation time 20788353 ps
CPU time 0.59 seconds
Started May 16 12:41:03 PM PDT 24
Finished May 16 12:41:07 PM PDT 24
Peak memory 191240 kb
Host smart-bef99614-088c-45fc-a214-4a7f08f192ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556550280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3556550280
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.352286021
Short name T457
Test name
Test status
Simulation time 50629540 ps
CPU time 1.28 seconds
Started May 16 12:40:53 PM PDT 24
Finished May 16 12:41:00 PM PDT 24
Peak memory 197260 kb
Host smart-39ea5031-3a4f-4efe-ae93-2d9a74535199
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352286021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.352286021
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.957803556
Short name T566
Test name
Test status
Simulation time 42381623 ps
CPU time 0.83 seconds
Started May 16 12:40:51 PM PDT 24
Finished May 16 12:40:56 PM PDT 24
Peak memory 193600 kb
Host smart-44e5d55b-99bd-4916-88c3-84e03565c3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957803556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.957803556
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3340949576
Short name T553
Test name
Test status
Simulation time 50102723 ps
CPU time 0.72 seconds
Started May 16 12:40:52 PM PDT 24
Finished May 16 12:40:57 PM PDT 24
Peak memory 194308 kb
Host smart-9d1ab31c-1ba1-422c-862a-3841be576148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340949576 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3340949576
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.342993828
Short name T562
Test name
Test status
Simulation time 22434909 ps
CPU time 0.54 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:01 PM PDT 24
Peak memory 182660 kb
Host smart-f66460f5-ca5d-42a3-a988-be6802d0ad6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342993828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.342993828
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.586451075
Short name T512
Test name
Test status
Simulation time 12240077 ps
CPU time 0.57 seconds
Started May 16 12:40:49 PM PDT 24
Finished May 16 12:40:53 PM PDT 24
Peak memory 182576 kb
Host smart-0d57982a-9e5a-473d-94ac-1eb539d2a03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586451075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.586451075
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1268664887
Short name T551
Test name
Test status
Simulation time 164435004 ps
CPU time 0.75 seconds
Started May 16 12:41:05 PM PDT 24
Finished May 16 12:41:09 PM PDT 24
Peak memory 193304 kb
Host smart-f18d4d3b-0b85-4399-aacc-d224cf511270
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268664887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1268664887
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2699407757
Short name T464
Test name
Test status
Simulation time 278239319 ps
CPU time 3.1 seconds
Started May 16 12:41:10 PM PDT 24
Finished May 16 12:41:15 PM PDT 24
Peak memory 197544 kb
Host smart-4a1c7d3c-9bbf-490d-9b49-260b967a61c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699407757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2699407757
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.539867424
Short name T487
Test name
Test status
Simulation time 130656079 ps
CPU time 0.85 seconds
Started May 16 12:40:52 PM PDT 24
Finished May 16 12:40:58 PM PDT 24
Peak memory 193392 kb
Host smart-71db642d-0057-4be7-8d52-17a27d6c0c85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539867424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.539867424
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2088157944
Short name T505
Test name
Test status
Simulation time 93382267 ps
CPU time 0.73 seconds
Started May 16 12:41:10 PM PDT 24
Finished May 16 12:41:13 PM PDT 24
Peak memory 195424 kb
Host smart-34b41ce6-3b71-4cd8-ac85-181f7afafff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088157944 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2088157944
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.947213315
Short name T488
Test name
Test status
Simulation time 13162780 ps
CPU time 0.53 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:00 PM PDT 24
Peak memory 182588 kb
Host smart-042c5a8f-4df1-4f69-95cf-2546997c8f4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947213315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.947213315
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.866414129
Short name T540
Test name
Test status
Simulation time 17966119 ps
CPU time 0.56 seconds
Started May 16 12:40:50 PM PDT 24
Finished May 16 12:40:54 PM PDT 24
Peak memory 182396 kb
Host smart-a645c556-07f4-43e8-b331-04e6731b1914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866414129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.866414129
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2176435979
Short name T509
Test name
Test status
Simulation time 30906140 ps
CPU time 0.82 seconds
Started May 16 12:40:54 PM PDT 24
Finished May 16 12:40:59 PM PDT 24
Peak memory 191536 kb
Host smart-11005450-4c61-4407-bed6-d0f6e699524a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176435979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2176435979
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4137903232
Short name T472
Test name
Test status
Simulation time 212671800 ps
CPU time 2.19 seconds
Started May 16 12:41:05 PM PDT 24
Finished May 16 12:41:11 PM PDT 24
Peak memory 197464 kb
Host smart-a48955ac-6c8b-4766-a8ea-60fb2a7b4cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137903232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4137903232
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4263793892
Short name T519
Test name
Test status
Simulation time 285119873 ps
CPU time 1.1 seconds
Started May 16 12:40:59 PM PDT 24
Finished May 16 12:41:05 PM PDT 24
Peak memory 194840 kb
Host smart-c6591274-5fdf-42b6-9f39-7de079cb2982
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263793892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.4263793892
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3392792082
Short name T575
Test name
Test status
Simulation time 30461832 ps
CPU time 0.84 seconds
Started May 16 12:41:01 PM PDT 24
Finished May 16 12:41:06 PM PDT 24
Peak memory 195852 kb
Host smart-54de1761-76bd-4dda-90f9-ba13191befea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392792082 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3392792082
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.67508914
Short name T85
Test name
Test status
Simulation time 80979633 ps
CPU time 0.54 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:41:24 PM PDT 24
Peak memory 182728 kb
Host smart-f10ddc98-8055-4399-b7cd-bf7c391a6c71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67508914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.67508914
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.66775978
Short name T556
Test name
Test status
Simulation time 15129339 ps
CPU time 0.58 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:01 PM PDT 24
Peak memory 182404 kb
Host smart-439afe26-ba37-4fde-a83e-034c63ab5bbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66775978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.66775978
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3239217502
Short name T94
Test name
Test status
Simulation time 96605279 ps
CPU time 0.73 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:00 PM PDT 24
Peak memory 191696 kb
Host smart-60cac67b-20ef-496f-ae47-a8244ebd8903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239217502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3239217502
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3912757077
Short name T547
Test name
Test status
Simulation time 335679323 ps
CPU time 1.92 seconds
Started May 16 12:41:07 PM PDT 24
Finished May 16 12:41:12 PM PDT 24
Peak memory 197600 kb
Host smart-c646480e-7367-4e8f-93a2-bbad77b042fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912757077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3912757077
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2635675420
Short name T29
Test name
Test status
Simulation time 95648405 ps
CPU time 1.04 seconds
Started May 16 12:40:56 PM PDT 24
Finished May 16 12:41:02 PM PDT 24
Peak memory 195164 kb
Host smart-18a8e7de-498e-4340-a109-3a9ac4a3be1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635675420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2635675420
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3499091563
Short name T48
Test name
Test status
Simulation time 35908902 ps
CPU time 0.81 seconds
Started May 16 12:40:55 PM PDT 24
Finished May 16 12:41:05 PM PDT 24
Peak memory 196852 kb
Host smart-d844d222-a194-4372-85c2-61a26d854bf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499091563 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3499091563
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.467541500
Short name T514
Test name
Test status
Simulation time 13902840 ps
CPU time 0.57 seconds
Started May 16 12:41:05 PM PDT 24
Finished May 16 12:41:09 PM PDT 24
Peak memory 182676 kb
Host smart-098d25d0-5003-4f7a-9c1a-e772b3c1e091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467541500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.467541500
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3697560531
Short name T578
Test name
Test status
Simulation time 65583546 ps
CPU time 0.55 seconds
Started May 16 12:40:53 PM PDT 24
Finished May 16 12:40:58 PM PDT 24
Peak memory 182712 kb
Host smart-23476cb6-2565-4353-8b43-5e9e809ee833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697560531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3697560531
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3878671843
Short name T511
Test name
Test status
Simulation time 36158851 ps
CPU time 0.87 seconds
Started May 16 12:41:01 PM PDT 24
Finished May 16 12:41:06 PM PDT 24
Peak memory 191588 kb
Host smart-deb6e989-430d-44fe-83e9-ccaac49ad9d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878671843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3878671843
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3316605494
Short name T525
Test name
Test status
Simulation time 181043859 ps
CPU time 1.76 seconds
Started May 16 12:41:06 PM PDT 24
Finished May 16 12:41:11 PM PDT 24
Peak memory 197544 kb
Host smart-eb609b27-405b-44e8-99be-bc706f321f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316605494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3316605494
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1714221797
Short name T495
Test name
Test status
Simulation time 48382180 ps
CPU time 0.83 seconds
Started May 16 12:40:44 PM PDT 24
Finished May 16 12:40:47 PM PDT 24
Peak memory 183112 kb
Host smart-a471f1a0-afac-4e89-a344-ff6f27b5f890
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714221797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1714221797
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3161037861
Short name T407
Test name
Test status
Simulation time 192851902501 ps
CPU time 301.93 seconds
Started May 16 12:41:18 PM PDT 24
Finished May 16 12:46:22 PM PDT 24
Peak memory 182508 kb
Host smart-ff4fd097-89ac-4638-b10e-1702240bbaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161037861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3161037861
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1720260287
Short name T296
Test name
Test status
Simulation time 169584005836 ps
CPU time 167.98 seconds
Started May 16 12:41:06 PM PDT 24
Finished May 16 12:43:57 PM PDT 24
Peak memory 182568 kb
Host smart-1c9475d2-cd8f-492e-b7a8-8685cde7cf0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720260287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1720260287
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.432526687
Short name T381
Test name
Test status
Simulation time 716545919 ps
CPU time 0.79 seconds
Started May 16 12:41:12 PM PDT 24
Finished May 16 12:41:15 PM PDT 24
Peak memory 190792 kb
Host smart-1b1fa76e-6674-4fb9-8a13-fc3af4d6aac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432526687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.432526687
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.912419980
Short name T294
Test name
Test status
Simulation time 573867151541 ps
CPU time 292.88 seconds
Started May 16 12:41:38 PM PDT 24
Finished May 16 12:46:38 PM PDT 24
Peak memory 182540 kb
Host smart-d44b278b-08ff-4296-8fe9-c02e1d9f2615
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912419980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.912419980
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2558910930
Short name T364
Test name
Test status
Simulation time 177727359201 ps
CPU time 140.1 seconds
Started May 16 12:41:38 PM PDT 24
Finished May 16 12:44:05 PM PDT 24
Peak memory 182624 kb
Host smart-7c4aae45-abf2-46a6-aad9-68f625c05455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558910930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2558910930
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.986450360
Short name T403
Test name
Test status
Simulation time 167370622856 ps
CPU time 201.03 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:44:55 PM PDT 24
Peak memory 182640 kb
Host smart-4e37f3ce-5f2f-46cb-a5ff-dc10409b2479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986450360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.986450360
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1440694959
Short name T410
Test name
Test status
Simulation time 6169988278 ps
CPU time 54.35 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:42:17 PM PDT 24
Peak memory 182492 kb
Host smart-6994e2fa-27a2-4c68-95ba-bf2c0d646050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440694959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1440694959
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.521927600
Short name T16
Test name
Test status
Simulation time 240436829 ps
CPU time 1.12 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:27 PM PDT 24
Peak memory 214136 kb
Host smart-df673cd8-2a1b-4a53-a169-5e263de501e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521927600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.521927600
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1443253916
Short name T413
Test name
Test status
Simulation time 111419814003 ps
CPU time 169.58 seconds
Started May 16 12:41:18 PM PDT 24
Finished May 16 12:44:11 PM PDT 24
Peak memory 190708 kb
Host smart-c0e90479-adf7-41c5-a49d-4fe5fba66cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443253916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1443253916
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1015170118
Short name T181
Test name
Test status
Simulation time 774027004129 ps
CPU time 355.68 seconds
Started May 16 12:41:33 PM PDT 24
Finished May 16 12:47:36 PM PDT 24
Peak memory 182620 kb
Host smart-3f16db33-46ea-4ba9-bd34-ceffacd07cd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015170118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1015170118
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.443375604
Short name T378
Test name
Test status
Simulation time 79156537980 ps
CPU time 21.83 seconds
Started May 16 12:41:18 PM PDT 24
Finished May 16 12:41:42 PM PDT 24
Peak memory 182608 kb
Host smart-44c184ba-e7dd-4f20-aab8-729c7d536eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443375604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.443375604
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2697262635
Short name T135
Test name
Test status
Simulation time 128320590180 ps
CPU time 35.13 seconds
Started May 16 12:41:40 PM PDT 24
Finished May 16 12:42:22 PM PDT 24
Peak memory 182604 kb
Host smart-66da9c12-a990-4558-8101-bfcc2792a80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697262635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2697262635
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.755965375
Short name T2
Test name
Test status
Simulation time 3864029229 ps
CPU time 6.84 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:41:54 PM PDT 24
Peak memory 190804 kb
Host smart-6d145bb2-89e9-4212-aaf4-33fe715f5e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755965375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.755965375
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3359764684
Short name T144
Test name
Test status
Simulation time 910253996652 ps
CPU time 154.51 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:44:00 PM PDT 24
Peak memory 190476 kb
Host smart-cdd9bb31-57af-42c2-956f-9679288c598a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359764684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3359764684
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2993729502
Short name T34
Test name
Test status
Simulation time 256645795564 ps
CPU time 902.11 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:56:28 PM PDT 24
Peak memory 199676 kb
Host smart-acdb763e-e6ae-491f-bc83-60bfe00b6517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993729502 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2993729502
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.318933241
Short name T1
Test name
Test status
Simulation time 643753675180 ps
CPU time 576.69 seconds
Started May 16 12:42:03 PM PDT 24
Finished May 16 12:51:46 PM PDT 24
Peak memory 190796 kb
Host smart-2aa4380d-89ad-4552-b56c-6310ba729c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318933241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.318933241
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2750209205
Short name T307
Test name
Test status
Simulation time 60838351089 ps
CPU time 121.7 seconds
Started May 16 12:42:00 PM PDT 24
Finished May 16 12:44:08 PM PDT 24
Peak memory 190704 kb
Host smart-2f37780e-a5a7-4895-9ab7-b601b9b32168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750209205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2750209205
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.9170334
Short name T271
Test name
Test status
Simulation time 115626344149 ps
CPU time 185.46 seconds
Started May 16 12:41:54 PM PDT 24
Finished May 16 12:45:07 PM PDT 24
Peak memory 190720 kb
Host smart-2791666f-3ab1-4bfd-9cf7-a191ebf701ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9170334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.9170334
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1681362878
Short name T166
Test name
Test status
Simulation time 471290888233 ps
CPU time 313.35 seconds
Started May 16 12:41:53 PM PDT 24
Finished May 16 12:47:15 PM PDT 24
Peak memory 190660 kb
Host smart-24d3c522-f1be-4c8f-81f2-47993734867d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681362878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1681362878
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.4065492620
Short name T304
Test name
Test status
Simulation time 20066638720 ps
CPU time 34.35 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:42:02 PM PDT 24
Peak memory 182492 kb
Host smart-d72107a2-89d1-4e73-aa40-1589b74c7a95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065492620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.4065492620
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1161117690
Short name T392
Test name
Test status
Simulation time 189402649589 ps
CPU time 75.75 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:42:39 PM PDT 24
Peak memory 182548 kb
Host smart-c5b1c414-22ff-427e-a981-11cefbb8ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161117690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1161117690
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3206637603
Short name T121
Test name
Test status
Simulation time 89526491782 ps
CPU time 80.87 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:43:08 PM PDT 24
Peak memory 182600 kb
Host smart-d6a69d21-95c7-4200-9549-a4ce900f5d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206637603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3206637603
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.13760789
Short name T349
Test name
Test status
Simulation time 108171914462 ps
CPU time 569.57 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:50:54 PM PDT 24
Peak memory 182496 kb
Host smart-dff097df-32e0-471e-9684-0a40eaaa9195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13760789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.13760789
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.273688984
Short name T109
Test name
Test status
Simulation time 537928611524 ps
CPU time 586.17 seconds
Started May 16 12:41:54 PM PDT 24
Finished May 16 12:51:48 PM PDT 24
Peak memory 190700 kb
Host smart-666a1fca-7ffc-4256-9549-57299b78c62c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273688984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.273688984
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.733818477
Short name T427
Test name
Test status
Simulation time 75487957357 ps
CPU time 104.2 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:43:43 PM PDT 24
Peak memory 190820 kb
Host smart-d05d7b33-88b1-4daa-a42b-177a8832a5ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733818477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.733818477
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2297022350
Short name T232
Test name
Test status
Simulation time 948570920788 ps
CPU time 351.39 seconds
Started May 16 12:42:09 PM PDT 24
Finished May 16 12:48:05 PM PDT 24
Peak memory 190704 kb
Host smart-37546c5a-ea14-4cf9-96bb-5449486c4248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297022350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2297022350
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.4226595083
Short name T131
Test name
Test status
Simulation time 231899214274 ps
CPU time 539.15 seconds
Started May 16 12:42:00 PM PDT 24
Finished May 16 12:51:06 PM PDT 24
Peak memory 190776 kb
Host smart-c7bf8b8e-ba75-47fe-af8f-7defff88d2c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226595083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.4226595083
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3220128118
Short name T145
Test name
Test status
Simulation time 81069517137 ps
CPU time 85.2 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:43:25 PM PDT 24
Peak memory 190720 kb
Host smart-2d08ab14-45ee-4baa-88d1-a44785f1cdbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220128118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3220128118
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1193449159
Short name T259
Test name
Test status
Simulation time 52712961450 ps
CPU time 95.44 seconds
Started May 16 12:42:00 PM PDT 24
Finished May 16 12:43:42 PM PDT 24
Peak memory 190700 kb
Host smart-3d5ae64b-4f5d-4bf4-a8b9-8607d4091dff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193449159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1193449159
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1493326309
Short name T115
Test name
Test status
Simulation time 36241174401 ps
CPU time 74.28 seconds
Started May 16 12:42:00 PM PDT 24
Finished May 16 12:43:21 PM PDT 24
Peak memory 190708 kb
Host smart-93ebd8c0-5823-4ad1-a57e-9c6ef277cbdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493326309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1493326309
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3243775776
Short name T317
Test name
Test status
Simulation time 22417298245 ps
CPU time 189.16 seconds
Started May 16 12:42:05 PM PDT 24
Finished May 16 12:45:20 PM PDT 24
Peak memory 182568 kb
Host smart-3043e2e1-50f2-488f-b085-6e7d2f3d5894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243775776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3243775776
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1123528770
Short name T314
Test name
Test status
Simulation time 1616900595381 ps
CPU time 1038.32 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:58:49 PM PDT 24
Peak memory 182616 kb
Host smart-ddab8505-cad3-42ae-8838-2bb2ea8294fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123528770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1123528770
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.4282999151
Short name T380
Test name
Test status
Simulation time 247995242753 ps
CPU time 136.33 seconds
Started May 16 12:41:09 PM PDT 24
Finished May 16 12:43:29 PM PDT 24
Peak memory 182540 kb
Host smart-460660c8-e9a4-47ba-bef9-d7b721e83a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282999151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.4282999151
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1848334946
Short name T269
Test name
Test status
Simulation time 92085306045 ps
CPU time 66.15 seconds
Started May 16 12:41:15 PM PDT 24
Finished May 16 12:42:24 PM PDT 24
Peak memory 182612 kb
Host smart-f5f73318-f7d7-46bd-bbfd-16399009ee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848334946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1848334946
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.321927060
Short name T55
Test name
Test status
Simulation time 168583024179 ps
CPU time 77.35 seconds
Started May 16 12:42:07 PM PDT 24
Finished May 16 12:43:29 PM PDT 24
Peak memory 190776 kb
Host smart-b7178110-e741-4183-9eae-a49ba6593084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321927060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.321927060
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1047905591
Short name T188
Test name
Test status
Simulation time 46678301625 ps
CPU time 138.42 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:44:37 PM PDT 24
Peak memory 190628 kb
Host smart-2c1f7878-a8fa-491c-a7c4-1ec08b6f20dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047905591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1047905591
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1108255114
Short name T5
Test name
Test status
Simulation time 72669561254 ps
CPU time 108.55 seconds
Started May 16 12:42:01 PM PDT 24
Finished May 16 12:43:56 PM PDT 24
Peak memory 190708 kb
Host smart-1da61b29-22c6-4672-835b-b63cbe6d1e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108255114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1108255114
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2772846915
Short name T164
Test name
Test status
Simulation time 540471217524 ps
CPU time 234.99 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:45:56 PM PDT 24
Peak memory 190776 kb
Host smart-615a7ae1-63c7-4842-bfdc-7f7899374734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772846915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2772846915
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1186783480
Short name T355
Test name
Test status
Simulation time 155015961108 ps
CPU time 1608.37 seconds
Started May 16 12:41:57 PM PDT 24
Finished May 16 01:08:53 PM PDT 24
Peak memory 190760 kb
Host smart-79fc98d0-b3f4-490f-bbb9-11194bfccb6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186783480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1186783480
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.886445481
Short name T217
Test name
Test status
Simulation time 25523240143 ps
CPU time 193.67 seconds
Started May 16 12:42:04 PM PDT 24
Finished May 16 12:45:23 PM PDT 24
Peak memory 182508 kb
Host smart-fc552c10-9730-4749-a788-e8b21e79b48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886445481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.886445481
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3635324008
Short name T191
Test name
Test status
Simulation time 295535934730 ps
CPU time 260.99 seconds
Started May 16 12:42:08 PM PDT 24
Finished May 16 12:46:33 PM PDT 24
Peak memory 190788 kb
Host smart-7f47c910-0bd8-47d0-b1f4-87e261a59378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635324008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3635324008
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4135565680
Short name T266
Test name
Test status
Simulation time 57143448011 ps
CPU time 64.62 seconds
Started May 16 12:41:58 PM PDT 24
Finished May 16 12:43:09 PM PDT 24
Peak memory 190792 kb
Host smart-6ac8e332-a005-4147-be68-d382fa369a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135565680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4135565680
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.264598743
Short name T120
Test name
Test status
Simulation time 270285350687 ps
CPU time 482.97 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 12:49:45 PM PDT 24
Peak memory 182500 kb
Host smart-a216af76-6360-46f6-882a-d9b17b1c089a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264598743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.264598743
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3554186797
Short name T417
Test name
Test status
Simulation time 324393912356 ps
CPU time 147.87 seconds
Started May 16 12:41:32 PM PDT 24
Finished May 16 12:44:05 PM PDT 24
Peak memory 182512 kb
Host smart-4e52062e-7d9b-46c7-8144-eb3743f68e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554186797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3554186797
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1324470047
Short name T204
Test name
Test status
Simulation time 77865933165 ps
CPU time 238.73 seconds
Started May 16 12:41:44 PM PDT 24
Finished May 16 12:45:50 PM PDT 24
Peak memory 190908 kb
Host smart-ce506289-3889-454f-bd18-47fbe39e2404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324470047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1324470047
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3153902486
Short name T390
Test name
Test status
Simulation time 431598320933 ps
CPU time 200.41 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:44:47 PM PDT 24
Peak memory 194060 kb
Host smart-1d22fb84-06cb-4af9-bad8-03bb7aae7a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153902486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3153902486
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/134.rv_timer_random.1014125163
Short name T227
Test name
Test status
Simulation time 402078480480 ps
CPU time 173.4 seconds
Started May 16 12:41:54 PM PDT 24
Finished May 16 12:44:55 PM PDT 24
Peak memory 190792 kb
Host smart-3458389c-f927-4ff1-b40f-fc44493b7190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014125163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1014125163
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2204130893
Short name T184
Test name
Test status
Simulation time 96462819060 ps
CPU time 140.44 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:44:37 PM PDT 24
Peak memory 190768 kb
Host smart-506817b6-08db-4d10-8530-8d6e14836467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204130893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2204130893
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.510379500
Short name T265
Test name
Test status
Simulation time 13143155372 ps
CPU time 18.62 seconds
Started May 16 12:41:26 PM PDT 24
Finished May 16 12:41:50 PM PDT 24
Peak memory 182496 kb
Host smart-4981ef50-8f4f-4bb0-a7d6-c43edc5c8f09
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510379500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.510379500
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2502076455
Short name T400
Test name
Test status
Simulation time 158101981215 ps
CPU time 125.49 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:43:39 PM PDT 24
Peak memory 182608 kb
Host smart-fb956198-3cc8-44db-865c-32a267da33e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502076455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2502076455
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3042985415
Short name T289
Test name
Test status
Simulation time 101613450272 ps
CPU time 60.19 seconds
Started May 16 12:41:27 PM PDT 24
Finished May 16 12:42:33 PM PDT 24
Peak memory 190804 kb
Host smart-07281fa7-de32-417f-8969-d82af6d8e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042985415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3042985415
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1705635677
Short name T386
Test name
Test status
Simulation time 187403137920 ps
CPU time 104.18 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:43:07 PM PDT 24
Peak memory 194028 kb
Host smart-f469348f-ec55-4d73-a067-351c94280023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705635677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1705635677
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.1621059438
Short name T323
Test name
Test status
Simulation time 4780785880 ps
CPU time 5 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:42:22 PM PDT 24
Peak memory 182468 kb
Host smart-0e189f3c-fa82-4508-9d5c-d3aede15630e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621059438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1621059438
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3070197981
Short name T415
Test name
Test status
Simulation time 18445865680 ps
CPU time 35.08 seconds
Started May 16 12:42:21 PM PDT 24
Finished May 16 12:42:59 PM PDT 24
Peak memory 182532 kb
Host smart-215f4f01-dfaa-4997-869a-f4711f6484ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070197981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3070197981
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3831076774
Short name T273
Test name
Test status
Simulation time 129677689791 ps
CPU time 160.54 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:45:01 PM PDT 24
Peak memory 190696 kb
Host smart-c767d744-16ac-4a6f-89d5-1e3adee6d32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831076774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3831076774
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1047792310
Short name T133
Test name
Test status
Simulation time 98033237101 ps
CPU time 367.62 seconds
Started May 16 12:42:19 PM PDT 24
Finished May 16 12:48:29 PM PDT 24
Peak memory 193668 kb
Host smart-d81a393a-f1bf-4034-b5b8-5ac6f864140f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047792310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1047792310
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3851151944
Short name T437
Test name
Test status
Simulation time 99710370912 ps
CPU time 226.78 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:46:07 PM PDT 24
Peak memory 182584 kb
Host smart-672d94f4-70f9-4d77-b4c4-70945593bb04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851151944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3851151944
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2820284331
Short name T284
Test name
Test status
Simulation time 510575270215 ps
CPU time 578.11 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:51:57 PM PDT 24
Peak memory 190784 kb
Host smart-63522e8f-1c94-4159-964e-a4f23490050a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820284331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2820284331
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.870808580
Short name T367
Test name
Test status
Simulation time 103981546160 ps
CPU time 78.56 seconds
Started May 16 12:41:25 PM PDT 24
Finished May 16 12:42:50 PM PDT 24
Peak memory 182596 kb
Host smart-c18d4b69-8c85-4e3f-98bd-9382176f4b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870808580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.870808580
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.4092752380
Short name T264
Test name
Test status
Simulation time 70491648073 ps
CPU time 126.19 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 12:43:49 PM PDT 24
Peak memory 190804 kb
Host smart-bfb892ac-a4a0-46aa-acfe-3c49becd6845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092752380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4092752380
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3662708225
Short name T38
Test name
Test status
Simulation time 103264618308 ps
CPU time 58.22 seconds
Started May 16 12:41:38 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 205432 kb
Host smart-1e8fdc44-7123-4a44-a1e1-b63eefc24858
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662708225 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3662708225
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3863227380
Short name T49
Test name
Test status
Simulation time 27390036191 ps
CPU time 24.56 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 182492 kb
Host smart-c1414a26-3fc2-4dfb-bab2-c53feea19327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863227380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3863227380
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1267665773
Short name T141
Test name
Test status
Simulation time 1137871350517 ps
CPU time 817.76 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:55:57 PM PDT 24
Peak memory 190772 kb
Host smart-d6e573d6-61b5-4298-927d-8440d3b7539f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267665773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1267665773
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1185946029
Short name T270
Test name
Test status
Simulation time 34292762083 ps
CPU time 30.24 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 182564 kb
Host smart-0b1958ad-7de3-4f70-8ea6-a3dfbb95d22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185946029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1185946029
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.184215421
Short name T347
Test name
Test status
Simulation time 144301871333 ps
CPU time 118.07 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:44:16 PM PDT 24
Peak memory 190708 kb
Host smart-e6665be6-2369-460e-a027-a43838bb7d2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184215421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.184215421
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3676283743
Short name T238
Test name
Test status
Simulation time 124924729717 ps
CPU time 1897.48 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 01:13:57 PM PDT 24
Peak memory 190696 kb
Host smart-f59f577f-c4bb-48b5-8dc2-45f1de661bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676283743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3676283743
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2491663635
Short name T68
Test name
Test status
Simulation time 93703026527 ps
CPU time 152.02 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:44:51 PM PDT 24
Peak memory 191792 kb
Host smart-237bbab0-4937-4ab2-94a7-287540d69808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491663635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2491663635
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1325053323
Short name T275
Test name
Test status
Simulation time 7187488759 ps
CPU time 14.32 seconds
Started May 16 12:42:17 PM PDT 24
Finished May 16 12:42:35 PM PDT 24
Peak memory 182548 kb
Host smart-9dca44b6-996c-4309-9d68-2675f6bc544a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325053323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1325053323
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.54574605
Short name T379
Test name
Test status
Simulation time 210437650328 ps
CPU time 96.39 seconds
Started May 16 12:41:34 PM PDT 24
Finished May 16 12:43:17 PM PDT 24
Peak memory 182592 kb
Host smart-41322017-6974-447d-b98b-1f15b9875eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54574605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.54574605
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1897865700
Short name T309
Test name
Test status
Simulation time 41599376238 ps
CPU time 61.58 seconds
Started May 16 12:41:44 PM PDT 24
Finished May 16 12:42:52 PM PDT 24
Peak memory 182596 kb
Host smart-c8102e5d-dd8d-4ecf-bbaa-4029a68754a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897865700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1897865700
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2422478365
Short name T446
Test name
Test status
Simulation time 162132286040 ps
CPU time 65.86 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:42:34 PM PDT 24
Peak memory 182576 kb
Host smart-e6d1da31-f924-4511-8c94-3ab634efe12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422478365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2422478365
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3501670280
Short name T200
Test name
Test status
Simulation time 78405781124 ps
CPU time 77.95 seconds
Started May 16 12:42:18 PM PDT 24
Finished May 16 12:43:39 PM PDT 24
Peak memory 182416 kb
Host smart-b76f1f2a-d356-495d-a251-2ff75e13d885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501670280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3501670280
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.4153726375
Short name T140
Test name
Test status
Simulation time 203117723334 ps
CPU time 106.43 seconds
Started May 16 12:42:17 PM PDT 24
Finished May 16 12:44:07 PM PDT 24
Peak memory 190788 kb
Host smart-2f91e147-8848-48c6-8f35-bf910253e70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153726375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4153726375
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3715690219
Short name T103
Test name
Test status
Simulation time 82327421189 ps
CPU time 129.52 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:44:27 PM PDT 24
Peak memory 190708 kb
Host smart-a3061e21-e716-463e-9fe9-4b8f9d5d7d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715690219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3715690219
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4154877137
Short name T108
Test name
Test status
Simulation time 211628089298 ps
CPU time 412.28 seconds
Started May 16 12:42:17 PM PDT 24
Finished May 16 12:49:13 PM PDT 24
Peak memory 182572 kb
Host smart-ca922ae4-2741-490c-b497-4f562c435aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154877137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4154877137
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2898398730
Short name T299
Test name
Test status
Simulation time 29921127879 ps
CPU time 19.47 seconds
Started May 16 12:42:21 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 182460 kb
Host smart-46691841-09a1-42dc-ba8d-c0011e74f6e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898398730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2898398730
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2093385773
Short name T124
Test name
Test status
Simulation time 128821894977 ps
CPU time 156.61 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:44:54 PM PDT 24
Peak memory 193892 kb
Host smart-1cfd5dd2-8c19-4303-b331-5a3264d89bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093385773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2093385773
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3846295340
Short name T441
Test name
Test status
Simulation time 19086900021 ps
CPU time 30.64 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:42:51 PM PDT 24
Peak memory 182528 kb
Host smart-c662cb54-9e6e-449b-b85c-f6600b1b290c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846295340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3846295340
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.143557862
Short name T356
Test name
Test status
Simulation time 65157033123 ps
CPU time 1111.89 seconds
Started May 16 12:42:13 PM PDT 24
Finished May 16 01:00:49 PM PDT 24
Peak memory 182504 kb
Host smart-6ebf230a-6906-45cc-88a6-48d99a59b885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143557862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.143557862
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3705810838
Short name T412
Test name
Test status
Simulation time 109283102871 ps
CPU time 140 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:44:40 PM PDT 24
Peak memory 190792 kb
Host smart-04b5a3bb-d387-41f2-852d-af1d2c1abd8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705810838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3705810838
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2843711138
Short name T178
Test name
Test status
Simulation time 37467712443 ps
CPU time 1178.16 seconds
Started May 16 12:42:18 PM PDT 24
Finished May 16 01:02:00 PM PDT 24
Peak memory 190904 kb
Host smart-2e621ec9-51ad-417c-b9d5-5bf0438a5e34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843711138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2843711138
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.942200540
Short name T239
Test name
Test status
Simulation time 267740753483 ps
CPU time 436.96 seconds
Started May 16 12:41:26 PM PDT 24
Finished May 16 12:48:50 PM PDT 24
Peak memory 182516 kb
Host smart-64544a72-72e1-4926-ad22-8bdeb33197b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942200540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.942200540
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2751986537
Short name T375
Test name
Test status
Simulation time 510152193098 ps
CPU time 184.27 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:44:29 PM PDT 24
Peak memory 182604 kb
Host smart-6bc06baa-cd52-44c1-8684-5974663ef7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751986537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2751986537
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1165155060
Short name T315
Test name
Test status
Simulation time 274088734992 ps
CPU time 117.23 seconds
Started May 16 12:41:25 PM PDT 24
Finished May 16 12:43:28 PM PDT 24
Peak memory 190752 kb
Host smart-a71b6a42-b08f-4855-a66a-cd68f8aa9869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165155060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1165155060
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3612805249
Short name T228
Test name
Test status
Simulation time 68054512013 ps
CPU time 112.24 seconds
Started May 16 12:41:42 PM PDT 24
Finished May 16 12:43:41 PM PDT 24
Peak memory 182512 kb
Host smart-07fd46c9-a3a5-4566-9f8d-b4df2a4496d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612805249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3612805249
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/173.rv_timer_random.1334851703
Short name T253
Test name
Test status
Simulation time 124545823054 ps
CPU time 192.78 seconds
Started May 16 12:42:18 PM PDT 24
Finished May 16 12:45:34 PM PDT 24
Peak memory 190692 kb
Host smart-58d6fa8b-7c16-4434-b92c-38ca222917d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334851703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1334851703
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.185487200
Short name T231
Test name
Test status
Simulation time 54469138146 ps
CPU time 595.28 seconds
Started May 16 12:42:13 PM PDT 24
Finished May 16 12:52:12 PM PDT 24
Peak memory 190792 kb
Host smart-5ed04ce8-097f-436e-a996-6361c047fa09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185487200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.185487200
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2490466991
Short name T334
Test name
Test status
Simulation time 85645916466 ps
CPU time 59.51 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:43:18 PM PDT 24
Peak memory 182580 kb
Host smart-298b70e0-e2b2-4605-b090-adadf15f4c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490466991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2490466991
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.4041765904
Short name T153
Test name
Test status
Simulation time 68543205915 ps
CPU time 454.79 seconds
Started May 16 12:42:12 PM PDT 24
Finished May 16 12:49:50 PM PDT 24
Peak memory 190744 kb
Host smart-44d34c85-ce0c-4050-b0da-ff6c4ff995b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041765904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4041765904
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2974197157
Short name T300
Test name
Test status
Simulation time 155388736867 ps
CPU time 157.44 seconds
Started May 16 12:42:16 PM PDT 24
Finished May 16 12:44:57 PM PDT 24
Peak memory 190700 kb
Host smart-4a14fccf-a2be-4b58-a734-c22bf2515a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974197157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2974197157
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3802876164
Short name T242
Test name
Test status
Simulation time 11317383842 ps
CPU time 21.41 seconds
Started May 16 12:41:34 PM PDT 24
Finished May 16 12:42:02 PM PDT 24
Peak memory 182576 kb
Host smart-177d7dc3-5c16-4069-b630-7311ff37030b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802876164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3802876164
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.503033971
Short name T373
Test name
Test status
Simulation time 190809248130 ps
CPU time 176.96 seconds
Started May 16 12:41:44 PM PDT 24
Finished May 16 12:44:47 PM PDT 24
Peak memory 182572 kb
Host smart-f877634a-5308-4627-af05-0fa4c8738f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503033971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.503033971
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2079690149
Short name T209
Test name
Test status
Simulation time 303395280899 ps
CPU time 1014.48 seconds
Started May 16 12:41:29 PM PDT 24
Finished May 16 12:58:29 PM PDT 24
Peak memory 190784 kb
Host smart-f3ce0a69-d28f-4385-8fc5-bb8dc233578f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079690149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2079690149
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.4142809684
Short name T389
Test name
Test status
Simulation time 148496652 ps
CPU time 0.59 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:41:30 PM PDT 24
Peak memory 182300 kb
Host smart-fdfdb50f-8632-40f1-8413-c049778d05b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142809684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4142809684
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2644206667
Short name T11
Test name
Test status
Simulation time 111901447504 ps
CPU time 996.96 seconds
Started May 16 12:41:22 PM PDT 24
Finished May 16 12:58:05 PM PDT 24
Peak memory 206056 kb
Host smart-6b6c5407-d0c0-4c71-8ad2-87c8af5e0360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644206667 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2644206667
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.1094617797
Short name T337
Test name
Test status
Simulation time 75537025474 ps
CPU time 519.68 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:50:57 PM PDT 24
Peak memory 190768 kb
Host smart-bc689e24-8d7a-44ca-8370-ada0a2ee0cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094617797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1094617797
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1598619293
Short name T248
Test name
Test status
Simulation time 207940475018 ps
CPU time 206.74 seconds
Started May 16 12:42:20 PM PDT 24
Finished May 16 12:45:49 PM PDT 24
Peak memory 190788 kb
Host smart-2baa334f-fadf-4434-9b8c-22840f9ee0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598619293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1598619293
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2750885870
Short name T344
Test name
Test status
Simulation time 307493585023 ps
CPU time 599.44 seconds
Started May 16 12:42:15 PM PDT 24
Finished May 16 12:52:19 PM PDT 24
Peak memory 190660 kb
Host smart-9c29af5a-390e-4b3a-9a40-582b619ae3b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750885870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2750885870
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3615093003
Short name T147
Test name
Test status
Simulation time 128993391020 ps
CPU time 1045.82 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:59:43 PM PDT 24
Peak memory 190664 kb
Host smart-4aade309-2f78-4453-8dfb-7464ecca4dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615093003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3615093003
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2175367122
Short name T340
Test name
Test status
Simulation time 302105698495 ps
CPU time 564.36 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:51:41 PM PDT 24
Peak memory 190824 kb
Host smart-e7fa9bf4-08d5-4ee7-af12-0e4ebd160698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175367122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2175367122
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3318035947
Short name T19
Test name
Test status
Simulation time 323139323442 ps
CPU time 149.17 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:44:47 PM PDT 24
Peak memory 190780 kb
Host smart-7d4d81a4-370f-4f0f-9bcb-6a5f677685d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318035947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3318035947
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1232133042
Short name T305
Test name
Test status
Simulation time 451482797917 ps
CPU time 245.24 seconds
Started May 16 12:41:43 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 182552 kb
Host smart-72cecfb8-d9e9-4b9f-acc7-d6ca63339909
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232133042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1232133042
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2103097082
Short name T421
Test name
Test status
Simulation time 44818837138 ps
CPU time 65.05 seconds
Started May 16 12:41:34 PM PDT 24
Finished May 16 12:42:46 PM PDT 24
Peak memory 182580 kb
Host smart-c82e3482-7fc6-4656-993c-da9c666d655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103097082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2103097082
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.129758025
Short name T405
Test name
Test status
Simulation time 121338143 ps
CPU time 0.6 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:41:31 PM PDT 24
Peak memory 182332 kb
Host smart-d5940153-4674-4634-a6ee-aac05f828581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129758025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.129758025
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1368648762
Short name T174
Test name
Test status
Simulation time 427015477355 ps
CPU time 559.93 seconds
Started May 16 12:41:25 PM PDT 24
Finished May 16 12:50:51 PM PDT 24
Peak memory 190792 kb
Host smart-133f3c07-564d-4e66-9069-0f4802b0e64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368648762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1368648762
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.1667231116
Short name T198
Test name
Test status
Simulation time 60657581033 ps
CPU time 1602.87 seconds
Started May 16 12:42:19 PM PDT 24
Finished May 16 01:09:05 PM PDT 24
Peak memory 190772 kb
Host smart-4d9b7334-8cb1-4e58-ae5a-7e1420bc6fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667231116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1667231116
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1951751768
Short name T252
Test name
Test status
Simulation time 578371582593 ps
CPU time 214.88 seconds
Started May 16 12:42:22 PM PDT 24
Finished May 16 12:46:00 PM PDT 24
Peak memory 190756 kb
Host smart-8b755330-ee52-4507-b3eb-4d5df910a07b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951751768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1951751768
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3475995362
Short name T426
Test name
Test status
Simulation time 83423288762 ps
CPU time 696.99 seconds
Started May 16 12:42:19 PM PDT 24
Finished May 16 12:53:59 PM PDT 24
Peak memory 190696 kb
Host smart-8322b35f-2953-4375-b67d-f1b57c16739d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475995362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3475995362
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1432604507
Short name T254
Test name
Test status
Simulation time 368159837486 ps
CPU time 742.95 seconds
Started May 16 12:42:23 PM PDT 24
Finished May 16 12:54:48 PM PDT 24
Peak memory 190756 kb
Host smart-311715bd-0b0a-4c5c-acbe-4f6484d021c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432604507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1432604507
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3858720408
Short name T311
Test name
Test status
Simulation time 377181745352 ps
CPU time 590.61 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:52:07 PM PDT 24
Peak memory 190724 kb
Host smart-d05fd2c4-f39f-4d8d-b1cb-9457bc3698aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858720408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3858720408
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.272585390
Short name T23
Test name
Test status
Simulation time 85131153303 ps
CPU time 47.47 seconds
Started May 16 12:42:13 PM PDT 24
Finished May 16 12:43:04 PM PDT 24
Peak memory 182472 kb
Host smart-f173452b-c5b8-495e-b866-190fb1973dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272585390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.272585390
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2848546976
Short name T414
Test name
Test status
Simulation time 760277735418 ps
CPU time 440.26 seconds
Started May 16 12:42:14 PM PDT 24
Finished May 16 12:49:38 PM PDT 24
Peak memory 182488 kb
Host smart-21b4ee2c-32f9-48fb-8fd2-6bfadd8c6d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848546976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2848546976
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3292532404
Short name T257
Test name
Test status
Simulation time 1312816747243 ps
CPU time 308.33 seconds
Started May 16 12:41:22 PM PDT 24
Finished May 16 12:46:36 PM PDT 24
Peak memory 182580 kb
Host smart-db360e75-8b8d-445c-8dbe-e5db3db36980
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292532404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3292532404
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1575084042
Short name T370
Test name
Test status
Simulation time 134641154437 ps
CPU time 197.1 seconds
Started May 16 12:41:22 PM PDT 24
Finished May 16 12:44:45 PM PDT 24
Peak memory 182508 kb
Host smart-5104e83b-f922-4c0f-97f2-bcf7c7e2e649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575084042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1575084042
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1291712846
Short name T319
Test name
Test status
Simulation time 362692127607 ps
CPU time 409.18 seconds
Started May 16 12:41:09 PM PDT 24
Finished May 16 12:48:01 PM PDT 24
Peak memory 190744 kb
Host smart-9d9c2dcf-f854-48f7-8b06-b151ee54ba20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291712846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1291712846
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.4212134286
Short name T402
Test name
Test status
Simulation time 608179526 ps
CPU time 2.53 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 12:41:45 PM PDT 24
Peak memory 194068 kb
Host smart-62f866f3-1617-475d-94f5-227b2467bd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212134286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.4212134286
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.76375913
Short name T15
Test name
Test status
Simulation time 65985146 ps
CPU time 0.81 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:41:26 PM PDT 24
Peak memory 213716 kb
Host smart-213e3b41-fd79-4fd1-932b-3b9761066411
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76375913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.76375913
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3447052273
Short name T22
Test name
Test status
Simulation time 83558276498 ps
CPU time 55.07 seconds
Started May 16 12:41:22 PM PDT 24
Finished May 16 12:42:22 PM PDT 24
Peak memory 182504 kb
Host smart-358f5267-e6b2-4c28-a101-ab4b6c6eab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447052273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3447052273
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3556646487
Short name T125
Test name
Test status
Simulation time 77265753608 ps
CPU time 559.22 seconds
Started May 16 12:41:48 PM PDT 24
Finished May 16 12:51:16 PM PDT 24
Peak memory 190904 kb
Host smart-70724622-6679-4a8e-bc89-96751ce645af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556646487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3556646487
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3476003813
Short name T225
Test name
Test status
Simulation time 333042077066 ps
CPU time 90.35 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:43:04 PM PDT 24
Peak memory 190700 kb
Host smart-7e387d1c-9fac-4e15-933f-7ab4ed4c337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476003813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3476003813
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.720726494
Short name T283
Test name
Test status
Simulation time 5414961491 ps
CPU time 10.48 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 12:41:55 PM PDT 24
Peak memory 182592 kb
Host smart-b7c12876-113f-4632-bebc-e60877e704d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720726494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.720726494
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.901308443
Short name T423
Test name
Test status
Simulation time 145451075250 ps
CPU time 117.58 seconds
Started May 16 12:41:27 PM PDT 24
Finished May 16 12:43:31 PM PDT 24
Peak memory 182612 kb
Host smart-64929d8e-e092-47a7-b654-f8b88897ca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901308443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.901308443
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3281303343
Short name T348
Test name
Test status
Simulation time 83170081122 ps
CPU time 170.46 seconds
Started May 16 12:41:39 PM PDT 24
Finished May 16 12:44:36 PM PDT 24
Peak memory 190780 kb
Host smart-b00c3ba8-0949-4ccb-9f71-2b4e965f147d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281303343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3281303343
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.301584990
Short name T350
Test name
Test status
Simulation time 36527419769 ps
CPU time 13.26 seconds
Started May 16 12:41:27 PM PDT 24
Finished May 16 12:41:46 PM PDT 24
Peak memory 182508 kb
Host smart-d651cd67-0508-4d3b-a02e-e332702d8018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301584990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.301584990
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1884660241
Short name T27
Test name
Test status
Simulation time 499391794407 ps
CPU time 204.06 seconds
Started May 16 12:41:22 PM PDT 24
Finished May 16 12:44:52 PM PDT 24
Peak memory 194112 kb
Host smart-c8683953-6cf6-482d-92cf-fa952b606cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884660241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1884660241
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3176014816
Short name T210
Test name
Test status
Simulation time 250690073958 ps
CPU time 146.75 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:44:01 PM PDT 24
Peak memory 182588 kb
Host smart-f0485111-c09a-4829-9051-d37d09c00c4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176014816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3176014816
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1398527459
Short name T363
Test name
Test status
Simulation time 241845089072 ps
CPU time 94.96 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:43:29 PM PDT 24
Peak memory 182588 kb
Host smart-cea97a99-aa74-49a0-8af9-5ab4c64139c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398527459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1398527459
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2037585624
Short name T433
Test name
Test status
Simulation time 29998529057 ps
CPU time 60.59 seconds
Started May 16 12:41:22 PM PDT 24
Finished May 16 12:42:29 PM PDT 24
Peak memory 182524 kb
Host smart-25df724b-7618-4fee-a819-bbaf946a280b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037585624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2037585624
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4249662
Short name T159
Test name
Test status
Simulation time 64788383981 ps
CPU time 89.35 seconds
Started May 16 12:41:34 PM PDT 24
Finished May 16 12:43:10 PM PDT 24
Peak memory 182560 kb
Host smart-9a3c49b8-f20d-453c-9ca0-ce72b1e1122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4249662
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.501827149
Short name T376
Test name
Test status
Simulation time 36140843798 ps
CPU time 56.66 seconds
Started May 16 12:41:46 PM PDT 24
Finished May 16 12:42:50 PM PDT 24
Peak memory 182476 kb
Host smart-03502c72-1b34-414f-8364-64a6f21aa24b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501827149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
501827149
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2054156577
Short name T148
Test name
Test status
Simulation time 3466888405 ps
CPU time 5.11 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 12:41:49 PM PDT 24
Peak memory 182616 kb
Host smart-d73267ca-ea28-47d0-bbc2-52d628007b01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054156577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2054156577
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.125849798
Short name T361
Test name
Test status
Simulation time 168298341689 ps
CPU time 260.97 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:46:18 PM PDT 24
Peak memory 182560 kb
Host smart-cfecd4a4-37d7-4b1b-aeb0-aa3576c352e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125849798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.125849798
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1370996175
Short name T214
Test name
Test status
Simulation time 453104627336 ps
CPU time 384.13 seconds
Started May 16 12:41:33 PM PDT 24
Finished May 16 12:48:03 PM PDT 24
Peak memory 190828 kb
Host smart-ceffb6a6-33e2-465b-ac71-a65ada693069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370996175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1370996175
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2405196651
Short name T306
Test name
Test status
Simulation time 380377672199 ps
CPU time 268.78 seconds
Started May 16 12:41:34 PM PDT 24
Finished May 16 12:46:10 PM PDT 24
Peak memory 190776 kb
Host smart-7800be6d-4d0b-4581-b735-a36ab7d0acd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405196651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2405196651
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.4126822065
Short name T12
Test name
Test status
Simulation time 45402795065 ps
CPU time 244.66 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:45:52 PM PDT 24
Peak memory 197148 kb
Host smart-39670ff2-7702-43cb-b875-a9448d9fc58f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126822065 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.4126822065
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2679693289
Short name T448
Test name
Test status
Simulation time 3483241869 ps
CPU time 3.35 seconds
Started May 16 12:41:45 PM PDT 24
Finished May 16 12:41:55 PM PDT 24
Peak memory 182596 kb
Host smart-e8a551e6-3086-4036-b27c-7720f5c9d5c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679693289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2679693289
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2819283636
Short name T366
Test name
Test status
Simulation time 133618263784 ps
CPU time 92.76 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:43:07 PM PDT 24
Peak memory 182528 kb
Host smart-d25a981d-7ace-4eff-bcee-46cf49455600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819283636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2819283636
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3835496453
Short name T139
Test name
Test status
Simulation time 21109225695 ps
CPU time 141.98 seconds
Started May 16 12:41:40 PM PDT 24
Finished May 16 12:44:09 PM PDT 24
Peak memory 182476 kb
Host smart-0c9d02b5-9dc7-4461-abcb-a625c97c6bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835496453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3835496453
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3378471417
Short name T56
Test name
Test status
Simulation time 154588677327 ps
CPU time 86.51 seconds
Started May 16 12:41:42 PM PDT 24
Finished May 16 12:43:15 PM PDT 24
Peak memory 193984 kb
Host smart-078e3d12-2157-49e0-b038-56fb76b5ba89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378471417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3378471417
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1050969535
Short name T399
Test name
Test status
Simulation time 3944183439309 ps
CPU time 616.85 seconds
Started May 16 12:41:42 PM PDT 24
Finished May 16 12:52:06 PM PDT 24
Peak memory 190792 kb
Host smart-58bd13b1-2664-42a8-852d-e1b3a77175ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050969535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1050969535
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.4071989033
Short name T186
Test name
Test status
Simulation time 24987834424 ps
CPU time 44.9 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:42:19 PM PDT 24
Peak memory 182592 kb
Host smart-2006b16a-3fa0-4564-99e2-7a9077b263ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071989033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.4071989033
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.369986360
Short name T442
Test name
Test status
Simulation time 542693517390 ps
CPU time 184.29 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:44:52 PM PDT 24
Peak memory 182600 kb
Host smart-e1fac5f5-8d27-44a5-a191-bbbb69af4ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369986360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.369986360
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2145247848
Short name T240
Test name
Test status
Simulation time 370639103160 ps
CPU time 768.85 seconds
Started May 16 12:41:43 PM PDT 24
Finished May 16 12:54:38 PM PDT 24
Peak memory 190760 kb
Host smart-ca2bd9d3-d274-4c27-9967-39dfc81ac694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145247848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2145247848
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2842994748
Short name T422
Test name
Test status
Simulation time 56681250333 ps
CPU time 21.87 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:42:14 PM PDT 24
Peak memory 194632 kb
Host smart-0fed0ae5-ed89-4104-92fa-df4d9f5514ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842994748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2842994748
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.4128886401
Short name T365
Test name
Test status
Simulation time 491682709796 ps
CPU time 499.57 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:50:07 PM PDT 24
Peak memory 190696 kb
Host smart-0c8fbd0c-764e-4626-8a34-70c9a7a48888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128886401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.4128886401
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1552572980
Short name T436
Test name
Test status
Simulation time 536032705903 ps
CPU time 266.42 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:46:27 PM PDT 24
Peak memory 182548 kb
Host smart-84110e04-8e88-4959-9ed1-c20ebffc6412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552572980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1552572980
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.349111188
Short name T119
Test name
Test status
Simulation time 171035478188 ps
CPU time 105.26 seconds
Started May 16 12:41:40 PM PDT 24
Finished May 16 12:43:32 PM PDT 24
Peak memory 190756 kb
Host smart-7a734d47-6e50-4d20-bc31-44ade02753a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349111188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.349111188
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3584168173
Short name T401
Test name
Test status
Simulation time 38534650071 ps
CPU time 19.59 seconds
Started May 16 12:41:31 PM PDT 24
Finished May 16 12:41:57 PM PDT 24
Peak memory 190704 kb
Host smart-0026bff9-ba6b-4b3b-8a32-331af7c17a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584168173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3584168173
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2356252139
Short name T358
Test name
Test status
Simulation time 365129965664 ps
CPU time 216.63 seconds
Started May 16 12:41:38 PM PDT 24
Finished May 16 12:45:22 PM PDT 24
Peak memory 182572 kb
Host smart-df496df4-8e4d-44ef-8ca2-fca99047e297
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356252139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2356252139
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3322566762
Short name T408
Test name
Test status
Simulation time 2177212098 ps
CPU time 3.48 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:42:00 PM PDT 24
Peak memory 182428 kb
Host smart-87070f15-6637-458d-8ef3-14cddab02c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322566762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3322566762
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2959426672
Short name T211
Test name
Test status
Simulation time 94148186274 ps
CPU time 47.92 seconds
Started May 16 12:41:30 PM PDT 24
Finished May 16 12:42:24 PM PDT 24
Peak memory 190704 kb
Host smart-72fc0530-8e00-4ab6-9356-962348ecb964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959426672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2959426672
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.4745321
Short name T447
Test name
Test status
Simulation time 993583504118 ps
CPU time 396.91 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:48:25 PM PDT 24
Peak memory 190800 kb
Host smart-69b5a911-e1ce-4dc5-8dd4-9312250173a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4745321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.4745321
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.1235309130
Short name T43
Test name
Test status
Simulation time 112173754545 ps
CPU time 854.16 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:56:13 PM PDT 24
Peak memory 210116 kb
Host smart-1b90566b-7655-4b9b-89d7-6df2d1e0f6e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235309130 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.1235309130
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2611926940
Short name T167
Test name
Test status
Simulation time 56730323615 ps
CPU time 37.86 seconds
Started May 16 12:41:38 PM PDT 24
Finished May 16 12:42:23 PM PDT 24
Peak memory 182584 kb
Host smart-4f7805e0-cc13-4168-bb0c-f965311f9835
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611926940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2611926940
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3244236696
Short name T76
Test name
Test status
Simulation time 38370976095 ps
CPU time 59.51 seconds
Started May 16 12:41:32 PM PDT 24
Finished May 16 12:42:37 PM PDT 24
Peak memory 182500 kb
Host smart-c474d5ed-85d1-493a-afcf-256710c09497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244236696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3244236696
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.846340787
Short name T258
Test name
Test status
Simulation time 573687649862 ps
CPU time 498.16 seconds
Started May 16 12:41:41 PM PDT 24
Finished May 16 12:50:05 PM PDT 24
Peak memory 190740 kb
Host smart-800f7e1b-d806-4f67-9fa6-8649077b9d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846340787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.846340787
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2110728370
Short name T111
Test name
Test status
Simulation time 3397776890693 ps
CPU time 1999.19 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 01:15:02 PM PDT 24
Peak memory 190784 kb
Host smart-800c652d-65d9-47c3-9999-0f151ac7546b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110728370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2110728370
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1499780071
Short name T52
Test name
Test status
Simulation time 144924142749 ps
CPU time 220.81 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 12:45:25 PM PDT 24
Peak memory 182568 kb
Host smart-805a081d-7ae8-476a-b827-c40481781488
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499780071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1499780071
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3295620676
Short name T411
Test name
Test status
Simulation time 115418447763 ps
CPU time 46.01 seconds
Started May 16 12:41:40 PM PDT 24
Finished May 16 12:42:32 PM PDT 24
Peak memory 182508 kb
Host smart-b5130d69-ffc7-4971-8e40-94ab900fb094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295620676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3295620676
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2354045441
Short name T298
Test name
Test status
Simulation time 43310879969 ps
CPU time 68.04 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:43:05 PM PDT 24
Peak memory 190776 kb
Host smart-2926ef88-ab67-4052-bb7f-ae191f01f371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354045441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2354045441
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1964019627
Short name T431
Test name
Test status
Simulation time 17916808946 ps
CPU time 27.92 seconds
Started May 16 12:41:36 PM PDT 24
Finished May 16 12:42:11 PM PDT 24
Peak memory 190812 kb
Host smart-d0c0f3ef-fec8-4ffc-acfc-19e6811888ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964019627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1964019627
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.26890076
Short name T64
Test name
Test status
Simulation time 256794332159 ps
CPU time 400.73 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:48:15 PM PDT 24
Peak memory 182508 kb
Host smart-4690d322-b390-40f1-affe-86c1e37f8563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26890076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.26890076
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3484014765
Short name T183
Test name
Test status
Simulation time 363782322459 ps
CPU time 634.84 seconds
Started May 16 12:41:13 PM PDT 24
Finished May 16 12:51:51 PM PDT 24
Peak memory 182596 kb
Host smart-e6dab936-ded6-4f79-a687-8c20dfad6ee5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484014765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3484014765
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1758990710
Short name T388
Test name
Test status
Simulation time 195843897747 ps
CPU time 154.4 seconds
Started May 16 12:41:22 PM PDT 24
Finished May 16 12:44:02 PM PDT 24
Peak memory 182556 kb
Host smart-68233a67-b275-4445-813a-f8f704bc38d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758990710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1758990710
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2232813981
Short name T286
Test name
Test status
Simulation time 189306095998 ps
CPU time 83.77 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:42:47 PM PDT 24
Peak memory 190744 kb
Host smart-6f9cea20-61fc-47a7-8179-0de061f2a8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232813981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2232813981
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.169007143
Short name T368
Test name
Test status
Simulation time 16148546393 ps
CPU time 22.28 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:41:45 PM PDT 24
Peak memory 190696 kb
Host smart-c06f3b3b-c3e2-4f3f-88e0-2babf1b3d216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169007143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.169007143
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2798575562
Short name T13
Test name
Test status
Simulation time 70757917 ps
CPU time 0.73 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:41:35 PM PDT 24
Peak memory 213664 kb
Host smart-cf4b73e4-0475-48f8-874f-50bfea8d159f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798575562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2798575562
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.40421457
Short name T267
Test name
Test status
Simulation time 99609726797 ps
CPU time 41 seconds
Started May 16 12:41:58 PM PDT 24
Finished May 16 12:42:45 PM PDT 24
Peak memory 182572 kb
Host smart-c543c0c9-ddc4-49ee-a70b-b941734bcc3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40421457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.rv_timer_cfg_update_on_fly.40421457
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2845025011
Short name T382
Test name
Test status
Simulation time 365148574532 ps
CPU time 153.61 seconds
Started May 16 12:41:33 PM PDT 24
Finished May 16 12:44:13 PM PDT 24
Peak memory 182508 kb
Host smart-ef9d0591-674a-4dd1-b786-ab99f6a1a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845025011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2845025011
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2925807399
Short name T237
Test name
Test status
Simulation time 78409190615 ps
CPU time 52.79 seconds
Started May 16 12:41:40 PM PDT 24
Finished May 16 12:42:39 PM PDT 24
Peak memory 182496 kb
Host smart-f854a8be-0c6c-4b9e-b10e-ac61d6e5a23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925807399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2925807399
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1454021953
Short name T396
Test name
Test status
Simulation time 31773439203 ps
CPU time 48.34 seconds
Started May 16 12:41:45 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 190764 kb
Host smart-c6f3d58b-5807-4ba4-a287-30beccb95e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454021953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1454021953
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.4210019496
Short name T63
Test name
Test status
Simulation time 1701194689666 ps
CPU time 1104.38 seconds
Started May 16 12:41:31 PM PDT 24
Finished May 16 01:00:01 PM PDT 24
Peak memory 190724 kb
Host smart-4c388d17-cfdb-4b23-ad80-0c0ab171a4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210019496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.4210019496
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3015786520
Short name T206
Test name
Test status
Simulation time 5447563936138 ps
CPU time 1256.36 seconds
Started May 16 12:41:35 PM PDT 24
Finished May 16 01:02:38 PM PDT 24
Peak memory 182520 kb
Host smart-c6d3577f-4857-4034-a14a-fe8262872af0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015786520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3015786520
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3560486628
Short name T384
Test name
Test status
Simulation time 114551601594 ps
CPU time 44.59 seconds
Started May 16 12:41:29 PM PDT 24
Finished May 16 12:42:20 PM PDT 24
Peak memory 182500 kb
Host smart-54662c72-96d7-4b57-b2bd-ef8e735290fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560486628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3560486628
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1394094500
Short name T288
Test name
Test status
Simulation time 257786585993 ps
CPU time 146.64 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:44:23 PM PDT 24
Peak memory 190736 kb
Host smart-e6fa87fc-50cc-4d86-85f8-8801eb5d768d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394094500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1394094500
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3438147662
Short name T54
Test name
Test status
Simulation time 349103559 ps
CPU time 0.92 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 12:41:45 PM PDT 24
Peak memory 192056 kb
Host smart-245f503a-6a66-4467-9ad7-16b602df0b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438147662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3438147662
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2345352210
Short name T302
Test name
Test status
Simulation time 309431357075 ps
CPU time 471.42 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:49:51 PM PDT 24
Peak memory 182612 kb
Host smart-b8a1139f-7c84-4740-a3c9-c788b1cba75a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345352210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2345352210
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1943638117
Short name T18
Test name
Test status
Simulation time 270092838393 ps
CPU time 235.61 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:45:53 PM PDT 24
Peak memory 182536 kb
Host smart-38576d93-f40b-4e59-a71a-2791e75ffc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943638117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1943638117
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.943986228
Short name T171
Test name
Test status
Simulation time 49194314143 ps
CPU time 98.24 seconds
Started May 16 12:41:48 PM PDT 24
Finished May 16 12:43:33 PM PDT 24
Peak memory 182472 kb
Host smart-a4387b8c-aa04-4b6e-8e6f-79d908821587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943986228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.943986228
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2825917437
Short name T21
Test name
Test status
Simulation time 97882454 ps
CPU time 0.57 seconds
Started May 16 12:41:44 PM PDT 24
Finished May 16 12:41:51 PM PDT 24
Peak memory 182352 kb
Host smart-2c44ab89-00e4-4a52-a8c4-16779a605b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825917437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2825917437
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4190141083
Short name T353
Test name
Test status
Simulation time 139747211434 ps
CPU time 121.64 seconds
Started May 16 12:41:48 PM PDT 24
Finished May 16 12:43:58 PM PDT 24
Peak memory 182596 kb
Host smart-8a86c5b0-0fe7-46f0-acf2-30234e982a1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190141083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.4190141083
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1430542895
Short name T374
Test name
Test status
Simulation time 173305416913 ps
CPU time 174.18 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 12:44:38 PM PDT 24
Peak memory 182632 kb
Host smart-ca579ed3-770a-4593-96f0-df4fe20579c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430542895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1430542895
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1984290289
Short name T197
Test name
Test status
Simulation time 291143917417 ps
CPU time 237.37 seconds
Started May 16 12:41:43 PM PDT 24
Finished May 16 12:45:47 PM PDT 24
Peak memory 190664 kb
Host smart-031784f4-e8a7-4f15-8e37-d1f19989b18a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984290289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1984290289
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3980685875
Short name T395
Test name
Test status
Simulation time 419347976 ps
CPU time 0.66 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:41:59 PM PDT 24
Peak memory 182340 kb
Host smart-38a77454-2bad-4fd7-b2c7-78709cb44660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980685875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3980685875
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.629982752
Short name T39
Test name
Test status
Simulation time 304483379726 ps
CPU time 664.3 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:53:02 PM PDT 24
Peak memory 208208 kb
Host smart-37ddf3a5-8086-4d06-9293-a8fbc49d0dbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629982752 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.629982752
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.519840693
Short name T295
Test name
Test status
Simulation time 175239194681 ps
CPU time 238.29 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:45:57 PM PDT 24
Peak memory 182500 kb
Host smart-5de7947b-3e4e-48e1-adb3-b38de0061fc9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519840693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.519840693
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.230683665
Short name T67
Test name
Test status
Simulation time 67978086062 ps
CPU time 88.94 seconds
Started May 16 12:41:35 PM PDT 24
Finished May 16 12:43:10 PM PDT 24
Peak memory 182564 kb
Host smart-6a61d75f-c232-49ff-a455-430c6f53365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230683665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.230683665
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.93410011
Short name T328
Test name
Test status
Simulation time 220354554806 ps
CPU time 198.87 seconds
Started May 16 12:41:44 PM PDT 24
Finished May 16 12:45:10 PM PDT 24
Peak memory 190780 kb
Host smart-6cd1f1cb-a3a7-4aa3-b0ad-0611939f7778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93410011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.93410011
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2226103142
Short name T241
Test name
Test status
Simulation time 254136733336 ps
CPU time 210.54 seconds
Started May 16 12:41:46 PM PDT 24
Finished May 16 12:45:23 PM PDT 24
Peak memory 194620 kb
Host smart-4ee7be82-8add-461d-9d63-fac36882fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226103142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2226103142
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.582359543
Short name T207
Test name
Test status
Simulation time 471611192100 ps
CPU time 773.2 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:54:54 PM PDT 24
Peak memory 194216 kb
Host smart-53ab4b63-1980-4c33-b003-4088d56bff49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582359543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
582359543
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1343111254
Short name T316
Test name
Test status
Simulation time 37001985069 ps
CPU time 20.2 seconds
Started May 16 12:41:43 PM PDT 24
Finished May 16 12:42:09 PM PDT 24
Peak memory 182608 kb
Host smart-d9ece6f5-6990-4c92-a9e5-7bb5294c7442
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343111254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1343111254
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random.431667471
Short name T320
Test name
Test status
Simulation time 666577359947 ps
CPU time 184.4 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:44:59 PM PDT 24
Peak memory 194240 kb
Host smart-d82e061b-017f-4c65-b323-46a66b69a296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431667471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.431667471
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2425046371
Short name T310
Test name
Test status
Simulation time 425679874602 ps
CPU time 525.19 seconds
Started May 16 12:41:45 PM PDT 24
Finished May 16 12:50:36 PM PDT 24
Peak memory 194368 kb
Host smart-aea22412-5052-4f31-b30a-42ced7816aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425046371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2425046371
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1435685862
Short name T434
Test name
Test status
Simulation time 665365427311 ps
CPU time 331.24 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:47:28 PM PDT 24
Peak memory 182592 kb
Host smart-37ca098c-e969-4c5c-b0cb-c7c73904e2e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435685862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1435685862
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3107477877
Short name T409
Test name
Test status
Simulation time 105684087333 ps
CPU time 142.05 seconds
Started May 16 12:41:55 PM PDT 24
Finished May 16 12:44:25 PM PDT 24
Peak memory 182548 kb
Host smart-0ad28c9c-aabc-4931-ab7d-5ccd2d0d5b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107477877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3107477877
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1561620868
Short name T157
Test name
Test status
Simulation time 54686126417 ps
CPU time 97.2 seconds
Started May 16 12:41:42 PM PDT 24
Finished May 16 12:43:25 PM PDT 24
Peak memory 190792 kb
Host smart-8c029176-0b45-4b72-bddd-57110eea7f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561620868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1561620868
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2085149700
Short name T440
Test name
Test status
Simulation time 1011182672 ps
CPU time 0.9 seconds
Started May 16 12:41:42 PM PDT 24
Finished May 16 12:41:49 PM PDT 24
Peak memory 191052 kb
Host smart-9c969578-4b1c-4aac-b2e2-30873056cc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085149700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2085149700
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3442283183
Short name T36
Test name
Test status
Simulation time 131783631955 ps
CPU time 352.8 seconds
Started May 16 12:41:42 PM PDT 24
Finished May 16 12:47:41 PM PDT 24
Peak memory 205424 kb
Host smart-6e20601e-1667-4a91-a319-80d668c5f0b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442283183 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3442283183
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.49508799
Short name T394
Test name
Test status
Simulation time 41336075023 ps
CPU time 32.24 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:42:33 PM PDT 24
Peak memory 182600 kb
Host smart-1237b3a5-8535-459b-8b7b-85667da79c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49508799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.49508799
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3292354395
Short name T287
Test name
Test status
Simulation time 170590224654 ps
CPU time 1752.38 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 01:11:13 PM PDT 24
Peak memory 190776 kb
Host smart-8d45b24d-8b23-43fd-ab92-597d6e0fc8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292354395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3292354395
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2173319220
Short name T71
Test name
Test status
Simulation time 19123305222 ps
CPU time 29.14 seconds
Started May 16 12:41:46 PM PDT 24
Finished May 16 12:42:22 PM PDT 24
Peak memory 182540 kb
Host smart-f4ab2a77-afc7-4211-828b-edace895127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173319220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2173319220
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1699343047
Short name T329
Test name
Test status
Simulation time 1231273024271 ps
CPU time 579.27 seconds
Started May 16 12:41:43 PM PDT 24
Finished May 16 12:51:29 PM PDT 24
Peak memory 182604 kb
Host smart-dbe5e535-e523-405f-ab2d-118d6fd8d7ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699343047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1699343047
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3629921046
Short name T418
Test name
Test status
Simulation time 26016295982 ps
CPU time 31.22 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:42:29 PM PDT 24
Peak memory 182540 kb
Host smart-9330eced-e1ab-4fc1-a3b5-76a2c8cd3345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629921046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3629921046
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.4120147822
Short name T123
Test name
Test status
Simulation time 69936225384 ps
CPU time 119.92 seconds
Started May 16 12:41:45 PM PDT 24
Finished May 16 12:43:52 PM PDT 24
Peak memory 190740 kb
Host smart-15e42522-0233-431a-ac64-b7534c53d1d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120147822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.4120147822
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2912473392
Short name T260
Test name
Test status
Simulation time 194661975639 ps
CPU time 1499.31 seconds
Started May 16 12:41:46 PM PDT 24
Finished May 16 01:06:53 PM PDT 24
Peak memory 182548 kb
Host smart-b441f930-cb92-4d99-adab-dd99c33950ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912473392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2912473392
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3566996617
Short name T385
Test name
Test status
Simulation time 212325932418 ps
CPU time 297.47 seconds
Started May 16 12:41:48 PM PDT 24
Finished May 16 12:46:54 PM PDT 24
Peak memory 192824 kb
Host smart-4054edff-54d3-436e-8c87-43173f8a15b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566996617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3566996617
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2149372307
Short name T142
Test name
Test status
Simulation time 33126074533 ps
CPU time 58.7 seconds
Started May 16 12:41:44 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 182580 kb
Host smart-5ec9319b-ec55-432c-a569-a9475fba3621
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149372307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2149372307
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3585415770
Short name T428
Test name
Test status
Simulation time 524337203310 ps
CPU time 200.35 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:45:18 PM PDT 24
Peak memory 182584 kb
Host smart-1ec610bc-c4ea-4b70-9fad-fcb85713e6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585415770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3585415770
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.4265299727
Short name T169
Test name
Test status
Simulation time 262610734788 ps
CPU time 106.08 seconds
Started May 16 12:42:11 PM PDT 24
Finished May 16 12:44:01 PM PDT 24
Peak memory 193136 kb
Host smart-ec06b352-c9c8-4eb6-8f66-6f2a9902c7fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265299727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4265299727
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1695753401
Short name T432
Test name
Test status
Simulation time 926364306 ps
CPU time 1.89 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:41:56 PM PDT 24
Peak memory 182376 kb
Host smart-9b2ac716-68df-43e5-ae82-8dbfa032973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695753401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1695753401
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.1700853575
Short name T44
Test name
Test status
Simulation time 54270253108 ps
CPU time 437.28 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:49:17 PM PDT 24
Peak memory 205352 kb
Host smart-3d9d690a-897a-4b92-aaa5-2abd49632abc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700853575 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.1700853575
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.393909081
Short name T143
Test name
Test status
Simulation time 190268912365 ps
CPU time 169.23 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:44:20 PM PDT 24
Peak memory 182588 kb
Host smart-37f8a264-1416-4ac9-98f7-7fc8a91a0e49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393909081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.393909081
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3878967214
Short name T369
Test name
Test status
Simulation time 119026695552 ps
CPU time 168.81 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:44:13 PM PDT 24
Peak memory 182560 kb
Host smart-03107e0a-e2f2-47c2-aa09-b7ada47ea67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878967214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3878967214
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3364756429
Short name T276
Test name
Test status
Simulation time 320712149455 ps
CPU time 195.41 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:44:45 PM PDT 24
Peak memory 190700 kb
Host smart-753a9df9-b2ab-4cd4-aa4c-0eada50eb2ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364756429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3364756429
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1220733952
Short name T50
Test name
Test status
Simulation time 41228408948 ps
CPU time 57.72 seconds
Started May 16 12:41:05 PM PDT 24
Finished May 16 12:42:06 PM PDT 24
Peak memory 192428 kb
Host smart-2a392a1d-c807-4b1e-8756-313c587a9dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220733952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1220733952
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1425261215
Short name T17
Test name
Test status
Simulation time 40280170 ps
CPU time 0.73 seconds
Started May 16 12:41:32 PM PDT 24
Finished May 16 12:41:39 PM PDT 24
Peak memory 213708 kb
Host smart-10ddcce3-5769-4614-8a62-0fb8c9f8d86e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425261215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1425261215
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4228385903
Short name T435
Test name
Test status
Simulation time 188973108858 ps
CPU time 164.78 seconds
Started May 16 12:41:57 PM PDT 24
Finished May 16 12:44:48 PM PDT 24
Peak memory 182516 kb
Host smart-ba2213ed-0343-4d2b-bfb6-26b1421446a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228385903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4228385903
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.136518035
Short name T377
Test name
Test status
Simulation time 125629377651 ps
CPU time 191.33 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:45:11 PM PDT 24
Peak memory 182508 kb
Host smart-9c9c8834-73cf-45d7-8e2c-b532c377a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136518035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.136518035
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.201805225
Short name T371
Test name
Test status
Simulation time 124365017889 ps
CPU time 187.34 seconds
Started May 16 12:42:04 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 194120 kb
Host smart-d9803f47-de30-4c32-a7f6-ebcbec3a23e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201805225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
201805225
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.1985581874
Short name T40
Test name
Test status
Simulation time 7017188288 ps
CPU time 18.72 seconds
Started May 16 12:41:58 PM PDT 24
Finished May 16 12:42:24 PM PDT 24
Peak memory 197176 kb
Host smart-26da38e2-5f1f-41f4-9e7c-90bf2db6227f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985581874 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.1985581874
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1037779669
Short name T342
Test name
Test status
Simulation time 81064364271 ps
CPU time 146.65 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:44:22 PM PDT 24
Peak memory 182620 kb
Host smart-fd4aa378-c803-47b7-9a70-e13d33f9db79
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037779669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1037779669
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3155046627
Short name T51
Test name
Test status
Simulation time 349692629759 ps
CPU time 133.11 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:44:10 PM PDT 24
Peak memory 182500 kb
Host smart-3df69642-fe97-4bd8-b238-75edee45da82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155046627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3155046627
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1662290606
Short name T7
Test name
Test status
Simulation time 95195150535 ps
CPU time 125.55 seconds
Started May 16 12:41:48 PM PDT 24
Finished May 16 12:44:01 PM PDT 24
Peak memory 194052 kb
Host smart-be076477-2c37-42c1-aacb-3e5688eebb5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662290606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1662290606
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2627908577
Short name T343
Test name
Test status
Simulation time 172799937844 ps
CPU time 92.58 seconds
Started May 16 12:41:56 PM PDT 24
Finished May 16 12:43:36 PM PDT 24
Peak memory 194064 kb
Host smart-689cd816-0629-49a5-b025-33fd3e892b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627908577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2627908577
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3803911164
Short name T449
Test name
Test status
Simulation time 165800635703 ps
CPU time 249.38 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:46:06 PM PDT 24
Peak memory 182596 kb
Host smart-51e1aae4-378a-4585-80c6-64932367e9c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803911164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3803911164
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1370004716
Short name T272
Test name
Test status
Simulation time 117364146675 ps
CPU time 114.88 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:43:54 PM PDT 24
Peak memory 182512 kb
Host smart-9e676e01-a33e-4bf4-9bc6-867fe92f5ce0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370004716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1370004716
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3964183536
Short name T416
Test name
Test status
Simulation time 257555628340 ps
CPU time 75.32 seconds
Started May 16 12:41:58 PM PDT 24
Finished May 16 12:43:20 PM PDT 24
Peak memory 182580 kb
Host smart-03682546-5009-4462-925f-fece14c84aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964183536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3964183536
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1804444238
Short name T126
Test name
Test status
Simulation time 172027914451 ps
CPU time 1530.4 seconds
Started May 16 12:41:58 PM PDT 24
Finished May 16 01:07:35 PM PDT 24
Peak memory 190672 kb
Host smart-37adb46a-4d0c-46b1-a86d-240e340dd1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804444238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1804444238
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1571726075
Short name T424
Test name
Test status
Simulation time 20235463 ps
CPU time 0.59 seconds
Started May 16 12:42:54 PM PDT 24
Finished May 16 12:43:00 PM PDT 24
Peak memory 180564 kb
Host smart-88397dad-578b-44dc-aa8f-e457dd33f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571726075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1571726075
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2053368990
Short name T391
Test name
Test status
Simulation time 901801973842 ps
CPU time 1410.21 seconds
Started May 16 12:41:54 PM PDT 24
Finished May 16 01:05:32 PM PDT 24
Peak memory 190820 kb
Host smart-44bcad64-f3cf-4be6-ac34-55ea1886309e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053368990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2053368990
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2183155281
Short name T393
Test name
Test status
Simulation time 136084414135 ps
CPU time 195.71 seconds
Started May 16 12:41:54 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 182540 kb
Host smart-9a974240-55be-4b54-9e39-2c368c5d51f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183155281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2183155281
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.401360440
Short name T332
Test name
Test status
Simulation time 4814216108 ps
CPU time 8.62 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:42:08 PM PDT 24
Peak memory 182604 kb
Host smart-84b7e3b7-a1ce-4b43-bfff-ba1e35f9b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401360440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.401360440
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.113459351
Short name T176
Test name
Test status
Simulation time 1824819298571 ps
CPU time 1083.8 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 01:00:04 PM PDT 24
Peak memory 190696 kb
Host smart-b4ed39e7-2aae-481c-9ca9-05b7dd186832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113459351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
113459351
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1249824389
Short name T134
Test name
Test status
Simulation time 35954110310 ps
CPU time 20.84 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:42:18 PM PDT 24
Peak memory 182568 kb
Host smart-69a4899a-1f56-4e46-afb1-ce2781f49a5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249824389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1249824389
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2170759000
Short name T372
Test name
Test status
Simulation time 32033787719 ps
CPU time 50.13 seconds
Started May 16 12:41:48 PM PDT 24
Finished May 16 12:42:46 PM PDT 24
Peak memory 182632 kb
Host smart-9bade28e-1bd0-42f8-b903-b2595e1155f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170759000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2170759000
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2263968644
Short name T73
Test name
Test status
Simulation time 68247453010 ps
CPU time 425.64 seconds
Started May 16 12:42:54 PM PDT 24
Finished May 16 12:50:05 PM PDT 24
Peak memory 188996 kb
Host smart-3055929e-28c1-4f98-b843-d8f6dbef494c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263968644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2263968644
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.280868591
Short name T354
Test name
Test status
Simulation time 85156464674 ps
CPU time 87.13 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:43:24 PM PDT 24
Peak memory 193440 kb
Host smart-cb28b990-2947-424c-b0d5-eb79fed1e12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280868591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.280868591
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1318005255
Short name T420
Test name
Test status
Simulation time 82517322000 ps
CPU time 145.73 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:44:24 PM PDT 24
Peak memory 205428 kb
Host smart-7da13e80-0a93-4659-8201-b588b1d83273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318005255 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1318005255
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.630419093
Short name T406
Test name
Test status
Simulation time 184113802138 ps
CPU time 276.54 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:46:34 PM PDT 24
Peak memory 182620 kb
Host smart-286904d7-f4dd-4433-9c16-ca72ffc25078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630419093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.630419093
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1175484736
Short name T419
Test name
Test status
Simulation time 199708695177 ps
CPU time 269.96 seconds
Started May 16 12:41:58 PM PDT 24
Finished May 16 12:46:35 PM PDT 24
Peak memory 182596 kb
Host smart-4c40d9b7-63b7-48b2-b43e-49a4d8c39bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175484736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1175484736
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3442718985
Short name T331
Test name
Test status
Simulation time 1677521745023 ps
CPU time 893.37 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:56:51 PM PDT 24
Peak memory 182616 kb
Host smart-81e2d2fa-499f-4975-a1ee-b9293574e2d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442718985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3442718985
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1803543370
Short name T397
Test name
Test status
Simulation time 360988185672 ps
CPU time 138.64 seconds
Started May 16 12:42:02 PM PDT 24
Finished May 16 12:44:27 PM PDT 24
Peak memory 182612 kb
Host smart-46223bf5-b741-4593-9401-2d27af00a895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803543370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1803543370
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.367844018
Short name T216
Test name
Test status
Simulation time 516293138836 ps
CPU time 781.01 seconds
Started May 16 12:42:07 PM PDT 24
Finished May 16 12:55:13 PM PDT 24
Peak memory 190796 kb
Host smart-ac481ae2-5fd3-4b96-a711-949e9fb73048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367844018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.367844018
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1066092950
Short name T281
Test name
Test status
Simulation time 75897976642 ps
CPU time 121.03 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:43:56 PM PDT 24
Peak memory 190812 kb
Host smart-ed517e8e-52cd-4163-a213-b5a46ca589b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066092950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1066092950
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1460383783
Short name T297
Test name
Test status
Simulation time 137556513498 ps
CPU time 246.75 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:46:05 PM PDT 24
Peak memory 194460 kb
Host smart-5e9285f8-d550-4ddc-a331-602e39b7bb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460383783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1460383783
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3522609734
Short name T438
Test name
Test status
Simulation time 220638972703 ps
CPU time 293.85 seconds
Started May 16 12:41:55 PM PDT 24
Finished May 16 12:46:56 PM PDT 24
Peak memory 182620 kb
Host smart-2c383bd8-3d88-49a5-9e97-4134c02ee1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522609734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3522609734
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.677830882
Short name T243
Test name
Test status
Simulation time 500491988751 ps
CPU time 48.8 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 182580 kb
Host smart-b0e5f7a0-2358-4d50-bed7-e0885836d74a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677830882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.677830882
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3700817749
Short name T321
Test name
Test status
Simulation time 164744039178 ps
CPU time 45.54 seconds
Started May 16 12:41:47 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 190680 kb
Host smart-47c9f363-9ff8-433a-bb29-758ef4a76785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700817749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3700817749
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3652491483
Short name T65
Test name
Test status
Simulation time 18668491 ps
CPU time 0.54 seconds
Started May 16 12:42:03 PM PDT 24
Finished May 16 12:42:10 PM PDT 24
Peak memory 181892 kb
Host smart-d7cf2792-c683-4a97-a9a5-ce3ced61d49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652491483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3652491483
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3326780527
Short name T77
Test name
Test status
Simulation time 434020906490 ps
CPU time 735.89 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:54:15 PM PDT 24
Peak memory 182600 kb
Host smart-b6f9cdb4-6133-47b3-8437-0728aaad8aeb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326780527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3326780527
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4219787202
Short name T430
Test name
Test status
Simulation time 70441463657 ps
CPU time 77.23 seconds
Started May 16 12:41:57 PM PDT 24
Finished May 16 12:43:21 PM PDT 24
Peak memory 182604 kb
Host smart-6b72afdb-8e3a-43ef-964d-f81ff2af9416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219787202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4219787202
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1239224115
Short name T345
Test name
Test status
Simulation time 259418101943 ps
CPU time 55.78 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:42:54 PM PDT 24
Peak memory 182636 kb
Host smart-b9226104-7014-42d9-95a9-fb2d00ce91ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239224115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1239224115
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2424024125
Short name T359
Test name
Test status
Simulation time 338254985 ps
CPU time 1.39 seconds
Started May 16 12:41:53 PM PDT 24
Finished May 16 12:42:03 PM PDT 24
Peak memory 190744 kb
Host smart-81f1698a-bc99-4b8e-b385-e000e4da3cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424024125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2424024125
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2563026178
Short name T262
Test name
Test status
Simulation time 643939130476 ps
CPU time 555.02 seconds
Started May 16 12:41:45 PM PDT 24
Finished May 16 12:51:06 PM PDT 24
Peak memory 196044 kb
Host smart-f7ccc45f-0e7e-4041-b5f8-b6df574c9c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563026178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2563026178
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.3282868815
Short name T35
Test name
Test status
Simulation time 109086795519 ps
CPU time 446.17 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:49:23 PM PDT 24
Peak memory 197140 kb
Host smart-a35ee7d3-988e-422a-90fe-82213407c15a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282868815 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.3282868815
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.754567518
Short name T247
Test name
Test status
Simulation time 213448977752 ps
CPU time 126.28 seconds
Started May 16 12:42:09 PM PDT 24
Finished May 16 12:44:19 PM PDT 24
Peak memory 182596 kb
Host smart-8a6f2db2-6b54-45e5-a3a4-da93f2cf05b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754567518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.754567518
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2809248851
Short name T404
Test name
Test status
Simulation time 130575722915 ps
CPU time 49.94 seconds
Started May 16 12:42:21 PM PDT 24
Finished May 16 12:43:14 PM PDT 24
Peak memory 182452 kb
Host smart-4e4e068b-975c-4eb1-8518-c9e5f6c8312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809248851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2809248851
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.26257772
Short name T220
Test name
Test status
Simulation time 107579010344 ps
CPU time 1273.19 seconds
Started May 16 12:41:58 PM PDT 24
Finished May 16 01:03:18 PM PDT 24
Peak memory 190792 kb
Host smart-474e516c-7fa6-409c-8f10-c1f51dd8372d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26257772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.26257772
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3894395634
Short name T383
Test name
Test status
Simulation time 37892559872 ps
CPU time 15.34 seconds
Started May 16 12:41:53 PM PDT 24
Finished May 16 12:42:17 PM PDT 24
Peak memory 193920 kb
Host smart-2488116a-d861-48a5-bd27-7835e4533b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894395634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3894395634
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2162428034
Short name T443
Test name
Test status
Simulation time 1186026062799 ps
CPU time 432.41 seconds
Started May 16 12:43:02 PM PDT 24
Finished May 16 12:50:20 PM PDT 24
Peak memory 190636 kb
Host smart-3656e004-2cc9-40d0-b669-f6dc0aeb3b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162428034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2162428034
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3460843134
Short name T425
Test name
Test status
Simulation time 458759845882 ps
CPU time 150.9 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:44:00 PM PDT 24
Peak memory 182472 kb
Host smart-1a4da6c4-0648-4284-a2bc-1d284f427f33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460843134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3460843134
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.157579073
Short name T387
Test name
Test status
Simulation time 70090000218 ps
CPU time 29.26 seconds
Started May 16 12:41:16 PM PDT 24
Finished May 16 12:41:48 PM PDT 24
Peak memory 182612 kb
Host smart-0769fc30-e9e4-4c57-9904-68cb268fc0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157579073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.157579073
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.675346883
Short name T160
Test name
Test status
Simulation time 345998003221 ps
CPU time 542.46 seconds
Started May 16 12:41:33 PM PDT 24
Finished May 16 12:50:42 PM PDT 24
Peak memory 190696 kb
Host smart-931e7b00-12c6-4b05-8cba-94c39e0be2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675346883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.675346883
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3763323082
Short name T116
Test name
Test status
Simulation time 93966878652 ps
CPU time 245.76 seconds
Started May 16 12:41:25 PM PDT 24
Finished May 16 12:45:37 PM PDT 24
Peak memory 195036 kb
Host smart-15331ffa-5492-42ee-95d0-04c3fc644df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763323082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3763323082
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.4144602409
Short name T322
Test name
Test status
Simulation time 30199618901 ps
CPU time 47.06 seconds
Started May 16 12:41:59 PM PDT 24
Finished May 16 12:42:52 PM PDT 24
Peak memory 182560 kb
Host smart-cb1ba849-4501-47a0-b821-5e2af31ab87f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144602409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.4144602409
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.185019710
Short name T326
Test name
Test status
Simulation time 19644588558 ps
CPU time 67.36 seconds
Started May 16 12:41:55 PM PDT 24
Finished May 16 12:43:09 PM PDT 24
Peak memory 182504 kb
Host smart-e512b614-ec8f-4414-9d50-2010d365f47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185019710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.185019710
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3591711294
Short name T274
Test name
Test status
Simulation time 17557879694 ps
CPU time 31.4 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:42:31 PM PDT 24
Peak memory 190744 kb
Host smart-77d171f5-ec98-4d46-8c3c-b67622a749d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591711294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3591711294
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.331748916
Short name T203
Test name
Test status
Simulation time 161596513011 ps
CPU time 274.18 seconds
Started May 16 12:42:02 PM PDT 24
Finished May 16 12:46:42 PM PDT 24
Peak memory 190696 kb
Host smart-f1b024e7-51b6-41b9-a1d2-e93281c3f8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331748916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.331748916
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.522372567
Short name T122
Test name
Test status
Simulation time 53672629099 ps
CPU time 79.89 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:43:17 PM PDT 24
Peak memory 190672 kb
Host smart-64f14290-7040-421e-a16f-d335ebdf6ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522372567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.522372567
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1326742821
Short name T445
Test name
Test status
Simulation time 1197224423 ps
CPU time 2.33 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:42:00 PM PDT 24
Peak memory 182388 kb
Host smart-5872710a-025a-4546-bdd2-b990a2a2b6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326742821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1326742821
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1035545508
Short name T352
Test name
Test status
Simulation time 126661428908 ps
CPU time 201.41 seconds
Started May 16 12:41:37 PM PDT 24
Finished May 16 12:45:05 PM PDT 24
Peak memory 182588 kb
Host smart-625560ba-93aa-4d1e-bff1-eeac07ddaebd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035545508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1035545508
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.413649278
Short name T78
Test name
Test status
Simulation time 502287278548 ps
CPU time 147.56 seconds
Started May 16 12:41:23 PM PDT 24
Finished May 16 12:43:56 PM PDT 24
Peak memory 182596 kb
Host smart-10138482-bbd3-4992-adc0-0054198aab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413649278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.413649278
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2071721594
Short name T325
Test name
Test status
Simulation time 42724340356 ps
CPU time 23.55 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:41:53 PM PDT 24
Peak memory 182596 kb
Host smart-9db65cac-c2b7-4c68-9926-cfb4c4ca344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071721594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2071721594
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.512576789
Short name T58
Test name
Test status
Simulation time 675928358174 ps
CPU time 294.09 seconds
Started May 16 12:41:10 PM PDT 24
Finished May 16 12:46:07 PM PDT 24
Peak memory 190804 kb
Host smart-8bdc644b-358c-48e2-a290-0c3a4d55f232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512576789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.512576789
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.3562659724
Short name T128
Test name
Test status
Simulation time 129512422928 ps
CPU time 196.59 seconds
Started May 16 12:43:01 PM PDT 24
Finished May 16 12:46:23 PM PDT 24
Peak memory 190492 kb
Host smart-e1d5c8b4-1705-4d03-839c-2e64c052bf64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562659724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3562659724
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2384729622
Short name T249
Test name
Test status
Simulation time 288058440194 ps
CPU time 435.35 seconds
Started May 16 12:42:06 PM PDT 24
Finished May 16 12:49:27 PM PDT 24
Peak memory 182572 kb
Host smart-0e889cc9-7c2f-46d0-b394-bc7e5912fc9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384729622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2384729622
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1660477161
Short name T292
Test name
Test status
Simulation time 56951351818 ps
CPU time 53.52 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:42:52 PM PDT 24
Peak memory 182488 kb
Host smart-152a3c12-929f-4828-86bc-6366d65e48e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660477161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1660477161
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1909667020
Short name T229
Test name
Test status
Simulation time 93703074284 ps
CPU time 462.62 seconds
Started May 16 12:42:07 PM PDT 24
Finished May 16 12:49:55 PM PDT 24
Peak memory 190784 kb
Host smart-92b9aeca-0e37-4c8d-8716-dc65fa4e298a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909667020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1909667020
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1315107470
Short name T312
Test name
Test status
Simulation time 98237170840 ps
CPU time 144.67 seconds
Started May 16 12:41:59 PM PDT 24
Finished May 16 12:44:31 PM PDT 24
Peak memory 190764 kb
Host smart-82aa8f15-7204-460c-8c80-fb2df7429889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315107470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1315107470
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.724208518
Short name T118
Test name
Test status
Simulation time 343114276385 ps
CPU time 165.73 seconds
Started May 16 12:42:04 PM PDT 24
Finished May 16 12:44:56 PM PDT 24
Peak memory 190796 kb
Host smart-d241d433-17a5-4195-ade3-e54f0d26b1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724208518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.724208518
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3223562354
Short name T256
Test name
Test status
Simulation time 67353028143 ps
CPU time 135.9 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:44:15 PM PDT 24
Peak memory 190796 kb
Host smart-eaa57c8b-95fb-4fe9-abfe-1ac59637ecf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223562354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3223562354
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3279235156
Short name T439
Test name
Test status
Simulation time 753720001730 ps
CPU time 174.72 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:44:53 PM PDT 24
Peak memory 190688 kb
Host smart-7a460a59-9836-4d03-9b5c-a64a0a9c7086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279235156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3279235156
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3774627609
Short name T201
Test name
Test status
Simulation time 1309125159300 ps
CPU time 678.2 seconds
Started May 16 12:41:18 PM PDT 24
Finished May 16 12:52:39 PM PDT 24
Peak memory 182560 kb
Host smart-93180d65-ebc9-40bd-8084-5e6d4dc45c13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774627609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3774627609
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1125437643
Short name T398
Test name
Test status
Simulation time 521214208946 ps
CPU time 184.86 seconds
Started May 16 12:41:33 PM PDT 24
Finished May 16 12:44:44 PM PDT 24
Peak memory 182572 kb
Host smart-62fe3e0f-6b36-4f41-9817-e5aeed34ae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125437643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1125437643
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.22905658
Short name T450
Test name
Test status
Simulation time 208308377750 ps
CPU time 126.14 seconds
Started May 16 12:41:34 PM PDT 24
Finished May 16 12:43:47 PM PDT 24
Peak memory 190700 kb
Host smart-ba45b8d3-86c7-4581-8238-0f10c71ef6dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22905658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.22905658
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3089625613
Short name T360
Test name
Test status
Simulation time 433442592 ps
CPU time 0.96 seconds
Started May 16 12:41:17 PM PDT 24
Finished May 16 12:41:20 PM PDT 24
Peak memory 191092 kb
Host smart-ce014f98-19ec-41f1-97c1-7907b397b453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089625613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3089625613
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.496438385
Short name T341
Test name
Test status
Simulation time 518388301216 ps
CPU time 664.38 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:52:30 PM PDT 24
Peak memory 190328 kb
Host smart-f23934b0-bd39-4d14-823b-f6a6541306c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496438385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.496438385
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.2031592509
Short name T251
Test name
Test status
Simulation time 71910438171 ps
CPU time 161.11 seconds
Started May 16 12:42:54 PM PDT 24
Finished May 16 12:45:41 PM PDT 24
Peak memory 189176 kb
Host smart-91913e59-8b5f-4ec4-9570-6927bc3293eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031592509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2031592509
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2945362982
Short name T246
Test name
Test status
Simulation time 692634269520 ps
CPU time 388.91 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:48:27 PM PDT 24
Peak memory 190768 kb
Host smart-a925b613-e96f-4cfe-abd5-1785764ae083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945362982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2945362982
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.913675279
Short name T303
Test name
Test status
Simulation time 471897631829 ps
CPU time 318.46 seconds
Started May 16 12:43:02 PM PDT 24
Finished May 16 12:48:26 PM PDT 24
Peak memory 190620 kb
Host smart-e351ce0d-c791-4fdc-a000-e1b5b490f7af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913675279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.913675279
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3889295878
Short name T24
Test name
Test status
Simulation time 992150269645 ps
CPU time 1027.31 seconds
Started May 16 12:41:50 PM PDT 24
Finished May 16 12:59:05 PM PDT 24
Peak memory 190768 kb
Host smart-e6256fd7-d67f-4963-8ad5-1d8aeafdc6e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889295878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3889295878
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1190126491
Short name T279
Test name
Test status
Simulation time 58972553749 ps
CPU time 836.66 seconds
Started May 16 12:41:49 PM PDT 24
Finished May 16 12:55:53 PM PDT 24
Peak memory 190784 kb
Host smart-70cb95b4-641a-440d-8b6e-f0649c9e6365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190126491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1190126491
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2612766511
Short name T137
Test name
Test status
Simulation time 186602448771 ps
CPU time 266.46 seconds
Started May 16 12:42:08 PM PDT 24
Finished May 16 12:46:39 PM PDT 24
Peak memory 190664 kb
Host smart-8d43c689-8a00-435f-a0de-e0657aee42bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612766511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2612766511
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.494290416
Short name T255
Test name
Test status
Simulation time 18843819314 ps
CPU time 19.65 seconds
Started May 16 12:41:54 PM PDT 24
Finished May 16 12:42:21 PM PDT 24
Peak memory 182496 kb
Host smart-85d2479b-9def-4143-b448-87e10b8771ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494290416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.494290416
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3604093199
Short name T330
Test name
Test status
Simulation time 377196662633 ps
CPU time 252.62 seconds
Started May 16 12:42:08 PM PDT 24
Finished May 16 12:46:25 PM PDT 24
Peak memory 190736 kb
Host smart-a74d6c8a-481a-4ae9-953a-4b83d7bf178b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604093199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3604093199
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2678722289
Short name T41
Test name
Test status
Simulation time 1036077022476 ps
CPU time 243.66 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:45:26 PM PDT 24
Peak memory 182560 kb
Host smart-4923116c-f46c-4a2b-b457-5ba25862281f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678722289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2678722289
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_random.3587156636
Short name T278
Test name
Test status
Simulation time 30516100266 ps
CPU time 67.14 seconds
Started May 16 12:41:21 PM PDT 24
Finished May 16 12:42:34 PM PDT 24
Peak memory 182600 kb
Host smart-54375c14-db69-4636-b809-3e09429899e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587156636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3587156636
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3848188082
Short name T444
Test name
Test status
Simulation time 188825001944 ps
CPU time 85.82 seconds
Started May 16 12:41:24 PM PDT 24
Finished May 16 12:42:56 PM PDT 24
Peak memory 190768 kb
Host smart-61da8b70-2421-4f76-9fa0-9b0b1d9b2d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848188082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3848188082
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2018160098
Short name T3
Test name
Test status
Simulation time 468219362147 ps
CPU time 492.13 seconds
Started May 16 12:41:28 PM PDT 24
Finished May 16 12:49:47 PM PDT 24
Peak memory 190792 kb
Host smart-f997a5b6-b39f-43d6-b7b1-1aa2c8df7c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018160098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2018160098
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/83.rv_timer_random.2799790889
Short name T25
Test name
Test status
Simulation time 115950462155 ps
CPU time 248.89 seconds
Started May 16 12:42:02 PM PDT 24
Finished May 16 12:46:17 PM PDT 24
Peak memory 190700 kb
Host smart-3d5cf7f3-29cc-412d-81e5-09b7b24e48ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799790889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2799790889
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.657218783
Short name T189
Test name
Test status
Simulation time 374731950900 ps
CPU time 1804.43 seconds
Started May 16 12:42:00 PM PDT 24
Finished May 16 01:12:11 PM PDT 24
Peak memory 190768 kb
Host smart-d5b02c19-f19b-482e-8351-76e3a5b2a45c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657218783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.657218783
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.900254859
Short name T6
Test name
Test status
Simulation time 62586941252 ps
CPU time 464.04 seconds
Started May 16 12:42:08 PM PDT 24
Finished May 16 12:49:56 PM PDT 24
Peak memory 190792 kb
Host smart-8ea49200-b96c-461d-b7ec-349a1902be33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900254859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.900254859
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2802908562
Short name T290
Test name
Test status
Simulation time 11808766911 ps
CPU time 6.16 seconds
Started May 16 12:42:05 PM PDT 24
Finished May 16 12:42:17 PM PDT 24
Peak memory 182508 kb
Host smart-df2e494b-db67-429e-8b6d-dba7815c29be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802908562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2802908562
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1851676882
Short name T215
Test name
Test status
Simulation time 83036435470 ps
CPU time 185.73 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 12:45:06 PM PDT 24
Peak memory 190792 kb
Host smart-1175c01b-0ec9-4b26-a0b8-ea413d870ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851676882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1851676882
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3884175870
Short name T261
Test name
Test status
Simulation time 111833514557 ps
CPU time 60.42 seconds
Started May 16 12:41:19 PM PDT 24
Finished May 16 12:42:23 PM PDT 24
Peak memory 182560 kb
Host smart-188ec276-2961-48ad-8d9d-68255ea29ced
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884175870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3884175870
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3907039305
Short name T362
Test name
Test status
Simulation time 93180730405 ps
CPU time 39.25 seconds
Started May 16 12:41:30 PM PDT 24
Finished May 16 12:42:15 PM PDT 24
Peak memory 182564 kb
Host smart-f8b02bdd-c720-43c5-872c-a93c94578d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907039305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3907039305
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2978231736
Short name T8
Test name
Test status
Simulation time 25094302138 ps
CPU time 42.18 seconds
Started May 16 12:41:20 PM PDT 24
Finished May 16 12:42:06 PM PDT 24
Peak memory 182592 kb
Host smart-6e641af8-d6cf-4030-b4b5-6985b4ef3774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978231736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2978231736
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3152839047
Short name T429
Test name
Test status
Simulation time 100742026337 ps
CPU time 120.04 seconds
Started May 16 12:41:32 PM PDT 24
Finished May 16 12:43:38 PM PDT 24
Peak memory 182612 kb
Host smart-b2965962-4a21-4ae7-b63b-1a44c8d2ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152839047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3152839047
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.436610548
Short name T37
Test name
Test status
Simulation time 43705453724 ps
CPU time 54.02 seconds
Started May 16 12:41:29 PM PDT 24
Finished May 16 12:42:30 PM PDT 24
Peak memory 197264 kb
Host smart-b0a45bed-d39b-4971-bb76-9d8419441eaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436610548 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.436610548
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.481721685
Short name T74
Test name
Test status
Simulation time 234632276610 ps
CPU time 812.62 seconds
Started May 16 12:42:02 PM PDT 24
Finished May 16 12:55:41 PM PDT 24
Peak memory 190792 kb
Host smart-d192c408-273d-4923-a8ed-8ec15d483651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481721685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.481721685
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3702109026
Short name T53
Test name
Test status
Simulation time 14794978106 ps
CPU time 18.67 seconds
Started May 16 12:42:06 PM PDT 24
Finished May 16 12:42:30 PM PDT 24
Peak memory 182532 kb
Host smart-f632afe3-7382-40c9-8e3b-8f8db6c68db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702109026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3702109026
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.441057073
Short name T233
Test name
Test status
Simulation time 538181305885 ps
CPU time 1798.21 seconds
Started May 16 12:42:09 PM PDT 24
Finished May 16 01:12:11 PM PDT 24
Peak memory 190692 kb
Host smart-561e0f92-d496-40d0-99e9-a6424984f8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441057073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.441057073
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3418376883
Short name T193
Test name
Test status
Simulation time 102183995486 ps
CPU time 710.24 seconds
Started May 16 12:42:03 PM PDT 24
Finished May 16 12:54:00 PM PDT 24
Peak memory 190632 kb
Host smart-7426c113-ec3a-4946-9c9a-6f76be0bfc14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418376883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3418376883
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1770865721
Short name T212
Test name
Test status
Simulation time 201529253412 ps
CPU time 1137.65 seconds
Started May 16 12:41:52 PM PDT 24
Finished May 16 01:00:58 PM PDT 24
Peak memory 190676 kb
Host smart-1252abd5-5088-4f25-b6b4-ed0ad4b91d98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770865721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1770865721
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.183235042
Short name T199
Test name
Test status
Simulation time 38436358083 ps
CPU time 1343.53 seconds
Started May 16 12:42:06 PM PDT 24
Finished May 16 01:04:35 PM PDT 24
Peak memory 182532 kb
Host smart-a07e9ac8-97b6-4fdf-89ee-b86b05bbc2da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183235042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.183235042
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3756702126
Short name T136
Test name
Test status
Simulation time 61281878129 ps
CPU time 232.69 seconds
Started May 16 12:41:54 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 193960 kb
Host smart-2606732f-f19f-4441-9975-7256adb7d34b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756702126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3756702126
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1755624658
Short name T336
Test name
Test status
Simulation time 127979706225 ps
CPU time 70.8 seconds
Started May 16 12:41:51 PM PDT 24
Finished May 16 12:43:10 PM PDT 24
Peak memory 190668 kb
Host smart-e61e02fd-7be9-4da5-bec2-c466aca13432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755624658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1755624658
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2677320373
Short name T318
Test name
Test status
Simulation time 153940954245 ps
CPU time 393.82 seconds
Started May 16 12:41:57 PM PDT 24
Finished May 16 12:48:38 PM PDT 24
Peak memory 190688 kb
Host smart-279ebba0-4ee3-49bb-be8a-cb9142549894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677320373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2677320373
Directory /workspace/99.rv_timer_random/latest
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