Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
133162468 |
1 |
|
T1 |
151147 |
|
T2 |
362319 |
|
T3 |
23 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
76167833 |
1 |
|
T1 |
140031 |
|
T2 |
6 |
|
T3 |
23 |
auto[1] |
56994635 |
1 |
|
T1 |
11116 |
|
T2 |
362313 |
|
T5 |
860 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
133156757 |
1 |
|
T1 |
151141 |
|
T2 |
362315 |
|
T3 |
15 |
auto[1] |
5711 |
1 |
|
T1 |
6 |
|
T2 |
4 |
|
T3 |
8 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
76164803 |
1 |
|
T1 |
140029 |
|
T2 |
6 |
|
T3 |
15 |
all_values[0] |
auto[0] |
auto[1] |
3030 |
1 |
|
T1 |
2 |
|
T3 |
8 |
|
T4 |
4 |
all_values[0] |
auto[1] |
auto[0] |
56991954 |
1 |
|
T1 |
11112 |
|
T2 |
362309 |
|
T5 |
857 |
all_values[0] |
auto[1] |
auto[1] |
2681 |
1 |
|
T1 |
4 |
|
T2 |
4 |
|
T5 |
3 |