Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
1183 |
1 |
|
T3 |
4 |
|
T11 |
18 |
|
T34 |
10 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
636 |
1 |
|
T3 |
4 |
|
T11 |
6 |
|
T34 |
5 |
auto[1] |
547 |
1 |
|
T11 |
12 |
|
T34 |
5 |
|
T23 |
6 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
442 |
1 |
|
T3 |
1 |
|
T11 |
8 |
|
T23 |
10 |
auto[1] |
741 |
1 |
|
T3 |
3 |
|
T11 |
10 |
|
T34 |
10 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
689 |
1 |
|
T3 |
2 |
|
T11 |
13 |
|
T34 |
3 |
auto[1] |
494 |
1 |
|
T3 |
2 |
|
T11 |
5 |
|
T34 |
7 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
235 |
1 |
|
T3 |
1 |
|
T11 |
3 |
|
T23 |
7 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
128 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T34 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
207 |
1 |
|
T11 |
5 |
|
T23 |
3 |
|
T25 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
119 |
1 |
|
T11 |
4 |
|
T34 |
2 |
|
T23 |
1 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
273 |
1 |
|
T3 |
2 |
|
T11 |
2 |
|
T34 |
4 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
221 |
1 |
|
T11 |
3 |
|
T34 |
3 |
|
T23 |
2 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |